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13 #ifndef LLVM_CODEGEN_MACHINEREGISTERINFO_H
14 #define LLVM_CODEGEN_MACHINEREGISTERINFO_H
53 virtual void anchor();
66 const bool TracksSubRegLiveness;
85 bool IsUpdatedCSRsInitialized =
false;
104 std::unique_ptr<MachineOperand *[]> PhysRegUseDefLists;
111 return PhysRegUseDefLists[RegNo.
id()];
117 return PhysRegUseDefLists[RegNo.
id()];
121 static MachineOperand *getNextOperandForReg(
const MachineOperand *MO) {
122 assert(MO && MO->isReg() &&
"This is not a register operand!");
123 return MO->Contents.Reg.Next;
128 BitVector UsedPhysRegMask;
134 BitVector ReservedRegs;
136 using VRegToTypeMap = IndexedMap<LLT, VirtReg2IndexFunctor>;
138 VRegToTypeMap VRegToType;
144 std::vector<std::pair<MCRegister, Register>> LiveIns;
159 assert(TheDelegate == delegate &&
160 "Only the current delegate can perform reset!");
161 TheDelegate =
nullptr;
165 assert(delegate && !TheDelegate &&
166 "Attempted to set delegate to null, or to change it without "
167 "first resetting it!");
169 TheDelegate = delegate;
220 return TracksSubRegLiveness;
272 template<
bool Uses,
bool Defs,
bool SkipDebug,
273 bool ByOperand,
bool ByInstr,
bool ByBundle>
275 template<
bool Uses,
bool Defs,
bool SkipDebug,
276 bool ByOperand,
bool ByInstr,
bool ByBundle>
280 template<
bool,
bool,
bool,
bool,
bool,
bool>
282 template<
bool,
bool,
bool,
bool,
bool,
bool>
442 "Named VRegs Must be Unique.");
644 "Register class not set, wrong accessor");
704 unsigned MinNumRegs = 0);
718 unsigned MinNumRegs = 0);
742 return VRegToType[
Reg];
775 RegAllocHints[VReg].first =
Type;
776 RegAllocHints[VReg].second.
clear();
777 RegAllocHints[VReg].second.push_back(PrefReg);
784 RegAllocHints[VReg].second.push_back(PrefReg);
794 assert (!RegAllocHints[VReg].first &&
795 "Expected to clear a non-target hint!");
796 RegAllocHints[VReg].second.
clear();
802 std::pair<Register, Register>
806 RegAllocHints[VReg.
id()].second[0] :
Register());
807 return std::pair<Register, Register>(RegAllocHints[VReg.
id()].first,
816 return Hint.first ?
Register() : Hint.second;
821 const std::pair<Register, SmallVector<Register, 4>>
824 return RegAllocHints[VReg];
847 if (
MI->isDebugValue()) {
848 for (
auto &
Op :
MI->debug_operands())
850 assert(
MI->hasDebugOperandForReg(NewReg) &&
851 "Expected debug value to have some overlap with OldReg");
852 }
else if (
MI->isDebugPHI()) {
853 UpdateOp(
MI->getOperand(0));
877 UsedPhysRegMask.setBitsNotInMask(RegMask);
901 return !ReservedRegs.empty();
916 "Reserved registers haven't been frozen yet. "
917 "Use TRI::getReservedRegs().");
955 LiveIns.push_back(std::make_pair(
Reg, vreg));
996 template <
bool ReturnUses,
bool ReturnDefs,
bool SkipDebug,
bool ByOperand,
997 bool ByInstr,
bool ByBundle>
1015 if ((!ReturnUses &&
op->isUse()) ||
1016 (!ReturnDefs &&
op->isDef()) ||
1017 (SkipDebug &&
op->isDebug()))
1023 assert(
Op &&
"Cannot increment end iterator!");
1024 Op = getNextOperandForReg(
Op);
1032 assert(!
Op->isDebug() &&
"Can't have debug defs");
1036 while (
Op && ((!ReturnDefs &&
Op->isDef()) ||
1037 (SkipDebug &&
Op->isDebug())))
1038 Op = getNextOperandForReg(
Op);
1057 assert(
Op &&
"Cannot increment end iterator!");
1064 }
while (
Op &&
Op->getParent() ==
P);
1065 }
else if (ByBundle) {
1082 assert(
Op &&
"Cannot dereference end iterator!");
1083 return Op - &
Op->getParent()->getOperand(0);
1088 assert(
Op &&
"Cannot dereference end iterator!");
1093 assert(
Op &&
"Cannot dereference end iterator!");
1104 template <
bool ReturnUses,
bool ReturnDefs,
bool SkipDebug,
bool ByOperand,
1105 bool ByInstr,
bool ByBundle>
1123 if ((!ReturnUses &&
op->isUse()) ||
1124 (!ReturnDefs &&
op->isDef()) ||
1125 (SkipDebug &&
op->isDebug()))
1131 assert(
Op &&
"Cannot increment end iterator!");
1132 Op = getNextOperandForReg(
Op);
1140 assert(!
Op->isDebug() &&
"Can't have debug defs");
1144 while (
Op && ((!ReturnDefs &&
Op->isDef()) ||
1145 (SkipDebug &&
Op->isDebug())))
1146 Op = getNextOperandForReg(
Op);
1165 assert(
Op &&
"Cannot increment end iterator!");
1172 }
while (
Op &&
Op->getParent() ==
P);
1173 }
else if (ByBundle) {
1189 assert(
Op &&
"Cannot dereference end iterator!");
1192 return *
Op->getParent();
1203 const int *PSet =
nullptr;
1204 unsigned Weight = 0;
1213 PSet =
TRI->getRegClassPressureSets(RC);
1214 Weight =
TRI->getRegClassWeight(RC).RegWeight;
1216 PSet =
TRI->getRegUnitPressureSets(RegUnit);
1217 Weight =
TRI->getRegUnitWeight(RegUnit);
1244 #endif // LLVM_CODEGEN_MACHINEREGISTERINFO_H
void addLiveIn(MCRegister Reg, Register vreg=Register())
addLiveIn - Add the specified register as a live-in.
static def_instr_iterator def_instr_end()
void markUsesInDebugValueAsUndef(Register Reg) const
markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the specified register as undefined wh...
bool hasProperty(Property P) const
def_iterator def_begin(Register RegNo) const
This is an optimization pass for GlobalISel generic memory operations.
bool subRegLivenessEnabled() const
defusechain_instr_iterator operator++(int)
bool isPhysRegUsed(MCRegister PhysReg, bool SkipRegMaskTest=false) const
Return true if the specified register is modified or read in this function.
static use_instr_nodbg_iterator use_instr_nodbg_end()
bool constrainRegAttrs(Register Reg, Register ConstrainingReg, unsigned MinNumRegs=0)
Constrain the register class or the register bank of the virtual register Reg (and low-level type) to...
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
bool shouldTrackSubRegLiveness(const TargetRegisterClass &RC) const
Returns true if liveness for register class RC should be tracked at the subregister level.
Register createIncompleteVirtualRegister(StringRef Name="")
Creates a new virtual register that has no register class, register bank or size assigned yet.
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
StringRef getVRegName(Register Reg) const
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
std::forward_iterator_tag iterator_category
bool operator==(const defusechain_iterator &x) const
bool recomputeRegClass(Register Reg)
recomputeRegClass - Try to find a legal super-class of Reg's register class that still satisfies the ...
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
def_bundle_iterator def_bundle_begin(Register RegNo) const
void disableCalleeSavedRegister(MCRegister Reg)
Disables the register from the list of CSRs.
iterator_range< reg_bundle_nodbg_iterator > reg_nodbg_bundles(Register Reg) const
def_instr_iterator def_instr_begin(Register RegNo) const
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
bool isInAllocatableClass(MCRegister RegNo) const
Return true if the register is in the allocation of any register class.
bool livein_empty() const
Reg
All possible values of the reg field in the ModR/M byte.
const TargetRegisterInfo * getTargetRegisterInfo() const
MachineInstr & operator*() const
MachineInstr * getUniqueVRegDef(Register Reg) const
getUniqueVRegDef - Return the unique machine instr that defines the specified virtual register or nul...
defusechain_iterator - This class provides iterator support for machine operands in the function that...
bool canReserveReg(MCRegister PhysReg) const
canReserveReg - Returns true if PhysReg can be used as a reserved register.
use_instr_nodbg_iterator use_instr_nodbg_begin(Register RegNo) const
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
iterator_range< use_instr_nodbg_iterator > use_nodbg_instructions(Register Reg) const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
bool operator==(const defusechain_instr_iterator &x) const
The instances of the Type class are immutable: once they are created, they are never changed.
iterator_range< use_instr_iterator > use_instructions(Register Reg) const
bool operator!=(const defusechain_instr_iterator &x) const
reg_nodbg_iterator reg_nodbg_begin(Register RegNo) const
Register getLiveInVirtReg(MCRegister PReg) const
getLiveInVirtReg - If PReg is a live-in physical register, return the corresponding live-in virtual r...
iterator_range< use_iterator > use_operands(Register Reg) const
unsigned getNumVirtRegs() const
getNumVirtRegs - Return the number of virtual registers created.
static reg_iterator reg_end()
reg_instr_iterator reg_instr_begin(Register RegNo) const
MachineOperand * operator->() const
std::pair< typename Base::iterator, bool > insert(StringRef key)
use_bundle_iterator use_bundle_begin(Register RegNo) const
friend class defusechain_iterator
iterator find(StringRef Key)
alloca< 16 x float >, align 16 %tmp2=alloca< 16 x float >, align 16 store< 16 x float > %A,< 16 x float > *%tmp %s=bitcast< 16 x float > *%tmp to i8 *%s2=bitcast< 16 x float > *%tmp2 to i8 *call void @llvm.memcpy.i64(i8 *%s, i8 *%s2, i64 64, i32 16) %R=load< 16 x float > *%tmp2 ret< 16 x float > %R } declare void @llvm.memcpy.i64(i8 *nocapture, i8 *nocapture, i64, i32) nounwind which compiles to:_foo:subl $140, %esp movaps %xmm3, 112(%esp) movaps %xmm2, 96(%esp) movaps %xmm1, 80(%esp) movaps %xmm0, 64(%esp) movl 60(%esp), %eax movl %eax, 124(%esp) movl 56(%esp), %eax movl %eax, 120(%esp) movl 52(%esp), %eax< many many more 32-bit copies > movaps(%esp), %xmm0 movaps 16(%esp), %xmm1 movaps 32(%esp), %xmm2 movaps 48(%esp), %xmm3 addl $140, %esp ret On Nehalem, it may even be cheaper to just use movups when unaligned than to fall back to lower-granularity chunks. Implement processor-specific optimizations for parity with GCC on these processors. GCC does two optimizations:1. ix86_pad_returns inserts a noop before ret instructions if immediately preceded by a conditional branch or is the target of a jump. 2. ix86_avoid_jump_misspredicts inserts noops in cases where a 16-byte block of code contains more than 3 branches. The first one is done for all AMDs, Core2, and "Generic" The second one is done for:Atom, Pentium Pro, all AMDs, Pentium 4, Nocona, Core 2, and "Generic" Testcase:int x(int a) { return(a &0xf0)> >4 tmp
unsigned const TargetRegisterInfo * TRI
void setDelegate(Delegate *delegate)
unsigned getOperandNo() const
getOperandNo - Return the operand # of this MachineOperand in its MachineInstr.
use_nodbg_iterator use_nodbg_begin(Register RegNo) const
MachineInstr * operator->() const
SmallPtrSet< MachineInstr *, 2 > Uses
defusechain_instr_iterator< true, true, false, false, false, true > reg_bundle_iterator
reg_bundle_iterator/reg_bundle_begin/reg_bundle_end - Walk all defs and uses of the specified registe...
bool tracksLiveness() const
tracksLiveness - Returns true when tracking register liveness accurately.
Iterate over the pressure sets affected by the given physical or virtual register.
iterator_range< reg_instr_nodbg_iterator > reg_nodbg_instructions(Register Reg) const
bool atEnd() const
atEnd - return true if this iterator is equal to reg_end() on the value.
TargetInstrInfo - Interface to description of machine instruction set.
iterator_range< use_nodbg_iterator > use_nodbg_operands(Register Reg) const
PointerUnion< const TargetRegisterClass *, const RegisterBank * > RegClassOrRegBank
Convenient type to represent either a register class or a register bank.
This class implements the register bank concept.
void setRegClassOrRegBank(Register Reg, const RegClassOrRegBank &RCOrRB)
void setType(Register VReg, LLT Ty)
Set the low-level type of VReg to Ty.
virtual void MRI_NoteNewVirtualRegister(Register Reg)=0
reg_bundle_iterator reg_bundle_begin(Register RegNo) const
StorageT::size_type size() const
defusechain_iterator< true, true, true, true, false, false > reg_nodbg_iterator
reg_nodbg_iterator/reg_nodbg_begin/reg_nodbg_end - Walk all defs and uses of the specified register,...
bool isUpdatedCSRsInitialized() const
Returns true if the updated CSR list was initialized and false otherwise.
bool isReserved(MCRegister PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.
const MachineFunctionProperties & getProperties() const
Get the function properties.
iterator_range< reg_nodbg_iterator > reg_nodbg_operands(Register Reg) const
std::ptrdiff_t difference_type
void insertVRegByName(StringRef Name, Register Reg)
static reg_instr_nodbg_iterator reg_instr_nodbg_end()
const HexagonInstrInfo * TII
defusechain_iterator< true, true, false, true, false, false > reg_iterator
reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specified register.
bool atEnd() const
atEnd - return true if this iterator is equal to reg_end() on the value.
MachineOperand class - Representation of each machine instruction operand.
iterator_range< reg_instr_iterator > reg_instructions(Register Reg) const
void setCalleeSavedRegs(ArrayRef< MCPhysReg > CSRs)
Sets the updated Callee Saved Registers list.
unsigned getWeight() const
defusechain_iterator< true, false, false, true, false, false > use_iterator
use_iterator/use_begin/use_end - Walk all uses of the specified register.
MachineOperand & operator*() const
defusechain_iterator< false, true, false, true, false, false > def_iterator
def_iterator/def_begin/def_end - Walk all defs of the specified register.
static use_nodbg_iterator use_nodbg_end()
void freezeReservedRegs(const MachineFunction &)
freezeReservedRegs - Called by the register allocator to freeze the set of reserved registers before ...
MachineRegisterInfo & operator=(const MachineRegisterInfo &)=delete
livein_iterator livein_begin() const
void clearVirtRegTypes()
Remove all types associated to virtual registers (after instruction selection and constraining of all...
Promote Memory to Register
bool reservedRegsFrozen() const
reservedRegsFrozen - Returns true after freezeReservedRegs() was called to ensure the set of reserved...
MachineInstr * getVRegDef(Register Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
iterator_range< use_bundle_iterator > use_bundles(Register Reg) const
bool use_empty(Register RegNo) const
use_empty - Return true if there are no instructions using the specified register.
static reg_instr_iterator reg_instr_end()
static reg_nodbg_iterator reg_nodbg_end()
defusechain_instr_iterator()=default
bool def_empty(Register RegNo) const
def_empty - Return true if there are no instructions defining the specified register (it may be live-...
defusechain_instr_iterator< true, true, false, false, true, false > reg_instr_iterator
reg_instr_iterator/reg_instr_begin/reg_instr_end - Walk all defs and uses of the specified register,...
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
friend class defusechain_instr_iterator
bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
void clearKillFlags(Register Reg) const
clearKillFlags - Iterate over all the uses of the given register and clear the kill flag from the Mac...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
defusechain_instr_iterator & operator++()
void verifyUseList(Register Reg) const
Verify the sanity of the use list for Reg.
iterator_range< reg_bundle_iterator > reg_bundles(Register Reg) const
bool regsOverlap(Register RegA, Register RegB) const
Returns true if the two registers are equal or alias each other.
static reg_bundle_iterator reg_bundle_end()
Representation of each machine instruction.
void setRegBank(Register Reg, const RegisterBank &RegBank)
Set the register bank to RegBank for Reg.
defusechain_iterator< true, false, true, true, false, false > use_nodbg_iterator
use_nodbg_iterator/use_nodbg_begin/use_nodbg_end - Walk all uses of the specified register,...
use_instr_iterator use_instr_begin(Register RegNo) const
static def_bundle_iterator def_bundle_end()
T dyn_cast() const
Returns the current pointer if it is of the specified pointer type, otherwise returns null.
defusechain_instr_iterator< false, true, false, false, true, false > def_instr_iterator
def_instr_iterator/def_instr_begin/def_instr_end - Walk all defs of the specified register,...
iterator_range< def_bundle_iterator > def_bundles(Register Reg) const
const MCPhysReg * getCalleeSavedRegs() const
Returns list of callee saved registers.
iterator_range< def_instr_iterator > def_instructions(Register Reg) const
reg_instr_nodbg_iterator reg_instr_nodbg_begin(Register RegNo) const
const bool HasDisjunctSubRegs
Whether the class supports two (or more) disjunct subregister indices.
MCRegister getLiveInPhysReg(Register VReg) const
getLiveInPhysReg - If VReg is a live-in virtual register, return the corresponding live-in physical r...
ArrayRef< std::pair< MCRegister, Register > > liveins() const
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
const TargetRegisterClass * getRegClassOrNull(Register Reg) const
Return the register class of Reg, or null if Reg has not been assigned a register class yet.
iterator_range< reg_iterator > reg_operands(Register Reg) const
bool isAllocatable(MCRegister PhysReg) const
isAllocatable - Returns true when PhysReg belongs to an allocatable register class and it hasn't been...
void setSimpleHint(Register VReg, Register PrefReg)
Specify the preferred (target independent) register allocation hint for the specified virtual registe...
MachineOperand * getOneDef(Register Reg) const
Returns the defining operand if there is exactly one operand defining the specified register,...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool isArgumentRegister(const MachineFunction &MF, MCRegister Reg) const
Returns true if a register can be used as an argument to a function.
Register createGenericVirtualRegister(LLT Ty, StringRef Name="")
Create and return a new generic virtual register with low-level type Ty.
bool hasOneDef(Register RegNo) const
Return true if there is exactly one operand defining the specified register.
static def_iterator def_end()
void updateDbgUsersToReg(MCRegister OldReg, MCRegister NewReg, ArrayRef< MachineInstr * > Users) const
updateDbgUsersToReg - Update a collection of debug instructions to refer to the designated register.
const RegClassOrRegBank & getRegClassOrRegBank(Register Reg) const
Return the register bank or register class of Reg.
void resetDelegate(Delegate *delegate)
bool use_nodbg_empty(Register RegNo) const
use_nodbg_empty - Return true if there are no non-Debug instructions using the specified register.
bool hasSingleElement(ContainerTy &&C)
Returns true if the given container only contains a single element.
StringSet - A wrapper for StringMap that provides set-like functionality.
defusechain_instr_iterator< true, false, false, false, true, false > use_instr_iterator
use_instr_iterator/use_instr_begin/use_instr_end - Walk all uses of the specified register,...
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
StringRef - Represent a constant reference to a string, i.e.
bool hasOneNonDBGUse(Register RegNo) const
hasOneNonDBGUse - Return true if there is exactly one non-Debug use of the specified register.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
bool isFixedRegister(const MachineFunction &MF, MCRegister Reg) const
Returns true if a register is a fixed register.
use_iterator use_begin(Register RegNo) const
void setRegAllocationHint(Register VReg, unsigned Type, Register PrefReg)
setRegAllocationHint - Specify a register allocation hint for the specified virtual register.
MachineBasicBlock::instr_iterator getBundleStart(MachineBasicBlock::instr_iterator I)
Returns an iterator to the first instruction in the bundle containing I.
void invalidateLiveness()
invalidateLiveness - Indicates that register liveness is no longer being tracked accurately.
defusechain_instr_iterator< true, true, true, false, true, false > reg_instr_nodbg_iterator
reg_instr_nodbg_iterator/reg_instr_nodbg_begin/reg_instr_nodbg_end - Walk all defs and uses of the sp...
void removeRegOperandFromUseList(MachineOperand *MO)
Remove MO from its use-def list.
bool operator!=(const defusechain_iterator &x) const
MachineFunctionProperties & reset(Property P)
const std::pair< Register, SmallVector< Register, 4 > > & getRegAllocationHints(Register VReg) const
getRegAllocationHints - Return a reference to the vector of all register allocation hints for VReg.
const BitVector & getReservedRegs() const
getReservedRegs - Returns a reference to the frozen set of reserved registers.
unsigned const MachineRegisterInfo * MRI
A discriminated union of two or more pointer types, with the discriminator in the low bit of the poin...
Wrapper class representing virtual and physical registers.
PSetIterator(Register RegUnit, const MachineRegisterInfo *MRI)
const BitVector & getUsedPhysRegsMask() const
bool isConstantPhysReg(MCRegister PhysReg) const
Returns true if PhysReg is unallocatable and constant throughout the function.
void replaceRegWith(Register FromReg, Register ToReg)
replaceRegWith - Replace all instances of FromReg with ToReg in the machine function.
iterator_range< def_iterator > def_operands(Register Reg) const
reg_iterator reg_begin(Register RegNo) const
bool test(unsigned Idx) const
void addRegOperandToUseList(MachineOperand *MO)
Add MO to the linked list of operands for its register.
Register getSimpleHint(Register VReg) const
getSimpleHint - same as getRegAllocationHint except it will only return a target independent hint.
bool isLiveIn(Register Reg) const
LaneBitmask getMaxLaneMaskForVReg(Register Reg) const
Returns a mask covering all bits that can appear in lane masks of subregisters of the virtual registe...
defusechain_instr_iterator< false, true, false, false, false, true > def_bundle_iterator
def_bundle_iterator/def_bundle_begin/def_bundle_end - Walk all defs of the specified register,...
Instructions::iterator instr_iterator
std::vector< std::pair< MCRegister, Register > >::const_iterator livein_iterator
bool reg_empty(Register RegNo) const
reg_empty - Return true if there are no instructions using or defining the specified register (it may...
const RegisterBank * getRegBankOrNull(Register Reg) const
Return the register bank of Reg, or null if Reg has not been assigned a register bank or has been ass...
void addPhysRegsUsedFromRegMask(const uint32_t *RegMask)
addPhysRegsUsedFromRegMask - Mark any registers not in RegMask as used.
void clearVirtRegs()
clearVirtRegs - Remove all virtual registers (after physreg assignment).
bool isPhysRegModified(MCRegister PhysReg, bool SkipNoReturnDef=false) const
Return true if the specified register is modified in this function.
bool hasOneNonDBGUser(Register RegNo) const
hasOneNonDBGUse - Return true if there is exactly one non-Debug instruction using the specified regis...
iterator_range< use_bundle_nodbg_iterator > use_nodbg_bundles(Register Reg) const
defusechain_iterator operator++(int)
static use_bundle_nodbg_iterator use_bundle_nodbg_end()
void addRegAllocationHint(Register VReg, Register PrefReg)
addRegAllocationHint - Add a register allocation hint to the hints vector for VReg.
defusechain_instr_iterator< true, false, true, false, false, true > use_bundle_nodbg_iterator
use_bundle_nodbg_iterator/use_bundle_nodbg_begin/use_bundle_nodbg_end - Walk all uses of the specifie...
std::ptrdiff_t difference_type
static use_iterator use_end()
static use_bundle_iterator use_bundle_end()
reg_bundle_nodbg_iterator reg_bundle_nodbg_begin(Register RegNo) const
bool hasOneUse(Register RegNo) const
hasOneUse - Return true if there is exactly one instruction using the specified register.
unsigned operator*() const
LLT getType(Register Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register.
Register cloneVirtualRegister(Register VReg, StringRef Name="")
Create and return a new virtual register in the function with the same attributes as the given regist...
bool inBounds(IndexT n) const
defusechain_instr_iterator< true, false, false, false, false, true > use_bundle_iterator
use_bundle_iterator/use_bundle_begin/use_bundle_end - Walk all uses of the specified register,...
bool isGeneralPurposeRegister(const MachineFunction &MF, MCRegister Reg) const
Returns true if a register is a general purpose register.
iv Induction Variable Users
A range adaptor for a pair of iterators.
const TargetRegisterClass * constrainRegClass(Register Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
reg_begin/reg_end - Provide iteration support to walk over all definitions and uses of a register wit...
use_bundle_nodbg_iterator use_bundle_nodbg_begin(Register RegNo) const
MachineRegisterInfo(MachineFunction *MF)
defusechain_instr_iterator< true, true, true, false, false, true > reg_bundle_nodbg_iterator
reg_bundle_nodbg_iterator/reg_bundle_nodbg_begin/reg_bundle_nodbg_end - Walk all defs and uses of the...
bool shouldTrackSubRegLiveness(Register VReg) const
bool isReservedRegUnit(unsigned Unit) const
Returns true when the given register unit is considered reserved.
void clearSimpleHint(Register VReg)
bool reg_nodbg_empty(Register RegNo) const
reg_nodbg_empty - Return true if the only instructions using or defining Reg are Debug instructions.
defusechain_iterator()=default
PSetIterator getPressureSets(Register RegUnit) const
Get an iterator over the pressure sets affected by the given physical or virtual register.
std::forward_iterator_tag iterator_category
void dumpUses(Register RegNo) const
livein_iterator livein_end() const
void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps)
Move NumOps operands from Src to Dst, updating use-def lists as needed.
static reg_bundle_nodbg_iterator reg_bundle_nodbg_end()
static use_instr_iterator use_instr_end()
void EmitLiveInCopies(MachineBasicBlock *EntryMBB, const TargetRegisterInfo &TRI, const TargetInstrInfo &TII)
EmitLiveInCopies - Emit copies to initialize livein virtual registers into the given entry block.
void setRegClass(Register Reg, const TargetRegisterClass *RC)
setRegClass - Set the register class of the specified virtual register.
std::pair< Register, Register > getRegAllocationHint(Register VReg) const
getRegAllocationHint - Return the register allocation hint for the specified virtual register.
void verifyUseLists() const
Verify the use list of all registers.
defusechain_instr_iterator< true, false, true, false, true, false > use_instr_nodbg_iterator
use_instr_nodbg_iterator/use_instr_nodbg_begin/use_instr_nodbg_end - Walk all uses of the specified r...
virtual ~Delegate()=default
Wrapper class representing physical registers. Should be passed by value.
defusechain_iterator & operator++()