LLVM  13.0.0git
MachineRegisterInfo.h
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1 //===- llvm/CodeGen/MachineRegisterInfo.h -----------------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the MachineRegisterInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_CODEGEN_MACHINEREGISTERINFO_H
14 #define LLVM_CODEGEN_MACHINEREGISTERINFO_H
15 
16 #include "llvm/ADT/ArrayRef.h"
17 #include "llvm/ADT/BitVector.h"
18 #include "llvm/ADT/DenseMap.h"
19 #include "llvm/ADT/IndexedMap.h"
20 #include "llvm/ADT/PointerUnion.h"
21 #include "llvm/ADT/SmallVector.h"
22 #include "llvm/ADT/StringSet.h"
32 #include "llvm/MC/LaneBitmask.h"
33 #include <cassert>
34 #include <cstddef>
35 #include <cstdint>
36 #include <iterator>
37 #include <memory>
38 #include <utility>
39 #include <vector>
40 
41 namespace llvm {
42 
43 class PSetIterator;
44 
45 /// Convenient type to represent either a register class or a register bank.
46 using RegClassOrRegBank =
48 
49 /// MachineRegisterInfo - Keep track of information for virtual and physical
50 /// registers, including vreg register classes, use/def chains for registers,
51 /// etc.
53 public:
54  class Delegate {
55  virtual void anchor();
56 
57  public:
58  virtual ~Delegate() = default;
59 
60  virtual void MRI_NoteNewVirtualRegister(Register Reg) = 0;
61  };
62 
63 private:
64  MachineFunction *MF;
65  Delegate *TheDelegate = nullptr;
66 
67  /// True if subregister liveness is tracked.
68  const bool TracksSubRegLiveness;
69 
70  /// VRegInfo - Information we keep for each virtual register.
71  ///
72  /// Each element in this list contains the register class of the vreg and the
73  /// start of the use/def list for the register.
76  VRegInfo;
77 
78  /// Map for recovering vreg name from vreg number.
79  /// This map is used by the MIR Printer.
81 
82  /// StringSet that is used to unique vreg names.
83  StringSet<> VRegNames;
84 
85  /// The flag is true upon \p UpdatedCSRs initialization
86  /// and false otherwise.
87  bool IsUpdatedCSRsInitialized;
88 
89  /// Contains the updated callee saved register list.
90  /// As opposed to the static list defined in register info,
91  /// all registers that were disabled are removed from the list.
92  SmallVector<MCPhysReg, 16> UpdatedCSRs;
93 
94  /// RegAllocHints - This vector records register allocation hints for
95  /// virtual registers. For each virtual register, it keeps a pair of hint
96  /// type and hints vector making up the allocation hints. Only the first
97  /// hint may be target specific, and in that case this is reflected by the
98  /// first member of the pair being non-zero. If the hinted register is
99  /// virtual, it means the allocator should prefer the physical register
100  /// allocated to it if any.
102  VirtReg2IndexFunctor> RegAllocHints;
103 
104  /// PhysRegUseDefLists - This is an array of the head of the use/def list for
105  /// physical registers.
106  std::unique_ptr<MachineOperand *[]> PhysRegUseDefLists;
107 
108  /// getRegUseDefListHead - Return the head pointer for the register use/def
109  /// list for the specified virtual or physical register.
110  MachineOperand *&getRegUseDefListHead(Register RegNo) {
111  if (RegNo.isVirtual())
112  return VRegInfo[RegNo.id()].second;
113  return PhysRegUseDefLists[RegNo.id()];
114  }
115 
116  MachineOperand *getRegUseDefListHead(Register RegNo) const {
117  if (RegNo.isVirtual())
118  return VRegInfo[RegNo.id()].second;
119  return PhysRegUseDefLists[RegNo.id()];
120  }
121 
122  /// Get the next element in the use-def chain.
123  static MachineOperand *getNextOperandForReg(const MachineOperand *MO) {
124  assert(MO && MO->isReg() && "This is not a register operand!");
125  return MO->Contents.Reg.Next;
126  }
127 
128  /// UsedPhysRegMask - Additional used physregs including aliases.
129  /// This bit vector represents all the registers clobbered by function calls.
130  BitVector UsedPhysRegMask;
131 
132  /// ReservedRegs - This is a bit vector of reserved registers. The target
133  /// may change its mind about which registers should be reserved. This
134  /// vector is the frozen set of reserved registers when register allocation
135  /// started.
136  BitVector ReservedRegs;
137 
138  using VRegToTypeMap = IndexedMap<LLT, VirtReg2IndexFunctor>;
139  /// Map generic virtual registers to their low-level type.
140  VRegToTypeMap VRegToType;
141 
142  /// Keep track of the physical registers that are live in to the function.
143  /// Live in values are typically arguments in registers. LiveIn values are
144  /// allowed to have virtual registers associated with them, stored in the
145  /// second element.
146  std::vector<std::pair<MCRegister, Register>> LiveIns;
147 
148 public:
149  explicit MachineRegisterInfo(MachineFunction *MF);
150  MachineRegisterInfo(const MachineRegisterInfo &) = delete;
152 
154  return MF->getSubtarget().getRegisterInfo();
155  }
156 
157  void resetDelegate(Delegate *delegate) {
158  // Ensure another delegate does not take over unless the current
159  // delegate first unattaches itself. If we ever need to multicast
160  // notifications, we will need to change to using a list.
161  assert(TheDelegate == delegate &&
162  "Only the current delegate can perform reset!");
163  TheDelegate = nullptr;
164  }
165 
166  void setDelegate(Delegate *delegate) {
167  assert(delegate && !TheDelegate &&
168  "Attempted to set delegate to null, or to change it without "
169  "first resetting it!");
170 
171  TheDelegate = delegate;
172  }
173 
174  //===--------------------------------------------------------------------===//
175  // Function State
176  //===--------------------------------------------------------------------===//
177 
178  // isSSA - Returns true when the machine function is in SSA form. Early
179  // passes require the machine function to be in SSA form where every virtual
180  // register has a single defining instruction.
181  //
182  // The TwoAddressInstructionPass and PHIElimination passes take the machine
183  // function out of SSA form when they introduce multiple defs per virtual
184  // register.
185  bool isSSA() const {
186  return MF->getProperties().hasProperty(
188  }
189 
190  // leaveSSA - Indicates that the machine function is no longer in SSA form.
191  void leaveSSA() {
193  }
194 
195  /// tracksLiveness - Returns true when tracking register liveness accurately.
196  /// (see MachineFUnctionProperties::Property description for details)
197  bool tracksLiveness() const {
198  return MF->getProperties().hasProperty(
200  }
201 
202  /// invalidateLiveness - Indicates that register liveness is no longer being
203  /// tracked accurately.
204  ///
205  /// This should be called by late passes that invalidate the liveness
206  /// information.
208  MF->getProperties().reset(
210  }
211 
212  /// Returns true if liveness for register class @p RC should be tracked at
213  /// the subregister level.
216  }
218  assert(VReg.isVirtual() && "Must pass a VReg");
219  return shouldTrackSubRegLiveness(*getRegClass(VReg));
220  }
221  bool subRegLivenessEnabled() const {
222  return TracksSubRegLiveness;
223  }
224 
225  //===--------------------------------------------------------------------===//
226  // Register Info
227  //===--------------------------------------------------------------------===//
228 
229  /// Returns true if the updated CSR list was initialized and false otherwise.
230  bool isUpdatedCSRsInitialized() const { return IsUpdatedCSRsInitialized; }
231 
232  /// Disables the register from the list of CSRs.
233  /// I.e. the register will not appear as part of the CSR mask.
234  /// \see UpdatedCalleeSavedRegs.
236 
237  /// Returns list of callee saved registers.
238  /// The function returns the updated CSR list (after taking into account
239  /// registers that are disabled from the CSR list).
240  const MCPhysReg *getCalleeSavedRegs() const;
241 
242  /// Sets the updated Callee Saved Registers list.
243  /// Notice that it will override ant previously disabled/saved CSRs.
245 
246  // Strictly for use by MachineInstr.cpp.
248 
249  // Strictly for use by MachineInstr.cpp.
251 
252  // Strictly for use by MachineInstr.cpp.
253  void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps);
254 
255  /// Verify the sanity of the use list for Reg.
256  void verifyUseList(Register Reg) const;
257 
258  /// Verify the use list of all registers.
259  void verifyUseLists() const;
260 
261  /// reg_begin/reg_end - Provide iteration support to walk over all definitions
262  /// and uses of a register within the MachineFunction that corresponds to this
263  /// MachineRegisterInfo object.
264  template<bool Uses, bool Defs, bool SkipDebug,
265  bool ByOperand, bool ByInstr, bool ByBundle>
267  template<bool Uses, bool Defs, bool SkipDebug,
268  bool ByOperand, bool ByInstr, bool ByBundle>
270 
271  // Make it a friend so it can access getNextOperandForReg().
272  template<bool, bool, bool, bool, bool, bool>
273  friend class defusechain_iterator;
274  template<bool, bool, bool, bool, bool, bool>
276 
277  /// reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specified
278  /// register.
279  using reg_iterator =
282  return reg_iterator(getRegUseDefListHead(RegNo));
283  }
284  static reg_iterator reg_end() { return reg_iterator(nullptr); }
285 
287  return make_range(reg_begin(Reg), reg_end());
288  }
289 
290  /// reg_instr_iterator/reg_instr_begin/reg_instr_end - Walk all defs and uses
291  /// of the specified register, stepping by MachineInstr.
292  using reg_instr_iterator =
295  return reg_instr_iterator(getRegUseDefListHead(RegNo));
296  }
298  return reg_instr_iterator(nullptr);
299  }
300 
304  }
305 
306  /// reg_bundle_iterator/reg_bundle_begin/reg_bundle_end - Walk all defs and uses
307  /// of the specified register, stepping by bundle.
308  using reg_bundle_iterator =
311  return reg_bundle_iterator(getRegUseDefListHead(RegNo));
312  }
314  return reg_bundle_iterator(nullptr);
315  }
316 
319  }
320 
321  /// reg_empty - Return true if there are no instructions using or defining the
322  /// specified register (it may be live-in).
323  bool reg_empty(Register RegNo) const { return reg_begin(RegNo) == reg_end(); }
324 
325  /// reg_nodbg_iterator/reg_nodbg_begin/reg_nodbg_end - Walk all defs and uses
326  /// of the specified register, skipping those marked as Debug.
327  using reg_nodbg_iterator =
330  return reg_nodbg_iterator(getRegUseDefListHead(RegNo));
331  }
333  return reg_nodbg_iterator(nullptr);
334  }
335 
339  }
340 
341  /// reg_instr_nodbg_iterator/reg_instr_nodbg_begin/reg_instr_nodbg_end - Walk
342  /// all defs and uses of the specified register, stepping by MachineInstr,
343  /// skipping those marked as Debug.
347  return reg_instr_nodbg_iterator(getRegUseDefListHead(RegNo));
348  }
350  return reg_instr_nodbg_iterator(nullptr);
351  }
352 
356  }
357 
358  /// reg_bundle_nodbg_iterator/reg_bundle_nodbg_begin/reg_bundle_nodbg_end - Walk
359  /// all defs and uses of the specified register, stepping by bundle,
360  /// skipping those marked as Debug.
364  return reg_bundle_nodbg_iterator(getRegUseDefListHead(RegNo));
365  }
367  return reg_bundle_nodbg_iterator(nullptr);
368  }
369 
373  }
374 
375  /// reg_nodbg_empty - Return true if the only instructions using or defining
376  /// Reg are Debug instructions.
377  bool reg_nodbg_empty(Register RegNo) const {
378  return reg_nodbg_begin(RegNo) == reg_nodbg_end();
379  }
380 
381  /// def_iterator/def_begin/def_end - Walk all defs of the specified register.
382  using def_iterator =
385  return def_iterator(getRegUseDefListHead(RegNo));
386  }
387  static def_iterator def_end() { return def_iterator(nullptr); }
388 
390  return make_range(def_begin(Reg), def_end());
391  }
392 
393  /// def_instr_iterator/def_instr_begin/def_instr_end - Walk all defs of the
394  /// specified register, stepping by MachineInst.
395  using def_instr_iterator =
398  return def_instr_iterator(getRegUseDefListHead(RegNo));
399  }
401  return def_instr_iterator(nullptr);
402  }
403 
407  }
408 
409  /// def_bundle_iterator/def_bundle_begin/def_bundle_end - Walk all defs of the
410  /// specified register, stepping by bundle.
411  using def_bundle_iterator =
414  return def_bundle_iterator(getRegUseDefListHead(RegNo));
415  }
417  return def_bundle_iterator(nullptr);
418  }
419 
422  }
423 
424  /// def_empty - Return true if there are no instructions defining the
425  /// specified register (it may be live-in).
426  bool def_empty(Register RegNo) const { return def_begin(RegNo) == def_end(); }
427 
429  return VReg2Name.inBounds(Reg) ? StringRef(VReg2Name[Reg]) : "";
430  }
431 
433  assert((Name.empty() || VRegNames.find(Name) == VRegNames.end()) &&
434  "Named VRegs Must be Unique.");
435  if (!Name.empty()) {
436  VRegNames.insert(Name);
437  VReg2Name.grow(Reg);
438  VReg2Name[Reg] = Name.str();
439  }
440  }
441 
442  /// Return true if there is exactly one operand defining the specified
443  /// register.
444  bool hasOneDef(Register RegNo) const {
445  return hasSingleElement(def_operands(RegNo));
446  }
447 
448  /// Returns the defining operand if there is exactly one operand defining the
449  /// specified register, otherwise nullptr.
451  def_iterator DI = def_begin(Reg);
452  if (DI == def_end()) // No defs.
453  return nullptr;
454 
455  def_iterator OneDef = DI;
456  if (++DI == def_end())
457  return &*OneDef;
458  return nullptr; // Multiple defs.
459  }
460 
461  /// use_iterator/use_begin/use_end - Walk all uses of the specified register.
462  using use_iterator =
465  return use_iterator(getRegUseDefListHead(RegNo));
466  }
467  static use_iterator use_end() { return use_iterator(nullptr); }
468 
470  return make_range(use_begin(Reg), use_end());
471  }
472 
473  /// use_instr_iterator/use_instr_begin/use_instr_end - Walk all uses of the
474  /// specified register, stepping by MachineInstr.
475  using use_instr_iterator =
478  return use_instr_iterator(getRegUseDefListHead(RegNo));
479  }
481  return use_instr_iterator(nullptr);
482  }
483 
487  }
488 
489  /// use_bundle_iterator/use_bundle_begin/use_bundle_end - Walk all uses of the
490  /// specified register, stepping by bundle.
491  using use_bundle_iterator =
494  return use_bundle_iterator(getRegUseDefListHead(RegNo));
495  }
497  return use_bundle_iterator(nullptr);
498  }
499 
502  }
503 
504  /// use_empty - Return true if there are no instructions using the specified
505  /// register.
506  bool use_empty(Register RegNo) const { return use_begin(RegNo) == use_end(); }
507 
508  /// hasOneUse - Return true if there is exactly one instruction using the
509  /// specified register.
510  bool hasOneUse(Register RegNo) const {
511  return hasSingleElement(use_operands(RegNo));
512  }
513 
514  /// use_nodbg_iterator/use_nodbg_begin/use_nodbg_end - Walk all uses of the
515  /// specified register, skipping those marked as Debug.
516  using use_nodbg_iterator =
519  return use_nodbg_iterator(getRegUseDefListHead(RegNo));
520  }
522  return use_nodbg_iterator(nullptr);
523  }
524 
528  }
529 
530  /// use_instr_nodbg_iterator/use_instr_nodbg_begin/use_instr_nodbg_end - Walk
531  /// all uses of the specified register, stepping by MachineInstr, skipping
532  /// those marked as Debug.
536  return use_instr_nodbg_iterator(getRegUseDefListHead(RegNo));
537  }
539  return use_instr_nodbg_iterator(nullptr);
540  }
541 
545  }
546 
547  /// use_bundle_nodbg_iterator/use_bundle_nodbg_begin/use_bundle_nodbg_end - Walk
548  /// all uses of the specified register, stepping by bundle, skipping
549  /// those marked as Debug.
553  return use_bundle_nodbg_iterator(getRegUseDefListHead(RegNo));
554  }
556  return use_bundle_nodbg_iterator(nullptr);
557  }
558 
562  }
563 
564  /// use_nodbg_empty - Return true if there are no non-Debug instructions
565  /// using the specified register.
566  bool use_nodbg_empty(Register RegNo) const {
567  return use_nodbg_begin(RegNo) == use_nodbg_end();
568  }
569 
570  /// hasOneNonDBGUse - Return true if there is exactly one non-Debug
571  /// use of the specified register.
572  bool hasOneNonDBGUse(Register RegNo) const;
573 
574  /// hasOneNonDBGUse - Return true if there is exactly one non-Debug
575  /// instruction using the specified register. Said instruction may have
576  /// multiple uses.
577  bool hasOneNonDBGUser(Register RegNo) const;
578 
579  /// replaceRegWith - Replace all instances of FromReg with ToReg in the
580  /// machine function. This is like llvm-level X->replaceAllUsesWith(Y),
581  /// except that it also changes any definitions of the register as well.
582  ///
583  /// Note that it is usually necessary to first constrain ToReg's register
584  /// class and register bank to match the FromReg constraints using one of the
585  /// methods:
586  ///
587  /// constrainRegClass(ToReg, getRegClass(FromReg))
588  /// constrainRegAttrs(ToReg, FromReg)
589  /// RegisterBankInfo::constrainGenericRegister(ToReg,
590  /// *MRI.getRegClass(FromReg), MRI)
591  ///
592  /// These functions will return a falsy result if the virtual registers have
593  /// incompatible constraints.
594  ///
595  /// Note that if ToReg is a physical register the function will replace and
596  /// apply sub registers to ToReg in order to obtain a final/proper physical
597  /// register.
598  void replaceRegWith(Register FromReg, Register ToReg);
599 
600  /// getVRegDef - Return the machine instr that defines the specified virtual
601  /// register or null if none is found. This assumes that the code is in SSA
602  /// form, so there should only be one definition.
604 
605  /// getUniqueVRegDef - Return the unique machine instr that defines the
606  /// specified virtual register or null if none is found. If there are
607  /// multiple definitions or no definition, return null.
609 
610  /// clearKillFlags - Iterate over all the uses of the given register and
611  /// clear the kill flag from the MachineOperand. This function is used by
612  /// optimization passes which extend register lifetimes and need only
613  /// preserve conservative kill flag information.
614  void clearKillFlags(Register Reg) const;
615 
616  void dumpUses(Register RegNo) const;
617 
618  /// Returns true if PhysReg is unallocatable and constant throughout the
619  /// function. Writing to a constant register has no effect.
620  bool isConstantPhysReg(MCRegister PhysReg) const;
621 
622  /// Get an iterator over the pressure sets affected by the given physical or
623  /// virtual register. If RegUnit is physical, it must be a register unit (from
624  /// MCRegUnitIterator).
625  PSetIterator getPressureSets(Register RegUnit) const;
626 
627  //===--------------------------------------------------------------------===//
628  // Virtual Register Info
629  //===--------------------------------------------------------------------===//
630 
631  /// Return the register class of the specified virtual register.
632  /// This shouldn't be used directly unless \p Reg has a register class.
633  /// \see getRegClassOrNull when this might happen.
635  assert(VRegInfo[Reg.id()].first.is<const TargetRegisterClass *>() &&
636  "Register class not set, wrong accessor");
637  return VRegInfo[Reg.id()].first.get<const TargetRegisterClass *>();
638  }
639 
640  /// Return the register class of \p Reg, or null if Reg has not been assigned
641  /// a register class yet.
642  ///
643  /// \note A null register class can only happen when these two
644  /// conditions are met:
645  /// 1. Generic virtual registers are created.
646  /// 2. The machine function has not completely been through the
647  /// instruction selection process.
648  /// None of this condition is possible without GlobalISel for now.
649  /// In other words, if GlobalISel is not used or if the query happens after
650  /// the select pass, using getRegClass is safe.
652  const RegClassOrRegBank &Val = VRegInfo[Reg].first;
653  return Val.dyn_cast<const TargetRegisterClass *>();
654  }
655 
656  /// Return the register bank of \p Reg, or null if Reg has not been assigned
657  /// a register bank or has been assigned a register class.
658  /// \note It is possible to get the register bank from the register class via
659  /// RegisterBankInfo::getRegBankFromRegClass.
661  const RegClassOrRegBank &Val = VRegInfo[Reg].first;
662  return Val.dyn_cast<const RegisterBank *>();
663  }
664 
665  /// Return the register bank or register class of \p Reg.
666  /// \note Before the register bank gets assigned (i.e., before the
667  /// RegBankSelect pass) \p Reg may not have either.
669  return VRegInfo[Reg].first;
670  }
671 
672  /// setRegClass - Set the register class of the specified virtual register.
673  void setRegClass(Register Reg, const TargetRegisterClass *RC);
674 
675  /// Set the register bank to \p RegBank for \p Reg.
676  void setRegBank(Register Reg, const RegisterBank &RegBank);
677 
679  const RegClassOrRegBank &RCOrRB){
680  VRegInfo[Reg].first = RCOrRB;
681  }
682 
683  /// constrainRegClass - Constrain the register class of the specified virtual
684  /// register to be a common subclass of RC and the current register class,
685  /// but only if the new class has at least MinNumRegs registers. Return the
686  /// new register class, or NULL if no such class exists.
687  /// This should only be used when the constraint is known to be trivial, like
688  /// GR32 -> GR32_NOSP. Beware of increasing register pressure.
689  ///
690  /// \note Assumes that the register has a register class assigned.
691  /// Use RegisterBankInfo::constrainGenericRegister in GlobalISel's
692  /// InstructionSelect pass and constrainRegAttrs in every other pass,
693  /// including non-select passes of GlobalISel, instead.
695  const TargetRegisterClass *RC,
696  unsigned MinNumRegs = 0);
697 
698  /// Constrain the register class or the register bank of the virtual register
699  /// \p Reg (and low-level type) to be a common subclass or a common bank of
700  /// both registers provided respectively (and a common low-level type). Do
701  /// nothing if any of the attributes (classes, banks, or low-level types) of
702  /// the registers are deemed incompatible, or if the resulting register will
703  /// have a class smaller than before and of size less than \p MinNumRegs.
704  /// Return true if such register attributes exist, false otherwise.
705  ///
706  /// \note Use this method instead of constrainRegClass and
707  /// RegisterBankInfo::constrainGenericRegister everywhere but SelectionDAG
708  /// ISel / FastISel and GlobalISel's InstructionSelect pass respectively.
709  bool constrainRegAttrs(Register Reg, Register ConstrainingReg,
710  unsigned MinNumRegs = 0);
711 
712  /// recomputeRegClass - Try to find a legal super-class of Reg's register
713  /// class that still satisfies the constraints from the instructions using
714  /// Reg. Returns true if Reg was upgraded.
715  ///
716  /// This method can be used after constraints have been removed from a
717  /// virtual register, for example after removing instructions or splitting
718  /// the live range.
720 
721  /// createVirtualRegister - Create and return a new virtual register in the
722  /// function with the specified register class.
724  StringRef Name = "");
725 
726  /// Create and return a new virtual register in the function with the same
727  /// attributes as the given register.
729 
730  /// Get the low-level type of \p Reg or LLT{} if Reg is not a generic
731  /// (target independent) virtual register.
733  if (Register::isVirtualRegister(Reg) && VRegToType.inBounds(Reg))
734  return VRegToType[Reg];
735  return LLT{};
736  }
737 
738  /// Set the low-level type of \p VReg to \p Ty.
739  void setType(Register VReg, LLT Ty);
740 
741  /// Create and return a new generic virtual register with low-level
742  /// type \p Ty.
744 
745  /// Remove all types associated to virtual registers (after instruction
746  /// selection and constraining of all generic virtual registers).
747  void clearVirtRegTypes();
748 
749  /// Creates a new virtual register that has no register class, register bank
750  /// or size assigned yet. This is only allowed to be used
751  /// temporarily while constructing machine instructions. Most operations are
752  /// undefined on an incomplete register until one of setRegClass(),
753  /// setRegBank() or setSize() has been called on it.
755 
756  /// getNumVirtRegs - Return the number of virtual registers created.
757  unsigned getNumVirtRegs() const { return VRegInfo.size(); }
758 
759  /// clearVirtRegs - Remove all virtual registers (after physreg assignment).
760  void clearVirtRegs();
761 
762  /// setRegAllocationHint - Specify a register allocation hint for the
763  /// specified virtual register. This is typically used by target, and in case
764  /// of an earlier hint it will be overwritten.
765  void setRegAllocationHint(Register VReg, unsigned Type, Register PrefReg) {
766  assert(VReg.isVirtual());
767  RegAllocHints[VReg].first = Type;
768  RegAllocHints[VReg].second.clear();
769  RegAllocHints[VReg].second.push_back(PrefReg);
770  }
771 
772  /// addRegAllocationHint - Add a register allocation hint to the hints
773  /// vector for VReg.
774  void addRegAllocationHint(Register VReg, Register PrefReg) {
776  RegAllocHints[VReg].second.push_back(PrefReg);
777  }
778 
779  /// Specify the preferred (target independent) register allocation hint for
780  /// the specified virtual register.
781  void setSimpleHint(Register VReg, Register PrefReg) {
782  setRegAllocationHint(VReg, /*Type=*/0, PrefReg);
783  }
784 
786  assert (!RegAllocHints[VReg].first &&
787  "Expected to clear a non-target hint!");
788  RegAllocHints[VReg].second.clear();
789  }
790 
791  /// getRegAllocationHint - Return the register allocation hint for the
792  /// specified virtual register. If there are many hints, this returns the
793  /// one with the greatest weight.
794  std::pair<Register, Register>
796  assert(VReg.isVirtual());
797  Register BestHint = (RegAllocHints[VReg.id()].second.size() ?
798  RegAllocHints[VReg.id()].second[0] : Register());
799  return std::pair<Register, Register>(RegAllocHints[VReg.id()].first,
800  BestHint);
801  }
802 
803  /// getSimpleHint - same as getRegAllocationHint except it will only return
804  /// a target independent hint.
806  assert(VReg.isVirtual());
807  std::pair<Register, Register> Hint = getRegAllocationHint(VReg);
808  return Hint.first ? Register() : Hint.second;
809  }
810 
811  /// getRegAllocationHints - Return a reference to the vector of all
812  /// register allocation hints for VReg.
813  const std::pair<Register, SmallVector<Register, 4>>
815  assert(VReg.isVirtual());
816  return RegAllocHints[VReg];
817  }
818 
819  /// markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the
820  /// specified register as undefined which causes the DBG_VALUE to be
821  /// deleted during LiveDebugVariables analysis.
823 
824  /// updateDbgUsersToReg - Update a collection of DBG_VALUE instructions
825  /// to refer to the designated register.
828  SmallSet<MCRegister, 4> OldRegUnits;
829  for (MCRegUnitIterator RUI(OldReg, getTargetRegisterInfo()); RUI.isValid();
830  ++RUI)
831  OldRegUnits.insert(*RUI);
832  for (MachineInstr *MI : Users) {
833  assert(MI->isDebugValue());
834  for (auto &Op : MI->debug_operands()) {
835  if (Op.isReg()) {
836  for (MCRegUnitIterator RUI(OldReg, getTargetRegisterInfo());
837  RUI.isValid(); ++RUI) {
838  if (OldRegUnits.contains(*RUI)) {
839  Op.setReg(NewReg);
840  break;
841  }
842  }
843  }
844  }
845  assert(MI->hasDebugOperandForReg(NewReg) &&
846  "Expected debug value to have some overlap with OldReg");
847  }
848  }
849 
850  /// Return true if the specified register is modified in this function.
851  /// This checks that no defining machine operands exist for the register or
852  /// any of its aliases. Definitions found on functions marked noreturn are
853  /// ignored, to consider them pass 'true' for optional parameter
854  /// SkipNoReturnDef. The register is also considered modified when it is set
855  /// in the UsedPhysRegMask.
856  bool isPhysRegModified(MCRegister PhysReg, bool SkipNoReturnDef = false) const;
857 
858  /// Return true if the specified register is modified or read in this
859  /// function. This checks that no machine operands exist for the register or
860  /// any of its aliases. The register is also considered used when it is set
861  /// in the UsedPhysRegMask.
862  bool isPhysRegUsed(MCRegister PhysReg) const;
863 
864  /// addPhysRegsUsedFromRegMask - Mark any registers not in RegMask as used.
865  /// This corresponds to the bit mask attached to register mask operands.
866  void addPhysRegsUsedFromRegMask(const uint32_t *RegMask) {
867  UsedPhysRegMask.setBitsNotInMask(RegMask);
868  }
869 
870  const BitVector &getUsedPhysRegsMask() const { return UsedPhysRegMask; }
871 
872  //===--------------------------------------------------------------------===//
873  // Reserved Register Info
874  //===--------------------------------------------------------------------===//
875  //
876  // The set of reserved registers must be invariant during register
877  // allocation. For example, the target cannot suddenly decide it needs a
878  // frame pointer when the register allocator has already used the frame
879  // pointer register for something else.
880  //
881  // These methods can be used by target hooks like hasFP() to avoid changing
882  // the reserved register set during register allocation.
883 
884  /// freezeReservedRegs - Called by the register allocator to freeze the set
885  /// of reserved registers before allocation begins.
886  void freezeReservedRegs(const MachineFunction&);
887 
888  /// reservedRegsFrozen - Returns true after freezeReservedRegs() was called
889  /// to ensure the set of reserved registers stays constant.
890  bool reservedRegsFrozen() const {
891  return !ReservedRegs.empty();
892  }
893 
894  /// canReserveReg - Returns true if PhysReg can be used as a reserved
895  /// register. Any register can be reserved before freezeReservedRegs() is
896  /// called.
897  bool canReserveReg(MCRegister PhysReg) const {
898  return !reservedRegsFrozen() || ReservedRegs.test(PhysReg);
899  }
900 
901  /// getReservedRegs - Returns a reference to the frozen set of reserved
902  /// registers. This method should always be preferred to calling
903  /// TRI::getReservedRegs() when possible.
904  const BitVector &getReservedRegs() const {
906  "Reserved registers haven't been frozen yet. "
907  "Use TRI::getReservedRegs().");
908  return ReservedRegs;
909  }
910 
911  /// isReserved - Returns true when PhysReg is a reserved register.
912  ///
913  /// Reserved registers may belong to an allocatable register class, but the
914  /// target has explicitly requested that they are not used.
915  bool isReserved(MCRegister PhysReg) const {
916  return getReservedRegs().test(PhysReg.id());
917  }
918 
919  /// Returns true when the given register unit is considered reserved.
920  ///
921  /// Register units are considered reserved when for at least one of their
922  /// root registers, the root register and all super registers are reserved.
923  /// This currently iterates the register hierarchy and may be slower than
924  /// expected.
925  bool isReservedRegUnit(unsigned Unit) const;
926 
927  /// isAllocatable - Returns true when PhysReg belongs to an allocatable
928  /// register class and it hasn't been reserved.
929  ///
930  /// Allocatable registers may show up in the allocation order of some virtual
931  /// register, so a register allocator needs to track its liveness and
932  /// availability.
933  bool isAllocatable(MCRegister PhysReg) const {
934  return getTargetRegisterInfo()->isInAllocatableClass(PhysReg) &&
935  !isReserved(PhysReg);
936  }
937 
938  //===--------------------------------------------------------------------===//
939  // LiveIn Management
940  //===--------------------------------------------------------------------===//
941 
942  /// addLiveIn - Add the specified register as a live-in. Note that it
943  /// is an error to add the same register to the same set more than once.
945  LiveIns.push_back(std::make_pair(Reg, vreg));
946  }
947 
948  // Iteration support for the live-ins set. It's kept in sorted order
949  // by register number.
950  using livein_iterator =
951  std::vector<std::pair<MCRegister,Register>>::const_iterator;
952  livein_iterator livein_begin() const { return LiveIns.begin(); }
953  livein_iterator livein_end() const { return LiveIns.end(); }
954  bool livein_empty() const { return LiveIns.empty(); }
955 
957  return LiveIns;
958  }
959 
960  bool isLiveIn(Register Reg) const;
961 
962  /// getLiveInPhysReg - If VReg is a live-in virtual register, return the
963  /// corresponding live-in physical register.
965 
966  /// getLiveInVirtReg - If PReg is a live-in physical register, return the
967  /// corresponding live-in physical register.
969 
970  /// EmitLiveInCopies - Emit copies to initialize livein virtual registers
971  /// into the given entry block.
972  void EmitLiveInCopies(MachineBasicBlock *EntryMBB,
973  const TargetRegisterInfo &TRI,
974  const TargetInstrInfo &TII);
975 
976  /// Returns a mask covering all bits that can appear in lane masks of
977  /// subregisters of the virtual register @p Reg.
979 
980  /// defusechain_iterator - This class provides iterator support for machine
981  /// operands in the function that use or define a specific register. If
982  /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it
983  /// returns defs. If neither are true then you are silly and it always
984  /// returns end(). If SkipDebug is true it skips uses marked Debug
985  /// when incrementing.
986  template <bool ReturnUses, bool ReturnDefs, bool SkipDebug, bool ByOperand,
987  bool ByInstr, bool ByBundle>
988  class defusechain_iterator {
989  friend class MachineRegisterInfo;
990 
991  public:
992  using iterator_category = std::forward_iterator_tag;
994  using difference_type = std::ptrdiff_t;
995  using pointer = value_type *;
997 
998  private:
999  MachineOperand *Op = nullptr;
1000 
1001  explicit defusechain_iterator(MachineOperand *op) : Op(op) {
1002  // If the first node isn't one we're interested in, advance to one that
1003  // we are interested in.
1004  if (op) {
1005  if ((!ReturnUses && op->isUse()) ||
1006  (!ReturnDefs && op->isDef()) ||
1007  (SkipDebug && op->isDebug()))
1008  advance();
1009  }
1010  }
1011 
1012  void advance() {
1013  assert(Op && "Cannot increment end iterator!");
1014  Op = getNextOperandForReg(Op);
1015 
1016  // All defs come before the uses, so stop def_iterator early.
1017  if (!ReturnUses) {
1018  if (Op) {
1019  if (Op->isUse())
1020  Op = nullptr;
1021  else
1022  assert(!Op->isDebug() && "Can't have debug defs");
1023  }
1024  } else {
1025  // If this is an operand we don't care about, skip it.
1026  while (Op && ((!ReturnDefs && Op->isDef()) ||
1027  (SkipDebug && Op->isDebug())))
1028  Op = getNextOperandForReg(Op);
1029  }
1030  }
1031 
1032  public:
1033  defusechain_iterator() = default;
1034 
1035  bool operator==(const defusechain_iterator &x) const {
1036  return Op == x.Op;
1037  }
1038  bool operator!=(const defusechain_iterator &x) const {
1039  return !operator==(x);
1040  }
1041 
1042  /// atEnd - return true if this iterator is equal to reg_end() on the value.
1043  bool atEnd() const { return Op == nullptr; }
1044 
1045  // Iterator traversal: forward iteration only
1046  defusechain_iterator &operator++() { // Preincrement
1047  assert(Op && "Cannot increment end iterator!");
1048  if (ByOperand)
1049  advance();
1050  else if (ByInstr) {
1051  MachineInstr *P = Op->getParent();
1052  do {
1053  advance();
1054  } while (Op && Op->getParent() == P);
1055  } else if (ByBundle) {
1057  getBundleStart(Op->getParent()->getIterator());
1058  do {
1059  advance();
1060  } while (Op && getBundleStart(Op->getParent()->getIterator()) == P);
1061  }
1062 
1063  return *this;
1064  }
1065  defusechain_iterator operator++(int) { // Postincrement
1066  defusechain_iterator tmp = *this; ++*this; return tmp;
1067  }
1068 
1069  /// getOperandNo - Return the operand # of this MachineOperand in its
1070  /// MachineInstr.
1071  unsigned getOperandNo() const {
1072  assert(Op && "Cannot dereference end iterator!");
1073  return Op - &Op->getParent()->getOperand(0);
1074  }
1075 
1076  // Retrieve a reference to the current operand.
1078  assert(Op && "Cannot dereference end iterator!");
1079  return *Op;
1080  }
1081 
1083  assert(Op && "Cannot dereference end iterator!");
1084  return Op;
1085  }
1086  };
1087 
1088  /// defusechain_iterator - This class provides iterator support for machine
1089  /// operands in the function that use or define a specific register. If
1090  /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it
1091  /// returns defs. If neither are true then you are silly and it always
1092  /// returns end(). If SkipDebug is true it skips uses marked Debug
1093  /// when incrementing.
1094  template <bool ReturnUses, bool ReturnDefs, bool SkipDebug, bool ByOperand,
1095  bool ByInstr, bool ByBundle>
1097  friend class MachineRegisterInfo;
1098 
1099  public:
1100  using iterator_category = std::forward_iterator_tag;
1102  using difference_type = std::ptrdiff_t;
1103  using pointer = value_type *;
1105 
1106  private:
1107  MachineOperand *Op = nullptr;
1108 
1110  // If the first node isn't one we're interested in, advance to one that
1111  // we are interested in.
1112  if (op) {
1113  if ((!ReturnUses && op->isUse()) ||
1114  (!ReturnDefs && op->isDef()) ||
1115  (SkipDebug && op->isDebug()))
1116  advance();
1117  }
1118  }
1119 
1120  void advance() {
1121  assert(Op && "Cannot increment end iterator!");
1122  Op = getNextOperandForReg(Op);
1123 
1124  // All defs come before the uses, so stop def_iterator early.
1125  if (!ReturnUses) {
1126  if (Op) {
1127  if (Op->isUse())
1128  Op = nullptr;
1129  else
1130  assert(!Op->isDebug() && "Can't have debug defs");
1131  }
1132  } else {
1133  // If this is an operand we don't care about, skip it.
1134  while (Op && ((!ReturnDefs && Op->isDef()) ||
1135  (SkipDebug && Op->isDebug())))
1136  Op = getNextOperandForReg(Op);
1137  }
1138  }
1139 
1140  public:
1141  defusechain_instr_iterator() = default;
1142 
1144  return Op == x.Op;
1145  }
1147  return !operator==(x);
1148  }
1149 
1150  /// atEnd - return true if this iterator is equal to reg_end() on the value.
1151  bool atEnd() const { return Op == nullptr; }
1152 
1153  // Iterator traversal: forward iteration only
1155  assert(Op && "Cannot increment end iterator!");
1156  if (ByOperand)
1157  advance();
1158  else if (ByInstr) {
1159  MachineInstr *P = Op->getParent();
1160  do {
1161  advance();
1162  } while (Op && Op->getParent() == P);
1163  } else if (ByBundle) {
1165  getBundleStart(Op->getParent()->getIterator());
1166  do {
1167  advance();
1168  } while (Op && getBundleStart(Op->getParent()->getIterator()) == P);
1169  }
1170 
1171  return *this;
1172  }
1173  defusechain_instr_iterator operator++(int) { // Postincrement
1174  defusechain_instr_iterator tmp = *this; ++*this; return tmp;
1175  }
1176 
1177  // Retrieve a reference to the current operand.
1179  assert(Op && "Cannot dereference end iterator!");
1180  if (ByBundle)
1181  return *getBundleStart(Op->getParent()->getIterator());
1182  return *Op->getParent();
1183  }
1184 
1185  MachineInstr *operator->() const { return &operator*(); }
1186  };
1187 };
1188 
1189 /// Iterate over the pressure sets affected by the given physical or virtual
1190 /// register. If Reg is physical, it must be a register unit (from
1191 /// MCRegUnitIterator).
1193  const int *PSet = nullptr;
1194  unsigned Weight = 0;
1195 
1196 public:
1197  PSetIterator() = default;
1198 
1200  const TargetRegisterInfo *TRI = MRI->getTargetRegisterInfo();
1201  if (RegUnit.isVirtual()) {
1202  const TargetRegisterClass *RC = MRI->getRegClass(RegUnit);
1203  PSet = TRI->getRegClassPressureSets(RC);
1204  Weight = TRI->getRegClassWeight(RC).RegWeight;
1205  } else {
1206  PSet = TRI->getRegUnitPressureSets(RegUnit);
1207  Weight = TRI->getRegUnitWeight(RegUnit);
1208  }
1209  if (*PSet == -1)
1210  PSet = nullptr;
1211  }
1212 
1213  bool isValid() const { return PSet; }
1214 
1215  unsigned getWeight() const { return Weight; }
1216 
1217  unsigned operator*() const { return *PSet; }
1218 
1219  void operator++() {
1220  assert(isValid() && "Invalid PSetIterator.");
1221  ++PSet;
1222  if (*PSet == -1)
1223  PSet = nullptr;
1224  }
1225 };
1226 
1227 inline PSetIterator
1229  return PSetIterator(RegUnit, this);
1230 }
1231 
1232 } // end namespace llvm
1233 
1234 #endif // LLVM_CODEGEN_MACHINEREGISTERINFO_H
llvm::MachineRegisterInfo::addLiveIn
void addLiveIn(MCRegister Reg, Register vreg=Register())
addLiveIn - Add the specified register as a live-in.
Definition: MachineRegisterInfo.h:944
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Definition: MachineRegisterInfo.h:400
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Definition: LaneBitmask.h:40
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Definition: MachineRegisterInfo.h:384
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Definition: MachineRegisterInfo.h:1213
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Definition: MachineRegisterInfo.h:538
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Constrain the register class or the register bank of the virtual register Reg (and low-level type) to...
Definition: MachineRegisterInfo.cpp:92
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Definition: iterator_range.h:53
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Returns true if liveness for register class RC should be tracked at the subregister level.
Definition: MachineRegisterInfo.h:214
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Definition: MachineRegisterInfo.cpp:146
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Definition: MachineRegisterInfo.cpp:158
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Definition: MachineRegisterInfo.h:428
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Definition: MachineRegisterInfo.h:52
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Definition: MachineRegisterInfo.cpp:122
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This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
Definition: README-SSE.txt:411
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def_bundle_iterator def_bundle_begin(Register RegNo) const
Definition: MachineRegisterInfo.h:413
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void disableCalleeSavedRegister(MCRegister Reg)
Disables the register from the list of CSRs.
Definition: MachineRegisterInfo.cpp:597
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unsigned id() const
Definition: Register.h:111
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iterator_range< reg_bundle_nodbg_iterator > reg_nodbg_bundles(Register Reg) const
Definition: MachineRegisterInfo.h:371
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Definition: MachineRegisterInfo.h:397
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#define op(i)
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This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1167
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bool isInAllocatableClass(MCRegister RegNo) const
Return true if the register is in the allocation of any register class.
Definition: TargetRegisterInfo.h:359
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bool livein_empty() const
Definition: MachineRegisterInfo.h:954
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const TargetRegisterInfo * getTargetRegisterInfo() const
Definition: MachineRegisterInfo.h:153
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Definition: MachineRegisterInfo.h:1178
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MachineInstr * getUniqueVRegDef(Register Reg) const
getUniqueVRegDef - Return the unique machine instr that defines the specified virtual register or nul...
Definition: MachineRegisterInfo.cpp:411
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Definition: MachineRegisterInfo.h:269
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bool canReserveReg(MCRegister PhysReg) const
canReserveReg - Returns true if PhysReg can be used as a reserved register.
Definition: MachineRegisterInfo.h:897
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use_instr_nodbg_iterator use_instr_nodbg_begin(Register RegNo) const
Definition: MachineRegisterInfo.h:535
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Definition: TargetSubtargetInfo.h:124
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Definition: MachineRegisterInfo.h:543
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Definition: TargetRegisterInfo.h:231
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Definition: MachineRegisterInfo.h:1143
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Definition: StringMap.h:205
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The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:46
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Definition: IndexedMap.h:63
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Definition: MachineRegisterInfo.h:485
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Definition: MachineRegisterInfo.h:1146
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Definition: MachineRegisterInfo.h:329
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getLiveInVirtReg - If PReg is a live-in physical register, return the corresponding live-in physical ...
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Definition: MachineRegisterInfo.h:469
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Definition: MachineRegisterInfo.h:757
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Definition: MachineRegisterInfo.h:284
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Definition: MachineRegisterInfo.h:493
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Definition: MachineRegisterInfo.h:269
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Definition: StringMap.h:218
tmp
alloca< 16 x float >, align 16 %tmp2=alloca< 16 x float >, align 16 store< 16 x float > %A,< 16 x float > *%tmp %s=bitcast< 16 x float > *%tmp to i8 *%s2=bitcast< 16 x float > *%tmp2 to i8 *call void @llvm.memcpy.i64(i8 *%s, i8 *%s2, i64 64, i32 16) %R=load< 16 x float > *%tmp2 ret< 16 x float > %R } declare void @llvm.memcpy.i64(i8 *nocapture, i8 *nocapture, i64, i32) nounwind which compiles to:_foo:subl $140, %esp movaps %xmm3, 112(%esp) movaps %xmm2, 96(%esp) movaps %xmm1, 80(%esp) movaps %xmm0, 64(%esp) movl 60(%esp), %eax movl %eax, 124(%esp) movl 56(%esp), %eax movl %eax, 120(%esp) movl 52(%esp), %eax< many many more 32-bit copies > movaps(%esp), %xmm0 movaps 16(%esp), %xmm1 movaps 32(%esp), %xmm2 movaps 48(%esp), %xmm3 addl $140, %esp ret On Nehalem, it may even be cheaper to just use movups when unaligned than to fall back to lower-granularity chunks. Implement processor-specific optimizations for parity with GCC on these processors. GCC does two optimizations:1. ix86_pad_returns inserts a noop before ret instructions if immediately preceded by a conditional branch or is the target of a jump. 2. ix86_avoid_jump_misspredicts inserts noops in cases where a 16-byte block of code contains more than 3 branches. The first one is done for all AMDs, Core2, and "Generic" The second one is done for:Atom, Pentium Pro, all AMDs, Pentium 4, Nocona, Core 2, and "Generic" Testcase:int x(int a) { return(a &0xf0)> >4 tmp
Definition: README.txt:1347
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
llvm::MachineRegisterInfo::setDelegate
void setDelegate(Delegate *delegate)
Definition: MachineRegisterInfo.h:166
llvm::MachineRegisterInfo::defusechain_iterator::getOperandNo
unsigned getOperandNo() const
getOperandNo - Return the operand # of this MachineOperand in its MachineInstr.
Definition: MachineRegisterInfo.h:1071
llvm::MachineRegisterInfo::use_nodbg_begin
use_nodbg_iterator use_nodbg_begin(Register RegNo) const
Definition: MachineRegisterInfo.h:518
llvm::MachineRegisterInfo::defusechain_instr_iterator::operator->
MachineInstr * operator->() const
Definition: MachineRegisterInfo.h:1185
Uses
SmallPtrSet< MachineInstr *, 2 > Uses
Definition: ARMLowOverheadLoops.cpp:583
llvm::MachineRegisterInfo::reg_bundle_iterator
defusechain_instr_iterator< true, true, false, false, false, true > reg_bundle_iterator
reg_bundle_iterator/reg_bundle_begin/reg_bundle_end - Walk all defs and uses of the specified registe...
Definition: MachineRegisterInfo.h:309
llvm::MachineRegisterInfo::tracksLiveness
bool tracksLiveness() const
tracksLiveness - Returns true when tracking register liveness accurately.
Definition: MachineRegisterInfo.h:197
llvm::PSetIterator
Iterate over the pressure sets affected by the given physical or virtual register.
Definition: MachineRegisterInfo.h:1192
llvm::MachineRegisterInfo::reg_nodbg_instructions
iterator_range< reg_instr_nodbg_iterator > reg_nodbg_instructions(Register Reg) const
Definition: MachineRegisterInfo.h:354
llvm::MachineRegisterInfo::defusechain_instr_iterator::atEnd
bool atEnd() const
atEnd - return true if this iterator is equal to reg_end() on the value.
Definition: MachineRegisterInfo.h:1151
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:97
llvm::MachineRegisterInfo::use_nodbg_operands
iterator_range< use_nodbg_iterator > use_nodbg_operands(Register Reg) const
Definition: MachineRegisterInfo.h:526
llvm::RegClassOrRegBank
PointerUnion< const TargetRegisterClass *, const RegisterBank * > RegClassOrRegBank
Convenient type to represent either a register class or a register bank.
Definition: MachineRegisterInfo.h:47
llvm::RegisterBank
This class implements the register bank concept.
Definition: RegisterBank.h:28
llvm::MachineRegisterInfo::setRegClassOrRegBank
void setRegClassOrRegBank(Register Reg, const RegClassOrRegBank &RCOrRB)
Definition: MachineRegisterInfo.h:678
llvm::MachineRegisterInfo::setType
void setType(Register VReg, LLT Ty)
Set the low-level type of VReg to Ty.
Definition: MachineRegisterInfo.cpp:182
llvm::MachineRegisterInfo::Delegate::MRI_NoteNewVirtualRegister
virtual void MRI_NoteNewVirtualRegister(Register Reg)=0
llvm::MachineRegisterInfo::reg_bundle_begin
reg_bundle_iterator reg_bundle_begin(Register RegNo) const
Definition: MachineRegisterInfo.h:310
llvm::IndexedMap::size
StorageT::size_type size() const
Definition: IndexedMap.h:77
llvm::MachineRegisterInfo::reg_nodbg_iterator
defusechain_iterator< true, true, true, true, false, false > reg_nodbg_iterator
reg_nodbg_iterator/reg_nodbg_begin/reg_nodbg_end - Walk all defs and uses of the specified register,...
Definition: MachineRegisterInfo.h:328
llvm::MachineRegisterInfo::isUpdatedCSRsInitialized
bool isUpdatedCSRsInitialized() const
Returns true if the updated CSR list was initialized and false otherwise.
Definition: MachineRegisterInfo.h:230
llvm::MachineRegisterInfo::isReserved
bool isReserved(MCRegister PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.
Definition: MachineRegisterInfo.h:915
llvm::IndexedMap
Definition: IndexedMap.h:29
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::MachineFunction::getProperties
const MachineFunctionProperties & getProperties() const
Get the function properties.
Definition: MachineFunction.h:667
llvm::MachineRegisterInfo::reg_nodbg_operands
iterator_range< reg_nodbg_iterator > reg_nodbg_operands(Register Reg) const
Definition: MachineRegisterInfo.h:337
llvm::MachineRegisterInfo::defusechain_iterator::difference_type
std::ptrdiff_t difference_type
Definition: MachineRegisterInfo.h:994
llvm::MachineRegisterInfo::insertVRegByName
void insertVRegByName(StringRef Name, Register Reg)
Definition: MachineRegisterInfo.h:432
llvm::MachineRegisterInfo::reg_instr_nodbg_end
static reg_instr_nodbg_iterator reg_instr_nodbg_end()
Definition: MachineRegisterInfo.h:349
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:129
llvm::MachineRegisterInfo::reg_iterator
defusechain_iterator< true, true, false, true, false, false > reg_iterator
reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specified register.
Definition: MachineRegisterInfo.h:280
llvm::MachineRegisterInfo::defusechain_iterator::atEnd
bool atEnd() const
atEnd - return true if this iterator is equal to reg_end() on the value.
Definition: MachineRegisterInfo.h:1043
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
llvm::MachineRegisterInfo::reg_instructions
iterator_range< reg_instr_iterator > reg_instructions(Register Reg) const
Definition: MachineRegisterInfo.h:302
llvm::MachineRegisterInfo::setCalleeSavedRegs
void setCalleeSavedRegs(ArrayRef< MCPhysReg > CSRs)
Sets the updated Callee Saved Registers list.
Definition: MachineRegisterInfo.cpp:627
llvm::PSetIterator::getWeight
unsigned getWeight() const
Definition: MachineRegisterInfo.h:1215
MachineInstrBundle.h
llvm::MachineRegisterInfo::use_iterator
defusechain_iterator< true, false, false, true, false, false > use_iterator
use_iterator/use_begin/use_end - Walk all uses of the specified register.
Definition: MachineRegisterInfo.h:463
llvm::MachineRegisterInfo::defusechain_iterator::operator*
MachineOperand & operator*() const
Definition: MachineRegisterInfo.h:1077
llvm::MachineRegisterInfo::def_iterator
defusechain_iterator< false, true, false, true, false, false > def_iterator
def_iterator/def_begin/def_end - Walk all defs of the specified register.
Definition: MachineRegisterInfo.h:383
BitVector.h
llvm::MachineRegisterInfo::use_nodbg_end
static use_nodbg_iterator use_nodbg_end()
Definition: MachineRegisterInfo.h:521
llvm::MachineRegisterInfo::freezeReservedRegs
void freezeReservedRegs(const MachineFunction &)
freezeReservedRegs - Called by the register allocator to freeze the set of reserved registers before ...
Definition: MachineRegisterInfo.cpp:507
llvm::MachineRegisterInfo::operator=
MachineRegisterInfo & operator=(const MachineRegisterInfo &)=delete
llvm::BitVector
Definition: BitVector.h:74
llvm::MachineRegisterInfo::livein_begin
livein_iterator livein_begin() const
Definition: MachineRegisterInfo.h:952
llvm::MachineRegisterInfo::clearVirtRegTypes
void clearVirtRegTypes()
Remove all types associated to virtual registers (after instruction selection and constraining of all...
Definition: MachineRegisterInfo.cpp:199
Register
Promote Memory to Register
Definition: Mem2Reg.cpp:110
llvm::MachineRegisterInfo::reservedRegsFrozen
bool reservedRegsFrozen() const
reservedRegsFrozen - Returns true after freezeReservedRegs() was called to ensure the set of reserved...
Definition: MachineRegisterInfo.h:890
llvm::MachineRegisterInfo::getVRegDef
MachineInstr * getVRegDef(Register Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
Definition: MachineRegisterInfo.cpp:400
llvm::MachineRegisterInfo::use_bundles
iterator_range< use_bundle_iterator > use_bundles(Register Reg) const
Definition: MachineRegisterInfo.h:500
llvm::MachineRegisterInfo::use_empty
bool use_empty(Register RegNo) const
use_empty - Return true if there are no instructions using the specified register.
Definition: MachineRegisterInfo.h:506
llvm::MachineRegisterInfo::reg_instr_end
static reg_instr_iterator reg_instr_end()
Definition: MachineRegisterInfo.h:297
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::MachineRegisterInfo::reg_nodbg_end
static reg_nodbg_iterator reg_nodbg_end()
Definition: MachineRegisterInfo.h:332
llvm::MachineRegisterInfo::defusechain_instr_iterator::defusechain_instr_iterator
defusechain_instr_iterator()=default
llvm::MachineRegisterInfo::def_empty
bool def_empty(Register RegNo) const
def_empty - Return true if there are no instructions defining the specified register (it may be live-...
Definition: MachineRegisterInfo.h:426
llvm::MachineRegisterInfo::reg_instr_iterator
defusechain_instr_iterator< true, true, false, false, true, false > reg_instr_iterator
reg_instr_iterator/reg_instr_begin/reg_instr_end - Walk all defs and uses of the specified register,...
Definition: MachineRegisterInfo.h:293
llvm::MachineRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
Definition: MachineRegisterInfo.h:634
llvm::MachineRegisterInfo::isSSA
bool isSSA() const
Definition: MachineRegisterInfo.h:185
llvm::MachineRegisterInfo::defusechain_instr_iterator
friend class defusechain_instr_iterator
Definition: MachineRegisterInfo.h:275
llvm::Register::isVirtual
bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:91
llvm::MachineRegisterInfo::clearKillFlags
void clearKillFlags(Register Reg) const
clearKillFlags - Iterate over all the uses of the given register and clear the kill flag from the Mac...
Definition: MachineRegisterInfo.cpp:431
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:576
llvm::MachineRegisterInfo::defusechain_instr_iterator::operator++
defusechain_instr_iterator & operator++()
Definition: MachineRegisterInfo.h:1154
llvm::MachineRegisterInfo::verifyUseList
void verifyUseList(Register Reg) const
Verify the sanity of the use list for Reg.
Definition: MachineRegisterInfo.cpp:217
llvm::MachineRegisterInfo::reg_bundles
iterator_range< reg_bundle_iterator > reg_bundles(Register Reg) const
Definition: MachineRegisterInfo.h:317
llvm::PSetIterator::operator++
void operator++()
Definition: MachineRegisterInfo.h:1219
llvm::MachineRegisterInfo::reg_bundle_end
static reg_bundle_iterator reg_bundle_end()
Definition: MachineRegisterInfo.h:313
llvm::MachineFunctionProperties::Property::TracksLiveness
@ TracksLiveness
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::MachineRegisterInfo::setRegBank
void setRegBank(Register Reg, const RegisterBank &RegBank)
Set the register bank to RegBank for Reg.
Definition: MachineRegisterInfo.cpp:63
llvm::MachineRegisterInfo::use_nodbg_iterator
defusechain_iterator< true, false, true, true, false, false > use_nodbg_iterator
use_nodbg_iterator/use_nodbg_begin/use_nodbg_end - Walk all uses of the specified register,...
Definition: MachineRegisterInfo.h:517
llvm::MachineRegisterInfo::use_instr_begin
use_instr_iterator use_instr_begin(Register RegNo) const
Definition: MachineRegisterInfo.h:477
llvm::MachineRegisterInfo::def_bundle_end
static def_bundle_iterator def_bundle_end()
Definition: MachineRegisterInfo.h:416
llvm::PointerUnion::dyn_cast
T dyn_cast() const
Returns the current pointer if it is of the specified pointer type, otherwise returns null.
Definition: PointerUnion.h:194
llvm::MachineRegisterInfo::def_instr_iterator
defusechain_instr_iterator< false, true, false, false, true, false > def_instr_iterator
def_instr_iterator/def_instr_begin/def_instr_end - Walk all defs of the specified register,...
Definition: MachineRegisterInfo.h:396
llvm::MachineRegisterInfo::def_bundles
iterator_range< def_bundle_iterator > def_bundles(Register Reg) const
Definition: MachineRegisterInfo.h:420
llvm::MachineRegisterInfo::getCalleeSavedRegs
const MCPhysReg * getCalleeSavedRegs() const
Returns list of callee saved registers.
Definition: MachineRegisterInfo.cpp:620
llvm::MachineRegisterInfo::def_instructions
iterator_range< def_instr_iterator > def_instructions(Register Reg) const
Definition: MachineRegisterInfo.h:405
llvm::MachineRegisterInfo::reg_instr_nodbg_begin
reg_instr_nodbg_iterator reg_instr_nodbg_begin(Register RegNo) const
Definition: MachineRegisterInfo.h:346
llvm::TargetRegisterClass::HasDisjunctSubRegs
const bool HasDisjunctSubRegs
Whether the class supports two (or more) disjunct subregister indices.
Definition: TargetRegisterInfo.h:61
llvm::MachineRegisterInfo::getLiveInPhysReg
MCRegister getLiveInPhysReg(Register VReg) const
getLiveInPhysReg - If VReg is a live-in virtual register, return the corresponding live-in physical r...
Definition: MachineRegisterInfo.cpp:445
llvm::MachineRegisterInfo::liveins
ArrayRef< std::pair< MCRegister, Register > > liveins() const
Definition: MachineRegisterInfo.h:956
ArrayRef.h
TemplateParamKind::Type
@ Type
llvm::Register::isVirtualRegister
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:71
llvm::MachineRegisterInfo::getRegClassOrNull
const TargetRegisterClass * getRegClassOrNull(Register Reg) const
Return the register class of Reg, or null if Reg has not been assigned a register class yet.
Definition: MachineRegisterInfo.h:651
llvm::MachineRegisterInfo::reg_operands
iterator_range< reg_iterator > reg_operands(Register Reg) const
Definition: MachineRegisterInfo.h:286
llvm::MachineRegisterInfo::isAllocatable
bool isAllocatable(MCRegister PhysReg) const
isAllocatable - Returns true when PhysReg belongs to an allocatable register class and it hasn't been...
Definition: MachineRegisterInfo.h:933
llvm::MachineRegisterInfo::setSimpleHint
void setSimpleHint(Register VReg, Register PrefReg)
Specify the preferred (target independent) register allocation hint for the specified virtual registe...
Definition: MachineRegisterInfo.h:781
llvm::MachineRegisterInfo::getOneDef
MachineOperand * getOneDef(Register Reg) const
Returns the defining operand if there is exactly one operand defining the specified register,...
Definition: MachineRegisterInfo.h:450
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
PointerUnion.h
iterator_range.h
llvm::MachineRegisterInfo::createGenericVirtualRegister
Register createGenericVirtualRegister(LLT Ty, StringRef Name="")
Create and return a new generic virtual register with low-level type Ty.
Definition: MachineRegisterInfo.cpp:188
llvm::MachineRegisterInfo::hasOneDef
bool hasOneDef(Register RegNo) const
Return true if there is exactly one operand defining the specified register.
Definition: MachineRegisterInfo.h:444
llvm::MachineRegisterInfo::def_end
static def_iterator def_end()
Definition: MachineRegisterInfo.h:387
llvm::MachineRegisterInfo::updateDbgUsersToReg
void updateDbgUsersToReg(MCRegister OldReg, MCRegister NewReg, ArrayRef< MachineInstr * > Users) const
updateDbgUsersToReg - Update a collection of DBG_VALUE instructions to refer to the designated regist...
Definition: MachineRegisterInfo.h:826
llvm::MachineRegisterInfo::getRegClassOrRegBank
const RegClassOrRegBank & getRegClassOrRegBank(Register Reg) const
Return the register bank or register class of Reg.
Definition: MachineRegisterInfo.h:668
llvm::MachineFunction
Definition: MachineFunction.h:230
llvm::MachineRegisterInfo::resetDelegate
void resetDelegate(Delegate *delegate)
Definition: MachineRegisterInfo.h:157
llvm::MachineRegisterInfo::use_nodbg_empty
bool use_nodbg_empty(Register RegNo) const
use_nodbg_empty - Return true if there are no non-Debug instructions using the specified register.
Definition: MachineRegisterInfo.h:566
llvm::MCRegister::id
unsigned id() const
Definition: MCRegister.h:71
llvm::hasSingleElement
bool hasSingleElement(ContainerTy &&C)
Returns true if the given container only contains a single element.
Definition: STLExtras.h:259
llvm::StringSet
StringSet - A wrapper for StringMap that provides set-like functionality.
Definition: StringSet.h:22
llvm::MachineRegisterInfo::use_instr_iterator
defusechain_instr_iterator< true, false, false, false, true, false > use_instr_iterator
use_instr_iterator/use_instr_begin/use_instr_end - Walk all uses of the specified register,...
Definition: MachineRegisterInfo.h:476
llvm::IndexedMap::grow
void grow(IndexT n)
Definition: IndexedMap.h:67
llvm::MachineRegisterInfo::Delegate
Definition: MachineRegisterInfo.h:54
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::MachineRegisterInfo::hasOneNonDBGUse
bool hasOneNonDBGUse(Register RegNo) const
hasOneNonDBGUse - Return true if there is exactly one non-Debug use of the specified register.
Definition: MachineRegisterInfo.cpp:419
const_iterator
llvm::MachineRegisterInfo::use_begin
use_iterator use_begin(Register RegNo) const
Definition: MachineRegisterInfo.h:464
llvm::MachineRegisterInfo::setRegAllocationHint
void setRegAllocationHint(Register VReg, unsigned Type, Register PrefReg)
setRegAllocationHint - Specify a register allocation hint for the specified virtual register.
Definition: MachineRegisterInfo.h:765
uint32_t
llvm::getBundleStart
MachineBasicBlock::instr_iterator getBundleStart(MachineBasicBlock::instr_iterator I)
Returns an iterator to the first instruction in the bundle containing I.
Definition: MachineInstrBundle.h:44
llvm::MachineRegisterInfo::invalidateLiveness
void invalidateLiveness()
invalidateLiveness - Indicates that register liveness is no longer being tracked accurately.
Definition: MachineRegisterInfo.h:207
llvm::MachineRegisterInfo::reg_instr_nodbg_iterator
defusechain_instr_iterator< true, true, true, false, true, false > reg_instr_nodbg_iterator
reg_instr_nodbg_iterator/reg_instr_nodbg_begin/reg_instr_nodbg_end - Walk all defs and uses of the sp...
Definition: MachineRegisterInfo.h:345
TargetSubtargetInfo.h
llvm::MachineRegisterInfo::removeRegOperandFromUseList
void removeRegOperandFromUseList(MachineOperand *MO)
Remove MO from its use-def list.
Definition: MachineRegisterInfo.cpp:304
llvm::MachineRegisterInfo::defusechain_iterator::operator!=
bool operator!=(const defusechain_iterator &x) const
Definition: MachineRegisterInfo.h:1038
llvm::SmallSet::insert
std::pair< NoneType, bool > insert(const T &V)
insert - Insert an element into the set if it isn't already there.
Definition: SmallSet.h:180
llvm::MachineFunctionProperties::reset
MachineFunctionProperties & reset(Property P)
Definition: MachineFunction.h:174
llvm::MachineRegisterInfo::getRegAllocationHints
const std::pair< Register, SmallVector< Register, 4 > > & getRegAllocationHints(Register VReg) const
getRegAllocationHints - Return a reference to the vector of all register allocation hints for VReg.
Definition: MachineRegisterInfo.h:814
llvm::MachineRegisterInfo::getReservedRegs
const BitVector & getReservedRegs() const
getReservedRegs - Returns a reference to the frozen set of reserved registers.
Definition: MachineRegisterInfo.h:904
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::PointerUnion
A discriminated union of two or more pointer types, with the discriminator in the low bit of the poin...
Definition: PointerUnion.h:149
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::PSetIterator::PSetIterator
PSetIterator(Register RegUnit, const MachineRegisterInfo *MRI)
Definition: MachineRegisterInfo.h:1199
llvm::MachineRegisterInfo::getUsedPhysRegsMask
const BitVector & getUsedPhysRegsMask() const
Definition: MachineRegisterInfo.h:870
llvm::MachineRegisterInfo::isConstantPhysReg
bool isConstantPhysReg(MCRegister PhysReg) const
Returns true if PhysReg is unallocatable and constant throughout the function.
Definition: MachineRegisterInfo.cpp:513
llvm::MachineRegisterInfo::replaceRegWith
void replaceRegWith(Register FromReg, Register ToReg)
replaceRegWith - Replace all instances of FromReg with ToReg in the machine function.
Definition: MachineRegisterInfo.cpp:380
StringSet.h
llvm::MachineRegisterInfo::def_operands
iterator_range< def_iterator > def_operands(Register Reg) const
Definition: MachineRegisterInfo.h:389
llvm::MachineRegisterInfo::reg_begin
reg_iterator reg_begin(Register RegNo) const
Definition: MachineRegisterInfo.h:281
llvm::BitVector::test
bool test(unsigned Idx) const
Definition: BitVector.h:447
llvm::MachineRegisterInfo::addRegOperandToUseList
void addRegOperandToUseList(MachineOperand *MO)
Add MO to the linked list of operands for its register.
Definition: MachineRegisterInfo.cpp:265
llvm::MachineRegisterInfo::getSimpleHint
Register getSimpleHint(Register VReg) const
getSimpleHint - same as getRegAllocationHint except it will only return a target independent hint.
Definition: MachineRegisterInfo.h:805
llvm::MachineRegisterInfo::isLiveIn
bool isLiveIn(Register Reg) const
Definition: MachineRegisterInfo.cpp:436
llvm::MachineRegisterInfo::getMaxLaneMaskForVReg
LaneBitmask getMaxLaneMaskForVReg(Register Reg) const
Returns a mask covering all bits that can appear in lane masks of subregisters of the virtual registe...
Definition: MachineRegisterInfo.cpp:493
llvm::GraphProgram::Name
Name
Definition: GraphWriter.h:52
uint16_t
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:314
llvm::MachineRegisterInfo::def_bundle_iterator
defusechain_instr_iterator< false, true, false, false, false, true > def_bundle_iterator
def_bundle_iterator/def_bundle_begin/def_bundle_end - Walk all defs of the specified register,...
Definition: MachineRegisterInfo.h:412
llvm::MachineBasicBlock::instr_iterator
Instructions::iterator instr_iterator
Definition: MachineBasicBlock.h:228
llvm::MachineRegisterInfo::livein_iterator
std::vector< std::pair< MCRegister, Register > >::const_iterator livein_iterator
Definition: MachineRegisterInfo.h:951
llvm::MachineRegisterInfo::reg_empty
bool reg_empty(Register RegNo) const
reg_empty - Return true if there are no instructions using or defining the specified register (it may...
Definition: MachineRegisterInfo.h:323
llvm::MachineRegisterInfo::getRegBankOrNull
const RegisterBank * getRegBankOrNull(Register Reg) const
Return the register bank of Reg, or null if Reg has not been assigned a register bank or has been ass...
Definition: MachineRegisterInfo.h:660
x
TODO unsigned x
Definition: README.txt:10
llvm::MachineRegisterInfo::addPhysRegsUsedFromRegMask
void addPhysRegsUsedFromRegMask(const uint32_t *RegMask)
addPhysRegsUsedFromRegMask - Mark any registers not in RegMask as used.
Definition: MachineRegisterInfo.h:866
llvm::MachineRegisterInfo::isPhysRegUsed
bool isPhysRegUsed(MCRegister PhysReg) const
Return true if the specified register is modified or read in this function.
Definition: MachineRegisterInfo.cpp:585
llvm::MachineRegisterInfo::clearVirtRegs
void clearVirtRegs()
clearVirtRegs - Remove all virtual registers (after physreg assignment).
Definition: MachineRegisterInfo.cpp:202
llvm::MachineRegisterInfo::isPhysRegModified
bool isPhysRegModified(MCRegister PhysReg, bool SkipNoReturnDef=false) const
Return true if the specified register is modified in this function.
Definition: MachineRegisterInfo.cpp:570
llvm::MachineRegisterInfo::hasOneNonDBGUser
bool hasOneNonDBGUser(Register RegNo) const
hasOneNonDBGUse - Return true if there is exactly one non-Debug instruction using the specified regis...
Definition: MachineRegisterInfo.cpp:423
llvm::MachineRegisterInfo::use_nodbg_bundles
iterator_range< use_bundle_nodbg_iterator > use_nodbg_bundles(Register Reg) const
Definition: MachineRegisterInfo.h:560
llvm::MachineRegisterInfo::defusechain_iterator::operator++
defusechain_iterator operator++(int)
Definition: MachineRegisterInfo.h:1065
llvm::VRegInfo
Definition: MIParser.h:35
llvm::MachineRegisterInfo::use_bundle_nodbg_end
static use_bundle_nodbg_iterator use_bundle_nodbg_end()
Definition: MachineRegisterInfo.h:555
llvm::MachineRegisterInfo::addRegAllocationHint
void addRegAllocationHint(Register VReg, Register PrefReg)
addRegAllocationHint - Add a register allocation hint to the hints vector for VReg.
Definition: MachineRegisterInfo.h:774
llvm::MCRegUnitIterator
Definition: MCRegisterInfo.h:677
llvm::MachineRegisterInfo::use_bundle_nodbg_iterator
defusechain_instr_iterator< true, false, true, false, false, true > use_bundle_nodbg_iterator
use_bundle_nodbg_iterator/use_bundle_nodbg_begin/use_bundle_nodbg_end - Walk all uses of the specifie...
Definition: MachineRegisterInfo.h:551
llvm::MachineRegisterInfo::defusechain_instr_iterator::difference_type
std::ptrdiff_t difference_type
Definition: MachineRegisterInfo.h:1102
llvm::MachineRegisterInfo::use_end
static use_iterator use_end()
Definition: MachineRegisterInfo.h:467
llvm::MachineRegisterInfo::use_bundle_end
static use_bundle_iterator use_bundle_end()
Definition: MachineRegisterInfo.h:496
llvm::MachineRegisterInfo::reg_bundle_nodbg_begin
reg_bundle_nodbg_iterator reg_bundle_nodbg_begin(Register RegNo) const
Definition: MachineRegisterInfo.h:363
llvm::MachineRegisterInfo::hasOneUse
bool hasOneUse(Register RegNo) const
hasOneUse - Return true if there is exactly one instruction using the specified register.
Definition: MachineRegisterInfo.h:510
SmallVector.h
llvm::PSetIterator::operator*
unsigned operator*() const
Definition: MachineRegisterInfo.h:1217
llvm::MachineRegisterInfo::getType
LLT getType(Register Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register.
Definition: MachineRegisterInfo.h:732
llvm::MachineRegisterInfo::cloneVirtualRegister
Register cloneVirtualRegister(Register VReg, StringRef Name="")
Create and return a new virtual register in the function with the same attributes as the given regist...
Definition: MachineRegisterInfo.cpp:172
RegisterBank.h
llvm::IndexedMap::inBounds
bool inBounds(IndexT n) const
Definition: IndexedMap.h:73
llvm::MCRegisterInfo::DiffListIterator::isValid
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
Definition: MCRegisterInfo.h:224
llvm::MachineRegisterInfo::leaveSSA
void leaveSSA()
Definition: MachineRegisterInfo.h:191
llvm::MachineRegisterInfo::use_bundle_iterator
defusechain_instr_iterator< true, false, false, false, false, true > use_bundle_iterator
use_bundle_iterator/use_bundle_begin/use_bundle_end - Walk all uses of the specified register,...
Definition: MachineRegisterInfo.h:492
LaneBitmask.h
Users
iv Induction Variable Users
Definition: IVUsers.cpp:52
llvm::iterator_range
A range adaptor for a pair of iterators.
Definition: iterator_range.h:30
llvm::MachineRegisterInfo::constrainRegClass
const TargetRegisterClass * constrainRegClass(Register Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
Definition: MachineRegisterInfo.cpp:85
llvm::MachineRegisterInfo::defusechain_iterator
reg_begin/reg_end - Provide iteration support to walk over all definitions and uses of a register wit...
Definition: MachineRegisterInfo.h:266
MachineOperand.h
llvm::MachineRegisterInfo::use_bundle_nodbg_begin
use_bundle_nodbg_iterator use_bundle_nodbg_begin(Register RegNo) const
Definition: MachineRegisterInfo.h:552
llvm::MachineRegisterInfo::MachineRegisterInfo
MachineRegisterInfo(MachineFunction *MF)
Definition: MachineRegisterInfo.cpp:44
llvm::MachineRegisterInfo::reg_bundle_nodbg_iterator
defusechain_instr_iterator< true, true, true, false, false, true > reg_bundle_nodbg_iterator
reg_bundle_nodbg_iterator/reg_bundle_nodbg_begin/reg_bundle_nodbg_end - Walk all defs and uses of the...
Definition: MachineRegisterInfo.h:362
llvm::MachineRegisterInfo::shouldTrackSubRegLiveness
bool shouldTrackSubRegLiveness(Register VReg) const
Definition: MachineRegisterInfo.h:217
llvm::MachineRegisterInfo::isReservedRegUnit
bool isReservedRegUnit(unsigned Unit) const
Returns true when the given register unit is considered reserved.
Definition: MachineRegisterInfo.cpp:639
llvm::MachineRegisterInfo::clearSimpleHint
void clearSimpleHint(Register VReg)
Definition: MachineRegisterInfo.h:785
llvm::MachineRegisterInfo::reg_nodbg_empty
bool reg_nodbg_empty(Register RegNo) const
reg_nodbg_empty - Return true if the only instructions using or defining Reg are Debug instructions.
Definition: MachineRegisterInfo.h:377
MachineFunction.h
llvm::MachineRegisterInfo::defusechain_iterator::defusechain_iterator
defusechain_iterator()=default
llvm::MachineRegisterInfo::getPressureSets
PSetIterator getPressureSets(Register RegUnit) const
Get an iterator over the pressure sets affected by the given physical or virtual register.
Definition: MachineRegisterInfo.h:1228
llvm::MachineRegisterInfo::defusechain_instr_iterator::iterator_category
std::forward_iterator_tag iterator_category
Definition: MachineRegisterInfo.h:1100
llvm::MachineRegisterInfo::dumpUses
void dumpUses(Register RegNo) const
Definition: MachineRegisterInfo.cpp:501
llvm::MachineRegisterInfo::livein_end
livein_iterator livein_end() const
Definition: MachineRegisterInfo.h:953
llvm::MachineRegisterInfo::moveOperands
void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps)
Move NumOps operands from Src to Dst, updating use-def lists as needed.
Definition: MachineRegisterInfo.cpp:333
llvm::MachineRegisterInfo::reg_bundle_nodbg_end
static reg_bundle_nodbg_iterator reg_bundle_nodbg_end()
Definition: MachineRegisterInfo.h:366
llvm::MachineRegisterInfo::use_instr_end
static use_instr_iterator use_instr_end()
Definition: MachineRegisterInfo.h:480
TargetRegisterInfo.h
llvm::MachineRegisterInfo::EmitLiveInCopies
void EmitLiveInCopies(MachineBasicBlock *EntryMBB, const TargetRegisterInfo &TRI, const TargetInstrInfo &TII)
EmitLiveInCopies - Emit copies to initialize livein virtual registers into the given entry block.
Definition: MachineRegisterInfo.cpp:464
llvm::MachineRegisterInfo::setRegClass
void setRegClass(Register Reg, const TargetRegisterClass *RC)
setRegClass - Set the register class of the specified virtual register.
Definition: MachineRegisterInfo.cpp:58
llvm::SmallSet::contains
bool contains(const T &V) const
Check if the SmallSet contains the given element.
Definition: SmallSet.h:236
llvm::MachineRegisterInfo::getRegAllocationHint
std::pair< Register, Register > getRegAllocationHint(Register VReg) const
getRegAllocationHint - Return the register allocation hint for the specified virtual register.
Definition: MachineRegisterInfo.h:795
llvm::MachineRegisterInfo::verifyUseLists
void verifyUseLists() const
Verify the use list of all registers.
Definition: MachineRegisterInfo.cpp:255
llvm::MachineRegisterInfo::use_instr_nodbg_iterator
defusechain_instr_iterator< true, false, true, false, true, false > use_instr_nodbg_iterator
use_instr_nodbg_iterator/use_instr_nodbg_begin/use_instr_nodbg_end - Walk all uses of the specified r...
Definition: MachineRegisterInfo.h:534
llvm::MachineRegisterInfo::Delegate::~Delegate
virtual ~Delegate()=default
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:23
llvm::MachineRegisterInfo::defusechain_iterator::operator++
defusechain_iterator & operator++()
Definition: MachineRegisterInfo.h:1046
llvm::LLT
Definition: LowLevelTypeImpl.h:40