LLVM  17.0.0git
MachineRegisterInfo.h
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1 //===- llvm/CodeGen/MachineRegisterInfo.h -----------------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the MachineRegisterInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_CODEGEN_MACHINEREGISTERINFO_H
14 #define LLVM_CODEGEN_MACHINEREGISTERINFO_H
15 
16 #include "llvm/ADT/ArrayRef.h"
17 #include "llvm/ADT/BitVector.h"
18 #include "llvm/ADT/IndexedMap.h"
19 #include "llvm/ADT/PointerUnion.h"
20 #include "llvm/ADT/SmallPtrSet.h"
21 #include "llvm/ADT/SmallVector.h"
22 #include "llvm/ADT/StringSet.h"
31 #include "llvm/MC/LaneBitmask.h"
32 #include <cassert>
33 #include <cstddef>
34 #include <cstdint>
35 #include <iterator>
36 #include <memory>
37 #include <utility>
38 #include <vector>
39 
40 namespace llvm {
41 
42 class PSetIterator;
43 
44 /// Convenient type to represent either a register class or a register bank.
45 using RegClassOrRegBank =
47 
48 /// MachineRegisterInfo - Keep track of information for virtual and physical
49 /// registers, including vreg register classes, use/def chains for registers,
50 /// etc.
52 public:
53  class Delegate {
54  virtual void anchor();
55 
56  public:
57  virtual ~Delegate() = default;
58 
59  virtual void MRI_NoteNewVirtualRegister(Register Reg) = 0;
61  Register SrcReg) {
63  }
64  };
65 
66 private:
67  MachineFunction *MF;
68  SmallPtrSet<Delegate *, 1> TheDelegates;
69 
70  /// True if subregister liveness is tracked.
71  const bool TracksSubRegLiveness;
72 
73  /// VRegInfo - Information we keep for each virtual register.
74  ///
75  /// Each element in this list contains the register class of the vreg and the
76  /// start of the use/def list for the register.
79  VRegInfo;
80 
81  /// Map for recovering vreg name from vreg number.
82  /// This map is used by the MIR Printer.
84 
85  /// StringSet that is used to unique vreg names.
86  StringSet<> VRegNames;
87 
88  /// The flag is true upon \p UpdatedCSRs initialization
89  /// and false otherwise.
90  bool IsUpdatedCSRsInitialized = false;
91 
92  /// Contains the updated callee saved register list.
93  /// As opposed to the static list defined in register info,
94  /// all registers that were disabled are removed from the list.
95  SmallVector<MCPhysReg, 16> UpdatedCSRs;
96 
97  /// RegAllocHints - This vector records register allocation hints for
98  /// virtual registers. For each virtual register, it keeps a pair of hint
99  /// type and hints vector making up the allocation hints. Only the first
100  /// hint may be target specific, and in that case this is reflected by the
101  /// first member of the pair being non-zero. If the hinted register is
102  /// virtual, it means the allocator should prefer the physical register
103  /// allocated to it if any.
105  VirtReg2IndexFunctor> RegAllocHints;
106 
107  /// PhysRegUseDefLists - This is an array of the head of the use/def list for
108  /// physical registers.
109  std::unique_ptr<MachineOperand *[]> PhysRegUseDefLists;
110 
111  /// getRegUseDefListHead - Return the head pointer for the register use/def
112  /// list for the specified virtual or physical register.
113  MachineOperand *&getRegUseDefListHead(Register RegNo) {
114  if (RegNo.isVirtual())
115  return VRegInfo[RegNo.id()].second;
116  return PhysRegUseDefLists[RegNo.id()];
117  }
118 
119  MachineOperand *getRegUseDefListHead(Register RegNo) const {
120  if (RegNo.isVirtual())
121  return VRegInfo[RegNo.id()].second;
122  return PhysRegUseDefLists[RegNo.id()];
123  }
124 
125  /// Get the next element in the use-def chain.
126  static MachineOperand *getNextOperandForReg(const MachineOperand *MO) {
127  assert(MO && MO->isReg() && "This is not a register operand!");
128  return MO->Contents.Reg.Next;
129  }
130 
131  /// UsedPhysRegMask - Additional used physregs including aliases.
132  /// This bit vector represents all the registers clobbered by function calls.
133  BitVector UsedPhysRegMask;
134 
135  /// ReservedRegs - This is a bit vector of reserved registers. The target
136  /// may change its mind about which registers should be reserved. This
137  /// vector is the frozen set of reserved registers when register allocation
138  /// started.
139  BitVector ReservedRegs;
140 
141  using VRegToTypeMap = IndexedMap<LLT, VirtReg2IndexFunctor>;
142  /// Map generic virtual registers to their low-level type.
143  VRegToTypeMap VRegToType;
144 
145  /// Keep track of the physical registers that are live in to the function.
146  /// Live in values are typically arguments in registers. LiveIn values are
147  /// allowed to have virtual registers associated with them, stored in the
148  /// second element.
149  std::vector<std::pair<MCRegister, Register>> LiveIns;
150 
151 public:
152  explicit MachineRegisterInfo(MachineFunction *MF);
153  MachineRegisterInfo(const MachineRegisterInfo &) = delete;
155 
157  return MF->getSubtarget().getRegisterInfo();
158  }
159 
160  void resetDelegate(Delegate *delegate) {
161  // Ensure another delegate does not take over unless the current
162  // delegate first unattaches itself.
163  assert(TheDelegates.count(delegate) &&
164  "Only an existing delegate can perform reset!");
165  TheDelegates.erase(delegate);
166  }
167 
168  void addDelegate(Delegate *delegate) {
169  assert(delegate && !TheDelegates.count(delegate) &&
170  "Attempted to add null delegate, or to change it without "
171  "first resetting it!");
172 
173  TheDelegates.insert(delegate);
174  }
175 
177  for (auto *TheDelegate : TheDelegates)
178  TheDelegate->MRI_NoteNewVirtualRegister(Reg);
179  }
180 
182  for (auto *TheDelegate : TheDelegates)
183  TheDelegate->MRI_NotecloneVirtualRegister(NewReg, SrcReg);
184  }
185 
186  //===--------------------------------------------------------------------===//
187  // Function State
188  //===--------------------------------------------------------------------===//
189 
190  // isSSA - Returns true when the machine function is in SSA form. Early
191  // passes require the machine function to be in SSA form where every virtual
192  // register has a single defining instruction.
193  //
194  // The TwoAddressInstructionPass and PHIElimination passes take the machine
195  // function out of SSA form when they introduce multiple defs per virtual
196  // register.
197  bool isSSA() const {
198  return MF->getProperties().hasProperty(
200  }
201 
202  // leaveSSA - Indicates that the machine function is no longer in SSA form.
203  void leaveSSA() {
205  }
206 
207  /// tracksLiveness - Returns true when tracking register liveness accurately.
208  /// (see MachineFUnctionProperties::Property description for details)
209  bool tracksLiveness() const {
210  return MF->getProperties().hasProperty(
212  }
213 
214  /// invalidateLiveness - Indicates that register liveness is no longer being
215  /// tracked accurately.
216  ///
217  /// This should be called by late passes that invalidate the liveness
218  /// information.
220  MF->getProperties().reset(
222  }
223 
224  /// Returns true if liveness for register class @p RC should be tracked at
225  /// the subregister level.
228  }
230  assert(VReg.isVirtual() && "Must pass a VReg");
231  return shouldTrackSubRegLiveness(*getRegClass(VReg));
232  }
233  bool subRegLivenessEnabled() const {
234  return TracksSubRegLiveness;
235  }
236 
237  //===--------------------------------------------------------------------===//
238  // Register Info
239  //===--------------------------------------------------------------------===//
240 
241  /// Returns true if the updated CSR list was initialized and false otherwise.
242  bool isUpdatedCSRsInitialized() const { return IsUpdatedCSRsInitialized; }
243 
244  /// Returns true if a register can be used as an argument to a function.
245  bool isArgumentRegister(const MachineFunction &MF, MCRegister Reg) const;
246 
247  /// Returns true if a register is a fixed register.
248  bool isFixedRegister(const MachineFunction &MF, MCRegister Reg) const;
249 
250  /// Returns true if a register is a general purpose register.
252  MCRegister Reg) const;
253 
254  /// Disables the register from the list of CSRs.
255  /// I.e. the register will not appear as part of the CSR mask.
256  /// \see UpdatedCalleeSavedRegs.
258 
259  /// Returns list of callee saved registers.
260  /// The function returns the updated CSR list (after taking into account
261  /// registers that are disabled from the CSR list).
262  const MCPhysReg *getCalleeSavedRegs() const;
263 
264  /// Sets the updated Callee Saved Registers list.
265  /// Notice that it will override ant previously disabled/saved CSRs.
267 
268  // Strictly for use by MachineInstr.cpp.
270 
271  // Strictly for use by MachineInstr.cpp.
273 
274  // Strictly for use by MachineInstr.cpp.
275  void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps);
276 
277  /// Verify the sanity of the use list for Reg.
278  void verifyUseList(Register Reg) const;
279 
280  /// Verify the use list of all registers.
281  void verifyUseLists() const;
282 
283  /// reg_begin/reg_end - Provide iteration support to walk over all definitions
284  /// and uses of a register within the MachineFunction that corresponds to this
285  /// MachineRegisterInfo object.
286  template<bool Uses, bool Defs, bool SkipDebug,
287  bool ByOperand, bool ByInstr, bool ByBundle>
289  template<bool Uses, bool Defs, bool SkipDebug,
290  bool ByOperand, bool ByInstr, bool ByBundle>
292 
293  // Make it a friend so it can access getNextOperandForReg().
294  template<bool, bool, bool, bool, bool, bool>
295  friend class defusechain_iterator;
296  template<bool, bool, bool, bool, bool, bool>
298 
299  /// reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specified
300  /// register.
301  using reg_iterator =
304  return reg_iterator(getRegUseDefListHead(RegNo));
305  }
306  static reg_iterator reg_end() { return reg_iterator(nullptr); }
307 
309  return make_range(reg_begin(Reg), reg_end());
310  }
311 
312  /// reg_instr_iterator/reg_instr_begin/reg_instr_end - Walk all defs and uses
313  /// of the specified register, stepping by MachineInstr.
314  using reg_instr_iterator =
317  return reg_instr_iterator(getRegUseDefListHead(RegNo));
318  }
320  return reg_instr_iterator(nullptr);
321  }
322 
326  }
327 
328  /// reg_bundle_iterator/reg_bundle_begin/reg_bundle_end - Walk all defs and uses
329  /// of the specified register, stepping by bundle.
330  using reg_bundle_iterator =
333  return reg_bundle_iterator(getRegUseDefListHead(RegNo));
334  }
336  return reg_bundle_iterator(nullptr);
337  }
338 
341  }
342 
343  /// reg_empty - Return true if there are no instructions using or defining the
344  /// specified register (it may be live-in).
345  bool reg_empty(Register RegNo) const { return reg_begin(RegNo) == reg_end(); }
346 
347  /// reg_nodbg_iterator/reg_nodbg_begin/reg_nodbg_end - Walk all defs and uses
348  /// of the specified register, skipping those marked as Debug.
349  using reg_nodbg_iterator =
352  return reg_nodbg_iterator(getRegUseDefListHead(RegNo));
353  }
355  return reg_nodbg_iterator(nullptr);
356  }
357 
361  }
362 
363  /// reg_instr_nodbg_iterator/reg_instr_nodbg_begin/reg_instr_nodbg_end - Walk
364  /// all defs and uses of the specified register, stepping by MachineInstr,
365  /// skipping those marked as Debug.
369  return reg_instr_nodbg_iterator(getRegUseDefListHead(RegNo));
370  }
372  return reg_instr_nodbg_iterator(nullptr);
373  }
374 
378  }
379 
380  /// reg_bundle_nodbg_iterator/reg_bundle_nodbg_begin/reg_bundle_nodbg_end - Walk
381  /// all defs and uses of the specified register, stepping by bundle,
382  /// skipping those marked as Debug.
386  return reg_bundle_nodbg_iterator(getRegUseDefListHead(RegNo));
387  }
389  return reg_bundle_nodbg_iterator(nullptr);
390  }
391 
395  }
396 
397  /// reg_nodbg_empty - Return true if the only instructions using or defining
398  /// Reg are Debug instructions.
399  bool reg_nodbg_empty(Register RegNo) const {
400  return reg_nodbg_begin(RegNo) == reg_nodbg_end();
401  }
402 
403  /// def_iterator/def_begin/def_end - Walk all defs of the specified register.
404  using def_iterator =
407  return def_iterator(getRegUseDefListHead(RegNo));
408  }
409  static def_iterator def_end() { return def_iterator(nullptr); }
410 
412  return make_range(def_begin(Reg), def_end());
413  }
414 
415  /// def_instr_iterator/def_instr_begin/def_instr_end - Walk all defs of the
416  /// specified register, stepping by MachineInst.
417  using def_instr_iterator =
420  return def_instr_iterator(getRegUseDefListHead(RegNo));
421  }
423  return def_instr_iterator(nullptr);
424  }
425 
429  }
430 
431  /// def_bundle_iterator/def_bundle_begin/def_bundle_end - Walk all defs of the
432  /// specified register, stepping by bundle.
433  using def_bundle_iterator =
436  return def_bundle_iterator(getRegUseDefListHead(RegNo));
437  }
439  return def_bundle_iterator(nullptr);
440  }
441 
444  }
445 
446  /// def_empty - Return true if there are no instructions defining the
447  /// specified register (it may be live-in).
448  bool def_empty(Register RegNo) const { return def_begin(RegNo) == def_end(); }
449 
451  return VReg2Name.inBounds(Reg) ? StringRef(VReg2Name[Reg]) : "";
452  }
453 
455  assert((Name.empty() || VRegNames.find(Name) == VRegNames.end()) &&
456  "Named VRegs Must be Unique.");
457  if (!Name.empty()) {
458  VRegNames.insert(Name);
459  VReg2Name.grow(Reg);
460  VReg2Name[Reg] = Name.str();
461  }
462  }
463 
464  /// Return true if there is exactly one operand defining the specified
465  /// register.
466  bool hasOneDef(Register RegNo) const {
467  return hasSingleElement(def_operands(RegNo));
468  }
469 
470  /// Returns the defining operand if there is exactly one operand defining the
471  /// specified register, otherwise nullptr.
473  def_iterator DI = def_begin(Reg);
474  if (DI == def_end()) // No defs.
475  return nullptr;
476 
477  def_iterator OneDef = DI;
478  if (++DI == def_end())
479  return &*OneDef;
480  return nullptr; // Multiple defs.
481  }
482 
483  /// use_iterator/use_begin/use_end - Walk all uses of the specified register.
484  using use_iterator =
487  return use_iterator(getRegUseDefListHead(RegNo));
488  }
489  static use_iterator use_end() { return use_iterator(nullptr); }
490 
492  return make_range(use_begin(Reg), use_end());
493  }
494 
495  /// use_instr_iterator/use_instr_begin/use_instr_end - Walk all uses of the
496  /// specified register, stepping by MachineInstr.
497  using use_instr_iterator =
500  return use_instr_iterator(getRegUseDefListHead(RegNo));
501  }
503  return use_instr_iterator(nullptr);
504  }
505 
509  }
510 
511  /// use_bundle_iterator/use_bundle_begin/use_bundle_end - Walk all uses of the
512  /// specified register, stepping by bundle.
513  using use_bundle_iterator =
516  return use_bundle_iterator(getRegUseDefListHead(RegNo));
517  }
519  return use_bundle_iterator(nullptr);
520  }
521 
524  }
525 
526  /// use_empty - Return true if there are no instructions using the specified
527  /// register.
528  bool use_empty(Register RegNo) const { return use_begin(RegNo) == use_end(); }
529 
530  /// hasOneUse - Return true if there is exactly one instruction using the
531  /// specified register.
532  bool hasOneUse(Register RegNo) const {
533  return hasSingleElement(use_operands(RegNo));
534  }
535 
536  /// use_nodbg_iterator/use_nodbg_begin/use_nodbg_end - Walk all uses of the
537  /// specified register, skipping those marked as Debug.
538  using use_nodbg_iterator =
541  return use_nodbg_iterator(getRegUseDefListHead(RegNo));
542  }
544  return use_nodbg_iterator(nullptr);
545  }
546 
550  }
551 
552  /// use_instr_nodbg_iterator/use_instr_nodbg_begin/use_instr_nodbg_end - Walk
553  /// all uses of the specified register, stepping by MachineInstr, skipping
554  /// those marked as Debug.
558  return use_instr_nodbg_iterator(getRegUseDefListHead(RegNo));
559  }
561  return use_instr_nodbg_iterator(nullptr);
562  }
563 
567  }
568 
569  /// use_bundle_nodbg_iterator/use_bundle_nodbg_begin/use_bundle_nodbg_end - Walk
570  /// all uses of the specified register, stepping by bundle, skipping
571  /// those marked as Debug.
575  return use_bundle_nodbg_iterator(getRegUseDefListHead(RegNo));
576  }
578  return use_bundle_nodbg_iterator(nullptr);
579  }
580 
584  }
585 
586  /// use_nodbg_empty - Return true if there are no non-Debug instructions
587  /// using the specified register.
588  bool use_nodbg_empty(Register RegNo) const {
589  return use_nodbg_begin(RegNo) == use_nodbg_end();
590  }
591 
592  /// hasOneNonDBGUse - Return true if there is exactly one non-Debug
593  /// use of the specified register.
594  bool hasOneNonDBGUse(Register RegNo) const;
595 
596  /// hasOneNonDBGUse - Return true if there is exactly one non-Debug
597  /// instruction using the specified register. Said instruction may have
598  /// multiple uses.
599  bool hasOneNonDBGUser(Register RegNo) const;
600 
601 
602  /// hasAtMostUses - Return true if the given register has at most \p MaxUsers
603  /// non-debug user instructions.
604  bool hasAtMostUserInstrs(Register Reg, unsigned MaxUsers) const;
605 
606  /// replaceRegWith - Replace all instances of FromReg with ToReg in the
607  /// machine function. This is like llvm-level X->replaceAllUsesWith(Y),
608  /// except that it also changes any definitions of the register as well.
609  ///
610  /// Note that it is usually necessary to first constrain ToReg's register
611  /// class and register bank to match the FromReg constraints using one of the
612  /// methods:
613  ///
614  /// constrainRegClass(ToReg, getRegClass(FromReg))
615  /// constrainRegAttrs(ToReg, FromReg)
616  /// RegisterBankInfo::constrainGenericRegister(ToReg,
617  /// *MRI.getRegClass(FromReg), MRI)
618  ///
619  /// These functions will return a falsy result if the virtual registers have
620  /// incompatible constraints.
621  ///
622  /// Note that if ToReg is a physical register the function will replace and
623  /// apply sub registers to ToReg in order to obtain a final/proper physical
624  /// register.
625  void replaceRegWith(Register FromReg, Register ToReg);
626 
627  /// getVRegDef - Return the machine instr that defines the specified virtual
628  /// register or null if none is found. This assumes that the code is in SSA
629  /// form, so there should only be one definition.
631 
632  /// getUniqueVRegDef - Return the unique machine instr that defines the
633  /// specified virtual register or null if none is found. If there are
634  /// multiple definitions or no definition, return null.
636 
637  /// clearKillFlags - Iterate over all the uses of the given register and
638  /// clear the kill flag from the MachineOperand. This function is used by
639  /// optimization passes which extend register lifetimes and need only
640  /// preserve conservative kill flag information.
641  void clearKillFlags(Register Reg) const;
642 
643  void dumpUses(Register RegNo) const;
644 
645  /// Returns true if PhysReg is unallocatable and constant throughout the
646  /// function. Writing to a constant register has no effect.
647  bool isConstantPhysReg(MCRegister PhysReg) const;
648 
649  /// Get an iterator over the pressure sets affected by the given physical or
650  /// virtual register. If RegUnit is physical, it must be a register unit (from
651  /// MCRegUnitIterator).
652  PSetIterator getPressureSets(Register RegUnit) const;
653 
654  //===--------------------------------------------------------------------===//
655  // Virtual Register Info
656  //===--------------------------------------------------------------------===//
657 
658  /// Return the register class of the specified virtual register.
659  /// This shouldn't be used directly unless \p Reg has a register class.
660  /// \see getRegClassOrNull when this might happen.
662  assert(VRegInfo[Reg.id()].first.is<const TargetRegisterClass *>() &&
663  "Register class not set, wrong accessor");
664  return VRegInfo[Reg.id()].first.get<const TargetRegisterClass *>();
665  }
666 
667  /// Return the register class of \p Reg, or null if Reg has not been assigned
668  /// a register class yet.
669  ///
670  /// \note A null register class can only happen when these two
671  /// conditions are met:
672  /// 1. Generic virtual registers are created.
673  /// 2. The machine function has not completely been through the
674  /// instruction selection process.
675  /// None of this condition is possible without GlobalISel for now.
676  /// In other words, if GlobalISel is not used or if the query happens after
677  /// the select pass, using getRegClass is safe.
679  const RegClassOrRegBank &Val = VRegInfo[Reg].first;
680  return Val.dyn_cast<const TargetRegisterClass *>();
681  }
682 
683  /// Return the register bank of \p Reg, or null if Reg has not been assigned
684  /// a register bank or has been assigned a register class.
685  /// \note It is possible to get the register bank from the register class via
686  /// RegisterBankInfo::getRegBankFromRegClass.
688  const RegClassOrRegBank &Val = VRegInfo[Reg].first;
689  return Val.dyn_cast<const RegisterBank *>();
690  }
691 
692  /// Return the register bank or register class of \p Reg.
693  /// \note Before the register bank gets assigned (i.e., before the
694  /// RegBankSelect pass) \p Reg may not have either.
696  return VRegInfo[Reg].first;
697  }
698 
699  /// setRegClass - Set the register class of the specified virtual register.
700  void setRegClass(Register Reg, const TargetRegisterClass *RC);
701 
702  /// Set the register bank to \p RegBank for \p Reg.
703  void setRegBank(Register Reg, const RegisterBank &RegBank);
704 
706  const RegClassOrRegBank &RCOrRB){
707  VRegInfo[Reg].first = RCOrRB;
708  }
709 
710  /// constrainRegClass - Constrain the register class of the specified virtual
711  /// register to be a common subclass of RC and the current register class,
712  /// but only if the new class has at least MinNumRegs registers. Return the
713  /// new register class, or NULL if no such class exists.
714  /// This should only be used when the constraint is known to be trivial, like
715  /// GR32 -> GR32_NOSP. Beware of increasing register pressure.
716  ///
717  /// \note Assumes that the register has a register class assigned.
718  /// Use RegisterBankInfo::constrainGenericRegister in GlobalISel's
719  /// InstructionSelect pass and constrainRegAttrs in every other pass,
720  /// including non-select passes of GlobalISel, instead.
722  const TargetRegisterClass *RC,
723  unsigned MinNumRegs = 0);
724 
725  /// Constrain the register class or the register bank of the virtual register
726  /// \p Reg (and low-level type) to be a common subclass or a common bank of
727  /// both registers provided respectively (and a common low-level type). Do
728  /// nothing if any of the attributes (classes, banks, or low-level types) of
729  /// the registers are deemed incompatible, or if the resulting register will
730  /// have a class smaller than before and of size less than \p MinNumRegs.
731  /// Return true if such register attributes exist, false otherwise.
732  ///
733  /// \note Use this method instead of constrainRegClass and
734  /// RegisterBankInfo::constrainGenericRegister everywhere but SelectionDAG
735  /// ISel / FastISel and GlobalISel's InstructionSelect pass respectively.
736  bool constrainRegAttrs(Register Reg, Register ConstrainingReg,
737  unsigned MinNumRegs = 0);
738 
739  /// recomputeRegClass - Try to find a legal super-class of Reg's register
740  /// class that still satisfies the constraints from the instructions using
741  /// Reg. Returns true if Reg was upgraded.
742  ///
743  /// This method can be used after constraints have been removed from a
744  /// virtual register, for example after removing instructions or splitting
745  /// the live range.
747 
748  /// createVirtualRegister - Create and return a new virtual register in the
749  /// function with the specified register class.
751  StringRef Name = "");
752 
753  /// Create and return a new virtual register in the function with the same
754  /// attributes as the given register.
756 
757  /// Get the low-level type of \p Reg or LLT{} if Reg is not a generic
758  /// (target independent) virtual register.
760  if (Reg.isVirtual() && VRegToType.inBounds(Reg))
761  return VRegToType[Reg];
762  return LLT{};
763  }
764 
765  /// Set the low-level type of \p VReg to \p Ty.
766  void setType(Register VReg, LLT Ty);
767 
768  /// Create and return a new generic virtual register with low-level
769  /// type \p Ty.
771 
772  /// Remove all types associated to virtual registers (after instruction
773  /// selection and constraining of all generic virtual registers).
774  void clearVirtRegTypes();
775 
776  /// Creates a new virtual register that has no register class, register bank
777  /// or size assigned yet. This is only allowed to be used
778  /// temporarily while constructing machine instructions. Most operations are
779  /// undefined on an incomplete register until one of setRegClass(),
780  /// setRegBank() or setSize() has been called on it.
782 
783  /// getNumVirtRegs - Return the number of virtual registers created.
784  unsigned getNumVirtRegs() const { return VRegInfo.size(); }
785 
786  /// clearVirtRegs - Remove all virtual registers (after physreg assignment).
787  void clearVirtRegs();
788 
789  /// setRegAllocationHint - Specify a register allocation hint for the
790  /// specified virtual register. This is typically used by target, and in case
791  /// of an earlier hint it will be overwritten.
792  void setRegAllocationHint(Register VReg, unsigned Type, Register PrefReg) {
793  assert(VReg.isVirtual());
794  RegAllocHints[VReg].first = Type;
795  RegAllocHints[VReg].second.clear();
796  RegAllocHints[VReg].second.push_back(PrefReg);
797  }
798 
799  /// addRegAllocationHint - Add a register allocation hint to the hints
800  /// vector for VReg.
801  void addRegAllocationHint(Register VReg, Register PrefReg) {
802  assert(VReg.isVirtual());
803  RegAllocHints[VReg].second.push_back(PrefReg);
804  }
805 
806  /// Specify the preferred (target independent) register allocation hint for
807  /// the specified virtual register.
808  void setSimpleHint(Register VReg, Register PrefReg) {
809  setRegAllocationHint(VReg, /*Type=*/0, PrefReg);
810  }
811 
813  assert (!RegAllocHints[VReg].first &&
814  "Expected to clear a non-target hint!");
815  RegAllocHints[VReg].second.clear();
816  }
817 
818  /// getRegAllocationHint - Return the register allocation hint for the
819  /// specified virtual register. If there are many hints, this returns the
820  /// one with the greatest weight.
821  std::pair<Register, Register>
823  assert(VReg.isVirtual());
824  Register BestHint = (RegAllocHints[VReg.id()].second.size() ?
825  RegAllocHints[VReg.id()].second[0] : Register());
826  return std::pair<Register, Register>(RegAllocHints[VReg.id()].first,
827  BestHint);
828  }
829 
830  /// getSimpleHint - same as getRegAllocationHint except it will only return
831  /// a target independent hint.
833  assert(VReg.isVirtual());
834  std::pair<Register, Register> Hint = getRegAllocationHint(VReg);
835  return Hint.first ? Register() : Hint.second;
836  }
837 
838  /// getRegAllocationHints - Return a reference to the vector of all
839  /// register allocation hints for VReg.
840  const std::pair<Register, SmallVector<Register, 4>>
842  assert(VReg.isVirtual());
843  return RegAllocHints[VReg];
844  }
845 
846  /// markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the
847  /// specified register as undefined which causes the DBG_VALUE to be
848  /// deleted during LiveDebugVariables analysis.
850 
851  /// updateDbgUsersToReg - Update a collection of debug instructions
852  /// to refer to the designated register.
855  // If this operand is a register, check whether it overlaps with OldReg.
856  // If it does, replace with NewReg.
857  auto UpdateOp = [this, &NewReg, &OldReg](MachineOperand &Op) {
858  if (Op.isReg() &&
859  getTargetRegisterInfo()->regsOverlap(Op.getReg(), OldReg))
860  Op.setReg(NewReg);
861  };
862 
863  // Iterate through (possibly several) operands to DBG_VALUEs and update
864  // each. For DBG_PHIs, only one operand will be present.
865  for (MachineInstr *MI : Users) {
866  if (MI->isDebugValue()) {
867  for (auto &Op : MI->debug_operands())
868  UpdateOp(Op);
869  assert(MI->hasDebugOperandForReg(NewReg) &&
870  "Expected debug value to have some overlap with OldReg");
871  } else if (MI->isDebugPHI()) {
872  UpdateOp(MI->getOperand(0));
873  } else {
874  llvm_unreachable("Non-DBG_VALUE, Non-DBG_PHI debug instr updated");
875  }
876  }
877  }
878 
879  /// Return true if the specified register is modified in this function.
880  /// This checks that no defining machine operands exist for the register or
881  /// any of its aliases. Definitions found on functions marked noreturn are
882  /// ignored, to consider them pass 'true' for optional parameter
883  /// SkipNoReturnDef. The register is also considered modified when it is set
884  /// in the UsedPhysRegMask.
885  bool isPhysRegModified(MCRegister PhysReg, bool SkipNoReturnDef = false) const;
886 
887  /// Return true if the specified register is modified or read in this
888  /// function. This checks that no machine operands exist for the register or
889  /// any of its aliases. If SkipRegMaskTest is false, the register is
890  /// considered used when it is set in the UsedPhysRegMask.
891  bool isPhysRegUsed(MCRegister PhysReg, bool SkipRegMaskTest = false) const;
892 
893  /// addPhysRegsUsedFromRegMask - Mark any registers not in RegMask as used.
894  /// This corresponds to the bit mask attached to register mask operands.
895  void addPhysRegsUsedFromRegMask(const uint32_t *RegMask) {
896  UsedPhysRegMask.setBitsNotInMask(RegMask);
897  }
898 
899  const BitVector &getUsedPhysRegsMask() const { return UsedPhysRegMask; }
900 
901  //===--------------------------------------------------------------------===//
902  // Reserved Register Info
903  //===--------------------------------------------------------------------===//
904  //
905  // The set of reserved registers must be invariant during register
906  // allocation. For example, the target cannot suddenly decide it needs a
907  // frame pointer when the register allocator has already used the frame
908  // pointer register for something else.
909  //
910  // These methods can be used by target hooks like hasFP() to avoid changing
911  // the reserved register set during register allocation.
912 
913  /// freezeReservedRegs - Called by the register allocator to freeze the set
914  /// of reserved registers before allocation begins.
915  void freezeReservedRegs(const MachineFunction&);
916 
917  /// reserveReg -- Mark a register as reserved so checks like isAllocatable
918  /// will not suggest using it. This should not be used during the middle
919  /// of a function walk, or when liveness info is available.
920  void reserveReg(MCRegister PhysReg, const TargetRegisterInfo *TRI) {
922  "Reserved registers haven't been frozen yet. ");
923  MCRegAliasIterator R(PhysReg, TRI, true);
924 
925  for (; R.isValid(); ++R)
926  ReservedRegs.set(*R);
927  }
928 
929  /// reservedRegsFrozen - Returns true after freezeReservedRegs() was called
930  /// to ensure the set of reserved registers stays constant.
931  bool reservedRegsFrozen() const {
932  return !ReservedRegs.empty();
933  }
934 
935  /// canReserveReg - Returns true if PhysReg can be used as a reserved
936  /// register. Any register can be reserved before freezeReservedRegs() is
937  /// called.
938  bool canReserveReg(MCRegister PhysReg) const {
939  return !reservedRegsFrozen() || ReservedRegs.test(PhysReg);
940  }
941 
942  /// getReservedRegs - Returns a reference to the frozen set of reserved
943  /// registers. This method should always be preferred to calling
944  /// TRI::getReservedRegs() when possible.
945  const BitVector &getReservedRegs() const {
947  "Reserved registers haven't been frozen yet. "
948  "Use TRI::getReservedRegs().");
949  return ReservedRegs;
950  }
951 
952  /// isReserved - Returns true when PhysReg is a reserved register.
953  ///
954  /// Reserved registers may belong to an allocatable register class, but the
955  /// target has explicitly requested that they are not used.
956  bool isReserved(MCRegister PhysReg) const {
957  return getReservedRegs().test(PhysReg.id());
958  }
959 
960  /// Returns true when the given register unit is considered reserved.
961  ///
962  /// Register units are considered reserved when for at least one of their
963  /// root registers, the root register and all super registers are reserved.
964  /// This currently iterates the register hierarchy and may be slower than
965  /// expected.
966  bool isReservedRegUnit(unsigned Unit) const;
967 
968  /// isAllocatable - Returns true when PhysReg belongs to an allocatable
969  /// register class and it hasn't been reserved.
970  ///
971  /// Allocatable registers may show up in the allocation order of some virtual
972  /// register, so a register allocator needs to track its liveness and
973  /// availability.
974  bool isAllocatable(MCRegister PhysReg) const {
975  return getTargetRegisterInfo()->isInAllocatableClass(PhysReg) &&
976  !isReserved(PhysReg);
977  }
978 
979  //===--------------------------------------------------------------------===//
980  // LiveIn Management
981  //===--------------------------------------------------------------------===//
982 
983  /// addLiveIn - Add the specified register as a live-in. Note that it
984  /// is an error to add the same register to the same set more than once.
986  LiveIns.push_back(std::make_pair(Reg, vreg));
987  }
988 
989  // Iteration support for the live-ins set. It's kept in sorted order
990  // by register number.
991  using livein_iterator =
992  std::vector<std::pair<MCRegister,Register>>::const_iterator;
993  livein_iterator livein_begin() const { return LiveIns.begin(); }
994  livein_iterator livein_end() const { return LiveIns.end(); }
995  bool livein_empty() const { return LiveIns.empty(); }
996 
998  return LiveIns;
999  }
1000 
1001  bool isLiveIn(Register Reg) const;
1002 
1003  /// getLiveInPhysReg - If VReg is a live-in virtual register, return the
1004  /// corresponding live-in physical register.
1005  MCRegister getLiveInPhysReg(Register VReg) const;
1006 
1007  /// getLiveInVirtReg - If PReg is a live-in physical register, return the
1008  /// corresponding live-in virtual register.
1009  Register getLiveInVirtReg(MCRegister PReg) const;
1010 
1011  /// EmitLiveInCopies - Emit copies to initialize livein virtual registers
1012  /// into the given entry block.
1013  void EmitLiveInCopies(MachineBasicBlock *EntryMBB,
1014  const TargetRegisterInfo &TRI,
1015  const TargetInstrInfo &TII);
1016 
1017  /// Returns a mask covering all bits that can appear in lane masks of
1018  /// subregisters of the virtual register @p Reg.
1020 
1021  /// defusechain_iterator - This class provides iterator support for machine
1022  /// operands in the function that use or define a specific register. If
1023  /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it
1024  /// returns defs. If neither are true then you are silly and it always
1025  /// returns end(). If SkipDebug is true it skips uses marked Debug
1026  /// when incrementing.
1027  template <bool ReturnUses, bool ReturnDefs, bool SkipDebug, bool ByOperand,
1028  bool ByInstr, bool ByBundle>
1029  class defusechain_iterator {
1030  friend class MachineRegisterInfo;
1031 
1032  public:
1033  using iterator_category = std::forward_iterator_tag;
1035  using difference_type = std::ptrdiff_t;
1036  using pointer = value_type *;
1038 
1039  private:
1040  MachineOperand *Op = nullptr;
1041 
1042  explicit defusechain_iterator(MachineOperand *op) : Op(op) {
1043  // If the first node isn't one we're interested in, advance to one that
1044  // we are interested in.
1045  if (op) {
1046  if ((!ReturnUses && op->isUse()) ||
1047  (!ReturnDefs && op->isDef()) ||
1048  (SkipDebug && op->isDebug()))
1049  advance();
1050  }
1051  }
1052 
1053  void advance() {
1054  assert(Op && "Cannot increment end iterator!");
1055  Op = getNextOperandForReg(Op);
1056 
1057  // All defs come before the uses, so stop def_iterator early.
1058  if (!ReturnUses) {
1059  if (Op) {
1060  if (Op->isUse())
1061  Op = nullptr;
1062  else
1063  assert(!Op->isDebug() && "Can't have debug defs");
1064  }
1065  } else {
1066  // If this is an operand we don't care about, skip it.
1067  while (Op && ((!ReturnDefs && Op->isDef()) ||
1068  (SkipDebug && Op->isDebug())))
1069  Op = getNextOperandForReg(Op);
1070  }
1071  }
1072 
1073  public:
1074  defusechain_iterator() = default;
1075 
1076  bool operator==(const defusechain_iterator &x) const {
1077  return Op == x.Op;
1078  }
1079  bool operator!=(const defusechain_iterator &x) const {
1080  return !operator==(x);
1081  }
1082 
1083  /// atEnd - return true if this iterator is equal to reg_end() on the value.
1084  bool atEnd() const { return Op == nullptr; }
1085 
1086  // Iterator traversal: forward iteration only
1087  defusechain_iterator &operator++() { // Preincrement
1088  assert(Op && "Cannot increment end iterator!");
1089  if (ByOperand)
1090  advance();
1091  else if (ByInstr) {
1092  MachineInstr *P = Op->getParent();
1093  do {
1094  advance();
1095  } while (Op && Op->getParent() == P);
1096  } else if (ByBundle) {
1098  getBundleStart(Op->getParent()->getIterator());
1099  do {
1100  advance();
1101  } while (Op && getBundleStart(Op->getParent()->getIterator()) == P);
1102  }
1103 
1104  return *this;
1105  }
1106  defusechain_iterator operator++(int) { // Postincrement
1107  defusechain_iterator tmp = *this; ++*this; return tmp;
1108  }
1109 
1110  /// getOperandNo - Return the operand # of this MachineOperand in its
1111  /// MachineInstr.
1112  unsigned getOperandNo() const {
1113  assert(Op && "Cannot dereference end iterator!");
1114  return Op - &Op->getParent()->getOperand(0);
1115  }
1116 
1117  // Retrieve a reference to the current operand.
1119  assert(Op && "Cannot dereference end iterator!");
1120  return *Op;
1121  }
1122 
1124  assert(Op && "Cannot dereference end iterator!");
1125  return Op;
1126  }
1127  };
1128 
1129  /// defusechain_iterator - This class provides iterator support for machine
1130  /// operands in the function that use or define a specific register. If
1131  /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it
1132  /// returns defs. If neither are true then you are silly and it always
1133  /// returns end(). If SkipDebug is true it skips uses marked Debug
1134  /// when incrementing.
1135  template <bool ReturnUses, bool ReturnDefs, bool SkipDebug, bool ByOperand,
1136  bool ByInstr, bool ByBundle>
1138  friend class MachineRegisterInfo;
1139 
1140  public:
1141  using iterator_category = std::forward_iterator_tag;
1143  using difference_type = std::ptrdiff_t;
1144  using pointer = value_type *;
1146 
1147  private:
1148  MachineOperand *Op = nullptr;
1149 
1151  // If the first node isn't one we're interested in, advance to one that
1152  // we are interested in.
1153  if (op) {
1154  if ((!ReturnUses && op->isUse()) ||
1155  (!ReturnDefs && op->isDef()) ||
1156  (SkipDebug && op->isDebug()))
1157  advance();
1158  }
1159  }
1160 
1161  void advance() {
1162  assert(Op && "Cannot increment end iterator!");
1163  Op = getNextOperandForReg(Op);
1164 
1165  // All defs come before the uses, so stop def_iterator early.
1166  if (!ReturnUses) {
1167  if (Op) {
1168  if (Op->isUse())
1169  Op = nullptr;
1170  else
1171  assert(!Op->isDebug() && "Can't have debug defs");
1172  }
1173  } else {
1174  // If this is an operand we don't care about, skip it.
1175  while (Op && ((!ReturnDefs && Op->isDef()) ||
1176  (SkipDebug && Op->isDebug())))
1177  Op = getNextOperandForReg(Op);
1178  }
1179  }
1180 
1181  public:
1182  defusechain_instr_iterator() = default;
1183 
1185  return Op == x.Op;
1186  }
1188  return !operator==(x);
1189  }
1190 
1191  /// atEnd - return true if this iterator is equal to reg_end() on the value.
1192  bool atEnd() const { return Op == nullptr; }
1193 
1194  // Iterator traversal: forward iteration only
1196  assert(Op && "Cannot increment end iterator!");
1197  if (ByOperand)
1198  advance();
1199  else if (ByInstr) {
1200  MachineInstr *P = Op->getParent();
1201  do {
1202  advance();
1203  } while (Op && Op->getParent() == P);
1204  } else if (ByBundle) {
1206  getBundleStart(Op->getParent()->getIterator());
1207  do {
1208  advance();
1209  } while (Op && getBundleStart(Op->getParent()->getIterator()) == P);
1210  }
1211 
1212  return *this;
1213  }
1214  defusechain_instr_iterator operator++(int) { // Postincrement
1215  defusechain_instr_iterator tmp = *this; ++*this; return tmp;
1216  }
1217 
1218  // Retrieve a reference to the current operand.
1220  assert(Op && "Cannot dereference end iterator!");
1221  if (ByBundle)
1222  return *getBundleStart(Op->getParent()->getIterator());
1223  return *Op->getParent();
1224  }
1225 
1226  MachineInstr *operator->() const { return &operator*(); }
1227  };
1228 };
1229 
1230 /// Iterate over the pressure sets affected by the given physical or virtual
1231 /// register. If Reg is physical, it must be a register unit (from
1232 /// MCRegUnitIterator).
1234  const int *PSet = nullptr;
1235  unsigned Weight = 0;
1236 
1237 public:
1238  PSetIterator() = default;
1239 
1241  const TargetRegisterInfo *TRI = MRI->getTargetRegisterInfo();
1242  if (RegUnit.isVirtual()) {
1243  const TargetRegisterClass *RC = MRI->getRegClass(RegUnit);
1244  PSet = TRI->getRegClassPressureSets(RC);
1245  Weight = TRI->getRegClassWeight(RC).RegWeight;
1246  } else {
1247  PSet = TRI->getRegUnitPressureSets(RegUnit);
1248  Weight = TRI->getRegUnitWeight(RegUnit);
1249  }
1250  if (*PSet == -1)
1251  PSet = nullptr;
1252  }
1253 
1254  bool isValid() const { return PSet; }
1255 
1256  unsigned getWeight() const { return Weight; }
1257 
1258  unsigned operator*() const { return *PSet; }
1259 
1260  void operator++() {
1261  assert(isValid() && "Invalid PSetIterator.");
1262  ++PSet;
1263  if (*PSet == -1)
1264  PSet = nullptr;
1265  }
1266 };
1267 
1268 inline PSetIterator
1270  return PSetIterator(RegUnit, this);
1271 }
1272 
1273 } // end namespace llvm
1274 
1275 #endif // LLVM_CODEGEN_MACHINEREGISTERINFO_H
llvm::MachineRegisterInfo::addLiveIn
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addLiveIn - Add the specified register as a live-in.
Definition: MachineRegisterInfo.h:985
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static def_instr_iterator def_instr_end()
Definition: MachineRegisterInfo.h:422
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Definition: LaneBitmask.h:40
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Definition: AddressRanges.h:18
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Definition: MachineRegisterInfo.h:1214
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bool isPhysRegUsed(MCRegister PhysReg, bool SkipRegMaskTest=false) const
Return true if the specified register is modified or read in this function.
Definition: MachineRegisterInfo.cpp:589
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Definition: MachineRegisterInfo.h:560
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Definition: MachineRegisterInfo.cpp:91
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Definition: iterator_range.h:53
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Returns true if liveness for register class RC should be tracked at the subregister level.
Definition: MachineRegisterInfo.h:226
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Definition: SmallPtrSet.h:379
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Definition: MachineRegisterInfo.h:450
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Definition: MachineRegisterInfo.h:51
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bool operator==(const defusechain_iterator &x) const
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recomputeRegClass - Try to find a legal super-class of Reg's register class that still satisfies the ...
Definition: MachineRegisterInfo.cpp:121
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def_bundle_iterator def_bundle_begin(Register RegNo) const
Definition: MachineRegisterInfo.h:435
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void disableCalleeSavedRegister(MCRegister Reg)
Disables the register from the list of CSRs.
Definition: MachineRegisterInfo.cpp:602
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unsigned id() const
Definition: Register.h:111
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Definition: MachineRegisterInfo.h:393
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def_instr_iterator def_instr_begin(Register RegNo) const
Definition: MachineRegisterInfo.h:419
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This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1199
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bool isInAllocatableClass(MCRegister RegNo) const
Return true if the register is in the allocation of any register class.
Definition: TargetRegisterInfo.h:364
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bool livein_empty() const
Definition: MachineRegisterInfo.h:995
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Reg
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const TargetRegisterInfo * getTargetRegisterInfo() const
Definition: MachineRegisterInfo.h:156
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Definition: MachineRegisterInfo.h:1219
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getUniqueVRegDef - Return the unique machine instr that defines the specified virtual register or nul...
Definition: MachineRegisterInfo.cpp:409
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Definition: MachineRegisterInfo.h:291
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bool canReserveReg(MCRegister PhysReg) const
canReserveReg - Returns true if PhysReg can be used as a reserved register.
Definition: MachineRegisterInfo.h:938
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use_instr_nodbg_iterator use_instr_nodbg_begin(Register RegNo) const
Definition: MachineRegisterInfo.h:557
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Definition: TargetSubtargetInfo.h:127
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Definition: MachineRegisterInfo.h:565
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Definition: TargetRegisterInfo.h:236
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Definition: MachineRegisterInfo.h:1184
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Definition: StringMap.h:204
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Definition: Type.h:45
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llvm::MachineRegisterInfo::defusechain_instr_iterator::operator!=
bool operator!=(const defusechain_instr_iterator &x) const
Definition: MachineRegisterInfo.h:1187
llvm::MachineRegisterInfo::reg_nodbg_begin
reg_nodbg_iterator reg_nodbg_begin(Register RegNo) const
Definition: MachineRegisterInfo.h:351
llvm::MachineRegisterInfo::getLiveInVirtReg
Register getLiveInVirtReg(MCRegister PReg) const
getLiveInVirtReg - If PReg is a live-in physical register, return the corresponding live-in virtual r...
Definition: MachineRegisterInfo.cpp:458
llvm::MachineRegisterInfo::use_operands
iterator_range< use_iterator > use_operands(Register Reg) const
Definition: MachineRegisterInfo.h:491
llvm::MachineFunctionProperties::Property::IsSSA
@ IsSSA
llvm::MachineRegisterInfo::getNumVirtRegs
unsigned getNumVirtRegs() const
getNumVirtRegs - Return the number of virtual registers created.
Definition: MachineRegisterInfo.h:784
llvm::SmallPtrSet
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.
Definition: SmallPtrSet.h:450
llvm::MachineRegisterInfo::reg_end
static reg_iterator reg_end()
Definition: MachineRegisterInfo.h:306
llvm::MachineRegisterInfo::reg_instr_begin
reg_instr_iterator reg_instr_begin(Register RegNo) const
Definition: MachineRegisterInfo.h:316
llvm::MachineRegisterInfo::defusechain_iterator::operator->
MachineOperand * operator->() const
Definition: MachineRegisterInfo.h:1123
llvm::StringSet::insert
std::pair< typename Base::iterator, bool > insert(StringRef key)
Definition: StringSet.h:34
llvm::MachineRegisterInfo::use_bundle_begin
use_bundle_iterator use_bundle_begin(Register RegNo) const
Definition: MachineRegisterInfo.h:515
llvm::MachineRegisterInfo::defusechain_iterator
friend class defusechain_iterator
Definition: MachineRegisterInfo.h:291
llvm::StringMap< std::nullopt_t, MallocAllocator >::find
iterator find(StringRef Key)
Definition: StringMap.h:217
tmp
alloca< 16 x float >, align 16 %tmp2=alloca< 16 x float >, align 16 store< 16 x float > %A,< 16 x float > *%tmp %s=bitcast< 16 x float > *%tmp to i8 *%s2=bitcast< 16 x float > *%tmp2 to i8 *call void @llvm.memcpy.i64(i8 *%s, i8 *%s2, i64 64, i32 16) %R=load< 16 x float > *%tmp2 ret< 16 x float > %R } declare void @llvm.memcpy.i64(i8 *nocapture, i8 *nocapture, i64, i32) nounwind which compiles to:_foo:subl $140, %esp movaps %xmm3, 112(%esp) movaps %xmm2, 96(%esp) movaps %xmm1, 80(%esp) movaps %xmm0, 64(%esp) movl 60(%esp), %eax movl %eax, 124(%esp) movl 56(%esp), %eax movl %eax, 120(%esp) movl 52(%esp), %eax< many many more 32-bit copies > movaps(%esp), %xmm0 movaps 16(%esp), %xmm1 movaps 32(%esp), %xmm2 movaps 48(%esp), %xmm3 addl $140, %esp ret On Nehalem, it may even be cheaper to just use movups when unaligned than to fall back to lower-granularity chunks. Implement processor-specific optimizations for parity with GCC on these processors. GCC does two optimizations:1. ix86_pad_returns inserts a noop before ret instructions if immediately preceded by a conditional branch or is the target of a jump. 2. ix86_avoid_jump_misspredicts inserts noops in cases where a 16-byte block of code contains more than 3 branches. The first one is done for all AMDs, Core2, and "Generic" The second one is done for:Atom, Pentium Pro, all AMDs, Pentium 4, Nocona, Core 2, and "Generic" Testcase:int x(int a) { return(a &0xf0)> >4 tmp
Definition: README.txt:1347
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
llvm::MachineRegisterInfo::defusechain_iterator::getOperandNo
unsigned getOperandNo() const
getOperandNo - Return the operand # of this MachineOperand in its MachineInstr.
Definition: MachineRegisterInfo.h:1112
llvm::RISCVFenceField::R
@ R
Definition: RISCVBaseInfo.h:275
llvm::MachineRegisterInfo::use_nodbg_begin
use_nodbg_iterator use_nodbg_begin(Register RegNo) const
Definition: MachineRegisterInfo.h:540
llvm::MachineRegisterInfo::defusechain_instr_iterator::operator->
MachineInstr * operator->() const
Definition: MachineRegisterInfo.h:1226
Uses
SmallPtrSet< MachineInstr *, 2 > Uses
Definition: ARMLowOverheadLoops.cpp:590
llvm::MachineRegisterInfo::reg_bundle_iterator
defusechain_instr_iterator< true, true, false, false, false, true > reg_bundle_iterator
reg_bundle_iterator/reg_bundle_begin/reg_bundle_end - Walk all defs and uses of the specified registe...
Definition: MachineRegisterInfo.h:331
llvm::MachineRegisterInfo::tracksLiveness
bool tracksLiveness() const
tracksLiveness - Returns true when tracking register liveness accurately.
Definition: MachineRegisterInfo.h:209
llvm::PSetIterator
Iterate over the pressure sets affected by the given physical or virtual register.
Definition: MachineRegisterInfo.h:1233
llvm::MachineRegisterInfo::reg_nodbg_instructions
iterator_range< reg_instr_nodbg_iterator > reg_nodbg_instructions(Register Reg) const
Definition: MachineRegisterInfo.h:376
llvm::MachineRegisterInfo::defusechain_instr_iterator::atEnd
bool atEnd() const
atEnd - return true if this iterator is equal to reg_end() on the value.
Definition: MachineRegisterInfo.h:1192
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:98
llvm::MachineRegisterInfo::use_nodbg_operands
iterator_range< use_nodbg_iterator > use_nodbg_operands(Register Reg) const
Definition: MachineRegisterInfo.h:548
llvm::RegClassOrRegBank
PointerUnion< const TargetRegisterClass *, const RegisterBank * > RegClassOrRegBank
Convenient type to represent either a register class or a register bank.
Definition: MachineRegisterInfo.h:46
llvm::RegisterBank
This class implements the register bank concept.
Definition: RegisterBank.h:28
llvm::MachineRegisterInfo::setRegClassOrRegBank
void setRegClassOrRegBank(Register Reg, const RegClassOrRegBank &RCOrRB)
Definition: MachineRegisterInfo.h:705
llvm::MachineRegisterInfo::setType
void setType(Register VReg, LLT Ty)
Set the low-level type of VReg to Ty.
Definition: MachineRegisterInfo.cpp:179
llvm::MachineRegisterInfo::Delegate::MRI_NoteNewVirtualRegister
virtual void MRI_NoteNewVirtualRegister(Register Reg)=0
llvm::MachineRegisterInfo::reg_bundle_begin
reg_bundle_iterator reg_bundle_begin(Register RegNo) const
Definition: MachineRegisterInfo.h:332
llvm::IndexedMap::size
StorageT::size_type size() const
Definition: IndexedMap.h:78
llvm::MachineRegisterInfo::reg_nodbg_iterator
defusechain_iterator< true, true, true, true, false, false > reg_nodbg_iterator
reg_nodbg_iterator/reg_nodbg_begin/reg_nodbg_end - Walk all defs and uses of the specified register,...
Definition: MachineRegisterInfo.h:350
llvm::MachineRegisterInfo::isUpdatedCSRsInitialized
bool isUpdatedCSRsInitialized() const
Returns true if the updated CSR list was initialized and false otherwise.
Definition: MachineRegisterInfo.h:242
llvm::MachineRegisterInfo::noteCloneVirtualRegister
void noteCloneVirtualRegister(Register NewReg, Register SrcReg)
Definition: MachineRegisterInfo.h:181
llvm::MachineRegisterInfo::isReserved
bool isReserved(MCRegister PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.
Definition: MachineRegisterInfo.h:956
llvm::IndexedMap
Definition: IndexedMap.h:30
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:45
llvm::MachineFunction::getProperties
const MachineFunctionProperties & getProperties() const
Get the function properties.
Definition: MachineFunction.h:763
llvm::MachineRegisterInfo::reg_nodbg_operands
iterator_range< reg_nodbg_iterator > reg_nodbg_operands(Register Reg) const
Definition: MachineRegisterInfo.h:359
llvm::MachineRegisterInfo::defusechain_iterator::difference_type
std::ptrdiff_t difference_type
Definition: MachineRegisterInfo.h:1035
llvm::MachineRegisterInfo::insertVRegByName
void insertVRegByName(StringRef Name, Register Reg)
Definition: MachineRegisterInfo.h:454
llvm::MachineRegisterInfo::reg_instr_nodbg_end
static reg_instr_nodbg_iterator reg_instr_nodbg_end()
Definition: MachineRegisterInfo.h:371
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:125
llvm::MachineRegisterInfo::reg_iterator
defusechain_iterator< true, true, false, true, false, false > reg_iterator
reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specified register.
Definition: MachineRegisterInfo.h:302
llvm::MachineRegisterInfo::defusechain_iterator::atEnd
bool atEnd() const
atEnd - return true if this iterator is equal to reg_end() on the value.
Definition: MachineRegisterInfo.h:1084
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48
llvm::MachineRegisterInfo::reg_instructions
iterator_range< reg_instr_iterator > reg_instructions(Register Reg) const
Definition: MachineRegisterInfo.h:324
llvm::MachineRegisterInfo::setCalleeSavedRegs
void setCalleeSavedRegs(ArrayRef< MCPhysReg > CSRs)
Sets the updated Callee Saved Registers list.
Definition: MachineRegisterInfo.cpp:632
llvm::PSetIterator::getWeight
unsigned getWeight() const
Definition: MachineRegisterInfo.h:1256
MachineInstrBundle.h
llvm::MachineRegisterInfo::use_iterator
defusechain_iterator< true, false, false, true, false, false > use_iterator
use_iterator/use_begin/use_end - Walk all uses of the specified register.
Definition: MachineRegisterInfo.h:485
llvm::MachineRegisterInfo::defusechain_iterator::operator*
MachineOperand & operator*() const
Definition: MachineRegisterInfo.h:1118
llvm::MachineRegisterInfo::def_iterator
defusechain_iterator< false, true, false, true, false, false > def_iterator
def_iterator/def_begin/def_end - Walk all defs of the specified register.
Definition: MachineRegisterInfo.h:405
BitVector.h
llvm::MachineRegisterInfo::use_nodbg_end
static use_nodbg_iterator use_nodbg_end()
Definition: MachineRegisterInfo.h:543
llvm::MachineRegisterInfo::freezeReservedRegs
void freezeReservedRegs(const MachineFunction &)
freezeReservedRegs - Called by the register allocator to freeze the set of reserved registers before ...
Definition: MachineRegisterInfo.cpp:511
llvm::MachineRegisterInfo::Delegate::MRI_NotecloneVirtualRegister
virtual void MRI_NotecloneVirtualRegister(Register NewReg, Register SrcReg)
Definition: MachineRegisterInfo.h:60
SmallPtrSet.h
llvm::MachineRegisterInfo::operator=
MachineRegisterInfo & operator=(const MachineRegisterInfo &)=delete
llvm::BitVector
Definition: BitVector.h:75
llvm::MachineRegisterInfo::livein_begin
livein_iterator livein_begin() const
Definition: MachineRegisterInfo.h:993
llvm::MachineRegisterInfo::clearVirtRegTypes
void clearVirtRegTypes()
Remove all types associated to virtual registers (after instruction selection and constraining of all...
Definition: MachineRegisterInfo.cpp:195
Register
Promote Memory to Register
Definition: Mem2Reg.cpp:110
llvm::MachineRegisterInfo::reservedRegsFrozen
bool reservedRegsFrozen() const
reservedRegsFrozen - Returns true after freezeReservedRegs() was called to ensure the set of reserved...
Definition: MachineRegisterInfo.h:931
llvm::MachineRegisterInfo::getVRegDef
MachineInstr * getVRegDef(Register Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
Definition: MachineRegisterInfo.cpp:398
llvm::MachineRegisterInfo::use_bundles
iterator_range< use_bundle_iterator > use_bundles(Register Reg) const
Definition: MachineRegisterInfo.h:522
llvm::MachineRegisterInfo::use_empty
bool use_empty(Register RegNo) const
use_empty - Return true if there are no instructions using the specified register.
Definition: MachineRegisterInfo.h:528
llvm::MachineRegisterInfo::reg_instr_end
static reg_instr_iterator reg_instr_end()
Definition: MachineRegisterInfo.h:319
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::MachineRegisterInfo::reg_nodbg_end
static reg_nodbg_iterator reg_nodbg_end()
Definition: MachineRegisterInfo.h:354
llvm::MachineRegisterInfo::defusechain_instr_iterator::defusechain_instr_iterator
defusechain_instr_iterator()=default
llvm::MachineRegisterInfo::def_empty
bool def_empty(Register RegNo) const
def_empty - Return true if there are no instructions defining the specified register (it may be live-...
Definition: MachineRegisterInfo.h:448
llvm::MachineRegisterInfo::reg_instr_iterator
defusechain_instr_iterator< true, true, false, false, true, false > reg_instr_iterator
reg_instr_iterator/reg_instr_begin/reg_instr_end - Walk all defs and uses of the specified register,...
Definition: MachineRegisterInfo.h:315
llvm::MachineRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
Definition: MachineRegisterInfo.h:661
llvm::MachineRegisterInfo::isSSA
bool isSSA() const
Definition: MachineRegisterInfo.h:197
llvm::MachineRegisterInfo::defusechain_instr_iterator
friend class defusechain_instr_iterator
Definition: MachineRegisterInfo.h:297
llvm::Register::isVirtual
bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:91
llvm::MachineRegisterInfo::clearKillFlags
void clearKillFlags(Register Reg) const
clearKillFlags - Iterate over all the uses of the given register and clear the kill flag from the Mac...
Definition: MachineRegisterInfo.cpp:435
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:672
llvm::MachineRegisterInfo::defusechain_instr_iterator::operator++
defusechain_instr_iterator & operator++()
Definition: MachineRegisterInfo.h:1195
llvm::MachineRegisterInfo::verifyUseList
void verifyUseList(Register Reg) const
Verify the sanity of the use list for Reg.
Definition: MachineRegisterInfo.cpp:217
llvm::MachineRegisterInfo::reg_bundles
iterator_range< reg_bundle_iterator > reg_bundles(Register Reg) const
Definition: MachineRegisterInfo.h:339
llvm::TargetRegisterInfo::regsOverlap
bool regsOverlap(Register RegA, Register RegB) const
Returns true if the two registers are equal or alias each other.
Definition: TargetRegisterInfo.h:421
llvm::PSetIterator::operator++
void operator++()
Definition: MachineRegisterInfo.h:1260
llvm::MachineRegisterInfo::reg_bundle_end
static reg_bundle_iterator reg_bundle_end()
Definition: MachineRegisterInfo.h:335
llvm::MachineFunctionProperties::Property::TracksLiveness
@ TracksLiveness
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::MachineRegisterInfo::setRegBank
void setRegBank(Register Reg, const RegisterBank &RegBank)
Set the register bank to RegBank for Reg.
Definition: MachineRegisterInfo.cpp:62
llvm::MachineRegisterInfo::use_nodbg_iterator
defusechain_iterator< true, false, true, true, false, false > use_nodbg_iterator
use_nodbg_iterator/use_nodbg_begin/use_nodbg_end - Walk all uses of the specified register,...
Definition: MachineRegisterInfo.h:539
llvm::MachineRegisterInfo::use_instr_begin
use_instr_iterator use_instr_begin(Register RegNo) const
Definition: MachineRegisterInfo.h:499
llvm::MachineRegisterInfo::def_bundle_end
static def_bundle_iterator def_bundle_end()
Definition: MachineRegisterInfo.h:438
llvm::PointerUnion::dyn_cast
T dyn_cast() const
Returns the current pointer if it is of the specified pointer type, otherwise returns null.
Definition: PointerUnion.h:162
llvm::MachineRegisterInfo::def_instr_iterator
defusechain_instr_iterator< false, true, false, false, true, false > def_instr_iterator
def_instr_iterator/def_instr_begin/def_instr_end - Walk all defs of the specified register,...
Definition: MachineRegisterInfo.h:418
llvm::MachineRegisterInfo::def_bundles
iterator_range< def_bundle_iterator > def_bundles(Register Reg) const
Definition: MachineRegisterInfo.h:442
llvm::MachineRegisterInfo::getCalleeSavedRegs
const MCPhysReg * getCalleeSavedRegs() const
Returns list of callee saved registers.
Definition: MachineRegisterInfo.cpp:625
llvm::MachineRegisterInfo::def_instructions
iterator_range< def_instr_iterator > def_instructions(Register Reg) const
Definition: MachineRegisterInfo.h:427
llvm::MachineRegisterInfo::reg_instr_nodbg_begin
reg_instr_nodbg_iterator reg_instr_nodbg_begin(Register RegNo) const
Definition: MachineRegisterInfo.h:368
llvm::TargetRegisterClass::HasDisjunctSubRegs
const bool HasDisjunctSubRegs
Whether the class supports two (or more) disjunct subregister indices.
Definition: TargetRegisterInfo.h:66
llvm::MachineRegisterInfo::getLiveInPhysReg
MCRegister getLiveInPhysReg(Register VReg) const
getLiveInPhysReg - If VReg is a live-in virtual register, return the corresponding live-in physical r...
Definition: MachineRegisterInfo.cpp:449
llvm::MachineRegisterInfo::addDelegate
void addDelegate(Delegate *delegate)
Definition: MachineRegisterInfo.h:168
llvm::MachineRegisterInfo::liveins
ArrayRef< std::pair< MCRegister, Register > > liveins() const
Definition: MachineRegisterInfo.h:997
llvm::MachineRegisterInfo::reserveReg
void reserveReg(MCRegister PhysReg, const TargetRegisterInfo *TRI)
reserveReg – Mark a register as reserved so checks like isAllocatable will not suggest using it.
Definition: MachineRegisterInfo.h:920
ArrayRef.h
TemplateParamKind::Type
@ Type
llvm::MachineRegisterInfo::getRegClassOrNull
const TargetRegisterClass * getRegClassOrNull(Register Reg) const
Return the register class of Reg, or null if Reg has not been assigned a register class yet.
Definition: MachineRegisterInfo.h:678
llvm::MachineRegisterInfo::reg_operands
iterator_range< reg_iterator > reg_operands(Register Reg) const
Definition: MachineRegisterInfo.h:308
llvm::MachineRegisterInfo::isAllocatable
bool isAllocatable(MCRegister PhysReg) const
isAllocatable - Returns true when PhysReg belongs to an allocatable register class and it hasn't been...
Definition: MachineRegisterInfo.h:974
llvm::MachineRegisterInfo::setSimpleHint
void setSimpleHint(Register VReg, Register PrefReg)
Specify the preferred (target independent) register allocation hint for the specified virtual registe...
Definition: MachineRegisterInfo.h:808
llvm::MachineRegisterInfo::getOneDef
MachineOperand * getOneDef(Register Reg) const
Returns the defining operand if there is exactly one operand defining the specified register,...
Definition: MachineRegisterInfo.h:472
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
PointerUnion.h
iterator_range.h
llvm::MachineRegisterInfo::isArgumentRegister
bool isArgumentRegister(const MachineFunction &MF, MCRegister Reg) const
Returns true if a register can be used as an argument to a function.
Definition: MachineRegisterInfo.cpp:662
llvm::MachineRegisterInfo::createGenericVirtualRegister
Register createGenericVirtualRegister(LLT Ty, StringRef Name="")
Create and return a new generic virtual register with low-level type Ty.
Definition: MachineRegisterInfo.cpp:185
llvm::MachineRegisterInfo::hasOneDef
bool hasOneDef(Register RegNo) const
Return true if there is exactly one operand defining the specified register.
Definition: MachineRegisterInfo.h:466
llvm::MachineRegisterInfo::def_end
static def_iterator def_end()
Definition: MachineRegisterInfo.h:409
llvm::MachineRegisterInfo::updateDbgUsersToReg
void updateDbgUsersToReg(MCRegister OldReg, MCRegister NewReg, ArrayRef< MachineInstr * > Users) const
updateDbgUsersToReg - Update a collection of debug instructions to refer to the designated register.
Definition: MachineRegisterInfo.h:853
llvm::SmallPtrSetImpl::count
size_type count(ConstPtrType Ptr) const
count - Return 1 if the specified pointer is in the set, 0 otherwise.
Definition: SmallPtrSet.h:383
llvm::MachineRegisterInfo::getRegClassOrRegBank
const RegClassOrRegBank & getRegClassOrRegBank(Register Reg) const
Return the register bank or register class of Reg.
Definition: MachineRegisterInfo.h:695
llvm::MachineFunction
Definition: MachineFunction.h:258
llvm::MachineRegisterInfo::resetDelegate
void resetDelegate(Delegate *delegate)
Definition: MachineRegisterInfo.h:160
llvm::MachineRegisterInfo::use_nodbg_empty
bool use_nodbg_empty(Register RegNo) const
use_nodbg_empty - Return true if there are no non-Debug instructions using the specified register.
Definition: MachineRegisterInfo.h:588
llvm::MCRegister::id
unsigned id() const
Definition: MCRegister.h:72
llvm::hasSingleElement
bool hasSingleElement(ContainerTy &&C)
Returns true if the given container only contains a single element.
Definition: STLExtras.h:379
llvm::StringSet
StringSet - A wrapper for StringMap that provides set-like functionality.
Definition: StringSet.h:23
llvm::MachineRegisterInfo::use_instr_iterator
defusechain_instr_iterator< true, false, false, false, true, false > use_instr_iterator
use_instr_iterator/use_instr_begin/use_instr_end - Walk all uses of the specified register,...
Definition: MachineRegisterInfo.h:498
llvm::IndexedMap::grow
void grow(IndexT n)
Definition: IndexedMap.h:68
llvm::MachineRegisterInfo::Delegate
Definition: MachineRegisterInfo.h:53
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:33
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
llvm::MachineRegisterInfo::hasOneNonDBGUse
bool hasOneNonDBGUse(Register RegNo) const
hasOneNonDBGUse - Return true if there is exactly one non-Debug use of the specified register.
Definition: MachineRegisterInfo.cpp:417
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::MachineRegisterInfo::isFixedRegister
bool isFixedRegister(const MachineFunction &MF, MCRegister Reg) const
Returns true if a register is a fixed register.
Definition: MachineRegisterInfo.cpp:667
llvm::MachineRegisterInfo::use_begin
use_iterator use_begin(Register RegNo) const
Definition: MachineRegisterInfo.h:486
llvm::MachineRegisterInfo::setRegAllocationHint
void setRegAllocationHint(Register VReg, unsigned Type, Register PrefReg)
setRegAllocationHint - Specify a register allocation hint for the specified virtual register.
Definition: MachineRegisterInfo.h:792
uint32_t
llvm::getBundleStart
MachineBasicBlock::instr_iterator getBundleStart(MachineBasicBlock::instr_iterator I)
Returns an iterator to the first instruction in the bundle containing I.
Definition: MachineInstrBundle.h:44
llvm::MachineRegisterInfo::invalidateLiveness
void invalidateLiveness()
invalidateLiveness - Indicates that register liveness is no longer being tracked accurately.
Definition: MachineRegisterInfo.h:219
llvm::MachineRegisterInfo::reg_instr_nodbg_iterator
defusechain_instr_iterator< true, true, true, false, true, false > reg_instr_nodbg_iterator
reg_instr_nodbg_iterator/reg_instr_nodbg_begin/reg_instr_nodbg_end - Walk all defs and uses of the sp...
Definition: MachineRegisterInfo.h:367
TargetSubtargetInfo.h
llvm::MachineRegisterInfo::removeRegOperandFromUseList
void removeRegOperandFromUseList(MachineOperand *MO)
Remove MO from its use-def list.
Definition: MachineRegisterInfo.cpp:304
llvm::MachineRegisterInfo::defusechain_iterator::operator!=
bool operator!=(const defusechain_iterator &x) const
Definition: MachineRegisterInfo.h:1079
llvm::MachineFunctionProperties::reset
MachineFunctionProperties & reset(Property P)
Definition: MachineFunction.h:202
llvm::MachineRegisterInfo::getRegAllocationHints
const std::pair< Register, SmallVector< Register, 4 > > & getRegAllocationHints(Register VReg) const
getRegAllocationHints - Return a reference to the vector of all register allocation hints for VReg.
Definition: MachineRegisterInfo.h:841
llvm::MachineRegisterInfo::getReservedRegs
const BitVector & getReservedRegs() const
getReservedRegs - Returns a reference to the frozen set of reserved registers.
Definition: MachineRegisterInfo.h:945
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::PointerUnion
A discriminated union of two or more pointer types, with the discriminator in the low bit of the poin...
Definition: PointerUnion.h:112
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::PSetIterator::PSetIterator
PSetIterator(Register RegUnit, const MachineRegisterInfo *MRI)
Definition: MachineRegisterInfo.h:1240
llvm::MachineRegisterInfo::getUsedPhysRegsMask
const BitVector & getUsedPhysRegsMask() const
Definition: MachineRegisterInfo.h:899
llvm::MachineRegisterInfo::isConstantPhysReg
bool isConstantPhysReg(MCRegister PhysReg) const
Returns true if PhysReg is unallocatable and constant throughout the function.
Definition: MachineRegisterInfo.cpp:517
llvm::MachineRegisterInfo::replaceRegWith
void replaceRegWith(Register FromReg, Register ToReg)
replaceRegWith - Replace all instances of FromReg with ToReg in the machine function.
Definition: MachineRegisterInfo.cpp:380
StringSet.h
llvm::MachineRegisterInfo::hasAtMostUserInstrs
bool hasAtMostUserInstrs(Register Reg, unsigned MaxUsers) const
hasAtMostUses - Return true if the given register has at most MaxUsers non-debug user instructions.
Definition: MachineRegisterInfo.cpp:425
llvm::MachineRegisterInfo::def_operands
iterator_range< def_iterator > def_operands(Register Reg) const
Definition: MachineRegisterInfo.h:411
llvm::MachineRegisterInfo::reg_begin
reg_iterator reg_begin(Register RegNo) const
Definition: MachineRegisterInfo.h:303
llvm::BitVector::test
bool test(unsigned Idx) const
Definition: BitVector.h:454
llvm::MachineRegisterInfo::addRegOperandToUseList
void addRegOperandToUseList(MachineOperand *MO)
Add MO to the linked list of operands for its register.
Definition: MachineRegisterInfo.cpp:265
llvm::MachineRegisterInfo::getSimpleHint
Register getSimpleHint(Register VReg) const
getSimpleHint - same as getRegAllocationHint except it will only return a target independent hint.
Definition: MachineRegisterInfo.h:832
llvm::MachineRegisterInfo::isLiveIn
bool isLiveIn(Register Reg) const
Definition: MachineRegisterInfo.cpp:440
llvm::MachineRegisterInfo::getMaxLaneMaskForVReg
LaneBitmask getMaxLaneMaskForVReg(Register Reg) const
Returns a mask covering all bits that can appear in lane masks of subregisters of the virtual registe...
Definition: MachineRegisterInfo.cpp:497
llvm::GraphProgram::Name
Name
Definition: GraphWriter.h:50
uint16_t
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:354
llvm::MachineRegisterInfo::def_bundle_iterator
defusechain_instr_iterator< false, true, false, false, false, true > def_bundle_iterator
def_bundle_iterator/def_bundle_begin/def_bundle_end - Walk all defs of the specified register,...
Definition: MachineRegisterInfo.h:434
llvm::MachineBasicBlock::instr_iterator
Instructions::iterator instr_iterator
Definition: MachineBasicBlock.h:268
llvm::MachineRegisterInfo::livein_iterator
std::vector< std::pair< MCRegister, Register > >::const_iterator livein_iterator
Definition: MachineRegisterInfo.h:992
llvm::MachineRegisterInfo::reg_empty
bool reg_empty(Register RegNo) const
reg_empty - Return true if there are no instructions using or defining the specified register (it may...
Definition: MachineRegisterInfo.h:345
llvm::MachineRegisterInfo::getRegBankOrNull
const RegisterBank * getRegBankOrNull(Register Reg) const
Return the register bank of Reg, or null if Reg has not been assigned a register bank or has been ass...
Definition: MachineRegisterInfo.h:687
x
TODO unsigned x
Definition: README.txt:10
llvm::MachineRegisterInfo::addPhysRegsUsedFromRegMask
void addPhysRegsUsedFromRegMask(const uint32_t *RegMask)
addPhysRegsUsedFromRegMask - Mark any registers not in RegMask as used.
Definition: MachineRegisterInfo.h:895
llvm::MachineRegisterInfo::clearVirtRegs
void clearVirtRegs()
clearVirtRegs - Remove all virtual registers (after physreg assignment).
Definition: MachineRegisterInfo.cpp:198
llvm::MachineRegisterInfo::isPhysRegModified
bool isPhysRegModified(MCRegister PhysReg, bool SkipNoReturnDef=false) const
Return true if the specified register is modified in this function.
Definition: MachineRegisterInfo.cpp:574
llvm::MachineRegisterInfo::hasOneNonDBGUser
bool hasOneNonDBGUser(Register RegNo) const
hasOneNonDBGUse - Return true if there is exactly one non-Debug instruction using the specified regis...
Definition: MachineRegisterInfo.cpp:421
llvm::MachineRegisterInfo::use_nodbg_bundles
iterator_range< use_bundle_nodbg_iterator > use_nodbg_bundles(Register Reg) const
Definition: MachineRegisterInfo.h:582
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defusechain_iterator operator++(int)
Definition: MachineRegisterInfo.h:1106
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Definition: MIParser.h:37
llvm::MachineRegisterInfo::use_bundle_nodbg_end
static use_bundle_nodbg_iterator use_bundle_nodbg_end()
Definition: MachineRegisterInfo.h:577
llvm::MachineRegisterInfo::addRegAllocationHint
void addRegAllocationHint(Register VReg, Register PrefReg)
addRegAllocationHint - Add a register allocation hint to the hints vector for VReg.
Definition: MachineRegisterInfo.h:801
llvm::MachineRegisterInfo::use_bundle_nodbg_iterator
defusechain_instr_iterator< true, false, true, false, false, true > use_bundle_nodbg_iterator
use_bundle_nodbg_iterator/use_bundle_nodbg_begin/use_bundle_nodbg_end - Walk all uses of the specifie...
Definition: MachineRegisterInfo.h:573
llvm::MachineRegisterInfo::defusechain_instr_iterator::difference_type
std::ptrdiff_t difference_type
Definition: MachineRegisterInfo.h:1143
llvm::MachineRegisterInfo::use_end
static use_iterator use_end()
Definition: MachineRegisterInfo.h:489
llvm::MachineRegisterInfo::use_bundle_end
static use_bundle_iterator use_bundle_end()
Definition: MachineRegisterInfo.h:518
llvm::MachineRegisterInfo::reg_bundle_nodbg_begin
reg_bundle_nodbg_iterator reg_bundle_nodbg_begin(Register RegNo) const
Definition: MachineRegisterInfo.h:385
llvm::MachineRegisterInfo::hasOneUse
bool hasOneUse(Register RegNo) const
hasOneUse - Return true if there is exactly one instruction using the specified register.
Definition: MachineRegisterInfo.h:532
SmallVector.h
llvm::PSetIterator::operator*
unsigned operator*() const
Definition: MachineRegisterInfo.h:1258
llvm::MachineRegisterInfo::getType
LLT getType(Register Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register.
Definition: MachineRegisterInfo.h:759
llvm::MachineRegisterInfo::cloneVirtualRegister
Register cloneVirtualRegister(Register VReg, StringRef Name="")
Create and return a new virtual register in the function with the same attributes as the given regist...
Definition: MachineRegisterInfo.cpp:170
RegisterBank.h
llvm::MachineRegisterInfo::noteNewVirtualRegister
void noteNewVirtualRegister(Register Reg)
Definition: MachineRegisterInfo.h:176
llvm::IndexedMap::inBounds
bool inBounds(IndexT n) const
Definition: IndexedMap.h:74
llvm::MachineRegisterInfo::leaveSSA
void leaveSSA()
Definition: MachineRegisterInfo.h:203
llvm::MachineRegisterInfo::use_bundle_iterator
defusechain_instr_iterator< true, false, false, false, false, true > use_bundle_iterator
use_bundle_iterator/use_bundle_begin/use_bundle_end - Walk all uses of the specified register,...
Definition: MachineRegisterInfo.h:514
llvm::MachineRegisterInfo::isGeneralPurposeRegister
bool isGeneralPurposeRegister(const MachineFunction &MF, MCRegister Reg) const
Returns true if a register is a general purpose register.
Definition: MachineRegisterInfo.cpp:672
LaneBitmask.h
Users
iv Induction Variable Users
Definition: IVUsers.cpp:48
llvm::iterator_range
A range adaptor for a pair of iterators.
Definition: iterator_range.h:30
llvm::MachineRegisterInfo::constrainRegClass
const TargetRegisterClass * constrainRegClass(Register Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
Definition: MachineRegisterInfo.cpp:83
llvm::MachineRegisterInfo::defusechain_iterator
reg_begin/reg_end - Provide iteration support to walk over all definitions and uses of a register wit...
Definition: MachineRegisterInfo.h:288
MachineOperand.h
llvm::MachineRegisterInfo::use_bundle_nodbg_begin
use_bundle_nodbg_iterator use_bundle_nodbg_begin(Register RegNo) const
Definition: MachineRegisterInfo.h:574
llvm::MachineRegisterInfo::MachineRegisterInfo
MachineRegisterInfo(MachineFunction *MF)
Definition: MachineRegisterInfo.cpp:43
llvm::MachineRegisterInfo::reg_bundle_nodbg_iterator
defusechain_instr_iterator< true, true, true, false, false, true > reg_bundle_nodbg_iterator
reg_bundle_nodbg_iterator/reg_bundle_nodbg_begin/reg_bundle_nodbg_end - Walk all defs and uses of the...
Definition: MachineRegisterInfo.h:384
llvm::MachineRegisterInfo::shouldTrackSubRegLiveness
bool shouldTrackSubRegLiveness(Register VReg) const
Definition: MachineRegisterInfo.h:229
llvm::MachineRegisterInfo::isReservedRegUnit
bool isReservedRegUnit(unsigned Unit) const
Returns true when the given register unit is considered reserved.
Definition: MachineRegisterInfo.cpp:644
llvm::MachineRegisterInfo::clearSimpleHint
void clearSimpleHint(Register VReg)
Definition: MachineRegisterInfo.h:812
llvm::MachineRegisterInfo::reg_nodbg_empty
bool reg_nodbg_empty(Register RegNo) const
reg_nodbg_empty - Return true if the only instructions using or defining Reg are Debug instructions.
Definition: MachineRegisterInfo.h:399
MachineFunction.h
llvm::MachineRegisterInfo::defusechain_iterator::defusechain_iterator
defusechain_iterator()=default
llvm::MachineRegisterInfo::getPressureSets
PSetIterator getPressureSets(Register RegUnit) const
Get an iterator over the pressure sets affected by the given physical or virtual register.
Definition: MachineRegisterInfo.h:1269
llvm::MachineRegisterInfo::defusechain_instr_iterator::iterator_category
std::forward_iterator_tag iterator_category
Definition: MachineRegisterInfo.h:1141
llvm::MachineRegisterInfo::dumpUses
void dumpUses(Register RegNo) const
Definition: MachineRegisterInfo.cpp:505
llvm::MachineRegisterInfo::livein_end
livein_iterator livein_end() const
Definition: MachineRegisterInfo.h:994
llvm::MachineRegisterInfo::moveOperands
void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps)
Move NumOps operands from Src to Dst, updating use-def lists as needed.
Definition: MachineRegisterInfo.cpp:333
llvm::MachineRegisterInfo::reg_bundle_nodbg_end
static reg_bundle_nodbg_iterator reg_bundle_nodbg_end()
Definition: MachineRegisterInfo.h:388
llvm::MachineRegisterInfo::use_instr_end
static use_instr_iterator use_instr_end()
Definition: MachineRegisterInfo.h:502
TargetRegisterInfo.h
llvm::MachineRegisterInfo::EmitLiveInCopies
void EmitLiveInCopies(MachineBasicBlock *EntryMBB, const TargetRegisterInfo &TRI, const TargetInstrInfo &TII)
EmitLiveInCopies - Emit copies to initialize livein virtual registers into the given entry block.
Definition: MachineRegisterInfo.cpp:468
llvm::MachineRegisterInfo::setRegClass
void setRegClass(Register Reg, const TargetRegisterClass *RC)
setRegClass - Set the register class of the specified virtual register.
Definition: MachineRegisterInfo.cpp:57
llvm::MCRegAliasIterator
MCRegAliasIterator enumerates all registers aliasing Reg.
Definition: MCRegisterInfo.h:788
llvm::MachineRegisterInfo::getRegAllocationHint
std::pair< Register, Register > getRegAllocationHint(Register VReg) const
getRegAllocationHint - Return the register allocation hint for the specified virtual register.
Definition: MachineRegisterInfo.h:822
llvm::MachineRegisterInfo::verifyUseLists
void verifyUseLists() const
Verify the use list of all registers.
Definition: MachineRegisterInfo.cpp:255
llvm::MachineRegisterInfo::use_instr_nodbg_iterator
defusechain_instr_iterator< true, false, true, false, true, false > use_instr_nodbg_iterator
use_instr_nodbg_iterator/use_instr_nodbg_begin/use_instr_nodbg_end - Walk all uses of the specified r...
Definition: MachineRegisterInfo.h:556
llvm::MachineRegisterInfo::Delegate::~Delegate
virtual ~Delegate()=default
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24
llvm::SmallPtrSetImpl::insert
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
Definition: SmallPtrSet.h:365
llvm::MachineRegisterInfo::defusechain_iterator::operator++
defusechain_iterator & operator++()
Definition: MachineRegisterInfo.h:1087
llvm::LLT
Definition: LowLevelTypeImpl.h:39