LLVM  15.0.0git
MachineRegisterInfo.h
Go to the documentation of this file.
1 //===- llvm/CodeGen/MachineRegisterInfo.h -----------------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the MachineRegisterInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_CODEGEN_MACHINEREGISTERINFO_H
14 #define LLVM_CODEGEN_MACHINEREGISTERINFO_H
15 
16 #include "llvm/ADT/ArrayRef.h"
17 #include "llvm/ADT/BitVector.h"
18 #include "llvm/ADT/IndexedMap.h"
19 #include "llvm/ADT/PointerUnion.h"
20 #include "llvm/ADT/SmallVector.h"
21 #include "llvm/ADT/StringSet.h"
30 #include "llvm/MC/LaneBitmask.h"
31 #include <cassert>
32 #include <cstddef>
33 #include <cstdint>
34 #include <iterator>
35 #include <memory>
36 #include <utility>
37 #include <vector>
38 
39 namespace llvm {
40 
41 class PSetIterator;
42 
43 /// Convenient type to represent either a register class or a register bank.
44 using RegClassOrRegBank =
46 
47 /// MachineRegisterInfo - Keep track of information for virtual and physical
48 /// registers, including vreg register classes, use/def chains for registers,
49 /// etc.
51 public:
52  class Delegate {
53  virtual void anchor();
54 
55  public:
56  virtual ~Delegate() = default;
57 
58  virtual void MRI_NoteNewVirtualRegister(Register Reg) = 0;
59  };
60 
61 private:
62  MachineFunction *MF;
63  Delegate *TheDelegate = nullptr;
64 
65  /// True if subregister liveness is tracked.
66  const bool TracksSubRegLiveness;
67 
68  /// VRegInfo - Information we keep for each virtual register.
69  ///
70  /// Each element in this list contains the register class of the vreg and the
71  /// start of the use/def list for the register.
74  VRegInfo;
75 
76  /// Map for recovering vreg name from vreg number.
77  /// This map is used by the MIR Printer.
79 
80  /// StringSet that is used to unique vreg names.
81  StringSet<> VRegNames;
82 
83  /// The flag is true upon \p UpdatedCSRs initialization
84  /// and false otherwise.
85  bool IsUpdatedCSRsInitialized = false;
86 
87  /// Contains the updated callee saved register list.
88  /// As opposed to the static list defined in register info,
89  /// all registers that were disabled are removed from the list.
90  SmallVector<MCPhysReg, 16> UpdatedCSRs;
91 
92  /// RegAllocHints - This vector records register allocation hints for
93  /// virtual registers. For each virtual register, it keeps a pair of hint
94  /// type and hints vector making up the allocation hints. Only the first
95  /// hint may be target specific, and in that case this is reflected by the
96  /// first member of the pair being non-zero. If the hinted register is
97  /// virtual, it means the allocator should prefer the physical register
98  /// allocated to it if any.
100  VirtReg2IndexFunctor> RegAllocHints;
101 
102  /// PhysRegUseDefLists - This is an array of the head of the use/def list for
103  /// physical registers.
104  std::unique_ptr<MachineOperand *[]> PhysRegUseDefLists;
105 
106  /// getRegUseDefListHead - Return the head pointer for the register use/def
107  /// list for the specified virtual or physical register.
108  MachineOperand *&getRegUseDefListHead(Register RegNo) {
109  if (RegNo.isVirtual())
110  return VRegInfo[RegNo.id()].second;
111  return PhysRegUseDefLists[RegNo.id()];
112  }
113 
114  MachineOperand *getRegUseDefListHead(Register RegNo) const {
115  if (RegNo.isVirtual())
116  return VRegInfo[RegNo.id()].second;
117  return PhysRegUseDefLists[RegNo.id()];
118  }
119 
120  /// Get the next element in the use-def chain.
121  static MachineOperand *getNextOperandForReg(const MachineOperand *MO) {
122  assert(MO && MO->isReg() && "This is not a register operand!");
123  return MO->Contents.Reg.Next;
124  }
125 
126  /// UsedPhysRegMask - Additional used physregs including aliases.
127  /// This bit vector represents all the registers clobbered by function calls.
128  BitVector UsedPhysRegMask;
129 
130  /// ReservedRegs - This is a bit vector of reserved registers. The target
131  /// may change its mind about which registers should be reserved. This
132  /// vector is the frozen set of reserved registers when register allocation
133  /// started.
134  BitVector ReservedRegs;
135 
136  using VRegToTypeMap = IndexedMap<LLT, VirtReg2IndexFunctor>;
137  /// Map generic virtual registers to their low-level type.
138  VRegToTypeMap VRegToType;
139 
140  /// Keep track of the physical registers that are live in to the function.
141  /// Live in values are typically arguments in registers. LiveIn values are
142  /// allowed to have virtual registers associated with them, stored in the
143  /// second element.
144  std::vector<std::pair<MCRegister, Register>> LiveIns;
145 
146 public:
147  explicit MachineRegisterInfo(MachineFunction *MF);
148  MachineRegisterInfo(const MachineRegisterInfo &) = delete;
150 
152  return MF->getSubtarget().getRegisterInfo();
153  }
154 
155  void resetDelegate(Delegate *delegate) {
156  // Ensure another delegate does not take over unless the current
157  // delegate first unattaches itself. If we ever need to multicast
158  // notifications, we will need to change to using a list.
159  assert(TheDelegate == delegate &&
160  "Only the current delegate can perform reset!");
161  TheDelegate = nullptr;
162  }
163 
164  void setDelegate(Delegate *delegate) {
165  assert(delegate && !TheDelegate &&
166  "Attempted to set delegate to null, or to change it without "
167  "first resetting it!");
168 
169  TheDelegate = delegate;
170  }
171 
172  //===--------------------------------------------------------------------===//
173  // Function State
174  //===--------------------------------------------------------------------===//
175 
176  // isSSA - Returns true when the machine function is in SSA form. Early
177  // passes require the machine function to be in SSA form where every virtual
178  // register has a single defining instruction.
179  //
180  // The TwoAddressInstructionPass and PHIElimination passes take the machine
181  // function out of SSA form when they introduce multiple defs per virtual
182  // register.
183  bool isSSA() const {
184  return MF->getProperties().hasProperty(
186  }
187 
188  // leaveSSA - Indicates that the machine function is no longer in SSA form.
189  void leaveSSA() {
191  }
192 
193  /// tracksLiveness - Returns true when tracking register liveness accurately.
194  /// (see MachineFUnctionProperties::Property description for details)
195  bool tracksLiveness() const {
196  return MF->getProperties().hasProperty(
198  }
199 
200  /// invalidateLiveness - Indicates that register liveness is no longer being
201  /// tracked accurately.
202  ///
203  /// This should be called by late passes that invalidate the liveness
204  /// information.
206  MF->getProperties().reset(
208  }
209 
210  /// Returns true if liveness for register class @p RC should be tracked at
211  /// the subregister level.
214  }
216  assert(VReg.isVirtual() && "Must pass a VReg");
217  return shouldTrackSubRegLiveness(*getRegClass(VReg));
218  }
219  bool subRegLivenessEnabled() const {
220  return TracksSubRegLiveness;
221  }
222 
223  //===--------------------------------------------------------------------===//
224  // Register Info
225  //===--------------------------------------------------------------------===//
226 
227  /// Returns true if the updated CSR list was initialized and false otherwise.
228  bool isUpdatedCSRsInitialized() const { return IsUpdatedCSRsInitialized; }
229 
230  /// Returns true if a register can be used as an argument to a function.
231  bool isArgumentRegister(const MachineFunction &MF, MCRegister Reg) const;
232 
233  /// Returns true if a register is a fixed register.
234  bool isFixedRegister(const MachineFunction &MF, MCRegister Reg) const;
235 
236  /// Returns true if a register is a general purpose register.
238  MCRegister Reg) const;
239 
240  /// Disables the register from the list of CSRs.
241  /// I.e. the register will not appear as part of the CSR mask.
242  /// \see UpdatedCalleeSavedRegs.
244 
245  /// Returns list of callee saved registers.
246  /// The function returns the updated CSR list (after taking into account
247  /// registers that are disabled from the CSR list).
248  const MCPhysReg *getCalleeSavedRegs() const;
249 
250  /// Sets the updated Callee Saved Registers list.
251  /// Notice that it will override ant previously disabled/saved CSRs.
253 
254  // Strictly for use by MachineInstr.cpp.
256 
257  // Strictly for use by MachineInstr.cpp.
259 
260  // Strictly for use by MachineInstr.cpp.
261  void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps);
262 
263  /// Verify the sanity of the use list for Reg.
264  void verifyUseList(Register Reg) const;
265 
266  /// Verify the use list of all registers.
267  void verifyUseLists() const;
268 
269  /// reg_begin/reg_end - Provide iteration support to walk over all definitions
270  /// and uses of a register within the MachineFunction that corresponds to this
271  /// MachineRegisterInfo object.
272  template<bool Uses, bool Defs, bool SkipDebug,
273  bool ByOperand, bool ByInstr, bool ByBundle>
275  template<bool Uses, bool Defs, bool SkipDebug,
276  bool ByOperand, bool ByInstr, bool ByBundle>
278 
279  // Make it a friend so it can access getNextOperandForReg().
280  template<bool, bool, bool, bool, bool, bool>
281  friend class defusechain_iterator;
282  template<bool, bool, bool, bool, bool, bool>
284 
285  /// reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specified
286  /// register.
287  using reg_iterator =
290  return reg_iterator(getRegUseDefListHead(RegNo));
291  }
292  static reg_iterator reg_end() { return reg_iterator(nullptr); }
293 
295  return make_range(reg_begin(Reg), reg_end());
296  }
297 
298  /// reg_instr_iterator/reg_instr_begin/reg_instr_end - Walk all defs and uses
299  /// of the specified register, stepping by MachineInstr.
300  using reg_instr_iterator =
303  return reg_instr_iterator(getRegUseDefListHead(RegNo));
304  }
306  return reg_instr_iterator(nullptr);
307  }
308 
312  }
313 
314  /// reg_bundle_iterator/reg_bundle_begin/reg_bundle_end - Walk all defs and uses
315  /// of the specified register, stepping by bundle.
316  using reg_bundle_iterator =
319  return reg_bundle_iterator(getRegUseDefListHead(RegNo));
320  }
322  return reg_bundle_iterator(nullptr);
323  }
324 
327  }
328 
329  /// reg_empty - Return true if there are no instructions using or defining the
330  /// specified register (it may be live-in).
331  bool reg_empty(Register RegNo) const { return reg_begin(RegNo) == reg_end(); }
332 
333  /// reg_nodbg_iterator/reg_nodbg_begin/reg_nodbg_end - Walk all defs and uses
334  /// of the specified register, skipping those marked as Debug.
335  using reg_nodbg_iterator =
338  return reg_nodbg_iterator(getRegUseDefListHead(RegNo));
339  }
341  return reg_nodbg_iterator(nullptr);
342  }
343 
347  }
348 
349  /// reg_instr_nodbg_iterator/reg_instr_nodbg_begin/reg_instr_nodbg_end - Walk
350  /// all defs and uses of the specified register, stepping by MachineInstr,
351  /// skipping those marked as Debug.
355  return reg_instr_nodbg_iterator(getRegUseDefListHead(RegNo));
356  }
358  return reg_instr_nodbg_iterator(nullptr);
359  }
360 
364  }
365 
366  /// reg_bundle_nodbg_iterator/reg_bundle_nodbg_begin/reg_bundle_nodbg_end - Walk
367  /// all defs and uses of the specified register, stepping by bundle,
368  /// skipping those marked as Debug.
372  return reg_bundle_nodbg_iterator(getRegUseDefListHead(RegNo));
373  }
375  return reg_bundle_nodbg_iterator(nullptr);
376  }
377 
381  }
382 
383  /// reg_nodbg_empty - Return true if the only instructions using or defining
384  /// Reg are Debug instructions.
385  bool reg_nodbg_empty(Register RegNo) const {
386  return reg_nodbg_begin(RegNo) == reg_nodbg_end();
387  }
388 
389  /// def_iterator/def_begin/def_end - Walk all defs of the specified register.
390  using def_iterator =
393  return def_iterator(getRegUseDefListHead(RegNo));
394  }
395  static def_iterator def_end() { return def_iterator(nullptr); }
396 
398  return make_range(def_begin(Reg), def_end());
399  }
400 
401  /// def_instr_iterator/def_instr_begin/def_instr_end - Walk all defs of the
402  /// specified register, stepping by MachineInst.
403  using def_instr_iterator =
406  return def_instr_iterator(getRegUseDefListHead(RegNo));
407  }
409  return def_instr_iterator(nullptr);
410  }
411 
415  }
416 
417  /// def_bundle_iterator/def_bundle_begin/def_bundle_end - Walk all defs of the
418  /// specified register, stepping by bundle.
419  using def_bundle_iterator =
422  return def_bundle_iterator(getRegUseDefListHead(RegNo));
423  }
425  return def_bundle_iterator(nullptr);
426  }
427 
430  }
431 
432  /// def_empty - Return true if there are no instructions defining the
433  /// specified register (it may be live-in).
434  bool def_empty(Register RegNo) const { return def_begin(RegNo) == def_end(); }
435 
437  return VReg2Name.inBounds(Reg) ? StringRef(VReg2Name[Reg]) : "";
438  }
439 
441  assert((Name.empty() || VRegNames.find(Name) == VRegNames.end()) &&
442  "Named VRegs Must be Unique.");
443  if (!Name.empty()) {
444  VRegNames.insert(Name);
445  VReg2Name.grow(Reg);
446  VReg2Name[Reg] = Name.str();
447  }
448  }
449 
450  /// Return true if there is exactly one operand defining the specified
451  /// register.
452  bool hasOneDef(Register RegNo) const {
453  return hasSingleElement(def_operands(RegNo));
454  }
455 
456  /// Returns the defining operand if there is exactly one operand defining the
457  /// specified register, otherwise nullptr.
459  def_iterator DI = def_begin(Reg);
460  if (DI == def_end()) // No defs.
461  return nullptr;
462 
463  def_iterator OneDef = DI;
464  if (++DI == def_end())
465  return &*OneDef;
466  return nullptr; // Multiple defs.
467  }
468 
469  /// use_iterator/use_begin/use_end - Walk all uses of the specified register.
470  using use_iterator =
473  return use_iterator(getRegUseDefListHead(RegNo));
474  }
475  static use_iterator use_end() { return use_iterator(nullptr); }
476 
478  return make_range(use_begin(Reg), use_end());
479  }
480 
481  /// use_instr_iterator/use_instr_begin/use_instr_end - Walk all uses of the
482  /// specified register, stepping by MachineInstr.
483  using use_instr_iterator =
486  return use_instr_iterator(getRegUseDefListHead(RegNo));
487  }
489  return use_instr_iterator(nullptr);
490  }
491 
495  }
496 
497  /// use_bundle_iterator/use_bundle_begin/use_bundle_end - Walk all uses of the
498  /// specified register, stepping by bundle.
499  using use_bundle_iterator =
502  return use_bundle_iterator(getRegUseDefListHead(RegNo));
503  }
505  return use_bundle_iterator(nullptr);
506  }
507 
510  }
511 
512  /// use_empty - Return true if there are no instructions using the specified
513  /// register.
514  bool use_empty(Register RegNo) const { return use_begin(RegNo) == use_end(); }
515 
516  /// hasOneUse - Return true if there is exactly one instruction using the
517  /// specified register.
518  bool hasOneUse(Register RegNo) const {
519  return hasSingleElement(use_operands(RegNo));
520  }
521 
522  /// use_nodbg_iterator/use_nodbg_begin/use_nodbg_end - Walk all uses of the
523  /// specified register, skipping those marked as Debug.
524  using use_nodbg_iterator =
527  return use_nodbg_iterator(getRegUseDefListHead(RegNo));
528  }
530  return use_nodbg_iterator(nullptr);
531  }
532 
536  }
537 
538  /// use_instr_nodbg_iterator/use_instr_nodbg_begin/use_instr_nodbg_end - Walk
539  /// all uses of the specified register, stepping by MachineInstr, skipping
540  /// those marked as Debug.
544  return use_instr_nodbg_iterator(getRegUseDefListHead(RegNo));
545  }
547  return use_instr_nodbg_iterator(nullptr);
548  }
549 
553  }
554 
555  /// use_bundle_nodbg_iterator/use_bundle_nodbg_begin/use_bundle_nodbg_end - Walk
556  /// all uses of the specified register, stepping by bundle, skipping
557  /// those marked as Debug.
561  return use_bundle_nodbg_iterator(getRegUseDefListHead(RegNo));
562  }
564  return use_bundle_nodbg_iterator(nullptr);
565  }
566 
570  }
571 
572  /// use_nodbg_empty - Return true if there are no non-Debug instructions
573  /// using the specified register.
574  bool use_nodbg_empty(Register RegNo) const {
575  return use_nodbg_begin(RegNo) == use_nodbg_end();
576  }
577 
578  /// hasOneNonDBGUse - Return true if there is exactly one non-Debug
579  /// use of the specified register.
580  bool hasOneNonDBGUse(Register RegNo) const;
581 
582  /// hasOneNonDBGUse - Return true if there is exactly one non-Debug
583  /// instruction using the specified register. Said instruction may have
584  /// multiple uses.
585  bool hasOneNonDBGUser(Register RegNo) const;
586 
587  /// replaceRegWith - Replace all instances of FromReg with ToReg in the
588  /// machine function. This is like llvm-level X->replaceAllUsesWith(Y),
589  /// except that it also changes any definitions of the register as well.
590  ///
591  /// Note that it is usually necessary to first constrain ToReg's register
592  /// class and register bank to match the FromReg constraints using one of the
593  /// methods:
594  ///
595  /// constrainRegClass(ToReg, getRegClass(FromReg))
596  /// constrainRegAttrs(ToReg, FromReg)
597  /// RegisterBankInfo::constrainGenericRegister(ToReg,
598  /// *MRI.getRegClass(FromReg), MRI)
599  ///
600  /// These functions will return a falsy result if the virtual registers have
601  /// incompatible constraints.
602  ///
603  /// Note that if ToReg is a physical register the function will replace and
604  /// apply sub registers to ToReg in order to obtain a final/proper physical
605  /// register.
606  void replaceRegWith(Register FromReg, Register ToReg);
607 
608  /// getVRegDef - Return the machine instr that defines the specified virtual
609  /// register or null if none is found. This assumes that the code is in SSA
610  /// form, so there should only be one definition.
612 
613  /// getUniqueVRegDef - Return the unique machine instr that defines the
614  /// specified virtual register or null if none is found. If there are
615  /// multiple definitions or no definition, return null.
617 
618  /// clearKillFlags - Iterate over all the uses of the given register and
619  /// clear the kill flag from the MachineOperand. This function is used by
620  /// optimization passes which extend register lifetimes and need only
621  /// preserve conservative kill flag information.
622  void clearKillFlags(Register Reg) const;
623 
624  void dumpUses(Register RegNo) const;
625 
626  /// Returns true if PhysReg is unallocatable and constant throughout the
627  /// function. Writing to a constant register has no effect.
628  bool isConstantPhysReg(MCRegister PhysReg) const;
629 
630  /// Get an iterator over the pressure sets affected by the given physical or
631  /// virtual register. If RegUnit is physical, it must be a register unit (from
632  /// MCRegUnitIterator).
633  PSetIterator getPressureSets(Register RegUnit) const;
634 
635  //===--------------------------------------------------------------------===//
636  // Virtual Register Info
637  //===--------------------------------------------------------------------===//
638 
639  /// Return the register class of the specified virtual register.
640  /// This shouldn't be used directly unless \p Reg has a register class.
641  /// \see getRegClassOrNull when this might happen.
643  assert(VRegInfo[Reg.id()].first.is<const TargetRegisterClass *>() &&
644  "Register class not set, wrong accessor");
645  return VRegInfo[Reg.id()].first.get<const TargetRegisterClass *>();
646  }
647 
648  /// Return the register class of \p Reg, or null if Reg has not been assigned
649  /// a register class yet.
650  ///
651  /// \note A null register class can only happen when these two
652  /// conditions are met:
653  /// 1. Generic virtual registers are created.
654  /// 2. The machine function has not completely been through the
655  /// instruction selection process.
656  /// None of this condition is possible without GlobalISel for now.
657  /// In other words, if GlobalISel is not used or if the query happens after
658  /// the select pass, using getRegClass is safe.
660  const RegClassOrRegBank &Val = VRegInfo[Reg].first;
661  return Val.dyn_cast<const TargetRegisterClass *>();
662  }
663 
664  /// Return the register bank of \p Reg, or null if Reg has not been assigned
665  /// a register bank or has been assigned a register class.
666  /// \note It is possible to get the register bank from the register class via
667  /// RegisterBankInfo::getRegBankFromRegClass.
669  const RegClassOrRegBank &Val = VRegInfo[Reg].first;
670  return Val.dyn_cast<const RegisterBank *>();
671  }
672 
673  /// Return the register bank or register class of \p Reg.
674  /// \note Before the register bank gets assigned (i.e., before the
675  /// RegBankSelect pass) \p Reg may not have either.
677  return VRegInfo[Reg].first;
678  }
679 
680  /// setRegClass - Set the register class of the specified virtual register.
681  void setRegClass(Register Reg, const TargetRegisterClass *RC);
682 
683  /// Set the register bank to \p RegBank for \p Reg.
684  void setRegBank(Register Reg, const RegisterBank &RegBank);
685 
687  const RegClassOrRegBank &RCOrRB){
688  VRegInfo[Reg].first = RCOrRB;
689  }
690 
691  /// constrainRegClass - Constrain the register class of the specified virtual
692  /// register to be a common subclass of RC and the current register class,
693  /// but only if the new class has at least MinNumRegs registers. Return the
694  /// new register class, or NULL if no such class exists.
695  /// This should only be used when the constraint is known to be trivial, like
696  /// GR32 -> GR32_NOSP. Beware of increasing register pressure.
697  ///
698  /// \note Assumes that the register has a register class assigned.
699  /// Use RegisterBankInfo::constrainGenericRegister in GlobalISel's
700  /// InstructionSelect pass and constrainRegAttrs in every other pass,
701  /// including non-select passes of GlobalISel, instead.
703  const TargetRegisterClass *RC,
704  unsigned MinNumRegs = 0);
705 
706  /// Constrain the register class or the register bank of the virtual register
707  /// \p Reg (and low-level type) to be a common subclass or a common bank of
708  /// both registers provided respectively (and a common low-level type). Do
709  /// nothing if any of the attributes (classes, banks, or low-level types) of
710  /// the registers are deemed incompatible, or if the resulting register will
711  /// have a class smaller than before and of size less than \p MinNumRegs.
712  /// Return true if such register attributes exist, false otherwise.
713  ///
714  /// \note Use this method instead of constrainRegClass and
715  /// RegisterBankInfo::constrainGenericRegister everywhere but SelectionDAG
716  /// ISel / FastISel and GlobalISel's InstructionSelect pass respectively.
717  bool constrainRegAttrs(Register Reg, Register ConstrainingReg,
718  unsigned MinNumRegs = 0);
719 
720  /// recomputeRegClass - Try to find a legal super-class of Reg's register
721  /// class that still satisfies the constraints from the instructions using
722  /// Reg. Returns true if Reg was upgraded.
723  ///
724  /// This method can be used after constraints have been removed from a
725  /// virtual register, for example after removing instructions or splitting
726  /// the live range.
728 
729  /// createVirtualRegister - Create and return a new virtual register in the
730  /// function with the specified register class.
732  StringRef Name = "");
733 
734  /// Create and return a new virtual register in the function with the same
735  /// attributes as the given register.
737 
738  /// Get the low-level type of \p Reg or LLT{} if Reg is not a generic
739  /// (target independent) virtual register.
741  if (Register::isVirtualRegister(Reg) && VRegToType.inBounds(Reg))
742  return VRegToType[Reg];
743  return LLT{};
744  }
745 
746  /// Set the low-level type of \p VReg to \p Ty.
747  void setType(Register VReg, LLT Ty);
748 
749  /// Create and return a new generic virtual register with low-level
750  /// type \p Ty.
752 
753  /// Remove all types associated to virtual registers (after instruction
754  /// selection and constraining of all generic virtual registers).
755  void clearVirtRegTypes();
756 
757  /// Creates a new virtual register that has no register class, register bank
758  /// or size assigned yet. This is only allowed to be used
759  /// temporarily while constructing machine instructions. Most operations are
760  /// undefined on an incomplete register until one of setRegClass(),
761  /// setRegBank() or setSize() has been called on it.
763 
764  /// getNumVirtRegs - Return the number of virtual registers created.
765  unsigned getNumVirtRegs() const { return VRegInfo.size(); }
766 
767  /// clearVirtRegs - Remove all virtual registers (after physreg assignment).
768  void clearVirtRegs();
769 
770  /// setRegAllocationHint - Specify a register allocation hint for the
771  /// specified virtual register. This is typically used by target, and in case
772  /// of an earlier hint it will be overwritten.
773  void setRegAllocationHint(Register VReg, unsigned Type, Register PrefReg) {
774  assert(VReg.isVirtual());
775  RegAllocHints[VReg].first = Type;
776  RegAllocHints[VReg].second.clear();
777  RegAllocHints[VReg].second.push_back(PrefReg);
778  }
779 
780  /// addRegAllocationHint - Add a register allocation hint to the hints
781  /// vector for VReg.
782  void addRegAllocationHint(Register VReg, Register PrefReg) {
784  RegAllocHints[VReg].second.push_back(PrefReg);
785  }
786 
787  /// Specify the preferred (target independent) register allocation hint for
788  /// the specified virtual register.
789  void setSimpleHint(Register VReg, Register PrefReg) {
790  setRegAllocationHint(VReg, /*Type=*/0, PrefReg);
791  }
792 
794  assert (!RegAllocHints[VReg].first &&
795  "Expected to clear a non-target hint!");
796  RegAllocHints[VReg].second.clear();
797  }
798 
799  /// getRegAllocationHint - Return the register allocation hint for the
800  /// specified virtual register. If there are many hints, this returns the
801  /// one with the greatest weight.
802  std::pair<Register, Register>
804  assert(VReg.isVirtual());
805  Register BestHint = (RegAllocHints[VReg.id()].second.size() ?
806  RegAllocHints[VReg.id()].second[0] : Register());
807  return std::pair<Register, Register>(RegAllocHints[VReg.id()].first,
808  BestHint);
809  }
810 
811  /// getSimpleHint - same as getRegAllocationHint except it will only return
812  /// a target independent hint.
814  assert(VReg.isVirtual());
815  std::pair<Register, Register> Hint = getRegAllocationHint(VReg);
816  return Hint.first ? Register() : Hint.second;
817  }
818 
819  /// getRegAllocationHints - Return a reference to the vector of all
820  /// register allocation hints for VReg.
821  const std::pair<Register, SmallVector<Register, 4>>
823  assert(VReg.isVirtual());
824  return RegAllocHints[VReg];
825  }
826 
827  /// markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the
828  /// specified register as undefined which causes the DBG_VALUE to be
829  /// deleted during LiveDebugVariables analysis.
831 
832  /// updateDbgUsersToReg - Update a collection of debug instructions
833  /// to refer to the designated register.
836  // If this operand is a register, check whether it overlaps with OldReg.
837  // If it does, replace with NewReg.
838  auto UpdateOp = [this, &NewReg, &OldReg](MachineOperand &Op) {
839  if (Op.isReg() &&
840  getTargetRegisterInfo()->regsOverlap(Op.getReg(), OldReg))
841  Op.setReg(NewReg);
842  };
843 
844  // Iterate through (possibly several) operands to DBG_VALUEs and update
845  // each. For DBG_PHIs, only one operand will be present.
846  for (MachineInstr *MI : Users) {
847  if (MI->isDebugValue()) {
848  for (auto &Op : MI->debug_operands())
849  UpdateOp(Op);
850  assert(MI->hasDebugOperandForReg(NewReg) &&
851  "Expected debug value to have some overlap with OldReg");
852  } else if (MI->isDebugPHI()) {
853  UpdateOp(MI->getOperand(0));
854  } else {
855  llvm_unreachable("Non-DBG_VALUE, Non-DBG_PHI debug instr updated");
856  }
857  }
858  }
859 
860  /// Return true if the specified register is modified in this function.
861  /// This checks that no defining machine operands exist for the register or
862  /// any of its aliases. Definitions found on functions marked noreturn are
863  /// ignored, to consider them pass 'true' for optional parameter
864  /// SkipNoReturnDef. The register is also considered modified when it is set
865  /// in the UsedPhysRegMask.
866  bool isPhysRegModified(MCRegister PhysReg, bool SkipNoReturnDef = false) const;
867 
868  /// Return true if the specified register is modified or read in this
869  /// function. This checks that no machine operands exist for the register or
870  /// any of its aliases. If SkipRegMaskTest is false, the register is
871  /// considered used when it is set in the UsedPhysRegMask.
872  bool isPhysRegUsed(MCRegister PhysReg, bool SkipRegMaskTest = false) const;
873 
874  /// addPhysRegsUsedFromRegMask - Mark any registers not in RegMask as used.
875  /// This corresponds to the bit mask attached to register mask operands.
876  void addPhysRegsUsedFromRegMask(const uint32_t *RegMask) {
877  UsedPhysRegMask.setBitsNotInMask(RegMask);
878  }
879 
880  const BitVector &getUsedPhysRegsMask() const { return UsedPhysRegMask; }
881 
882  //===--------------------------------------------------------------------===//
883  // Reserved Register Info
884  //===--------------------------------------------------------------------===//
885  //
886  // The set of reserved registers must be invariant during register
887  // allocation. For example, the target cannot suddenly decide it needs a
888  // frame pointer when the register allocator has already used the frame
889  // pointer register for something else.
890  //
891  // These methods can be used by target hooks like hasFP() to avoid changing
892  // the reserved register set during register allocation.
893 
894  /// freezeReservedRegs - Called by the register allocator to freeze the set
895  /// of reserved registers before allocation begins.
896  void freezeReservedRegs(const MachineFunction&);
897 
898  /// reservedRegsFrozen - Returns true after freezeReservedRegs() was called
899  /// to ensure the set of reserved registers stays constant.
900  bool reservedRegsFrozen() const {
901  return !ReservedRegs.empty();
902  }
903 
904  /// canReserveReg - Returns true if PhysReg can be used as a reserved
905  /// register. Any register can be reserved before freezeReservedRegs() is
906  /// called.
907  bool canReserveReg(MCRegister PhysReg) const {
908  return !reservedRegsFrozen() || ReservedRegs.test(PhysReg);
909  }
910 
911  /// getReservedRegs - Returns a reference to the frozen set of reserved
912  /// registers. This method should always be preferred to calling
913  /// TRI::getReservedRegs() when possible.
914  const BitVector &getReservedRegs() const {
916  "Reserved registers haven't been frozen yet. "
917  "Use TRI::getReservedRegs().");
918  return ReservedRegs;
919  }
920 
921  /// isReserved - Returns true when PhysReg is a reserved register.
922  ///
923  /// Reserved registers may belong to an allocatable register class, but the
924  /// target has explicitly requested that they are not used.
925  bool isReserved(MCRegister PhysReg) const {
926  return getReservedRegs().test(PhysReg.id());
927  }
928 
929  /// Returns true when the given register unit is considered reserved.
930  ///
931  /// Register units are considered reserved when for at least one of their
932  /// root registers, the root register and all super registers are reserved.
933  /// This currently iterates the register hierarchy and may be slower than
934  /// expected.
935  bool isReservedRegUnit(unsigned Unit) const;
936 
937  /// isAllocatable - Returns true when PhysReg belongs to an allocatable
938  /// register class and it hasn't been reserved.
939  ///
940  /// Allocatable registers may show up in the allocation order of some virtual
941  /// register, so a register allocator needs to track its liveness and
942  /// availability.
943  bool isAllocatable(MCRegister PhysReg) const {
944  return getTargetRegisterInfo()->isInAllocatableClass(PhysReg) &&
945  !isReserved(PhysReg);
946  }
947 
948  //===--------------------------------------------------------------------===//
949  // LiveIn Management
950  //===--------------------------------------------------------------------===//
951 
952  /// addLiveIn - Add the specified register as a live-in. Note that it
953  /// is an error to add the same register to the same set more than once.
955  LiveIns.push_back(std::make_pair(Reg, vreg));
956  }
957 
958  // Iteration support for the live-ins set. It's kept in sorted order
959  // by register number.
960  using livein_iterator =
961  std::vector<std::pair<MCRegister,Register>>::const_iterator;
962  livein_iterator livein_begin() const { return LiveIns.begin(); }
963  livein_iterator livein_end() const { return LiveIns.end(); }
964  bool livein_empty() const { return LiveIns.empty(); }
965 
967  return LiveIns;
968  }
969 
970  bool isLiveIn(Register Reg) const;
971 
972  /// getLiveInPhysReg - If VReg is a live-in virtual register, return the
973  /// corresponding live-in physical register.
975 
976  /// getLiveInVirtReg - If PReg is a live-in physical register, return the
977  /// corresponding live-in virtual register.
979 
980  /// EmitLiveInCopies - Emit copies to initialize livein virtual registers
981  /// into the given entry block.
982  void EmitLiveInCopies(MachineBasicBlock *EntryMBB,
983  const TargetRegisterInfo &TRI,
984  const TargetInstrInfo &TII);
985 
986  /// Returns a mask covering all bits that can appear in lane masks of
987  /// subregisters of the virtual register @p Reg.
989 
990  /// defusechain_iterator - This class provides iterator support for machine
991  /// operands in the function that use or define a specific register. If
992  /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it
993  /// returns defs. If neither are true then you are silly and it always
994  /// returns end(). If SkipDebug is true it skips uses marked Debug
995  /// when incrementing.
996  template <bool ReturnUses, bool ReturnDefs, bool SkipDebug, bool ByOperand,
997  bool ByInstr, bool ByBundle>
998  class defusechain_iterator {
999  friend class MachineRegisterInfo;
1000 
1001  public:
1002  using iterator_category = std::forward_iterator_tag;
1004  using difference_type = std::ptrdiff_t;
1005  using pointer = value_type *;
1007 
1008  private:
1009  MachineOperand *Op = nullptr;
1010 
1011  explicit defusechain_iterator(MachineOperand *op) : Op(op) {
1012  // If the first node isn't one we're interested in, advance to one that
1013  // we are interested in.
1014  if (op) {
1015  if ((!ReturnUses && op->isUse()) ||
1016  (!ReturnDefs && op->isDef()) ||
1017  (SkipDebug && op->isDebug()))
1018  advance();
1019  }
1020  }
1021 
1022  void advance() {
1023  assert(Op && "Cannot increment end iterator!");
1024  Op = getNextOperandForReg(Op);
1025 
1026  // All defs come before the uses, so stop def_iterator early.
1027  if (!ReturnUses) {
1028  if (Op) {
1029  if (Op->isUse())
1030  Op = nullptr;
1031  else
1032  assert(!Op->isDebug() && "Can't have debug defs");
1033  }
1034  } else {
1035  // If this is an operand we don't care about, skip it.
1036  while (Op && ((!ReturnDefs && Op->isDef()) ||
1037  (SkipDebug && Op->isDebug())))
1038  Op = getNextOperandForReg(Op);
1039  }
1040  }
1041 
1042  public:
1043  defusechain_iterator() = default;
1044 
1045  bool operator==(const defusechain_iterator &x) const {
1046  return Op == x.Op;
1047  }
1048  bool operator!=(const defusechain_iterator &x) const {
1049  return !operator==(x);
1050  }
1051 
1052  /// atEnd - return true if this iterator is equal to reg_end() on the value.
1053  bool atEnd() const { return Op == nullptr; }
1054 
1055  // Iterator traversal: forward iteration only
1056  defusechain_iterator &operator++() { // Preincrement
1057  assert(Op && "Cannot increment end iterator!");
1058  if (ByOperand)
1059  advance();
1060  else if (ByInstr) {
1061  MachineInstr *P = Op->getParent();
1062  do {
1063  advance();
1064  } while (Op && Op->getParent() == P);
1065  } else if (ByBundle) {
1067  getBundleStart(Op->getParent()->getIterator());
1068  do {
1069  advance();
1070  } while (Op && getBundleStart(Op->getParent()->getIterator()) == P);
1071  }
1072 
1073  return *this;
1074  }
1075  defusechain_iterator operator++(int) { // Postincrement
1076  defusechain_iterator tmp = *this; ++*this; return tmp;
1077  }
1078 
1079  /// getOperandNo - Return the operand # of this MachineOperand in its
1080  /// MachineInstr.
1081  unsigned getOperandNo() const {
1082  assert(Op && "Cannot dereference end iterator!");
1083  return Op - &Op->getParent()->getOperand(0);
1084  }
1085 
1086  // Retrieve a reference to the current operand.
1088  assert(Op && "Cannot dereference end iterator!");
1089  return *Op;
1090  }
1091 
1093  assert(Op && "Cannot dereference end iterator!");
1094  return Op;
1095  }
1096  };
1097 
1098  /// defusechain_iterator - This class provides iterator support for machine
1099  /// operands in the function that use or define a specific register. If
1100  /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it
1101  /// returns defs. If neither are true then you are silly and it always
1102  /// returns end(). If SkipDebug is true it skips uses marked Debug
1103  /// when incrementing.
1104  template <bool ReturnUses, bool ReturnDefs, bool SkipDebug, bool ByOperand,
1105  bool ByInstr, bool ByBundle>
1107  friend class MachineRegisterInfo;
1108 
1109  public:
1110  using iterator_category = std::forward_iterator_tag;
1112  using difference_type = std::ptrdiff_t;
1113  using pointer = value_type *;
1115 
1116  private:
1117  MachineOperand *Op = nullptr;
1118 
1120  // If the first node isn't one we're interested in, advance to one that
1121  // we are interested in.
1122  if (op) {
1123  if ((!ReturnUses && op->isUse()) ||
1124  (!ReturnDefs && op->isDef()) ||
1125  (SkipDebug && op->isDebug()))
1126  advance();
1127  }
1128  }
1129 
1130  void advance() {
1131  assert(Op && "Cannot increment end iterator!");
1132  Op = getNextOperandForReg(Op);
1133 
1134  // All defs come before the uses, so stop def_iterator early.
1135  if (!ReturnUses) {
1136  if (Op) {
1137  if (Op->isUse())
1138  Op = nullptr;
1139  else
1140  assert(!Op->isDebug() && "Can't have debug defs");
1141  }
1142  } else {
1143  // If this is an operand we don't care about, skip it.
1144  while (Op && ((!ReturnDefs && Op->isDef()) ||
1145  (SkipDebug && Op->isDebug())))
1146  Op = getNextOperandForReg(Op);
1147  }
1148  }
1149 
1150  public:
1151  defusechain_instr_iterator() = default;
1152 
1154  return Op == x.Op;
1155  }
1157  return !operator==(x);
1158  }
1159 
1160  /// atEnd - return true if this iterator is equal to reg_end() on the value.
1161  bool atEnd() const { return Op == nullptr; }
1162 
1163  // Iterator traversal: forward iteration only
1165  assert(Op && "Cannot increment end iterator!");
1166  if (ByOperand)
1167  advance();
1168  else if (ByInstr) {
1169  MachineInstr *P = Op->getParent();
1170  do {
1171  advance();
1172  } while (Op && Op->getParent() == P);
1173  } else if (ByBundle) {
1175  getBundleStart(Op->getParent()->getIterator());
1176  do {
1177  advance();
1178  } while (Op && getBundleStart(Op->getParent()->getIterator()) == P);
1179  }
1180 
1181  return *this;
1182  }
1183  defusechain_instr_iterator operator++(int) { // Postincrement
1184  defusechain_instr_iterator tmp = *this; ++*this; return tmp;
1185  }
1186 
1187  // Retrieve a reference to the current operand.
1189  assert(Op && "Cannot dereference end iterator!");
1190  if (ByBundle)
1191  return *getBundleStart(Op->getParent()->getIterator());
1192  return *Op->getParent();
1193  }
1194 
1195  MachineInstr *operator->() const { return &operator*(); }
1196  };
1197 };
1198 
1199 /// Iterate over the pressure sets affected by the given physical or virtual
1200 /// register. If Reg is physical, it must be a register unit (from
1201 /// MCRegUnitIterator).
1203  const int *PSet = nullptr;
1204  unsigned Weight = 0;
1205 
1206 public:
1207  PSetIterator() = default;
1208 
1210  const TargetRegisterInfo *TRI = MRI->getTargetRegisterInfo();
1211  if (RegUnit.isVirtual()) {
1212  const TargetRegisterClass *RC = MRI->getRegClass(RegUnit);
1213  PSet = TRI->getRegClassPressureSets(RC);
1214  Weight = TRI->getRegClassWeight(RC).RegWeight;
1215  } else {
1216  PSet = TRI->getRegUnitPressureSets(RegUnit);
1217  Weight = TRI->getRegUnitWeight(RegUnit);
1218  }
1219  if (*PSet == -1)
1220  PSet = nullptr;
1221  }
1222 
1223  bool isValid() const { return PSet; }
1224 
1225  unsigned getWeight() const { return Weight; }
1226 
1227  unsigned operator*() const { return *PSet; }
1228 
1229  void operator++() {
1230  assert(isValid() && "Invalid PSetIterator.");
1231  ++PSet;
1232  if (*PSet == -1)
1233  PSet = nullptr;
1234  }
1235 };
1236 
1237 inline PSetIterator
1239  return PSetIterator(RegUnit, this);
1240 }
1241 
1242 } // end namespace llvm
1243 
1244 #endif // LLVM_CODEGEN_MACHINEREGISTERINFO_H
llvm::MachineRegisterInfo::addLiveIn
void addLiveIn(MCRegister Reg, Register vreg=Register())
addLiveIn - Add the specified register as a live-in.
Definition: MachineRegisterInfo.h:954
llvm::MachineRegisterInfo::def_instr_end
static def_instr_iterator def_instr_end()
Definition: MachineRegisterInfo.h:408
llvm::LaneBitmask
Definition: LaneBitmask.h:40
llvm::PSetIterator::PSetIterator
PSetIterator()=default
const_iterator
llvm::MachineRegisterInfo::markUsesInDebugValueAsUndef
void markUsesInDebugValueAsUndef(Register Reg) const
markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the specified register as undefined wh...
Definition: MachineRegisterInfo.cpp:528
IndexedMap.h
llvm::MachineFunctionProperties::hasProperty
bool hasProperty(Property P) const
Definition: MachineFunction.h:176
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:104
llvm::MachineRegisterInfo::def_begin
def_iterator def_begin(Register RegNo) const
Definition: MachineRegisterInfo.h:392
llvm::PSetIterator::isValid
bool isValid() const
Definition: MachineRegisterInfo.h:1223
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::MachineRegisterInfo::subRegLivenessEnabled
bool subRegLivenessEnabled() const
Definition: MachineRegisterInfo.h:219
llvm::MachineRegisterInfo::defusechain_instr_iterator::operator++
defusechain_instr_iterator operator++(int)
Definition: MachineRegisterInfo.h:1183
llvm::MachineRegisterInfo::isPhysRegUsed
bool isPhysRegUsed(MCRegister PhysReg, bool SkipRegMaskTest=false) const
Return true if the specified register is modified or read in this function.
Definition: MachineRegisterInfo.cpp:581
llvm::MachineRegisterInfo::use_instr_nodbg_end
static use_instr_nodbg_iterator use_instr_nodbg_end()
Definition: MachineRegisterInfo.h:546
llvm::MachineRegisterInfo::constrainRegAttrs
bool constrainRegAttrs(Register Reg, Register ConstrainingReg, unsigned MinNumRegs=0)
Constrain the register class or the register bank of the virtual register Reg (and low-level type) to...
Definition: MachineRegisterInfo.cpp:90
llvm::make_range
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
Definition: iterator_range.h:53
llvm::MachineRegisterInfo::shouldTrackSubRegLiveness
bool shouldTrackSubRegLiveness(const TargetRegisterClass &RC) const
Returns true if liveness for register class RC should be tracked at the subregister level.
Definition: MachineRegisterInfo.h:212
llvm::MachineRegisterInfo::createIncompleteVirtualRegister
Register createIncompleteVirtualRegister(StringRef Name="")
Creates a new virtual register that has no register class, register bank or size assigned yet.
Definition: MachineRegisterInfo.cpp:144
llvm::MachineRegisterInfo::createVirtualRegister
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
Definition: MachineRegisterInfo.cpp:156
llvm::MachineRegisterInfo::getVRegName
StringRef getVRegName(Register Reg) const
Definition: MachineRegisterInfo.h:436
llvm::VirtReg2IndexFunctor
Definition: TargetRegisterInfo.h:1271
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
llvm::MachineRegisterInfo::defusechain_iterator::iterator_category
std::forward_iterator_tag iterator_category
Definition: MachineRegisterInfo.h:1002
llvm::MachineRegisterInfo::defusechain_iterator::operator==
bool operator==(const defusechain_iterator &x) const
Definition: MachineRegisterInfo.h:1045
llvm::MachineRegisterInfo::recomputeRegClass
bool recomputeRegClass(Register Reg)
recomputeRegClass - Try to find a legal super-class of Reg's register class that still satisfies the ...
Definition: MachineRegisterInfo.cpp:120
P
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
Definition: README-SSE.txt:411
llvm::MachineRegisterInfo::def_bundle_begin
def_bundle_iterator def_bundle_begin(Register RegNo) const
Definition: MachineRegisterInfo.h:421
llvm::MachineRegisterInfo::disableCalleeSavedRegister
void disableCalleeSavedRegister(MCRegister Reg)
Disables the register from the list of CSRs.
Definition: MachineRegisterInfo.cpp:594
llvm::Register::id
unsigned id() const
Definition: Register.h:111
llvm::MachineRegisterInfo::reg_nodbg_bundles
iterator_range< reg_bundle_nodbg_iterator > reg_nodbg_bundles(Register Reg) const
Definition: MachineRegisterInfo.h:379
llvm::MachineRegisterInfo::def_instr_begin
def_instr_iterator def_instr_begin(Register RegNo) const
Definition: MachineRegisterInfo.h:405
op
#define op(i)
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1185
llvm::TargetRegisterInfo::isInAllocatableClass
bool isInAllocatableClass(MCRegister RegNo) const
Return true if the register is in the allocation of any register class.
Definition: TargetRegisterInfo.h:362
llvm::MachineRegisterInfo::livein_empty
bool livein_empty() const
Definition: MachineRegisterInfo.h:964
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::MachineRegisterInfo::getTargetRegisterInfo
const TargetRegisterInfo * getTargetRegisterInfo() const
Definition: MachineRegisterInfo.h:151
llvm::MachineRegisterInfo::defusechain_instr_iterator::operator*
MachineInstr & operator*() const
Definition: MachineRegisterInfo.h:1188
llvm::MachineRegisterInfo::getUniqueVRegDef
MachineInstr * getUniqueVRegDef(Register Reg) const
getUniqueVRegDef - Return the unique machine instr that defines the specified virtual register or nul...
Definition: MachineRegisterInfo.cpp:407
llvm::MachineRegisterInfo::defusechain_instr_iterator
defusechain_iterator - This class provides iterator support for machine operands in the function that...
Definition: MachineRegisterInfo.h:277
llvm::MachineRegisterInfo::canReserveReg
bool canReserveReg(MCRegister PhysReg) const
canReserveReg - Returns true if PhysReg can be used as a reserved register.
Definition: MachineRegisterInfo.h:907
llvm::MachineRegisterInfo::use_instr_nodbg_begin
use_instr_nodbg_iterator use_instr_nodbg_begin(Register RegNo) const
Definition: MachineRegisterInfo.h:543
MachineBasicBlock.h
llvm::TargetSubtargetInfo::getRegisterInfo
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
Definition: TargetSubtargetInfo.h:125
llvm::MachineRegisterInfo::use_nodbg_instructions
iterator_range< use_instr_nodbg_iterator > use_nodbg_instructions(Register Reg) const
Definition: MachineRegisterInfo.h:551
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:234
llvm::MachineRegisterInfo::defusechain_instr_iterator::operator==
bool operator==(const defusechain_instr_iterator &x) const
Definition: MachineRegisterInfo.h:1153
llvm::StringMap< NoneType, MallocAllocator >::end
iterator end()
Definition: StringMap.h:205
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::IndexedMap::clear
void clear()
Definition: IndexedMap.h:64
llvm::MachineRegisterInfo::use_instructions
iterator_range< use_instr_iterator > use_instructions(Register Reg) const
Definition: MachineRegisterInfo.h:493
llvm::MachineRegisterInfo::defusechain_instr_iterator::operator!=
bool operator!=(const defusechain_instr_iterator &x) const
Definition: MachineRegisterInfo.h:1156
llvm::MachineRegisterInfo::reg_nodbg_begin
reg_nodbg_iterator reg_nodbg_begin(Register RegNo) const
Definition: MachineRegisterInfo.h:337
llvm::MachineRegisterInfo::getLiveInVirtReg
Register getLiveInVirtReg(MCRegister PReg) const
getLiveInVirtReg - If PReg is a live-in physical register, return the corresponding live-in virtual r...
Definition: MachineRegisterInfo.cpp:450
llvm::MachineRegisterInfo::use_operands
iterator_range< use_iterator > use_operands(Register Reg) const
Definition: MachineRegisterInfo.h:477
llvm::MachineFunctionProperties::Property::IsSSA
@ IsSSA
llvm::MachineRegisterInfo::getNumVirtRegs
unsigned getNumVirtRegs() const
getNumVirtRegs - Return the number of virtual registers created.
Definition: MachineRegisterInfo.h:765
llvm::MachineRegisterInfo::reg_end
static reg_iterator reg_end()
Definition: MachineRegisterInfo.h:292
llvm::MachineRegisterInfo::reg_instr_begin
reg_instr_iterator reg_instr_begin(Register RegNo) const
Definition: MachineRegisterInfo.h:302
llvm::MachineRegisterInfo::defusechain_iterator::operator->
MachineOperand * operator->() const
Definition: MachineRegisterInfo.h:1092
llvm::StringSet::insert
std::pair< typename Base::iterator, bool > insert(StringRef key)
Definition: StringSet.h:34
llvm::MachineRegisterInfo::use_bundle_begin
use_bundle_iterator use_bundle_begin(Register RegNo) const
Definition: MachineRegisterInfo.h:501
llvm::MachineRegisterInfo::defusechain_iterator
friend class defusechain_iterator
Definition: MachineRegisterInfo.h:277
llvm::StringMap< NoneType, MallocAllocator >::find
iterator find(StringRef Key)
Definition: StringMap.h:218
tmp
alloca< 16 x float >, align 16 %tmp2=alloca< 16 x float >, align 16 store< 16 x float > %A,< 16 x float > *%tmp %s=bitcast< 16 x float > *%tmp to i8 *%s2=bitcast< 16 x float > *%tmp2 to i8 *call void @llvm.memcpy.i64(i8 *%s, i8 *%s2, i64 64, i32 16) %R=load< 16 x float > *%tmp2 ret< 16 x float > %R } declare void @llvm.memcpy.i64(i8 *nocapture, i8 *nocapture, i64, i32) nounwind which compiles to:_foo:subl $140, %esp movaps %xmm3, 112(%esp) movaps %xmm2, 96(%esp) movaps %xmm1, 80(%esp) movaps %xmm0, 64(%esp) movl 60(%esp), %eax movl %eax, 124(%esp) movl 56(%esp), %eax movl %eax, 120(%esp) movl 52(%esp), %eax< many many more 32-bit copies > movaps(%esp), %xmm0 movaps 16(%esp), %xmm1 movaps 32(%esp), %xmm2 movaps 48(%esp), %xmm3 addl $140, %esp ret On Nehalem, it may even be cheaper to just use movups when unaligned than to fall back to lower-granularity chunks. Implement processor-specific optimizations for parity with GCC on these processors. GCC does two optimizations:1. ix86_pad_returns inserts a noop before ret instructions if immediately preceded by a conditional branch or is the target of a jump. 2. ix86_avoid_jump_misspredicts inserts noops in cases where a 16-byte block of code contains more than 3 branches. The first one is done for all AMDs, Core2, and "Generic" The second one is done for:Atom, Pentium Pro, all AMDs, Pentium 4, Nocona, Core 2, and "Generic" Testcase:int x(int a) { return(a &0xf0)> >4 tmp
Definition: README.txt:1347
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1620
llvm::MachineRegisterInfo::setDelegate
void setDelegate(Delegate *delegate)
Definition: MachineRegisterInfo.h:164
llvm::MachineRegisterInfo::defusechain_iterator::getOperandNo
unsigned getOperandNo() const
getOperandNo - Return the operand # of this MachineOperand in its MachineInstr.
Definition: MachineRegisterInfo.h:1081
llvm::MachineRegisterInfo::use_nodbg_begin
use_nodbg_iterator use_nodbg_begin(Register RegNo) const
Definition: MachineRegisterInfo.h:526
llvm::MachineRegisterInfo::defusechain_instr_iterator::operator->
MachineInstr * operator->() const
Definition: MachineRegisterInfo.h:1195
Uses
SmallPtrSet< MachineInstr *, 2 > Uses
Definition: ARMLowOverheadLoops.cpp:585
llvm::MachineRegisterInfo::reg_bundle_iterator
defusechain_instr_iterator< true, true, false, false, false, true > reg_bundle_iterator
reg_bundle_iterator/reg_bundle_begin/reg_bundle_end - Walk all defs and uses of the specified registe...
Definition: MachineRegisterInfo.h:317
llvm::MachineRegisterInfo::tracksLiveness
bool tracksLiveness() const
tracksLiveness - Returns true when tracking register liveness accurately.
Definition: MachineRegisterInfo.h:195
llvm::PSetIterator
Iterate over the pressure sets affected by the given physical or virtual register.
Definition: MachineRegisterInfo.h:1202
llvm::MachineRegisterInfo::reg_nodbg_instructions
iterator_range< reg_instr_nodbg_iterator > reg_nodbg_instructions(Register Reg) const
Definition: MachineRegisterInfo.h:362
llvm::MachineRegisterInfo::defusechain_instr_iterator::atEnd
bool atEnd() const
atEnd - return true if this iterator is equal to reg_end() on the value.
Definition: MachineRegisterInfo.h:1161
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:97
llvm::MachineRegisterInfo::use_nodbg_operands
iterator_range< use_nodbg_iterator > use_nodbg_operands(Register Reg) const
Definition: MachineRegisterInfo.h:534
llvm::RegClassOrRegBank
PointerUnion< const TargetRegisterClass *, const RegisterBank * > RegClassOrRegBank
Convenient type to represent either a register class or a register bank.
Definition: MachineRegisterInfo.h:45
llvm::RegisterBank
This class implements the register bank concept.
Definition: RegisterBank.h:28
llvm::MachineRegisterInfo::setRegClassOrRegBank
void setRegClassOrRegBank(Register Reg, const RegClassOrRegBank &RCOrRB)
Definition: MachineRegisterInfo.h:686
llvm::MachineRegisterInfo::setType
void setType(Register VReg, LLT Ty)
Set the low-level type of VReg to Ty.
Definition: MachineRegisterInfo.cpp:180
llvm::MachineRegisterInfo::Delegate::MRI_NoteNewVirtualRegister
virtual void MRI_NoteNewVirtualRegister(Register Reg)=0
llvm::MachineRegisterInfo::reg_bundle_begin
reg_bundle_iterator reg_bundle_begin(Register RegNo) const
Definition: MachineRegisterInfo.h:318
llvm::IndexedMap::size
StorageT::size_type size() const
Definition: IndexedMap.h:78
llvm::MachineRegisterInfo::reg_nodbg_iterator
defusechain_iterator< true, true, true, true, false, false > reg_nodbg_iterator
reg_nodbg_iterator/reg_nodbg_begin/reg_nodbg_end - Walk all defs and uses of the specified register,...
Definition: MachineRegisterInfo.h:336
llvm::MachineRegisterInfo::isUpdatedCSRsInitialized
bool isUpdatedCSRsInitialized() const
Returns true if the updated CSR list was initialized and false otherwise.
Definition: MachineRegisterInfo.h:228
llvm::MachineRegisterInfo::isReserved
bool isReserved(MCRegister PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.
Definition: MachineRegisterInfo.h:925
llvm::IndexedMap
Definition: IndexedMap.h:30
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:45
llvm::MachineFunction::getProperties
const MachineFunctionProperties & getProperties() const
Get the function properties.
Definition: MachineFunction.h:731
llvm::MachineRegisterInfo::reg_nodbg_operands
iterator_range< reg_nodbg_iterator > reg_nodbg_operands(Register Reg) const
Definition: MachineRegisterInfo.h:345
llvm::MachineRegisterInfo::defusechain_iterator::difference_type
std::ptrdiff_t difference_type
Definition: MachineRegisterInfo.h:1004
llvm::MachineRegisterInfo::insertVRegByName
void insertVRegByName(StringRef Name, Register Reg)
Definition: MachineRegisterInfo.h:440
llvm::MachineRegisterInfo::reg_instr_nodbg_end
static reg_instr_nodbg_iterator reg_instr_nodbg_end()
Definition: MachineRegisterInfo.h:357
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:127
llvm::MachineRegisterInfo::reg_iterator
defusechain_iterator< true, true, false, true, false, false > reg_iterator
reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specified register.
Definition: MachineRegisterInfo.h:288
llvm::MachineRegisterInfo::defusechain_iterator::atEnd
bool atEnd() const
atEnd - return true if this iterator is equal to reg_end() on the value.
Definition: MachineRegisterInfo.h:1053
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48
llvm::MachineRegisterInfo::reg_instructions
iterator_range< reg_instr_iterator > reg_instructions(Register Reg) const
Definition: MachineRegisterInfo.h:310
llvm::MachineRegisterInfo::setCalleeSavedRegs
void setCalleeSavedRegs(ArrayRef< MCPhysReg > CSRs)
Sets the updated Callee Saved Registers list.
Definition: MachineRegisterInfo.cpp:624
llvm::PSetIterator::getWeight
unsigned getWeight() const
Definition: MachineRegisterInfo.h:1225
MachineInstrBundle.h
llvm::MachineRegisterInfo::use_iterator
defusechain_iterator< true, false, false, true, false, false > use_iterator
use_iterator/use_begin/use_end - Walk all uses of the specified register.
Definition: MachineRegisterInfo.h:471
llvm::MachineRegisterInfo::defusechain_iterator::operator*
MachineOperand & operator*() const
Definition: MachineRegisterInfo.h:1087
llvm::MachineRegisterInfo::def_iterator
defusechain_iterator< false, true, false, true, false, false > def_iterator
def_iterator/def_begin/def_end - Walk all defs of the specified register.
Definition: MachineRegisterInfo.h:391
BitVector.h
llvm::MachineRegisterInfo::use_nodbg_end
static use_nodbg_iterator use_nodbg_end()
Definition: MachineRegisterInfo.h:529
llvm::MachineRegisterInfo::freezeReservedRegs
void freezeReservedRegs(const MachineFunction &)
freezeReservedRegs - Called by the register allocator to freeze the set of reserved registers before ...
Definition: MachineRegisterInfo.cpp:503
llvm::MachineRegisterInfo::operator=
MachineRegisterInfo & operator=(const MachineRegisterInfo &)=delete
llvm::BitVector
Definition: BitVector.h:75
llvm::MachineRegisterInfo::livein_begin
livein_iterator livein_begin() const
Definition: MachineRegisterInfo.h:962
llvm::MachineRegisterInfo::clearVirtRegTypes
void clearVirtRegTypes()
Remove all types associated to virtual registers (after instruction selection and constraining of all...
Definition: MachineRegisterInfo.cpp:197
Register
Promote Memory to Register
Definition: Mem2Reg.cpp:110
llvm::MachineRegisterInfo::reservedRegsFrozen
bool reservedRegsFrozen() const
reservedRegsFrozen - Returns true after freezeReservedRegs() was called to ensure the set of reserved...
Definition: MachineRegisterInfo.h:900
llvm::MachineRegisterInfo::getVRegDef
MachineInstr * getVRegDef(Register Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
Definition: MachineRegisterInfo.cpp:396
llvm::MachineRegisterInfo::use_bundles
iterator_range< use_bundle_iterator > use_bundles(Register Reg) const
Definition: MachineRegisterInfo.h:508
llvm::MachineRegisterInfo::use_empty
bool use_empty(Register RegNo) const
use_empty - Return true if there are no instructions using the specified register.
Definition: MachineRegisterInfo.h:514
llvm::MachineRegisterInfo::reg_instr_end
static reg_instr_iterator reg_instr_end()
Definition: MachineRegisterInfo.h:305
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::MachineRegisterInfo::reg_nodbg_end
static reg_nodbg_iterator reg_nodbg_end()
Definition: MachineRegisterInfo.h:340
llvm::MachineRegisterInfo::defusechain_instr_iterator::defusechain_instr_iterator
defusechain_instr_iterator()=default
llvm::MachineRegisterInfo::def_empty
bool def_empty(Register RegNo) const
def_empty - Return true if there are no instructions defining the specified register (it may be live-...
Definition: MachineRegisterInfo.h:434
llvm::MachineRegisterInfo::reg_instr_iterator
defusechain_instr_iterator< true, true, false, false, true, false > reg_instr_iterator
reg_instr_iterator/reg_instr_begin/reg_instr_end - Walk all defs and uses of the specified register,...
Definition: MachineRegisterInfo.h:301
llvm::MachineRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
Definition: MachineRegisterInfo.h:642
llvm::MachineRegisterInfo::isSSA
bool isSSA() const
Definition: MachineRegisterInfo.h:183
llvm::MachineRegisterInfo::defusechain_instr_iterator
friend class defusechain_instr_iterator
Definition: MachineRegisterInfo.h:283
llvm::Register::isVirtual
bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:91
llvm::MachineRegisterInfo::clearKillFlags
void clearKillFlags(Register Reg) const
clearKillFlags - Iterate over all the uses of the given register and clear the kill flag from the Mac...
Definition: MachineRegisterInfo.cpp:427
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:640
llvm::MachineRegisterInfo::defusechain_instr_iterator::operator++
defusechain_instr_iterator & operator++()
Definition: MachineRegisterInfo.h:1164
llvm::MachineRegisterInfo::verifyUseList
void verifyUseList(Register Reg) const
Verify the sanity of the use list for Reg.
Definition: MachineRegisterInfo.cpp:215
llvm::MachineRegisterInfo::reg_bundles
iterator_range< reg_bundle_iterator > reg_bundles(Register Reg) const
Definition: MachineRegisterInfo.h:325
llvm::TargetRegisterInfo::regsOverlap
bool regsOverlap(Register RegA, Register RegB) const
Returns true if the two registers are equal or alias each other.
Definition: TargetRegisterInfo.h:419
llvm::PSetIterator::operator++
void operator++()
Definition: MachineRegisterInfo.h:1229
llvm::MachineRegisterInfo::reg_bundle_end
static reg_bundle_iterator reg_bundle_end()
Definition: MachineRegisterInfo.h:321
llvm::MachineFunctionProperties::Property::TracksLiveness
@ TracksLiveness
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::MachineRegisterInfo::setRegBank
void setRegBank(Register Reg, const RegisterBank &RegBank)
Set the register bank to RegBank for Reg.
Definition: MachineRegisterInfo.cpp:61
llvm::MachineRegisterInfo::use_nodbg_iterator
defusechain_iterator< true, false, true, true, false, false > use_nodbg_iterator
use_nodbg_iterator/use_nodbg_begin/use_nodbg_end - Walk all uses of the specified register,...
Definition: MachineRegisterInfo.h:525
llvm::MachineRegisterInfo::use_instr_begin
use_instr_iterator use_instr_begin(Register RegNo) const
Definition: MachineRegisterInfo.h:485
llvm::MachineRegisterInfo::def_bundle_end
static def_bundle_iterator def_bundle_end()
Definition: MachineRegisterInfo.h:424
llvm::PointerUnion::dyn_cast
T dyn_cast() const
Returns the current pointer if it is of the specified pointer type, otherwise returns null.
Definition: PointerUnion.h:162
llvm::MachineRegisterInfo::def_instr_iterator
defusechain_instr_iterator< false, true, false, false, true, false > def_instr_iterator
def_instr_iterator/def_instr_begin/def_instr_end - Walk all defs of the specified register,...
Definition: MachineRegisterInfo.h:404
llvm::MachineRegisterInfo::def_bundles
iterator_range< def_bundle_iterator > def_bundles(Register Reg) const
Definition: MachineRegisterInfo.h:428
llvm::MachineRegisterInfo::getCalleeSavedRegs
const MCPhysReg * getCalleeSavedRegs() const
Returns list of callee saved registers.
Definition: MachineRegisterInfo.cpp:617
llvm::MachineRegisterInfo::def_instructions
iterator_range< def_instr_iterator > def_instructions(Register Reg) const
Definition: MachineRegisterInfo.h:413
llvm::MachineRegisterInfo::reg_instr_nodbg_begin
reg_instr_nodbg_iterator reg_instr_nodbg_begin(Register RegNo) const
Definition: MachineRegisterInfo.h:354
llvm::TargetRegisterClass::HasDisjunctSubRegs
const bool HasDisjunctSubRegs
Whether the class supports two (or more) disjunct subregister indices.
Definition: TargetRegisterInfo.h:64
llvm::MachineRegisterInfo::getLiveInPhysReg
MCRegister getLiveInPhysReg(Register VReg) const
getLiveInPhysReg - If VReg is a live-in virtual register, return the corresponding live-in physical r...
Definition: MachineRegisterInfo.cpp:441
llvm::MachineRegisterInfo::liveins
ArrayRef< std::pair< MCRegister, Register > > liveins() const
Definition: MachineRegisterInfo.h:966
ArrayRef.h
TemplateParamKind::Type
@ Type
llvm::Register::isVirtualRegister
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:71
llvm::MachineRegisterInfo::getRegClassOrNull
const TargetRegisterClass * getRegClassOrNull(Register Reg) const
Return the register class of Reg, or null if Reg has not been assigned a register class yet.
Definition: MachineRegisterInfo.h:659
llvm::MachineRegisterInfo::reg_operands
iterator_range< reg_iterator > reg_operands(Register Reg) const
Definition: MachineRegisterInfo.h:294
llvm::MachineRegisterInfo::isAllocatable
bool isAllocatable(MCRegister PhysReg) const
isAllocatable - Returns true when PhysReg belongs to an allocatable register class and it hasn't been...
Definition: MachineRegisterInfo.h:943
llvm::MachineRegisterInfo::setSimpleHint
void setSimpleHint(Register VReg, Register PrefReg)
Specify the preferred (target independent) register allocation hint for the specified virtual registe...
Definition: MachineRegisterInfo.h:789
llvm::MachineRegisterInfo::getOneDef
MachineOperand * getOneDef(Register Reg) const
Returns the defining operand if there is exactly one operand defining the specified register,...
Definition: MachineRegisterInfo.h:458
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
PointerUnion.h
iterator_range.h
llvm::MachineRegisterInfo::isArgumentRegister
bool isArgumentRegister(const MachineFunction &MF, MCRegister Reg) const
Returns true if a register can be used as an argument to a function.
Definition: MachineRegisterInfo.cpp:654
llvm::MachineRegisterInfo::createGenericVirtualRegister
Register createGenericVirtualRegister(LLT Ty, StringRef Name="")
Create and return a new generic virtual register with low-level type Ty.
Definition: MachineRegisterInfo.cpp:186
llvm::MachineRegisterInfo::hasOneDef
bool hasOneDef(Register RegNo) const
Return true if there is exactly one operand defining the specified register.
Definition: MachineRegisterInfo.h:452
llvm::MachineRegisterInfo::def_end
static def_iterator def_end()
Definition: MachineRegisterInfo.h:395
llvm::MachineRegisterInfo::updateDbgUsersToReg
void updateDbgUsersToReg(MCRegister OldReg, MCRegister NewReg, ArrayRef< MachineInstr * > Users) const
updateDbgUsersToReg - Update a collection of debug instructions to refer to the designated register.
Definition: MachineRegisterInfo.h:834
llvm::MachineRegisterInfo::getRegClassOrRegBank
const RegClassOrRegBank & getRegClassOrRegBank(Register Reg) const
Return the register bank or register class of Reg.
Definition: MachineRegisterInfo.h:676
llvm::MachineFunction
Definition: MachineFunction.h:241
llvm::MachineRegisterInfo::resetDelegate
void resetDelegate(Delegate *delegate)
Definition: MachineRegisterInfo.h:155
llvm::MachineRegisterInfo::use_nodbg_empty
bool use_nodbg_empty(Register RegNo) const
use_nodbg_empty - Return true if there are no non-Debug instructions using the specified register.
Definition: MachineRegisterInfo.h:574
llvm::MCRegister::id
unsigned id() const
Definition: MCRegister.h:72
llvm::hasSingleElement
bool hasSingleElement(ContainerTy &&C)
Returns true if the given container only contains a single element.
Definition: STLExtras.h:273
llvm::StringSet
StringSet - A wrapper for StringMap that provides set-like functionality.
Definition: StringSet.h:23
llvm::MachineRegisterInfo::use_instr_iterator
defusechain_instr_iterator< true, false, false, false, true, false > use_instr_iterator
use_instr_iterator/use_instr_begin/use_instr_end - Walk all uses of the specified register,...
Definition: MachineRegisterInfo.h:484
llvm::IndexedMap::grow
void grow(IndexT n)
Definition: IndexedMap.h:68
llvm::MachineRegisterInfo::Delegate
Definition: MachineRegisterInfo.h:52
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::MachineRegisterInfo::hasOneNonDBGUse
bool hasOneNonDBGUse(Register RegNo) const
hasOneNonDBGUse - Return true if there is exactly one non-Debug use of the specified register.
Definition: MachineRegisterInfo.cpp:415
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::MachineRegisterInfo::isFixedRegister
bool isFixedRegister(const MachineFunction &MF, MCRegister Reg) const
Returns true if a register is a fixed register.
Definition: MachineRegisterInfo.cpp:659
llvm::MachineRegisterInfo::use_begin
use_iterator use_begin(Register RegNo) const
Definition: MachineRegisterInfo.h:472
llvm::MachineRegisterInfo::setRegAllocationHint
void setRegAllocationHint(Register VReg, unsigned Type, Register PrefReg)
setRegAllocationHint - Specify a register allocation hint for the specified virtual register.
Definition: MachineRegisterInfo.h:773
uint32_t
llvm::getBundleStart
MachineBasicBlock::instr_iterator getBundleStart(MachineBasicBlock::instr_iterator I)
Returns an iterator to the first instruction in the bundle containing I.
Definition: MachineInstrBundle.h:44
llvm::MachineRegisterInfo::invalidateLiveness
void invalidateLiveness()
invalidateLiveness - Indicates that register liveness is no longer being tracked accurately.
Definition: MachineRegisterInfo.h:205
llvm::MachineRegisterInfo::reg_instr_nodbg_iterator
defusechain_instr_iterator< true, true, true, false, true, false > reg_instr_nodbg_iterator
reg_instr_nodbg_iterator/reg_instr_nodbg_begin/reg_instr_nodbg_end - Walk all defs and uses of the sp...
Definition: MachineRegisterInfo.h:353
TargetSubtargetInfo.h
llvm::MachineRegisterInfo::removeRegOperandFromUseList
void removeRegOperandFromUseList(MachineOperand *MO)
Remove MO from its use-def list.
Definition: MachineRegisterInfo.cpp:302
llvm::MachineRegisterInfo::defusechain_iterator::operator!=
bool operator!=(const defusechain_iterator &x) const
Definition: MachineRegisterInfo.h:1048
llvm::MachineFunctionProperties::reset
MachineFunctionProperties & reset(Property P)
Definition: MachineFunction.h:185
llvm::MachineRegisterInfo::getRegAllocationHints
const std::pair< Register, SmallVector< Register, 4 > > & getRegAllocationHints(Register VReg) const
getRegAllocationHints - Return a reference to the vector of all register allocation hints for VReg.
Definition: MachineRegisterInfo.h:822
llvm::MachineRegisterInfo::getReservedRegs
const BitVector & getReservedRegs() const
getReservedRegs - Returns a reference to the frozen set of reserved registers.
Definition: MachineRegisterInfo.h:914
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::PointerUnion
A discriminated union of two or more pointer types, with the discriminator in the low bit of the poin...
Definition: PointerUnion.h:112
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::PSetIterator::PSetIterator
PSetIterator(Register RegUnit, const MachineRegisterInfo *MRI)
Definition: MachineRegisterInfo.h:1209
llvm::MachineRegisterInfo::getUsedPhysRegsMask
const BitVector & getUsedPhysRegsMask() const
Definition: MachineRegisterInfo.h:880
llvm::MachineRegisterInfo::isConstantPhysReg
bool isConstantPhysReg(MCRegister PhysReg) const
Returns true if PhysReg is unallocatable and constant throughout the function.
Definition: MachineRegisterInfo.cpp:509
llvm::MachineRegisterInfo::replaceRegWith
void replaceRegWith(Register FromReg, Register ToReg)
replaceRegWith - Replace all instances of FromReg with ToReg in the machine function.
Definition: MachineRegisterInfo.cpp:378
StringSet.h
llvm::MachineRegisterInfo::def_operands
iterator_range< def_iterator > def_operands(Register Reg) const
Definition: MachineRegisterInfo.h:397
llvm::MachineRegisterInfo::reg_begin
reg_iterator reg_begin(Register RegNo) const
Definition: MachineRegisterInfo.h:289
llvm::BitVector::test
bool test(unsigned Idx) const
Definition: BitVector.h:454
llvm::MachineRegisterInfo::addRegOperandToUseList
void addRegOperandToUseList(MachineOperand *MO)
Add MO to the linked list of operands for its register.
Definition: MachineRegisterInfo.cpp:263
llvm::MachineRegisterInfo::getSimpleHint
Register getSimpleHint(Register VReg) const
getSimpleHint - same as getRegAllocationHint except it will only return a target independent hint.
Definition: MachineRegisterInfo.h:813
llvm::MachineRegisterInfo::isLiveIn
bool isLiveIn(Register Reg) const
Definition: MachineRegisterInfo.cpp:432
llvm::MachineRegisterInfo::getMaxLaneMaskForVReg
LaneBitmask getMaxLaneMaskForVReg(Register Reg) const
Returns a mask covering all bits that can appear in lane masks of subregisters of the virtual registe...
Definition: MachineRegisterInfo.cpp:489
llvm::GraphProgram::Name
Name
Definition: GraphWriter.h:50
uint16_t
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:344
llvm::MachineRegisterInfo::def_bundle_iterator
defusechain_instr_iterator< false, true, false, false, false, true > def_bundle_iterator
def_bundle_iterator/def_bundle_begin/def_bundle_end - Walk all defs of the specified register,...
Definition: MachineRegisterInfo.h:420
llvm::MachineBasicBlock::instr_iterator
Instructions::iterator instr_iterator
Definition: MachineBasicBlock.h:237
llvm::MachineRegisterInfo::livein_iterator
std::vector< std::pair< MCRegister, Register > >::const_iterator livein_iterator
Definition: MachineRegisterInfo.h:961
llvm::MachineRegisterInfo::reg_empty
bool reg_empty(Register RegNo) const
reg_empty - Return true if there are no instructions using or defining the specified register (it may...
Definition: MachineRegisterInfo.h:331
llvm::MachineRegisterInfo::getRegBankOrNull
const RegisterBank * getRegBankOrNull(Register Reg) const
Return the register bank of Reg, or null if Reg has not been assigned a register bank or has been ass...
Definition: MachineRegisterInfo.h:668
x
TODO unsigned x
Definition: README.txt:10
llvm::MachineRegisterInfo::addPhysRegsUsedFromRegMask
void addPhysRegsUsedFromRegMask(const uint32_t *RegMask)
addPhysRegsUsedFromRegMask - Mark any registers not in RegMask as used.
Definition: MachineRegisterInfo.h:876
llvm::MachineRegisterInfo::clearVirtRegs
void clearVirtRegs()
clearVirtRegs - Remove all virtual registers (after physreg assignment).
Definition: MachineRegisterInfo.cpp:200
llvm::MachineRegisterInfo::isPhysRegModified
bool isPhysRegModified(MCRegister PhysReg, bool SkipNoReturnDef=false) const
Return true if the specified register is modified in this function.
Definition: MachineRegisterInfo.cpp:566
llvm::MachineRegisterInfo::hasOneNonDBGUser
bool hasOneNonDBGUser(Register RegNo) const
hasOneNonDBGUse - Return true if there is exactly one non-Debug instruction using the specified regis...
Definition: MachineRegisterInfo.cpp:419
llvm::MachineRegisterInfo::use_nodbg_bundles
iterator_range< use_bundle_nodbg_iterator > use_nodbg_bundles(Register Reg) const
Definition: MachineRegisterInfo.h:568
llvm::MachineRegisterInfo::defusechain_iterator::operator++
defusechain_iterator operator++(int)
Definition: MachineRegisterInfo.h:1075
llvm::VRegInfo
Definition: MIParser.h:37
llvm::MachineRegisterInfo::use_bundle_nodbg_end
static use_bundle_nodbg_iterator use_bundle_nodbg_end()
Definition: MachineRegisterInfo.h:563
llvm::MachineRegisterInfo::addRegAllocationHint
void addRegAllocationHint(Register VReg, Register PrefReg)
addRegAllocationHint - Add a register allocation hint to the hints vector for VReg.
Definition: MachineRegisterInfo.h:782
llvm::MachineRegisterInfo::use_bundle_nodbg_iterator
defusechain_instr_iterator< true, false, true, false, false, true > use_bundle_nodbg_iterator
use_bundle_nodbg_iterator/use_bundle_nodbg_begin/use_bundle_nodbg_end - Walk all uses of the specifie...
Definition: MachineRegisterInfo.h:559
llvm::MachineRegisterInfo::defusechain_instr_iterator::difference_type
std::ptrdiff_t difference_type
Definition: MachineRegisterInfo.h:1112
llvm::MachineRegisterInfo::use_end
static use_iterator use_end()
Definition: MachineRegisterInfo.h:475
llvm::MachineRegisterInfo::use_bundle_end
static use_bundle_iterator use_bundle_end()
Definition: MachineRegisterInfo.h:504
llvm::MachineRegisterInfo::reg_bundle_nodbg_begin
reg_bundle_nodbg_iterator reg_bundle_nodbg_begin(Register RegNo) const
Definition: MachineRegisterInfo.h:371
llvm::MachineRegisterInfo::hasOneUse
bool hasOneUse(Register RegNo) const
hasOneUse - Return true if there is exactly one instruction using the specified register.
Definition: MachineRegisterInfo.h:518
SmallVector.h
llvm::PSetIterator::operator*
unsigned operator*() const
Definition: MachineRegisterInfo.h:1227
llvm::MachineRegisterInfo::getType
LLT getType(Register Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register.
Definition: MachineRegisterInfo.h:740
llvm::MachineRegisterInfo::cloneVirtualRegister
Register cloneVirtualRegister(Register VReg, StringRef Name="")
Create and return a new virtual register in the function with the same attributes as the given regist...
Definition: MachineRegisterInfo.cpp:170
RegisterBank.h
llvm::IndexedMap::inBounds
bool inBounds(IndexT n) const
Definition: IndexedMap.h:74
llvm::MachineRegisterInfo::leaveSSA
void leaveSSA()
Definition: MachineRegisterInfo.h:189
llvm::MachineRegisterInfo::use_bundle_iterator
defusechain_instr_iterator< true, false, false, false, false, true > use_bundle_iterator
use_bundle_iterator/use_bundle_begin/use_bundle_end - Walk all uses of the specified register,...
Definition: MachineRegisterInfo.h:500
llvm::MachineRegisterInfo::isGeneralPurposeRegister
bool isGeneralPurposeRegister(const MachineFunction &MF, MCRegister Reg) const
Returns true if a register is a general purpose register.
Definition: MachineRegisterInfo.cpp:664
LaneBitmask.h
Users
iv Induction Variable Users
Definition: IVUsers.cpp:48
llvm::iterator_range
A range adaptor for a pair of iterators.
Definition: iterator_range.h:30
llvm::MachineRegisterInfo::constrainRegClass
const TargetRegisterClass * constrainRegClass(Register Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
Definition: MachineRegisterInfo.cpp:83
llvm::MachineRegisterInfo::defusechain_iterator
reg_begin/reg_end - Provide iteration support to walk over all definitions and uses of a register wit...
Definition: MachineRegisterInfo.h:274
MachineOperand.h
llvm::MachineRegisterInfo::use_bundle_nodbg_begin
use_bundle_nodbg_iterator use_bundle_nodbg_begin(Register RegNo) const
Definition: MachineRegisterInfo.h:560
llvm::MachineRegisterInfo::MachineRegisterInfo
MachineRegisterInfo(MachineFunction *MF)
Definition: MachineRegisterInfo.cpp:43
llvm::MachineRegisterInfo::reg_bundle_nodbg_iterator
defusechain_instr_iterator< true, true, true, false, false, true > reg_bundle_nodbg_iterator
reg_bundle_nodbg_iterator/reg_bundle_nodbg_begin/reg_bundle_nodbg_end - Walk all defs and uses of the...
Definition: MachineRegisterInfo.h:370
llvm::MachineRegisterInfo::shouldTrackSubRegLiveness
bool shouldTrackSubRegLiveness(Register VReg) const
Definition: MachineRegisterInfo.h:215
llvm::MachineRegisterInfo::isReservedRegUnit
bool isReservedRegUnit(unsigned Unit) const
Returns true when the given register unit is considered reserved.
Definition: MachineRegisterInfo.cpp:636
llvm::MachineRegisterInfo::clearSimpleHint
void clearSimpleHint(Register VReg)
Definition: MachineRegisterInfo.h:793
llvm::MachineRegisterInfo::reg_nodbg_empty
bool reg_nodbg_empty(Register RegNo) const
reg_nodbg_empty - Return true if the only instructions using or defining Reg are Debug instructions.
Definition: MachineRegisterInfo.h:385
MachineFunction.h
llvm::MachineRegisterInfo::defusechain_iterator::defusechain_iterator
defusechain_iterator()=default
llvm::MachineRegisterInfo::getPressureSets
PSetIterator getPressureSets(Register RegUnit) const
Get an iterator over the pressure sets affected by the given physical or virtual register.
Definition: MachineRegisterInfo.h:1238
llvm::MachineRegisterInfo::defusechain_instr_iterator::iterator_category
std::forward_iterator_tag iterator_category
Definition: MachineRegisterInfo.h:1110
llvm::MachineRegisterInfo::dumpUses
void dumpUses(Register RegNo) const
Definition: MachineRegisterInfo.cpp:497
llvm::MachineRegisterInfo::livein_end
livein_iterator livein_end() const
Definition: MachineRegisterInfo.h:963
llvm::MachineRegisterInfo::moveOperands
void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps)
Move NumOps operands from Src to Dst, updating use-def lists as needed.
Definition: MachineRegisterInfo.cpp:331
llvm::MachineRegisterInfo::reg_bundle_nodbg_end
static reg_bundle_nodbg_iterator reg_bundle_nodbg_end()
Definition: MachineRegisterInfo.h:374
llvm::MachineRegisterInfo::use_instr_end
static use_instr_iterator use_instr_end()
Definition: MachineRegisterInfo.h:488
TargetRegisterInfo.h
llvm::MachineRegisterInfo::EmitLiveInCopies
void EmitLiveInCopies(MachineBasicBlock *EntryMBB, const TargetRegisterInfo &TRI, const TargetInstrInfo &TII)
EmitLiveInCopies - Emit copies to initialize livein virtual registers into the given entry block.
Definition: MachineRegisterInfo.cpp:460
llvm::MachineRegisterInfo::setRegClass
void setRegClass(Register Reg, const TargetRegisterClass *RC)
setRegClass - Set the register class of the specified virtual register.
Definition: MachineRegisterInfo.cpp:56
llvm::MachineRegisterInfo::getRegAllocationHint
std::pair< Register, Register > getRegAllocationHint(Register VReg) const
getRegAllocationHint - Return the register allocation hint for the specified virtual register.
Definition: MachineRegisterInfo.h:803
llvm::MachineRegisterInfo::verifyUseLists
void verifyUseLists() const
Verify the use list of all registers.
Definition: MachineRegisterInfo.cpp:253
llvm::MachineRegisterInfo::use_instr_nodbg_iterator
defusechain_instr_iterator< true, false, true, false, true, false > use_instr_nodbg_iterator
use_instr_nodbg_iterator/use_instr_nodbg_begin/use_instr_nodbg_end - Walk all uses of the specified r...
Definition: MachineRegisterInfo.h:542
llvm::MachineRegisterInfo::Delegate::~Delegate
virtual ~Delegate()=default
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24
llvm::MachineRegisterInfo::defusechain_iterator::operator++
defusechain_iterator & operator++()
Definition: MachineRegisterInfo.h:1056
llvm::LLT
Definition: LowLevelTypeImpl.h:39