LLVM  13.0.0git
Utils.h
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1 //==-- llvm/CodeGen/GlobalISel/Utils.h ---------------------------*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file This file declares the API of helper functions used throughout the
10 /// GlobalISel pipeline.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_CODEGEN_GLOBALISEL_UTILS_H
15 #define LLVM_CODEGEN_GLOBALISEL_UTILS_H
16 
17 #include "llvm/ADT/StringRef.h"
19 #include "llvm/CodeGen/Register.h"
20 #include "llvm/Support/Alignment.h"
22 #include <cstdint>
23 
24 namespace llvm {
25 
26 class AnalysisUsage;
27 class BlockFrequencyInfo;
28 class GISelKnownBits;
29 class MachineFunction;
30 class MachineInstr;
31 class MachineOperand;
32 class MachineOptimizationRemarkEmitter;
33 class MachineOptimizationRemarkMissed;
34 struct MachinePointerInfo;
35 class MachineRegisterInfo;
36 class MCInstrDesc;
37 class ProfileSummaryInfo;
38 class RegisterBankInfo;
39 class TargetInstrInfo;
40 class TargetLowering;
41 class TargetPassConfig;
42 class TargetRegisterInfo;
43 class TargetRegisterClass;
44 class ConstantFP;
45 class APFloat;
46 
47 // Convenience macros for dealing with vector reduction opcodes.
48 #define GISEL_VECREDUCE_CASES_ALL \
49  case TargetOpcode::G_VECREDUCE_SEQ_FADD: \
50  case TargetOpcode::G_VECREDUCE_SEQ_FMUL: \
51  case TargetOpcode::G_VECREDUCE_FADD: \
52  case TargetOpcode::G_VECREDUCE_FMUL: \
53  case TargetOpcode::G_VECREDUCE_FMAX: \
54  case TargetOpcode::G_VECREDUCE_FMIN: \
55  case TargetOpcode::G_VECREDUCE_ADD: \
56  case TargetOpcode::G_VECREDUCE_MUL: \
57  case TargetOpcode::G_VECREDUCE_AND: \
58  case TargetOpcode::G_VECREDUCE_OR: \
59  case TargetOpcode::G_VECREDUCE_XOR: \
60  case TargetOpcode::G_VECREDUCE_SMAX: \
61  case TargetOpcode::G_VECREDUCE_SMIN: \
62  case TargetOpcode::G_VECREDUCE_UMAX: \
63  case TargetOpcode::G_VECREDUCE_UMIN:
64 
65 #define GISEL_VECREDUCE_CASES_NONSEQ \
66  case TargetOpcode::G_VECREDUCE_FADD: \
67  case TargetOpcode::G_VECREDUCE_FMUL: \
68  case TargetOpcode::G_VECREDUCE_FMAX: \
69  case TargetOpcode::G_VECREDUCE_FMIN: \
70  case TargetOpcode::G_VECREDUCE_ADD: \
71  case TargetOpcode::G_VECREDUCE_MUL: \
72  case TargetOpcode::G_VECREDUCE_AND: \
73  case TargetOpcode::G_VECREDUCE_OR: \
74  case TargetOpcode::G_VECREDUCE_XOR: \
75  case TargetOpcode::G_VECREDUCE_SMAX: \
76  case TargetOpcode::G_VECREDUCE_SMIN: \
77  case TargetOpcode::G_VECREDUCE_UMAX: \
78  case TargetOpcode::G_VECREDUCE_UMIN:
79 
80 /// Try to constrain Reg to the specified register class. If this fails,
81 /// create a new virtual register in the correct class.
82 ///
83 /// \return The virtual register constrained to the right register class.
84 Register constrainRegToClass(MachineRegisterInfo &MRI,
85  const TargetInstrInfo &TII,
86  const RegisterBankInfo &RBI, Register Reg,
87  const TargetRegisterClass &RegClass);
88 
89 /// Constrain the Register operand OpIdx, so that it is now constrained to the
90 /// TargetRegisterClass passed as an argument (RegClass).
91 /// If this fails, create a new virtual register in the correct class and insert
92 /// a COPY before \p InsertPt if it is a use or after if it is a definition.
93 /// In both cases, the function also updates the register of RegMo. The debug
94 /// location of \p InsertPt is used for the new copy.
95 ///
96 /// \return The virtual register constrained to the right register class.
97 Register constrainOperandRegClass(const MachineFunction &MF,
98  const TargetRegisterInfo &TRI,
99  MachineRegisterInfo &MRI,
100  const TargetInstrInfo &TII,
101  const RegisterBankInfo &RBI,
102  MachineInstr &InsertPt,
103  const TargetRegisterClass &RegClass,
104  MachineOperand &RegMO);
105 
106 /// Try to constrain Reg so that it is usable by argument OpIdx of the provided
107 /// MCInstrDesc \p II. If this fails, create a new virtual register in the
108 /// correct class and insert a COPY before \p InsertPt if it is a use or after
109 /// if it is a definition. In both cases, the function also updates the register
110 /// of RegMo.
111 /// This is equivalent to constrainOperandRegClass(..., RegClass, ...)
112 /// with RegClass obtained from the MCInstrDesc. The debug location of \p
113 /// InsertPt is used for the new copy.
114 ///
115 /// \return The virtual register constrained to the right register class.
116 Register constrainOperandRegClass(const MachineFunction &MF,
117  const TargetRegisterInfo &TRI,
118  MachineRegisterInfo &MRI,
119  const TargetInstrInfo &TII,
120  const RegisterBankInfo &RBI,
121  MachineInstr &InsertPt, const MCInstrDesc &II,
122  MachineOperand &RegMO, unsigned OpIdx);
123 
124 /// Mutate the newly-selected instruction \p I to constrain its (possibly
125 /// generic) virtual register operands to the instruction's register class.
126 /// This could involve inserting COPYs before (for uses) or after (for defs).
127 /// This requires the number of operands to match the instruction description.
128 /// \returns whether operand regclass constraining succeeded.
129 ///
130 // FIXME: Not all instructions have the same number of operands. We should
131 // probably expose a constrain helper per operand and let the target selector
132 // constrain individual registers, like fast-isel.
133 bool constrainSelectedInstRegOperands(MachineInstr &I,
134  const TargetInstrInfo &TII,
135  const TargetRegisterInfo &TRI,
136  const RegisterBankInfo &RBI);
137 
138 /// Check if DstReg can be replaced with SrcReg depending on the register
139 /// constraints.
140 bool canReplaceReg(Register DstReg, Register SrcReg, MachineRegisterInfo &MRI);
141 
142 /// Check whether an instruction \p MI is dead: it only defines dead virtual
143 /// registers, and doesn't have other side effects.
144 bool isTriviallyDead(const MachineInstr &MI, const MachineRegisterInfo &MRI);
145 
146 /// Report an ISel error as a missed optimization remark to the LLVMContext's
147 /// diagnostic stream. Set the FailedISel MachineFunction property.
148 void reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC,
149  MachineOptimizationRemarkEmitter &MORE,
150  MachineOptimizationRemarkMissed &R);
151 
152 void reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC,
153  MachineOptimizationRemarkEmitter &MORE,
154  const char *PassName, StringRef Msg,
155  const MachineInstr &MI);
156 
157 /// Report an ISel warning as a missed optimization remark to the LLVMContext's
158 /// diagnostic stream.
159 void reportGISelWarning(MachineFunction &MF, const TargetPassConfig &TPC,
160  MachineOptimizationRemarkEmitter &MORE,
161  MachineOptimizationRemarkMissed &R);
162 
163 /// If \p VReg is defined by a G_CONSTANT, return the corresponding value.
164 Optional<APInt> getConstantVRegVal(Register VReg,
165  const MachineRegisterInfo &MRI);
166 
167 /// If \p VReg is defined by a G_CONSTANT fits in int64_t
168 /// returns it.
169 Optional<int64_t> getConstantVRegSExtVal(Register VReg,
170  const MachineRegisterInfo &MRI);
171 
172 /// Simple struct used to hold a constant integer value and a virtual
173 /// register.
174 struct ValueAndVReg {
177 };
178 /// If \p VReg is defined by a statically evaluable chain of
179 /// instructions rooted on a G_F/CONSTANT (\p LookThroughInstrs == true)
180 /// and that constant fits in int64_t, returns its value as well as the
181 /// virtual register defined by this G_F/CONSTANT.
182 /// When \p LookThroughInstrs == false this function behaves like
183 /// getConstantVRegVal.
184 /// When \p HandleFConstants == false the function bails on G_FCONSTANTs.
185 /// When \p LookThroughAnyExt == true the function treats G_ANYEXT same as
186 /// G_SEXT.
189  bool LookThroughInstrs = true,
190  bool HandleFConstants = true,
191  bool LookThroughAnyExt = false);
193  const MachineRegisterInfo &MRI);
194 
195 /// See if Reg is defined by an single def instruction that is
196 /// Opcode. Also try to do trivial folding if it's a COPY with
197 /// same types. Returns null otherwise.
198 MachineInstr *getOpcodeDef(unsigned Opcode, Register Reg,
199  const MachineRegisterInfo &MRI);
200 
201 /// Simple struct used to hold a Register value and the instruction which
202 /// defines it.
206 };
207 
208 /// Find the def instruction for \p Reg, and underlying value Register folding
209 /// away any copies.
210 ///
211 /// Also walks through hints such as G_ASSERT_ZEXT.
214 
215 /// Find the def instruction for \p Reg, folding away any trivial copies. May
216 /// return nullptr if \p Reg is not a generic virtual register.
217 ///
218 /// Also walks through hints such as G_ASSERT_ZEXT.
220  const MachineRegisterInfo &MRI);
221 
222 /// Find the source register for \p Reg, folding away any trivial copies. It
223 /// will be an output register of the instruction that getDefIgnoringCopies
224 /// returns. May return an invalid register if \p Reg is not a generic virtual
225 /// register.
226 ///
227 /// Also walks through hints such as G_ASSERT_ZEXT.
229 
230 /// Returns an APFloat from Val converted to the appropriate size.
231 APFloat getAPFloatFromSize(double Val, unsigned Size);
232 
233 /// Modify analysis usage so it preserves passes required for the SelectionDAG
234 /// fallback.
236 
237 Optional<APInt> ConstantFoldBinOp(unsigned Opcode, const Register Op1,
238  const Register Op2,
239  const MachineRegisterInfo &MRI);
240 Optional<APFloat> ConstantFoldFPBinOp(unsigned Opcode, const Register Op1,
241  const Register Op2,
242  const MachineRegisterInfo &MRI);
243 
244 Optional<APInt> ConstantFoldExtOp(unsigned Opcode, const Register Op1,
245  uint64_t Imm, const MachineRegisterInfo &MRI);
246 
247 /// Test if the given value is known to have exactly one bit set. This differs
248 /// from computeKnownBits in that it doesn't necessarily determine which bit is
249 /// set.
251  GISelKnownBits *KnownBits = nullptr);
252 
253 /// Returns true if \p Val can be assumed to never be a NaN. If \p SNaN is true,
254 /// this returns if \p Val can be assumed to never be a signaling NaN.
256  bool SNaN = false);
257 
258 /// Returns true if \p Val can be assumed to never be a signaling NaN.
260  return isKnownNeverNaN(Val, MRI, true);
261 }
262 
263 Align inferAlignFromPtrInfo(MachineFunction &MF, const MachinePointerInfo &MPO);
264 
265 /// Return a virtual register corresponding to the incoming argument register \p
266 /// PhysReg. This register is expected to have class \p RC, and optional type \p
267 /// RegTy. This assumes all references to the register will use the same type.
268 ///
269 /// If there is an existing live-in argument register, it will be returned.
270 /// This will also ensure there is a valid copy
271 Register getFunctionLiveInPhysReg(MachineFunction &MF, const TargetInstrInfo &TII,
272  MCRegister PhysReg,
273  const TargetRegisterClass &RC,
274  LLT RegTy = LLT());
275 
276 /// Return the least common multiple type of \p OrigTy and \p TargetTy, by changing the
277 /// number of vector elements or scalar bitwidth. The intent is a
278 /// G_MERGE_VALUES, G_BUILD_VECTOR, or G_CONCAT_VECTORS can be constructed from
279 /// \p OrigTy elements, and unmerged into \p TargetTy
281 LLT getLCMType(LLT OrigTy, LLT TargetTy);
282 
283 /// Return a type where the total size is the greatest common divisor of \p
284 /// OrigTy and \p TargetTy. This will try to either change the number of vector
285 /// elements, or bitwidth of scalars. The intent is the result type can be used
286 /// as the result of a G_UNMERGE_VALUES from \p OrigTy, and then some
287 /// combination of G_MERGE_VALUES, G_BUILD_VECTOR and G_CONCAT_VECTORS (possibly
288 /// with intermediate casts) can re-form \p TargetTy.
289 ///
290 /// If these are vectors with different element types, this will try to produce
291 /// a vector with a compatible total size, but the element type of \p OrigTy. If
292 /// this can't be satisfied, this will produce a scalar smaller than the
293 /// original vector elements.
294 ///
295 /// In the worst case, this returns LLT::scalar(1)
297 LLT getGCDType(LLT OrigTy, LLT TargetTy);
298 
299 /// Represents a value which can be a Register or a constant.
300 ///
301 /// This is useful in situations where an instruction may have an interesting
302 /// register operand or interesting constant operand. For a concrete example,
303 /// \see getVectorSplat.
305  int64_t Cst;
306  Register Reg;
307  bool IsReg;
308 
309 public:
310  explicit RegOrConstant(Register Reg) : Reg(Reg), IsReg(true) {}
311  explicit RegOrConstant(int64_t Cst) : Cst(Cst), IsReg(false) {}
312  bool isReg() const { return IsReg; }
313  bool isCst() const { return !IsReg; }
314  Register getReg() const {
315  assert(isReg() && "Expected a register!");
316  return Reg;
317  }
318  int64_t getCst() const {
319  assert(isCst() && "Expected a constant!");
320  return Cst;
321  }
322 };
323 
324 /// \returns The splat index of a G_SHUFFLE_VECTOR \p MI when \p MI is a splat.
325 /// If \p MI is not a splat, returns None.
326 Optional<int> getSplatIndex(MachineInstr &MI);
327 
328 /// Returns a scalar constant of a G_BUILD_VECTOR splat if it exists.
329 Optional<int64_t> getBuildVectorConstantSplat(const MachineInstr &MI,
330  const MachineRegisterInfo &MRI);
331 
332 /// Return true if the specified instruction is a G_BUILD_VECTOR or
333 /// G_BUILD_VECTOR_TRUNC where all of the elements are 0 or undef.
334 bool isBuildVectorAllZeros(const MachineInstr &MI,
335  const MachineRegisterInfo &MRI);
336 
337 /// Return true if the specified instruction is a G_BUILD_VECTOR or
338 /// G_BUILD_VECTOR_TRUNC where all of the elements are ~0 or undef.
339 bool isBuildVectorAllOnes(const MachineInstr &MI,
340  const MachineRegisterInfo &MRI);
341 
342 /// \returns a value when \p MI is a vector splat. The splat can be either a
343 /// Register or a constant.
344 ///
345 /// Examples:
346 ///
347 /// \code
348 /// %reg = COPY $physreg
349 /// %reg_splat = G_BUILD_VECTOR %reg, %reg, ..., %reg
350 /// \endcode
351 ///
352 /// If called on the G_BUILD_VECTOR above, this will return a RegOrConstant
353 /// containing %reg.
354 ///
355 /// \code
356 /// %cst = G_CONSTANT iN 4
357 /// %constant_splat = G_BUILD_VECTOR %cst, %cst, ..., %cst
358 /// \endcode
359 ///
360 /// In the above case, this will return a RegOrConstant containing 4.
361 Optional<RegOrConstant> getVectorSplat(const MachineInstr &MI,
362  const MachineRegisterInfo &MRI);
363 
364 /// Attempt to match a unary predicate against a scalar/splat constant or every
365 /// element of a constant G_BUILD_VECTOR. If \p ConstVal is null, the source
366 /// value was undef.
367 bool matchUnaryPredicate(const MachineRegisterInfo &MRI, Register Reg,
368  std::function<bool(const Constant *ConstVal)> Match,
369  bool AllowUndefs = false);
370 
371 /// Returns true if given the TargetLowering's boolean contents information,
372 /// the value \p Val contains a true value.
373 bool isConstTrueVal(const TargetLowering &TLI, int64_t Val, bool IsVector,
374  bool IsFP);
375 
376 /// Returns an integer representing true, as defined by the
377 /// TargetBooleanContents.
378 int64_t getICmpTrueVal(const TargetLowering &TLI, bool IsVector, bool IsFP);
379 
380 /// Returns true if the given block should be optimized for size.
381 bool shouldOptForSize(const MachineBasicBlock &MBB, ProfileSummaryInfo *PSI,
382  BlockFrequencyInfo *BFI);
383 } // End namespace llvm.
384 #endif
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
llvm::lltok::APFloat
@ APFloat
Definition: LLToken.h:487
llvm::getDefIgnoringCopies
MachineInstr * getDefIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI)
Find the def instruction for Reg, folding away any trivial copies.
Definition: Utils.cpp:396
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:100
llvm
Definition: AllocatorList.h:23
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::isBuildVectorAllOnes
bool isBuildVectorAllOnes(const MachineInstr &MI, const MachineRegisterInfo &MRI)
Return true if the specified instruction is a G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC where all of the...
Definition: Utils.cpp:910
llvm::ValueAndVReg
Simple struct used to hold a constant integer value and a virtual register.
Definition: Utils.h:174
llvm::GISelKnownBits
Definition: GISelKnownBits.h:29
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
llvm::getAPFloatFromSize
APFloat getAPFloatFromSize(double Val, unsigned Size)
Returns an APFloat from Val converted to the appropriate size.
Definition: Utils.cpp:416
llvm::ISD::ConstantFP
@ ConstantFP
Definition: ISDOpcodes.h:70
StringRef.h
llvm::getOpcodeDef
MachineInstr * getOpcodeDef(unsigned Opcode, Register Reg, const MachineRegisterInfo &MRI)
See if Reg is defined by an single def instruction that is Opcode.
Definition: Utils.cpp:410
llvm::getSrcRegIgnoringCopies
Register getSrcRegIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI)
Find the source register for Reg, folding away any trivial copies.
Definition: Utils.cpp:403
MachineBasicBlock.h
llvm::RegOrConstant::isCst
bool isCst() const
Definition: Utils.h:313
llvm::shouldOptForSize
bool shouldOptForSize(const MachineBasicBlock &MBB, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI)
Returns true if the given block should be optimized for size.
Definition: Utils.cpp:986
llvm::getFunctionLiveInPhysReg
Register getFunctionLiveInPhysReg(MachineFunction &MF, const TargetInstrInfo &TII, MCRegister PhysReg, const TargetRegisterClass &RC, LLT RegTy=LLT())
Return a virtual register corresponding to the incoming argument register PhysReg.
Definition: Utils.cpp:617
llvm::ConstantFoldFPBinOp
Optional< APFloat > ConstantFoldFPBinOp(unsigned Opcode, const Register Op1, const Register Op2, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:484
llvm::RegOrConstant::getCst
int64_t getCst() const
Definition: Utils.h:318
llvm::Optional
Definition: APInt.h:34
llvm::getSelectionDAGFallbackAnalysisUsage
void getSelectionDAGFallbackAnalysisUsage(AnalysisUsage &AU)
Modify analysis usage so it preserves passes required for the SelectionDAG fallback.
Definition: Utils.cpp:741
llvm::reportGISelWarning
void reportGISelWarning(MachineFunction &MF, const TargetPassConfig &TPC, MachineOptimizationRemarkEmitter &MORE, MachineOptimizationRemarkMissed &R)
Report an ISel warning as a missed optimization remark to the LLVMContext's diagnostic stream.
Definition: Utils.cpp:244
llvm::RegOrConstant
Represents a value which can be a Register or a constant.
Definition: Utils.h:304
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
llvm::ValueAndVReg::Value
APInt Value
Definition: Utils.h:175
llvm::constrainSelectedInstRegOperands
bool constrainSelectedInstRegOperands(MachineInstr &I, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI)
Mutate the newly-selected instruction I to constrain its (possibly generic) virtual register operands...
Definition: Utils.cpp:134
llvm::getICmpTrueVal
int64_t getICmpTrueVal(const TargetLowering &TLI, bool IsVector, bool IsFP)
Returns an integer representing true, as defined by the TargetBooleanContents.
Definition: Utils.cpp:974
llvm::RISCVFenceField::R
@ R
Definition: RISCVBaseInfo.h:129
llvm::ValueAndVReg::VReg
Register VReg
Definition: Utils.h:176
llvm::getGCDType
LLVM_READNONE LLT getGCDType(LLT OrigTy, LLT TargetTy)
Return a type where the total size is the greatest common divisor of OrigTy and TargetTy.
Definition: Utils.cpp:796
llvm::RegOrConstant::getReg
Register getReg() const
Definition: Utils.h:314
llvm::AnalysisUsage
Represent the analysis usage information of a pass.
Definition: PassAnalysisSupport.h:47
false
Definition: StackSlotColoring.cpp:142
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:129
llvm::ConstantFoldExtOp
Optional< APInt > ConstantFoldExtOp(unsigned Opcode, const Register Op1, uint64_t Imm, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:651
llvm::ConstantFP
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:255
Align
uint64_t Align
Definition: ELFObjHandler.cpp:83
Register
Promote Memory to Register
Definition: Mem2Reg.cpp:110
llvm::RegOrConstant::isReg
bool isReg() const
Definition: Utils.h:312
LowLevelTypeImpl.h
llvm::matchUnaryPredicate
bool matchUnaryPredicate(const MachineRegisterInfo &MRI, Register Reg, std::function< bool(const Constant *ConstVal)> Match, bool AllowUndefs=false)
Attempt to match a unary predicate against a scalar/splat constant or every element of a constant G_B...
Definition: Utils.cpp:929
llvm::getLCMType
LLVM_READNONE LLT getLCMType(LLT OrigTy, LLT TargetTy)
Return the least common multiple type of OrigTy and TargetTy, by changing the number of vector elemen...
Definition: Utils.cpp:751
llvm::APFloat
Definition: APFloat.h:701
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::isConstTrueVal
bool isConstTrueVal(const TargetLowering &TLI, int64_t Val, bool IsVector, bool IsFP)
Returns true if given the TargetLowering's boolean contents information, the value Val contains a tru...
Definition: Utils.cpp:961
llvm::inferAlignFromPtrInfo
Align inferAlignFromPtrInfo(MachineFunction &MF, const MachinePointerInfo &MPO)
Definition: Utils.cpp:600
llvm::isBuildVectorAllZeros
bool isBuildVectorAllZeros(const MachineInstr &MI, const MachineRegisterInfo &MRI)
Return true if the specified instruction is a G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC where all of the...
Definition: Utils.cpp:905
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::getConstantVRegSExtVal
Optional< int64_t > getConstantVRegSExtVal(Register VReg, const MachineRegisterInfo &MRI)
If VReg is defined by a G_CONSTANT fits in int64_t returns it.
Definition: Utils.cpp:281
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
function
print Print MemDeps of function
Definition: MemDepPrinter.cpp:83
llvm::isTriviallyDead
bool isTriviallyDead(const MachineInstr &MI, const MachineRegisterInfo &MRI)
Check whether an instruction MI is dead: it only defines dead virtual registers, and doesn't have oth...
Definition: Utils.cpp:194
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:71
llvm::getConstantVRegVal
Optional< APInt > getConstantVRegVal(Register VReg, const MachineRegisterInfo &MRI)
If VReg is defined by a G_CONSTANT, return the corresponding value.
Definition: Utils.cpp:270
llvm::constrainRegToClass
Register constrainRegToClass(MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, Register Reg, const TargetRegisterClass &RegClass)
Try to constrain Reg to the specified register class.
Definition: Utils.cpp:38
llvm::AMDGPUISD::BFI
@ BFI
Definition: AMDGPUISelLowering.h:419
llvm::isKnownNeverNaN
bool isKnownNeverNaN(const Value *V, const TargetLibraryInfo *TLI, unsigned Depth=0)
Return true if the floating-point scalar value is not a NaN or if the floating-point vector value has...
Definition: ValueTracking.cpp:3633
MORE
#define MORE()
Definition: regcomp.c:252
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
LLVM_READNONE
#define LLVM_READNONE
Definition: Compiler.h:205
Alignment.h
llvm::KnownBits
Definition: KnownBits.h:23
llvm::getBuildVectorConstantSplat
Optional< int64_t > getBuildVectorConstantSplat(const MachineInstr &MI, const MachineRegisterInfo &MRI)
Returns a scalar constant of a G_BUILD_VECTOR splat if it exists.
Definition: Utils.cpp:884
llvm::DefinitionAndSourceRegister
Simple struct used to hold a Register value and the instruction which defines it.
Definition: Utils.h:203
llvm::canReplaceReg
bool canReplaceReg(Register DstReg, Register SrcReg, MachineRegisterInfo &MRI)
Check if DstReg can be replaced with SrcReg depending on the register constraints.
Definition: Utils.cpp:180
llvm::isKnownNeverSNaN
bool isKnownNeverSNaN(Register Val, const MachineRegisterInfo &MRI)
Returns true if Val can be assumed to never be a signaling NaN.
Definition: Utils.h:259
llvm::getVectorSplat
Optional< RegOrConstant > getVectorSplat(const MachineInstr &MI, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:915
llvm::RegOrConstant::RegOrConstant
RegOrConstant(int64_t Cst)
Definition: Utils.h:311
llvm::reportGISelFailure
void reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC, MachineOptimizationRemarkEmitter &MORE, MachineOptimizationRemarkMissed &R)
Report an ISel error as a missed optimization remark to the LLVMContext's diagnostic stream.
Definition: Utils.cpp:250
llvm::getSplatIndex
int getSplatIndex(ArrayRef< int > Mask)
If all non-negative Mask elements are the same value, return that value.
Definition: VectorUtils.cpp:328
llvm::constrainOperandRegClass
Register constrainOperandRegClass(const MachineFunction &MF, const TargetRegisterInfo &TRI, MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, MachineInstr &InsertPt, const TargetRegisterClass &RegClass, MachineOperand &RegMO)
Constrain the Register operand OpIdx, so that it is now constrained to the TargetRegisterClass passed...
Definition: Utils.cpp:48
llvm::getConstantFPVRegVal
const ConstantFP * getConstantFPVRegVal(Register VReg, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:369
Register.h
llvm::isKnownToBeAPowerOfTwo
bool isKnownToBeAPowerOfTwo(const Value *V, const DataLayout &DL, bool OrZero=false, unsigned Depth=0, AssumptionCache *AC=nullptr, const Instruction *CxtI=nullptr, const DominatorTree *DT=nullptr, bool UseInstrInfo=true)
Return true if the given value is known to have exactly one bit set when defined.
Definition: ValueTracking.cpp:295
llvm::RegOrConstant::RegOrConstant
RegOrConstant(Register Reg)
Definition: Utils.h:310
llvm::DefinitionAndSourceRegister::Reg
Register Reg
Definition: Utils.h:205
llvm::DefinitionAndSourceRegister::MI
MachineInstr * MI
Definition: Utils.h:204
true
basic Basic Alias true
Definition: BasicAliasAnalysis.cpp:1789
llvm::getDefSrcRegIgnoringCopies
Optional< DefinitionAndSourceRegister > getDefSrcRegIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI)
Find the def instruction for Reg, and underlying value Register folding away any copies.
Definition: Utils.cpp:377
PassName
static const char PassName[]
Definition: X86LowerAMXIntrinsics.cpp:666
llvm::getConstantVRegValWithLookThrough
Optional< ValueAndVReg > getConstantVRegValWithLookThrough(Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs=true, bool HandleFConstants=true, bool LookThroughAnyExt=false)
If VReg is defined by a statically evaluable chain of instructions rooted on a G_F/CONSTANT (LookThro...
Definition: Utils.cpp:289
llvm::ConstantFoldBinOp
Optional< APInt > ConstantFoldBinOp(unsigned Opcode, const Register Op1, const Register Op2, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:429