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Utils.h
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1 //==-- llvm/CodeGen/GlobalISel/Utils.h ---------------------------*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file This file declares the API of helper functions used throughout the
10 /// GlobalISel pipeline.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_CODEGEN_GLOBALISEL_UTILS_H
15 #define LLVM_CODEGEN_GLOBALISEL_UTILS_H
16 
17 #include "GISelWorkList.h"
18 #include "llvm/ADT/APFloat.h"
19 #include "llvm/ADT/StringRef.h"
20 #include "llvm/CodeGen/Register.h"
21 #include "llvm/IR/DebugLoc.h"
22 #include "llvm/Support/Alignment.h"
23 #include "llvm/Support/Casting.h"
25 #include <cstdint>
26 
27 namespace llvm {
28 
29 class AnalysisUsage;
30 class LostDebugLocObserver;
31 class MachineBasicBlock;
32 class BlockFrequencyInfo;
33 class GISelKnownBits;
34 class MachineFunction;
35 class MachineInstr;
36 class MachineOperand;
37 class MachineOptimizationRemarkEmitter;
38 class MachineOptimizationRemarkMissed;
39 struct MachinePointerInfo;
40 class MachineRegisterInfo;
41 class MCInstrDesc;
42 class ProfileSummaryInfo;
43 class RegisterBankInfo;
44 class TargetInstrInfo;
45 class TargetLowering;
46 class TargetPassConfig;
47 class TargetRegisterInfo;
48 class TargetRegisterClass;
49 class ConstantFP;
50 class APFloat;
51 
52 // Convenience macros for dealing with vector reduction opcodes.
53 #define GISEL_VECREDUCE_CASES_ALL \
54  case TargetOpcode::G_VECREDUCE_SEQ_FADD: \
55  case TargetOpcode::G_VECREDUCE_SEQ_FMUL: \
56  case TargetOpcode::G_VECREDUCE_FADD: \
57  case TargetOpcode::G_VECREDUCE_FMUL: \
58  case TargetOpcode::G_VECREDUCE_FMAX: \
59  case TargetOpcode::G_VECREDUCE_FMIN: \
60  case TargetOpcode::G_VECREDUCE_ADD: \
61  case TargetOpcode::G_VECREDUCE_MUL: \
62  case TargetOpcode::G_VECREDUCE_AND: \
63  case TargetOpcode::G_VECREDUCE_OR: \
64  case TargetOpcode::G_VECREDUCE_XOR: \
65  case TargetOpcode::G_VECREDUCE_SMAX: \
66  case TargetOpcode::G_VECREDUCE_SMIN: \
67  case TargetOpcode::G_VECREDUCE_UMAX: \
68  case TargetOpcode::G_VECREDUCE_UMIN:
69 
70 #define GISEL_VECREDUCE_CASES_NONSEQ \
71  case TargetOpcode::G_VECREDUCE_FADD: \
72  case TargetOpcode::G_VECREDUCE_FMUL: \
73  case TargetOpcode::G_VECREDUCE_FMAX: \
74  case TargetOpcode::G_VECREDUCE_FMIN: \
75  case TargetOpcode::G_VECREDUCE_ADD: \
76  case TargetOpcode::G_VECREDUCE_MUL: \
77  case TargetOpcode::G_VECREDUCE_AND: \
78  case TargetOpcode::G_VECREDUCE_OR: \
79  case TargetOpcode::G_VECREDUCE_XOR: \
80  case TargetOpcode::G_VECREDUCE_SMAX: \
81  case TargetOpcode::G_VECREDUCE_SMIN: \
82  case TargetOpcode::G_VECREDUCE_UMAX: \
83  case TargetOpcode::G_VECREDUCE_UMIN:
84 
85 /// Try to constrain Reg to the specified register class. If this fails,
86 /// create a new virtual register in the correct class.
87 ///
88 /// \return The virtual register constrained to the right register class.
89 Register constrainRegToClass(MachineRegisterInfo &MRI,
90  const TargetInstrInfo &TII,
91  const RegisterBankInfo &RBI, Register Reg,
92  const TargetRegisterClass &RegClass);
93 
94 /// Constrain the Register operand OpIdx, so that it is now constrained to the
95 /// TargetRegisterClass passed as an argument (RegClass).
96 /// If this fails, create a new virtual register in the correct class and insert
97 /// a COPY before \p InsertPt if it is a use or after if it is a definition.
98 /// In both cases, the function also updates the register of RegMo. The debug
99 /// location of \p InsertPt is used for the new copy.
100 ///
101 /// \return The virtual register constrained to the right register class.
102 Register constrainOperandRegClass(const MachineFunction &MF,
103  const TargetRegisterInfo &TRI,
104  MachineRegisterInfo &MRI,
105  const TargetInstrInfo &TII,
106  const RegisterBankInfo &RBI,
107  MachineInstr &InsertPt,
108  const TargetRegisterClass &RegClass,
109  MachineOperand &RegMO);
110 
111 /// Try to constrain Reg so that it is usable by argument OpIdx of the provided
112 /// MCInstrDesc \p II. If this fails, create a new virtual register in the
113 /// correct class and insert a COPY before \p InsertPt if it is a use or after
114 /// if it is a definition. In both cases, the function also updates the register
115 /// of RegMo.
116 /// This is equivalent to constrainOperandRegClass(..., RegClass, ...)
117 /// with RegClass obtained from the MCInstrDesc. The debug location of \p
118 /// InsertPt is used for the new copy.
119 ///
120 /// \return The virtual register constrained to the right register class.
121 Register constrainOperandRegClass(const MachineFunction &MF,
122  const TargetRegisterInfo &TRI,
123  MachineRegisterInfo &MRI,
124  const TargetInstrInfo &TII,
125  const RegisterBankInfo &RBI,
126  MachineInstr &InsertPt, const MCInstrDesc &II,
127  MachineOperand &RegMO, unsigned OpIdx);
128 
129 /// Mutate the newly-selected instruction \p I to constrain its (possibly
130 /// generic) virtual register operands to the instruction's register class.
131 /// This could involve inserting COPYs before (for uses) or after (for defs).
132 /// This requires the number of operands to match the instruction description.
133 /// \returns whether operand regclass constraining succeeded.
134 ///
135 // FIXME: Not all instructions have the same number of operands. We should
136 // probably expose a constrain helper per operand and let the target selector
137 // constrain individual registers, like fast-isel.
138 bool constrainSelectedInstRegOperands(MachineInstr &I,
139  const TargetInstrInfo &TII,
140  const TargetRegisterInfo &TRI,
141  const RegisterBankInfo &RBI);
142 
143 /// Check if DstReg can be replaced with SrcReg depending on the register
144 /// constraints.
145 bool canReplaceReg(Register DstReg, Register SrcReg, MachineRegisterInfo &MRI);
146 
147 /// Check whether an instruction \p MI is dead: it only defines dead virtual
148 /// registers, and doesn't have other side effects.
149 bool isTriviallyDead(const MachineInstr &MI, const MachineRegisterInfo &MRI);
150 
151 /// Report an ISel error as a missed optimization remark to the LLVMContext's
152 /// diagnostic stream. Set the FailedISel MachineFunction property.
153 void reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC,
154  MachineOptimizationRemarkEmitter &MORE,
155  MachineOptimizationRemarkMissed &R);
156 
157 void reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC,
158  MachineOptimizationRemarkEmitter &MORE,
159  const char *PassName, StringRef Msg,
160  const MachineInstr &MI);
161 
162 /// Report an ISel warning as a missed optimization remark to the LLVMContext's
163 /// diagnostic stream.
164 void reportGISelWarning(MachineFunction &MF, const TargetPassConfig &TPC,
165  MachineOptimizationRemarkEmitter &MORE,
166  MachineOptimizationRemarkMissed &R);
167 
168 /// If \p VReg is defined by a G_CONSTANT, return the corresponding value.
169 Optional<APInt> getIConstantVRegVal(Register VReg,
170  const MachineRegisterInfo &MRI);
171 
172 /// If \p VReg is defined by a G_CONSTANT fits in int64_t returns it.
173 Optional<int64_t> getIConstantVRegSExtVal(Register VReg,
174  const MachineRegisterInfo &MRI);
175 
176 /// Simple struct used to hold a constant integer value and a virtual
177 /// register.
178 struct ValueAndVReg {
181 };
182 
183 /// If \p VReg is defined by a statically evaluable chain of instructions rooted
184 /// on a G_CONSTANT returns its APInt value and def register.
187  const MachineRegisterInfo &MRI,
188  bool LookThroughInstrs = true);
189 
190 /// If \p VReg is defined by a statically evaluable chain of instructions rooted
191 /// on a G_CONSTANT or G_FCONSTANT returns its value as APInt and def register.
193  Register VReg, const MachineRegisterInfo &MRI,
194  bool LookThroughInstrs = true, bool LookThroughAnyExt = false);
195 
199 };
200 
201 /// If \p VReg is defined by a statically evaluable chain of instructions rooted
202 /// on a G_FCONSTANT returns its APFloat value and def register.
205  const MachineRegisterInfo &MRI,
206  bool LookThroughInstrs = true);
207 
209  const MachineRegisterInfo &MRI);
210 
211 /// See if Reg is defined by an single def instruction that is
212 /// Opcode. Also try to do trivial folding if it's a COPY with
213 /// same types. Returns null otherwise.
214 MachineInstr *getOpcodeDef(unsigned Opcode, Register Reg,
215  const MachineRegisterInfo &MRI);
216 
217 /// Simple struct used to hold a Register value and the instruction which
218 /// defines it.
222 };
223 
224 /// Find the def instruction for \p Reg, and underlying value Register folding
225 /// away any copies.
226 ///
227 /// Also walks through hints such as G_ASSERT_ZEXT.
230 
231 /// Find the def instruction for \p Reg, folding away any trivial copies. May
232 /// return nullptr if \p Reg is not a generic virtual register.
233 ///
234 /// Also walks through hints such as G_ASSERT_ZEXT.
236  const MachineRegisterInfo &MRI);
237 
238 /// Find the source register for \p Reg, folding away any trivial copies. It
239 /// will be an output register of the instruction that getDefIgnoringCopies
240 /// returns. May return an invalid register if \p Reg is not a generic virtual
241 /// register.
242 ///
243 /// Also walks through hints such as G_ASSERT_ZEXT.
245 
246 // Templated variant of getOpcodeDef returning a MachineInstr derived T.
247 /// See if Reg is defined by an single def instruction of type T
248 /// Also try to do trivial folding if it's a COPY with
249 /// same types. Returns null otherwise.
250 template <class T>
253  return dyn_cast_or_null<T>(DefMI);
254 }
255 
256 /// Returns an APFloat from Val converted to the appropriate size.
257 APFloat getAPFloatFromSize(double Val, unsigned Size);
258 
259 /// Modify analysis usage so it preserves passes required for the SelectionDAG
260 /// fallback.
261 void getSelectionDAGFallbackAnalysisUsage(AnalysisUsage &AU);
262 
263 Optional<APInt> ConstantFoldBinOp(unsigned Opcode, const Register Op1,
264  const Register Op2,
265  const MachineRegisterInfo &MRI);
266 Optional<APFloat> ConstantFoldFPBinOp(unsigned Opcode, const Register Op1,
267  const Register Op2,
268  const MachineRegisterInfo &MRI);
269 
270 /// Tries to constant fold a vector binop with sources \p Op1 and \p Op2.
271 /// Returns an empty vector on failure.
272 SmallVector<APInt> ConstantFoldVectorBinop(unsigned Opcode, const Register Op1,
273  const Register Op2,
274  const MachineRegisterInfo &MRI);
275 
276 Optional<APInt> ConstantFoldExtOp(unsigned Opcode, const Register Op1,
277  uint64_t Imm, const MachineRegisterInfo &MRI);
278 
279 Optional<APFloat> ConstantFoldIntToFloat(unsigned Opcode, LLT DstTy,
280  Register Src,
281  const MachineRegisterInfo &MRI);
282 
283 /// Tries to constant fold a G_CTLZ operation on \p Src. If \p Src is a vector
284 /// then it tries to do an element-wise constant fold.
285 Optional<SmallVector<unsigned>>
286 ConstantFoldCTLZ(Register Src, const MachineRegisterInfo &MRI);
287 
288 /// Test if the given value is known to have exactly one bit set. This differs
289 /// from computeKnownBits in that it doesn't necessarily determine which bit is
290 /// set.
291 bool isKnownToBeAPowerOfTwo(Register Val, const MachineRegisterInfo &MRI,
292  GISelKnownBits *KnownBits = nullptr);
293 
294 /// Returns true if \p Val can be assumed to never be a NaN. If \p SNaN is true,
295 /// this returns if \p Val can be assumed to never be a signaling NaN.
296 bool isKnownNeverNaN(Register Val, const MachineRegisterInfo &MRI,
297  bool SNaN = false);
298 
299 /// Returns true if \p Val can be assumed to never be a signaling NaN.
301  return isKnownNeverNaN(Val, MRI, true);
302 }
303 
304 Align inferAlignFromPtrInfo(MachineFunction &MF, const MachinePointerInfo &MPO);
305 
306 /// Return a virtual register corresponding to the incoming argument register \p
307 /// PhysReg. This register is expected to have class \p RC, and optional type \p
308 /// RegTy. This assumes all references to the register will use the same type.
309 ///
310 /// If there is an existing live-in argument register, it will be returned.
311 /// This will also ensure there is a valid copy
312 Register getFunctionLiveInPhysReg(MachineFunction &MF,
313  const TargetInstrInfo &TII,
314  MCRegister PhysReg,
315  const TargetRegisterClass &RC,
316  const DebugLoc &DL, LLT RegTy = LLT());
317 
318 /// Return the least common multiple type of \p OrigTy and \p TargetTy, by changing the
319 /// number of vector elements or scalar bitwidth. The intent is a
320 /// G_MERGE_VALUES, G_BUILD_VECTOR, or G_CONCAT_VECTORS can be constructed from
321 /// \p OrigTy elements, and unmerged into \p TargetTy
323 LLT getLCMType(LLT OrigTy, LLT TargetTy);
324 
326 /// Return smallest type that covers both \p OrigTy and \p TargetTy and is
327 /// multiple of TargetTy.
328 LLT getCoverTy(LLT OrigTy, LLT TargetTy);
329 
330 /// Return a type where the total size is the greatest common divisor of \p
331 /// OrigTy and \p TargetTy. This will try to either change the number of vector
332 /// elements, or bitwidth of scalars. The intent is the result type can be used
333 /// as the result of a G_UNMERGE_VALUES from \p OrigTy, and then some
334 /// combination of G_MERGE_VALUES, G_BUILD_VECTOR and G_CONCAT_VECTORS (possibly
335 /// with intermediate casts) can re-form \p TargetTy.
336 ///
337 /// If these are vectors with different element types, this will try to produce
338 /// a vector with a compatible total size, but the element type of \p OrigTy. If
339 /// this can't be satisfied, this will produce a scalar smaller than the
340 /// original vector elements.
341 ///
342 /// In the worst case, this returns LLT::scalar(1)
344 LLT getGCDType(LLT OrigTy, LLT TargetTy);
345 
346 /// Represents a value which can be a Register or a constant.
347 ///
348 /// This is useful in situations where an instruction may have an interesting
349 /// register operand or interesting constant operand. For a concrete example,
350 /// \see getVectorSplat.
352  int64_t Cst;
353  Register Reg;
354  bool IsReg;
355 
356 public:
357  explicit RegOrConstant(Register Reg) : Reg(Reg), IsReg(true) {}
358  explicit RegOrConstant(int64_t Cst) : Cst(Cst), IsReg(false) {}
359  bool isReg() const { return IsReg; }
360  bool isCst() const { return !IsReg; }
361  Register getReg() const {
362  assert(isReg() && "Expected a register!");
363  return Reg;
364  }
365  int64_t getCst() const {
366  assert(isCst() && "Expected a constant!");
367  return Cst;
368  }
369 };
370 
371 /// \returns The splat index of a G_SHUFFLE_VECTOR \p MI when \p MI is a splat.
372 /// If \p MI is not a splat, returns None.
373 Optional<int> getSplatIndex(MachineInstr &MI);
374 
375 /// \returns the scalar integral splat value of \p Reg if possible.
376 Optional<APInt> getIConstantSplatVal(const Register Reg,
377  const MachineRegisterInfo &MRI);
378 
379 /// \returns the scalar integral splat value defined by \p MI if possible.
380 Optional<APInt> getIConstantSplatVal(const MachineInstr &MI,
381  const MachineRegisterInfo &MRI);
382 
383 /// \returns the scalar sign extended integral splat value of \p Reg if
384 /// possible.
385 Optional<int64_t> getIConstantSplatSExtVal(const Register Reg,
386  const MachineRegisterInfo &MRI);
387 
388 /// \returns the scalar sign extended integral splat value defined by \p MI if
389 /// possible.
390 Optional<int64_t> getIConstantSplatSExtVal(const MachineInstr &MI,
391  const MachineRegisterInfo &MRI);
392 
393 /// Returns a floating point scalar constant of a build vector splat if it
394 /// exists. When \p AllowUndef == true some elements can be undef but not all.
395 Optional<FPValueAndVReg> getFConstantSplat(Register VReg,
396  const MachineRegisterInfo &MRI,
397  bool AllowUndef = true);
398 
399 /// Return true if the specified register is defined by G_BUILD_VECTOR or
400 /// G_BUILD_VECTOR_TRUNC where all of the elements are \p SplatValue or undef.
401 bool isBuildVectorConstantSplat(const Register Reg,
402  const MachineRegisterInfo &MRI,
403  int64_t SplatValue, bool AllowUndef);
404 
405 /// Return true if the specified instruction is a G_BUILD_VECTOR or
406 /// G_BUILD_VECTOR_TRUNC where all of the elements are \p SplatValue or undef.
407 bool isBuildVectorConstantSplat(const MachineInstr &MI,
408  const MachineRegisterInfo &MRI,
409  int64_t SplatValue, bool AllowUndef);
410 
411 /// Return true if the specified instruction is a G_BUILD_VECTOR or
412 /// G_BUILD_VECTOR_TRUNC where all of the elements are 0 or undef.
413 bool isBuildVectorAllZeros(const MachineInstr &MI,
414  const MachineRegisterInfo &MRI,
415  bool AllowUndef = false);
416 
417 /// Return true if the specified instruction is a G_BUILD_VECTOR or
418 /// G_BUILD_VECTOR_TRUNC where all of the elements are ~0 or undef.
419 bool isBuildVectorAllOnes(const MachineInstr &MI,
420  const MachineRegisterInfo &MRI,
421  bool AllowUndef = false);
422 
423 /// Return true if the specified instruction is known to be a constant, or a
424 /// vector of constants.
425 ///
426 /// If \p AllowFP is true, this will consider G_FCONSTANT in addition to
427 /// G_CONSTANT. If \p AllowOpaqueConstants is true, constant-like instructions
428 /// such as G_GLOBAL_VALUE will also be considered.
429 bool isConstantOrConstantVector(const MachineInstr &MI,
430  const MachineRegisterInfo &MRI,
431  bool AllowFP = true,
432  bool AllowOpaqueConstants = true);
433 
434 /// Return true if the value is a constant 0 integer or a splatted vector of a
435 /// constant 0 integer (with no undefs if \p AllowUndefs is false). This will
436 /// handle G_BUILD_VECTOR and G_BUILD_VECTOR_TRUNC as truncation is not an issue
437 /// for null values.
438 bool isNullOrNullSplat(const MachineInstr &MI, const MachineRegisterInfo &MRI,
439  bool AllowUndefs = false);
440 
441 /// Return true if the value is a constant -1 integer or a splatted vector of a
442 /// constant -1 integer (with no undefs if \p AllowUndefs is false).
443 bool isAllOnesOrAllOnesSplat(const MachineInstr &MI,
444  const MachineRegisterInfo &MRI,
445  bool AllowUndefs = false);
446 
447 /// \returns a value when \p MI is a vector splat. The splat can be either a
448 /// Register or a constant.
449 ///
450 /// Examples:
451 ///
452 /// \code
453 /// %reg = COPY $physreg
454 /// %reg_splat = G_BUILD_VECTOR %reg, %reg, ..., %reg
455 /// \endcode
456 ///
457 /// If called on the G_BUILD_VECTOR above, this will return a RegOrConstant
458 /// containing %reg.
459 ///
460 /// \code
461 /// %cst = G_CONSTANT iN 4
462 /// %constant_splat = G_BUILD_VECTOR %cst, %cst, ..., %cst
463 /// \endcode
464 ///
465 /// In the above case, this will return a RegOrConstant containing 4.
466 Optional<RegOrConstant> getVectorSplat(const MachineInstr &MI,
467  const MachineRegisterInfo &MRI);
468 
469 /// Determines if \p MI defines a constant integer or a build vector of
470 /// constant integers. Treats undef values as constants.
471 bool isConstantOrConstantVector(MachineInstr &MI,
472  const MachineRegisterInfo &MRI);
473 
474 /// Determines if \p MI defines a constant integer or a splat vector of
475 /// constant integers.
476 /// \returns the scalar constant or None.
477 Optional<APInt> isConstantOrConstantSplatVector(MachineInstr &MI,
478  const MachineRegisterInfo &MRI);
479 
480 /// Attempt to match a unary predicate against a scalar/splat constant or every
481 /// element of a constant G_BUILD_VECTOR. If \p ConstVal is null, the source
482 /// value was undef.
483 bool matchUnaryPredicate(const MachineRegisterInfo &MRI, Register Reg,
484  std::function<bool(const Constant *ConstVal)> Match,
485  bool AllowUndefs = false);
486 
487 /// Returns true if given the TargetLowering's boolean contents information,
488 /// the value \p Val contains a true value.
489 bool isConstTrueVal(const TargetLowering &TLI, int64_t Val, bool IsVector,
490  bool IsFP);
491 /// \returns true if given the TargetLowering's boolean contents information,
492 /// the value \p Val contains a false value.
493 bool isConstFalseVal(const TargetLowering &TLI, int64_t Val, bool IsVector,
494  bool IsFP);
495 
496 /// Returns an integer representing true, as defined by the
497 /// TargetBooleanContents.
498 int64_t getICmpTrueVal(const TargetLowering &TLI, bool IsVector, bool IsFP);
499 
500 /// Returns true if the given block should be optimized for size.
501 bool shouldOptForSize(const MachineBasicBlock &MBB, ProfileSummaryInfo *PSI,
502  BlockFrequencyInfo *BFI);
503 
506  LostDebugLocObserver *LocObserver,
507  SmallInstListTy &DeadInstChain);
509  LostDebugLocObserver *LocObserver = nullptr);
511  LostDebugLocObserver *LocObserver = nullptr);
512 
513 /// Assuming the instruction \p MI is going to be deleted, attempt to salvage
514 /// debug users of \p MI by writing the effect of \p MI in a DIExpression.
516 
517 } // End namespace llvm.
518 #endif
llvm::lltok::APFloat
@ APFloat
Definition: LLToken.h:438
llvm::getIConstantVRegSExtVal
Optional< int64_t > getIConstantVRegSExtVal(Register VReg, const MachineRegisterInfo &MRI)
If VReg is defined by a G_CONSTANT fits in int64_t returns it.
Definition: Utils.cpp:300
llvm::saveUsesAndErase
void saveUsesAndErase(MachineInstr &MI, MachineRegisterInfo &MRI, LostDebugLocObserver *LocObserver, SmallInstListTy &DeadInstChain)
Definition: Utils.cpp:1326
llvm::getDefIgnoringCopies
MachineInstr * getDefIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI)
Find the def instruction for Reg, folding away any trivial copies.
Definition: Utils.cpp:461
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:108
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::LostDebugLocObserver
Definition: LostDebugLocObserver.h:19
llvm::FPValueAndVReg::Value
APFloat Value
Definition: Utils.h:197
llvm::ValueAndVReg
Simple struct used to hold a constant integer value and a virtual register.
Definition: Utils.h:178
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
llvm::getAPFloatFromSize
APFloat getAPFloatFromSize(double Val, unsigned Size)
Returns an APFloat from Val converted to the appropriate size.
Definition: Utils.cpp:481
llvm::ISD::ConstantFP
@ ConstantFP
Definition: ISDOpcodes.h:77
StringRef.h
llvm::getOpcodeDef
MachineInstr * getOpcodeDef(unsigned Opcode, Register Reg, const MachineRegisterInfo &MRI)
See if Reg is defined by an single def instruction that is Opcode.
Definition: Utils.cpp:475
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::getSrcRegIgnoringCopies
Register getSrcRegIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI)
Find the source register for Reg, folding away any trivial copies.
Definition: Utils.cpp:468
llvm::isAllOnesOrAllOnesSplat
bool isAllOnesOrAllOnesSplat(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowUndefs=false)
Return true if the value is a constant -1 integer or a splatted vector of a constant -1 integer (with...
Definition: Utils.cpp:1235
llvm::RegOrConstant::isCst
bool isCst() const
Definition: Utils.h:360
llvm::isConstantOrConstantVector
bool isConstantOrConstantVector(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowFP=true, bool AllowOpaqueConstants=true)
Return true if the specified instruction is known to be a constant, or a vector of constants.
Definition: Utils.cpp:1185
true
basic Basic Alias true
Definition: BasicAliasAnalysis.cpp:1835
llvm::shouldOptForSize
bool shouldOptForSize(const MachineBasicBlock &MBB, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI)
Returns true if the given block should be optimized for size.
Definition: Utils.cpp:1319
llvm::eraseInstrs
void eraseInstrs(ArrayRef< MachineInstr * > DeadInstrs, MachineRegisterInfo &MRI, LostDebugLocObserver *LocObserver=nullptr)
Definition: Utils.cpp:1340
llvm::ConstantFoldFPBinOp
Optional< APFloat > ConstantFoldFPBinOp(unsigned Opcode, const Register Op1, const Register Op2, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:558
llvm::RegOrConstant::getCst
int64_t getCst() const
Definition: Utils.h:365
llvm::Optional
Definition: APInt.h:33
T
#define T
Definition: Mips16ISelLowering.cpp:341
llvm::isConstFalseVal
bool isConstFalseVal(const TargetLowering &TLI, int64_t Val, bool IsVector, bool IsFP)
Definition: Utils.cpp:1295
llvm::getSelectionDAGFallbackAnalysisUsage
void getSelectionDAGFallbackAnalysisUsage(AnalysisUsage &AU)
Modify analysis usage so it preserves passes required for the SelectionDAG fallback.
Definition: Utils.cpp:894
llvm::reportGISelWarning
void reportGISelWarning(MachineFunction &MF, const TargetPassConfig &TPC, MachineOptimizationRemarkEmitter &MORE, MachineOptimizationRemarkMissed &R)
Report an ISel warning as a missed optimization remark to the LLVMContext's diagnostic stream.
Definition: Utils.cpp:262
llvm::RegOrConstant
Represents a value which can be a Register or a constant.
Definition: Utils.h:351
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
llvm::ValueAndVReg::Value
APInt Value
Definition: Utils.h:179
llvm::constrainSelectedInstRegOperands
bool constrainSelectedInstRegOperands(MachineInstr &I, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI)
Mutate the newly-selected instruction I to constrain its (possibly generic) virtual register operands...
Definition: Utils.cpp:152
llvm::getICmpTrueVal
int64_t getICmpTrueVal(const TargetLowering &TLI, bool IsVector, bool IsFP)
Returns an integer representing true, as defined by the TargetBooleanContents.
Definition: Utils.cpp:1307
llvm::RISCVFenceField::R
@ R
Definition: RISCVBaseInfo.h:265
llvm::ValueAndVReg::VReg
Register VReg
Definition: Utils.h:180
llvm::getFunctionLiveInPhysReg
Register getFunctionLiveInPhysReg(MachineFunction &MF, const TargetInstrInfo &TII, MCRegister PhysReg, const TargetRegisterClass &RC, const DebugLoc &DL, LLT RegTy=LLT())
Return a virtual register corresponding to the incoming argument register PhysReg.
Definition: Utils.cpp:728
llvm::getGCDType
LLVM_READNONE LLT getGCDType(LLT OrigTy, LLT TargetTy)
Return a type where the total size is the greatest common divisor of OrigTy and TargetTy.
Definition: Utils.cpp:959
llvm::RegOrConstant::getReg
Register getReg() const
Definition: Utils.h:361
false
Definition: StackSlotColoring.cpp:141
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:125
llvm::ConstantFoldExtOp
Optional< APInt > ConstantFoldExtOp(unsigned Opcode, const Register Op1, uint64_t Imm, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:761
llvm::salvageDebugInfo
void salvageDebugInfo(const MachineRegisterInfo &MRI, MachineInstr &MI)
Assuming the instruction MI is going to be deleted, attempt to salvage debug users of MI by writing t...
Definition: Utils.cpp:1360
llvm::ConstantFP
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:257
APFloat.h
llvm::ConstantFoldIntToFloat
Optional< APFloat > ConstantFoldIntToFloat(unsigned Opcode, LLT DstTy, Register Src, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:778
llvm::isConstantOrConstantSplatVector
Optional< APInt > isConstantOrConstantSplatVector(MachineInstr &MI, const MachineRegisterInfo &MRI)
Determines if MI defines a constant integer or a splat vector of constant integers.
Definition: Utils.cpp:1205
DebugLoc.h
Align
uint64_t Align
Definition: ELFObjHandler.cpp:81
Register
Promote Memory to Register
Definition: Mem2Reg.cpp:110
llvm::FPValueAndVReg::VReg
Register VReg
Definition: Utils.h:198
llvm::RegOrConstant::isReg
bool isReg() const
Definition: Utils.h:359
LowLevelTypeImpl.h
llvm::matchUnaryPredicate
bool matchUnaryPredicate(const MachineRegisterInfo &MRI, Register Reg, std::function< bool(const Constant *ConstVal)> Match, bool AllowUndefs=false)
Attempt to match a unary predicate against a scalar/splat constant or every element of a constant G_B...
Definition: Utils.cpp:1250
llvm::getLCMType
LLVM_READNONE LLT getLCMType(LLT OrigTy, LLT TargetTy)
Return the least common multiple type of OrigTy and TargetTy, by changing the number of vector elemen...
Definition: Utils.cpp:898
llvm::APFloat
Definition: APFloat.h:707
llvm::FPValueAndVReg
Definition: Utils.h:196
llvm::eraseInstr
void eraseInstr(MachineInstr &MI, MachineRegisterInfo &MRI, LostDebugLocObserver *LocObserver=nullptr)
Definition: Utils.cpp:1355
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
uint64_t
llvm::isConstTrueVal
bool isConstTrueVal(const TargetLowering &TLI, int64_t Val, bool IsVector, bool IsFP)
Returns true if given the TargetLowering's boolean contents information, the value Val contains a tru...
Definition: Utils.cpp:1282
llvm::inferAlignFromPtrInfo
Align inferAlignFromPtrInfo(MachineFunction &MF, const MachinePointerInfo &MPO)
Definition: Utils.cpp:711
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::getCoverTy
LLVM_READNONE LLT getCoverTy(LLT OrigTy, LLT TargetTy)
Return smallest type that covers both OrigTy and TargetTy and is multiple of TargetTy.
Definition: Utils.cpp:944
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
function
print Print MemDeps of function
Definition: MemDepPrinter.cpp:82
llvm::getIConstantVRegVal
Optional< APInt > getIConstantVRegVal(Register VReg, const MachineRegisterInfo &MRI)
If VReg is defined by a G_CONSTANT, return the corresponding value.
Definition: Utils.cpp:288
llvm::isTriviallyDead
bool isTriviallyDead(const MachineInstr &MI, const MachineRegisterInfo &MRI)
Check whether an instruction MI is dead: it only defines dead virtual registers, and doesn't have oth...
Definition: Utils.cpp:212
llvm::getIConstantSplatSExtVal
Optional< int64_t > getIConstantSplatSExtVal(const Register Reg, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:1100
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::getAnyConstantVRegValWithLookThrough
Optional< ValueAndVReg > getAnyConstantVRegValWithLookThrough(Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs=true, bool LookThroughAnyExt=false)
If VReg is defined by a statically evaluable chain of instructions rooted on a G_CONSTANT or G_FCONST...
Definition: Utils.cpp:415
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::constrainRegToClass
Register constrainRegToClass(MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, Register Reg, const TargetRegisterClass &RegClass)
Try to constrain Reg to the specified register class.
Definition: Utils.cpp:43
llvm::getIConstantVRegValWithLookThrough
Optional< ValueAndVReg > getIConstantVRegValWithLookThrough(Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs=true)
If VReg is defined by a statically evaluable chain of instructions rooted on a G_CONSTANT returns its...
Definition: Utils.cpp:409
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::AMDGPUISD::BFI
@ BFI
Definition: AMDGPUISelLowering.h:429
llvm::isKnownNeverNaN
bool isKnownNeverNaN(const Value *V, const TargetLibraryInfo *TLI, unsigned Depth=0)
Return true if the floating-point scalar value is not a NaN or if the floating-point vector value has...
Definition: ValueTracking.cpp:3837
MORE
#define MORE()
Definition: regcomp.c:252
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::isNullOrNullSplat
bool isNullOrNullSplat(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowUndefs=false)
Return true if the value is a constant 0 integer or a splatted vector of a constant 0 integer (with n...
Definition: Utils.cpp:1217
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
GISelWorkList.h
llvm::AMDGPU::SendMsg::Msg
const CustomOperand< const MCSubtargetInfo & > Msg[]
Definition: AMDGPUAsmUtils.cpp:39
llvm::ConstantFoldCTLZ
Optional< SmallVector< unsigned > > ConstantFoldCTLZ(Register Src, const MachineRegisterInfo &MRI)
Tries to constant fold a G_CTLZ operation on Src.
Definition: Utils.cpp:792
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::isBuildVectorAllOnes
bool isBuildVectorAllOnes(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowUndef=false)
Return true if the specified instruction is a G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC where all of the...
Definition: Utils.cpp:1128
LLVM_READNONE
#define LLVM_READNONE
Definition: Compiler.h:189
Alignment.h
llvm::DefinitionAndSourceRegister
Simple struct used to hold a Register value and the instruction which defines it.
Definition: Utils.h:219
llvm::canReplaceReg
bool canReplaceReg(Register DstReg, Register SrcReg, MachineRegisterInfo &MRI)
Check if DstReg can be replaced with SrcReg depending on the register constraints.
Definition: Utils.cpp:198
llvm::getIConstantSplatVal
Optional< APInt > getIConstantSplatVal(const Register Reg, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:1082
Casting.h
llvm::isKnownNeverSNaN
bool isKnownNeverSNaN(Register Val, const MachineRegisterInfo &MRI)
Returns true if Val can be assumed to never be a signaling NaN.
Definition: Utils.h:300
llvm::getVectorSplat
Optional< RegOrConstant > getVectorSplat(const MachineInstr &MI, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:1134
llvm::getFConstantVRegValWithLookThrough
Optional< FPValueAndVReg > getFConstantVRegValWithLookThrough(Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs=true)
If VReg is defined by a statically evaluable chain of instructions rooted on a G_FCONSTANT returns it...
Definition: Utils.cpp:423
llvm::RegOrConstant::RegOrConstant
RegOrConstant(int64_t Cst)
Definition: Utils.h:358
llvm::reportGISelFailure
void reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC, MachineOptimizationRemarkEmitter &MORE, MachineOptimizationRemarkMissed &R)
Report an ISel error as a missed optimization remark to the LLVMContext's diagnostic stream.
Definition: Utils.cpp:268
llvm::RISCVMatInt::Imm
@ Imm
Definition: RISCVMatInt.h:23
llvm::getSplatIndex
int getSplatIndex(ArrayRef< int > Mask)
If all non-negative Mask elements are the same value, return that value.
Definition: VectorUtils.cpp:349
llvm::GISelWorkList
Definition: GISelWorkList.h:27
llvm::getFConstantSplat
Optional< FPValueAndVReg > getFConstantSplat(Register VReg, const MachineRegisterInfo &MRI, bool AllowUndef=true)
Returns a floating point scalar constant of a build vector splat if it exists.
Definition: Utils.cpp:1114
DefMI
MachineInstrBuilder MachineInstrBuilder & DefMI
Definition: AArch64ExpandPseudoInsts.cpp:106
llvm::constrainOperandRegClass
Register constrainOperandRegClass(const MachineFunction &MF, const TargetRegisterInfo &TRI, MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, MachineInstr &InsertPt, const TargetRegisterClass &RegClass, MachineOperand &RegMO)
Constrain the Register operand OpIdx, so that it is now constrained to the TargetRegisterClass passed...
Definition: Utils.cpp:53
llvm::ConstantFoldVectorBinop
SmallVector< APInt > ConstantFoldVectorBinop(unsigned Opcode, const Register Op1, const Register Op2, const MachineRegisterInfo &MRI)
Tries to constant fold a vector binop with sources Op1 and Op2.
Definition: Utils.cpp:613
llvm::isBuildVectorConstantSplat
bool isBuildVectorConstantSplat(const Register Reg, const MachineRegisterInfo &MRI, int64_t SplatValue, bool AllowUndef)
Return true if the specified register is defined by G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC where all ...
Definition: Utils.cpp:1067
llvm::getConstantFPVRegVal
const ConstantFP * getConstantFPVRegVal(Register VReg, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:434
Register.h
llvm::isKnownToBeAPowerOfTwo
bool isKnownToBeAPowerOfTwo(const Value *V, const DataLayout &DL, bool OrZero=false, unsigned Depth=0, AssumptionCache *AC=nullptr, const Instruction *CxtI=nullptr, const DominatorTree *DT=nullptr, bool UseInstrInfo=true)
Return true if the given value is known to have exactly one bit set when defined.
Definition: ValueTracking.cpp:327
llvm::RegOrConstant::RegOrConstant
RegOrConstant(Register Reg)
Definition: Utils.h:357
llvm::DefinitionAndSourceRegister::Reg
Register Reg
Definition: Utils.h:221
llvm::DefinitionAndSourceRegister::MI
MachineInstr * MI
Definition: Utils.h:220
llvm::getDefSrcRegIgnoringCopies
Optional< DefinitionAndSourceRegister > getDefSrcRegIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI)
Find the def instruction for Reg, and underlying value Register folding away any copies.
Definition: Utils.cpp:442
PassName
static const char PassName[]
Definition: X86LowerAMXIntrinsics.cpp:671
llvm::isBuildVectorAllZeros
bool isBuildVectorAllZeros(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowUndef=false)
Return true if the specified instruction is a G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC where all of the...
Definition: Utils.cpp:1122
llvm::ConstantFoldBinOp
Optional< APInt > ConstantFoldBinOp(unsigned Opcode, const Register Op1, const Register Op2, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:494