14#ifndef LLVM_CODEGEN_GLOBALISEL_UTILS_H
15#define LLVM_CODEGEN_GLOBALISEL_UTILS_H
30class LostDebugLocObserver;
31class MachineBasicBlock;
32class BlockFrequencyInfo;
37class MachineOptimizationRemarkEmitter;
38class MachineOptimizationRemarkMissed;
39struct MachinePointerInfo;
40class MachineRegisterInfo;
42class ProfileSummaryInfo;
43class RegisterBankInfo;
46class TargetPassConfig;
47class TargetRegisterInfo;
48class TargetRegisterClass;
53#define GISEL_VECREDUCE_CASES_ALL \
54 case TargetOpcode::G_VECREDUCE_SEQ_FADD: \
55 case TargetOpcode::G_VECREDUCE_SEQ_FMUL: \
56 case TargetOpcode::G_VECREDUCE_FADD: \
57 case TargetOpcode::G_VECREDUCE_FMUL: \
58 case TargetOpcode::G_VECREDUCE_FMAX: \
59 case TargetOpcode::G_VECREDUCE_FMIN: \
60 case TargetOpcode::G_VECREDUCE_ADD: \
61 case TargetOpcode::G_VECREDUCE_MUL: \
62 case TargetOpcode::G_VECREDUCE_AND: \
63 case TargetOpcode::G_VECREDUCE_OR: \
64 case TargetOpcode::G_VECREDUCE_XOR: \
65 case TargetOpcode::G_VECREDUCE_SMAX: \
66 case TargetOpcode::G_VECREDUCE_SMIN: \
67 case TargetOpcode::G_VECREDUCE_UMAX: \
68 case TargetOpcode::G_VECREDUCE_UMIN:
70#define GISEL_VECREDUCE_CASES_NONSEQ \
71 case TargetOpcode::G_VECREDUCE_FADD: \
72 case TargetOpcode::G_VECREDUCE_FMUL: \
73 case TargetOpcode::G_VECREDUCE_FMAX: \
74 case TargetOpcode::G_VECREDUCE_FMIN: \
75 case TargetOpcode::G_VECREDUCE_ADD: \
76 case TargetOpcode::G_VECREDUCE_MUL: \
77 case TargetOpcode::G_VECREDUCE_AND: \
78 case TargetOpcode::G_VECREDUCE_OR: \
79 case TargetOpcode::G_VECREDUCE_XOR: \
80 case TargetOpcode::G_VECREDUCE_SMAX: \
81 case TargetOpcode::G_VECREDUCE_SMIN: \
82 case TargetOpcode::G_VECREDUCE_UMAX: \
83 case TargetOpcode::G_VECREDUCE_UMIN:
90 const TargetInstrInfo &
TII,
92 const TargetRegisterClass &RegClass);
103 const TargetRegisterInfo &
TRI,
104 MachineRegisterInfo &
MRI,
105 const TargetInstrInfo &
TII,
106 const RegisterBankInfo &RBI,
107 MachineInstr &InsertPt,
108 const TargetRegisterClass &RegClass,
109 MachineOperand &RegMO);
122 const TargetRegisterInfo &
TRI,
123 MachineRegisterInfo &
MRI,
124 const TargetInstrInfo &
TII,
125 const RegisterBankInfo &RBI,
126 MachineInstr &InsertPt,
const MCInstrDesc &II,
127 MachineOperand &RegMO,
unsigned OpIdx);
139 const TargetInstrInfo &
TII,
140 const TargetRegisterInfo &
TRI,
141 const RegisterBankInfo &RBI);
154 MachineOptimizationRemarkEmitter &
MORE,
155 MachineOptimizationRemarkMissed &R);
158 MachineOptimizationRemarkEmitter &
MORE,
159 const char *
PassName, StringRef Msg,
160 const MachineInstr &
MI);
165 MachineOptimizationRemarkEmitter &
MORE,
166 MachineOptimizationRemarkMissed &R);
170 const MachineRegisterInfo &
MRI);
174 const MachineRegisterInfo &
MRI);
185std::optional<ValueAndVReg>
188 bool LookThroughInstrs =
true);
194 bool LookThroughInstrs =
true,
bool LookThroughAnyExt =
false);
203std::optional<FPValueAndVReg>
206 bool LookThroughInstrs =
true);
228std::optional<DefinitionAndSourceRegister>
253 return dyn_cast_or_null<T>(
DefMI);
265 const MachineRegisterInfo &
MRI);
268 const MachineRegisterInfo &
MRI);
274 const MachineRegisterInfo &
MRI);
278 const MachineRegisterInfo &
MRI);
282 const MachineRegisterInfo &
MRI);
286std::optional<SmallVector<unsigned>>
293 GISelKnownBits *KnownBits =
nullptr);
314 const TargetInstrInfo &
TII,
316 const TargetRegisterClass &RC,
317 const DebugLoc &
DL, LLT RegTy = LLT());
360 bool isReg()
const {
return IsReg; }
361 bool isCst()
const {
return !IsReg; }
378 const MachineRegisterInfo &
MRI);
382 const MachineRegisterInfo &
MRI);
387 const MachineRegisterInfo &
MRI);
392 const MachineRegisterInfo &
MRI);
397 const MachineRegisterInfo &
MRI,
398 bool AllowUndef =
true);
403 const MachineRegisterInfo &
MRI,
404 int64_t SplatValue,
bool AllowUndef);
409 const MachineRegisterInfo &
MRI,
410 int64_t SplatValue,
bool AllowUndef);
415 const MachineRegisterInfo &
MRI,
416 bool AllowUndef =
false);
421 const MachineRegisterInfo &
MRI,
422 bool AllowUndef =
false);
431 const MachineRegisterInfo &
MRI,
433 bool AllowOpaqueConstants =
true);
440 bool AllowUndefs =
false);
445 const MachineRegisterInfo &
MRI,
446 bool AllowUndefs =
false);
468 const MachineRegisterInfo &
MRI);
473 const MachineRegisterInfo &
MRI);
480 const MachineRegisterInfo &
MRI);
486 std::function<
bool(
const Constant *ConstVal)>
Match,
487 bool AllowUndefs =
false);
491bool isConstTrueVal(
const TargetLowering &TLI, int64_t Val,
bool IsVector,
495bool isConstFalseVal(
const TargetLowering &TLI, int64_t Val,
bool IsVector,
500int64_t
getICmpTrueVal(
const TargetLowering &TLI,
bool IsVector,
bool IsFP);
504 BlockFrequencyInfo *BFI);
unsigned const MachineRegisterInfo * MRI
MachineInstrBuilder MachineInstrBuilder & DefMI
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
This file declares a class to represent arbitrary precision floating point values and provide a varie...
const HexagonInstrInfo * TII
Implement a low-level type suitable for MachineInstr level instruction selection.
unsigned const TargetRegisterInfo * TRI
Promote Memory to Register
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static const char PassName[]
Class for arbitrary precision integers.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
ConstantFP - Floating Point Values [float, double].
Representation of each machine instruction.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Represents a value which can be a Register or a constant.
RegOrConstant(Register Reg)
RegOrConstant(int64_t Cst)
Wrapper class representing virtual and physical registers.
This is an optimization pass for GlobalISel generic memory operations.
Register getFunctionLiveInPhysReg(MachineFunction &MF, const TargetInstrInfo &TII, MCRegister PhysReg, const TargetRegisterClass &RC, const DebugLoc &DL, LLT RegTy=LLT())
Return a virtual register corresponding to the incoming argument register PhysReg.
bool isBuildVectorAllZeros(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowUndef=false)
Return true if the specified instruction is a G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC where all of the...
Register constrainOperandRegClass(const MachineFunction &MF, const TargetRegisterInfo &TRI, MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, MachineInstr &InsertPt, const TargetRegisterClass &RegClass, MachineOperand &RegMO)
Constrain the Register operand OpIdx, so that it is now constrained to the TargetRegisterClass passed...
MachineInstr * getOpcodeDef(unsigned Opcode, Register Reg, const MachineRegisterInfo &MRI)
See if Reg is defined by an single def instruction that is Opcode.
const ConstantFP * getConstantFPVRegVal(Register VReg, const MachineRegisterInfo &MRI)
std::optional< APInt > getIConstantVRegVal(Register VReg, const MachineRegisterInfo &MRI)
If VReg is defined by a G_CONSTANT, return the corresponding value.
std::optional< APFloat > ConstantFoldIntToFloat(unsigned Opcode, LLT DstTy, Register Src, const MachineRegisterInfo &MRI)
std::optional< APInt > getIConstantSplatVal(const Register Reg, const MachineRegisterInfo &MRI)
bool isAllOnesOrAllOnesSplat(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowUndefs=false)
Return true if the value is a constant -1 integer or a splatted vector of a constant -1 integer (with...
std::optional< APFloat > ConstantFoldFPBinOp(unsigned Opcode, const Register Op1, const Register Op2, const MachineRegisterInfo &MRI)
void salvageDebugInfo(const MachineRegisterInfo &MRI, MachineInstr &MI)
Assuming the instruction MI is going to be deleted, attempt to salvage debug users of MI by writing t...
bool constrainSelectedInstRegOperands(MachineInstr &I, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI)
Mutate the newly-selected instruction I to constrain its (possibly generic) virtual register operands...
std::optional< APInt > ConstantFoldExtOp(unsigned Opcode, const Register Op1, uint64_t Imm, const MachineRegisterInfo &MRI)
std::optional< RegOrConstant > getVectorSplat(const MachineInstr &MI, const MachineRegisterInfo &MRI)
bool isKnownToBeAPowerOfTwo(const Value *V, const DataLayout &DL, bool OrZero=false, unsigned Depth=0, AssumptionCache *AC=nullptr, const Instruction *CxtI=nullptr, const DominatorTree *DT=nullptr, bool UseInstrInfo=true)
Return true if the given value is known to have exactly one bit set when defined.
std::optional< APInt > isConstantOrConstantSplatVector(MachineInstr &MI, const MachineRegisterInfo &MRI)
Determines if MI defines a constant integer or a splat vector of constant integers.
bool isNullOrNullSplat(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowUndefs=false)
Return true if the value is a constant 0 integer or a splatted vector of a constant 0 integer (with n...
MachineInstr * getDefIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI)
Find the def instruction for Reg, folding away any trivial copies.
bool matchUnaryPredicate(const MachineRegisterInfo &MRI, Register Reg, std::function< bool(const Constant *ConstVal)> Match, bool AllowUndefs=false)
Attempt to match a unary predicate against a scalar/splat constant or every element of a constant G_B...
bool isConstTrueVal(const TargetLowering &TLI, int64_t Val, bool IsVector, bool IsFP)
Returns true if given the TargetLowering's boolean contents information, the value Val contains a tru...
bool isKnownNeverNaN(const Value *V, const DataLayout &DL, const TargetLibraryInfo *TLI, unsigned Depth=0, AssumptionCache *AC=nullptr, const Instruction *CtxI=nullptr, const DominatorTree *DT=nullptr, bool UseInstrInfo=true)
Return true if the floating-point scalar value is not a NaN or if the floating-point vector value has...
LLVM_READNONE LLT getLCMType(LLT OrigTy, LLT TargetTy)
Return the least common multiple type of OrigTy and TargetTy, by changing the number of vector elemen...
std::optional< int64_t > getIConstantVRegSExtVal(Register VReg, const MachineRegisterInfo &MRI)
If VReg is defined by a G_CONSTANT fits in int64_t returns it.
std::optional< APInt > ConstantFoldBinOp(unsigned Opcode, const Register Op1, const Register Op2, const MachineRegisterInfo &MRI)
bool shouldOptForSize(const MachineBasicBlock &MBB, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI)
Returns true if the given block should be optimized for size.
bool isConstantOrConstantVector(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowFP=true, bool AllowOpaqueConstants=true)
Return true if the specified instruction is known to be a constant, or a vector of constants.
bool canReplaceReg(Register DstReg, Register SrcReg, MachineRegisterInfo &MRI)
Check if DstReg can be replaced with SrcReg depending on the register constraints.
void saveUsesAndErase(MachineInstr &MI, MachineRegisterInfo &MRI, LostDebugLocObserver *LocObserver, SmallInstListTy &DeadInstChain)
void reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC, MachineOptimizationRemarkEmitter &MORE, MachineOptimizationRemarkMissed &R)
Report an ISel error as a missed optimization remark to the LLVMContext's diagnostic stream.
std::optional< ValueAndVReg > getAnyConstantVRegValWithLookThrough(Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs=true, bool LookThroughAnyExt=false)
If VReg is defined by a statically evaluable chain of instructions rooted on a G_CONSTANT or G_FCONST...
bool isBuildVectorAllOnes(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowUndef=false)
Return true if the specified instruction is a G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC where all of the...
SmallVector< APInt > ConstantFoldVectorBinop(unsigned Opcode, const Register Op1, const Register Op2, const MachineRegisterInfo &MRI)
Tries to constant fold a vector binop with sources Op1 and Op2.
std::optional< FPValueAndVReg > getFConstantSplat(Register VReg, const MachineRegisterInfo &MRI, bool AllowUndef=true)
Returns a floating point scalar constant of a build vector splat if it exists.
void getSelectionDAGFallbackAnalysisUsage(AnalysisUsage &AU)
Modify analysis usage so it preserves passes required for the SelectionDAG fallback.
LLVM_READNONE LLT getCoverTy(LLT OrigTy, LLT TargetTy)
Return smallest type that covers both OrigTy and TargetTy and is multiple of TargetTy.
std::optional< FPValueAndVReg > getFConstantVRegValWithLookThrough(Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs=true)
If VReg is defined by a statically evaluable chain of instructions rooted on a G_FCONSTANT returns it...
bool isConstFalseVal(const TargetLowering &TLI, int64_t Val, bool IsVector, bool IsFP)
APFloat getAPFloatFromSize(double Val, unsigned Size)
Returns an APFloat from Val converted to the appropriate size.
bool isBuildVectorConstantSplat(const Register Reg, const MachineRegisterInfo &MRI, int64_t SplatValue, bool AllowUndef)
Return true if the specified register is defined by G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC where all ...
void eraseInstr(MachineInstr &MI, MachineRegisterInfo &MRI, LostDebugLocObserver *LocObserver=nullptr)
Register constrainRegToClass(MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, Register Reg, const TargetRegisterClass &RegClass)
Try to constrain Reg to the specified register class.
int64_t getICmpTrueVal(const TargetLowering &TLI, bool IsVector, bool IsFP)
Returns an integer representing true, as defined by the TargetBooleanContents.
std::optional< ValueAndVReg > getIConstantVRegValWithLookThrough(Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs=true)
If VReg is defined by a statically evaluable chain of instructions rooted on a G_CONSTANT returns its...
bool isKnownNeverSNaN(Register Val, const MachineRegisterInfo &MRI)
Returns true if Val can be assumed to never be a signaling NaN.
std::optional< DefinitionAndSourceRegister > getDefSrcRegIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI)
Find the def instruction for Reg, and underlying value Register folding away any copies.
void eraseInstrs(ArrayRef< MachineInstr * > DeadInstrs, MachineRegisterInfo &MRI, LostDebugLocObserver *LocObserver=nullptr)
Register getSrcRegIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI)
Find the source register for Reg, folding away any trivial copies.
LLVM_READNONE LLT getGCDType(LLT OrigTy, LLT TargetTy)
Return a type where the total size is the greatest common divisor of OrigTy and TargetTy.
std::optional< int64_t > getIConstantSplatSExtVal(const Register Reg, const MachineRegisterInfo &MRI)
std::optional< SmallVector< unsigned > > ConstantFoldCTLZ(Register Src, const MachineRegisterInfo &MRI)
Tries to constant fold a G_CTLZ operation on Src.
int getSplatIndex(ArrayRef< int > Mask)
If all non-negative Mask elements are the same value, return that value.
bool isTriviallyDead(const MachineInstr &MI, const MachineRegisterInfo &MRI)
Check whether an instruction MI is dead: it only defines dead virtual registers, and doesn't have oth...
Align inferAlignFromPtrInfo(MachineFunction &MF, const MachinePointerInfo &MPO)
void reportGISelWarning(MachineFunction &MF, const TargetPassConfig &TPC, MachineOptimizationRemarkEmitter &MORE, MachineOptimizationRemarkMissed &R)
Report an ISel warning as a missed optimization remark to the LLVMContext's diagnostic stream.
Simple struct used to hold a Register value and the instruction which defines it.
Simple struct used to hold a constant integer value and a virtual register.