LLVM 17.0.0git
MachineIRBuilder.h
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1//===-- llvm/CodeGen/GlobalISel/MachineIRBuilder.h - MIBuilder --*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8/// \file
9/// This file declares the MachineIRBuilder class.
10/// This is a helper class to build MachineInstr.
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_CODEGEN_GLOBALISEL_MACHINEIRBUILDER_H
14#define LLVM_CODEGEN_GLOBALISEL_MACHINEIRBUILDER_H
15
21#include "llvm/IR/DebugLoc.h"
22#include "llvm/IR/Module.h"
23
24namespace llvm {
25
26// Forward declarations.
27class APInt;
28class BlockAddress;
29class Constant;
30class ConstantFP;
31class ConstantInt;
32class DataLayout;
33class GISelCSEInfo;
34class GlobalValue;
35class TargetRegisterClass;
36class MachineFunction;
37class MachineInstr;
38class TargetInstrInfo;
39class GISelChangeObserver;
40
41/// Class which stores all the state required in a MachineIRBuilder.
42/// Since MachineIRBuilders will only store state in this object, it allows
43/// to transfer BuilderState between different kinds of MachineIRBuilders.
45 /// MachineFunction under construction.
46 MachineFunction *MF = nullptr;
47 /// Information used to access the description of the opcodes.
48 const TargetInstrInfo *TII = nullptr;
49 /// Information used to verify types are consistent and to create virtual registers.
51 /// Debug location to be set to any instruction we create.
53 /// PC sections metadata to be set to any instruction we create.
54 MDNode *PCSections = nullptr;
55
56 /// \name Fields describing the insertion point.
57 /// @{
60 /// @}
61
63
65};
66
67class DstOp {
68 union {
72 };
73
74public:
75 enum class DstType { Ty_LLT, Ty_Reg, Ty_RC };
76 DstOp(unsigned R) : Reg(R), Ty(DstType::Ty_Reg) {}
77 DstOp(Register R) : Reg(R), Ty(DstType::Ty_Reg) {}
78 DstOp(const MachineOperand &Op) : Reg(Op.getReg()), Ty(DstType::Ty_Reg) {}
79 DstOp(const LLT T) : LLTTy(T), Ty(DstType::Ty_LLT) {}
80 DstOp(const TargetRegisterClass *TRC) : RC(TRC), Ty(DstType::Ty_RC) {}
81
83 switch (Ty) {
84 case DstType::Ty_Reg:
85 MIB.addDef(Reg);
86 break;
87 case DstType::Ty_LLT:
88 MIB.addDef(MRI.createGenericVirtualRegister(LLTTy));
89 break;
90 case DstType::Ty_RC:
91 MIB.addDef(MRI.createVirtualRegister(RC));
92 break;
93 }
94 }
95
97 switch (Ty) {
98 case DstType::Ty_RC:
99 return LLT{};
100 case DstType::Ty_LLT:
101 return LLTTy;
102 case DstType::Ty_Reg:
103 return MRI.getType(Reg);
104 }
105 llvm_unreachable("Unrecognised DstOp::DstType enum");
106 }
107
108 Register getReg() const {
109 assert(Ty == DstType::Ty_Reg && "Not a register");
110 return Reg;
111 }
112
114 switch (Ty) {
115 case DstType::Ty_RC:
116 return RC;
117 default:
118 llvm_unreachable("Not a RC Operand");
119 }
120 }
121
122 DstType getDstOpKind() const { return Ty; }
123
124private:
125 DstType Ty;
126};
127
128class SrcOp {
129 union {
133 int64_t Imm;
134 };
135
136public:
138 SrcOp(Register R) : Reg(R), Ty(SrcType::Ty_Reg) {}
139 SrcOp(const MachineOperand &Op) : Reg(Op.getReg()), Ty(SrcType::Ty_Reg) {}
140 SrcOp(const MachineInstrBuilder &MIB) : SrcMIB(MIB), Ty(SrcType::Ty_MIB) {}
142 /// Use of registers held in unsigned integer variables (or more rarely signed
143 /// integers) is no longer permitted to avoid ambiguity with upcoming support
144 /// for immediates.
145 SrcOp(unsigned) = delete;
146 SrcOp(int) = delete;
147 SrcOp(uint64_t V) : Imm(V), Ty(SrcType::Ty_Imm) {}
148 SrcOp(int64_t V) : Imm(V), Ty(SrcType::Ty_Imm) {}
149
151 switch (Ty) {
153 MIB.addPredicate(Pred);
154 break;
155 case SrcType::Ty_Reg:
156 MIB.addUse(Reg);
157 break;
158 case SrcType::Ty_MIB:
159 MIB.addUse(SrcMIB->getOperand(0).getReg());
160 break;
161 case SrcType::Ty_Imm:
162 MIB.addImm(Imm);
163 break;
164 }
165 }
166
168 switch (Ty) {
170 case SrcType::Ty_Imm:
171 llvm_unreachable("Not a register operand");
172 case SrcType::Ty_Reg:
173 return MRI.getType(Reg);
174 case SrcType::Ty_MIB:
175 return MRI.getType(SrcMIB->getOperand(0).getReg());
176 }
177 llvm_unreachable("Unrecognised SrcOp::SrcType enum");
178 }
179
180 Register getReg() const {
181 switch (Ty) {
183 case SrcType::Ty_Imm:
184 llvm_unreachable("Not a register operand");
185 case SrcType::Ty_Reg:
186 return Reg;
187 case SrcType::Ty_MIB:
188 return SrcMIB->getOperand(0).getReg();
189 }
190 llvm_unreachable("Unrecognised SrcOp::SrcType enum");
191 }
192
194 switch (Ty) {
196 return Pred;
197 default:
198 llvm_unreachable("Not a register operand");
199 }
200 }
201
202 int64_t getImm() const {
203 switch (Ty) {
204 case SrcType::Ty_Imm:
205 return Imm;
206 default:
207 llvm_unreachable("Not an immediate");
208 }
209 }
210
211 SrcType getSrcOpKind() const { return Ty; }
212
213private:
214 SrcType Ty;
215};
216
217/// Helper class to build MachineInstr.
218/// It keeps internally the insertion point and debug location for all
219/// the new instructions we want to create.
220/// This information can be modified via the related setters.
222
224
225 unsigned getOpcodeForMerge(const DstOp &DstOp, ArrayRef<SrcOp> SrcOps) const;
226
227protected:
228 void validateTruncExt(const LLT Dst, const LLT Src, bool IsExtend);
229
230 void validateUnaryOp(const LLT Res, const LLT Op0);
231 void validateBinaryOp(const LLT Res, const LLT Op0, const LLT Op1);
232 void validateShiftOp(const LLT Res, const LLT Op0, const LLT Op1);
233
234 void validateSelectOp(const LLT ResTy, const LLT TstTy, const LLT Op0Ty,
235 const LLT Op1Ty);
236
237 void recordInsertion(MachineInstr *InsertedInstr) const {
238 if (State.Observer)
239 State.Observer->createdInstr(*InsertedInstr);
240 }
241
242public:
243 /// Some constructors for easy use.
244 MachineIRBuilder() = default;
246
248 setMF(*MBB.getParent());
249 setInsertPt(MBB, InsPt);
250 }
251
253 MachineIRBuilder(*MI.getParent(), MI.getIterator()) {
254 setInstr(MI);
255 setDebugLoc(MI.getDebugLoc());
256 }
257
260 setChangeObserver(Observer);
261 }
262
263 virtual ~MachineIRBuilder() = default;
264
265 MachineIRBuilder(const MachineIRBuilderState &BState) : State(BState) {}
266
268 assert(State.TII && "TargetInstrInfo is not set");
269 return *State.TII;
270 }
271
272 /// Getter for the function we currently build.
274 assert(State.MF && "MachineFunction is not set");
275 return *State.MF;
276 }
277
278 const MachineFunction &getMF() const {
279 assert(State.MF && "MachineFunction is not set");
280 return *State.MF;
281 }
282
283 const DataLayout &getDataLayout() const {
285 }
286
288 return getMF().getFunction().getContext();
289 }
290
291 /// Getter for DebugLoc
292 const DebugLoc &getDL() { return State.DL; }
293
294 /// Getter for MRI
295 MachineRegisterInfo *getMRI() { return State.MRI; }
296 const MachineRegisterInfo *getMRI() const { return State.MRI; }
297
298 /// Getter for the State
299 MachineIRBuilderState &getState() { return State; }
300
301 /// Getter for the basic block we currently build.
302 const MachineBasicBlock &getMBB() const {
303 assert(State.MBB && "MachineBasicBlock is not set");
304 return *State.MBB;
305 }
306
308 return const_cast<MachineBasicBlock &>(
309 const_cast<const MachineIRBuilder *>(this)->getMBB());
310 }
311
312 GISelCSEInfo *getCSEInfo() { return State.CSEInfo; }
313 const GISelCSEInfo *getCSEInfo() const { return State.CSEInfo; }
314
315 /// Current insertion point for new instructions.
317
318 /// Set the insertion point before the specified position.
319 /// \pre MBB must be in getMF().
320 /// \pre II must be a valid iterator in MBB.
322 assert(MBB.getParent() == &getMF() &&
323 "Basic block is in a different function");
324 State.MBB = &MBB;
325 State.II = II;
326 }
327
328 /// @}
329
331
332 /// \name Setters for the insertion point.
333 /// @{
334 /// Set the MachineFunction where to build instructions.
335 void setMF(MachineFunction &MF);
336
337 /// Set the insertion point to the end of \p MBB.
338 /// \pre \p MBB must be contained by getMF().
340 State.MBB = &MBB;
341 State.II = MBB.end();
342 assert(&getMF() == MBB.getParent() &&
343 "Basic block is in a different function");
344 }
345
346 /// Set the insertion point to before MI.
347 /// \pre MI must be in getMF().
349 assert(MI.getParent() && "Instruction is not part of a basic block");
350 setMBB(*MI.getParent());
351 State.II = MI.getIterator();
352 setPCSections(MI.getPCSections());
353 }
354 /// @}
355
356 /// Set the insertion point to before MI, and set the debug loc to MI's loc.
357 /// \pre MI must be in getMF().
359 setInstr(MI);
360 setDebugLoc(MI.getDebugLoc());
361 }
362
364 State.Observer = &Observer;
365 }
366
367 void stopObservingChanges() { State.Observer = nullptr; }
368 /// @}
369
370 /// Set the debug location to \p DL for all the next build instructions.
371 void setDebugLoc(const DebugLoc &DL) { this->State.DL = DL; }
372
373 /// Get the current instruction's debug location.
374 const DebugLoc &getDebugLoc() { return State.DL; }
375
376 /// Set the PC sections metadata to \p MD for all the next build instructions.
377 void setPCSections(MDNode *MD) { State.PCSections = MD; }
378
379 /// Get the current instruction's PC sections metadata.
380 MDNode *getPCSections() { return State.PCSections; }
381
382 /// Build and insert <empty> = \p Opcode <empty>.
383 /// The insertion point is the one set by the last call of either
384 /// setBasicBlock or setMI.
385 ///
386 /// \pre setBasicBlock or setMI must have been called.
387 ///
388 /// \return a MachineInstrBuilder for the newly created instruction.
390 return insertInstr(buildInstrNoInsert(Opcode));
391 }
392
393 /// Build but don't insert <empty> = \p Opcode <empty>.
394 ///
395 /// \pre setMF, setBasicBlock or setMI must have been called.
396 ///
397 /// \return a MachineInstrBuilder for the newly created instruction.
399
400 /// Insert an existing instruction at the insertion point.
402
403 /// Build and insert a DBG_VALUE instruction expressing the fact that the
404 /// associated \p Variable lives in \p Reg (suitably modified by \p Expr).
406 const MDNode *Expr);
407
408 /// Build and insert a DBG_VALUE instruction expressing the fact that the
409 /// associated \p Variable lives in memory at \p Reg (suitably modified by \p
410 /// Expr).
412 const MDNode *Variable,
413 const MDNode *Expr);
414
415 /// Build and insert a DBG_VALUE instruction expressing the fact that the
416 /// associated \p Variable lives in the stack slot specified by \p FI
417 /// (suitably modified by \p Expr).
418 MachineInstrBuilder buildFIDbgValue(int FI, const MDNode *Variable,
419 const MDNode *Expr);
420
421 /// Build and insert a DBG_VALUE instructions specifying that \p Variable is
422 /// given by \p C (suitably modified by \p Expr).
424 const MDNode *Variable,
425 const MDNode *Expr);
426
427 /// Build and insert a DBG_LABEL instructions specifying that \p Label is
428 /// given. Convert "llvm.dbg.label Label" to "DBG_LABEL Label".
430
431 /// Build and insert \p Res = G_DYN_STACKALLOC \p Size, \p Align
432 ///
433 /// G_DYN_STACKALLOC does a dynamic stack allocation and writes the address of
434 /// the allocated memory into \p Res.
435 /// \pre setBasicBlock or setMI must have been called.
436 /// \pre \p Res must be a generic virtual register with pointer type.
437 ///
438 /// \return a MachineInstrBuilder for the newly created instruction.
440 Align Alignment);
441
442 /// Build and insert \p Res = G_FRAME_INDEX \p Idx
443 ///
444 /// G_FRAME_INDEX materializes the address of an alloca value or other
445 /// stack-based object.
446 ///
447 /// \pre setBasicBlock or setMI must have been called.
448 /// \pre \p Res must be a generic virtual register with pointer type.
449 ///
450 /// \return a MachineInstrBuilder for the newly created instruction.
452
453 /// Build and insert \p Res = G_GLOBAL_VALUE \p GV
454 ///
455 /// G_GLOBAL_VALUE materializes the address of the specified global
456 /// into \p Res.
457 ///
458 /// \pre setBasicBlock or setMI must have been called.
459 /// \pre \p Res must be a generic virtual register with pointer type
460 /// in the same address space as \p GV.
461 ///
462 /// \return a MachineInstrBuilder for the newly created instruction.
464
465 /// Build and insert \p Res = G_CONSTANT_POOL \p Idx
466 ///
467 /// G_CONSTANT_POOL materializes the address of an object in the constant
468 /// pool.
469 ///
470 /// \pre setBasicBlock or setMI must have been called.
471 /// \pre \p Res must be a generic virtual register with pointer type.
472 ///
473 /// \return a MachineInstrBuilder for the newly created instruction.
474 MachineInstrBuilder buildConstantPool(const DstOp &Res, unsigned Idx);
475
476 /// Build and insert \p Res = G_PTR_ADD \p Op0, \p Op1
477 ///
478 /// G_PTR_ADD adds \p Op1 addressible units to the pointer specified by \p Op0,
479 /// storing the resulting pointer in \p Res. Addressible units are typically
480 /// bytes but this can vary between targets.
481 ///
482 /// \pre setBasicBlock or setMI must have been called.
483 /// \pre \p Res and \p Op0 must be generic virtual registers with pointer
484 /// type.
485 /// \pre \p Op1 must be a generic virtual register with scalar type.
486 ///
487 /// \return a MachineInstrBuilder for the newly created instruction.
488 MachineInstrBuilder buildPtrAdd(const DstOp &Res, const SrcOp &Op0,
489 const SrcOp &Op1);
490
491 /// Materialize and insert \p Res = G_PTR_ADD \p Op0, (G_CONSTANT \p Value)
492 ///
493 /// G_PTR_ADD adds \p Value bytes to the pointer specified by \p Op0,
494 /// storing the resulting pointer in \p Res. If \p Value is zero then no
495 /// G_PTR_ADD or G_CONSTANT will be created and \pre Op0 will be assigned to
496 /// \p Res.
497 ///
498 /// \pre setBasicBlock or setMI must have been called.
499 /// \pre \p Op0 must be a generic virtual register with pointer type.
500 /// \pre \p ValueTy must be a scalar type.
501 /// \pre \p Res must be 0. This is to detect confusion between
502 /// materializePtrAdd() and buildPtrAdd().
503 /// \post \p Res will either be a new generic virtual register of the same
504 /// type as \p Op0 or \p Op0 itself.
505 ///
506 /// \return a MachineInstrBuilder for the newly created instruction.
507 std::optional<MachineInstrBuilder> materializePtrAdd(Register &Res,
508 Register Op0,
509 const LLT ValueTy,
511
512 /// Build and insert \p Res = G_PTRMASK \p Op0, \p Op1
514 const SrcOp &Op1) {
515 return buildInstr(TargetOpcode::G_PTRMASK, {Res}, {Op0, Op1});
516 }
517
518 /// Build and insert \p Res = G_PTRMASK \p Op0, \p G_CONSTANT (1 << NumBits) - 1
519 ///
520 /// This clears the low bits of a pointer operand without destroying its
521 /// pointer properties. This has the effect of rounding the address *down* to
522 /// a specified alignment in bits.
523 ///
524 /// \pre setBasicBlock or setMI must have been called.
525 /// \pre \p Res and \p Op0 must be generic virtual registers with pointer
526 /// type.
527 /// \pre \p NumBits must be an integer representing the number of low bits to
528 /// be cleared in \p Op0.
529 ///
530 /// \return a MachineInstrBuilder for the newly created instruction.
531 MachineInstrBuilder buildMaskLowPtrBits(const DstOp &Res, const SrcOp &Op0,
532 uint32_t NumBits);
533
534 /// Build and insert
535 /// a, b, ..., x = G_UNMERGE_VALUES \p Op0
536 /// \p Res = G_BUILD_VECTOR a, b, ..., x, undef, ..., undef
537 ///
538 /// Pad \p Op0 with undef elements to match number of elements in \p Res.
539 ///
540 /// \pre setBasicBlock or setMI must have been called.
541 /// \pre \p Res and \p Op0 must be generic virtual registers with vector type,
542 /// same vector element type and Op0 must have fewer elements then Res.
543 ///
544 /// \return a MachineInstrBuilder for the newly created build vector instr.
546 const SrcOp &Op0);
547
548 /// Build and insert
549 /// a, b, ..., x, y, z = G_UNMERGE_VALUES \p Op0
550 /// \p Res = G_BUILD_VECTOR a, b, ..., x
551 ///
552 /// Delete trailing elements in \p Op0 to match number of elements in \p Res.
553 ///
554 /// \pre setBasicBlock or setMI must have been called.
555 /// \pre \p Res and \p Op0 must be generic virtual registers with vector type,
556 /// same vector element type and Op0 must have more elements then Res.
557 ///
558 /// \return a MachineInstrBuilder for the newly created build vector instr.
560 const SrcOp &Op0);
561
562 /// Build and insert \p Res, \p CarryOut = G_UADDO \p Op0, \p Op1
563 ///
564 /// G_UADDO sets \p Res to \p Op0 + \p Op1 (truncated to the bit width) and
565 /// sets \p CarryOut to 1 if the result overflowed in unsigned arithmetic.
566 ///
567 /// \pre setBasicBlock or setMI must have been called.
568 /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers with the
569 /// same scalar type.
570 ////\pre \p CarryOut must be generic virtual register with scalar type
571 ///(typically s1)
572 ///
573 /// \return The newly created instruction.
574 MachineInstrBuilder buildUAddo(const DstOp &Res, const DstOp &CarryOut,
575 const SrcOp &Op0, const SrcOp &Op1) {
576 return buildInstr(TargetOpcode::G_UADDO, {Res, CarryOut}, {Op0, Op1});
577 }
578
579 /// Build and insert \p Res, \p CarryOut = G_USUBO \p Op0, \p Op1
580 MachineInstrBuilder buildUSubo(const DstOp &Res, const DstOp &CarryOut,
581 const SrcOp &Op0, const SrcOp &Op1) {
582 return buildInstr(TargetOpcode::G_USUBO, {Res, CarryOut}, {Op0, Op1});
583 }
584
585 /// Build and insert \p Res, \p CarryOut = G_SADDO \p Op0, \p Op1
586 MachineInstrBuilder buildSAddo(const DstOp &Res, const DstOp &CarryOut,
587 const SrcOp &Op0, const SrcOp &Op1) {
588 return buildInstr(TargetOpcode::G_SADDO, {Res, CarryOut}, {Op0, Op1});
589 }
590
591 /// Build and insert \p Res, \p CarryOut = G_SUBO \p Op0, \p Op1
592 MachineInstrBuilder buildSSubo(const DstOp &Res, const DstOp &CarryOut,
593 const SrcOp &Op0, const SrcOp &Op1) {
594 return buildInstr(TargetOpcode::G_SSUBO, {Res, CarryOut}, {Op0, Op1});
595 }
596
597 /// Build and insert \p Res, \p CarryOut = G_UADDE \p Op0,
598 /// \p Op1, \p CarryIn
599 ///
600 /// G_UADDE sets \p Res to \p Op0 + \p Op1 + \p CarryIn (truncated to the bit
601 /// width) and sets \p CarryOut to 1 if the result overflowed in unsigned
602 /// arithmetic.
603 ///
604 /// \pre setBasicBlock or setMI must have been called.
605 /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
606 /// with the same scalar type.
607 /// \pre \p CarryOut and \p CarryIn must be generic virtual
608 /// registers with the same scalar type (typically s1)
609 ///
610 /// \return The newly created instruction.
611 MachineInstrBuilder buildUAdde(const DstOp &Res, const DstOp &CarryOut,
612 const SrcOp &Op0, const SrcOp &Op1,
613 const SrcOp &CarryIn) {
614 return buildInstr(TargetOpcode::G_UADDE, {Res, CarryOut},
615 {Op0, Op1, CarryIn});
616 }
617
618 /// Build and insert \p Res, \p CarryOut = G_USUBE \p Op0, \p Op1, \p CarryInp
619 MachineInstrBuilder buildUSube(const DstOp &Res, const DstOp &CarryOut,
620 const SrcOp &Op0, const SrcOp &Op1,
621 const SrcOp &CarryIn) {
622 return buildInstr(TargetOpcode::G_USUBE, {Res, CarryOut},
623 {Op0, Op1, CarryIn});
624 }
625
626 /// Build and insert \p Res, \p CarryOut = G_SADDE \p Op0, \p Op1, \p CarryInp
627 MachineInstrBuilder buildSAdde(const DstOp &Res, const DstOp &CarryOut,
628 const SrcOp &Op0, const SrcOp &Op1,
629 const SrcOp &CarryIn) {
630 return buildInstr(TargetOpcode::G_SADDE, {Res, CarryOut},
631 {Op0, Op1, CarryIn});
632 }
633
634 /// Build and insert \p Res, \p CarryOut = G_SSUBE \p Op0, \p Op1, \p CarryInp
635 MachineInstrBuilder buildSSube(const DstOp &Res, const DstOp &CarryOut,
636 const SrcOp &Op0, const SrcOp &Op1,
637 const SrcOp &CarryIn) {
638 return buildInstr(TargetOpcode::G_SSUBE, {Res, CarryOut},
639 {Op0, Op1, CarryIn});
640 }
641
642 /// Build and insert \p Res = G_ANYEXT \p Op0
643 ///
644 /// G_ANYEXT produces a register of the specified width, with bits 0 to
645 /// sizeof(\p Ty) * 8 set to \p Op. The remaining bits are unspecified
646 /// (i.e. this is neither zero nor sign-extension). For a vector register,
647 /// each element is extended individually.
648 ///
649 /// \pre setBasicBlock or setMI must have been called.
650 /// \pre \p Res must be a generic virtual register with scalar or vector type.
651 /// \pre \p Op must be a generic virtual register with scalar or vector type.
652 /// \pre \p Op must be smaller than \p Res
653 ///
654 /// \return The newly created instruction.
655
656 MachineInstrBuilder buildAnyExt(const DstOp &Res, const SrcOp &Op);
657
658 /// Build and insert \p Res = G_SEXT \p Op
659 ///
660 /// G_SEXT produces a register of the specified width, with bits 0 to
661 /// sizeof(\p Ty) * 8 set to \p Op. The remaining bits are duplicated from the
662 /// high bit of \p Op (i.e. 2s-complement sign extended).
663 ///
664 /// \pre setBasicBlock or setMI must have been called.
665 /// \pre \p Res must be a generic virtual register with scalar or vector type.
666 /// \pre \p Op must be a generic virtual register with scalar or vector type.
667 /// \pre \p Op must be smaller than \p Res
668 ///
669 /// \return The newly created instruction.
670 MachineInstrBuilder buildSExt(const DstOp &Res, const SrcOp &Op);
671
672 /// Build and insert \p Res = G_SEXT_INREG \p Op, ImmOp
673 MachineInstrBuilder buildSExtInReg(const DstOp &Res, const SrcOp &Op, int64_t ImmOp) {
674 return buildInstr(TargetOpcode::G_SEXT_INREG, {Res}, {Op, SrcOp(ImmOp)});
675 }
676
677 /// Build and insert \p Res = G_FPEXT \p Op
679 std::optional<unsigned> Flags = std::nullopt) {
680 return buildInstr(TargetOpcode::G_FPEXT, {Res}, {Op}, Flags);
681 }
682
683 /// Build and insert a G_PTRTOINT instruction.
685 return buildInstr(TargetOpcode::G_PTRTOINT, {Dst}, {Src});
686 }
687
688 /// Build and insert a G_INTTOPTR instruction.
690 return buildInstr(TargetOpcode::G_INTTOPTR, {Dst}, {Src});
691 }
692
693 /// Build and insert \p Dst = G_BITCAST \p Src
694 MachineInstrBuilder buildBitcast(const DstOp &Dst, const SrcOp &Src) {
695 return buildInstr(TargetOpcode::G_BITCAST, {Dst}, {Src});
696 }
697
698 /// Build and insert \p Dst = G_ADDRSPACE_CAST \p Src
700 return buildInstr(TargetOpcode::G_ADDRSPACE_CAST, {Dst}, {Src});
701 }
702
703 /// \return The opcode of the extension the target wants to use for boolean
704 /// values.
705 unsigned getBoolExtOp(bool IsVec, bool IsFP) const;
706
707 // Build and insert \p Res = G_ANYEXT \p Op, \p Res = G_SEXT \p Op, or \p Res
708 // = G_ZEXT \p Op depending on how the target wants to extend boolean values.
709 MachineInstrBuilder buildBoolExt(const DstOp &Res, const SrcOp &Op,
710 bool IsFP);
711
712 // Build and insert \p Res = G_SEXT_INREG \p Op, 1 or \p Res = G_AND \p Op, 1,
713 // or COPY depending on how the target wants to extend boolean values, using
714 // the original register size.
715 MachineInstrBuilder buildBoolExtInReg(const DstOp &Res, const SrcOp &Op,
716 bool IsVector,
717 bool IsFP);
718
719 /// Build and insert \p Res = G_ZEXT \p Op
720 ///
721 /// G_ZEXT produces a register of the specified width, with bits 0 to
722 /// sizeof(\p Ty) * 8 set to \p Op. The remaining bits are 0. For a vector
723 /// register, each element is extended individually.
724 ///
725 /// \pre setBasicBlock or setMI must have been called.
726 /// \pre \p Res must be a generic virtual register with scalar or vector type.
727 /// \pre \p Op must be a generic virtual register with scalar or vector type.
728 /// \pre \p Op must be smaller than \p Res
729 ///
730 /// \return The newly created instruction.
731 MachineInstrBuilder buildZExt(const DstOp &Res, const SrcOp &Op);
732
733 /// Build and insert \p Res = G_SEXT \p Op, \p Res = G_TRUNC \p Op, or
734 /// \p Res = COPY \p Op depending on the differing sizes of \p Res and \p Op.
735 /// ///
736 /// \pre setBasicBlock or setMI must have been called.
737 /// \pre \p Res must be a generic virtual register with scalar or vector type.
738 /// \pre \p Op must be a generic virtual register with scalar or vector type.
739 ///
740 /// \return The newly created instruction.
741 MachineInstrBuilder buildSExtOrTrunc(const DstOp &Res, const SrcOp &Op);
742
743 /// Build and insert \p Res = G_ZEXT \p Op, \p Res = G_TRUNC \p Op, or
744 /// \p Res = COPY \p Op depending on the differing sizes of \p Res and \p Op.
745 /// ///
746 /// \pre setBasicBlock or setMI must have been called.
747 /// \pre \p Res must be a generic virtual register with scalar or vector type.
748 /// \pre \p Op must be a generic virtual register with scalar or vector type.
749 ///
750 /// \return The newly created instruction.
751 MachineInstrBuilder buildZExtOrTrunc(const DstOp &Res, const SrcOp &Op);
752
753 // Build and insert \p Res = G_ANYEXT \p Op, \p Res = G_TRUNC \p Op, or
754 /// \p Res = COPY \p Op depending on the differing sizes of \p Res and \p Op.
755 /// ///
756 /// \pre setBasicBlock or setMI must have been called.
757 /// \pre \p Res must be a generic virtual register with scalar or vector type.
758 /// \pre \p Op must be a generic virtual register with scalar or vector type.
759 ///
760 /// \return The newly created instruction.
761 MachineInstrBuilder buildAnyExtOrTrunc(const DstOp &Res, const SrcOp &Op);
762
763 /// Build and insert \p Res = \p ExtOpc, \p Res = G_TRUNC \p
764 /// Op, or \p Res = COPY \p Op depending on the differing sizes of \p Res and
765 /// \p Op.
766 /// ///
767 /// \pre setBasicBlock or setMI must have been called.
768 /// \pre \p Res must be a generic virtual register with scalar or vector type.
769 /// \pre \p Op must be a generic virtual register with scalar or vector type.
770 ///
771 /// \return The newly created instruction.
772 MachineInstrBuilder buildExtOrTrunc(unsigned ExtOpc, const DstOp &Res,
773 const SrcOp &Op);
774
775 /// Build and inserts \p Res = \p G_AND \p Op, \p LowBitsSet(ImmOp)
776 /// Since there is no G_ZEXT_INREG like G_SEXT_INREG, the instruction is
777 /// emulated using G_AND.
778 MachineInstrBuilder buildZExtInReg(const DstOp &Res, const SrcOp &Op,
779 int64_t ImmOp);
780
781 /// Build and insert an appropriate cast between two registers of equal size.
782 MachineInstrBuilder buildCast(const DstOp &Dst, const SrcOp &Src);
783
784 /// Build and insert G_BR \p Dest
785 ///
786 /// G_BR is an unconditional branch to \p Dest.
787 ///
788 /// \pre setBasicBlock or setMI must have been called.
789 ///
790 /// \return a MachineInstrBuilder for the newly created instruction.
792
793 /// Build and insert G_BRCOND \p Tst, \p Dest
794 ///
795 /// G_BRCOND is a conditional branch to \p Dest.
796 ///
797 /// \pre setBasicBlock or setMI must have been called.
798 /// \pre \p Tst must be a generic virtual register with scalar
799 /// type. At the beginning of legalization, this will be a single
800 /// bit (s1). Targets with interesting flags registers may change
801 /// this. For a wider type, whether the branch is taken must only
802 /// depend on bit 0 (for now).
803 ///
804 /// \return The newly created instruction.
806
807 /// Build and insert G_BRINDIRECT \p Tgt
808 ///
809 /// G_BRINDIRECT is an indirect branch to \p Tgt.
810 ///
811 /// \pre setBasicBlock or setMI must have been called.
812 /// \pre \p Tgt must be a generic virtual register with pointer type.
813 ///
814 /// \return a MachineInstrBuilder for the newly created instruction.
816
817 /// Build and insert G_BRJT \p TablePtr, \p JTI, \p IndexReg
818 ///
819 /// G_BRJT is a jump table branch using a table base pointer \p TablePtr,
820 /// jump table index \p JTI and index \p IndexReg
821 ///
822 /// \pre setBasicBlock or setMI must have been called.
823 /// \pre \p TablePtr must be a generic virtual register with pointer type.
824 /// \pre \p JTI must be be a jump table index.
825 /// \pre \p IndexReg must be a generic virtual register with pointer type.
826 ///
827 /// \return a MachineInstrBuilder for the newly created instruction.
828 MachineInstrBuilder buildBrJT(Register TablePtr, unsigned JTI,
829 Register IndexReg);
830
831 /// Build and insert \p Res = G_CONSTANT \p Val
832 ///
833 /// G_CONSTANT is an integer constant with the specified size and value. \p
834 /// Val will be extended or truncated to the size of \p Reg.
835 ///
836 /// \pre setBasicBlock or setMI must have been called.
837 /// \pre \p Res must be a generic virtual register with scalar or pointer
838 /// type.
839 ///
840 /// \return The newly created instruction.
841 virtual MachineInstrBuilder buildConstant(const DstOp &Res,
842 const ConstantInt &Val);
843
844 /// Build and insert \p Res = G_CONSTANT \p Val
845 ///
846 /// G_CONSTANT is an integer constant with the specified size and value.
847 ///
848 /// \pre setBasicBlock or setMI must have been called.
849 /// \pre \p Res must be a generic virtual register with scalar type.
850 ///
851 /// \return The newly created instruction.
852 MachineInstrBuilder buildConstant(const DstOp &Res, int64_t Val);
853 MachineInstrBuilder buildConstant(const DstOp &Res, const APInt &Val);
854
855 /// Build and insert \p Res = G_FCONSTANT \p Val
856 ///
857 /// G_FCONSTANT is a floating-point constant with the specified size and
858 /// value.
859 ///
860 /// \pre setBasicBlock or setMI must have been called.
861 /// \pre \p Res must be a generic virtual register with scalar type.
862 ///
863 /// \return The newly created instruction.
864 virtual MachineInstrBuilder buildFConstant(const DstOp &Res,
865 const ConstantFP &Val);
866
867 MachineInstrBuilder buildFConstant(const DstOp &Res, double Val);
868 MachineInstrBuilder buildFConstant(const DstOp &Res, const APFloat &Val);
869
870 /// Build and insert \p Res = COPY Op
871 ///
872 /// Register-to-register COPY sets \p Res to \p Op.
873 ///
874 /// \pre setBasicBlock or setMI must have been called.
875 ///
876 /// \return a MachineInstrBuilder for the newly created instruction.
877 MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op);
878
879
880 /// Build and insert G_ASSERT_SEXT, G_ASSERT_ZEXT, or G_ASSERT_ALIGN
881 ///
882 /// \return a MachineInstrBuilder for the newly created instruction.
884 const SrcOp &Op, unsigned Val) {
885 return buildInstr(Opc, Res, Op).addImm(Val);
886 }
887
888 /// Build and insert \p Res = G_ASSERT_ZEXT Op, Size
889 ///
890 /// \return a MachineInstrBuilder for the newly created instruction.
892 unsigned Size) {
893 return buildAssertInstr(TargetOpcode::G_ASSERT_ZEXT, Res, Op, Size);
894 }
895
896 /// Build and insert \p Res = G_ASSERT_SEXT Op, Size
897 ///
898 /// \return a MachineInstrBuilder for the newly created instruction.
900 unsigned Size) {
901 return buildAssertInstr(TargetOpcode::G_ASSERT_SEXT, Res, Op, Size);
902 }
903
904 /// Build and insert \p Res = G_ASSERT_ALIGN Op, AlignVal
905 ///
906 /// \return a MachineInstrBuilder for the newly created instruction.
908 Align AlignVal) {
909 return buildAssertInstr(TargetOpcode::G_ASSERT_ALIGN, Res, Op,
910 AlignVal.value());
911 }
912
913 /// Build and insert `Res = G_LOAD Addr, MMO`.
914 ///
915 /// Loads the value stored at \p Addr. Puts the result in \p Res.
916 ///
917 /// \pre setBasicBlock or setMI must have been called.
918 /// \pre \p Res must be a generic virtual register.
919 /// \pre \p Addr must be a generic virtual register with pointer type.
920 ///
921 /// \return a MachineInstrBuilder for the newly created instruction.
923 MachineMemOperand &MMO) {
924 return buildLoadInstr(TargetOpcode::G_LOAD, Res, Addr, MMO);
925 }
926
927 /// Build and insert a G_LOAD instruction, while constructing the
928 /// MachineMemOperand.
930 buildLoad(const DstOp &Res, const SrcOp &Addr, MachinePointerInfo PtrInfo,
931 Align Alignment,
933 const AAMDNodes &AAInfo = AAMDNodes());
934
935 /// Build and insert `Res = <opcode> Addr, MMO`.
936 ///
937 /// Loads the value stored at \p Addr. Puts the result in \p Res.
938 ///
939 /// \pre setBasicBlock or setMI must have been called.
940 /// \pre \p Res must be a generic virtual register.
941 /// \pre \p Addr must be a generic virtual register with pointer type.
942 ///
943 /// \return a MachineInstrBuilder for the newly created instruction.
944 MachineInstrBuilder buildLoadInstr(unsigned Opcode, const DstOp &Res,
945 const SrcOp &Addr, MachineMemOperand &MMO);
946
947 /// Helper to create a load from a constant offset given a base address. Load
948 /// the type of \p Dst from \p Offset from the given base address and memory
949 /// operand.
951 const SrcOp &BasePtr,
952 MachineMemOperand &BaseMMO,
953 int64_t Offset);
954
955 /// Build and insert `G_STORE Val, Addr, MMO`.
956 ///
957 /// Stores the value \p Val to \p Addr.
958 ///
959 /// \pre setBasicBlock or setMI must have been called.
960 /// \pre \p Val must be a generic virtual register.
961 /// \pre \p Addr must be a generic virtual register with pointer type.
962 ///
963 /// \return a MachineInstrBuilder for the newly created instruction.
964 MachineInstrBuilder buildStore(const SrcOp &Val, const SrcOp &Addr,
965 MachineMemOperand &MMO);
966
967 /// Build and insert a G_STORE instruction, while constructing the
968 /// MachineMemOperand.
970 buildStore(const SrcOp &Val, const SrcOp &Addr, MachinePointerInfo PtrInfo,
971 Align Alignment,
973 const AAMDNodes &AAInfo = AAMDNodes());
974
975 /// Build and insert `Res0, ... = G_EXTRACT Src, Idx0`.
976 ///
977 /// \pre setBasicBlock or setMI must have been called.
978 /// \pre \p Res and \p Src must be generic virtual registers.
979 ///
980 /// \return a MachineInstrBuilder for the newly created instruction.
981 MachineInstrBuilder buildExtract(const DstOp &Res, const SrcOp &Src, uint64_t Index);
982
983 /// Build and insert \p Res = IMPLICIT_DEF.
985
986 /// Build and insert \p Res = G_MERGE_VALUES \p Op0, ...
987 ///
988 /// G_MERGE_VALUES combines the input elements contiguously into a larger
989 /// register. It should only be used when the destination register is not a
990 /// vector.
991 ///
992 /// \pre setBasicBlock or setMI must have been called.
993 /// \pre The entire register \p Res (and no more) must be covered by the input
994 /// registers.
995 /// \pre The type of all \p Ops registers must be identical.
996 ///
997 /// \return a MachineInstrBuilder for the newly created instruction.
1000
1001 /// Build and insert \p Res = G_MERGE_VALUES \p Op0, ...
1002 /// or \p Res = G_BUILD_VECTOR \p Op0, ...
1003 /// or \p Res = G_CONCAT_VECTORS \p Op0, ...
1004 ///
1005 /// G_MERGE_VALUES combines the input elements contiguously into a larger
1006 /// register. It is used when the destination register is not a vector.
1007 /// G_BUILD_VECTOR combines scalar inputs into a vector register.
1008 /// G_CONCAT_VECTORS combines vector inputs into a vector register.
1009 ///
1010 /// \pre setBasicBlock or setMI must have been called.
1011 /// \pre The entire register \p Res (and no more) must be covered by the input
1012 /// registers.
1013 /// \pre The type of all \p Ops registers must be identical.
1014 ///
1015 /// \return a MachineInstrBuilder for the newly created instruction. The
1016 /// opcode of the new instruction will depend on the types of both
1017 /// the destination and the sources.
1019 ArrayRef<Register> Ops);
1021 std::initializer_list<SrcOp> Ops);
1022
1023 /// Build and insert \p Res0, ... = G_UNMERGE_VALUES \p Op
1024 ///
1025 /// G_UNMERGE_VALUES splits contiguous bits of the input into multiple
1026 ///
1027 /// \pre setBasicBlock or setMI must have been called.
1028 /// \pre The entire register \p Res (and no more) must be covered by the input
1029 /// registers.
1030 /// \pre The type of all \p Res registers must be identical.
1031 ///
1032 /// \return a MachineInstrBuilder for the newly created instruction.
1035
1036 /// Build and insert an unmerge of \p Res sized pieces to cover \p Op
1037 MachineInstrBuilder buildUnmerge(LLT Res, const SrcOp &Op);
1038
1039 /// Build and insert \p Res = G_BUILD_VECTOR \p Op0, ...
1040 ///
1041 /// G_BUILD_VECTOR creates a vector value from multiple scalar registers.
1042 /// \pre setBasicBlock or setMI must have been called.
1043 /// \pre The entire register \p Res (and no more) must be covered by the
1044 /// input scalar registers.
1045 /// \pre The type of all \p Ops registers must be identical.
1046 ///
1047 /// \return a MachineInstrBuilder for the newly created instruction.
1049 ArrayRef<Register> Ops);
1050
1051 /// Build and insert \p Res = G_BUILD_VECTOR \p Op0, ... where each OpN is
1052 /// built with G_CONSTANT.
1054 ArrayRef<APInt> Ops);
1055
1056 /// Build and insert \p Res = G_BUILD_VECTOR with \p Src replicated to fill
1057 /// the number of elements
1059 const SrcOp &Src);
1060
1061 /// Build and insert \p Res = G_BUILD_VECTOR_TRUNC \p Op0, ...
1062 ///
1063 /// G_BUILD_VECTOR_TRUNC creates a vector value from multiple scalar registers
1064 /// which have types larger than the destination vector element type, and
1065 /// truncates the values to fit.
1066 ///
1067 /// If the operands given are already the same size as the vector elt type,
1068 /// then this method will instead create a G_BUILD_VECTOR instruction.
1069 ///
1070 /// \pre setBasicBlock or setMI must have been called.
1071 /// \pre The type of all \p Ops registers must be identical.
1072 ///
1073 /// \return a MachineInstrBuilder for the newly created instruction.
1075 ArrayRef<Register> Ops);
1076
1077 /// Build and insert a vector splat of a scalar \p Src using a
1078 /// G_INSERT_VECTOR_ELT and G_SHUFFLE_VECTOR idiom.
1079 ///
1080 /// \pre setBasicBlock or setMI must have been called.
1081 /// \pre \p Src must have the same type as the element type of \p Dst
1082 ///
1083 /// \return a MachineInstrBuilder for the newly created instruction.
1084 MachineInstrBuilder buildShuffleSplat(const DstOp &Res, const SrcOp &Src);
1085
1086 /// Build and insert \p Res = G_SHUFFLE_VECTOR \p Src1, \p Src2, \p Mask
1087 ///
1088 /// \pre setBasicBlock or setMI must have been called.
1089 ///
1090 /// \return a MachineInstrBuilder for the newly created instruction.
1091 MachineInstrBuilder buildShuffleVector(const DstOp &Res, const SrcOp &Src1,
1092 const SrcOp &Src2, ArrayRef<int> Mask);
1093
1094 /// Build and insert \p Res = G_CONCAT_VECTORS \p Op0, ...
1095 ///
1096 /// G_CONCAT_VECTORS creates a vector from the concatenation of 2 or more
1097 /// vectors.
1098 ///
1099 /// \pre setBasicBlock or setMI must have been called.
1100 /// \pre The entire register \p Res (and no more) must be covered by the input
1101 /// registers.
1102 /// \pre The type of all source operands must be identical.
1103 ///
1104 /// \return a MachineInstrBuilder for the newly created instruction.
1106 ArrayRef<Register> Ops);
1107
1108 MachineInstrBuilder buildInsert(const DstOp &Res, const SrcOp &Src,
1109 const SrcOp &Op, unsigned Index);
1110
1111 /// Build and insert either a G_INTRINSIC (if \p HasSideEffects is false) or
1112 /// G_INTRINSIC_W_SIDE_EFFECTS instruction. Its first operand will be the
1113 /// result register definition unless \p Reg is NoReg (== 0). The second
1114 /// operand will be the intrinsic's ID.
1115 ///
1116 /// Callers are expected to add the required definitions and uses afterwards.
1117 ///
1118 /// \pre setBasicBlock or setMI must have been called.
1119 ///
1120 /// \return a MachineInstrBuilder for the newly created instruction.
1122 bool HasSideEffects);
1124 bool HasSideEffects);
1125
1126 /// Build and insert \p Res = G_FPTRUNC \p Op
1127 ///
1128 /// G_FPTRUNC converts a floating-point value into one with a smaller type.
1129 ///
1130 /// \pre setBasicBlock or setMI must have been called.
1131 /// \pre \p Res must be a generic virtual register with scalar or vector type.
1132 /// \pre \p Op must be a generic virtual register with scalar or vector type.
1133 /// \pre \p Res must be smaller than \p Op
1134 ///
1135 /// \return The newly created instruction.
1137 buildFPTrunc(const DstOp &Res, const SrcOp &Op,
1138 std::optional<unsigned> Flags = std::nullopt);
1139
1140 /// Build and insert \p Res = G_TRUNC \p Op
1141 ///
1142 /// G_TRUNC extracts the low bits of a type. For a vector type each element is
1143 /// truncated independently before being packed into the destination.
1144 ///
1145 /// \pre setBasicBlock or setMI must have been called.
1146 /// \pre \p Res must be a generic virtual register with scalar or vector type.
1147 /// \pre \p Op must be a generic virtual register with scalar or vector type.
1148 /// \pre \p Res must be smaller than \p Op
1149 ///
1150 /// \return The newly created instruction.
1151 MachineInstrBuilder buildTrunc(const DstOp &Res, const SrcOp &Op);
1152
1153 /// Build and insert a \p Res = G_ICMP \p Pred, \p Op0, \p Op1
1154 ///
1155 /// \pre setBasicBlock or setMI must have been called.
1156
1157 /// \pre \p Res must be a generic virtual register with scalar or
1158 /// vector type. Typically this starts as s1 or <N x s1>.
1159 /// \pre \p Op0 and Op1 must be generic virtual registers with the
1160 /// same number of elements as \p Res. If \p Res is a scalar,
1161 /// \p Op0 must be either a scalar or pointer.
1162 /// \pre \p Pred must be an integer predicate.
1163 ///
1164 /// \return a MachineInstrBuilder for the newly created instruction.
1166 const SrcOp &Op0, const SrcOp &Op1);
1167
1168 /// Build and insert a \p Res = G_FCMP \p Pred\p Op0, \p Op1
1169 ///
1170 /// \pre setBasicBlock or setMI must have been called.
1171
1172 /// \pre \p Res must be a generic virtual register with scalar or
1173 /// vector type. Typically this starts as s1 or <N x s1>.
1174 /// \pre \p Op0 and Op1 must be generic virtual registers with the
1175 /// same number of elements as \p Res (or scalar, if \p Res is
1176 /// scalar).
1177 /// \pre \p Pred must be a floating-point predicate.
1178 ///
1179 /// \return a MachineInstrBuilder for the newly created instruction.
1181 const SrcOp &Op0, const SrcOp &Op1,
1182 std::optional<unsigned> Flags = std::nullopt);
1183
1184 /// Build and insert a \p Res = G_SELECT \p Tst, \p Op0, \p Op1
1185 ///
1186 /// \pre setBasicBlock or setMI must have been called.
1187 /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1188 /// with the same type.
1189 /// \pre \p Tst must be a generic virtual register with scalar, pointer or
1190 /// vector type. If vector then it must have the same number of
1191 /// elements as the other parameters.
1192 ///
1193 /// \return a MachineInstrBuilder for the newly created instruction.
1194 MachineInstrBuilder buildSelect(const DstOp &Res, const SrcOp &Tst,
1195 const SrcOp &Op0, const SrcOp &Op1,
1196 std::optional<unsigned> Flags = std::nullopt);
1197
1198 /// Build and insert \p Res = G_INSERT_VECTOR_ELT \p Val,
1199 /// \p Elt, \p Idx
1200 ///
1201 /// \pre setBasicBlock or setMI must have been called.
1202 /// \pre \p Res and \p Val must be a generic virtual register
1203 // with the same vector type.
1204 /// \pre \p Elt and \p Idx must be a generic virtual register
1205 /// with scalar type.
1206 ///
1207 /// \return The newly created instruction.
1209 const SrcOp &Val,
1210 const SrcOp &Elt,
1211 const SrcOp &Idx);
1212
1213 /// Build and insert \p Res = G_EXTRACT_VECTOR_ELT \p Val, \p Idx
1214 ///
1215 /// \pre setBasicBlock or setMI must have been called.
1216 /// \pre \p Res must be a generic virtual register with scalar type.
1217 /// \pre \p Val must be a generic virtual register with vector type.
1218 ///
1219 /// \return The newly created instruction.
1221 const SrcOp &Val,
1222 const int Idx) {
1223 return buildExtractVectorElement(Res, Val,
1225 }
1226
1227 /// Build and insert \p Res = G_EXTRACT_VECTOR_ELT \p Val, \p Idx
1228 ///
1229 /// \pre setBasicBlock or setMI must have been called.
1230 /// \pre \p Res must be a generic virtual register with scalar type.
1231 /// \pre \p Val must be a generic virtual register with vector type.
1232 /// \pre \p Idx must be a generic virtual register with scalar type.
1233 ///
1234 /// \return The newly created instruction.
1236 const SrcOp &Val,
1237 const SrcOp &Idx);
1238
1239 /// Build and insert `OldValRes<def>, SuccessRes<def> =
1240 /// G_ATOMIC_CMPXCHG_WITH_SUCCESS Addr, CmpVal, NewVal, MMO`.
1241 ///
1242 /// Atomically replace the value at \p Addr with \p NewVal if it is currently
1243 /// \p CmpVal otherwise leaves it unchanged. Puts the original value from \p
1244 /// Addr in \p Res, along with an s1 indicating whether it was replaced.
1245 ///
1246 /// \pre setBasicBlock or setMI must have been called.
1247 /// \pre \p OldValRes must be a generic virtual register of scalar type.
1248 /// \pre \p SuccessRes must be a generic virtual register of scalar type. It
1249 /// will be assigned 0 on failure and 1 on success.
1250 /// \pre \p Addr must be a generic virtual register with pointer type.
1251 /// \pre \p OldValRes, \p CmpVal, and \p NewVal must be generic virtual
1252 /// registers of the same type.
1253 ///
1254 /// \return a MachineInstrBuilder for the newly created instruction.
1256 buildAtomicCmpXchgWithSuccess(Register OldValRes, Register SuccessRes,
1257 Register Addr, Register CmpVal, Register NewVal,
1258 MachineMemOperand &MMO);
1259
1260 /// Build and insert `OldValRes<def> = G_ATOMIC_CMPXCHG Addr, CmpVal, NewVal,
1261 /// MMO`.
1262 ///
1263 /// Atomically replace the value at \p Addr with \p NewVal if it is currently
1264 /// \p CmpVal otherwise leaves it unchanged. Puts the original value from \p
1265 /// Addr in \p Res.
1266 ///
1267 /// \pre setBasicBlock or setMI must have been called.
1268 /// \pre \p OldValRes must be a generic virtual register of scalar type.
1269 /// \pre \p Addr must be a generic virtual register with pointer type.
1270 /// \pre \p OldValRes, \p CmpVal, and \p NewVal must be generic virtual
1271 /// registers of the same type.
1272 ///
1273 /// \return a MachineInstrBuilder for the newly created instruction.
1275 Register CmpVal, Register NewVal,
1276 MachineMemOperand &MMO);
1277
1278 /// Build and insert `OldValRes<def> = G_ATOMICRMW_<Opcode> Addr, Val, MMO`.
1279 ///
1280 /// Atomically read-modify-update the value at \p Addr with \p Val. Puts the
1281 /// original value from \p Addr in \p OldValRes. The modification is
1282 /// determined by the opcode.
1283 ///
1284 /// \pre setBasicBlock or setMI must have been called.
1285 /// \pre \p OldValRes must be a generic virtual register.
1286 /// \pre \p Addr must be a generic virtual register with pointer type.
1287 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1288 /// same type.
1289 ///
1290 /// \return a MachineInstrBuilder for the newly created instruction.
1291 MachineInstrBuilder buildAtomicRMW(unsigned Opcode, const DstOp &OldValRes,
1292 const SrcOp &Addr, const SrcOp &Val,
1293 MachineMemOperand &MMO);
1294
1295 /// Build and insert `OldValRes<def> = G_ATOMICRMW_XCHG Addr, Val, MMO`.
1296 ///
1297 /// Atomically replace the value at \p Addr with \p Val. Puts the original
1298 /// value from \p Addr in \p OldValRes.
1299 ///
1300 /// \pre setBasicBlock or setMI must have been called.
1301 /// \pre \p OldValRes must be a generic virtual register.
1302 /// \pre \p Addr must be a generic virtual register with pointer type.
1303 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1304 /// same type.
1305 ///
1306 /// \return a MachineInstrBuilder for the newly created instruction.
1308 Register Val, MachineMemOperand &MMO);
1309
1310 /// Build and insert `OldValRes<def> = G_ATOMICRMW_ADD Addr, Val, MMO`.
1311 ///
1312 /// Atomically replace the value at \p Addr with the addition of \p Val and
1313 /// the original value. Puts the original value from \p Addr in \p OldValRes.
1314 ///
1315 /// \pre setBasicBlock or setMI must have been called.
1316 /// \pre \p OldValRes must be a generic virtual register.
1317 /// \pre \p Addr must be a generic virtual register with pointer type.
1318 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1319 /// same type.
1320 ///
1321 /// \return a MachineInstrBuilder for the newly created instruction.
1323 Register Val, MachineMemOperand &MMO);
1324
1325 /// Build and insert `OldValRes<def> = G_ATOMICRMW_SUB Addr, Val, MMO`.
1326 ///
1327 /// Atomically replace the value at \p Addr with the subtraction of \p Val and
1328 /// the original value. Puts the original value from \p Addr in \p OldValRes.
1329 ///
1330 /// \pre setBasicBlock or setMI must have been called.
1331 /// \pre \p OldValRes must be a generic virtual register.
1332 /// \pre \p Addr must be a generic virtual register with pointer type.
1333 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1334 /// same type.
1335 ///
1336 /// \return a MachineInstrBuilder for the newly created instruction.
1338 Register Val, MachineMemOperand &MMO);
1339
1340 /// Build and insert `OldValRes<def> = G_ATOMICRMW_AND Addr, Val, MMO`.
1341 ///
1342 /// Atomically replace the value at \p Addr with the bitwise and of \p Val and
1343 /// the original value. Puts the original value from \p Addr in \p OldValRes.
1344 ///
1345 /// \pre setBasicBlock or setMI must have been called.
1346 /// \pre \p OldValRes must be a generic virtual register.
1347 /// \pre \p Addr must be a generic virtual register with pointer type.
1348 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1349 /// same type.
1350 ///
1351 /// \return a MachineInstrBuilder for the newly created instruction.
1353 Register Val, MachineMemOperand &MMO);
1354
1355 /// Build and insert `OldValRes<def> = G_ATOMICRMW_NAND Addr, Val, MMO`.
1356 ///
1357 /// Atomically replace the value at \p Addr with the bitwise nand of \p Val
1358 /// and the original value. Puts the original value from \p Addr in \p
1359 /// OldValRes.
1360 ///
1361 /// \pre setBasicBlock or setMI must have been called.
1362 /// \pre \p OldValRes must be a generic virtual register.
1363 /// \pre \p Addr must be a generic virtual register with pointer type.
1364 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1365 /// same type.
1366 ///
1367 /// \return a MachineInstrBuilder for the newly created instruction.
1369 Register Val, MachineMemOperand &MMO);
1370
1371 /// Build and insert `OldValRes<def> = G_ATOMICRMW_OR Addr, Val, MMO`.
1372 ///
1373 /// Atomically replace the value at \p Addr with the bitwise or of \p Val and
1374 /// the original value. Puts the original value from \p Addr in \p OldValRes.
1375 ///
1376 /// \pre setBasicBlock or setMI must have been called.
1377 /// \pre \p OldValRes must be a generic virtual register.
1378 /// \pre \p Addr must be a generic virtual register with pointer type.
1379 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1380 /// same type.
1381 ///
1382 /// \return a MachineInstrBuilder for the newly created instruction.
1384 Register Val, MachineMemOperand &MMO);
1385
1386 /// Build and insert `OldValRes<def> = G_ATOMICRMW_XOR Addr, Val, MMO`.
1387 ///
1388 /// Atomically replace the value at \p Addr with the bitwise xor of \p Val and
1389 /// the original value. Puts the original value from \p Addr in \p OldValRes.
1390 ///
1391 /// \pre setBasicBlock or setMI must have been called.
1392 /// \pre \p OldValRes must be a generic virtual register.
1393 /// \pre \p Addr must be a generic virtual register with pointer type.
1394 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1395 /// same type.
1396 ///
1397 /// \return a MachineInstrBuilder for the newly created instruction.
1399 Register Val, MachineMemOperand &MMO);
1400
1401 /// Build and insert `OldValRes<def> = G_ATOMICRMW_MAX Addr, Val, MMO`.
1402 ///
1403 /// Atomically replace the value at \p Addr with the signed maximum of \p
1404 /// Val and the original value. Puts the original value from \p Addr in \p
1405 /// OldValRes.
1406 ///
1407 /// \pre setBasicBlock or setMI must have been called.
1408 /// \pre \p OldValRes must be a generic virtual register.
1409 /// \pre \p Addr must be a generic virtual register with pointer type.
1410 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1411 /// same type.
1412 ///
1413 /// \return a MachineInstrBuilder for the newly created instruction.
1415 Register Val, MachineMemOperand &MMO);
1416
1417 /// Build and insert `OldValRes<def> = G_ATOMICRMW_MIN Addr, Val, MMO`.
1418 ///
1419 /// Atomically replace the value at \p Addr with the signed minimum of \p
1420 /// Val and the original value. Puts the original value from \p Addr in \p
1421 /// OldValRes.
1422 ///
1423 /// \pre setBasicBlock or setMI must have been called.
1424 /// \pre \p OldValRes must be a generic virtual register.
1425 /// \pre \p Addr must be a generic virtual register with pointer type.
1426 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1427 /// same type.
1428 ///
1429 /// \return a MachineInstrBuilder for the newly created instruction.
1431 Register Val, MachineMemOperand &MMO);
1432
1433 /// Build and insert `OldValRes<def> = G_ATOMICRMW_UMAX Addr, Val, MMO`.
1434 ///
1435 /// Atomically replace the value at \p Addr with the unsigned maximum of \p
1436 /// Val and the original value. Puts the original value from \p Addr in \p
1437 /// OldValRes.
1438 ///
1439 /// \pre setBasicBlock or setMI must have been called.
1440 /// \pre \p OldValRes must be a generic virtual register.
1441 /// \pre \p Addr must be a generic virtual register with pointer type.
1442 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1443 /// same type.
1444 ///
1445 /// \return a MachineInstrBuilder for the newly created instruction.
1447 Register Val, MachineMemOperand &MMO);
1448
1449 /// Build and insert `OldValRes<def> = G_ATOMICRMW_UMIN Addr, Val, MMO`.
1450 ///
1451 /// Atomically replace the value at \p Addr with the unsigned minimum of \p
1452 /// Val and the original value. Puts the original value from \p Addr in \p
1453 /// OldValRes.
1454 ///
1455 /// \pre setBasicBlock or setMI must have been called.
1456 /// \pre \p OldValRes must be a generic virtual register.
1457 /// \pre \p Addr must be a generic virtual register with pointer type.
1458 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1459 /// same type.
1460 ///
1461 /// \return a MachineInstrBuilder for the newly created instruction.
1463 Register Val, MachineMemOperand &MMO);
1464
1465 /// Build and insert `OldValRes<def> = G_ATOMICRMW_FADD Addr, Val, MMO`.
1467 const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val,
1468 MachineMemOperand &MMO);
1469
1470 /// Build and insert `OldValRes<def> = G_ATOMICRMW_FSUB Addr, Val, MMO`.
1472 const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val,
1473 MachineMemOperand &MMO);
1474
1475 /// Build and insert `OldValRes<def> = G_ATOMICRMW_FMAX Addr, Val, MMO`.
1476 ///
1477 /// Atomically replace the value at \p Addr with the floating point maximum of
1478 /// \p Val and the original value. Puts the original value from \p Addr in \p
1479 /// OldValRes.
1480 ///
1481 /// \pre setBasicBlock or setMI must have been called.
1482 /// \pre \p OldValRes must be a generic virtual register.
1483 /// \pre \p Addr must be a generic virtual register with pointer type.
1484 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1485 /// same type.
1486 ///
1487 /// \return a MachineInstrBuilder for the newly created instruction.
1489 const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val,
1490 MachineMemOperand &MMO);
1491
1492 /// Build and insert `OldValRes<def> = G_ATOMICRMW_FMIN Addr, Val, MMO`.
1493 ///
1494 /// Atomically replace the value at \p Addr with the floating point minimum of
1495 /// \p Val and the original value. Puts the original value from \p Addr in \p
1496 /// OldValRes.
1497 ///
1498 /// \pre setBasicBlock or setMI must have been called.
1499 /// \pre \p OldValRes must be a generic virtual register.
1500 /// \pre \p Addr must be a generic virtual register with pointer type.
1501 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1502 /// same type.
1503 ///
1504 /// \return a MachineInstrBuilder for the newly created instruction.
1506 const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val,
1507 MachineMemOperand &MMO);
1508
1509 /// Build and insert `G_FENCE Ordering, Scope`.
1510 MachineInstrBuilder buildFence(unsigned Ordering, unsigned Scope);
1511
1512 /// Build and insert \p Dst = G_FREEZE \p Src
1513 MachineInstrBuilder buildFreeze(const DstOp &Dst, const SrcOp &Src) {
1514 return buildInstr(TargetOpcode::G_FREEZE, {Dst}, {Src});
1515 }
1516
1517 /// Build and insert \p Res = G_BLOCK_ADDR \p BA
1518 ///
1519 /// G_BLOCK_ADDR computes the address of a basic block.
1520 ///
1521 /// \pre setBasicBlock or setMI must have been called.
1522 /// \pre \p Res must be a generic virtual register of a pointer type.
1523 ///
1524 /// \return The newly created instruction.
1526
1527 /// Build and insert \p Res = G_ADD \p Op0, \p Op1
1528 ///
1529 /// G_ADD sets \p Res to the sum of integer parameters \p Op0 and \p Op1,
1530 /// truncated to their width.
1531 ///
1532 /// \pre setBasicBlock or setMI must have been called.
1533 /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1534 /// with the same (scalar or vector) type).
1535 ///
1536 /// \return a MachineInstrBuilder for the newly created instruction.
1537
1538 MachineInstrBuilder buildAdd(const DstOp &Dst, const SrcOp &Src0,
1539 const SrcOp &Src1,
1540 std::optional<unsigned> Flags = std::nullopt) {
1541 return buildInstr(TargetOpcode::G_ADD, {Dst}, {Src0, Src1}, Flags);
1542 }
1543
1544 /// Build and insert \p Res = G_SUB \p Op0, \p Op1
1545 ///
1546 /// G_SUB sets \p Res to the difference of integer parameters \p Op0 and
1547 /// \p Op1, truncated to their width.
1548 ///
1549 /// \pre setBasicBlock or setMI must have been called.
1550 /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1551 /// with the same (scalar or vector) type).
1552 ///
1553 /// \return a MachineInstrBuilder for the newly created instruction.
1554
1555 MachineInstrBuilder buildSub(const DstOp &Dst, const SrcOp &Src0,
1556 const SrcOp &Src1,
1557 std::optional<unsigned> Flags = std::nullopt) {
1558 return buildInstr(TargetOpcode::G_SUB, {Dst}, {Src0, Src1}, Flags);
1559 }
1560
1561 /// Build and insert \p Res = G_MUL \p Op0, \p Op1
1562 ///
1563 /// G_MUL sets \p Res to the product of integer parameters \p Op0 and \p Op1,
1564 /// truncated to their width.
1565 ///
1566 /// \pre setBasicBlock or setMI must have been called.
1567 /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1568 /// with the same (scalar or vector) type).
1569 ///
1570 /// \return a MachineInstrBuilder for the newly created instruction.
1571 MachineInstrBuilder buildMul(const DstOp &Dst, const SrcOp &Src0,
1572 const SrcOp &Src1,
1573 std::optional<unsigned> Flags = std::nullopt) {
1574 return buildInstr(TargetOpcode::G_MUL, {Dst}, {Src0, Src1}, Flags);
1575 }
1576
1578 const SrcOp &Src1,
1579 std::optional<unsigned> Flags = std::nullopt) {
1580 return buildInstr(TargetOpcode::G_UMULH, {Dst}, {Src0, Src1}, Flags);
1581 }
1582
1584 const SrcOp &Src1,
1585 std::optional<unsigned> Flags = std::nullopt) {
1586 return buildInstr(TargetOpcode::G_SMULH, {Dst}, {Src0, Src1}, Flags);
1587 }
1588
1589 /// Build and insert \p Res = G_UREM \p Op0, \p Op1
1590 MachineInstrBuilder buildURem(const DstOp &Dst, const SrcOp &Src0,
1591 const SrcOp &Src1,
1592 std::optional<unsigned> Flags = std::nullopt) {
1593 return buildInstr(TargetOpcode::G_UREM, {Dst}, {Src0, Src1}, Flags);
1594 }
1595
1596 MachineInstrBuilder buildFMul(const DstOp &Dst, const SrcOp &Src0,
1597 const SrcOp &Src1,
1598 std::optional<unsigned> Flags = std::nullopt) {
1599 return buildInstr(TargetOpcode::G_FMUL, {Dst}, {Src0, Src1}, Flags);
1600 }
1601
1603 buildFMinNum(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1,
1604 std::optional<unsigned> Flags = std::nullopt) {
1605 return buildInstr(TargetOpcode::G_FMINNUM, {Dst}, {Src0, Src1}, Flags);
1606 }
1607
1609 buildFMaxNum(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1,
1610 std::optional<unsigned> Flags = std::nullopt) {
1611 return buildInstr(TargetOpcode::G_FMAXNUM, {Dst}, {Src0, Src1}, Flags);
1612 }
1613
1615 buildFMinNumIEEE(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1,
1616 std::optional<unsigned> Flags = std::nullopt) {
1617 return buildInstr(TargetOpcode::G_FMINNUM_IEEE, {Dst}, {Src0, Src1}, Flags);
1618 }
1619
1621 buildFMaxNumIEEE(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1,
1622 std::optional<unsigned> Flags = std::nullopt) {
1623 return buildInstr(TargetOpcode::G_FMAXNUM_IEEE, {Dst}, {Src0, Src1}, Flags);
1624 }
1625
1626 MachineInstrBuilder buildShl(const DstOp &Dst, const SrcOp &Src0,
1627 const SrcOp &Src1,
1628 std::optional<unsigned> Flags = std::nullopt) {
1629 return buildInstr(TargetOpcode::G_SHL, {Dst}, {Src0, Src1}, Flags);
1630 }
1631
1632 MachineInstrBuilder buildLShr(const DstOp &Dst, const SrcOp &Src0,
1633 const SrcOp &Src1,
1634 std::optional<unsigned> Flags = std::nullopt) {
1635 return buildInstr(TargetOpcode::G_LSHR, {Dst}, {Src0, Src1}, Flags);
1636 }
1637
1638 MachineInstrBuilder buildAShr(const DstOp &Dst, const SrcOp &Src0,
1639 const SrcOp &Src1,
1640 std::optional<unsigned> Flags = std::nullopt) {
1641 return buildInstr(TargetOpcode::G_ASHR, {Dst}, {Src0, Src1}, Flags);
1642 }
1643
1644 /// Build and insert \p Res = G_AND \p Op0, \p Op1
1645 ///
1646 /// G_AND sets \p Res to the bitwise and of integer parameters \p Op0 and \p
1647 /// Op1.
1648 ///
1649 /// \pre setBasicBlock or setMI must have been called.
1650 /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1651 /// with the same (scalar or vector) type).
1652 ///
1653 /// \return a MachineInstrBuilder for the newly created instruction.
1654
1655 MachineInstrBuilder buildAnd(const DstOp &Dst, const SrcOp &Src0,
1656 const SrcOp &Src1) {
1657 return buildInstr(TargetOpcode::G_AND, {Dst}, {Src0, Src1});
1658 }
1659
1660 /// Build and insert \p Res = G_OR \p Op0, \p Op1
1661 ///
1662 /// G_OR sets \p Res to the bitwise or of integer parameters \p Op0 and \p
1663 /// Op1.
1664 ///
1665 /// \pre setBasicBlock or setMI must have been called.
1666 /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1667 /// with the same (scalar or vector) type).
1668 ///
1669 /// \return a MachineInstrBuilder for the newly created instruction.
1670 MachineInstrBuilder buildOr(const DstOp &Dst, const SrcOp &Src0,
1671 const SrcOp &Src1,
1672 std::optional<unsigned> Flags = std::nullopt) {
1673 return buildInstr(TargetOpcode::G_OR, {Dst}, {Src0, Src1}, Flags);
1674 }
1675
1676 /// Build and insert \p Res = G_XOR \p Op0, \p Op1
1677 MachineInstrBuilder buildXor(const DstOp &Dst, const SrcOp &Src0,
1678 const SrcOp &Src1) {
1679 return buildInstr(TargetOpcode::G_XOR, {Dst}, {Src0, Src1});
1680 }
1681
1682 /// Build and insert a bitwise not,
1683 /// \p NegOne = G_CONSTANT -1
1684 /// \p Res = G_OR \p Op0, NegOne
1685 MachineInstrBuilder buildNot(const DstOp &Dst, const SrcOp &Src0) {
1686 auto NegOne = buildConstant(Dst.getLLTTy(*getMRI()), -1);
1687 return buildInstr(TargetOpcode::G_XOR, {Dst}, {Src0, NegOne});
1688 }
1689
1690 /// Build and insert integer negation
1691 /// \p Zero = G_CONSTANT 0
1692 /// \p Res = G_SUB Zero, \p Op0
1693 MachineInstrBuilder buildNeg(const DstOp &Dst, const SrcOp &Src0) {
1694 auto Zero = buildConstant(Dst.getLLTTy(*getMRI()), 0);
1695 return buildInstr(TargetOpcode::G_SUB, {Dst}, {Zero, Src0});
1696 }
1697
1698 /// Build and insert \p Res = G_CTPOP \p Op0, \p Src0
1699 MachineInstrBuilder buildCTPOP(const DstOp &Dst, const SrcOp &Src0) {
1700 return buildInstr(TargetOpcode::G_CTPOP, {Dst}, {Src0});
1701 }
1702
1703 /// Build and insert \p Res = G_CTLZ \p Op0, \p Src0
1704 MachineInstrBuilder buildCTLZ(const DstOp &Dst, const SrcOp &Src0) {
1705 return buildInstr(TargetOpcode::G_CTLZ, {Dst}, {Src0});
1706 }
1707
1708 /// Build and insert \p Res = G_CTLZ_ZERO_UNDEF \p Op0, \p Src0
1710 return buildInstr(TargetOpcode::G_CTLZ_ZERO_UNDEF, {Dst}, {Src0});
1711 }
1712
1713 /// Build and insert \p Res = G_CTTZ \p Op0, \p Src0
1714 MachineInstrBuilder buildCTTZ(const DstOp &Dst, const SrcOp &Src0) {
1715 return buildInstr(TargetOpcode::G_CTTZ, {Dst}, {Src0});
1716 }
1717
1718 /// Build and insert \p Res = G_CTTZ_ZERO_UNDEF \p Op0, \p Src0
1720 return buildInstr(TargetOpcode::G_CTTZ_ZERO_UNDEF, {Dst}, {Src0});
1721 }
1722
1723 /// Build and insert \p Dst = G_BSWAP \p Src0
1724 MachineInstrBuilder buildBSwap(const DstOp &Dst, const SrcOp &Src0) {
1725 return buildInstr(TargetOpcode::G_BSWAP, {Dst}, {Src0});
1726 }
1727
1728 /// Build and insert \p Res = G_FADD \p Op0, \p Op1
1729 MachineInstrBuilder buildFAdd(const DstOp &Dst, const SrcOp &Src0,
1730 const SrcOp &Src1,
1731 std::optional<unsigned> Flags = std::nullopt) {
1732 return buildInstr(TargetOpcode::G_FADD, {Dst}, {Src0, Src1}, Flags);
1733 }
1734
1735 /// Build and insert \p Res = G_STRICT_FADD \p Op0, \p Op1
1737 buildStrictFAdd(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1,
1738 std::optional<unsigned> Flags = std::nullopt) {
1739 return buildInstr(TargetOpcode::G_STRICT_FADD, {Dst}, {Src0, Src1}, Flags);
1740 }
1741
1742 /// Build and insert \p Res = G_FSUB \p Op0, \p Op1
1743 MachineInstrBuilder buildFSub(const DstOp &Dst, const SrcOp &Src0,
1744 const SrcOp &Src1,
1745 std::optional<unsigned> Flags = std::nullopt) {
1746 return buildInstr(TargetOpcode::G_FSUB, {Dst}, {Src0, Src1}, Flags);
1747 }
1748
1749 /// Build and insert \p Res = G_FDIV \p Op0, \p Op1
1750 MachineInstrBuilder buildFDiv(const DstOp &Dst, const SrcOp &Src0,
1751 const SrcOp &Src1,
1752 std::optional<unsigned> Flags = std::nullopt) {
1753 return buildInstr(TargetOpcode::G_FDIV, {Dst}, {Src0, Src1}, Flags);
1754 }
1755
1756 /// Build and insert \p Res = G_FMA \p Op0, \p Op1, \p Op2
1757 MachineInstrBuilder buildFMA(const DstOp &Dst, const SrcOp &Src0,
1758 const SrcOp &Src1, const SrcOp &Src2,
1759 std::optional<unsigned> Flags = std::nullopt) {
1760 return buildInstr(TargetOpcode::G_FMA, {Dst}, {Src0, Src1, Src2}, Flags);
1761 }
1762
1763 /// Build and insert \p Res = G_FMAD \p Op0, \p Op1, \p Op2
1764 MachineInstrBuilder buildFMAD(const DstOp &Dst, const SrcOp &Src0,
1765 const SrcOp &Src1, const SrcOp &Src2,
1766 std::optional<unsigned> Flags = std::nullopt) {
1767 return buildInstr(TargetOpcode::G_FMAD, {Dst}, {Src0, Src1, Src2}, Flags);
1768 }
1769
1770 /// Build and insert \p Res = G_FNEG \p Op0
1771 MachineInstrBuilder buildFNeg(const DstOp &Dst, const SrcOp &Src0,
1772 std::optional<unsigned> Flags = std::nullopt) {
1773 return buildInstr(TargetOpcode::G_FNEG, {Dst}, {Src0}, Flags);
1774 }
1775
1776 /// Build and insert \p Res = G_FABS \p Op0
1777 MachineInstrBuilder buildFAbs(const DstOp &Dst, const SrcOp &Src0,
1778 std::optional<unsigned> Flags = std::nullopt) {
1779 return buildInstr(TargetOpcode::G_FABS, {Dst}, {Src0}, Flags);
1780 }
1781
1782 /// Build and insert \p Dst = G_FCANONICALIZE \p Src0
1784 buildFCanonicalize(const DstOp &Dst, const SrcOp &Src0,
1785 std::optional<unsigned> Flags = std::nullopt) {
1786 return buildInstr(TargetOpcode::G_FCANONICALIZE, {Dst}, {Src0}, Flags);
1787 }
1788
1789 /// Build and insert \p Dst = G_INTRINSIC_TRUNC \p Src0
1791 buildIntrinsicTrunc(const DstOp &Dst, const SrcOp &Src0,
1792 std::optional<unsigned> Flags = std::nullopt) {
1793 return buildInstr(TargetOpcode::G_INTRINSIC_TRUNC, {Dst}, {Src0}, Flags);
1794 }
1795
1796 /// Build and insert \p Res = GFFLOOR \p Op0, \p Op1
1798 buildFFloor(const DstOp &Dst, const SrcOp &Src0,
1799 std::optional<unsigned> Flags = std::nullopt) {
1800 return buildInstr(TargetOpcode::G_FFLOOR, {Dst}, {Src0}, Flags);
1801 }
1802
1803 /// Build and insert \p Dst = G_FLOG \p Src
1805 std::optional<unsigned> Flags = std::nullopt) {
1806 return buildInstr(TargetOpcode::G_FLOG, {Dst}, {Src}, Flags);
1807 }
1808
1809 /// Build and insert \p Dst = G_FLOG2 \p Src
1811 std::optional<unsigned> Flags = std::nullopt) {
1812 return buildInstr(TargetOpcode::G_FLOG2, {Dst}, {Src}, Flags);
1813 }
1814
1815 /// Build and insert \p Dst = G_FEXP2 \p Src
1817 std::optional<unsigned> Flags = std::nullopt) {
1818 return buildInstr(TargetOpcode::G_FEXP2, {Dst}, {Src}, Flags);
1819 }
1820
1821 /// Build and insert \p Dst = G_FPOW \p Src0, \p Src1
1822 MachineInstrBuilder buildFPow(const DstOp &Dst, const SrcOp &Src0,
1823 const SrcOp &Src1,
1824 std::optional<unsigned> Flags = std::nullopt) {
1825 return buildInstr(TargetOpcode::G_FPOW, {Dst}, {Src0, Src1}, Flags);
1826 }
1827
1828 /// Build and insert \p Dst = G_FLDEXP \p Src0, \p Src1
1830 buildFLdexp(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1,
1831 std::optional<unsigned> Flags = std::nullopt) {
1832 return buildInstr(TargetOpcode::G_FLDEXP, {Dst}, {Src0, Src1}, Flags);
1833 }
1834
1835 /// Build and insert \p Res = G_FCOPYSIGN \p Op0, \p Op1
1837 const SrcOp &Src1) {
1838 return buildInstr(TargetOpcode::G_FCOPYSIGN, {Dst}, {Src0, Src1});
1839 }
1840
1841 /// Build and insert \p Res = G_UITOFP \p Src0
1842 MachineInstrBuilder buildUITOFP(const DstOp &Dst, const SrcOp &Src0) {
1843 return buildInstr(TargetOpcode::G_UITOFP, {Dst}, {Src0});
1844 }
1845
1846 /// Build and insert \p Res = G_SITOFP \p Src0
1847 MachineInstrBuilder buildSITOFP(const DstOp &Dst, const SrcOp &Src0) {
1848 return buildInstr(TargetOpcode::G_SITOFP, {Dst}, {Src0});
1849 }
1850
1851 /// Build and insert \p Res = G_FPTOUI \p Src0
1852 MachineInstrBuilder buildFPTOUI(const DstOp &Dst, const SrcOp &Src0) {
1853 return buildInstr(TargetOpcode::G_FPTOUI, {Dst}, {Src0});
1854 }
1855
1856 /// Build and insert \p Res = G_FPTOSI \p Src0
1857 MachineInstrBuilder buildFPTOSI(const DstOp &Dst, const SrcOp &Src0) {
1858 return buildInstr(TargetOpcode::G_FPTOSI, {Dst}, {Src0});
1859 }
1860
1861 /// Build and insert \p Res = G_SMIN \p Op0, \p Op1
1862 MachineInstrBuilder buildSMin(const DstOp &Dst, const SrcOp &Src0,
1863 const SrcOp &Src1) {
1864 return buildInstr(TargetOpcode::G_SMIN, {Dst}, {Src0, Src1});
1865 }
1866
1867 /// Build and insert \p Res = G_SMAX \p Op0, \p Op1
1868 MachineInstrBuilder buildSMax(const DstOp &Dst, const SrcOp &Src0,
1869 const SrcOp &Src1) {
1870 return buildInstr(TargetOpcode::G_SMAX, {Dst}, {Src0, Src1});
1871 }
1872
1873 /// Build and insert \p Res = G_UMIN \p Op0, \p Op1
1874 MachineInstrBuilder buildUMin(const DstOp &Dst, const SrcOp &Src0,
1875 const SrcOp &Src1) {
1876 return buildInstr(TargetOpcode::G_UMIN, {Dst}, {Src0, Src1});
1877 }
1878
1879 /// Build and insert \p Res = G_UMAX \p Op0, \p Op1
1880 MachineInstrBuilder buildUMax(const DstOp &Dst, const SrcOp &Src0,
1881 const SrcOp &Src1) {
1882 return buildInstr(TargetOpcode::G_UMAX, {Dst}, {Src0, Src1});
1883 }
1884
1885 /// Build and insert \p Dst = G_ABS \p Src
1886 MachineInstrBuilder buildAbs(const DstOp &Dst, const SrcOp &Src) {
1887 return buildInstr(TargetOpcode::G_ABS, {Dst}, {Src});
1888 }
1889
1890 /// Build and insert \p Res = G_JUMP_TABLE \p JTI
1891 ///
1892 /// G_JUMP_TABLE sets \p Res to the address of the jump table specified by
1893 /// the jump table index \p JTI.
1894 ///
1895 /// \return a MachineInstrBuilder for the newly created instruction.
1896 MachineInstrBuilder buildJumpTable(const LLT PtrTy, unsigned JTI);
1897
1898 /// Build and insert \p Res = G_VECREDUCE_SEQ_FADD \p ScalarIn, \p VecIn
1899 ///
1900 /// \p ScalarIn is the scalar accumulator input to start the sequential
1901 /// reduction operation of \p VecIn.
1903 const SrcOp &ScalarIn,
1904 const SrcOp &VecIn) {
1905 return buildInstr(TargetOpcode::G_VECREDUCE_SEQ_FADD, {Dst},
1906 {ScalarIn, {VecIn}});
1907 }
1908
1909 /// Build and insert \p Res = G_VECREDUCE_SEQ_FMUL \p ScalarIn, \p VecIn
1910 ///
1911 /// \p ScalarIn is the scalar accumulator input to start the sequential
1912 /// reduction operation of \p VecIn.
1914 const SrcOp &ScalarIn,
1915 const SrcOp &VecIn) {
1916 return buildInstr(TargetOpcode::G_VECREDUCE_SEQ_FMUL, {Dst},
1917 {ScalarIn, {VecIn}});
1918 }
1919
1920 /// Build and insert \p Res = G_VECREDUCE_FADD \p Src
1921 ///
1922 /// \p ScalarIn is the scalar accumulator input to the reduction operation of
1923 /// \p VecIn.
1925 const SrcOp &ScalarIn,
1926 const SrcOp &VecIn) {
1927 return buildInstr(TargetOpcode::G_VECREDUCE_FADD, {Dst}, {ScalarIn, VecIn});
1928 }
1929
1930 /// Build and insert \p Res = G_VECREDUCE_FMUL \p Src
1931 ///
1932 /// \p ScalarIn is the scalar accumulator input to the reduction operation of
1933 /// \p VecIn.
1935 const SrcOp &ScalarIn,
1936 const SrcOp &VecIn) {
1937 return buildInstr(TargetOpcode::G_VECREDUCE_FMUL, {Dst}, {ScalarIn, VecIn});
1938 }
1939
1940 /// Build and insert \p Res = G_VECREDUCE_FMAX \p Src
1942 return buildInstr(TargetOpcode::G_VECREDUCE_FMAX, {Dst}, {Src});
1943 }
1944
1945 /// Build and insert \p Res = G_VECREDUCE_FMIN \p Src
1947 return buildInstr(TargetOpcode::G_VECREDUCE_FMIN, {Dst}, {Src});
1948 }
1949 /// Build and insert \p Res = G_VECREDUCE_ADD \p Src
1951 return buildInstr(TargetOpcode::G_VECREDUCE_ADD, {Dst}, {Src});
1952 }
1953
1954 /// Build and insert \p Res = G_VECREDUCE_MUL \p Src
1956 return buildInstr(TargetOpcode::G_VECREDUCE_MUL, {Dst}, {Src});
1957 }
1958
1959 /// Build and insert \p Res = G_VECREDUCE_AND \p Src
1961 return buildInstr(TargetOpcode::G_VECREDUCE_AND, {Dst}, {Src});
1962 }
1963
1964 /// Build and insert \p Res = G_VECREDUCE_OR \p Src
1966 return buildInstr(TargetOpcode::G_VECREDUCE_OR, {Dst}, {Src});
1967 }
1968
1969 /// Build and insert \p Res = G_VECREDUCE_XOR \p Src
1971 return buildInstr(TargetOpcode::G_VECREDUCE_XOR, {Dst}, {Src});
1972 }
1973
1974 /// Build and insert \p Res = G_VECREDUCE_SMAX \p Src
1976 return buildInstr(TargetOpcode::G_VECREDUCE_SMAX, {Dst}, {Src});
1977 }
1978
1979 /// Build and insert \p Res = G_VECREDUCE_SMIN \p Src
1981 return buildInstr(TargetOpcode::G_VECREDUCE_SMIN, {Dst}, {Src});
1982 }
1983
1984 /// Build and insert \p Res = G_VECREDUCE_UMAX \p Src
1986 return buildInstr(TargetOpcode::G_VECREDUCE_UMAX, {Dst}, {Src});
1987 }
1988
1989 /// Build and insert \p Res = G_VECREDUCE_UMIN \p Src
1991 return buildInstr(TargetOpcode::G_VECREDUCE_UMIN, {Dst}, {Src});
1992 }
1993
1994 /// Build and insert G_MEMCPY or G_MEMMOVE
1995 MachineInstrBuilder buildMemTransferInst(unsigned Opcode, const SrcOp &DstPtr,
1996 const SrcOp &SrcPtr,
1997 const SrcOp &Size,
1998 MachineMemOperand &DstMMO,
1999 MachineMemOperand &SrcMMO) {
2000 auto MIB = buildInstr(
2001 Opcode, {}, {DstPtr, SrcPtr, Size, SrcOp(INT64_C(0) /*isTailCall*/)});
2002 MIB.addMemOperand(&DstMMO);
2003 MIB.addMemOperand(&SrcMMO);
2004 return MIB;
2005 }
2006
2007 MachineInstrBuilder buildMemCpy(const SrcOp &DstPtr, const SrcOp &SrcPtr,
2008 const SrcOp &Size, MachineMemOperand &DstMMO,
2009 MachineMemOperand &SrcMMO) {
2010 return buildMemTransferInst(TargetOpcode::G_MEMCPY, DstPtr, SrcPtr, Size,
2011 DstMMO, SrcMMO);
2012 }
2013
2014 /// Build and insert \p Dst = G_SBFX \p Src, \p LSB, \p Width.
2016 const SrcOp &LSB, const SrcOp &Width) {
2017 return buildInstr(TargetOpcode::G_SBFX, {Dst}, {Src, LSB, Width});
2018 }
2019
2020 /// Build and insert \p Dst = G_UBFX \p Src, \p LSB, \p Width.
2022 const SrcOp &LSB, const SrcOp &Width) {
2023 return buildInstr(TargetOpcode::G_UBFX, {Dst}, {Src, LSB, Width});
2024 }
2025
2026 /// Build and insert \p Dst = G_ROTR \p Src, \p Amt
2028 const SrcOp &Amt) {
2029 return buildInstr(TargetOpcode::G_ROTR, {Dst}, {Src, Amt});
2030 }
2031
2032 /// Build and insert \p Dst = G_ROTL \p Src, \p Amt
2034 const SrcOp &Amt) {
2035 return buildInstr(TargetOpcode::G_ROTL, {Dst}, {Src, Amt});
2036 }
2037
2038 /// Build and insert \p Dst = G_BITREVERSE \p Src
2040 return buildInstr(TargetOpcode::G_BITREVERSE, {Dst}, {Src});
2041 }
2042
2043 virtual MachineInstrBuilder
2044 buildInstr(unsigned Opc, ArrayRef<DstOp> DstOps, ArrayRef<SrcOp> SrcOps,
2045 std::optional<unsigned> Flags = std::nullopt);
2046};
2047
2048} // End namespace llvm.
2049#endif // LLVM_CODEGEN_GLOBALISEL_MACHINEIRBUILDER_H
unsigned const MachineRegisterInfo * MRI
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
static const Function * getParent(const Value *V)
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
uint64_t Addr
uint64_t Size
This contains common code to allow clients to notify changes to machine instr.
IRTranslator LLVM IR MI
unsigned Reg
Module.h This file contains the declarations for the Module class.
#define P(N)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
@ Flags
Definition: TextStubV5.cpp:93
Class for arbitrary precision integers.
Definition: APInt.h:75
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
The address of a basic block.
Definition: Constants.h:874
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:711
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:260
This is the shared class of boolean and integer constants.
Definition: Constants.h:78
This is an important base class in LLVM.
Definition: Constant.h:41
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:110
A debug info location.
Definition: DebugLoc.h:33
DstOp(const LLT T)
DstOp(unsigned R)
DstOp(Register R)
void addDefToMIB(MachineRegisterInfo &MRI, MachineInstrBuilder &MIB) const
LLT getLLTTy(const MachineRegisterInfo &MRI) const
DstOp(const MachineOperand &Op)
DstType getDstOpKind() const
const TargetRegisterClass * RC
const TargetRegisterClass * getRegClass() const
DstOp(const TargetRegisterClass *TRC)
Register getReg() const
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function.
Definition: Function.cpp:319
The CSE Analysis object.
Definition: CSEInfo.h:69
Abstract class that contains various methods for clients to notify about changes.
virtual void createdInstr(MachineInstr &MI)=0
An instruction has been created and inserted into the function.
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:652
static constexpr LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
Definition: LowLevelType.h:42
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
Metadata node.
Definition: Metadata.h:950
Function & getFunction()
Return the LLVM function that this machine code represents.
Helper class to build MachineInstr.
MachineInstrBuilder buildLoadFromOffset(const DstOp &Dst, const SrcOp &BasePtr, MachineMemOperand &BaseMMO, int64_t Offset)
Helper to create a load from a constant offset given a base address.
MachineInstrBuilder buildAtomicRMWFMin(const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_FMIN Addr, Val, MMO.
MachineInstrBuilder buildFSub(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_FSUB Op0, Op1.
MachineInstrBuilder buildFPTOSI(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_FPTOSI Src0.
MachineInstrBuilder buildFMul(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
MachineInstrBuilder buildBoolExtInReg(const DstOp &Res, const SrcOp &Op, bool IsVector, bool IsFP)
MachineInstrBuilder insertInstr(MachineInstrBuilder MIB)
Insert an existing instruction at the insertion point.
MachineInstrBuilder buildFLdexp(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
Build and insert Dst = G_FLDEXP Src0, Src1.
MachineInstrBuilder buildFreeze(const DstOp &Dst, const SrcOp &Src)
Build and insert Dst = G_FREEZE Src.
MachineInstrBuilder buildAtomicRMWXor(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_XOR Addr, Val, MMO.
MachineInstrBuilder buildGlobalValue(const DstOp &Res, const GlobalValue *GV)
Build and insert Res = G_GLOBAL_VALUE GV.
MachineInstrBuilder buildBr(MachineBasicBlock &Dest)
Build and insert G_BR Dest.
void setInsertPt(MachineBasicBlock &MBB, MachineBasicBlock::iterator II)
Set the insertion point before the specified position.
const MachineFunction & getMF() const
std::optional< MachineInstrBuilder > materializePtrAdd(Register &Res, Register Op0, const LLT ValueTy, uint64_t Value)
Materialize and insert Res = G_PTR_ADD Op0, (G_CONSTANT Value)
LLVMContext & getContext() const
MachineInstrBuilder buildAdd(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_ADD Op0, Op1.
MachineInstrBuilder buildUndef(const DstOp &Res)
Build and insert Res = IMPLICIT_DEF.
MachineInstrBuilder buildFPExt(const DstOp &Res, const SrcOp &Op, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_FPEXT Op.
MachineInstrBuilder buildNot(const DstOp &Dst, const SrcOp &Src0)
Build and insert a bitwise not, NegOne = G_CONSTANT -1 Res = G_OR Op0, NegOne.
MachineInstrBuilder buildVecReduceSeqFAdd(const DstOp &Dst, const SrcOp &ScalarIn, const SrcOp &VecIn)
Build and insert Res = G_VECREDUCE_SEQ_FADD ScalarIn, VecIn.
MachineInstrBuilder buildRotateRight(const DstOp &Dst, const SrcOp &Src, const SrcOp &Amt)
Build and insert Dst = G_ROTR Src, Amt.
MachineInstrBuilder buildCTTZ(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_CTTZ Op0, Src0.
virtual ~MachineIRBuilder()=default
MachineInstrBuilder buildVecReduceOr(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_OR Src.
MachineInstrBuilder buildFLog2(const DstOp &Dst, const SrcOp &Src, std::optional< unsigned > Flags=std::nullopt)
Build and insert Dst = G_FLOG2 Src.
MachineInstrBuilder buildAShr(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
MachineInstrBuilder buildConstantPool(const DstOp &Res, unsigned Idx)
Build and insert Res = G_CONSTANT_POOL Idx.
MachineInstrBuilder buildJumpTable(const LLT PtrTy, unsigned JTI)
Build and insert Res = G_JUMP_TABLE JTI.
MachineInstrBuilder buildBoolExt(const DstOp &Res, const SrcOp &Op, bool IsFP)
MachineInstrBuilder buildUnmerge(ArrayRef< LLT > Res, const SrcOp &Op)
Build and insert Res0, ... = G_UNMERGE_VALUES Op.
MachineInstrBuilder buildFAbs(const DstOp &Dst, const SrcOp &Src0, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_FABS Op0.
MachineInstrBuilder buildFence(unsigned Ordering, unsigned Scope)
Build and insert G_FENCE Ordering, Scope.
MachineInstrBuilder buildFMinNumIEEE(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
MachineInstrBuilder buildSelect(const DstOp &Res, const SrcOp &Tst, const SrcOp &Op0, const SrcOp &Op1, std::optional< unsigned > Flags=std::nullopt)
Build and insert a Res = G_SELECT Tst, Op0, Op1.
MachineInstrBuilder buildFMA(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, const SrcOp &Src2, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_FMA Op0, Op1, Op2.
MachineInstrBuilder buildAtomicRMWAnd(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_AND Addr, Val, MMO.
MachineInstrBuilder buildZExtInReg(const DstOp &Res, const SrcOp &Op, int64_t ImmOp)
Build and inserts Res = G_AND Op, LowBitsSet(ImmOp) Since there is no G_ZEXT_INREG like G_SEXT_INREG,...
MachineInstrBuilder buildSMulH(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
GISelCSEInfo * getCSEInfo()
MachineInstrBuilder buildAtomicRMWMin(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_MIN Addr, Val, MMO.
MachineInstrBuilder buildVecReduceFMax(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_FMAX Src.
MachineInstrBuilder buildExtract(const DstOp &Res, const SrcOp &Src, uint64_t Index)
Build and insert Res0, ... = G_EXTRACT Src, Idx0.
MachineInstrBuilder buildMul(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_MUL Op0, Op1.
MachineInstrBuilder buildAnd(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_AND Op0, Op1.
MachineInstrBuilder buildICmp(CmpInst::Predicate Pred, const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1)
Build and insert a Res = G_ICMP Pred, Op0, Op1.
MachineInstrBuilder buildCast(const DstOp &Dst, const SrcOp &Src)
Build and insert an appropriate cast between two registers of equal size.
const TargetInstrInfo & getTII()
MachineInstrBuilder buildAtomicRMWFAdd(const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_FADD Addr, Val, MMO.
MachineInstrBuilder buildSAdde(const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1, const SrcOp &CarryIn)
Build and insert Res, CarryOut = G_SADDE Op0, Op1, CarryInp.
MachineInstrBuilder buildAtomicRMWNand(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_NAND Addr, Val, MMO.
MachineInstrBuilder buildURem(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_UREM Op0, Op1.
MachineInstrBuilder buildSAddo(const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1)
Build and insert Res, CarryOut = G_SADDO Op0, Op1.
MachineInstrBuilder buildFPTOUI(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_FPTOUI Src0.
MachineInstrBuilder buildLShr(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
MachineInstrBuilder buildFPow(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
Build and insert Dst = G_FPOW Src0, Src1.
MachineInstrBuilder buildAnyExtOrTrunc(const DstOp &Res, const SrcOp &Op)
Res = COPY Op depending on the differing sizes of Res and Op.
MachineInstrBuilder buildSExt(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_SEXT Op.
MachineInstrBuilder buildIntrinsicTrunc(const DstOp &Dst, const SrcOp &Src0, std::optional< unsigned > Flags=std::nullopt)
Build and insert Dst = G_INTRINSIC_TRUNC Src0.
MachineBasicBlock::iterator getInsertPt()
Current insertion point for new instructions.
MachineInstrBuilder buildSExtOrTrunc(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_SEXT Op, Res = G_TRUNC Op, or Res = COPY Op depending on the differing sizes...
MachineInstrBuilder buildShuffleSplat(const DstOp &Res, const SrcOp &Src)
Build and insert a vector splat of a scalar Src using a G_INSERT_VECTOR_ELT and G_SHUFFLE_VECTOR idio...
MachineInstrBuilder buildAtomicCmpXchgWithSuccess(Register OldValRes, Register SuccessRes, Register Addr, Register CmpVal, Register NewVal, MachineMemOperand &MMO)
Build and insert OldValRes<def>, SuccessRes<def> = G_ATOMIC_CMPXCHG_WITH_SUCCESS Addr,...
MachineInstrBuilder buildConcatVectors(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_CONCAT_VECTORS Op0, ...
MachineInstrBuilder buildAtomicRMW(unsigned Opcode, const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_<Opcode> Addr, Val, MMO.
MachineInstrBuilder buildVecReduceSeqFMul(const DstOp &Dst, const SrcOp &ScalarIn, const SrcOp &VecIn)
Build and insert Res = G_VECREDUCE_SEQ_FMUL ScalarIn, VecIn.
MachineInstrBuilder buildSub(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_SUB Op0, Op1.
void setInstr(MachineInstr &MI)
Set the insertion point to before MI.
MDNode * getPCSections()
Get the current instruction's PC sections metadata.
MachineInstrBuilder buildBSwap(const DstOp &Dst, const SrcOp &Src0)
Build and insert Dst = G_BSWAP Src0.
MachineInstrBuilder buildVecReduceFMul(const DstOp &Dst, const SrcOp &ScalarIn, const SrcOp &VecIn)
Build and insert Res = G_VECREDUCE_FMUL Src.
MachineInstrBuilder buildCTLZ_ZERO_UNDEF(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_CTLZ_ZERO_UNDEF Op0, Src0.
MachineInstrBuilder buildAddrSpaceCast(const DstOp &Dst, const SrcOp &Src)
Build and insert Dst = G_ADDRSPACE_CAST Src.
MachineInstrBuilder buildFExp2(const DstOp &Dst, const SrcOp &Src, std::optional< unsigned > Flags=std::nullopt)
Build and insert Dst = G_FEXP2 Src.
MachineInstrBuilder buildIntToPtr(const DstOp &Dst, const SrcOp &Src)
Build and insert a G_INTTOPTR instruction.
MachineInstrBuilder buildIndirectDbgValue(Register Reg, const MDNode *Variable, const MDNode *Expr)
Build and insert a DBG_VALUE instruction expressing the fact that the associated Variable lives in me...
unsigned getBoolExtOp(bool IsVec, bool IsFP) const
MachineInstrBuilder buildUSubo(const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1)
Build and insert Res, CarryOut = G_USUBO Op0, Op1.
MachineInstrBuilder buildVecReduceFAdd(const DstOp &Dst, const SrcOp &ScalarIn, const SrcOp &VecIn)
Build and insert Res = G_VECREDUCE_FADD Src.
MachineInstrBuilder buildAtomicRMWUmax(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_UMAX Addr, Val, MMO.
MachineInstrBuilder buildBuildVector(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_BUILD_VECTOR Op0, ...
MachineIRBuilder(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsPt)
MachineInstrBuilder buildNeg(const DstOp &Dst, const SrcOp &Src0)
Build and insert integer negation Zero = G_CONSTANT 0 Res = G_SUB Zero, Op0.
MachineInstrBuilder buildVecReduceSMin(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_SMIN Src.
MachineInstrBuilder buildCTLZ(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_CTLZ Op0, Src0.
MachineInstrBuilder buildSMax(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_SMAX Op0, Op1.
MachineInstrBuilder buildConstDbgValue(const Constant &C, const MDNode *Variable, const MDNode *Expr)
Build and insert a DBG_VALUE instructions specifying that Variable is given by C (suitably modified b...
MachineInstrBuilder buildAssertZExt(const DstOp &Res, const SrcOp &Op, unsigned Size)
Build and insert Res = G_ASSERT_ZEXT Op, Size.
void recordInsertion(MachineInstr *InsertedInstr) const
MachineInstrBuilder buildUMulH(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
MachineInstrBuilder buildStrictFAdd(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_STRICT_FADD Op0, Op1.
MachineInstrBuilder buildBrCond(const SrcOp &Tst, MachineBasicBlock &Dest)
Build and insert G_BRCOND Tst, Dest.
MachineInstrBuilder buildVecReduceXor(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_XOR Src.
MachineInstrBuilder buildVecReduceFMin(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_FMIN Src.
MachineInstrBuilder buildFDiv(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_FDIV Op0, Op1.
MachineInstrBuilder buildMergeLikeInstr(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_MERGE_VALUES Op0, ... or Res = G_BUILD_VECTOR Op0, ... or Res = G_CONCAT_VEC...
const GISelCSEInfo * getCSEInfo() const
MachineInstrBuilder buildExtractVectorElement(const DstOp &Res, const SrcOp &Val, const SrcOp &Idx)
Build and insert Res = G_EXTRACT_VECTOR_ELT Val, Idx.
MachineInstrBuilder buildLoad(const DstOp &Res, const SrcOp &Addr, MachineMemOperand &MMO)
Build and insert Res = G_LOAD Addr, MMO.
MachineInstrBuilder buildZExtOrTrunc(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_ZEXT Op, Res = G_TRUNC Op, or Res = COPY Op depending on the differing sizes...
MachineInstrBuilder buildBuildVectorTrunc(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_BUILD_VECTOR_TRUNC Op0, ...
MachineBasicBlock & getMBB()
MachineIRBuilder(MachineInstr &MI)
MachineInstrBuilder buildExtractVectorElementConstant(const DstOp &Res, const SrcOp &Val, const int Idx)
Build and insert Res = G_EXTRACT_VECTOR_ELT Val, Idx.
MachineInstrBuilder buildCTTZ_ZERO_UNDEF(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_CTTZ_ZERO_UNDEF Op0, Src0.
virtual MachineInstrBuilder buildFConstant(const DstOp &Res, const ConstantFP &Val)
Build and insert Res = G_FCONSTANT Val.
MachineInstrBuilder buildBitReverse(const DstOp &Dst, const SrcOp &Src)
Build and insert Dst = G_BITREVERSE Src.
MachineInstrBuilder buildPtrAdd(const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1)
Build and insert Res = G_PTR_ADD Op0, Op1.
MachineInstrBuilder buildShl(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
MachineInstrBuilder buildUITOFP(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_UITOFP Src0.
MachineInstrBuilder buildStore(const SrcOp &Val, const SrcOp &Addr, MachineMemOperand &MMO)
Build and insert G_STORE Val, Addr, MMO.
MachineInstrBuilder buildAtomicCmpXchg(Register OldValRes, Register Addr, Register CmpVal, Register NewVal, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMIC_CMPXCHG Addr, CmpVal, NewVal, MMO.
MachineInstrBuilder buildInstr(unsigned Opcode)
Build and insert <empty> = Opcode <empty>.
MachineInstrBuilder buildSITOFP(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_SITOFP Src0.
MachineIRBuilder(MachineInstr &MI, GISelChangeObserver &Observer)
MachineInstrBuilder buildFMAD(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, const SrcOp &Src2, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_FMAD Op0, Op1, Op2.
MachineInstrBuilder buildPadVectorWithUndefElements(const DstOp &Res, const SrcOp &Op0)
Build and insert a, b, ..., x = G_UNMERGE_VALUES Op0 Res = G_BUILD_VECTOR a, b, .....
MachineInstrBuilder buildFLog(const DstOp &Dst, const SrcOp &Src, std::optional< unsigned > Flags=std::nullopt)
Build and insert Dst = G_FLOG Src.
void validateSelectOp(const LLT ResTy, const LLT TstTy, const LLT Op0Ty, const LLT Op1Ty)
MachineInstrBuilder buildFrameIndex(const DstOp &Res, int Idx)
Build and insert Res = G_FRAME_INDEX Idx.
MachineInstrBuilder buildVecReduceUMax(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_UMAX Src.
MachineInstrBuilder buildDirectDbgValue(Register Reg, const MDNode *Variable, const MDNode *Expr)
Build and insert a DBG_VALUE instruction expressing the fact that the associated Variable lives in Re...
const DebugLoc & getDL()
Getter for DebugLoc.
MachineInstrBuilder buildUbfx(const DstOp &Dst, const SrcOp &Src, const SrcOp &LSB, const SrcOp &Width)
Build and insert Dst = G_UBFX Src, LSB, Width.
const MachineRegisterInfo * getMRI() const
MachineInstrBuilder buildCTPOP(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_CTPOP Op0, Src0.
MachineInstrBuilder buildAbs(const DstOp &Dst, const SrcOp &Src)
Build and insert Dst = G_ABS Src.
MachineInstrBuilder buildBuildVectorConstant(const DstOp &Res, ArrayRef< APInt > Ops)
Build and insert Res = G_BUILD_VECTOR Op0, ... where each OpN is built with G_CONSTANT.
MachineInstrBuilder buildAtomicRMWUmin(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_UMIN Addr, Val, MMO.
void validateBinaryOp(const LLT Res, const LLT Op0, const LLT Op1)
MachineInstrBuilder buildVecReduceAnd(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_AND Src.
void validateShiftOp(const LLT Res, const LLT Op0, const LLT Op1)
MachineInstrBuilder buildZExt(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_ZEXT Op.
MachineFunction & getMF()
Getter for the function we currently build.
MachineIRBuilder(MachineFunction &MF)
MachineIRBuilder(const MachineIRBuilderState &BState)
MachineInstrBuilder buildMemCpy(const SrcOp &DstPtr, const SrcOp &SrcPtr, const SrcOp &Size, MachineMemOperand &DstMMO, MachineMemOperand &SrcMMO)
MachineInstrBuilder buildAssertAlign(const DstOp &Res, const SrcOp &Op, Align AlignVal)
Build and insert Res = G_ASSERT_ALIGN Op, AlignVal.
MachineInstrBuilder buildSbfx(const DstOp &Dst, const SrcOp &Src, const SrcOp &LSB, const SrcOp &Width)
Build and insert Dst = G_SBFX Src, LSB, Width.
MachineInstrBuilder buildFMaxNum(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
MachineInstrBuilder buildSMin(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_SMIN Op0, Op1.
MachineInstrBuilder buildFMinNum(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
MachineInstrBuilder buildDbgLabel(const MDNode *Label)
Build and insert a DBG_LABEL instructions specifying that Label is given.
MachineInstrBuilder buildBrJT(Register TablePtr, unsigned JTI, Register IndexReg)
Build and insert G_BRJT TablePtr, JTI, IndexReg.
MachineInstrBuilder buildInsert(const DstOp &Res, const SrcOp &Src, const SrcOp &Op, unsigned Index)
MachineInstrBuilder buildDynStackAlloc(const DstOp &Res, const SrcOp &Size, Align Alignment)
Build and insert Res = G_DYN_STACKALLOC Size, Align.
MachineInstrBuilder buildVecReduceUMin(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_UMIN Src.
MachineInstrBuilder buildFIDbgValue(int FI, const MDNode *Variable, const MDNode *Expr)
Build and insert a DBG_VALUE instruction expressing the fact that the associated Variable lives in th...
void setInstrAndDebugLoc(MachineInstr &MI)
Set the insertion point to before MI, and set the debug loc to MI's loc.
MachineInstrBuilder buildSSube(const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1, const SrcOp &CarryIn)
Build and insert Res, CarryOut = G_SSUBE Op0, Op1, CarryInp.
void setPCSections(MDNode *MD)
Set the PC sections metadata to MD for all the next build instructions.
MachineInstrBuilder buildExtOrTrunc(unsigned ExtOpc, const DstOp &Res, const SrcOp &Op)
Build and insert Res = ExtOpc, Res = G_TRUNC Op, or Res = COPY Op depending on the differing sizes of...
MachineInstrBuilder buildVecReduceAdd(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_ADD Src.
MachineInstrBuilder buildAtomicRMWSub(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_SUB Addr, Val, MMO.
MachineInstrBuilder buildMergeValues(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_MERGE_VALUES Op0, ...
MachineInstrBuilder buildUAdde(const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1, const SrcOp &CarryIn)
Build and insert Res, CarryOut = G_UADDE Op0, Op1, CarryIn.
MachineInstrBuilder buildAtomicRMWFMax(const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_FMAX Addr, Val, MMO.
void setDebugLoc(const DebugLoc &DL)
Set the debug location to DL for all the next build instructions.
MachineInstrBuilder buildFCopysign(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_FCOPYSIGN Op0, Op1.
MachineInstrBuilder buildSplatVector(const DstOp &Res, const SrcOp &Src)
Build and insert Res = G_BUILD_VECTOR with Src replicated to fill the number of elements.
MachineInstrBuilder buildSSubo(const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1)
Build and insert Res, CarryOut = G_SUBO Op0, Op1.
MachineInstrBuilder buildAtomicRMWOr(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_OR Addr, Val, MMO.
MachineInstrBuilder buildUSube(const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1, const SrcOp &CarryIn)
Build and insert Res, CarryOut = G_USUBE Op0, Op1, CarryInp.
const MachineBasicBlock & getMBB() const
Getter for the basic block we currently build.
MachineInstrBuilder buildFNeg(const DstOp &Dst, const SrcOp &Src0, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_FNEG Op0.
MachineInstrBuilder buildInsertVectorElement(const DstOp &Res, const SrcOp &Val, const SrcOp &Elt, const SrcOp &Idx)
Build and insert Res = G_INSERT_VECTOR_ELT Val, Elt, Idx.
MachineInstrBuilder buildAnyExt(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_ANYEXT Op0.
MachineInstrBuilder buildIntrinsic(Intrinsic::ID ID, ArrayRef< Register > Res, bool HasSideEffects)
Build and insert either a G_INTRINSIC (if HasSideEffects is false) or G_INTRINSIC_W_SIDE_EFFECTS inst...
void setMBB(MachineBasicBlock &MBB)
Set the insertion point to the end of MBB.
MachineInstrBuilder buildBitcast(const DstOp &Dst, const SrcOp &Src)
Build and insert Dst = G_BITCAST Src.
const DebugLoc & getDebugLoc()
Get the current instruction's debug location.
MachineInstrBuilder buildUAddo(const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1)
Build and insert Res, CarryOut = G_UADDO Op0, Op1.
void setCSEInfo(GISelCSEInfo *Info)
MachineInstrBuilder buildFMaxNumIEEE(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
MachineInstrBuilder buildTrunc(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_TRUNC Op.
MachineInstrBuilder buildFFloor(const DstOp &Dst, const SrcOp &Src0, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = GFFLOOR Op0, Op1.
MachineIRBuilder()=default
Some constructors for easy use.
MachineInstrBuilder buildDeleteTrailingVectorElements(const DstOp &Res, const SrcOp &Op0)
Build and insert a, b, ..., x, y, z = G_UNMERGE_VALUES Op0 Res = G_BUILD_VECTOR a,...
MachineRegisterInfo * getMRI()
Getter for MRI.
MachineInstrBuilder buildAtomicRMWAdd(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_ADD Addr, Val, MMO.
MachineInstrBuilder buildFPTrunc(const DstOp &Res, const SrcOp &Op, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_FPTRUNC Op.
MachineInstrBuilder buildOr(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_OR Op0, Op1.
MachineIRBuilderState & getState()
Getter for the State.
MachineInstrBuilder buildShuffleVector(const DstOp &Res, const SrcOp &Src1, const SrcOp &Src2, ArrayRef< int > Mask)
Build and insert Res = G_SHUFFLE_VECTOR Src1, Src2, Mask.
MachineInstrBuilder buildAssertInstr(unsigned Opc, const DstOp &Res, const SrcOp &Op, unsigned Val)
Build and insert G_ASSERT_SEXT, G_ASSERT_ZEXT, or G_ASSERT_ALIGN.
void validateTruncExt(const LLT Dst, const LLT Src, bool IsExtend)
MachineInstrBuilder buildInstrNoInsert(unsigned Opcode)
Build but don't insert <empty> = Opcode <empty>.
MachineInstrBuilder buildPtrMask(const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1)
Build and insert Res = G_PTRMASK Op0, Op1.
MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op)
Build and insert Res = COPY Op.
MachineInstrBuilder buildVecReduceSMax(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_SMAX Src.
MachineInstrBuilder buildMemTransferInst(unsigned Opcode, const SrcOp &DstPtr, const SrcOp &SrcPtr, const SrcOp &Size, MachineMemOperand &DstMMO, MachineMemOperand &SrcMMO)
Build and insert G_MEMCPY or G_MEMMOVE.
void validateUnaryOp(const LLT Res, const LLT Op0)
MachineInstrBuilder buildBlockAddress(Register Res, const BlockAddress *BA)
Build and insert Res = G_BLOCK_ADDR BA.
MachineInstrBuilder buildAtomicRMWMax(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_MAX Addr, Val, MMO.
const DataLayout & getDataLayout() const
MachineInstrBuilder buildBrIndirect(Register Tgt)
Build and insert G_BRINDIRECT Tgt.
MachineInstrBuilder buildLoadInstr(unsigned Opcode, const DstOp &Res, const SrcOp &Addr, MachineMemOperand &MMO)
Build and insert Res = <opcode> Addr, MMO.
void setMF(MachineFunction &MF)
MachineInstrBuilder buildAtomicRMWFSub(const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_FSUB Addr, Val, MMO.
MachineInstrBuilder buildAssertSExt(const DstOp &Res, const SrcOp &Op, unsigned Size)
Build and insert Res = G_ASSERT_SEXT Op, Size.
MachineInstrBuilder buildXor(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_XOR Op0, Op1.
MachineInstrBuilder buildAtomicRMWXchg(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_XCHG Addr, Val, MMO.
void setChangeObserver(GISelChangeObserver &Observer)
MachineInstrBuilder buildMaskLowPtrBits(const DstOp &Res, const SrcOp &Op0, uint32_t NumBits)
Build and insert Res = G_PTRMASK Op0, G_CONSTANT (1 << NumBits) - 1.
virtual MachineInstrBuilder buildConstant(const DstOp &Res, const ConstantInt &Val)
Build and insert Res = G_CONSTANT Val.
MachineInstrBuilder buildVecReduceMul(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_MUL Src.
MachineInstrBuilder buildUMin(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_UMIN Op0, Op1.
MachineInstrBuilder buildUMax(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_UMAX Op0, Op1.
MachineInstrBuilder buildFCmp(CmpInst::Predicate Pred, const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1, std::optional< unsigned > Flags=std::nullopt)
Build and insert a Res = G_FCMP PredOp0, Op1.
MachineInstrBuilder buildFAdd(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_FADD Op0, Op1.
MachineInstrBuilder buildPtrToInt(const DstOp &Dst, const SrcOp &Src)
Build and insert a G_PTRTOINT instruction.
MachineInstrBuilder buildFCanonicalize(const DstOp &Dst, const SrcOp &Src0, std::optional< unsigned > Flags=std::nullopt)
Build and insert Dst = G_FCANONICALIZE Src0.
MachineInstrBuilder buildSExtInReg(const DstOp &Res, const SrcOp &Op, int64_t ImmOp)
Build and insert Res = G_SEXT_INREG Op, ImmOp.
MachineInstrBuilder buildRotateLeft(const DstOp &Dst, const SrcOp &Src, const SrcOp &Amt)
Build and insert Dst = G_ROTL Src, Amt.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & addPredicate(CmpInst::Predicate Pred) const
const MachineInstrBuilder & addUse(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
Representation of each machine instruction.
Definition: MachineInstr.h:68
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:533
A description of a memory reference used in the backend.
Flags
Flags values. These may be or'd together.
MachineOperand class - Representation of each machine instruction operand.
Register getReg() const
getReg - Returns the register number.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
const DataLayout & getDataLayout() const
Get the data layout for the module's target platform.
Definition: Module.cpp:398
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
SrcOp(const MachineInstrBuilder &MIB)
SrcOp(int64_t V)
SrcOp(const CmpInst::Predicate P)
SrcOp(uint64_t V)
SrcOp(int)=delete
MachineInstrBuilder SrcMIB
CmpInst::Predicate getPredicate() const
SrcType getSrcOpKind() const
CmpInst::Predicate Pred
int64_t getImm() const
LLT getLLTTy(const MachineRegisterInfo &MRI) const
SrcOp(const MachineOperand &Op)
void addSrcToMIB(MachineInstrBuilder &MIB) const
SrcOp(unsigned)=delete
Use of registers held in unsigned integer variables (or more rarely signed integers) is no longer per...
Register getReg() const
SrcOp(Register R)
TargetInstrInfo - Interface to description of machine instruction set.
LLVM Value Representation.
Definition: Value.h:74
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
@ ConstantFP
Definition: ISDOpcodes.h:77
@ BlockAddress
Definition: ISDOpcodes.h:84
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:440
A collection of metadata nodes that might be associated with a memory access used by the alias-analys...
Definition: Metadata.h:651
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
uint64_t value() const
This is a hole in the type system and should not be abused.
Definition: Alignment.h:85
Class which stores all the state required in a MachineIRBuilder.
MachineFunction * MF
MachineFunction under construction.
DebugLoc DL
Debug location to be set to any instruction we create.
const TargetInstrInfo * TII
Information used to access the description of the opcodes.
MDNode * PCSections
PC sections metadata to be set to any instruction we create.
MachineBasicBlock::iterator II
MachineRegisterInfo * MRI
Information used to verify types are consistent and to create virtual registers.
GISelChangeObserver * Observer
This class contains a discriminated union of information about pointers in memory operands,...