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MachineIRBuilder.h
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1 //===-- llvm/CodeGen/GlobalISel/MachineIRBuilder.h - MIBuilder --*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file declares the MachineIRBuilder class.
10 /// This is a helper class to build MachineInstr.
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_CODEGEN_GLOBALISEL_MACHINEIRBUILDER_H
14 #define LLVM_CODEGEN_GLOBALISEL_MACHINEIRBUILDER_H
15 
22 #include "llvm/IR/Constants.h"
23 #include "llvm/IR/DebugLoc.h"
24 #include "llvm/IR/Module.h"
25 
26 namespace llvm {
27 
28 // Forward declarations.
29 class MachineFunction;
30 class MachineInstr;
31 class TargetInstrInfo;
32 class GISelChangeObserver;
33 
34 /// Class which stores all the state required in a MachineIRBuilder.
35 /// Since MachineIRBuilders will only store state in this object, it allows
36 /// to transfer BuilderState between different kinds of MachineIRBuilders.
38  /// MachineFunction under construction.
39  MachineFunction *MF = nullptr;
40  /// Information used to access the description of the opcodes.
41  const TargetInstrInfo *TII = nullptr;
42  /// Information used to verify types are consistent and to create virtual registers.
44  /// Debug location to be set to any instruction we create.
46 
47  /// \name Fields describing the insertion point.
48  /// @{
49  MachineBasicBlock *MBB = nullptr;
51  /// @}
52 
54 
55  GISelCSEInfo *CSEInfo = nullptr;
56 };
57 
58 class DstOp {
59  union {
63  };
64 
65 public:
66  enum class DstType { Ty_LLT, Ty_Reg, Ty_RC };
67  DstOp(unsigned R) : Reg(R), Ty(DstType::Ty_Reg) {}
68  DstOp(Register R) : Reg(R), Ty(DstType::Ty_Reg) {}
69  DstOp(const MachineOperand &Op) : Reg(Op.getReg()), Ty(DstType::Ty_Reg) {}
70  DstOp(const LLT T) : LLTTy(T), Ty(DstType::Ty_LLT) {}
71  DstOp(const TargetRegisterClass *TRC) : RC(TRC), Ty(DstType::Ty_RC) {}
72 
74  switch (Ty) {
75  case DstType::Ty_Reg:
76  MIB.addDef(Reg);
77  break;
78  case DstType::Ty_LLT:
79  MIB.addDef(MRI.createGenericVirtualRegister(LLTTy));
80  break;
81  case DstType::Ty_RC:
82  MIB.addDef(MRI.createVirtualRegister(RC));
83  break;
84  }
85  }
86 
88  switch (Ty) {
89  case DstType::Ty_RC:
90  return LLT{};
91  case DstType::Ty_LLT:
92  return LLTTy;
93  case DstType::Ty_Reg:
94  return MRI.getType(Reg);
95  }
96  llvm_unreachable("Unrecognised DstOp::DstType enum");
97  }
98 
99  Register getReg() const {
100  assert(Ty == DstType::Ty_Reg && "Not a register");
101  return Reg;
102  }
103 
105  switch (Ty) {
106  case DstType::Ty_RC:
107  return RC;
108  default:
109  llvm_unreachable("Not a RC Operand");
110  }
111  }
112 
113  DstType getDstOpKind() const { return Ty; }
114 
115 private:
116  DstType Ty;
117 };
118 
119 class SrcOp {
120  union {
124  int64_t Imm;
125  };
126 
127 public:
129  SrcOp(Register R) : Reg(R), Ty(SrcType::Ty_Reg) {}
130  SrcOp(const MachineOperand &Op) : Reg(Op.getReg()), Ty(SrcType::Ty_Reg) {}
131  SrcOp(const MachineInstrBuilder &MIB) : SrcMIB(MIB), Ty(SrcType::Ty_MIB) {}
132  SrcOp(const CmpInst::Predicate P) : Pred(P), Ty(SrcType::Ty_Predicate) {}
133  /// Use of registers held in unsigned integer variables (or more rarely signed
134  /// integers) is no longer permitted to avoid ambiguity with upcoming support
135  /// for immediates.
136  SrcOp(unsigned) = delete;
137  SrcOp(int) = delete;
138  SrcOp(uint64_t V) : Imm(V), Ty(SrcType::Ty_Imm) {}
139  SrcOp(int64_t V) : Imm(V), Ty(SrcType::Ty_Imm) {}
140 
141  void addSrcToMIB(MachineInstrBuilder &MIB) const {
142  switch (Ty) {
144  MIB.addPredicate(Pred);
145  break;
146  case SrcType::Ty_Reg:
147  MIB.addUse(Reg);
148  break;
149  case SrcType::Ty_MIB:
150  MIB.addUse(SrcMIB->getOperand(0).getReg());
151  break;
152  case SrcType::Ty_Imm:
153  MIB.addImm(Imm);
154  break;
155  }
156  }
157 
159  switch (Ty) {
161  case SrcType::Ty_Imm:
162  llvm_unreachable("Not a register operand");
163  case SrcType::Ty_Reg:
164  return MRI.getType(Reg);
165  case SrcType::Ty_MIB:
166  return MRI.getType(SrcMIB->getOperand(0).getReg());
167  }
168  llvm_unreachable("Unrecognised SrcOp::SrcType enum");
169  }
170 
171  Register getReg() const {
172  switch (Ty) {
174  case SrcType::Ty_Imm:
175  llvm_unreachable("Not a register operand");
176  case SrcType::Ty_Reg:
177  return Reg;
178  case SrcType::Ty_MIB:
179  return SrcMIB->getOperand(0).getReg();
180  }
181  llvm_unreachable("Unrecognised SrcOp::SrcType enum");
182  }
183 
185  switch (Ty) {
187  return Pred;
188  default:
189  llvm_unreachable("Not a register operand");
190  }
191  }
192 
193  int64_t getImm() const {
194  switch (Ty) {
195  case SrcType::Ty_Imm:
196  return Imm;
197  default:
198  llvm_unreachable("Not an immediate");
199  }
200  }
201 
202  SrcType getSrcOpKind() const { return Ty; }
203 
204 private:
205  SrcType Ty;
206 };
207 
208 class FlagsOp {
209  Optional<unsigned> Flags;
210 
211 public:
212  explicit FlagsOp(unsigned F) : Flags(F) {}
213  FlagsOp() : Flags(None) {}
214  Optional<unsigned> getFlags() const { return Flags; }
215 };
216 /// Helper class to build MachineInstr.
217 /// It keeps internally the insertion point and debug location for all
218 /// the new instructions we want to create.
219 /// This information can be modify via the related setters.
221 
222  MachineIRBuilderState State;
223 
224 protected:
225  void validateTruncExt(const LLT Dst, const LLT Src, bool IsExtend);
226 
227  void validateUnaryOp(const LLT Res, const LLT Op0);
228  void validateBinaryOp(const LLT Res, const LLT Op0, const LLT Op1);
229  void validateShiftOp(const LLT Res, const LLT Op0, const LLT Op1);
230 
231  void validateSelectOp(const LLT ResTy, const LLT TstTy, const LLT Op0Ty,
232  const LLT Op1Ty);
233 
234  void recordInsertion(MachineInstr *InsertedInstr) const {
235  if (State.Observer)
236  State.Observer->createdInstr(*InsertedInstr);
237  }
238 
239 public:
240  /// Some constructors for easy use.
241  MachineIRBuilder() = default;
243 
245  setMF(*MBB.getParent());
246  setInsertPt(MBB, InsPt);
247  }
248 
250  MachineIRBuilder(*MI.getParent(), MI.getIterator()) {
251  setInstr(MI);
252  setDebugLoc(MI.getDebugLoc());
253  }
254 
257  setChangeObserver(Observer);
258  }
259 
260  virtual ~MachineIRBuilder() = default;
261 
262  MachineIRBuilder(const MachineIRBuilderState &BState) : State(BState) {}
263 
265  assert(State.TII && "TargetInstrInfo is not set");
266  return *State.TII;
267  }
268 
269  /// Getter for the function we currently build.
271  assert(State.MF && "MachineFunction is not set");
272  return *State.MF;
273  }
274 
275  const MachineFunction &getMF() const {
276  assert(State.MF && "MachineFunction is not set");
277  return *State.MF;
278  }
279 
280  const DataLayout &getDataLayout() const {
281  return getMF().getFunction().getParent()->getDataLayout();
282  }
283 
284  /// Getter for DebugLoc
285  const DebugLoc &getDL() { return State.DL; }
286 
287  /// Getter for MRI
288  MachineRegisterInfo *getMRI() { return State.MRI; }
289  const MachineRegisterInfo *getMRI() const { return State.MRI; }
290 
291  /// Getter for the State
292  MachineIRBuilderState &getState() { return State; }
293 
294  /// Getter for the basic block we currently build.
295  const MachineBasicBlock &getMBB() const {
296  assert(State.MBB && "MachineBasicBlock is not set");
297  return *State.MBB;
298  }
299 
301  return const_cast<MachineBasicBlock &>(
302  const_cast<const MachineIRBuilder *>(this)->getMBB());
303  }
304 
305  GISelCSEInfo *getCSEInfo() { return State.CSEInfo; }
306  const GISelCSEInfo *getCSEInfo() const { return State.CSEInfo; }
307 
308  /// Current insertion point for new instructions.
310 
311  /// Set the insertion point before the specified position.
312  /// \pre MBB must be in getMF().
313  /// \pre II must be a valid iterator in MBB.
315  assert(MBB.getParent() == &getMF() &&
316  "Basic block is in a different function");
317  State.MBB = &MBB;
318  State.II = II;
319  }
320 
321  /// @}
322 
324 
325  /// \name Setters for the insertion point.
326  /// @{
327  /// Set the MachineFunction where to build instructions.
328  void setMF(MachineFunction &MF);
329 
330  /// Set the insertion point to the end of \p MBB.
331  /// \pre \p MBB must be contained by getMF().
333  State.MBB = &MBB;
334  State.II = MBB.end();
335  assert(&getMF() == MBB.getParent() &&
336  "Basic block is in a different function");
337  }
338 
339  /// Set the insertion point to before MI.
340  /// \pre MI must be in getMF().
342  assert(MI.getParent() && "Instruction is not part of a basic block");
343  setMBB(*MI.getParent());
344  State.II = MI.getIterator();
345  }
346  /// @}
347 
348  /// Set the insertion point to before MI, and set the debug loc to MI's loc.
349  /// \pre MI must be in getMF().
351  setInstr(MI);
352  setDebugLoc(MI.getDebugLoc());
353  }
354 
356  State.Observer = &Observer;
357  }
358 
359  void stopObservingChanges() { State.Observer = nullptr; }
360  /// @}
361 
362  /// Set the debug location to \p DL for all the next build instructions.
363  void setDebugLoc(const DebugLoc &DL) { this->State.DL = DL; }
364 
365  /// Get the current instruction's debug location.
366  DebugLoc getDebugLoc() { return State.DL; }
367 
368  /// Build and insert <empty> = \p Opcode <empty>.
369  /// The insertion point is the one set by the last call of either
370  /// setBasicBlock or setMI.
371  ///
372  /// \pre setBasicBlock or setMI must have been called.
373  ///
374  /// \return a MachineInstrBuilder for the newly created instruction.
375  MachineInstrBuilder buildInstr(unsigned Opcode) {
376  return insertInstr(buildInstrNoInsert(Opcode));
377  }
378 
379  /// Build but don't insert <empty> = \p Opcode <empty>.
380  ///
381  /// \pre setMF, setBasicBlock or setMI must have been called.
382  ///
383  /// \return a MachineInstrBuilder for the newly created instruction.
384  MachineInstrBuilder buildInstrNoInsert(unsigned Opcode);
385 
386  /// Insert an existing instruction at the insertion point.
388 
389  /// Build and insert a DBG_VALUE instruction expressing the fact that the
390  /// associated \p Variable lives in \p Reg (suitably modified by \p Expr).
392  const MDNode *Expr);
393 
394  /// Build and insert a DBG_VALUE instruction expressing the fact that the
395  /// associated \p Variable lives in memory at \p Reg (suitably modified by \p
396  /// Expr).
398  const MDNode *Variable,
399  const MDNode *Expr);
400 
401  /// Build and insert a DBG_VALUE instruction expressing the fact that the
402  /// associated \p Variable lives in the stack slot specified by \p FI
403  /// (suitably modified by \p Expr).
404  MachineInstrBuilder buildFIDbgValue(int FI, const MDNode *Variable,
405  const MDNode *Expr);
406 
407  /// Build and insert a DBG_VALUE instructions specifying that \p Variable is
408  /// given by \p C (suitably modified by \p Expr).
410  const MDNode *Variable,
411  const MDNode *Expr);
412 
413  /// Build and insert a DBG_LABEL instructions specifying that \p Label is
414  /// given. Convert "llvm.dbg.label Label" to "DBG_LABEL Label".
416 
417  /// Build and insert \p Res = G_DYN_STACKALLOC \p Size, \p Align
418  ///
419  /// G_DYN_STACKALLOC does a dynamic stack allocation and writes the address of
420  /// the allocated memory into \p Res.
421  /// \pre setBasicBlock or setMI must have been called.
422  /// \pre \p Res must be a generic virtual register with pointer type.
423  ///
424  /// \return a MachineInstrBuilder for the newly created instruction.
426  Align Alignment);
427 
428  /// Build and insert \p Res = G_FRAME_INDEX \p Idx
429  ///
430  /// G_FRAME_INDEX materializes the address of an alloca value or other
431  /// stack-based object.
432  ///
433  /// \pre setBasicBlock or setMI must have been called.
434  /// \pre \p Res must be a generic virtual register with pointer type.
435  ///
436  /// \return a MachineInstrBuilder for the newly created instruction.
437  MachineInstrBuilder buildFrameIndex(const DstOp &Res, int Idx);
438 
439  /// Build and insert \p Res = G_GLOBAL_VALUE \p GV
440  ///
441  /// G_GLOBAL_VALUE materializes the address of the specified global
442  /// into \p Res.
443  ///
444  /// \pre setBasicBlock or setMI must have been called.
445  /// \pre \p Res must be a generic virtual register with pointer type
446  /// in the same address space as \p GV.
447  ///
448  /// \return a MachineInstrBuilder for the newly created instruction.
449  MachineInstrBuilder buildGlobalValue(const DstOp &Res, const GlobalValue *GV);
450 
451  /// Build and insert \p Res = G_PTR_ADD \p Op0, \p Op1
452  ///
453  /// G_PTR_ADD adds \p Op1 addressible units to the pointer specified by \p Op0,
454  /// storing the resulting pointer in \p Res. Addressible units are typically
455  /// bytes but this can vary between targets.
456  ///
457  /// \pre setBasicBlock or setMI must have been called.
458  /// \pre \p Res and \p Op0 must be generic virtual registers with pointer
459  /// type.
460  /// \pre \p Op1 must be a generic virtual register with scalar type.
461  ///
462  /// \return a MachineInstrBuilder for the newly created instruction.
463  MachineInstrBuilder buildPtrAdd(const DstOp &Res, const SrcOp &Op0,
464  const SrcOp &Op1);
465 
466  /// Materialize and insert \p Res = G_PTR_ADD \p Op0, (G_CONSTANT \p Value)
467  ///
468  /// G_PTR_ADD adds \p Value bytes to the pointer specified by \p Op0,
469  /// storing the resulting pointer in \p Res. If \p Value is zero then no
470  /// G_PTR_ADD or G_CONSTANT will be created and \pre Op0 will be assigned to
471  /// \p Res.
472  ///
473  /// \pre setBasicBlock or setMI must have been called.
474  /// \pre \p Op0 must be a generic virtual register with pointer type.
475  /// \pre \p ValueTy must be a scalar type.
476  /// \pre \p Res must be 0. This is to detect confusion between
477  /// materializePtrAdd() and buildPtrAdd().
478  /// \post \p Res will either be a new generic virtual register of the same
479  /// type as \p Op0 or \p Op0 itself.
480  ///
481  /// \return a MachineInstrBuilder for the newly created instruction.
483  const LLT ValueTy,
484  uint64_t Value);
485 
486  /// Build and insert \p Res = G_PTRMASK \p Op0, \p Op1
487  MachineInstrBuilder buildPtrMask(const DstOp &Res, const SrcOp &Op0,
488  const SrcOp &Op1) {
489  return buildInstr(TargetOpcode::G_PTRMASK, {Res}, {Op0, Op1});
490  }
491 
492  /// Build and insert \p Res = G_PTRMASK \p Op0, \p G_CONSTANT (1 << NumBits) - 1
493  ///
494  /// This clears the low bits of a pointer operand without destroying its
495  /// pointer properties. This has the effect of rounding the address *down* to
496  /// a specified alignment in bits.
497  ///
498  /// \pre setBasicBlock or setMI must have been called.
499  /// \pre \p Res and \p Op0 must be generic virtual registers with pointer
500  /// type.
501  /// \pre \p NumBits must be an integer representing the number of low bits to
502  /// be cleared in \p Op0.
503  ///
504  /// \return a MachineInstrBuilder for the newly created instruction.
505  MachineInstrBuilder buildMaskLowPtrBits(const DstOp &Res, const SrcOp &Op0,
506  uint32_t NumBits);
507 
508  /// Build and insert \p Res, \p CarryOut = G_UADDO \p Op0, \p Op1
509  ///
510  /// G_UADDO sets \p Res to \p Op0 + \p Op1 (truncated to the bit width) and
511  /// sets \p CarryOut to 1 if the result overflowed in unsigned arithmetic.
512  ///
513  /// \pre setBasicBlock or setMI must have been called.
514  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers with the
515  /// same scalar type.
516  ////\pre \p CarryOut must be generic virtual register with scalar type
517  ///(typically s1)
518  ///
519  /// \return The newly created instruction.
520  MachineInstrBuilder buildUAddo(const DstOp &Res, const DstOp &CarryOut,
521  const SrcOp &Op0, const SrcOp &Op1) {
522  return buildInstr(TargetOpcode::G_UADDO, {Res, CarryOut}, {Op0, Op1});
523  }
524 
525  /// Build and insert \p Res, \p CarryOut = G_USUBO \p Op0, \p Op1
526  MachineInstrBuilder buildUSubo(const DstOp &Res, const DstOp &CarryOut,
527  const SrcOp &Op0, const SrcOp &Op1) {
528  return buildInstr(TargetOpcode::G_USUBO, {Res, CarryOut}, {Op0, Op1});
529  }
530 
531  /// Build and insert \p Res, \p CarryOut = G_SADDO \p Op0, \p Op1
532  MachineInstrBuilder buildSAddo(const DstOp &Res, const DstOp &CarryOut,
533  const SrcOp &Op0, const SrcOp &Op1) {
534  return buildInstr(TargetOpcode::G_SADDO, {Res, CarryOut}, {Op0, Op1});
535  }
536 
537  /// Build and insert \p Res, \p CarryOut = G_SUBO \p Op0, \p Op1
538  MachineInstrBuilder buildSSubo(const DstOp &Res, const DstOp &CarryOut,
539  const SrcOp &Op0, const SrcOp &Op1) {
540  return buildInstr(TargetOpcode::G_SSUBO, {Res, CarryOut}, {Op0, Op1});
541  }
542 
543  /// Build and insert \p Res, \p CarryOut = G_UADDE \p Op0,
544  /// \p Op1, \p CarryIn
545  ///
546  /// G_UADDE sets \p Res to \p Op0 + \p Op1 + \p CarryIn (truncated to the bit
547  /// width) and sets \p CarryOut to 1 if the result overflowed in unsigned
548  /// arithmetic.
549  ///
550  /// \pre setBasicBlock or setMI must have been called.
551  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
552  /// with the same scalar type.
553  /// \pre \p CarryOut and \p CarryIn must be generic virtual
554  /// registers with the same scalar type (typically s1)
555  ///
556  /// \return The newly created instruction.
557  MachineInstrBuilder buildUAdde(const DstOp &Res, const DstOp &CarryOut,
558  const SrcOp &Op0, const SrcOp &Op1,
559  const SrcOp &CarryIn) {
560  return buildInstr(TargetOpcode::G_UADDE, {Res, CarryOut},
561  {Op0, Op1, CarryIn});
562  }
563 
564  /// Build and insert \p Res, \p CarryOut = G_USUBE \p Op0, \p Op1, \p CarryInp
565  MachineInstrBuilder buildUSube(const DstOp &Res, const DstOp &CarryOut,
566  const SrcOp &Op0, const SrcOp &Op1,
567  const SrcOp &CarryIn) {
568  return buildInstr(TargetOpcode::G_USUBE, {Res, CarryOut},
569  {Op0, Op1, CarryIn});
570  }
571 
572  /// Build and insert \p Res, \p CarryOut = G_SADDE \p Op0, \p Op1, \p CarryInp
573  MachineInstrBuilder buildSAdde(const DstOp &Res, const DstOp &CarryOut,
574  const SrcOp &Op0, const SrcOp &Op1,
575  const SrcOp &CarryIn) {
576  return buildInstr(TargetOpcode::G_SADDE, {Res, CarryOut},
577  {Op0, Op1, CarryIn});
578  }
579 
580  /// Build and insert \p Res, \p CarryOut = G_SSUBE \p Op0, \p Op1, \p CarryInp
581  MachineInstrBuilder buildSSube(const DstOp &Res, const DstOp &CarryOut,
582  const SrcOp &Op0, const SrcOp &Op1,
583  const SrcOp &CarryIn) {
584  return buildInstr(TargetOpcode::G_SSUBE, {Res, CarryOut},
585  {Op0, Op1, CarryIn});
586  }
587 
588  /// Build and insert \p Res = G_ANYEXT \p Op0
589  ///
590  /// G_ANYEXT produces a register of the specified width, with bits 0 to
591  /// sizeof(\p Ty) * 8 set to \p Op. The remaining bits are unspecified
592  /// (i.e. this is neither zero nor sign-extension). For a vector register,
593  /// each element is extended individually.
594  ///
595  /// \pre setBasicBlock or setMI must have been called.
596  /// \pre \p Res must be a generic virtual register with scalar or vector type.
597  /// \pre \p Op must be a generic virtual register with scalar or vector type.
598  /// \pre \p Op must be smaller than \p Res
599  ///
600  /// \return The newly created instruction.
601 
602  MachineInstrBuilder buildAnyExt(const DstOp &Res, const SrcOp &Op);
603 
604  /// Build and insert \p Res = G_SEXT \p Op
605  ///
606  /// G_SEXT produces a register of the specified width, with bits 0 to
607  /// sizeof(\p Ty) * 8 set to \p Op. The remaining bits are duplicated from the
608  /// high bit of \p Op (i.e. 2s-complement sign extended).
609  ///
610  /// \pre setBasicBlock or setMI must have been called.
611  /// \pre \p Res must be a generic virtual register with scalar or vector type.
612  /// \pre \p Op must be a generic virtual register with scalar or vector type.
613  /// \pre \p Op must be smaller than \p Res
614  ///
615  /// \return The newly created instruction.
616  MachineInstrBuilder buildSExt(const DstOp &Res, const SrcOp &Op);
617 
618  /// Build and insert \p Res = G_SEXT_INREG \p Op, ImmOp
619  MachineInstrBuilder buildSExtInReg(const DstOp &Res, const SrcOp &Op, int64_t ImmOp) {
620  return buildInstr(TargetOpcode::G_SEXT_INREG, {Res}, {Op, SrcOp(ImmOp)});
621  }
622 
623  /// Build and insert \p Res = G_FPEXT \p Op
625  Optional<unsigned> Flags = None) {
626  return buildInstr(TargetOpcode::G_FPEXT, {Res}, {Op}, Flags);
627  }
628 
629 
630  /// Build and insert a G_PTRTOINT instruction.
631  MachineInstrBuilder buildPtrToInt(const DstOp &Dst, const SrcOp &Src) {
632  return buildInstr(TargetOpcode::G_PTRTOINT, {Dst}, {Src});
633  }
634 
635  /// Build and insert a G_INTTOPTR instruction.
636  MachineInstrBuilder buildIntToPtr(const DstOp &Dst, const SrcOp &Src) {
637  return buildInstr(TargetOpcode::G_INTTOPTR, {Dst}, {Src});
638  }
639 
640  /// Build and insert \p Dst = G_BITCAST \p Src
641  MachineInstrBuilder buildBitcast(const DstOp &Dst, const SrcOp &Src) {
642  return buildInstr(TargetOpcode::G_BITCAST, {Dst}, {Src});
643  }
644 
645  /// Build and insert \p Dst = G_ADDRSPACE_CAST \p Src
647  return buildInstr(TargetOpcode::G_ADDRSPACE_CAST, {Dst}, {Src});
648  }
649 
650  /// \return The opcode of the extension the target wants to use for boolean
651  /// values.
652  unsigned getBoolExtOp(bool IsVec, bool IsFP) const;
653 
654  // Build and insert \p Res = G_ANYEXT \p Op, \p Res = G_SEXT \p Op, or \p Res
655  // = G_ZEXT \p Op depending on how the target wants to extend boolean values.
656  MachineInstrBuilder buildBoolExt(const DstOp &Res, const SrcOp &Op,
657  bool IsFP);
658 
659  /// Build and insert \p Res = G_ZEXT \p Op
660  ///
661  /// G_ZEXT produces a register of the specified width, with bits 0 to
662  /// sizeof(\p Ty) * 8 set to \p Op. The remaining bits are 0. For a vector
663  /// register, each element is extended individually.
664  ///
665  /// \pre setBasicBlock or setMI must have been called.
666  /// \pre \p Res must be a generic virtual register with scalar or vector type.
667  /// \pre \p Op must be a generic virtual register with scalar or vector type.
668  /// \pre \p Op must be smaller than \p Res
669  ///
670  /// \return The newly created instruction.
671  MachineInstrBuilder buildZExt(const DstOp &Res, const SrcOp &Op);
672 
673  /// Build and insert \p Res = G_SEXT \p Op, \p Res = G_TRUNC \p Op, or
674  /// \p Res = COPY \p Op depending on the differing sizes of \p Res and \p Op.
675  /// ///
676  /// \pre setBasicBlock or setMI must have been called.
677  /// \pre \p Res must be a generic virtual register with scalar or vector type.
678  /// \pre \p Op must be a generic virtual register with scalar or vector type.
679  ///
680  /// \return The newly created instruction.
681  MachineInstrBuilder buildSExtOrTrunc(const DstOp &Res, const SrcOp &Op);
682 
683  /// Build and insert \p Res = G_ZEXT \p Op, \p Res = G_TRUNC \p Op, or
684  /// \p Res = COPY \p Op depending on the differing sizes of \p Res and \p Op.
685  /// ///
686  /// \pre setBasicBlock or setMI must have been called.
687  /// \pre \p Res must be a generic virtual register with scalar or vector type.
688  /// \pre \p Op must be a generic virtual register with scalar or vector type.
689  ///
690  /// \return The newly created instruction.
691  MachineInstrBuilder buildZExtOrTrunc(const DstOp &Res, const SrcOp &Op);
692 
693  // Build and insert \p Res = G_ANYEXT \p Op, \p Res = G_TRUNC \p Op, or
694  /// \p Res = COPY \p Op depending on the differing sizes of \p Res and \p Op.
695  /// ///
696  /// \pre setBasicBlock or setMI must have been called.
697  /// \pre \p Res must be a generic virtual register with scalar or vector type.
698  /// \pre \p Op must be a generic virtual register with scalar or vector type.
699  ///
700  /// \return The newly created instruction.
702 
703  /// Build and insert \p Res = \p ExtOpc, \p Res = G_TRUNC \p
704  /// Op, or \p Res = COPY \p Op depending on the differing sizes of \p Res and
705  /// \p Op.
706  /// ///
707  /// \pre setBasicBlock or setMI must have been called.
708  /// \pre \p Res must be a generic virtual register with scalar or vector type.
709  /// \pre \p Op must be a generic virtual register with scalar or vector type.
710  ///
711  /// \return The newly created instruction.
712  MachineInstrBuilder buildExtOrTrunc(unsigned ExtOpc, const DstOp &Res,
713  const SrcOp &Op);
714 
715  /// Build and inserts \p Res = \p G_AND \p Op, \p LowBitsSet(ImmOp)
716  /// Since there is no G_ZEXT_INREG like G_SEXT_INREG, the instruction is
717  /// emulated using G_AND.
718  MachineInstrBuilder buildZExtInReg(const DstOp &Res, const SrcOp &Op,
719  int64_t ImmOp);
720 
721  /// Build and insert an appropriate cast between two registers of equal size.
722  MachineInstrBuilder buildCast(const DstOp &Dst, const SrcOp &Src);
723 
724  /// Build and insert G_BR \p Dest
725  ///
726  /// G_BR is an unconditional branch to \p Dest.
727  ///
728  /// \pre setBasicBlock or setMI must have been called.
729  ///
730  /// \return a MachineInstrBuilder for the newly created instruction.
732 
733  /// Build and insert G_BRCOND \p Tst, \p Dest
734  ///
735  /// G_BRCOND is a conditional branch to \p Dest.
736  ///
737  /// \pre setBasicBlock or setMI must have been called.
738  /// \pre \p Tst must be a generic virtual register with scalar
739  /// type. At the beginning of legalization, this will be a single
740  /// bit (s1). Targets with interesting flags registers may change
741  /// this. For a wider type, whether the branch is taken must only
742  /// depend on bit 0 (for now).
743  ///
744  /// \return The newly created instruction.
746 
747  /// Build and insert G_BRINDIRECT \p Tgt
748  ///
749  /// G_BRINDIRECT is an indirect branch to \p Tgt.
750  ///
751  /// \pre setBasicBlock or setMI must have been called.
752  /// \pre \p Tgt must be a generic virtual register with pointer type.
753  ///
754  /// \return a MachineInstrBuilder for the newly created instruction.
756 
757  /// Build and insert G_BRJT \p TablePtr, \p JTI, \p IndexReg
758  ///
759  /// G_BRJT is a jump table branch using a table base pointer \p TablePtr,
760  /// jump table index \p JTI and index \p IndexReg
761  ///
762  /// \pre setBasicBlock or setMI must have been called.
763  /// \pre \p TablePtr must be a generic virtual register with pointer type.
764  /// \pre \p JTI must be be a jump table index.
765  /// \pre \p IndexReg must be a generic virtual register with pointer type.
766  ///
767  /// \return a MachineInstrBuilder for the newly created instruction.
768  MachineInstrBuilder buildBrJT(Register TablePtr, unsigned JTI,
769  Register IndexReg);
770 
771  /// Build and insert \p Res = G_CONSTANT \p Val
772  ///
773  /// G_CONSTANT is an integer constant with the specified size and value. \p
774  /// Val will be extended or truncated to the size of \p Reg.
775  ///
776  /// \pre setBasicBlock or setMI must have been called.
777  /// \pre \p Res must be a generic virtual register with scalar or pointer
778  /// type.
779  ///
780  /// \return The newly created instruction.
781  virtual MachineInstrBuilder buildConstant(const DstOp &Res,
782  const ConstantInt &Val);
783 
784  /// Build and insert \p Res = G_CONSTANT \p Val
785  ///
786  /// G_CONSTANT is an integer constant with the specified size and value.
787  ///
788  /// \pre setBasicBlock or setMI must have been called.
789  /// \pre \p Res must be a generic virtual register with scalar type.
790  ///
791  /// \return The newly created instruction.
792  MachineInstrBuilder buildConstant(const DstOp &Res, int64_t Val);
793  MachineInstrBuilder buildConstant(const DstOp &Res, const APInt &Val);
794 
795  /// Build and insert \p Res = G_FCONSTANT \p Val
796  ///
797  /// G_FCONSTANT is a floating-point constant with the specified size and
798  /// value.
799  ///
800  /// \pre setBasicBlock or setMI must have been called.
801  /// \pre \p Res must be a generic virtual register with scalar type.
802  ///
803  /// \return The newly created instruction.
804  virtual MachineInstrBuilder buildFConstant(const DstOp &Res,
805  const ConstantFP &Val);
806 
807  MachineInstrBuilder buildFConstant(const DstOp &Res, double Val);
808  MachineInstrBuilder buildFConstant(const DstOp &Res, const APFloat &Val);
809 
810  /// Build and insert \p Res = COPY Op
811  ///
812  /// Register-to-register COPY sets \p Res to \p Op.
813  ///
814  /// \pre setBasicBlock or setMI must have been called.
815  ///
816  /// \return a MachineInstrBuilder for the newly created instruction.
817  MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op);
818 
819  /// Build and insert \p Res = G_ASSERT_ZEXT Op, Size
820  ///
821  /// \return a MachineInstrBuilder for the newly created instruction.
822  MachineInstrBuilder buildAssertZExt(const DstOp &Res, const SrcOp &Op,
823  unsigned Size);
824 
825  /// Build and insert \p Res = G_ASSERT_SEXT Op, Size
826  ///
827  /// \return a MachineInstrBuilder for the newly created instruction.
828  MachineInstrBuilder buildAssertSExt(const DstOp &Res, const SrcOp &Op,
829  unsigned Size);
830 
831  /// Build and insert `Res = G_LOAD Addr, MMO`.
832  ///
833  /// Loads the value stored at \p Addr. Puts the result in \p Res.
834  ///
835  /// \pre setBasicBlock or setMI must have been called.
836  /// \pre \p Res must be a generic virtual register.
837  /// \pre \p Addr must be a generic virtual register with pointer type.
838  ///
839  /// \return a MachineInstrBuilder for the newly created instruction.
841  MachineMemOperand &MMO) {
842  return buildLoadInstr(TargetOpcode::G_LOAD, Res, Addr, MMO);
843  }
844 
845  /// Build and insert a G_LOAD instruction, while constructing the
846  /// MachineMemOperand.
848  buildLoad(const DstOp &Res, const SrcOp &Addr, MachinePointerInfo PtrInfo,
849  Align Alignment,
851  const AAMDNodes &AAInfo = AAMDNodes());
852 
853  /// Build and insert `Res = <opcode> Addr, MMO`.
854  ///
855  /// Loads the value stored at \p Addr. Puts the result in \p Res.
856  ///
857  /// \pre setBasicBlock or setMI must have been called.
858  /// \pre \p Res must be a generic virtual register.
859  /// \pre \p Addr must be a generic virtual register with pointer type.
860  ///
861  /// \return a MachineInstrBuilder for the newly created instruction.
862  MachineInstrBuilder buildLoadInstr(unsigned Opcode, const DstOp &Res,
863  const SrcOp &Addr, MachineMemOperand &MMO);
864 
865  /// Helper to create a load from a constant offset given a base address. Load
866  /// the type of \p Dst from \p Offset from the given base address and memory
867  /// operand.
869  const SrcOp &BasePtr,
870  MachineMemOperand &BaseMMO,
871  int64_t Offset);
872 
873  /// Build and insert `G_STORE Val, Addr, MMO`.
874  ///
875  /// Stores the value \p Val to \p Addr.
876  ///
877  /// \pre setBasicBlock or setMI must have been called.
878  /// \pre \p Val must be a generic virtual register.
879  /// \pre \p Addr must be a generic virtual register with pointer type.
880  ///
881  /// \return a MachineInstrBuilder for the newly created instruction.
882  MachineInstrBuilder buildStore(const SrcOp &Val, const SrcOp &Addr,
883  MachineMemOperand &MMO);
884 
885  /// Build and insert a G_STORE instruction, while constructing the
886  /// MachineMemOperand.
888  buildStore(const SrcOp &Val, const SrcOp &Addr, MachinePointerInfo PtrInfo,
889  Align Alignment,
891  const AAMDNodes &AAInfo = AAMDNodes());
892 
893  /// Build and insert `Res0, ... = G_EXTRACT Src, Idx0`.
894  ///
895  /// \pre setBasicBlock or setMI must have been called.
896  /// \pre \p Res and \p Src must be generic virtual registers.
897  ///
898  /// \return a MachineInstrBuilder for the newly created instruction.
899  MachineInstrBuilder buildExtract(const DstOp &Res, const SrcOp &Src, uint64_t Index);
900 
901  /// Build and insert \p Res = IMPLICIT_DEF.
903 
904  /// Build and insert instructions to put \p Ops together at the specified p
905  /// Indices to form a larger register.
906  ///
907  /// If the types of the input registers are uniform and cover the entirity of
908  /// \p Res then a G_MERGE_VALUES will be produced. Otherwise an IMPLICIT_DEF
909  /// followed by a sequence of G_INSERT instructions.
910  ///
911  /// \pre setBasicBlock or setMI must have been called.
912  /// \pre The final element of the sequence must not extend past the end of the
913  /// destination register.
914  /// \pre The bits defined by each Op (derived from index and scalar size) must
915  /// not overlap.
916  /// \pre \p Indices must be in ascending order of bit position.
918  ArrayRef<uint64_t> Indices);
919 
920  /// Build and insert \p Res = G_MERGE_VALUES \p Op0, ...
921  ///
922  /// G_MERGE_VALUES combines the input elements contiguously into a larger
923  /// register.
924  ///
925  /// \pre setBasicBlock or setMI must have been called.
926  /// \pre The entire register \p Res (and no more) must be covered by the input
927  /// registers.
928  /// \pre The type of all \p Ops registers must be identical.
929  ///
930  /// \return a MachineInstrBuilder for the newly created instruction.
933  std::initializer_list<SrcOp> Ops);
934 
935  /// Build and insert \p Res0, ... = G_UNMERGE_VALUES \p Op
936  ///
937  /// G_UNMERGE_VALUES splits contiguous bits of the input into multiple
938  ///
939  /// \pre setBasicBlock or setMI must have been called.
940  /// \pre The entire register \p Res (and no more) must be covered by the input
941  /// registers.
942  /// \pre The type of all \p Res registers must be identical.
943  ///
944  /// \return a MachineInstrBuilder for the newly created instruction.
947 
948  /// Build and insert an unmerge of \p Res sized pieces to cover \p Op
950 
951  /// Build and insert \p Res = G_BUILD_VECTOR \p Op0, ...
952  ///
953  /// G_BUILD_VECTOR creates a vector value from multiple scalar registers.
954  /// \pre setBasicBlock or setMI must have been called.
955  /// \pre The entire register \p Res (and no more) must be covered by the
956  /// input scalar registers.
957  /// \pre The type of all \p Ops registers must be identical.
958  ///
959  /// \return a MachineInstrBuilder for the newly created instruction.
961  ArrayRef<Register> Ops);
962 
963  /// Build and insert \p Res = G_BUILD_VECTOR with \p Src replicated to fill
964  /// the number of elements
966  const SrcOp &Src);
967 
968  /// Build and insert \p Res = G_BUILD_VECTOR_TRUNC \p Op0, ...
969  ///
970  /// G_BUILD_VECTOR_TRUNC creates a vector value from multiple scalar registers
971  /// which have types larger than the destination vector element type, and
972  /// truncates the values to fit.
973  ///
974  /// If the operands given are already the same size as the vector elt type,
975  /// then this method will instead create a G_BUILD_VECTOR instruction.
976  ///
977  /// \pre setBasicBlock or setMI must have been called.
978  /// \pre The type of all \p Ops registers must be identical.
979  ///
980  /// \return a MachineInstrBuilder for the newly created instruction.
982  ArrayRef<Register> Ops);
983 
984  /// Build and insert a vector splat of a scalar \p Src using a
985  /// G_INSERT_VECTOR_ELT and G_SHUFFLE_VECTOR idiom.
986  ///
987  /// \pre setBasicBlock or setMI must have been called.
988  /// \pre \p Src must have the same type as the element type of \p Dst
989  ///
990  /// \return a MachineInstrBuilder for the newly created instruction.
991  MachineInstrBuilder buildShuffleSplat(const DstOp &Res, const SrcOp &Src);
992 
993  /// Build and insert \p Res = G_SHUFFLE_VECTOR \p Src1, \p Src2, \p Mask
994  ///
995  /// \pre setBasicBlock or setMI must have been called.
996  ///
997  /// \return a MachineInstrBuilder for the newly created instruction.
998  MachineInstrBuilder buildShuffleVector(const DstOp &Res, const SrcOp &Src1,
999  const SrcOp &Src2, ArrayRef<int> Mask);
1000 
1001  /// Build and insert \p Res = G_CONCAT_VECTORS \p Op0, ...
1002  ///
1003  /// G_CONCAT_VECTORS creates a vector from the concatenation of 2 or more
1004  /// vectors.
1005  ///
1006  /// \pre setBasicBlock or setMI must have been called.
1007  /// \pre The entire register \p Res (and no more) must be covered by the input
1008  /// registers.
1009  /// \pre The type of all source operands must be identical.
1010  ///
1011  /// \return a MachineInstrBuilder for the newly created instruction.
1013  ArrayRef<Register> Ops);
1014 
1015  MachineInstrBuilder buildInsert(const DstOp &Res, const SrcOp &Src,
1016  const SrcOp &Op, unsigned Index);
1017 
1018  /// Build and insert either a G_INTRINSIC (if \p HasSideEffects is false) or
1019  /// G_INTRINSIC_W_SIDE_EFFECTS instruction. Its first operand will be the
1020  /// result register definition unless \p Reg is NoReg (== 0). The second
1021  /// operand will be the intrinsic's ID.
1022  ///
1023  /// Callers are expected to add the required definitions and uses afterwards.
1024  ///
1025  /// \pre setBasicBlock or setMI must have been called.
1026  ///
1027  /// \return a MachineInstrBuilder for the newly created instruction.
1029  bool HasSideEffects);
1031  bool HasSideEffects);
1032 
1033  /// Build and insert \p Res = G_FPTRUNC \p Op
1034  ///
1035  /// G_FPTRUNC converts a floating-point value into one with a smaller type.
1036  ///
1037  /// \pre setBasicBlock or setMI must have been called.
1038  /// \pre \p Res must be a generic virtual register with scalar or vector type.
1039  /// \pre \p Op must be a generic virtual register with scalar or vector type.
1040  /// \pre \p Res must be smaller than \p Op
1041  ///
1042  /// \return The newly created instruction.
1043  MachineInstrBuilder buildFPTrunc(const DstOp &Res, const SrcOp &Op,
1044  Optional<unsigned> Flags = None);
1045 
1046  /// Build and insert \p Res = G_TRUNC \p Op
1047  ///
1048  /// G_TRUNC extracts the low bits of a type. For a vector type each element is
1049  /// truncated independently before being packed into the destination.
1050  ///
1051  /// \pre setBasicBlock or setMI must have been called.
1052  /// \pre \p Res must be a generic virtual register with scalar or vector type.
1053  /// \pre \p Op must be a generic virtual register with scalar or vector type.
1054  /// \pre \p Res must be smaller than \p Op
1055  ///
1056  /// \return The newly created instruction.
1057  MachineInstrBuilder buildTrunc(const DstOp &Res, const SrcOp &Op);
1058 
1059  /// Build and insert a \p Res = G_ICMP \p Pred, \p Op0, \p Op1
1060  ///
1061  /// \pre setBasicBlock or setMI must have been called.
1062 
1063  /// \pre \p Res must be a generic virtual register with scalar or
1064  /// vector type. Typically this starts as s1 or <N x s1>.
1065  /// \pre \p Op0 and Op1 must be generic virtual registers with the
1066  /// same number of elements as \p Res. If \p Res is a scalar,
1067  /// \p Op0 must be either a scalar or pointer.
1068  /// \pre \p Pred must be an integer predicate.
1069  ///
1070  /// \return a MachineInstrBuilder for the newly created instruction.
1072  const SrcOp &Op0, const SrcOp &Op1);
1073 
1074  /// Build and insert a \p Res = G_FCMP \p Pred\p Op0, \p Op1
1075  ///
1076  /// \pre setBasicBlock or setMI must have been called.
1077 
1078  /// \pre \p Res must be a generic virtual register with scalar or
1079  /// vector type. Typically this starts as s1 or <N x s1>.
1080  /// \pre \p Op0 and Op1 must be generic virtual registers with the
1081  /// same number of elements as \p Res (or scalar, if \p Res is
1082  /// scalar).
1083  /// \pre \p Pred must be a floating-point predicate.
1084  ///
1085  /// \return a MachineInstrBuilder for the newly created instruction.
1087  const SrcOp &Op0, const SrcOp &Op1,
1088  Optional<unsigned> Flags = None);
1089 
1090  /// Build and insert a \p Res = G_SELECT \p Tst, \p Op0, \p Op1
1091  ///
1092  /// \pre setBasicBlock or setMI must have been called.
1093  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1094  /// with the same type.
1095  /// \pre \p Tst must be a generic virtual register with scalar, pointer or
1096  /// vector type. If vector then it must have the same number of
1097  /// elements as the other parameters.
1098  ///
1099  /// \return a MachineInstrBuilder for the newly created instruction.
1100  MachineInstrBuilder buildSelect(const DstOp &Res, const SrcOp &Tst,
1101  const SrcOp &Op0, const SrcOp &Op1,
1102  Optional<unsigned> Flags = None);
1103 
1104  /// Build and insert \p Res = G_INSERT_VECTOR_ELT \p Val,
1105  /// \p Elt, \p Idx
1106  ///
1107  /// \pre setBasicBlock or setMI must have been called.
1108  /// \pre \p Res and \p Val must be a generic virtual register
1109  // with the same vector type.
1110  /// \pre \p Elt and \p Idx must be a generic virtual register
1111  /// with scalar type.
1112  ///
1113  /// \return The newly created instruction.
1115  const SrcOp &Val,
1116  const SrcOp &Elt,
1117  const SrcOp &Idx);
1118 
1119  /// Build and insert \p Res = G_EXTRACT_VECTOR_ELT \p Val, \p Idx
1120  ///
1121  /// \pre setBasicBlock or setMI must have been called.
1122  /// \pre \p Res must be a generic virtual register with scalar type.
1123  /// \pre \p Val must be a generic virtual register with vector type.
1124  /// \pre \p Idx must be a generic virtual register with scalar type.
1125  ///
1126  /// \return The newly created instruction.
1128  const SrcOp &Val,
1129  const SrcOp &Idx);
1130 
1131  /// Build and insert `OldValRes<def>, SuccessRes<def> =
1132  /// G_ATOMIC_CMPXCHG_WITH_SUCCESS Addr, CmpVal, NewVal, MMO`.
1133  ///
1134  /// Atomically replace the value at \p Addr with \p NewVal if it is currently
1135  /// \p CmpVal otherwise leaves it unchanged. Puts the original value from \p
1136  /// Addr in \p Res, along with an s1 indicating whether it was replaced.
1137  ///
1138  /// \pre setBasicBlock or setMI must have been called.
1139  /// \pre \p OldValRes must be a generic virtual register of scalar type.
1140  /// \pre \p SuccessRes must be a generic virtual register of scalar type. It
1141  /// will be assigned 0 on failure and 1 on success.
1142  /// \pre \p Addr must be a generic virtual register with pointer type.
1143  /// \pre \p OldValRes, \p CmpVal, and \p NewVal must be generic virtual
1144  /// registers of the same type.
1145  ///
1146  /// \return a MachineInstrBuilder for the newly created instruction.
1148  buildAtomicCmpXchgWithSuccess(Register OldValRes, Register SuccessRes,
1149  Register Addr, Register CmpVal, Register NewVal,
1150  MachineMemOperand &MMO);
1151 
1152  /// Build and insert `OldValRes<def> = G_ATOMIC_CMPXCHG Addr, CmpVal, NewVal,
1153  /// MMO`.
1154  ///
1155  /// Atomically replace the value at \p Addr with \p NewVal if it is currently
1156  /// \p CmpVal otherwise leaves it unchanged. Puts the original value from \p
1157  /// Addr in \p Res.
1158  ///
1159  /// \pre setBasicBlock or setMI must have been called.
1160  /// \pre \p OldValRes must be a generic virtual register of scalar type.
1161  /// \pre \p Addr must be a generic virtual register with pointer type.
1162  /// \pre \p OldValRes, \p CmpVal, and \p NewVal must be generic virtual
1163  /// registers of the same type.
1164  ///
1165  /// \return a MachineInstrBuilder for the newly created instruction.
1167  Register CmpVal, Register NewVal,
1168  MachineMemOperand &MMO);
1169 
1170  /// Build and insert `OldValRes<def> = G_ATOMICRMW_<Opcode> Addr, Val, MMO`.
1171  ///
1172  /// Atomically read-modify-update the value at \p Addr with \p Val. Puts the
1173  /// original value from \p Addr in \p OldValRes. The modification is
1174  /// determined by the opcode.
1175  ///
1176  /// \pre setBasicBlock or setMI must have been called.
1177  /// \pre \p OldValRes must be a generic virtual register.
1178  /// \pre \p Addr must be a generic virtual register with pointer type.
1179  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1180  /// same type.
1181  ///
1182  /// \return a MachineInstrBuilder for the newly created instruction.
1183  MachineInstrBuilder buildAtomicRMW(unsigned Opcode, const DstOp &OldValRes,
1184  const SrcOp &Addr, const SrcOp &Val,
1185  MachineMemOperand &MMO);
1186 
1187  /// Build and insert `OldValRes<def> = G_ATOMICRMW_XCHG Addr, Val, MMO`.
1188  ///
1189  /// Atomically replace the value at \p Addr with \p Val. Puts the original
1190  /// value from \p Addr in \p OldValRes.
1191  ///
1192  /// \pre setBasicBlock or setMI must have been called.
1193  /// \pre \p OldValRes must be a generic virtual register.
1194  /// \pre \p Addr must be a generic virtual register with pointer type.
1195  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1196  /// same type.
1197  ///
1198  /// \return a MachineInstrBuilder for the newly created instruction.
1200  Register Val, MachineMemOperand &MMO);
1201 
1202  /// Build and insert `OldValRes<def> = G_ATOMICRMW_ADD Addr, Val, MMO`.
1203  ///
1204  /// Atomically replace the value at \p Addr with the addition of \p Val and
1205  /// the original value. Puts the original value from \p Addr in \p OldValRes.
1206  ///
1207  /// \pre setBasicBlock or setMI must have been called.
1208  /// \pre \p OldValRes must be a generic virtual register.
1209  /// \pre \p Addr must be a generic virtual register with pointer type.
1210  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1211  /// same type.
1212  ///
1213  /// \return a MachineInstrBuilder for the newly created instruction.
1215  Register Val, MachineMemOperand &MMO);
1216 
1217  /// Build and insert `OldValRes<def> = G_ATOMICRMW_SUB Addr, Val, MMO`.
1218  ///
1219  /// Atomically replace the value at \p Addr with the subtraction of \p Val and
1220  /// the original value. Puts the original value from \p Addr in \p OldValRes.
1221  ///
1222  /// \pre setBasicBlock or setMI must have been called.
1223  /// \pre \p OldValRes must be a generic virtual register.
1224  /// \pre \p Addr must be a generic virtual register with pointer type.
1225  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1226  /// same type.
1227  ///
1228  /// \return a MachineInstrBuilder for the newly created instruction.
1230  Register Val, MachineMemOperand &MMO);
1231 
1232  /// Build and insert `OldValRes<def> = G_ATOMICRMW_AND Addr, Val, MMO`.
1233  ///
1234  /// Atomically replace the value at \p Addr with the bitwise and of \p Val and
1235  /// the original value. Puts the original value from \p Addr in \p OldValRes.
1236  ///
1237  /// \pre setBasicBlock or setMI must have been called.
1238  /// \pre \p OldValRes must be a generic virtual register.
1239  /// \pre \p Addr must be a generic virtual register with pointer type.
1240  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1241  /// same type.
1242  ///
1243  /// \return a MachineInstrBuilder for the newly created instruction.
1245  Register Val, MachineMemOperand &MMO);
1246 
1247  /// Build and insert `OldValRes<def> = G_ATOMICRMW_NAND Addr, Val, MMO`.
1248  ///
1249  /// Atomically replace the value at \p Addr with the bitwise nand of \p Val
1250  /// and the original value. Puts the original value from \p Addr in \p
1251  /// OldValRes.
1252  ///
1253  /// \pre setBasicBlock or setMI must have been called.
1254  /// \pre \p OldValRes must be a generic virtual register.
1255  /// \pre \p Addr must be a generic virtual register with pointer type.
1256  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1257  /// same type.
1258  ///
1259  /// \return a MachineInstrBuilder for the newly created instruction.
1261  Register Val, MachineMemOperand &MMO);
1262 
1263  /// Build and insert `OldValRes<def> = G_ATOMICRMW_OR Addr, Val, MMO`.
1264  ///
1265  /// Atomically replace the value at \p Addr with the bitwise or of \p Val and
1266  /// the original value. Puts the original value from \p Addr in \p OldValRes.
1267  ///
1268  /// \pre setBasicBlock or setMI must have been called.
1269  /// \pre \p OldValRes must be a generic virtual register.
1270  /// \pre \p Addr must be a generic virtual register with pointer type.
1271  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1272  /// same type.
1273  ///
1274  /// \return a MachineInstrBuilder for the newly created instruction.
1276  Register Val, MachineMemOperand &MMO);
1277 
1278  /// Build and insert `OldValRes<def> = G_ATOMICRMW_XOR Addr, Val, MMO`.
1279  ///
1280  /// Atomically replace the value at \p Addr with the bitwise xor of \p Val and
1281  /// the original value. Puts the original value from \p Addr in \p OldValRes.
1282  ///
1283  /// \pre setBasicBlock or setMI must have been called.
1284  /// \pre \p OldValRes must be a generic virtual register.
1285  /// \pre \p Addr must be a generic virtual register with pointer type.
1286  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1287  /// same type.
1288  ///
1289  /// \return a MachineInstrBuilder for the newly created instruction.
1291  Register Val, MachineMemOperand &MMO);
1292 
1293  /// Build and insert `OldValRes<def> = G_ATOMICRMW_MAX Addr, Val, MMO`.
1294  ///
1295  /// Atomically replace the value at \p Addr with the signed maximum of \p
1296  /// Val and the original value. Puts the original value from \p Addr in \p
1297  /// OldValRes.
1298  ///
1299  /// \pre setBasicBlock or setMI must have been called.
1300  /// \pre \p OldValRes must be a generic virtual register.
1301  /// \pre \p Addr must be a generic virtual register with pointer type.
1302  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1303  /// same type.
1304  ///
1305  /// \return a MachineInstrBuilder for the newly created instruction.
1307  Register Val, MachineMemOperand &MMO);
1308 
1309  /// Build and insert `OldValRes<def> = G_ATOMICRMW_MIN Addr, Val, MMO`.
1310  ///
1311  /// Atomically replace the value at \p Addr with the signed minimum of \p
1312  /// Val and the original value. Puts the original value from \p Addr in \p
1313  /// OldValRes.
1314  ///
1315  /// \pre setBasicBlock or setMI must have been called.
1316  /// \pre \p OldValRes must be a generic virtual register.
1317  /// \pre \p Addr must be a generic virtual register with pointer type.
1318  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1319  /// same type.
1320  ///
1321  /// \return a MachineInstrBuilder for the newly created instruction.
1323  Register Val, MachineMemOperand &MMO);
1324 
1325  /// Build and insert `OldValRes<def> = G_ATOMICRMW_UMAX Addr, Val, MMO`.
1326  ///
1327  /// Atomically replace the value at \p Addr with the unsigned maximum of \p
1328  /// Val and the original value. Puts the original value from \p Addr in \p
1329  /// OldValRes.
1330  ///
1331  /// \pre setBasicBlock or setMI must have been called.
1332  /// \pre \p OldValRes must be a generic virtual register.
1333  /// \pre \p Addr must be a generic virtual register with pointer type.
1334  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1335  /// same type.
1336  ///
1337  /// \return a MachineInstrBuilder for the newly created instruction.
1339  Register Val, MachineMemOperand &MMO);
1340 
1341  /// Build and insert `OldValRes<def> = G_ATOMICRMW_UMIN Addr, Val, MMO`.
1342  ///
1343  /// Atomically replace the value at \p Addr with the unsigned minimum of \p
1344  /// Val and the original value. Puts the original value from \p Addr in \p
1345  /// OldValRes.
1346  ///
1347  /// \pre setBasicBlock or setMI must have been called.
1348  /// \pre \p OldValRes must be a generic virtual register.
1349  /// \pre \p Addr must be a generic virtual register with pointer type.
1350  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1351  /// same type.
1352  ///
1353  /// \return a MachineInstrBuilder for the newly created instruction.
1355  Register Val, MachineMemOperand &MMO);
1356 
1357  /// Build and insert `OldValRes<def> = G_ATOMICRMW_FADD Addr, Val, MMO`.
1359  const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val,
1360  MachineMemOperand &MMO);
1361 
1362  /// Build and insert `OldValRes<def> = G_ATOMICRMW_FSUB Addr, Val, MMO`.
1364  const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val,
1365  MachineMemOperand &MMO);
1366 
1367  /// Build and insert `G_FENCE Ordering, Scope`.
1368  MachineInstrBuilder buildFence(unsigned Ordering, unsigned Scope);
1369 
1370  /// Build and insert \p Dst = G_FREEZE \p Src
1371  MachineInstrBuilder buildFreeze(const DstOp &Dst, const SrcOp &Src) {
1372  return buildInstr(TargetOpcode::G_FREEZE, {Dst}, {Src});
1373  }
1374 
1375  /// Build and insert \p Res = G_BLOCK_ADDR \p BA
1376  ///
1377  /// G_BLOCK_ADDR computes the address of a basic block.
1378  ///
1379  /// \pre setBasicBlock or setMI must have been called.
1380  /// \pre \p Res must be a generic virtual register of a pointer type.
1381  ///
1382  /// \return The newly created instruction.
1384 
1385  /// Build and insert \p Res = G_ADD \p Op0, \p Op1
1386  ///
1387  /// G_ADD sets \p Res to the sum of integer parameters \p Op0 and \p Op1,
1388  /// truncated to their width.
1389  ///
1390  /// \pre setBasicBlock or setMI must have been called.
1391  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1392  /// with the same (scalar or vector) type).
1393  ///
1394  /// \return a MachineInstrBuilder for the newly created instruction.
1395 
1396  MachineInstrBuilder buildAdd(const DstOp &Dst, const SrcOp &Src0,
1397  const SrcOp &Src1,
1398  Optional<unsigned> Flags = None) {
1399  return buildInstr(TargetOpcode::G_ADD, {Dst}, {Src0, Src1}, Flags);
1400  }
1401 
1402  /// Build and insert \p Res = G_SUB \p Op0, \p Op1
1403  ///
1404  /// G_SUB sets \p Res to the sum of integer parameters \p Op0 and \p Op1,
1405  /// truncated to their width.
1406  ///
1407  /// \pre setBasicBlock or setMI must have been called.
1408  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1409  /// with the same (scalar or vector) type).
1410  ///
1411  /// \return a MachineInstrBuilder for the newly created instruction.
1412 
1413  MachineInstrBuilder buildSub(const DstOp &Dst, const SrcOp &Src0,
1414  const SrcOp &Src1,
1415  Optional<unsigned> Flags = None) {
1416  return buildInstr(TargetOpcode::G_SUB, {Dst}, {Src0, Src1}, Flags);
1417  }
1418 
1419  /// Build and insert \p Res = G_MUL \p Op0, \p Op1
1420  ///
1421  /// G_MUL sets \p Res to the sum of integer parameters \p Op0 and \p Op1,
1422  /// truncated to their width.
1423  ///
1424  /// \pre setBasicBlock or setMI must have been called.
1425  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1426  /// with the same (scalar or vector) type).
1427  ///
1428  /// \return a MachineInstrBuilder for the newly created instruction.
1429  MachineInstrBuilder buildMul(const DstOp &Dst, const SrcOp &Src0,
1430  const SrcOp &Src1,
1431  Optional<unsigned> Flags = None) {
1432  return buildInstr(TargetOpcode::G_MUL, {Dst}, {Src0, Src1}, Flags);
1433  }
1434 
1435  MachineInstrBuilder buildUMulH(const DstOp &Dst, const SrcOp &Src0,
1436  const SrcOp &Src1,
1437  Optional<unsigned> Flags = None) {
1438  return buildInstr(TargetOpcode::G_UMULH, {Dst}, {Src0, Src1}, Flags);
1439  }
1440 
1441  MachineInstrBuilder buildSMulH(const DstOp &Dst, const SrcOp &Src0,
1442  const SrcOp &Src1,
1443  Optional<unsigned> Flags = None) {
1444  return buildInstr(TargetOpcode::G_SMULH, {Dst}, {Src0, Src1}, Flags);
1445  }
1446 
1447  /// Build and insert \p Res = G_UREM \p Op0, \p Op1
1448  MachineInstrBuilder buildURem(const DstOp &Dst, const SrcOp &Src0,
1449  const SrcOp &Src1,
1450  Optional<unsigned> Flags = None) {
1451  return buildInstr(TargetOpcode::G_UREM, {Dst}, {Src0, Src1}, Flags);
1452  }
1453 
1454  MachineInstrBuilder buildFMul(const DstOp &Dst, const SrcOp &Src0,
1455  const SrcOp &Src1,
1456  Optional<unsigned> Flags = None) {
1457  return buildInstr(TargetOpcode::G_FMUL, {Dst}, {Src0, Src1}, Flags);
1458  }
1459 
1460  MachineInstrBuilder buildFMinNum(const DstOp &Dst, const SrcOp &Src0,
1461  const SrcOp &Src1,
1462  Optional<unsigned> Flags = None) {
1463  return buildInstr(TargetOpcode::G_FMINNUM, {Dst}, {Src0, Src1}, Flags);
1464  }
1465 
1466  MachineInstrBuilder buildFMaxNum(const DstOp &Dst, const SrcOp &Src0,
1467  const SrcOp &Src1,
1468  Optional<unsigned> Flags = None) {
1469  return buildInstr(TargetOpcode::G_FMAXNUM, {Dst}, {Src0, Src1}, Flags);
1470  }
1471 
1473  const SrcOp &Src1,
1474  Optional<unsigned> Flags = None) {
1475  return buildInstr(TargetOpcode::G_FMINNUM_IEEE, {Dst}, {Src0, Src1}, Flags);
1476  }
1477 
1479  const SrcOp &Src1,
1480  Optional<unsigned> Flags = None) {
1481  return buildInstr(TargetOpcode::G_FMAXNUM_IEEE, {Dst}, {Src0, Src1}, Flags);
1482  }
1483 
1484  MachineInstrBuilder buildShl(const DstOp &Dst, const SrcOp &Src0,
1485  const SrcOp &Src1,
1486  Optional<unsigned> Flags = None) {
1487  return buildInstr(TargetOpcode::G_SHL, {Dst}, {Src0, Src1}, Flags);
1488  }
1489 
1490  MachineInstrBuilder buildLShr(const DstOp &Dst, const SrcOp &Src0,
1491  const SrcOp &Src1,
1492  Optional<unsigned> Flags = None) {
1493  return buildInstr(TargetOpcode::G_LSHR, {Dst}, {Src0, Src1}, Flags);
1494  }
1495 
1496  MachineInstrBuilder buildAShr(const DstOp &Dst, const SrcOp &Src0,
1497  const SrcOp &Src1,
1498  Optional<unsigned> Flags = None) {
1499  return buildInstr(TargetOpcode::G_ASHR, {Dst}, {Src0, Src1}, Flags);
1500  }
1501 
1502  /// Build and insert \p Res = G_AND \p Op0, \p Op1
1503  ///
1504  /// G_AND sets \p Res to the bitwise and of integer parameters \p Op0 and \p
1505  /// Op1.
1506  ///
1507  /// \pre setBasicBlock or setMI must have been called.
1508  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1509  /// with the same (scalar or vector) type).
1510  ///
1511  /// \return a MachineInstrBuilder for the newly created instruction.
1512 
1513  MachineInstrBuilder buildAnd(const DstOp &Dst, const SrcOp &Src0,
1514  const SrcOp &Src1) {
1515  return buildInstr(TargetOpcode::G_AND, {Dst}, {Src0, Src1});
1516  }
1517 
1518  /// Build and insert \p Res = G_OR \p Op0, \p Op1
1519  ///
1520  /// G_OR sets \p Res to the bitwise or of integer parameters \p Op0 and \p
1521  /// Op1.
1522  ///
1523  /// \pre setBasicBlock or setMI must have been called.
1524  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1525  /// with the same (scalar or vector) type).
1526  ///
1527  /// \return a MachineInstrBuilder for the newly created instruction.
1528  MachineInstrBuilder buildOr(const DstOp &Dst, const SrcOp &Src0,
1529  const SrcOp &Src1,
1530  Optional<unsigned> Flags = None) {
1531  return buildInstr(TargetOpcode::G_OR, {Dst}, {Src0, Src1}, Flags);
1532  }
1533 
1534  /// Build and insert \p Res = G_XOR \p Op0, \p Op1
1535  MachineInstrBuilder buildXor(const DstOp &Dst, const SrcOp &Src0,
1536  const SrcOp &Src1) {
1537  return buildInstr(TargetOpcode::G_XOR, {Dst}, {Src0, Src1});
1538  }
1539 
1540  /// Build and insert a bitwise not,
1541  /// \p NegOne = G_CONSTANT -1
1542  /// \p Res = G_OR \p Op0, NegOne
1543  MachineInstrBuilder buildNot(const DstOp &Dst, const SrcOp &Src0) {
1544  auto NegOne = buildConstant(Dst.getLLTTy(*getMRI()), -1);
1545  return buildInstr(TargetOpcode::G_XOR, {Dst}, {Src0, NegOne});
1546  }
1547 
1548  /// Build and insert \p Res = G_CTPOP \p Op0, \p Src0
1549  MachineInstrBuilder buildCTPOP(const DstOp &Dst, const SrcOp &Src0) {
1550  return buildInstr(TargetOpcode::G_CTPOP, {Dst}, {Src0});
1551  }
1552 
1553  /// Build and insert \p Res = G_CTLZ \p Op0, \p Src0
1554  MachineInstrBuilder buildCTLZ(const DstOp &Dst, const SrcOp &Src0) {
1555  return buildInstr(TargetOpcode::G_CTLZ, {Dst}, {Src0});
1556  }
1557 
1558  /// Build and insert \p Res = G_CTLZ_ZERO_UNDEF \p Op0, \p Src0
1560  return buildInstr(TargetOpcode::G_CTLZ_ZERO_UNDEF, {Dst}, {Src0});
1561  }
1562 
1563  /// Build and insert \p Res = G_CTTZ \p Op0, \p Src0
1564  MachineInstrBuilder buildCTTZ(const DstOp &Dst, const SrcOp &Src0) {
1565  return buildInstr(TargetOpcode::G_CTTZ, {Dst}, {Src0});
1566  }
1567 
1568  /// Build and insert \p Res = G_CTTZ_ZERO_UNDEF \p Op0, \p Src0
1570  return buildInstr(TargetOpcode::G_CTTZ_ZERO_UNDEF, {Dst}, {Src0});
1571  }
1572 
1573  /// Build and insert \p Dst = G_BSWAP \p Src0
1574  MachineInstrBuilder buildBSwap(const DstOp &Dst, const SrcOp &Src0) {
1575  return buildInstr(TargetOpcode::G_BSWAP, {Dst}, {Src0});
1576  }
1577 
1578  /// Build and insert \p Res = G_FADD \p Op0, \p Op1
1579  MachineInstrBuilder buildFAdd(const DstOp &Dst, const SrcOp &Src0,
1580  const SrcOp &Src1,
1581  Optional<unsigned> Flags = None) {
1582  return buildInstr(TargetOpcode::G_FADD, {Dst}, {Src0, Src1}, Flags);
1583  }
1584 
1585  /// Build and insert \p Res = G_FSUB \p Op0, \p Op1
1586  MachineInstrBuilder buildFSub(const DstOp &Dst, const SrcOp &Src0,
1587  const SrcOp &Src1,
1588  Optional<unsigned> Flags = None) {
1589  return buildInstr(TargetOpcode::G_FSUB, {Dst}, {Src0, Src1}, Flags);
1590  }
1591 
1592  /// Build and insert \p Res = G_FDIV \p Op0, \p Op1
1593  MachineInstrBuilder buildFDiv(const DstOp &Dst, const SrcOp &Src0,
1594  const SrcOp &Src1,
1595  Optional<unsigned> Flags = None) {
1596  return buildInstr(TargetOpcode::G_FDIV, {Dst}, {Src0, Src1}, Flags);
1597  }
1598 
1599  /// Build and insert \p Res = G_FMA \p Op0, \p Op1, \p Op2
1600  MachineInstrBuilder buildFMA(const DstOp &Dst, const SrcOp &Src0,
1601  const SrcOp &Src1, const SrcOp &Src2,
1602  Optional<unsigned> Flags = None) {
1603  return buildInstr(TargetOpcode::G_FMA, {Dst}, {Src0, Src1, Src2}, Flags);
1604  }
1605 
1606  /// Build and insert \p Res = G_FMAD \p Op0, \p Op1, \p Op2
1607  MachineInstrBuilder buildFMAD(const DstOp &Dst, const SrcOp &Src0,
1608  const SrcOp &Src1, const SrcOp &Src2,
1609  Optional<unsigned> Flags = None) {
1610  return buildInstr(TargetOpcode::G_FMAD, {Dst}, {Src0, Src1, Src2}, Flags);
1611  }
1612 
1613  /// Build and insert \p Res = G_FNEG \p Op0
1614  MachineInstrBuilder buildFNeg(const DstOp &Dst, const SrcOp &Src0,
1615  Optional<unsigned> Flags = None) {
1616  return buildInstr(TargetOpcode::G_FNEG, {Dst}, {Src0}, Flags);
1617  }
1618 
1619  /// Build and insert \p Res = G_FABS \p Op0
1620  MachineInstrBuilder buildFAbs(const DstOp &Dst, const SrcOp &Src0,
1621  Optional<unsigned> Flags = None) {
1622  return buildInstr(TargetOpcode::G_FABS, {Dst}, {Src0}, Flags);
1623  }
1624 
1625  /// Build and insert \p Dst = G_FCANONICALIZE \p Src0
1627  Optional<unsigned> Flags = None) {
1628  return buildInstr(TargetOpcode::G_FCANONICALIZE, {Dst}, {Src0}, Flags);
1629  }
1630 
1631  /// Build and insert \p Dst = G_INTRINSIC_TRUNC \p Src0
1633  Optional<unsigned> Flags = None) {
1634  return buildInstr(TargetOpcode::G_INTRINSIC_TRUNC, {Dst}, {Src0}, Flags);
1635  }
1636 
1637  /// Build and insert \p Res = GFFLOOR \p Op0, \p Op1
1638  MachineInstrBuilder buildFFloor(const DstOp &Dst, const SrcOp &Src0,
1639  Optional<unsigned> Flags = None) {
1640  return buildInstr(TargetOpcode::G_FFLOOR, {Dst}, {Src0}, Flags);
1641  }
1642 
1643  /// Build and insert \p Dst = G_FLOG \p Src
1644  MachineInstrBuilder buildFLog(const DstOp &Dst, const SrcOp &Src,
1645  Optional<unsigned> Flags = None) {
1646  return buildInstr(TargetOpcode::G_FLOG, {Dst}, {Src}, Flags);
1647  }
1648 
1649  /// Build and insert \p Dst = G_FLOG2 \p Src
1650  MachineInstrBuilder buildFLog2(const DstOp &Dst, const SrcOp &Src,
1651  Optional<unsigned> Flags = None) {
1652  return buildInstr(TargetOpcode::G_FLOG2, {Dst}, {Src}, Flags);
1653  }
1654 
1655  /// Build and insert \p Dst = G_FEXP2 \p Src
1656  MachineInstrBuilder buildFExp2(const DstOp &Dst, const SrcOp &Src,
1657  Optional<unsigned> Flags = None) {
1658  return buildInstr(TargetOpcode::G_FEXP2, {Dst}, {Src}, Flags);
1659  }
1660 
1661  /// Build and insert \p Dst = G_FPOW \p Src0, \p Src1
1662  MachineInstrBuilder buildFPow(const DstOp &Dst, const SrcOp &Src0,
1663  const SrcOp &Src1,
1664  Optional<unsigned> Flags = None) {
1665  return buildInstr(TargetOpcode::G_FPOW, {Dst}, {Src0, Src1}, Flags);
1666  }
1667 
1668  /// Build and insert \p Res = G_FCOPYSIGN \p Op0, \p Op1
1670  const SrcOp &Src1) {
1671  return buildInstr(TargetOpcode::G_FCOPYSIGN, {Dst}, {Src0, Src1});
1672  }
1673 
1674  /// Build and insert \p Res = G_UITOFP \p Src0
1675  MachineInstrBuilder buildUITOFP(const DstOp &Dst, const SrcOp &Src0) {
1676  return buildInstr(TargetOpcode::G_UITOFP, {Dst}, {Src0});
1677  }
1678 
1679  /// Build and insert \p Res = G_SITOFP \p Src0
1680  MachineInstrBuilder buildSITOFP(const DstOp &Dst, const SrcOp &Src0) {
1681  return buildInstr(TargetOpcode::G_SITOFP, {Dst}, {Src0});
1682  }
1683 
1684  /// Build and insert \p Res = G_FPTOUI \p Src0
1685  MachineInstrBuilder buildFPTOUI(const DstOp &Dst, const SrcOp &Src0) {
1686  return buildInstr(TargetOpcode::G_FPTOUI, {Dst}, {Src0});
1687  }
1688 
1689  /// Build and insert \p Res = G_FPTOSI \p Src0
1690  MachineInstrBuilder buildFPTOSI(const DstOp &Dst, const SrcOp &Src0) {
1691  return buildInstr(TargetOpcode::G_FPTOSI, {Dst}, {Src0});
1692  }
1693 
1694  /// Build and insert \p Res = G_SMIN \p Op0, \p Op1
1695  MachineInstrBuilder buildSMin(const DstOp &Dst, const SrcOp &Src0,
1696  const SrcOp &Src1) {
1697  return buildInstr(TargetOpcode::G_SMIN, {Dst}, {Src0, Src1});
1698  }
1699 
1700  /// Build and insert \p Res = G_SMAX \p Op0, \p Op1
1701  MachineInstrBuilder buildSMax(const DstOp &Dst, const SrcOp &Src0,
1702  const SrcOp &Src1) {
1703  return buildInstr(TargetOpcode::G_SMAX, {Dst}, {Src0, Src1});
1704  }
1705 
1706  /// Build and insert \p Res = G_UMIN \p Op0, \p Op1
1707  MachineInstrBuilder buildUMin(const DstOp &Dst, const SrcOp &Src0,
1708  const SrcOp &Src1) {
1709  return buildInstr(TargetOpcode::G_UMIN, {Dst}, {Src0, Src1});
1710  }
1711 
1712  /// Build and insert \p Res = G_UMAX \p Op0, \p Op1
1713  MachineInstrBuilder buildUMax(const DstOp &Dst, const SrcOp &Src0,
1714  const SrcOp &Src1) {
1715  return buildInstr(TargetOpcode::G_UMAX, {Dst}, {Src0, Src1});
1716  }
1717 
1718  /// Build and insert \p Dst = G_ABS \p Src
1719  MachineInstrBuilder buildAbs(const DstOp &Dst, const SrcOp &Src) {
1720  return buildInstr(TargetOpcode::G_ABS, {Dst}, {Src});
1721  }
1722 
1723  /// Build and insert \p Res = G_JUMP_TABLE \p JTI
1724  ///
1725  /// G_JUMP_TABLE sets \p Res to the address of the jump table specified by
1726  /// the jump table index \p JTI.
1727  ///
1728  /// \return a MachineInstrBuilder for the newly created instruction.
1729  MachineInstrBuilder buildJumpTable(const LLT PtrTy, unsigned JTI);
1730 
1731  /// Build and insert \p Res = G_VECREDUCE_SEQ_FADD \p ScalarIn, \p VecIn
1732  ///
1733  /// \p ScalarIn is the scalar accumulator input to start the sequential
1734  /// reduction operation of \p VecIn.
1736  const SrcOp &ScalarIn,
1737  const SrcOp &VecIn) {
1738  return buildInstr(TargetOpcode::G_VECREDUCE_SEQ_FADD, {Dst},
1739  {ScalarIn, {VecIn}});
1740  }
1741 
1742  /// Build and insert \p Res = G_VECREDUCE_SEQ_FMUL \p ScalarIn, \p VecIn
1743  ///
1744  /// \p ScalarIn is the scalar accumulator input to start the sequential
1745  /// reduction operation of \p VecIn.
1747  const SrcOp &ScalarIn,
1748  const SrcOp &VecIn) {
1749  return buildInstr(TargetOpcode::G_VECREDUCE_SEQ_FMUL, {Dst},
1750  {ScalarIn, {VecIn}});
1751  }
1752 
1753  /// Build and insert \p Res = G_VECREDUCE_FADD \p Src
1754  ///
1755  /// \p ScalarIn is the scalar accumulator input to the reduction operation of
1756  /// \p VecIn.
1758  const SrcOp &ScalarIn,
1759  const SrcOp &VecIn) {
1760  return buildInstr(TargetOpcode::G_VECREDUCE_FADD, {Dst}, {ScalarIn, VecIn});
1761  }
1762 
1763  /// Build and insert \p Res = G_VECREDUCE_FMUL \p Src
1764  ///
1765  /// \p ScalarIn is the scalar accumulator input to the reduction operation of
1766  /// \p VecIn.
1768  const SrcOp &ScalarIn,
1769  const SrcOp &VecIn) {
1770  return buildInstr(TargetOpcode::G_VECREDUCE_FMUL, {Dst}, {ScalarIn, VecIn});
1771  }
1772 
1773  /// Build and insert \p Res = G_VECREDUCE_FMAX \p Src
1775  return buildInstr(TargetOpcode::G_VECREDUCE_FMAX, {Dst}, {Src});
1776  }
1777 
1778  /// Build and insert \p Res = G_VECREDUCE_FMIN \p Src
1780  return buildInstr(TargetOpcode::G_VECREDUCE_FMIN, {Dst}, {Src});
1781  }
1782  /// Build and insert \p Res = G_VECREDUCE_ADD \p Src
1784  return buildInstr(TargetOpcode::G_VECREDUCE_ADD, {Dst}, {Src});
1785  }
1786 
1787  /// Build and insert \p Res = G_VECREDUCE_MUL \p Src
1789  return buildInstr(TargetOpcode::G_VECREDUCE_MUL, {Dst}, {Src});
1790  }
1791 
1792  /// Build and insert \p Res = G_VECREDUCE_AND \p Src
1794  return buildInstr(TargetOpcode::G_VECREDUCE_AND, {Dst}, {Src});
1795  }
1796 
1797  /// Build and insert \p Res = G_VECREDUCE_OR \p Src
1799  return buildInstr(TargetOpcode::G_VECREDUCE_OR, {Dst}, {Src});
1800  }
1801 
1802  /// Build and insert \p Res = G_VECREDUCE_XOR \p Src
1804  return buildInstr(TargetOpcode::G_VECREDUCE_XOR, {Dst}, {Src});
1805  }
1806 
1807  /// Build and insert \p Res = G_VECREDUCE_SMAX \p Src
1809  return buildInstr(TargetOpcode::G_VECREDUCE_SMAX, {Dst}, {Src});
1810  }
1811 
1812  /// Build and insert \p Res = G_VECREDUCE_SMIN \p Src
1814  return buildInstr(TargetOpcode::G_VECREDUCE_SMIN, {Dst}, {Src});
1815  }
1816 
1817  /// Build and insert \p Res = G_VECREDUCE_UMAX \p Src
1819  return buildInstr(TargetOpcode::G_VECREDUCE_UMAX, {Dst}, {Src});
1820  }
1821 
1822  /// Build and insert \p Res = G_VECREDUCE_UMIN \p Src
1824  return buildInstr(TargetOpcode::G_VECREDUCE_UMIN, {Dst}, {Src});
1825  }
1826 
1827  /// Build and insert G_MEMCPY or G_MEMMOVE
1828  MachineInstrBuilder buildMemTransferInst(unsigned Opcode, const SrcOp &DstPtr,
1829  const SrcOp &SrcPtr,
1830  const SrcOp &Size,
1831  MachineMemOperand &DstMMO,
1832  MachineMemOperand &SrcMMO) {
1833  auto MIB = buildInstr(
1834  Opcode, {}, {DstPtr, SrcPtr, Size, SrcOp(INT64_C(0) /*isTailCall*/)});
1835  MIB.addMemOperand(&DstMMO);
1836  MIB.addMemOperand(&SrcMMO);
1837  return MIB;
1838  }
1839 
1840  MachineInstrBuilder buildMemCpy(const SrcOp &DstPtr, const SrcOp &SrcPtr,
1841  const SrcOp &Size, MachineMemOperand &DstMMO,
1842  MachineMemOperand &SrcMMO) {
1843  return buildMemTransferInst(TargetOpcode::G_MEMCPY, DstPtr, SrcPtr, Size,
1844  DstMMO, SrcMMO);
1845  }
1846 
1847  /// Build and insert \p Dst = G_SBFX \p Src, \p LSB, \p Width.
1848  MachineInstrBuilder buildSbfx(const DstOp &Dst, const SrcOp &Src,
1849  const SrcOp &LSB, const SrcOp &Width) {
1850  return buildInstr(TargetOpcode::G_SBFX, {Dst}, {Src, LSB, Width});
1851  }
1852 
1853  /// Build and insert \p Dst = G_UBFX \p Src, \p LSB, \p Width.
1854  MachineInstrBuilder buildUbfx(const DstOp &Dst, const SrcOp &Src,
1855  const SrcOp &LSB, const SrcOp &Width) {
1856  return buildInstr(TargetOpcode::G_UBFX, {Dst}, {Src, LSB, Width});
1857  }
1858 
1859  /// Build and insert \p Dst = G_ROTR \p Src, \p Amt
1861  const SrcOp &Amt) {
1862  return buildInstr(TargetOpcode::G_ROTR, {Dst}, {Src, Amt});
1863  }
1864 
1865  /// Build and insert \p Dst = G_ROTL \p Src, \p Amt
1867  const SrcOp &Amt) {
1868  return buildInstr(TargetOpcode::G_ROTL, {Dst}, {Src, Amt});
1869  }
1870 
1871  virtual MachineInstrBuilder buildInstr(unsigned Opc, ArrayRef<DstOp> DstOps,
1872  ArrayRef<SrcOp> SrcOps,
1873  Optional<unsigned> Flags = None);
1874 };
1875 
1876 } // End namespace llvm.
1877 #endif // LLVM_CODEGEN_GLOBALISEL_MACHINEIRBUILDER_H
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
llvm::MachineIRBuilder::buildUSubo
MachineInstrBuilder buildUSubo(const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1)
Build and insert Res, CarryOut = G_USUBO Op0, Op1.
Definition: MachineIRBuilder.h:526
llvm::MachineIRBuilder::setMF
void setMF(MachineFunction &MF)
Definition: MachineIRBuilder.cpp:26
llvm::MachineIRBuilder::buildInsertVectorElement
MachineInstrBuilder buildInsertVectorElement(const DstOp &Res, const SrcOp &Val, const SrcOp &Elt, const SrcOp &Idx)
Build and insert Res = G_INSERT_VECTOR_ELT Val, Elt, Idx.
Definition: MachineIRBuilder.cpp:774
LowLevelType.h
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:100
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:132
llvm
Definition: AllocatorList.h:23
llvm::MachineIRBuilder::buildGlobalValue
MachineInstrBuilder buildGlobalValue(const DstOp &Res, const GlobalValue *GV)
Build and insert Res = G_GLOBAL_VALUE GV.
Definition: MachineIRBuilder.cpp:146
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::DstOp::DstType::Ty_LLT
@ Ty_LLT
llvm::MachineIRBuilder::buildOr
MachineInstrBuilder buildOr(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Build and insert Res = G_OR Op0, Op1.
Definition: MachineIRBuilder.h:1528
llvm::MachineIRBuilder::buildFMul
MachineInstrBuilder buildFMul(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Definition: MachineIRBuilder.h:1454
llvm::MachineIRBuilder::buildAtomicRMW
MachineInstrBuilder buildAtomicRMW(unsigned Opcode, const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_<Opcode> Addr, Val, MMO.
Definition: MachineIRBuilder.cpp:837
llvm::MachineIRBuilder::setDebugLoc
void setDebugLoc(const DebugLoc &DL)
Set the debug location to DL for all the next build instructions.
Definition: MachineIRBuilder.h:363
llvm::MachineIRBuilder::buildIntToPtr
MachineInstrBuilder buildIntToPtr(const DstOp &Dst, const SrcOp &Src)
Build and insert a G_INTTOPTR instruction.
Definition: MachineIRBuilder.h:636
llvm::MachineIRBuilder::buildICmp
MachineInstrBuilder buildICmp(CmpInst::Predicate Pred, const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1)
Build and insert a Res = G_ICMP Pred, Op0, Op1.
Definition: MachineIRBuilder.cpp:748
llvm::MachineIRBuilder::buildSMax
MachineInstrBuilder buildSMax(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_SMAX Op0, Op1.
Definition: MachineIRBuilder.h:1701
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:112
llvm::CmpInst::Predicate
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:722
llvm::MachineIRBuilderState::II
MachineBasicBlock::iterator II
Definition: MachineIRBuilder.h:50
llvm::MachineIRBuilder::buildAShr
MachineInstrBuilder buildAShr(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Definition: MachineIRBuilder.h:1496
llvm::MachineIRBuilder::buildFSub
MachineInstrBuilder buildFSub(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Build and insert Res = G_FSUB Op0, Op1.
Definition: MachineIRBuilder.h:1586
llvm::MachineIRBuilder::buildUSube
MachineInstrBuilder buildUSube(const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1, const SrcOp &CarryIn)
Build and insert Res, CarryOut = G_USUBE Op0, Op1, CarryInp.
Definition: MachineIRBuilder.h:565
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
llvm::MachineIRBuilder::buildSMulH
MachineInstrBuilder buildSMulH(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Definition: MachineIRBuilder.h:1441
P
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
Definition: README-SSE.txt:411
llvm::MachineIRBuilder::buildSbfx
MachineInstrBuilder buildSbfx(const DstOp &Dst, const SrcOp &Src, const SrcOp &LSB, const SrcOp &Width)
Build and insert Dst = G_SBFX Src, LSB, Width.
Definition: MachineIRBuilder.h:1848
llvm::MachineIRBuilder::getCSEInfo
GISelCSEInfo * getCSEInfo()
Definition: MachineIRBuilder.h:305
llvm::MachineIRBuilder::buildUMulH
MachineInstrBuilder buildUMulH(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Definition: MachineIRBuilder.h:1435
llvm::MachineIRBuilder::buildBSwap
MachineInstrBuilder buildBSwap(const DstOp &Dst, const SrcOp &Src0)
Build and insert Dst = G_BSWAP Src0.
Definition: MachineIRBuilder.h:1574
llvm::MachineIRBuilder::buildSplatVector
MachineInstrBuilder buildSplatVector(const DstOp &Res, const SrcOp &Src)
Build and insert Res = G_BUILD_VECTOR with Src replicated to fill the number of elements.
Definition: MachineIRBuilder.cpp:643
llvm::MachineIRBuilder::getMRI
MachineRegisterInfo * getMRI()
Getter for MRI.
Definition: MachineIRBuilder.h:288
llvm::MachineIRBuilder::buildZExtInReg
MachineInstrBuilder buildZExtInReg(const DstOp &Res, const SrcOp &Op, int64_t ImmOp)
Build and inserts Res = G_AND Op, LowBitsSet(ImmOp) Since there is no G_ZEXT_INREG like G_SEXT_INREG,...
Definition: MachineIRBuilder.cpp:489
llvm::DstOp::RC
const TargetRegisterClass * RC
Definition: MachineIRBuilder.h:62
llvm::MachineIRBuilder::buildAtomicRMWOr
MachineInstrBuilder buildAtomicRMWOr(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_OR Addr, Val, MMO.
Definition: MachineIRBuilder.cpp:891
llvm::MachineIRBuilder::buildFCanonicalize
MachineInstrBuilder buildFCanonicalize(const DstOp &Dst, const SrcOp &Src0, Optional< unsigned > Flags=None)
Build and insert Dst = G_FCANONICALIZE Src0.
Definition: MachineIRBuilder.h:1626
llvm::GISelCSEInfo
The CSE Analysis object.
Definition: CSEInfo.h:69
llvm::MachineIRBuilder::buildFAbs
MachineInstrBuilder buildFAbs(const DstOp &Dst, const SrcOp &Src0, Optional< unsigned > Flags=None)
Build and insert Res = G_FABS Op0.
Definition: MachineIRBuilder.h:1620
llvm::MachineIRBuilder::MachineIRBuilder
MachineIRBuilder(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsPt)
Definition: MachineIRBuilder.h:244
llvm::MachineIRBuilder::buildZExtOrTrunc
MachineInstrBuilder buildZExtOrTrunc(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_ZEXT Op, Res = G_TRUNC Op, or Res = COPY Op depending on the differing sizes...
Definition: MachineIRBuilder.cpp:479
MachineBasicBlock.h
llvm::FlagsOp
Definition: MachineIRBuilder.h:208
llvm::MachineIRBuilder::buildUMin
MachineInstrBuilder buildUMin(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_UMIN Op0, Op1.
Definition: MachineIRBuilder.h:1707
llvm::AAMDNodes
A collection of metadata nodes that might be associated with a memory access used by the alias-analys...
Definition: Metadata.h:651
llvm::MachineIRBuilder::buildAtomicRMWAdd
MachineInstrBuilder buildAtomicRMWAdd(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_ADD Addr, Val, MMO.
Definition: MachineIRBuilder.cpp:868
llvm::MachineIRBuilder::buildAtomicCmpXchg
MachineInstrBuilder buildAtomicCmpXchg(Register OldValRes, Register Addr, Register CmpVal, Register NewVal, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMIC_CMPXCHG Addr, CmpVal, NewVal, MMO.
Definition: MachineIRBuilder.cpp:813
llvm::MachineIRBuilder::buildDbgLabel
MachineInstrBuilder buildDbgLabel(const MDNode *Label)
Build and insert a DBG_LABEL instructions specifying that Label is given.
Definition: MachineIRBuilder.cpp:117
Module.h
llvm::MachineIRBuilder::buildFMAD
MachineInstrBuilder buildFMAD(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, const SrcOp &Src2, Optional< unsigned > Flags=None)
Build and insert Res = G_FMAD Op0, Op1, Op2.
Definition: MachineIRBuilder.h:1607
llvm::SrcOp::Reg
Register Reg
Definition: MachineIRBuilder.h:122
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition: MachineMemOperand.h:127
llvm::MachineIRBuilder::MachineIRBuilder
MachineIRBuilder()=default
Some constructors for easy use.
llvm::MachineIRBuilder::getDL
const DebugLoc & getDL()
Getter for DebugLoc.
Definition: MachineIRBuilder.h:285
llvm::MachineIRBuilder::buildFPTrunc
MachineInstrBuilder buildFPTrunc(const DstOp &Res, const SrcOp &Op, Optional< unsigned > Flags=None)
Build and insert Res = G_FPTRUNC Op.
Definition: MachineIRBuilder.cpp:742
llvm::MachineIRBuilder::buildVecReduceAdd
MachineInstrBuilder buildVecReduceAdd(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_ADD Src.
Definition: MachineIRBuilder.h:1783
llvm::SrcOp::Imm
int64_t Imm
Definition: MachineIRBuilder.h:124
llvm::MachineIRBuilder::buildCTTZ
MachineInstrBuilder buildCTTZ(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_CTTZ Op0, Src0.
Definition: MachineIRBuilder.h:1564
llvm::Optional< unsigned >
T
#define T
Definition: Mips16ISelLowering.cpp:341
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
llvm::MachineIRBuilder::buildBuildVector
MachineInstrBuilder buildBuildVector(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_BUILD_VECTOR Op0, ...
Definition: MachineIRBuilder.cpp:634
llvm::MachineIRBuilder::getMF
const MachineFunction & getMF() const
Definition: MachineIRBuilder.h:275
llvm::MachineIRBuilder::buildInstrNoInsert
MachineInstrBuilder buildInstrNoInsert(unsigned Opcode)
Build but don't insert <empty> = Opcode <empty>.
Definition: MachineIRBuilder.cpp:40
llvm::MachineIRBuilder::setInstr
void setInstr(MachineInstr &MI)
Set the insertion point to before MI.
Definition: MachineIRBuilder.h:341
llvm::DstOp::DstOp
DstOp(const TargetRegisterClass *TRC)
Definition: MachineIRBuilder.h:71
llvm::MachineIRBuilder::buildExtOrTrunc
MachineInstrBuilder buildExtOrTrunc(unsigned ExtOpc, const DstOp &Res, const SrcOp &Op)
Build and insert Res = ExtOpc, Res = G_TRUNC Op, or Res = COPY Op depending on the differing sizes of...
Definition: MachineIRBuilder.cpp:450
llvm::MachineIRBuilderState::MBB
MachineBasicBlock * MBB
Definition: MachineIRBuilder.h:49
llvm::MachineIRBuilder::getDebugLoc
DebugLoc getDebugLoc()
Get the current instruction's debug location.
Definition: MachineIRBuilder.h:366
llvm::MachineIRBuilder::buildVecReduceFMin
MachineInstrBuilder buildVecReduceFMin(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_FMIN Src.
Definition: MachineIRBuilder.h:1779
llvm::MachineIRBuilder::buildPtrMask
MachineInstrBuilder buildPtrMask(const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1)
Build and insert Res = G_PTRMASK Op0, Op1.
Definition: MachineIRBuilder.h:487
llvm::MachineIRBuilder::buildXor
MachineInstrBuilder buildXor(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_XOR Op0, Op1.
Definition: MachineIRBuilder.h:1535
llvm::MachineIRBuilder::buildAtomicRMWFSub
MachineInstrBuilder buildAtomicRMWFSub(const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_FSUB Addr, Val, MMO.
Definition: MachineIRBuilder.cpp:938
llvm::MachineIRBuilder::buildFence
MachineInstrBuilder buildFence(unsigned Ordering, unsigned Scope)
Build and insert G_FENCE Ordering, Scope.
Definition: MachineIRBuilder.cpp:945
llvm::BitmaskEnumDetail::Mask
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::MachineIRBuilder::buildFCopysign
MachineInstrBuilder buildFCopysign(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_FCOPYSIGN Op0, Op1.
Definition: MachineIRBuilder.h:1669
llvm::SrcOp::SrcType::Ty_Predicate
@ Ty_Predicate
llvm::MachineIRBuilder::buildDynStackAlloc
MachineInstrBuilder buildDynStackAlloc(const DstOp &Res, const SrcOp &Size, Align Alignment)
Build and insert Res = G_DYN_STACKALLOC Size, Align.
Definition: MachineIRBuilder.cpp:126
llvm::MachineIRBuilder::getCSEInfo
const GISelCSEInfo * getCSEInfo() const
Definition: MachineIRBuilder.h:306
llvm::MachineIRBuilder::validateSelectOp
void validateSelectOp(const LLT ResTy, const LLT TstTy, const LLT Op0Ty, const LLT Op1Ty)
Definition: MachineIRBuilder.cpp:979
llvm::MachineIRBuilderState
Class which stores all the state required in a MachineIRBuilder.
Definition: MachineIRBuilder.h:37
llvm::MachineIRBuilder::buildConstant
virtual MachineInstrBuilder buildConstant(const DstOp &Res, const ConstantInt &Val)
Build and insert Res = G_CONSTANT Val.
Definition: MachineIRBuilder.cpp:255
llvm::MachineIRBuilder::buildURem
MachineInstrBuilder buildURem(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Build and insert Res = G_UREM Op0, Op1.
Definition: MachineIRBuilder.h:1448
F
#define F(x, y, z)
Definition: MD5.cpp:56
llvm::MachineIRBuilder::validateBinaryOp
void validateBinaryOp(const LLT Res, const LLT Op0, const LLT Op1)
Definition: MachineIRBuilder.cpp:170
MachineRegisterInfo.h
llvm::MachineIRBuilder::buildCTLZ_ZERO_UNDEF
MachineInstrBuilder buildCTLZ_ZERO_UNDEF(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_CTLZ_ZERO_UNDEF Op0, Src0.
Definition: MachineIRBuilder.h:1559
llvm::DstOp::getRegClass
const TargetRegisterClass * getRegClass() const
Definition: MachineIRBuilder.h:104
CSEInfo.h
llvm::DstOp::DstOp
DstOp(const LLT T)
Definition: MachineIRBuilder.h:70
llvm::MachineInstrBuilder::addDef
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
Definition: MachineInstrBuilder.h:117
llvm::MachineIRBuilder::setCSEInfo
void setCSEInfo(GISelCSEInfo *Info)
Definition: MachineIRBuilder.h:323
llvm::ConstantInt
This is the shared class of boolean and integer constants.
Definition: Constants.h:77
llvm::MachineIRBuilder::getMRI
const MachineRegisterInfo * getMRI() const
Definition: MachineIRBuilder.h:289
llvm::MachineIRBuilder::buildAtomicCmpXchgWithSuccess
MachineInstrBuilder buildAtomicCmpXchgWithSuccess(Register OldValRes, Register SuccessRes, Register Addr, Register CmpVal, Register NewVal, MachineMemOperand &MMO)
Build and insert OldValRes<def>, SuccessRes<def> = G_ATOMIC_CMPXCHG_WITH_SUCCESS Addr,...
Definition: MachineIRBuilder.cpp:785
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:97
llvm::MachineIRBuilder::buildUnmerge
MachineInstrBuilder buildUnmerge(ArrayRef< LLT > Res, const SrcOp &Op)
Build and insert Res0, ...
Definition: MachineIRBuilder.cpp:605
llvm::MachineIRBuilder::buildAtomicRMWMin
MachineInstrBuilder buildAtomicRMWMin(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_MIN Addr, Val, MMO.
Definition: MachineIRBuilder.cpp:911
llvm::MachineIRBuilder::buildZExt
MachineInstrBuilder buildZExt(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_ZEXT Op.
Definition: MachineIRBuilder.cpp:426
llvm::MachineIRBuilder::buildExtractVectorElement
MachineInstrBuilder buildExtractVectorElement(const DstOp &Res, const SrcOp &Val, const SrcOp &Idx)
Build and insert Res = G_EXTRACT_VECTOR_ELT Val, Idx.
Definition: MachineIRBuilder.cpp:780
llvm::MachineIRBuilder::buildLoad
MachineInstrBuilder buildLoad(const DstOp &Res, const SrcOp &Addr, MachineMemOperand &MMO)
Build and insert Res = G_LOAD Addr, MMO.
Definition: MachineIRBuilder.h:840
llvm::MachineIRBuilder::MachineIRBuilder
MachineIRBuilder(const MachineIRBuilderState &BState)
Definition: MachineIRBuilder.h:262
Constants.h
llvm::MachineIRBuilder::buildShl
MachineInstrBuilder buildShl(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Definition: MachineIRBuilder.h:1484
llvm::FlagsOp::FlagsOp
FlagsOp(unsigned F)
Definition: MachineIRBuilder.h:212
llvm::MachineIRBuilder::setMBB
void setMBB(MachineBasicBlock &MBB)
Set the insertion point to the end of MBB.
Definition: MachineIRBuilder.h:332
llvm::DstOp::LLTTy
LLT LLTTy
Definition: MachineIRBuilder.h:60
llvm::DstOp::addDefToMIB
void addDefToMIB(MachineRegisterInfo &MRI, MachineInstrBuilder &MIB) const
Definition: MachineIRBuilder.h:73
llvm::MachineIRBuilder::buildSAdde
MachineInstrBuilder buildSAdde(const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1, const SrcOp &CarryIn)
Build and insert Res, CarryOut = G_SADDE Op0, Op1, CarryInp.
Definition: MachineIRBuilder.h:573
llvm::DstOp::DstType::Ty_RC
@ Ty_RC
llvm::DstOp::getReg
Register getReg() const
Definition: MachineIRBuilder.h:99
llvm::MachineIRBuilder::buildFLog
MachineInstrBuilder buildFLog(const DstOp &Dst, const SrcOp &Src, Optional< unsigned > Flags=None)
Build and insert Dst = G_FLOG Src.
Definition: MachineIRBuilder.h:1644
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::MachineIRBuilder::buildBoolExt
MachineInstrBuilder buildBoolExt(const DstOp &Res, const SrcOp &Op, bool IsFP)
Definition: MachineIRBuilder.cpp:443
llvm::MachineInstr::getOperand
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:488
llvm::MachineIRBuilder::buildPtrToInt
MachineInstrBuilder buildPtrToInt(const DstOp &Dst, const SrcOp &Src)
Build and insert a G_PTRTOINT instruction.
Definition: MachineIRBuilder.h:631
llvm::MachineIRBuilder::recordInsertion
void recordInsertion(MachineInstr *InsertedInstr) const
Definition: MachineIRBuilder.h:234
llvm::MachineIRBuilder::buildAnyExtOrTrunc
MachineInstrBuilder buildAnyExtOrTrunc(const DstOp &Res, const SrcOp &Op)
Res = COPY Op depending on the differing sizes of Res and Op.
Definition: MachineIRBuilder.cpp:484
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::MachineIRBuilder::buildFCmp
MachineInstrBuilder buildFCmp(CmpInst::Predicate Pred, const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1, Optional< unsigned > Flags=None)
Build and insert a Res = G_FCMP PredOp0, Op1.
Definition: MachineIRBuilder.cpp:755
llvm::MachineIRBuilder::buildFIDbgValue
MachineInstrBuilder buildFIDbgValue(int FI, const MDNode *Variable, const MDNode *Expr)
Build and insert a DBG_VALUE instruction expressing the fact that the associated Variable lives in th...
Definition: MachineIRBuilder.cpp:77
llvm::MachineIRBuilder::buildCTLZ
MachineInstrBuilder buildCTLZ(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_CTLZ Op0, Src0.
Definition: MachineIRBuilder.h:1554
TargetOpcodes.h
llvm::MachineIRBuilder::buildConcatVectors
MachineInstrBuilder buildConcatVectors(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_CONCAT_VECTORS Op0, ...
Definition: MachineIRBuilder.cpp:689
llvm::MachineIRBuilder::getDataLayout
const DataLayout & getDataLayout() const
Definition: MachineIRBuilder.h:280
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
llvm::MachineIRBuilder::MachineIRBuilder
MachineIRBuilder(MachineFunction &MF)
Definition: MachineIRBuilder.h:242
llvm::DstOp::getDstOpKind
DstType getDstOpKind() const
Definition: MachineIRBuilder.h:113
llvm::MachineIRBuilder::buildAtomicRMWAnd
MachineInstrBuilder buildAtomicRMWAnd(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_AND Addr, Val, MMO.
Definition: MachineIRBuilder.cpp:880
llvm::MachineIRBuilder::getMF
MachineFunction & getMF()
Getter for the function we currently build.
Definition: MachineIRBuilder.h:270
llvm::FlagsOp::FlagsOp
FlagsOp()
Definition: MachineIRBuilder.h:213
llvm::ConstantFP
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:255
llvm::MachineIRBuilder::buildFFloor
MachineInstrBuilder buildFFloor(const DstOp &Dst, const SrcOp &Src0, Optional< unsigned > Flags=None)
Build and insert Res = GFFLOOR Op0, Op1.
Definition: MachineIRBuilder.h:1638
DebugLoc.h
llvm::MachineIRBuilder::buildAnd
MachineInstrBuilder buildAnd(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_AND Op0, Op1.
Definition: MachineIRBuilder.h:1513
llvm::MachineIRBuilder::getMBB
MachineBasicBlock & getMBB()
Definition: MachineIRBuilder.h:300
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:26
llvm::MachineIRBuilder::buildSMin
MachineInstrBuilder buildSMin(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_SMIN Op0, Op1.
Definition: MachineIRBuilder.h:1695
llvm::DstOp::DstOp
DstOp(Register R)
Definition: MachineIRBuilder.h:68
llvm::MachineIRBuilder::buildVecReduceOr
MachineInstrBuilder buildVecReduceOr(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_OR Src.
Definition: MachineIRBuilder.h:1798
llvm::MachineIRBuilder::buildIndirectDbgValue
MachineInstrBuilder buildIndirectDbgValue(Register Reg, const MDNode *Variable, const MDNode *Expr)
Build and insert a DBG_VALUE instruction expressing the fact that the associated Variable lives in me...
Definition: MachineIRBuilder.cpp:65
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::MachineIRBuilder::buildBrCond
MachineInstrBuilder buildBrCond(const SrcOp &Tst, MachineBasicBlock &Dest)
Build and insert G_BRCOND Tst, Dest.
Definition: MachineIRBuilder.cpp:332
llvm::MachineIRBuilder::buildLoadInstr
MachineInstrBuilder buildLoadInstr(unsigned Opcode, const DstOp &Res, const SrcOp &Addr, MachineMemOperand &MMO)
Build and insert Res = <opcode> Addr, MMO.
Definition: MachineIRBuilder.cpp:357
llvm::DstOp::DstOp
DstOp(unsigned R)
Definition: MachineIRBuilder.h:67
llvm::None
const NoneType None
Definition: None.h:23
llvm::MachineIRBuilder::buildAtomicRMWMax
MachineInstrBuilder buildAtomicRMWMax(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_MAX Addr, Val, MMO.
Definition: MachineIRBuilder.cpp:905
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::MachineIRBuilder::buildBrIndirect
MachineInstrBuilder buildBrIndirect(Register Tgt)
Build and insert G_BRINDIRECT Tgt.
Definition: MachineIRBuilder.cpp:222
llvm::MachineIRBuilder::buildVecReduceFMul
MachineInstrBuilder buildVecReduceFMul(const DstOp &Dst, const SrcOp &ScalarIn, const SrcOp &VecIn)
Build and insert Res = G_VECREDUCE_FMUL Src.
Definition: MachineIRBuilder.h:1767
llvm::MachineIRBuilder::validateUnaryOp
void validateUnaryOp(const LLT Res, const LLT Op0)
Definition: MachineIRBuilder.cpp:165
llvm::MachineIRBuilder::buildFNeg
MachineInstrBuilder buildFNeg(const DstOp &Dst, const SrcOp &Src0, Optional< unsigned > Flags=None)
Build and insert Res = G_FNEG Op0.
Definition: MachineIRBuilder.h:1614
llvm::MachineIRBuilder::buildCTPOP
MachineInstrBuilder buildCTPOP(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_CTPOP Op0, Src0.
Definition: MachineIRBuilder.h:1549
llvm::SrcOp::getImm
int64_t getImm() const
Definition: MachineIRBuilder.h:193
llvm::MachineIRBuilder::buildVecReduceXor
MachineInstrBuilder buildVecReduceXor(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_XOR Src.
Definition: MachineIRBuilder.h:1803
llvm::SrcOp::SrcOp
SrcOp(const MachineOperand &Op)
Definition: MachineIRBuilder.h:130
llvm::MachineIRBuilder::buildBr
MachineInstrBuilder buildBr(MachineBasicBlock &Dest)
Build and insert G_BR Dest.
Definition: MachineIRBuilder.cpp:218
llvm::MachineIRBuilder::buildMaskLowPtrBits
MachineInstrBuilder buildMaskLowPtrBits(const DstOp &Res, const SrcOp &Op0, uint32_t NumBits)
Build and insert Res = G_PTRMASK Op0, G_CONSTANT (1 << NumBits) - 1.
Definition: MachineIRBuilder.cpp:208
llvm::APFloat
Definition: APFloat.h:701
llvm::MachineIRBuilder::buildAbs
MachineInstrBuilder buildAbs(const DstOp &Dst, const SrcOp &Src)
Build and insert Dst = G_ABS Src.
Definition: MachineIRBuilder.h:1719
llvm::MachineIRBuilder::buildFAdd
MachineInstrBuilder buildFAdd(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Build and insert Res = G_FADD Op0, Op1.
Definition: MachineIRBuilder.h:1579
llvm::MachineIRBuilder::buildFMinNum
MachineInstrBuilder buildFMinNum(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Definition: MachineIRBuilder.h:1460
llvm::SrcOp::SrcOp
SrcOp(Register R)
Definition: MachineIRBuilder.h:129
llvm::GlobalValue
Definition: GlobalValue.h:44
llvm::MachineIRBuilder::buildFConstant
virtual MachineInstrBuilder buildFConstant(const DstOp &Res, const ConstantFP &Val)
Build and insert Res = G_FCONSTANT Val.
Definition: MachineIRBuilder.cpp:284
llvm::MachineIRBuilder::buildUbfx
MachineInstrBuilder buildUbfx(const DstOp &Dst, const SrcOp &Src, const SrcOp &LSB, const SrcOp &Width)
Build and insert Dst = G_UBFX Src, LSB, Width.
Definition: MachineIRBuilder.h:1854
llvm::Constant
This is an important base class in LLVM.
Definition: Constant.h:41
llvm::MachineIRBuilder::buildBrJT
MachineInstrBuilder buildBrJT(Register TablePtr, unsigned JTI, Register IndexReg)
Build and insert G_BRJT TablePtr, JTI, IndexReg.
Definition: MachineIRBuilder.cpp:227
llvm::MachineIRBuilder::buildSExtOrTrunc
MachineInstrBuilder buildSExtOrTrunc(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_SEXT Op, Res = G_TRUNC Op, or Res = COPY Op depending on the differing sizes...
Definition: MachineIRBuilder.cpp:474
llvm::MachineIRBuilder::setInsertPt
void setInsertPt(MachineBasicBlock &MBB, MachineBasicBlock::iterator II)
Set the insertion point before the specified position.
Definition: MachineIRBuilder.h:314
llvm::MachineIRBuilder
Helper class to build MachineInstr.
Definition: MachineIRBuilder.h:220
llvm::DstOp::Reg
Register Reg
Definition: MachineIRBuilder.h:61
Index
uint32_t Index
Definition: ELFObjHandler.cpp:84
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:70
llvm::MachineIRBuilder::buildAssertSExt
MachineInstrBuilder buildAssertSExt(const DstOp &Res, const SrcOp &Op, unsigned Size)
Build and insert Res = G_ASSERT_SEXT Op, Size.
Definition: MachineIRBuilder.cpp:243
llvm::SrcOp::SrcType
SrcType
Definition: MachineIRBuilder.h:128
llvm::GlobalValue::getParent
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:572
Addr
uint64_t Addr
Definition: ELFObjHandler.cpp:80
llvm::MachineIRBuilder::buildAssertZExt
MachineInstrBuilder buildAssertZExt(const DstOp &Res, const SrcOp &Op, unsigned Size)
Build and insert Res = G_ASSERT_ZEXT Op, Size.
Definition: MachineIRBuilder.cpp:249
llvm::MachineIRBuilder::buildUMax
MachineInstrBuilder buildUMax(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_UMAX Op0, Op1.
Definition: MachineIRBuilder.h:1713
llvm::MachineIRBuilder::buildBitcast
MachineInstrBuilder buildBitcast(const DstOp &Dst, const SrcOp &Src)
Build and insert Dst = G_BITCAST Src.
Definition: MachineIRBuilder.h:641
llvm::MachineIRBuilder::buildMul
MachineInstrBuilder buildMul(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Build and insert Res = G_MUL Op0, Op1.
Definition: MachineIRBuilder.h:1429
llvm::SrcOp::SrcType::Ty_Reg
@ Ty_Reg
llvm::MachineIRBuilder::getInsertPt
MachineBasicBlock::iterator getInsertPt()
Current insertion point for new instructions.
Definition: MachineIRBuilder.h:309
llvm::MachineIRBuilder::buildIntrinsicTrunc
MachineInstrBuilder buildIntrinsicTrunc(const DstOp &Dst, const SrcOp &Src0, Optional< unsigned > Flags=None)
Build and insert Dst = G_INTRINSIC_TRUNC Src0.
Definition: MachineIRBuilder.h:1632
llvm::MachinePointerInfo
This class contains a discriminated union of information about pointers in memory operands,...
Definition: MachineMemOperand.h:37
llvm::MachineIRBuilder::setInstrAndDebugLoc
void setInstrAndDebugLoc(MachineInstr &MI)
Set the insertion point to before MI, and set the debug loc to MI's loc.
Definition: MachineIRBuilder.h:350
llvm::MachineIRBuilder::buildPtrAdd
MachineInstrBuilder buildPtrAdd(const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1)
Build and insert Res = G_PTR_ADD Op0, Op1.
Definition: MachineIRBuilder.cpp:182
llvm::MachineIRBuilder::buildRotateLeft
MachineInstrBuilder buildRotateLeft(const DstOp &Dst, const SrcOp &Src, const SrcOp &Amt)
Build and insert Dst = G_ROTL Src, Amt.
Definition: MachineIRBuilder.h:1866
llvm::MachineIRBuilder::buildFPTOSI
MachineInstrBuilder buildFPTOSI(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_FPTOSI Src0.
Definition: MachineIRBuilder.h:1690
llvm::MachineIRBuilder::buildAtomicRMWNand
MachineInstrBuilder buildAtomicRMWNand(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_NAND Addr, Val, MMO.
Definition: MachineIRBuilder.cpp:886
llvm::MachineIRBuilder::buildSelect
MachineInstrBuilder buildSelect(const DstOp &Res, const SrcOp &Tst, const SrcOp &Op0, const SrcOp &Op1, Optional< unsigned > Flags=None)
Build and insert a Res = G_SELECT Tst, Op0, Op1.
Definition: MachineIRBuilder.cpp:764
llvm::MachineMemOperand::Flags
Flags
Flags values. These may be or'd together.
Definition: MachineMemOperand.h:130
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MachineIRBuilder::buildConstDbgValue
MachineInstrBuilder buildConstDbgValue(const Constant &C, const MDNode *Variable, const MDNode *Expr)
Build and insert a DBG_VALUE instructions specifying that Variable is given by C (suitably modified b...
Definition: MachineIRBuilder.cpp:92
llvm::MachineIRBuilder::buildMemTransferInst
MachineInstrBuilder buildMemTransferInst(unsigned Opcode, const SrcOp &DstPtr, const SrcOp &SrcPtr, const SrcOp &Size, MachineMemOperand &DstMMO, MachineMemOperand &SrcMMO)
Build and insert G_MEMCPY or G_MEMMOVE.
Definition: MachineIRBuilder.h:1828
llvm::MachineIRBuilder::getMBB
const MachineBasicBlock & getMBB() const
Getter for the basic block we currently build.
Definition: MachineIRBuilder.h:295
llvm::MachineInstrBuilder::addMemOperand
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
Definition: MachineInstrBuilder.h:203
llvm::MachineIRBuilder::MachineIRBuilder
MachineIRBuilder(MachineInstr &MI)
Definition: MachineIRBuilder.h:249
llvm::SrcOp::getSrcOpKind
SrcType getSrcOpKind() const
Definition: MachineIRBuilder.h:202
llvm::MachineIRBuilder::MachineIRBuilder
MachineIRBuilder(MachineInstr &MI, GISelChangeObserver &Observer)
Definition: MachineIRBuilder.h:255
llvm::MachineIRBuilder::buildFMaxNumIEEE
MachineInstrBuilder buildFMaxNumIEEE(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Definition: MachineIRBuilder.h:1478
llvm::MachineIRBuilder::buildUAddo
MachineInstrBuilder buildUAddo(const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1)
Build and insert Res, CarryOut = G_UADDO Op0, Op1.
Definition: MachineIRBuilder.h:520
llvm::MachineInstrBuilder::addUse
const MachineInstrBuilder & addUse(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
Definition: MachineInstrBuilder.h:124
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:357
llvm::MachineIRBuilder::buildAtomicRMWFAdd
MachineInstrBuilder buildAtomicRMWFAdd(const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_FADD Addr, Val, MMO.
Definition: MachineIRBuilder.cpp:930
llvm::MDNode
Metadata node.
Definition: Metadata.h:897
llvm::SrcOp::SrcOp
SrcOp(uint64_t V)
Definition: MachineIRBuilder.h:138
llvm::SrcOp::Pred
CmpInst::Predicate Pred
Definition: MachineIRBuilder.h:123
llvm::MachineIRBuilder::buildFMA
MachineInstrBuilder buildFMA(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, const SrcOp &Src2, Optional< unsigned > Flags=None)
Build and insert Res = G_FMA Op0, Op1, Op2.
Definition: MachineIRBuilder.h:1600
llvm::GISelChangeObserver::createdInstr
virtual void createdInstr(MachineInstr &MI)=0
An instruction has been created and inserted into the function.
llvm::MachineIRBuilder::setChangeObserver
void setChangeObserver(GISelChangeObserver &Observer)
Definition: MachineIRBuilder.h:355
llvm::MachineIRBuilder::buildVecReduceFMax
MachineInstrBuilder buildVecReduceFMax(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_FMAX Src.
Definition: MachineIRBuilder.h:1774
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:70
llvm::MachineFunction
Definition: MachineFunction.h:227
llvm::MachineIRBuilder::buildVecReduceSMax
MachineInstrBuilder buildVecReduceSMax(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_SMAX Src.
Definition: MachineIRBuilder.h:1808
llvm::MachineIRBuilderState::Observer
GISelChangeObserver * Observer
Definition: MachineIRBuilder.h:53
llvm::MachineIRBuilder::buildInstr
MachineInstrBuilder buildInstr(unsigned Opcode)
Build and insert <empty> = Opcode <empty>.
Definition: MachineIRBuilder.h:375
llvm::BlockAddress
The address of a basic block.
Definition: Constants.h:847
llvm::SrcOp::addSrcToMIB
void addSrcToMIB(MachineInstrBuilder &MIB) const
Definition: MachineIRBuilder.h:141
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::MachineIRBuilder::buildVecReduceFAdd
MachineInstrBuilder buildVecReduceFAdd(const DstOp &Dst, const SrcOp &ScalarIn, const SrcOp &VecIn)
Build and insert Res = G_VECREDUCE_FADD Src.
Definition: MachineIRBuilder.h:1757
llvm::SrcOp::getReg
Register getReg() const
Definition: MachineIRBuilder.h:171
llvm::FlagsOp::getFlags
Optional< unsigned > getFlags() const
Definition: MachineIRBuilder.h:214
llvm::MachineIRBuilder::insertInstr
MachineInstrBuilder insertInstr(MachineInstrBuilder MIB)
Insert an existing instruction at the insertion point.
Definition: MachineIRBuilder.cpp:45
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:136
llvm::MachineIRBuilder::buildCopy
MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op)
Build and insert Res = COPY Op.
Definition: MachineIRBuilder.cpp:238
llvm::MachineIRBuilder::buildFPTOUI
MachineInstrBuilder buildFPTOUI(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_FPTOUI Src0.
Definition: MachineIRBuilder.h:1685
llvm::MachineIRBuilder::buildFPExt
MachineInstrBuilder buildFPExt(const DstOp &Res, const SrcOp &Op, Optional< unsigned > Flags=None)
Build and insert Res = G_FPEXT Op.
Definition: MachineIRBuilder.h:624
getParent
static const Function * getParent(const Value *V)
Definition: BasicAliasAnalysis.cpp:759
uint32_t
llvm::SrcOp::SrcOp
SrcOp(const CmpInst::Predicate P)
Definition: MachineIRBuilder.h:132
llvm::MachineIRBuilder::buildSequence
void buildSequence(Register Res, ArrayRef< Register > Ops, ArrayRef< uint64_t > Indices)
Build and insert instructions to put Ops together at the specified p Indices to form a larger registe...
Definition: MachineIRBuilder.cpp:543
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::MachineIRBuilder::buildInsert
MachineInstrBuilder buildInsert(const DstOp &Res, const SrcOp &Src, const SrcOp &Op, unsigned Index)
Definition: MachineIRBuilder.cpp:697
llvm::DstOp::DstOp
DstOp(const MachineOperand &Op)
Definition: MachineIRBuilder.h:69
llvm::MachineIRBuilder::buildFLog2
MachineInstrBuilder buildFLog2(const DstOp &Dst, const SrcOp &Src, Optional< unsigned > Flags=None)
Build and insert Dst = G_FLOG2 Src.
Definition: MachineIRBuilder.h:1650
llvm::MachineIRBuilderState::TII
const TargetInstrInfo * TII
Information used to access the description of the opcodes.
Definition: MachineIRBuilder.h:41
llvm::MachineIRBuilder::buildExtract
MachineInstrBuilder buildExtract(const DstOp &Res, const SrcOp &Src, uint64_t Index)
Build and insert Res0, ...
Definition: MachineIRBuilder.cpp:518
llvm::MachineInstrBuilder::addPredicate
const MachineInstrBuilder & addPredicate(CmpInst::Predicate Pred) const
Definition: MachineInstrBuilder.h:258
llvm::MachineIRBuilder::buildVecReduceUMax
MachineInstrBuilder buildVecReduceUMax(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_UMAX Src.
Definition: MachineIRBuilder.h:1818
llvm::GISelChangeObserver
Abstract class that contains various methods for clients to notify about changes.
Definition: GISelChangeObserver.h:29
llvm::MachineIRBuilder::buildSExtInReg
MachineInstrBuilder buildSExtInReg(const DstOp &Res, const SrcOp &Op, int64_t ImmOp)
Build and insert Res = G_SEXT_INREG Op, ImmOp.
Definition: MachineIRBuilder.h:619
llvm::MachineIRBuilder::buildNot
MachineInstrBuilder buildNot(const DstOp &Dst, const SrcOp &Src0)
Build and insert a bitwise not, NegOne = G_CONSTANT -1 Res = G_OR Op0, NegOne.
Definition: MachineIRBuilder.h:1543
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::MachineIRBuilder::buildAnyExt
MachineInstrBuilder buildAnyExt(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_ANYEXT Op0.
Definition: MachineIRBuilder.cpp:416
llvm::MachineIRBuilder::materializePtrAdd
Optional< MachineInstrBuilder > materializePtrAdd(Register &Res, Register Op0, const LLT ValueTy, uint64_t Value)
Materialize and insert Res = G_PTR_ADD Op0, (G_CONSTANT Value)
Definition: MachineIRBuilder.cpp:193
llvm::MachineIRBuilder::buildJumpTable
MachineInstrBuilder buildJumpTable(const LLT PtrTy, unsigned JTI)
Build and insert Res = G_JUMP_TABLE JTI.
Definition: MachineIRBuilder.cpp:159
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::DstOp::DstType
DstType
Definition: MachineIRBuilder.h:66
llvm::MachineIRBuilder::buildFrameIndex
MachineInstrBuilder buildFrameIndex(const DstOp &Res, int Idx)
Build and insert Res = G_FRAME_INDEX Idx.
Definition: MachineIRBuilder.cpp:137
llvm::SrcOp::SrcMIB
MachineInstrBuilder SrcMIB
Definition: MachineIRBuilder.h:121
llvm::MachineIRBuilder::buildSSube
MachineInstrBuilder buildSSube(const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1, const SrcOp &CarryIn)
Build and insert Res, CarryOut = G_SSUBE Op0, Op1, CarryInp.
Definition: MachineIRBuilder.h:581
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::MachineIRBuilder::buildUAdde
MachineInstrBuilder buildUAdde(const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1, const SrcOp &CarryIn)
Build and insert Res, CarryOut = G_UADDE Op0, Op1, CarryIn.
Definition: MachineIRBuilder.h:557
llvm::MachineIRBuilder::buildUITOFP
MachineInstrBuilder buildUITOFP(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_UITOFP Src0.
Definition: MachineIRBuilder.h:1675
llvm::MachineIRBuilder::buildVecReduceSeqFAdd
MachineInstrBuilder buildVecReduceSeqFAdd(const DstOp &Dst, const SrcOp &ScalarIn, const SrcOp &VecIn)
Build and insert Res = G_VECREDUCE_SEQ_FADD ScalarIn, VecIn.
Definition: MachineIRBuilder.h:1735
llvm::MachineIRBuilder::buildVecReduceAnd
MachineInstrBuilder buildVecReduceAnd(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_AND Src.
Definition: MachineIRBuilder.h:1793
llvm::MachineIRBuilder::buildSAddo
MachineInstrBuilder buildSAddo(const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1)
Build and insert Res, CarryOut = G_SADDO Op0, Op1.
Definition: MachineIRBuilder.h:532
llvm::SrcOp::SrcType::Ty_Imm
@ Ty_Imm
llvm::MachineIRBuilder::buildFPow
MachineInstrBuilder buildFPow(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Build and insert Dst = G_FPOW Src0, Src1.
Definition: MachineIRBuilder.h:1662
llvm::MachineIRBuilder::buildTrunc
MachineInstrBuilder buildTrunc(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_TRUNC Op.
Definition: MachineIRBuilder.cpp:737
llvm::MachineIRBuilder::buildMemCpy
MachineInstrBuilder buildMemCpy(const SrcOp &DstPtr, const SrcOp &SrcPtr, const SrcOp &Size, MachineMemOperand &DstMMO, MachineMemOperand &SrcMMO)
Definition: MachineIRBuilder.h:1840
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:521
llvm::MachineIRBuilder::~MachineIRBuilder
virtual ~MachineIRBuilder()=default
llvm::MachineIRBuilder::buildVecReduceMul
MachineInstrBuilder buildVecReduceMul(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_MUL Src.
Definition: MachineIRBuilder.h:1788
llvm::MachineIRBuilderState::DL
DebugLoc DL
Debug location to be set to any instruction we create.
Definition: MachineIRBuilder.h:45
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:314
llvm::MachineIRBuilder::buildSITOFP
MachineInstrBuilder buildSITOFP(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_SITOFP Src0.
Definition: MachineIRBuilder.h:1680
llvm::MachineIRBuilder::buildUndef
MachineInstrBuilder buildUndef(const DstOp &Res)
Build and insert Res = IMPLICIT_DEF.
Definition: MachineIRBuilder.cpp:584
llvm::MachineIRBuilder::buildDirectDbgValue
MachineInstrBuilder buildDirectDbgValue(Register Reg, const MDNode *Variable, const MDNode *Expr)
Build and insert a DBG_VALUE instruction expressing the fact that the associated Variable lives in Re...
Definition: MachineIRBuilder.cpp:52
llvm::MachineIRBuilder::buildVecReduceUMin
MachineInstrBuilder buildVecReduceUMin(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_UMIN Src.
Definition: MachineIRBuilder.h:1823
llvm::MachineIRBuilder::buildAtomicRMWUmin
MachineInstrBuilder buildAtomicRMWUmin(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_UMIN Addr, Val, MMO.
Definition: MachineIRBuilder.cpp:923
llvm::MachineIRBuilder::buildShuffleVector
MachineInstrBuilder buildShuffleVector(const DstOp &Res, const SrcOp &Src1, const SrcOp &Src2, ArrayRef< int > Mask)
Build and insert Res = G_SHUFFLE_VECTOR Src1, Src2, Mask.
Definition: MachineIRBuilder.cpp:671
llvm::SrcOp::SrcOp
SrcOp(int64_t V)
Definition: MachineIRBuilder.h:139
llvm::MachineIRBuilder::buildAtomicRMWXor
MachineInstrBuilder buildAtomicRMWXor(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_XOR Addr, Val, MMO.
Definition: MachineIRBuilder.cpp:899
llvm::MachineIRBuilder::getTII
const TargetInstrInfo & getTII()
Definition: MachineIRBuilder.h:264
llvm::MachineIRBuilder::buildRotateRight
MachineInstrBuilder buildRotateRight(const DstOp &Dst, const SrcOp &Src, const SrcOp &Amt)
Build and insert Dst = G_ROTR Src, Amt.
Definition: MachineIRBuilder.h:1860
llvm::MachineIRBuilderState::MF
MachineFunction * MF
MachineFunction under construction.
Definition: MachineIRBuilder.h:39
llvm::SrcOp::getPredicate
CmpInst::Predicate getPredicate() const
Definition: MachineIRBuilder.h:184
llvm::AMDGPU::Hwreg::Width
Width
Definition: SIDefines.h:403
llvm::MachineIRBuilder::buildVecReduceSeqFMul
MachineInstrBuilder buildVecReduceSeqFMul(const DstOp &Dst, const SrcOp &ScalarIn, const SrcOp &VecIn)
Build and insert Res = G_VECREDUCE_SEQ_FMUL ScalarIn, VecIn.
Definition: MachineIRBuilder.h:1746
llvm::MachineIRBuilder::buildFMinNumIEEE
MachineInstrBuilder buildFMinNumIEEE(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Definition: MachineIRBuilder.h:1472
llvm::MachineIRBuilder::buildAddrSpaceCast
MachineInstrBuilder buildAddrSpaceCast(const DstOp &Dst, const SrcOp &Src)
Build and insert Dst = G_ADDRSPACE_CAST Src.
Definition: MachineIRBuilder.h:646
llvm::MachineIRBuilder::buildBlockAddress
MachineInstrBuilder buildBlockAddress(Register Res, const BlockAddress *BA)
Build and insert Res = G_BLOCK_ADDR BA.
Definition: MachineIRBuilder.cpp:952
llvm::MachineIRBuilder::validateTruncExt
void validateTruncExt(const LLT Dst, const LLT Src, bool IsExtend)
Definition: MachineIRBuilder.cpp:960
llvm::DstOp::getLLTTy
LLT getLLTTy(const MachineRegisterInfo &MRI) const
Definition: MachineIRBuilder.h:87
llvm::MachineIRBuilder::buildAtomicRMWUmax
MachineInstrBuilder buildAtomicRMWUmax(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_UMAX Addr, Val, MMO.
Definition: MachineIRBuilder.cpp:917
llvm::MachineIRBuilder::validateShiftOp
void validateShiftOp(const LLT Res, const LLT Op0, const LLT Op1)
Definition: MachineIRBuilder.cpp:176
llvm::MachineIRBuilder::buildIntrinsic
MachineInstrBuilder buildIntrinsic(Intrinsic::ID ID, ArrayRef< Register > Res, bool HasSideEffects)
Build and insert either a G_INTRINSIC (if HasSideEffects is false) or G_INTRINSIC_W_SIDE_EFFECTS inst...
Definition: MachineIRBuilder.cpp:713
llvm::MachineIRBuilder::buildSSubo
MachineInstrBuilder buildSSubo(const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1)
Build and insert Res, CarryOut = G_SUBO Op0, Op1.
Definition: MachineIRBuilder.h:538
MachineInstrBuilder.h
llvm::MachineIRBuilder::buildFExp2
MachineInstrBuilder buildFExp2(const DstOp &Dst, const SrcOp &Src, Optional< unsigned > Flags=None)
Build and insert Dst = G_FEXP2 Src.
Definition: MachineIRBuilder.h:1656
llvm::DstOp::DstType::Ty_Reg
@ Ty_Reg
llvm::MachineIRBuilder::buildSExt
MachineInstrBuilder buildSExt(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_SEXT Op.
Definition: MachineIRBuilder.cpp:421
llvm::DstOp
Definition: MachineIRBuilder.h:58
llvm::MachineIRBuilder::buildFMaxNum
MachineInstrBuilder buildFMaxNum(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Definition: MachineIRBuilder.h:1466
llvm::MachineIRBuilder::buildSub
MachineInstrBuilder buildSub(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Build and insert Res = G_SUB Op0, Op1.
Definition: MachineIRBuilder.h:1413
llvm::SrcOp::SrcOp
SrcOp(const MachineInstrBuilder &MIB)
Definition: MachineIRBuilder.h:131
llvm::MachineIRBuilder::buildLShr
MachineInstrBuilder buildLShr(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Definition: MachineIRBuilder.h:1490
llvm::MachineIRBuilder::buildFDiv
MachineInstrBuilder buildFDiv(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Build and insert Res = G_FDIV Op0, Op1.
Definition: MachineIRBuilder.h:1593
llvm::MachineIRBuilder::buildMerge
MachineInstrBuilder buildMerge(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_MERGE_VALUES Op0, ...
Definition: MachineIRBuilder.cpp:588
llvm::SrcOp::getLLTTy
LLT getLLTTy(const MachineRegisterInfo &MRI) const
Definition: MachineIRBuilder.h:158
llvm::MachineIRBuilder::buildLoadFromOffset
MachineInstrBuilder buildLoadFromOffset(const DstOp &Dst, const SrcOp &BasePtr, MachineMemOperand &BaseMMO, int64_t Offset)
Helper to create a load from a constant offset given a base address.
Definition: MachineIRBuilder.cpp:371
llvm::MachineIRBuilder::buildAtomicRMWSub
MachineInstrBuilder buildAtomicRMWSub(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_SUB Addr, Val, MMO.
Definition: MachineIRBuilder.cpp:874
llvm::Module::getDataLayout
const DataLayout & getDataLayout() const
Get the data layout for the module's target platform.
Definition: Module.cpp:397
llvm::MachineIRBuilder::buildBuildVectorTrunc
MachineInstrBuilder buildBuildVectorTrunc(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_BUILD_VECTOR_TRUNC Op0, ...
Definition: MachineIRBuilder.cpp:650
llvm::MachineIRBuilder::getBoolExtOp
unsigned getBoolExtOp(bool IsVec, bool IsFP) const
Definition: MachineIRBuilder.cpp:431
llvm::MachineIRBuilder::buildFreeze
MachineInstrBuilder buildFreeze(const DstOp &Dst, const SrcOp &Src)
Build and insert Dst = G_FREEZE Src.
Definition: MachineIRBuilder.h:1371
llvm::MachineIRBuilder::getState
MachineIRBuilderState & getState()
Getter for the State.
Definition: MachineIRBuilder.h:292
llvm::MachineIRBuilder::buildCTTZ_ZERO_UNDEF
MachineInstrBuilder buildCTTZ_ZERO_UNDEF(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_CTTZ_ZERO_UNDEF Op0, Src0.
Definition: MachineIRBuilder.h:1569
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::MachineIRBuilder::buildStore
MachineInstrBuilder buildStore(const SrcOp &Val, const SrcOp &Addr, MachineMemOperand &MMO)
Build and insert G_STORE Val, Addr, MMO.
Definition: MachineIRBuilder.cpp:388
llvm::MachineIRBuilder::buildAtomicRMWXchg
MachineInstrBuilder buildAtomicRMWXchg(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_XCHG Addr, Val, MMO.
Definition: MachineIRBuilder.cpp:862
llvm::MachineIRBuilder::buildAdd
MachineInstrBuilder buildAdd(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Build and insert Res = G_ADD Op0, Op1.
Definition: MachineIRBuilder.h:1396
llvm::MachineIRBuilder::stopObservingChanges
void stopObservingChanges()
Definition: MachineIRBuilder.h:359
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::MachineMemOperand::MONone
@ MONone
Definition: MachineMemOperand.h:132
llvm::Value
LLVM Value Representation.
Definition: Value.h:75
llvm::MachineIRBuilderState::CSEInfo
GISelCSEInfo * CSEInfo
Definition: MachineIRBuilder.h:55
llvm::MachineIRBuilderState::MRI
MachineRegisterInfo * MRI
Information used to verify types are consistent and to create virtual registers.
Definition: MachineIRBuilder.h:43
llvm::SrcOp
Definition: MachineIRBuilder.h:119
llvm::SrcOp::SrcType::Ty_MIB
@ Ty_MIB
llvm::MachineIRBuilder::buildCast
MachineInstrBuilder buildCast(const DstOp &Dst, const SrcOp &Src)
Build and insert an appropriate cast between two registers of equal size.
Definition: MachineIRBuilder.cpp:498
llvm::MachineIRBuilder::buildVecReduceSMin
MachineInstrBuilder buildVecReduceSMin(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_SMIN Src.
Definition: MachineIRBuilder.h:1813
llvm::MachineIRBuilder::buildShuffleSplat
MachineInstrBuilder buildShuffleSplat(const DstOp &Res, const SrcOp &Src)
Build and insert a vector splat of a scalar Src using a G_INSERT_VECTOR_ELT and G_SHUFFLE_VECTOR idio...
Definition: MachineIRBuilder.cpp:659
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:38
llvm::LLT
Definition: LowLevelTypeImpl.h:40