LLVM 17.0.0git
MachineIRBuilder.h
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1//===-- llvm/CodeGen/GlobalISel/MachineIRBuilder.h - MIBuilder --*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8/// \file
9/// This file declares the MachineIRBuilder class.
10/// This is a helper class to build MachineInstr.
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_CODEGEN_GLOBALISEL_MACHINEIRBUILDER_H
14#define LLVM_CODEGEN_GLOBALISEL_MACHINEIRBUILDER_H
15
21#include "llvm/IR/DebugLoc.h"
22#include "llvm/IR/Module.h"
23
24namespace llvm {
25
26// Forward declarations.
27class APInt;
28class BlockAddress;
29class Constant;
30class ConstantFP;
31class ConstantInt;
32class DataLayout;
33class GISelCSEInfo;
34class GlobalValue;
35class TargetRegisterClass;
36class MachineFunction;
37class MachineInstr;
38class TargetInstrInfo;
39class GISelChangeObserver;
40
41/// Class which stores all the state required in a MachineIRBuilder.
42/// Since MachineIRBuilders will only store state in this object, it allows
43/// to transfer BuilderState between different kinds of MachineIRBuilders.
45 /// MachineFunction under construction.
46 MachineFunction *MF = nullptr;
47 /// Information used to access the description of the opcodes.
48 const TargetInstrInfo *TII = nullptr;
49 /// Information used to verify types are consistent and to create virtual registers.
51 /// Debug location to be set to any instruction we create.
53 /// PC sections metadata to be set to any instruction we create.
54 MDNode *PCSections = nullptr;
55
56 /// \name Fields describing the insertion point.
57 /// @{
60 /// @}
61
63
65};
66
67class DstOp {
68 union {
72 };
73
74public:
75 enum class DstType { Ty_LLT, Ty_Reg, Ty_RC };
76 DstOp(unsigned R) : Reg(R), Ty(DstType::Ty_Reg) {}
77 DstOp(Register R) : Reg(R), Ty(DstType::Ty_Reg) {}
78 DstOp(const MachineOperand &Op) : Reg(Op.getReg()), Ty(DstType::Ty_Reg) {}
79 DstOp(const LLT T) : LLTTy(T), Ty(DstType::Ty_LLT) {}
80 DstOp(const TargetRegisterClass *TRC) : RC(TRC), Ty(DstType::Ty_RC) {}
81
83 switch (Ty) {
84 case DstType::Ty_Reg:
85 MIB.addDef(Reg);
86 break;
87 case DstType::Ty_LLT:
88 MIB.addDef(MRI.createGenericVirtualRegister(LLTTy));
89 break;
90 case DstType::Ty_RC:
91 MIB.addDef(MRI.createVirtualRegister(RC));
92 break;
93 }
94 }
95
97 switch (Ty) {
98 case DstType::Ty_RC:
99 return LLT{};
100 case DstType::Ty_LLT:
101 return LLTTy;
102 case DstType::Ty_Reg:
103 return MRI.getType(Reg);
104 }
105 llvm_unreachable("Unrecognised DstOp::DstType enum");
106 }
107
108 Register getReg() const {
109 assert(Ty == DstType::Ty_Reg && "Not a register");
110 return Reg;
111 }
112
114 switch (Ty) {
115 case DstType::Ty_RC:
116 return RC;
117 default:
118 llvm_unreachable("Not a RC Operand");
119 }
120 }
121
122 DstType getDstOpKind() const { return Ty; }
123
124private:
125 DstType Ty;
126};
127
128class SrcOp {
129 union {
133 int64_t Imm;
134 };
135
136public:
138 SrcOp(Register R) : Reg(R), Ty(SrcType::Ty_Reg) {}
139 SrcOp(const MachineOperand &Op) : Reg(Op.getReg()), Ty(SrcType::Ty_Reg) {}
140 SrcOp(const MachineInstrBuilder &MIB) : SrcMIB(MIB), Ty(SrcType::Ty_MIB) {}
142 /// Use of registers held in unsigned integer variables (or more rarely signed
143 /// integers) is no longer permitted to avoid ambiguity with upcoming support
144 /// for immediates.
145 SrcOp(unsigned) = delete;
146 SrcOp(int) = delete;
147 SrcOp(uint64_t V) : Imm(V), Ty(SrcType::Ty_Imm) {}
148 SrcOp(int64_t V) : Imm(V), Ty(SrcType::Ty_Imm) {}
149
151 switch (Ty) {
153 MIB.addPredicate(Pred);
154 break;
155 case SrcType::Ty_Reg:
156 MIB.addUse(Reg);
157 break;
158 case SrcType::Ty_MIB:
159 MIB.addUse(SrcMIB->getOperand(0).getReg());
160 break;
161 case SrcType::Ty_Imm:
162 MIB.addImm(Imm);
163 break;
164 }
165 }
166
168 switch (Ty) {
170 case SrcType::Ty_Imm:
171 llvm_unreachable("Not a register operand");
172 case SrcType::Ty_Reg:
173 return MRI.getType(Reg);
174 case SrcType::Ty_MIB:
175 return MRI.getType(SrcMIB->getOperand(0).getReg());
176 }
177 llvm_unreachable("Unrecognised SrcOp::SrcType enum");
178 }
179
180 Register getReg() const {
181 switch (Ty) {
183 case SrcType::Ty_Imm:
184 llvm_unreachable("Not a register operand");
185 case SrcType::Ty_Reg:
186 return Reg;
187 case SrcType::Ty_MIB:
188 return SrcMIB->getOperand(0).getReg();
189 }
190 llvm_unreachable("Unrecognised SrcOp::SrcType enum");
191 }
192
194 switch (Ty) {
196 return Pred;
197 default:
198 llvm_unreachable("Not a register operand");
199 }
200 }
201
202 int64_t getImm() const {
203 switch (Ty) {
204 case SrcType::Ty_Imm:
205 return Imm;
206 default:
207 llvm_unreachable("Not an immediate");
208 }
209 }
210
211 SrcType getSrcOpKind() const { return Ty; }
212
213private:
214 SrcType Ty;
215};
216
217/// Helper class to build MachineInstr.
218/// It keeps internally the insertion point and debug location for all
219/// the new instructions we want to create.
220/// This information can be modified via the related setters.
222
224
225 unsigned getOpcodeForMerge(const DstOp &DstOp, ArrayRef<SrcOp> SrcOps) const;
226
227protected:
228 void validateTruncExt(const LLT Dst, const LLT Src, bool IsExtend);
229
230 void validateUnaryOp(const LLT Res, const LLT Op0);
231 void validateBinaryOp(const LLT Res, const LLT Op0, const LLT Op1);
232 void validateShiftOp(const LLT Res, const LLT Op0, const LLT Op1);
233
234 void validateSelectOp(const LLT ResTy, const LLT TstTy, const LLT Op0Ty,
235 const LLT Op1Ty);
236
237 void recordInsertion(MachineInstr *InsertedInstr) const {
238 if (State.Observer)
239 State.Observer->createdInstr(*InsertedInstr);
240 }
241
242public:
243 /// Some constructors for easy use.
244 MachineIRBuilder() = default;
246
248 setMF(*MBB.getParent());
249 setInsertPt(MBB, InsPt);
250 }
251
253 MachineIRBuilder(*MI.getParent(), MI.getIterator()) {
254 setInstr(MI);
255 setDebugLoc(MI.getDebugLoc());
256 }
257
260 setChangeObserver(Observer);
261 }
262
263 virtual ~MachineIRBuilder() = default;
264
265 MachineIRBuilder(const MachineIRBuilderState &BState) : State(BState) {}
266
268 assert(State.TII && "TargetInstrInfo is not set");
269 return *State.TII;
270 }
271
272 /// Getter for the function we currently build.
274 assert(State.MF && "MachineFunction is not set");
275 return *State.MF;
276 }
277
278 const MachineFunction &getMF() const {
279 assert(State.MF && "MachineFunction is not set");
280 return *State.MF;
281 }
282
283 const DataLayout &getDataLayout() const {
285 }
286
287 /// Getter for DebugLoc
288 const DebugLoc &getDL() { return State.DL; }
289
290 /// Getter for MRI
291 MachineRegisterInfo *getMRI() { return State.MRI; }
292 const MachineRegisterInfo *getMRI() const { return State.MRI; }
293
294 /// Getter for the State
295 MachineIRBuilderState &getState() { return State; }
296
297 /// Getter for the basic block we currently build.
298 const MachineBasicBlock &getMBB() const {
299 assert(State.MBB && "MachineBasicBlock is not set");
300 return *State.MBB;
301 }
302
304 return const_cast<MachineBasicBlock &>(
305 const_cast<const MachineIRBuilder *>(this)->getMBB());
306 }
307
308 GISelCSEInfo *getCSEInfo() { return State.CSEInfo; }
309 const GISelCSEInfo *getCSEInfo() const { return State.CSEInfo; }
310
311 /// Current insertion point for new instructions.
313
314 /// Set the insertion point before the specified position.
315 /// \pre MBB must be in getMF().
316 /// \pre II must be a valid iterator in MBB.
318 assert(MBB.getParent() == &getMF() &&
319 "Basic block is in a different function");
320 State.MBB = &MBB;
321 State.II = II;
322 }
323
324 /// @}
325
327
328 /// \name Setters for the insertion point.
329 /// @{
330 /// Set the MachineFunction where to build instructions.
331 void setMF(MachineFunction &MF);
332
333 /// Set the insertion point to the end of \p MBB.
334 /// \pre \p MBB must be contained by getMF().
336 State.MBB = &MBB;
337 State.II = MBB.end();
338 assert(&getMF() == MBB.getParent() &&
339 "Basic block is in a different function");
340 }
341
342 /// Set the insertion point to before MI.
343 /// \pre MI must be in getMF().
345 assert(MI.getParent() && "Instruction is not part of a basic block");
346 setMBB(*MI.getParent());
347 State.II = MI.getIterator();
348 setPCSections(MI.getPCSections());
349 }
350 /// @}
351
352 /// Set the insertion point to before MI, and set the debug loc to MI's loc.
353 /// \pre MI must be in getMF().
355 setInstr(MI);
356 setDebugLoc(MI.getDebugLoc());
357 }
358
360 State.Observer = &Observer;
361 }
362
363 void stopObservingChanges() { State.Observer = nullptr; }
364 /// @}
365
366 /// Set the debug location to \p DL for all the next build instructions.
367 void setDebugLoc(const DebugLoc &DL) { this->State.DL = DL; }
368
369 /// Get the current instruction's debug location.
370 const DebugLoc &getDebugLoc() { return State.DL; }
371
372 /// Set the PC sections metadata to \p MD for all the next build instructions.
373 void setPCSections(MDNode *MD) { State.PCSections = MD; }
374
375 /// Get the current instruction's PC sections metadata.
376 MDNode *getPCSections() { return State.PCSections; }
377
378 /// Build and insert <empty> = \p Opcode <empty>.
379 /// The insertion point is the one set by the last call of either
380 /// setBasicBlock or setMI.
381 ///
382 /// \pre setBasicBlock or setMI must have been called.
383 ///
384 /// \return a MachineInstrBuilder for the newly created instruction.
386 return insertInstr(buildInstrNoInsert(Opcode));
387 }
388
389 /// Build but don't insert <empty> = \p Opcode <empty>.
390 ///
391 /// \pre setMF, setBasicBlock or setMI must have been called.
392 ///
393 /// \return a MachineInstrBuilder for the newly created instruction.
395
396 /// Insert an existing instruction at the insertion point.
398
399 /// Build and insert a DBG_VALUE instruction expressing the fact that the
400 /// associated \p Variable lives in \p Reg (suitably modified by \p Expr).
402 const MDNode *Expr);
403
404 /// Build and insert a DBG_VALUE instruction expressing the fact that the
405 /// associated \p Variable lives in memory at \p Reg (suitably modified by \p
406 /// Expr).
408 const MDNode *Variable,
409 const MDNode *Expr);
410
411 /// Build and insert a DBG_VALUE instruction expressing the fact that the
412 /// associated \p Variable lives in the stack slot specified by \p FI
413 /// (suitably modified by \p Expr).
414 MachineInstrBuilder buildFIDbgValue(int FI, const MDNode *Variable,
415 const MDNode *Expr);
416
417 /// Build and insert a DBG_VALUE instructions specifying that \p Variable is
418 /// given by \p C (suitably modified by \p Expr).
420 const MDNode *Variable,
421 const MDNode *Expr);
422
423 /// Build and insert a DBG_LABEL instructions specifying that \p Label is
424 /// given. Convert "llvm.dbg.label Label" to "DBG_LABEL Label".
426
427 /// Build and insert \p Res = G_DYN_STACKALLOC \p Size, \p Align
428 ///
429 /// G_DYN_STACKALLOC does a dynamic stack allocation and writes the address of
430 /// the allocated memory into \p Res.
431 /// \pre setBasicBlock or setMI must have been called.
432 /// \pre \p Res must be a generic virtual register with pointer type.
433 ///
434 /// \return a MachineInstrBuilder for the newly created instruction.
436 Align Alignment);
437
438 /// Build and insert \p Res = G_FRAME_INDEX \p Idx
439 ///
440 /// G_FRAME_INDEX materializes the address of an alloca value or other
441 /// stack-based object.
442 ///
443 /// \pre setBasicBlock or setMI must have been called.
444 /// \pre \p Res must be a generic virtual register with pointer type.
445 ///
446 /// \return a MachineInstrBuilder for the newly created instruction.
448
449 /// Build and insert \p Res = G_GLOBAL_VALUE \p GV
450 ///
451 /// G_GLOBAL_VALUE materializes the address of the specified global
452 /// into \p Res.
453 ///
454 /// \pre setBasicBlock or setMI must have been called.
455 /// \pre \p Res must be a generic virtual register with pointer type
456 /// in the same address space as \p GV.
457 ///
458 /// \return a MachineInstrBuilder for the newly created instruction.
460
461 /// Build and insert \p Res = G_PTR_ADD \p Op0, \p Op1
462 ///
463 /// G_PTR_ADD adds \p Op1 addressible units to the pointer specified by \p Op0,
464 /// storing the resulting pointer in \p Res. Addressible units are typically
465 /// bytes but this can vary between targets.
466 ///
467 /// \pre setBasicBlock or setMI must have been called.
468 /// \pre \p Res and \p Op0 must be generic virtual registers with pointer
469 /// type.
470 /// \pre \p Op1 must be a generic virtual register with scalar type.
471 ///
472 /// \return a MachineInstrBuilder for the newly created instruction.
473 MachineInstrBuilder buildPtrAdd(const DstOp &Res, const SrcOp &Op0,
474 const SrcOp &Op1);
475
476 /// Materialize and insert \p Res = G_PTR_ADD \p Op0, (G_CONSTANT \p Value)
477 ///
478 /// G_PTR_ADD adds \p Value bytes to the pointer specified by \p Op0,
479 /// storing the resulting pointer in \p Res. If \p Value is zero then no
480 /// G_PTR_ADD or G_CONSTANT will be created and \pre Op0 will be assigned to
481 /// \p Res.
482 ///
483 /// \pre setBasicBlock or setMI must have been called.
484 /// \pre \p Op0 must be a generic virtual register with pointer type.
485 /// \pre \p ValueTy must be a scalar type.
486 /// \pre \p Res must be 0. This is to detect confusion between
487 /// materializePtrAdd() and buildPtrAdd().
488 /// \post \p Res will either be a new generic virtual register of the same
489 /// type as \p Op0 or \p Op0 itself.
490 ///
491 /// \return a MachineInstrBuilder for the newly created instruction.
492 std::optional<MachineInstrBuilder> materializePtrAdd(Register &Res,
493 Register Op0,
494 const LLT ValueTy,
496
497 /// Build and insert \p Res = G_PTRMASK \p Op0, \p Op1
499 const SrcOp &Op1) {
500 return buildInstr(TargetOpcode::G_PTRMASK, {Res}, {Op0, Op1});
501 }
502
503 /// Build and insert \p Res = G_PTRMASK \p Op0, \p G_CONSTANT (1 << NumBits) - 1
504 ///
505 /// This clears the low bits of a pointer operand without destroying its
506 /// pointer properties. This has the effect of rounding the address *down* to
507 /// a specified alignment in bits.
508 ///
509 /// \pre setBasicBlock or setMI must have been called.
510 /// \pre \p Res and \p Op0 must be generic virtual registers with pointer
511 /// type.
512 /// \pre \p NumBits must be an integer representing the number of low bits to
513 /// be cleared in \p Op0.
514 ///
515 /// \return a MachineInstrBuilder for the newly created instruction.
516 MachineInstrBuilder buildMaskLowPtrBits(const DstOp &Res, const SrcOp &Op0,
517 uint32_t NumBits);
518
519 /// Build and insert
520 /// a, b, ..., x = G_UNMERGE_VALUES \p Op0
521 /// \p Res = G_BUILD_VECTOR a, b, ..., x, undef, ..., undef
522 ///
523 /// Pad \p Op0 with undef elements to match number of elements in \p Res.
524 ///
525 /// \pre setBasicBlock or setMI must have been called.
526 /// \pre \p Res and \p Op0 must be generic virtual registers with vector type,
527 /// same vector element type and Op0 must have fewer elements then Res.
528 ///
529 /// \return a MachineInstrBuilder for the newly created build vector instr.
531 const SrcOp &Op0);
532
533 /// Build and insert
534 /// a, b, ..., x, y, z = G_UNMERGE_VALUES \p Op0
535 /// \p Res = G_BUILD_VECTOR a, b, ..., x
536 ///
537 /// Delete trailing elements in \p Op0 to match number of elements in \p Res.
538 ///
539 /// \pre setBasicBlock or setMI must have been called.
540 /// \pre \p Res and \p Op0 must be generic virtual registers with vector type,
541 /// same vector element type and Op0 must have more elements then Res.
542 ///
543 /// \return a MachineInstrBuilder for the newly created build vector instr.
545 const SrcOp &Op0);
546
547 /// Build and insert \p Res, \p CarryOut = G_UADDO \p Op0, \p Op1
548 ///
549 /// G_UADDO sets \p Res to \p Op0 + \p Op1 (truncated to the bit width) and
550 /// sets \p CarryOut to 1 if the result overflowed in unsigned arithmetic.
551 ///
552 /// \pre setBasicBlock or setMI must have been called.
553 /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers with the
554 /// same scalar type.
555 ////\pre \p CarryOut must be generic virtual register with scalar type
556 ///(typically s1)
557 ///
558 /// \return The newly created instruction.
559 MachineInstrBuilder buildUAddo(const DstOp &Res, const DstOp &CarryOut,
560 const SrcOp &Op0, const SrcOp &Op1) {
561 return buildInstr(TargetOpcode::G_UADDO, {Res, CarryOut}, {Op0, Op1});
562 }
563
564 /// Build and insert \p Res, \p CarryOut = G_USUBO \p Op0, \p Op1
565 MachineInstrBuilder buildUSubo(const DstOp &Res, const DstOp &CarryOut,
566 const SrcOp &Op0, const SrcOp &Op1) {
567 return buildInstr(TargetOpcode::G_USUBO, {Res, CarryOut}, {Op0, Op1});
568 }
569
570 /// Build and insert \p Res, \p CarryOut = G_SADDO \p Op0, \p Op1
571 MachineInstrBuilder buildSAddo(const DstOp &Res, const DstOp &CarryOut,
572 const SrcOp &Op0, const SrcOp &Op1) {
573 return buildInstr(TargetOpcode::G_SADDO, {Res, CarryOut}, {Op0, Op1});
574 }
575
576 /// Build and insert \p Res, \p CarryOut = G_SUBO \p Op0, \p Op1
577 MachineInstrBuilder buildSSubo(const DstOp &Res, const DstOp &CarryOut,
578 const SrcOp &Op0, const SrcOp &Op1) {
579 return buildInstr(TargetOpcode::G_SSUBO, {Res, CarryOut}, {Op0, Op1});
580 }
581
582 /// Build and insert \p Res, \p CarryOut = G_UADDE \p Op0,
583 /// \p Op1, \p CarryIn
584 ///
585 /// G_UADDE sets \p Res to \p Op0 + \p Op1 + \p CarryIn (truncated to the bit
586 /// width) and sets \p CarryOut to 1 if the result overflowed in unsigned
587 /// arithmetic.
588 ///
589 /// \pre setBasicBlock or setMI must have been called.
590 /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
591 /// with the same scalar type.
592 /// \pre \p CarryOut and \p CarryIn must be generic virtual
593 /// registers with the same scalar type (typically s1)
594 ///
595 /// \return The newly created instruction.
596 MachineInstrBuilder buildUAdde(const DstOp &Res, const DstOp &CarryOut,
597 const SrcOp &Op0, const SrcOp &Op1,
598 const SrcOp &CarryIn) {
599 return buildInstr(TargetOpcode::G_UADDE, {Res, CarryOut},
600 {Op0, Op1, CarryIn});
601 }
602
603 /// Build and insert \p Res, \p CarryOut = G_USUBE \p Op0, \p Op1, \p CarryInp
604 MachineInstrBuilder buildUSube(const DstOp &Res, const DstOp &CarryOut,
605 const SrcOp &Op0, const SrcOp &Op1,
606 const SrcOp &CarryIn) {
607 return buildInstr(TargetOpcode::G_USUBE, {Res, CarryOut},
608 {Op0, Op1, CarryIn});
609 }
610
611 /// Build and insert \p Res, \p CarryOut = G_SADDE \p Op0, \p Op1, \p CarryInp
612 MachineInstrBuilder buildSAdde(const DstOp &Res, const DstOp &CarryOut,
613 const SrcOp &Op0, const SrcOp &Op1,
614 const SrcOp &CarryIn) {
615 return buildInstr(TargetOpcode::G_SADDE, {Res, CarryOut},
616 {Op0, Op1, CarryIn});
617 }
618
619 /// Build and insert \p Res, \p CarryOut = G_SSUBE \p Op0, \p Op1, \p CarryInp
620 MachineInstrBuilder buildSSube(const DstOp &Res, const DstOp &CarryOut,
621 const SrcOp &Op0, const SrcOp &Op1,
622 const SrcOp &CarryIn) {
623 return buildInstr(TargetOpcode::G_SSUBE, {Res, CarryOut},
624 {Op0, Op1, CarryIn});
625 }
626
627 /// Build and insert \p Res = G_ANYEXT \p Op0
628 ///
629 /// G_ANYEXT produces a register of the specified width, with bits 0 to
630 /// sizeof(\p Ty) * 8 set to \p Op. The remaining bits are unspecified
631 /// (i.e. this is neither zero nor sign-extension). For a vector register,
632 /// each element is extended individually.
633 ///
634 /// \pre setBasicBlock or setMI must have been called.
635 /// \pre \p Res must be a generic virtual register with scalar or vector type.
636 /// \pre \p Op must be a generic virtual register with scalar or vector type.
637 /// \pre \p Op must be smaller than \p Res
638 ///
639 /// \return The newly created instruction.
640
641 MachineInstrBuilder buildAnyExt(const DstOp &Res, const SrcOp &Op);
642
643 /// Build and insert \p Res = G_SEXT \p Op
644 ///
645 /// G_SEXT produces a register of the specified width, with bits 0 to
646 /// sizeof(\p Ty) * 8 set to \p Op. The remaining bits are duplicated from the
647 /// high bit of \p Op (i.e. 2s-complement sign extended).
648 ///
649 /// \pre setBasicBlock or setMI must have been called.
650 /// \pre \p Res must be a generic virtual register with scalar or vector type.
651 /// \pre \p Op must be a generic virtual register with scalar or vector type.
652 /// \pre \p Op must be smaller than \p Res
653 ///
654 /// \return The newly created instruction.
655 MachineInstrBuilder buildSExt(const DstOp &Res, const SrcOp &Op);
656
657 /// Build and insert \p Res = G_SEXT_INREG \p Op, ImmOp
658 MachineInstrBuilder buildSExtInReg(const DstOp &Res, const SrcOp &Op, int64_t ImmOp) {
659 return buildInstr(TargetOpcode::G_SEXT_INREG, {Res}, {Op, SrcOp(ImmOp)});
660 }
661
662 /// Build and insert \p Res = G_FPEXT \p Op
664 std::optional<unsigned> Flags = std::nullopt) {
665 return buildInstr(TargetOpcode::G_FPEXT, {Res}, {Op}, Flags);
666 }
667
668 /// Build and insert a G_PTRTOINT instruction.
670 return buildInstr(TargetOpcode::G_PTRTOINT, {Dst}, {Src});
671 }
672
673 /// Build and insert a G_INTTOPTR instruction.
675 return buildInstr(TargetOpcode::G_INTTOPTR, {Dst}, {Src});
676 }
677
678 /// Build and insert \p Dst = G_BITCAST \p Src
679 MachineInstrBuilder buildBitcast(const DstOp &Dst, const SrcOp &Src) {
680 return buildInstr(TargetOpcode::G_BITCAST, {Dst}, {Src});
681 }
682
683 /// Build and insert \p Dst = G_ADDRSPACE_CAST \p Src
685 return buildInstr(TargetOpcode::G_ADDRSPACE_CAST, {Dst}, {Src});
686 }
687
688 /// \return The opcode of the extension the target wants to use for boolean
689 /// values.
690 unsigned getBoolExtOp(bool IsVec, bool IsFP) const;
691
692 // Build and insert \p Res = G_ANYEXT \p Op, \p Res = G_SEXT \p Op, or \p Res
693 // = G_ZEXT \p Op depending on how the target wants to extend boolean values.
694 MachineInstrBuilder buildBoolExt(const DstOp &Res, const SrcOp &Op,
695 bool IsFP);
696
697 // Build and insert \p Res = G_SEXT_INREG \p Op, 1 or \p Res = G_AND \p Op, 1,
698 // or COPY depending on how the target wants to extend boolean values, using
699 // the original register size.
700 MachineInstrBuilder buildBoolExtInReg(const DstOp &Res, const SrcOp &Op,
701 bool IsVector,
702 bool IsFP);
703
704 /// Build and insert \p Res = G_ZEXT \p Op
705 ///
706 /// G_ZEXT produces a register of the specified width, with bits 0 to
707 /// sizeof(\p Ty) * 8 set to \p Op. The remaining bits are 0. For a vector
708 /// register, each element is extended individually.
709 ///
710 /// \pre setBasicBlock or setMI must have been called.
711 /// \pre \p Res must be a generic virtual register with scalar or vector type.
712 /// \pre \p Op must be a generic virtual register with scalar or vector type.
713 /// \pre \p Op must be smaller than \p Res
714 ///
715 /// \return The newly created instruction.
716 MachineInstrBuilder buildZExt(const DstOp &Res, const SrcOp &Op);
717
718 /// Build and insert \p Res = G_SEXT \p Op, \p Res = G_TRUNC \p Op, or
719 /// \p Res = COPY \p Op depending on the differing sizes of \p Res and \p Op.
720 /// ///
721 /// \pre setBasicBlock or setMI must have been called.
722 /// \pre \p Res must be a generic virtual register with scalar or vector type.
723 /// \pre \p Op must be a generic virtual register with scalar or vector type.
724 ///
725 /// \return The newly created instruction.
726 MachineInstrBuilder buildSExtOrTrunc(const DstOp &Res, const SrcOp &Op);
727
728 /// Build and insert \p Res = G_ZEXT \p Op, \p Res = G_TRUNC \p Op, or
729 /// \p Res = COPY \p Op depending on the differing sizes of \p Res and \p Op.
730 /// ///
731 /// \pre setBasicBlock or setMI must have been called.
732 /// \pre \p Res must be a generic virtual register with scalar or vector type.
733 /// \pre \p Op must be a generic virtual register with scalar or vector type.
734 ///
735 /// \return The newly created instruction.
736 MachineInstrBuilder buildZExtOrTrunc(const DstOp &Res, const SrcOp &Op);
737
738 // Build and insert \p Res = G_ANYEXT \p Op, \p Res = G_TRUNC \p Op, or
739 /// \p Res = COPY \p Op depending on the differing sizes of \p Res and \p Op.
740 /// ///
741 /// \pre setBasicBlock or setMI must have been called.
742 /// \pre \p Res must be a generic virtual register with scalar or vector type.
743 /// \pre \p Op must be a generic virtual register with scalar or vector type.
744 ///
745 /// \return The newly created instruction.
746 MachineInstrBuilder buildAnyExtOrTrunc(const DstOp &Res, const SrcOp &Op);
747
748 /// Build and insert \p Res = \p ExtOpc, \p Res = G_TRUNC \p
749 /// Op, or \p Res = COPY \p Op depending on the differing sizes of \p Res and
750 /// \p Op.
751 /// ///
752 /// \pre setBasicBlock or setMI must have been called.
753 /// \pre \p Res must be a generic virtual register with scalar or vector type.
754 /// \pre \p Op must be a generic virtual register with scalar or vector type.
755 ///
756 /// \return The newly created instruction.
757 MachineInstrBuilder buildExtOrTrunc(unsigned ExtOpc, const DstOp &Res,
758 const SrcOp &Op);
759
760 /// Build and inserts \p Res = \p G_AND \p Op, \p LowBitsSet(ImmOp)
761 /// Since there is no G_ZEXT_INREG like G_SEXT_INREG, the instruction is
762 /// emulated using G_AND.
763 MachineInstrBuilder buildZExtInReg(const DstOp &Res, const SrcOp &Op,
764 int64_t ImmOp);
765
766 /// Build and insert an appropriate cast between two registers of equal size.
767 MachineInstrBuilder buildCast(const DstOp &Dst, const SrcOp &Src);
768
769 /// Build and insert G_BR \p Dest
770 ///
771 /// G_BR is an unconditional branch to \p Dest.
772 ///
773 /// \pre setBasicBlock or setMI must have been called.
774 ///
775 /// \return a MachineInstrBuilder for the newly created instruction.
777
778 /// Build and insert G_BRCOND \p Tst, \p Dest
779 ///
780 /// G_BRCOND is a conditional branch to \p Dest.
781 ///
782 /// \pre setBasicBlock or setMI must have been called.
783 /// \pre \p Tst must be a generic virtual register with scalar
784 /// type. At the beginning of legalization, this will be a single
785 /// bit (s1). Targets with interesting flags registers may change
786 /// this. For a wider type, whether the branch is taken must only
787 /// depend on bit 0 (for now).
788 ///
789 /// \return The newly created instruction.
791
792 /// Build and insert G_BRINDIRECT \p Tgt
793 ///
794 /// G_BRINDIRECT is an indirect branch to \p Tgt.
795 ///
796 /// \pre setBasicBlock or setMI must have been called.
797 /// \pre \p Tgt must be a generic virtual register with pointer type.
798 ///
799 /// \return a MachineInstrBuilder for the newly created instruction.
801
802 /// Build and insert G_BRJT \p TablePtr, \p JTI, \p IndexReg
803 ///
804 /// G_BRJT is a jump table branch using a table base pointer \p TablePtr,
805 /// jump table index \p JTI and index \p IndexReg
806 ///
807 /// \pre setBasicBlock or setMI must have been called.
808 /// \pre \p TablePtr must be a generic virtual register with pointer type.
809 /// \pre \p JTI must be be a jump table index.
810 /// \pre \p IndexReg must be a generic virtual register with pointer type.
811 ///
812 /// \return a MachineInstrBuilder for the newly created instruction.
813 MachineInstrBuilder buildBrJT(Register TablePtr, unsigned JTI,
814 Register IndexReg);
815
816 /// Build and insert \p Res = G_CONSTANT \p Val
817 ///
818 /// G_CONSTANT is an integer constant with the specified size and value. \p
819 /// Val will be extended or truncated to the size of \p Reg.
820 ///
821 /// \pre setBasicBlock or setMI must have been called.
822 /// \pre \p Res must be a generic virtual register with scalar or pointer
823 /// type.
824 ///
825 /// \return The newly created instruction.
826 virtual MachineInstrBuilder buildConstant(const DstOp &Res,
827 const ConstantInt &Val);
828
829 /// Build and insert \p Res = G_CONSTANT \p Val
830 ///
831 /// G_CONSTANT is an integer constant with the specified size and value.
832 ///
833 /// \pre setBasicBlock or setMI must have been called.
834 /// \pre \p Res must be a generic virtual register with scalar type.
835 ///
836 /// \return The newly created instruction.
837 MachineInstrBuilder buildConstant(const DstOp &Res, int64_t Val);
838 MachineInstrBuilder buildConstant(const DstOp &Res, const APInt &Val);
839
840 /// Build and insert \p Res = G_FCONSTANT \p Val
841 ///
842 /// G_FCONSTANT is a floating-point constant with the specified size and
843 /// value.
844 ///
845 /// \pre setBasicBlock or setMI must have been called.
846 /// \pre \p Res must be a generic virtual register with scalar type.
847 ///
848 /// \return The newly created instruction.
849 virtual MachineInstrBuilder buildFConstant(const DstOp &Res,
850 const ConstantFP &Val);
851
852 MachineInstrBuilder buildFConstant(const DstOp &Res, double Val);
853 MachineInstrBuilder buildFConstant(const DstOp &Res, const APFloat &Val);
854
855 /// Build and insert \p Res = COPY Op
856 ///
857 /// Register-to-register COPY sets \p Res to \p Op.
858 ///
859 /// \pre setBasicBlock or setMI must have been called.
860 ///
861 /// \return a MachineInstrBuilder for the newly created instruction.
862 MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op);
863
864
865 /// Build and insert G_ASSERT_SEXT, G_ASSERT_ZEXT, or G_ASSERT_ALIGN
866 ///
867 /// \return a MachineInstrBuilder for the newly created instruction.
869 const SrcOp &Op, unsigned Val) {
870 return buildInstr(Opc, Res, Op).addImm(Val);
871 }
872
873 /// Build and insert \p Res = G_ASSERT_ZEXT Op, Size
874 ///
875 /// \return a MachineInstrBuilder for the newly created instruction.
877 unsigned Size) {
878 return buildAssertInstr(TargetOpcode::G_ASSERT_ZEXT, Res, Op, Size);
879 }
880
881 /// Build and insert \p Res = G_ASSERT_SEXT Op, Size
882 ///
883 /// \return a MachineInstrBuilder for the newly created instruction.
885 unsigned Size) {
886 return buildAssertInstr(TargetOpcode::G_ASSERT_SEXT, Res, Op, Size);
887 }
888
889 /// Build and insert \p Res = G_ASSERT_ALIGN Op, AlignVal
890 ///
891 /// \return a MachineInstrBuilder for the newly created instruction.
893 Align AlignVal) {
894 return buildAssertInstr(TargetOpcode::G_ASSERT_ALIGN, Res, Op,
895 AlignVal.value());
896 }
897
898 /// Build and insert `Res = G_LOAD Addr, MMO`.
899 ///
900 /// Loads the value stored at \p Addr. Puts the result in \p Res.
901 ///
902 /// \pre setBasicBlock or setMI must have been called.
903 /// \pre \p Res must be a generic virtual register.
904 /// \pre \p Addr must be a generic virtual register with pointer type.
905 ///
906 /// \return a MachineInstrBuilder for the newly created instruction.
908 MachineMemOperand &MMO) {
909 return buildLoadInstr(TargetOpcode::G_LOAD, Res, Addr, MMO);
910 }
911
912 /// Build and insert a G_LOAD instruction, while constructing the
913 /// MachineMemOperand.
915 buildLoad(const DstOp &Res, const SrcOp &Addr, MachinePointerInfo PtrInfo,
916 Align Alignment,
918 const AAMDNodes &AAInfo = AAMDNodes());
919
920 /// Build and insert `Res = <opcode> Addr, MMO`.
921 ///
922 /// Loads the value stored at \p Addr. Puts the result in \p Res.
923 ///
924 /// \pre setBasicBlock or setMI must have been called.
925 /// \pre \p Res must be a generic virtual register.
926 /// \pre \p Addr must be a generic virtual register with pointer type.
927 ///
928 /// \return a MachineInstrBuilder for the newly created instruction.
929 MachineInstrBuilder buildLoadInstr(unsigned Opcode, const DstOp &Res,
930 const SrcOp &Addr, MachineMemOperand &MMO);
931
932 /// Helper to create a load from a constant offset given a base address. Load
933 /// the type of \p Dst from \p Offset from the given base address and memory
934 /// operand.
936 const SrcOp &BasePtr,
937 MachineMemOperand &BaseMMO,
938 int64_t Offset);
939
940 /// Build and insert `G_STORE Val, Addr, MMO`.
941 ///
942 /// Stores the value \p Val to \p Addr.
943 ///
944 /// \pre setBasicBlock or setMI must have been called.
945 /// \pre \p Val must be a generic virtual register.
946 /// \pre \p Addr must be a generic virtual register with pointer type.
947 ///
948 /// \return a MachineInstrBuilder for the newly created instruction.
949 MachineInstrBuilder buildStore(const SrcOp &Val, const SrcOp &Addr,
950 MachineMemOperand &MMO);
951
952 /// Build and insert a G_STORE instruction, while constructing the
953 /// MachineMemOperand.
955 buildStore(const SrcOp &Val, const SrcOp &Addr, MachinePointerInfo PtrInfo,
956 Align Alignment,
958 const AAMDNodes &AAInfo = AAMDNodes());
959
960 /// Build and insert `Res0, ... = G_EXTRACT Src, Idx0`.
961 ///
962 /// \pre setBasicBlock or setMI must have been called.
963 /// \pre \p Res and \p Src must be generic virtual registers.
964 ///
965 /// \return a MachineInstrBuilder for the newly created instruction.
966 MachineInstrBuilder buildExtract(const DstOp &Res, const SrcOp &Src, uint64_t Index);
967
968 /// Build and insert \p Res = IMPLICIT_DEF.
970
971 /// Build and insert \p Res = G_MERGE_VALUES \p Op0, ...
972 ///
973 /// G_MERGE_VALUES combines the input elements contiguously into a larger
974 /// register. It should only be used when the destination register is not a
975 /// vector.
976 ///
977 /// \pre setBasicBlock or setMI must have been called.
978 /// \pre The entire register \p Res (and no more) must be covered by the input
979 /// registers.
980 /// \pre The type of all \p Ops registers must be identical.
981 ///
982 /// \return a MachineInstrBuilder for the newly created instruction.
985
986 /// Build and insert \p Res = G_MERGE_VALUES \p Op0, ...
987 /// or \p Res = G_BUILD_VECTOR \p Op0, ...
988 /// or \p Res = G_CONCAT_VECTORS \p Op0, ...
989 ///
990 /// G_MERGE_VALUES combines the input elements contiguously into a larger
991 /// register. It is used when the destination register is not a vector.
992 /// G_BUILD_VECTOR combines scalar inputs into a vector register.
993 /// G_CONCAT_VECTORS combines vector inputs into a vector register.
994 ///
995 /// \pre setBasicBlock or setMI must have been called.
996 /// \pre The entire register \p Res (and no more) must be covered by the input
997 /// registers.
998 /// \pre The type of all \p Ops registers must be identical.
999 ///
1000 /// \return a MachineInstrBuilder for the newly created instruction. The
1001 /// opcode of the new instruction will depend on the types of both
1002 /// the destination and the sources.
1004 ArrayRef<Register> Ops);
1006 std::initializer_list<SrcOp> Ops);
1007
1008 /// Build and insert \p Res0, ... = G_UNMERGE_VALUES \p Op
1009 ///
1010 /// G_UNMERGE_VALUES splits contiguous bits of the input into multiple
1011 ///
1012 /// \pre setBasicBlock or setMI must have been called.
1013 /// \pre The entire register \p Res (and no more) must be covered by the input
1014 /// registers.
1015 /// \pre The type of all \p Res registers must be identical.
1016 ///
1017 /// \return a MachineInstrBuilder for the newly created instruction.
1020
1021 /// Build and insert an unmerge of \p Res sized pieces to cover \p Op
1022 MachineInstrBuilder buildUnmerge(LLT Res, const SrcOp &Op);
1023
1024 /// Build and insert \p Res = G_BUILD_VECTOR \p Op0, ...
1025 ///
1026 /// G_BUILD_VECTOR creates a vector value from multiple scalar registers.
1027 /// \pre setBasicBlock or setMI must have been called.
1028 /// \pre The entire register \p Res (and no more) must be covered by the
1029 /// input scalar registers.
1030 /// \pre The type of all \p Ops registers must be identical.
1031 ///
1032 /// \return a MachineInstrBuilder for the newly created instruction.
1034 ArrayRef<Register> Ops);
1035
1036 /// Build and insert \p Res = G_BUILD_VECTOR \p Op0, ... where each OpN is
1037 /// built with G_CONSTANT.
1039 ArrayRef<APInt> Ops);
1040
1041 /// Build and insert \p Res = G_BUILD_VECTOR with \p Src replicated to fill
1042 /// the number of elements
1044 const SrcOp &Src);
1045
1046 /// Build and insert \p Res = G_BUILD_VECTOR_TRUNC \p Op0, ...
1047 ///
1048 /// G_BUILD_VECTOR_TRUNC creates a vector value from multiple scalar registers
1049 /// which have types larger than the destination vector element type, and
1050 /// truncates the values to fit.
1051 ///
1052 /// If the operands given are already the same size as the vector elt type,
1053 /// then this method will instead create a G_BUILD_VECTOR instruction.
1054 ///
1055 /// \pre setBasicBlock or setMI must have been called.
1056 /// \pre The type of all \p Ops registers must be identical.
1057 ///
1058 /// \return a MachineInstrBuilder for the newly created instruction.
1060 ArrayRef<Register> Ops);
1061
1062 /// Build and insert a vector splat of a scalar \p Src using a
1063 /// G_INSERT_VECTOR_ELT and G_SHUFFLE_VECTOR idiom.
1064 ///
1065 /// \pre setBasicBlock or setMI must have been called.
1066 /// \pre \p Src must have the same type as the element type of \p Dst
1067 ///
1068 /// \return a MachineInstrBuilder for the newly created instruction.
1069 MachineInstrBuilder buildShuffleSplat(const DstOp &Res, const SrcOp &Src);
1070
1071 /// Build and insert \p Res = G_SHUFFLE_VECTOR \p Src1, \p Src2, \p Mask
1072 ///
1073 /// \pre setBasicBlock or setMI must have been called.
1074 ///
1075 /// \return a MachineInstrBuilder for the newly created instruction.
1076 MachineInstrBuilder buildShuffleVector(const DstOp &Res, const SrcOp &Src1,
1077 const SrcOp &Src2, ArrayRef<int> Mask);
1078
1079 /// Build and insert \p Res = G_CONCAT_VECTORS \p Op0, ...
1080 ///
1081 /// G_CONCAT_VECTORS creates a vector from the concatenation of 2 or more
1082 /// vectors.
1083 ///
1084 /// \pre setBasicBlock or setMI must have been called.
1085 /// \pre The entire register \p Res (and no more) must be covered by the input
1086 /// registers.
1087 /// \pre The type of all source operands must be identical.
1088 ///
1089 /// \return a MachineInstrBuilder for the newly created instruction.
1091 ArrayRef<Register> Ops);
1092
1093 MachineInstrBuilder buildInsert(const DstOp &Res, const SrcOp &Src,
1094 const SrcOp &Op, unsigned Index);
1095
1096 /// Build and insert either a G_INTRINSIC (if \p HasSideEffects is false) or
1097 /// G_INTRINSIC_W_SIDE_EFFECTS instruction. Its first operand will be the
1098 /// result register definition unless \p Reg is NoReg (== 0). The second
1099 /// operand will be the intrinsic's ID.
1100 ///
1101 /// Callers are expected to add the required definitions and uses afterwards.
1102 ///
1103 /// \pre setBasicBlock or setMI must have been called.
1104 ///
1105 /// \return a MachineInstrBuilder for the newly created instruction.
1107 bool HasSideEffects);
1109 bool HasSideEffects);
1110
1111 /// Build and insert \p Res = G_FPTRUNC \p Op
1112 ///
1113 /// G_FPTRUNC converts a floating-point value into one with a smaller type.
1114 ///
1115 /// \pre setBasicBlock or setMI must have been called.
1116 /// \pre \p Res must be a generic virtual register with scalar or vector type.
1117 /// \pre \p Op must be a generic virtual register with scalar or vector type.
1118 /// \pre \p Res must be smaller than \p Op
1119 ///
1120 /// \return The newly created instruction.
1122 buildFPTrunc(const DstOp &Res, const SrcOp &Op,
1123 std::optional<unsigned> Flags = std::nullopt);
1124
1125 /// Build and insert \p Res = G_TRUNC \p Op
1126 ///
1127 /// G_TRUNC extracts the low bits of a type. For a vector type each element is
1128 /// truncated independently before being packed into the destination.
1129 ///
1130 /// \pre setBasicBlock or setMI must have been called.
1131 /// \pre \p Res must be a generic virtual register with scalar or vector type.
1132 /// \pre \p Op must be a generic virtual register with scalar or vector type.
1133 /// \pre \p Res must be smaller than \p Op
1134 ///
1135 /// \return The newly created instruction.
1136 MachineInstrBuilder buildTrunc(const DstOp &Res, const SrcOp &Op);
1137
1138 /// Build and insert a \p Res = G_ICMP \p Pred, \p Op0, \p Op1
1139 ///
1140 /// \pre setBasicBlock or setMI must have been called.
1141
1142 /// \pre \p Res must be a generic virtual register with scalar or
1143 /// vector type. Typically this starts as s1 or <N x s1>.
1144 /// \pre \p Op0 and Op1 must be generic virtual registers with the
1145 /// same number of elements as \p Res. If \p Res is a scalar,
1146 /// \p Op0 must be either a scalar or pointer.
1147 /// \pre \p Pred must be an integer predicate.
1148 ///
1149 /// \return a MachineInstrBuilder for the newly created instruction.
1151 const SrcOp &Op0, const SrcOp &Op1);
1152
1153 /// Build and insert a \p Res = G_FCMP \p Pred\p Op0, \p Op1
1154 ///
1155 /// \pre setBasicBlock or setMI must have been called.
1156
1157 /// \pre \p Res must be a generic virtual register with scalar or
1158 /// vector type. Typically this starts as s1 or <N x s1>.
1159 /// \pre \p Op0 and Op1 must be generic virtual registers with the
1160 /// same number of elements as \p Res (or scalar, if \p Res is
1161 /// scalar).
1162 /// \pre \p Pred must be a floating-point predicate.
1163 ///
1164 /// \return a MachineInstrBuilder for the newly created instruction.
1166 const SrcOp &Op0, const SrcOp &Op1,
1167 std::optional<unsigned> Flags = std::nullopt);
1168
1169 /// Build and insert a \p Res = G_SELECT \p Tst, \p Op0, \p Op1
1170 ///
1171 /// \pre setBasicBlock or setMI must have been called.
1172 /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1173 /// with the same type.
1174 /// \pre \p Tst must be a generic virtual register with scalar, pointer or
1175 /// vector type. If vector then it must have the same number of
1176 /// elements as the other parameters.
1177 ///
1178 /// \return a MachineInstrBuilder for the newly created instruction.
1179 MachineInstrBuilder buildSelect(const DstOp &Res, const SrcOp &Tst,
1180 const SrcOp &Op0, const SrcOp &Op1,
1181 std::optional<unsigned> Flags = std::nullopt);
1182
1183 /// Build and insert \p Res = G_INSERT_VECTOR_ELT \p Val,
1184 /// \p Elt, \p Idx
1185 ///
1186 /// \pre setBasicBlock or setMI must have been called.
1187 /// \pre \p Res and \p Val must be a generic virtual register
1188 // with the same vector type.
1189 /// \pre \p Elt and \p Idx must be a generic virtual register
1190 /// with scalar type.
1191 ///
1192 /// \return The newly created instruction.
1194 const SrcOp &Val,
1195 const SrcOp &Elt,
1196 const SrcOp &Idx);
1197
1198 /// Build and insert \p Res = G_EXTRACT_VECTOR_ELT \p Val, \p Idx
1199 ///
1200 /// \pre setBasicBlock or setMI must have been called.
1201 /// \pre \p Res must be a generic virtual register with scalar type.
1202 /// \pre \p Val must be a generic virtual register with vector type.
1203 ///
1204 /// \return The newly created instruction.
1206 const SrcOp &Val,
1207 const int Idx) {
1208 return buildExtractVectorElement(Res, Val,
1210 }
1211
1212 /// Build and insert \p Res = G_EXTRACT_VECTOR_ELT \p Val, \p Idx
1213 ///
1214 /// \pre setBasicBlock or setMI must have been called.
1215 /// \pre \p Res must be a generic virtual register with scalar type.
1216 /// \pre \p Val must be a generic virtual register with vector type.
1217 /// \pre \p Idx must be a generic virtual register with scalar type.
1218 ///
1219 /// \return The newly created instruction.
1221 const SrcOp &Val,
1222 const SrcOp &Idx);
1223
1224 /// Build and insert `OldValRes<def>, SuccessRes<def> =
1225 /// G_ATOMIC_CMPXCHG_WITH_SUCCESS Addr, CmpVal, NewVal, MMO`.
1226 ///
1227 /// Atomically replace the value at \p Addr with \p NewVal if it is currently
1228 /// \p CmpVal otherwise leaves it unchanged. Puts the original value from \p
1229 /// Addr in \p Res, along with an s1 indicating whether it was replaced.
1230 ///
1231 /// \pre setBasicBlock or setMI must have been called.
1232 /// \pre \p OldValRes must be a generic virtual register of scalar type.
1233 /// \pre \p SuccessRes must be a generic virtual register of scalar type. It
1234 /// will be assigned 0 on failure and 1 on success.
1235 /// \pre \p Addr must be a generic virtual register with pointer type.
1236 /// \pre \p OldValRes, \p CmpVal, and \p NewVal must be generic virtual
1237 /// registers of the same type.
1238 ///
1239 /// \return a MachineInstrBuilder for the newly created instruction.
1241 buildAtomicCmpXchgWithSuccess(Register OldValRes, Register SuccessRes,
1242 Register Addr, Register CmpVal, Register NewVal,
1243 MachineMemOperand &MMO);
1244
1245 /// Build and insert `OldValRes<def> = G_ATOMIC_CMPXCHG Addr, CmpVal, NewVal,
1246 /// MMO`.
1247 ///
1248 /// Atomically replace the value at \p Addr with \p NewVal if it is currently
1249 /// \p CmpVal otherwise leaves it unchanged. Puts the original value from \p
1250 /// Addr in \p Res.
1251 ///
1252 /// \pre setBasicBlock or setMI must have been called.
1253 /// \pre \p OldValRes must be a generic virtual register of scalar type.
1254 /// \pre \p Addr must be a generic virtual register with pointer type.
1255 /// \pre \p OldValRes, \p CmpVal, and \p NewVal must be generic virtual
1256 /// registers of the same type.
1257 ///
1258 /// \return a MachineInstrBuilder for the newly created instruction.
1260 Register CmpVal, Register NewVal,
1261 MachineMemOperand &MMO);
1262
1263 /// Build and insert `OldValRes<def> = G_ATOMICRMW_<Opcode> Addr, Val, MMO`.
1264 ///
1265 /// Atomically read-modify-update the value at \p Addr with \p Val. Puts the
1266 /// original value from \p Addr in \p OldValRes. The modification is
1267 /// determined by the opcode.
1268 ///
1269 /// \pre setBasicBlock or setMI must have been called.
1270 /// \pre \p OldValRes must be a generic virtual register.
1271 /// \pre \p Addr must be a generic virtual register with pointer type.
1272 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1273 /// same type.
1274 ///
1275 /// \return a MachineInstrBuilder for the newly created instruction.
1276 MachineInstrBuilder buildAtomicRMW(unsigned Opcode, const DstOp &OldValRes,
1277 const SrcOp &Addr, const SrcOp &Val,
1278 MachineMemOperand &MMO);
1279
1280 /// Build and insert `OldValRes<def> = G_ATOMICRMW_XCHG Addr, Val, MMO`.
1281 ///
1282 /// Atomically replace the value at \p Addr with \p Val. Puts the original
1283 /// value from \p Addr in \p OldValRes.
1284 ///
1285 /// \pre setBasicBlock or setMI must have been called.
1286 /// \pre \p OldValRes must be a generic virtual register.
1287 /// \pre \p Addr must be a generic virtual register with pointer type.
1288 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1289 /// same type.
1290 ///
1291 /// \return a MachineInstrBuilder for the newly created instruction.
1293 Register Val, MachineMemOperand &MMO);
1294
1295 /// Build and insert `OldValRes<def> = G_ATOMICRMW_ADD Addr, Val, MMO`.
1296 ///
1297 /// Atomically replace the value at \p Addr with the addition of \p Val and
1298 /// the original value. Puts the original value from \p Addr in \p OldValRes.
1299 ///
1300 /// \pre setBasicBlock or setMI must have been called.
1301 /// \pre \p OldValRes must be a generic virtual register.
1302 /// \pre \p Addr must be a generic virtual register with pointer type.
1303 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1304 /// same type.
1305 ///
1306 /// \return a MachineInstrBuilder for the newly created instruction.
1308 Register Val, MachineMemOperand &MMO);
1309
1310 /// Build and insert `OldValRes<def> = G_ATOMICRMW_SUB Addr, Val, MMO`.
1311 ///
1312 /// Atomically replace the value at \p Addr with the subtraction of \p Val and
1313 /// the original value. Puts the original value from \p Addr in \p OldValRes.
1314 ///
1315 /// \pre setBasicBlock or setMI must have been called.
1316 /// \pre \p OldValRes must be a generic virtual register.
1317 /// \pre \p Addr must be a generic virtual register with pointer type.
1318 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1319 /// same type.
1320 ///
1321 /// \return a MachineInstrBuilder for the newly created instruction.
1323 Register Val, MachineMemOperand &MMO);
1324
1325 /// Build and insert `OldValRes<def> = G_ATOMICRMW_AND Addr, Val, MMO`.
1326 ///
1327 /// Atomically replace the value at \p Addr with the bitwise and of \p Val and
1328 /// the original value. Puts the original value from \p Addr in \p OldValRes.
1329 ///
1330 /// \pre setBasicBlock or setMI must have been called.
1331 /// \pre \p OldValRes must be a generic virtual register.
1332 /// \pre \p Addr must be a generic virtual register with pointer type.
1333 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1334 /// same type.
1335 ///
1336 /// \return a MachineInstrBuilder for the newly created instruction.
1338 Register Val, MachineMemOperand &MMO);
1339
1340 /// Build and insert `OldValRes<def> = G_ATOMICRMW_NAND Addr, Val, MMO`.
1341 ///
1342 /// Atomically replace the value at \p Addr with the bitwise nand of \p Val
1343 /// and the original value. Puts the original value from \p Addr in \p
1344 /// OldValRes.
1345 ///
1346 /// \pre setBasicBlock or setMI must have been called.
1347 /// \pre \p OldValRes must be a generic virtual register.
1348 /// \pre \p Addr must be a generic virtual register with pointer type.
1349 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1350 /// same type.
1351 ///
1352 /// \return a MachineInstrBuilder for the newly created instruction.
1354 Register Val, MachineMemOperand &MMO);
1355
1356 /// Build and insert `OldValRes<def> = G_ATOMICRMW_OR Addr, Val, MMO`.
1357 ///
1358 /// Atomically replace the value at \p Addr with the bitwise or of \p Val and
1359 /// the original value. Puts the original value from \p Addr in \p OldValRes.
1360 ///
1361 /// \pre setBasicBlock or setMI must have been called.
1362 /// \pre \p OldValRes must be a generic virtual register.
1363 /// \pre \p Addr must be a generic virtual register with pointer type.
1364 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1365 /// same type.
1366 ///
1367 /// \return a MachineInstrBuilder for the newly created instruction.
1369 Register Val, MachineMemOperand &MMO);
1370
1371 /// Build and insert `OldValRes<def> = G_ATOMICRMW_XOR Addr, Val, MMO`.
1372 ///
1373 /// Atomically replace the value at \p Addr with the bitwise xor of \p Val and
1374 /// the original value. Puts the original value from \p Addr in \p OldValRes.
1375 ///
1376 /// \pre setBasicBlock or setMI must have been called.
1377 /// \pre \p OldValRes must be a generic virtual register.
1378 /// \pre \p Addr must be a generic virtual register with pointer type.
1379 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1380 /// same type.
1381 ///
1382 /// \return a MachineInstrBuilder for the newly created instruction.
1384 Register Val, MachineMemOperand &MMO);
1385
1386 /// Build and insert `OldValRes<def> = G_ATOMICRMW_MAX Addr, Val, MMO`.
1387 ///
1388 /// Atomically replace the value at \p Addr with the signed maximum of \p
1389 /// Val and the original value. Puts the original value from \p Addr in \p
1390 /// OldValRes.
1391 ///
1392 /// \pre setBasicBlock or setMI must have been called.
1393 /// \pre \p OldValRes must be a generic virtual register.
1394 /// \pre \p Addr must be a generic virtual register with pointer type.
1395 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1396 /// same type.
1397 ///
1398 /// \return a MachineInstrBuilder for the newly created instruction.
1400 Register Val, MachineMemOperand &MMO);
1401
1402 /// Build and insert `OldValRes<def> = G_ATOMICRMW_MIN Addr, Val, MMO`.
1403 ///
1404 /// Atomically replace the value at \p Addr with the signed minimum of \p
1405 /// Val and the original value. Puts the original value from \p Addr in \p
1406 /// OldValRes.
1407 ///
1408 /// \pre setBasicBlock or setMI must have been called.
1409 /// \pre \p OldValRes must be a generic virtual register.
1410 /// \pre \p Addr must be a generic virtual register with pointer type.
1411 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1412 /// same type.
1413 ///
1414 /// \return a MachineInstrBuilder for the newly created instruction.
1416 Register Val, MachineMemOperand &MMO);
1417
1418 /// Build and insert `OldValRes<def> = G_ATOMICRMW_UMAX Addr, Val, MMO`.
1419 ///
1420 /// Atomically replace the value at \p Addr with the unsigned maximum of \p
1421 /// Val and the original value. Puts the original value from \p Addr in \p
1422 /// OldValRes.
1423 ///
1424 /// \pre setBasicBlock or setMI must have been called.
1425 /// \pre \p OldValRes must be a generic virtual register.
1426 /// \pre \p Addr must be a generic virtual register with pointer type.
1427 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1428 /// same type.
1429 ///
1430 /// \return a MachineInstrBuilder for the newly created instruction.
1432 Register Val, MachineMemOperand &MMO);
1433
1434 /// Build and insert `OldValRes<def> = G_ATOMICRMW_UMIN Addr, Val, MMO`.
1435 ///
1436 /// Atomically replace the value at \p Addr with the unsigned minimum of \p
1437 /// Val and the original value. Puts the original value from \p Addr in \p
1438 /// OldValRes.
1439 ///
1440 /// \pre setBasicBlock or setMI must have been called.
1441 /// \pre \p OldValRes must be a generic virtual register.
1442 /// \pre \p Addr must be a generic virtual register with pointer type.
1443 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1444 /// same type.
1445 ///
1446 /// \return a MachineInstrBuilder for the newly created instruction.
1448 Register Val, MachineMemOperand &MMO);
1449
1450 /// Build and insert `OldValRes<def> = G_ATOMICRMW_FADD Addr, Val, MMO`.
1452 const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val,
1453 MachineMemOperand &MMO);
1454
1455 /// Build and insert `OldValRes<def> = G_ATOMICRMW_FSUB Addr, Val, MMO`.
1457 const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val,
1458 MachineMemOperand &MMO);
1459
1460 /// Build and insert `OldValRes<def> = G_ATOMICRMW_FMAX Addr, Val, MMO`.
1461 ///
1462 /// Atomically replace the value at \p Addr with the floating point maximum of
1463 /// \p Val and the original value. Puts the original value from \p Addr in \p
1464 /// OldValRes.
1465 ///
1466 /// \pre setBasicBlock or setMI must have been called.
1467 /// \pre \p OldValRes must be a generic virtual register.
1468 /// \pre \p Addr must be a generic virtual register with pointer type.
1469 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1470 /// same type.
1471 ///
1472 /// \return a MachineInstrBuilder for the newly created instruction.
1474 const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val,
1475 MachineMemOperand &MMO);
1476
1477 /// Build and insert `OldValRes<def> = G_ATOMICRMW_FMIN Addr, Val, MMO`.
1478 ///
1479 /// Atomically replace the value at \p Addr with the floating point minimum of
1480 /// \p Val and the original value. Puts the original value from \p Addr in \p
1481 /// OldValRes.
1482 ///
1483 /// \pre setBasicBlock or setMI must have been called.
1484 /// \pre \p OldValRes must be a generic virtual register.
1485 /// \pre \p Addr must be a generic virtual register with pointer type.
1486 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1487 /// same type.
1488 ///
1489 /// \return a MachineInstrBuilder for the newly created instruction.
1491 const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val,
1492 MachineMemOperand &MMO);
1493
1494 /// Build and insert `G_FENCE Ordering, Scope`.
1495 MachineInstrBuilder buildFence(unsigned Ordering, unsigned Scope);
1496
1497 /// Build and insert \p Dst = G_FREEZE \p Src
1498 MachineInstrBuilder buildFreeze(const DstOp &Dst, const SrcOp &Src) {
1499 return buildInstr(TargetOpcode::G_FREEZE, {Dst}, {Src});
1500 }
1501
1502 /// Build and insert \p Res = G_BLOCK_ADDR \p BA
1503 ///
1504 /// G_BLOCK_ADDR computes the address of a basic block.
1505 ///
1506 /// \pre setBasicBlock or setMI must have been called.
1507 /// \pre \p Res must be a generic virtual register of a pointer type.
1508 ///
1509 /// \return The newly created instruction.
1511
1512 /// Build and insert \p Res = G_ADD \p Op0, \p Op1
1513 ///
1514 /// G_ADD sets \p Res to the sum of integer parameters \p Op0 and \p Op1,
1515 /// truncated to their width.
1516 ///
1517 /// \pre setBasicBlock or setMI must have been called.
1518 /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1519 /// with the same (scalar or vector) type).
1520 ///
1521 /// \return a MachineInstrBuilder for the newly created instruction.
1522
1523 MachineInstrBuilder buildAdd(const DstOp &Dst, const SrcOp &Src0,
1524 const SrcOp &Src1,
1525 std::optional<unsigned> Flags = std::nullopt) {
1526 return buildInstr(TargetOpcode::G_ADD, {Dst}, {Src0, Src1}, Flags);
1527 }
1528
1529 /// Build and insert \p Res = G_SUB \p Op0, \p Op1
1530 ///
1531 /// G_SUB sets \p Res to the difference of integer parameters \p Op0 and
1532 /// \p Op1, truncated to their width.
1533 ///
1534 /// \pre setBasicBlock or setMI must have been called.
1535 /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1536 /// with the same (scalar or vector) type).
1537 ///
1538 /// \return a MachineInstrBuilder for the newly created instruction.
1539
1540 MachineInstrBuilder buildSub(const DstOp &Dst, const SrcOp &Src0,
1541 const SrcOp &Src1,
1542 std::optional<unsigned> Flags = std::nullopt) {
1543 return buildInstr(TargetOpcode::G_SUB, {Dst}, {Src0, Src1}, Flags);
1544 }
1545
1546 /// Build and insert \p Res = G_MUL \p Op0, \p Op1
1547 ///
1548 /// G_MUL sets \p Res to the product of integer parameters \p Op0 and \p Op1,
1549 /// truncated to their width.
1550 ///
1551 /// \pre setBasicBlock or setMI must have been called.
1552 /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1553 /// with the same (scalar or vector) type).
1554 ///
1555 /// \return a MachineInstrBuilder for the newly created instruction.
1556 MachineInstrBuilder buildMul(const DstOp &Dst, const SrcOp &Src0,
1557 const SrcOp &Src1,
1558 std::optional<unsigned> Flags = std::nullopt) {
1559 return buildInstr(TargetOpcode::G_MUL, {Dst}, {Src0, Src1}, Flags);
1560 }
1561
1563 const SrcOp &Src1,
1564 std::optional<unsigned> Flags = std::nullopt) {
1565 return buildInstr(TargetOpcode::G_UMULH, {Dst}, {Src0, Src1}, Flags);
1566 }
1567
1569 const SrcOp &Src1,
1570 std::optional<unsigned> Flags = std::nullopt) {
1571 return buildInstr(TargetOpcode::G_SMULH, {Dst}, {Src0, Src1}, Flags);
1572 }
1573
1574 /// Build and insert \p Res = G_UREM \p Op0, \p Op1
1575 MachineInstrBuilder buildURem(const DstOp &Dst, const SrcOp &Src0,
1576 const SrcOp &Src1,
1577 std::optional<unsigned> Flags = std::nullopt) {
1578 return buildInstr(TargetOpcode::G_UREM, {Dst}, {Src0, Src1}, Flags);
1579 }
1580
1581 MachineInstrBuilder buildFMul(const DstOp &Dst, const SrcOp &Src0,
1582 const SrcOp &Src1,
1583 std::optional<unsigned> Flags = std::nullopt) {
1584 return buildInstr(TargetOpcode::G_FMUL, {Dst}, {Src0, Src1}, Flags);
1585 }
1586
1588 buildFMinNum(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1,
1589 std::optional<unsigned> Flags = std::nullopt) {
1590 return buildInstr(TargetOpcode::G_FMINNUM, {Dst}, {Src0, Src1}, Flags);
1591 }
1592
1594 buildFMaxNum(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1,
1595 std::optional<unsigned> Flags = std::nullopt) {
1596 return buildInstr(TargetOpcode::G_FMAXNUM, {Dst}, {Src0, Src1}, Flags);
1597 }
1598
1600 buildFMinNumIEEE(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1,
1601 std::optional<unsigned> Flags = std::nullopt) {
1602 return buildInstr(TargetOpcode::G_FMINNUM_IEEE, {Dst}, {Src0, Src1}, Flags);
1603 }
1604
1606 buildFMaxNumIEEE(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1,
1607 std::optional<unsigned> Flags = std::nullopt) {
1608 return buildInstr(TargetOpcode::G_FMAXNUM_IEEE, {Dst}, {Src0, Src1}, Flags);
1609 }
1610
1611 MachineInstrBuilder buildShl(const DstOp &Dst, const SrcOp &Src0,
1612 const SrcOp &Src1,
1613 std::optional<unsigned> Flags = std::nullopt) {
1614 return buildInstr(TargetOpcode::G_SHL, {Dst}, {Src0, Src1}, Flags);
1615 }
1616
1617 MachineInstrBuilder buildLShr(const DstOp &Dst, const SrcOp &Src0,
1618 const SrcOp &Src1,
1619 std::optional<unsigned> Flags = std::nullopt) {
1620 return buildInstr(TargetOpcode::G_LSHR, {Dst}, {Src0, Src1}, Flags);
1621 }
1622
1623 MachineInstrBuilder buildAShr(const DstOp &Dst, const SrcOp &Src0,
1624 const SrcOp &Src1,
1625 std::optional<unsigned> Flags = std::nullopt) {
1626 return buildInstr(TargetOpcode::G_ASHR, {Dst}, {Src0, Src1}, Flags);
1627 }
1628
1629 /// Build and insert \p Res = G_AND \p Op0, \p Op1
1630 ///
1631 /// G_AND sets \p Res to the bitwise and of integer parameters \p Op0 and \p
1632 /// Op1.
1633 ///
1634 /// \pre setBasicBlock or setMI must have been called.
1635 /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1636 /// with the same (scalar or vector) type).
1637 ///
1638 /// \return a MachineInstrBuilder for the newly created instruction.
1639
1640 MachineInstrBuilder buildAnd(const DstOp &Dst, const SrcOp &Src0,
1641 const SrcOp &Src1) {
1642 return buildInstr(TargetOpcode::G_AND, {Dst}, {Src0, Src1});
1643 }
1644
1645 /// Build and insert \p Res = G_OR \p Op0, \p Op1
1646 ///
1647 /// G_OR sets \p Res to the bitwise or of integer parameters \p Op0 and \p
1648 /// Op1.
1649 ///
1650 /// \pre setBasicBlock or setMI must have been called.
1651 /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1652 /// with the same (scalar or vector) type).
1653 ///
1654 /// \return a MachineInstrBuilder for the newly created instruction.
1655 MachineInstrBuilder buildOr(const DstOp &Dst, const SrcOp &Src0,
1656 const SrcOp &Src1,
1657 std::optional<unsigned> Flags = std::nullopt) {
1658 return buildInstr(TargetOpcode::G_OR, {Dst}, {Src0, Src1}, Flags);
1659 }
1660
1661 /// Build and insert \p Res = G_XOR \p Op0, \p Op1
1662 MachineInstrBuilder buildXor(const DstOp &Dst, const SrcOp &Src0,
1663 const SrcOp &Src1) {
1664 return buildInstr(TargetOpcode::G_XOR, {Dst}, {Src0, Src1});
1665 }
1666
1667 /// Build and insert a bitwise not,
1668 /// \p NegOne = G_CONSTANT -1
1669 /// \p Res = G_OR \p Op0, NegOne
1670 MachineInstrBuilder buildNot(const DstOp &Dst, const SrcOp &Src0) {
1671 auto NegOne = buildConstant(Dst.getLLTTy(*getMRI()), -1);
1672 return buildInstr(TargetOpcode::G_XOR, {Dst}, {Src0, NegOne});
1673 }
1674
1675 /// Build and insert integer negation
1676 /// \p Zero = G_CONSTANT 0
1677 /// \p Res = G_SUB Zero, \p Op0
1678 MachineInstrBuilder buildNeg(const DstOp &Dst, const SrcOp &Src0) {
1679 auto Zero = buildConstant(Dst.getLLTTy(*getMRI()), 0);
1680 return buildInstr(TargetOpcode::G_SUB, {Dst}, {Zero, Src0});
1681 }
1682
1683 /// Build and insert \p Res = G_CTPOP \p Op0, \p Src0
1684 MachineInstrBuilder buildCTPOP(const DstOp &Dst, const SrcOp &Src0) {
1685 return buildInstr(TargetOpcode::G_CTPOP, {Dst}, {Src0});
1686 }
1687
1688 /// Build and insert \p Res = G_CTLZ \p Op0, \p Src0
1689 MachineInstrBuilder buildCTLZ(const DstOp &Dst, const SrcOp &Src0) {
1690 return buildInstr(TargetOpcode::G_CTLZ, {Dst}, {Src0});
1691 }
1692
1693 /// Build and insert \p Res = G_CTLZ_ZERO_UNDEF \p Op0, \p Src0
1695 return buildInstr(TargetOpcode::G_CTLZ_ZERO_UNDEF, {Dst}, {Src0});
1696 }
1697
1698 /// Build and insert \p Res = G_CTTZ \p Op0, \p Src0
1699 MachineInstrBuilder buildCTTZ(const DstOp &Dst, const SrcOp &Src0) {
1700 return buildInstr(TargetOpcode::G_CTTZ, {Dst}, {Src0});
1701 }
1702
1703 /// Build and insert \p Res = G_CTTZ_ZERO_UNDEF \p Op0, \p Src0
1705 return buildInstr(TargetOpcode::G_CTTZ_ZERO_UNDEF, {Dst}, {Src0});
1706 }
1707
1708 /// Build and insert \p Dst = G_BSWAP \p Src0
1709 MachineInstrBuilder buildBSwap(const DstOp &Dst, const SrcOp &Src0) {
1710 return buildInstr(TargetOpcode::G_BSWAP, {Dst}, {Src0});
1711 }
1712
1713 /// Build and insert \p Res = G_FADD \p Op0, \p Op1
1714 MachineInstrBuilder buildFAdd(const DstOp &Dst, const SrcOp &Src0,
1715 const SrcOp &Src1,
1716 std::optional<unsigned> Flags = std::nullopt) {
1717 return buildInstr(TargetOpcode::G_FADD, {Dst}, {Src0, Src1}, Flags);
1718 }
1719
1720 /// Build and insert \p Res = G_STRICT_FADD \p Op0, \p Op1
1722 buildStrictFAdd(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1,
1723 std::optional<unsigned> Flags = std::nullopt) {
1724 return buildInstr(TargetOpcode::G_STRICT_FADD, {Dst}, {Src0, Src1}, Flags);
1725 }
1726
1727 /// Build and insert \p Res = G_FSUB \p Op0, \p Op1
1728 MachineInstrBuilder buildFSub(const DstOp &Dst, const SrcOp &Src0,
1729 const SrcOp &Src1,
1730 std::optional<unsigned> Flags = std::nullopt) {
1731 return buildInstr(TargetOpcode::G_FSUB, {Dst}, {Src0, Src1}, Flags);
1732 }
1733
1734 /// Build and insert \p Res = G_FDIV \p Op0, \p Op1
1735 MachineInstrBuilder buildFDiv(const DstOp &Dst, const SrcOp &Src0,
1736 const SrcOp &Src1,
1737 std::optional<unsigned> Flags = std::nullopt) {
1738 return buildInstr(TargetOpcode::G_FDIV, {Dst}, {Src0, Src1}, Flags);
1739 }
1740
1741 /// Build and insert \p Res = G_FMA \p Op0, \p Op1, \p Op2
1742 MachineInstrBuilder buildFMA(const DstOp &Dst, const SrcOp &Src0,
1743 const SrcOp &Src1, const SrcOp &Src2,
1744 std::optional<unsigned> Flags = std::nullopt) {
1745 return buildInstr(TargetOpcode::G_FMA, {Dst}, {Src0, Src1, Src2}, Flags);
1746 }
1747
1748 /// Build and insert \p Res = G_FMAD \p Op0, \p Op1, \p Op2
1749 MachineInstrBuilder buildFMAD(const DstOp &Dst, const SrcOp &Src0,
1750 const SrcOp &Src1, const SrcOp &Src2,
1751 std::optional<unsigned> Flags = std::nullopt) {
1752 return buildInstr(TargetOpcode::G_FMAD, {Dst}, {Src0, Src1, Src2}, Flags);
1753 }
1754
1755 /// Build and insert \p Res = G_FNEG \p Op0
1756 MachineInstrBuilder buildFNeg(const DstOp &Dst, const SrcOp &Src0,
1757 std::optional<unsigned> Flags = std::nullopt) {
1758 return buildInstr(TargetOpcode::G_FNEG, {Dst}, {Src0}, Flags);
1759 }
1760
1761 /// Build and insert \p Res = G_FABS \p Op0
1762 MachineInstrBuilder buildFAbs(const DstOp &Dst, const SrcOp &Src0,
1763 std::optional<unsigned> Flags = std::nullopt) {
1764 return buildInstr(TargetOpcode::G_FABS, {Dst}, {Src0}, Flags);
1765 }
1766
1767 /// Build and insert \p Dst = G_FCANONICALIZE \p Src0
1769 buildFCanonicalize(const DstOp &Dst, const SrcOp &Src0,
1770 std::optional<unsigned> Flags = std::nullopt) {
1771 return buildInstr(TargetOpcode::G_FCANONICALIZE, {Dst}, {Src0}, Flags);
1772 }
1773
1774 /// Build and insert \p Dst = G_INTRINSIC_TRUNC \p Src0
1776 buildIntrinsicTrunc(const DstOp &Dst, const SrcOp &Src0,
1777 std::optional<unsigned> Flags = std::nullopt) {
1778 return buildInstr(TargetOpcode::G_INTRINSIC_TRUNC, {Dst}, {Src0}, Flags);
1779 }
1780
1781 /// Build and insert \p Res = GFFLOOR \p Op0, \p Op1
1783 buildFFloor(const DstOp &Dst, const SrcOp &Src0,
1784 std::optional<unsigned> Flags = std::nullopt) {
1785 return buildInstr(TargetOpcode::G_FFLOOR, {Dst}, {Src0}, Flags);
1786 }
1787
1788 /// Build and insert \p Dst = G_FLOG \p Src
1790 std::optional<unsigned> Flags = std::nullopt) {
1791 return buildInstr(TargetOpcode::G_FLOG, {Dst}, {Src}, Flags);
1792 }
1793
1794 /// Build and insert \p Dst = G_FLOG2 \p Src
1796 std::optional<unsigned> Flags = std::nullopt) {
1797 return buildInstr(TargetOpcode::G_FLOG2, {Dst}, {Src}, Flags);
1798 }
1799
1800 /// Build and insert \p Dst = G_FEXP2 \p Src
1802 std::optional<unsigned> Flags = std::nullopt) {
1803 return buildInstr(TargetOpcode::G_FEXP2, {Dst}, {Src}, Flags);
1804 }
1805
1806 /// Build and insert \p Dst = G_FPOW \p Src0, \p Src1
1807 MachineInstrBuilder buildFPow(const DstOp &Dst, const SrcOp &Src0,
1808 const SrcOp &Src1,
1809 std::optional<unsigned> Flags = std::nullopt) {
1810 return buildInstr(TargetOpcode::G_FPOW, {Dst}, {Src0, Src1}, Flags);
1811 }
1812
1813 /// Build and insert \p Res = G_FCOPYSIGN \p Op0, \p Op1
1815 const SrcOp &Src1) {
1816 return buildInstr(TargetOpcode::G_FCOPYSIGN, {Dst}, {Src0, Src1});
1817 }
1818
1819 /// Build and insert \p Res = G_UITOFP \p Src0
1820 MachineInstrBuilder buildUITOFP(const DstOp &Dst, const SrcOp &Src0) {
1821 return buildInstr(TargetOpcode::G_UITOFP, {Dst}, {Src0});
1822 }
1823
1824 /// Build and insert \p Res = G_SITOFP \p Src0
1825 MachineInstrBuilder buildSITOFP(const DstOp &Dst, const SrcOp &Src0) {
1826 return buildInstr(TargetOpcode::G_SITOFP, {Dst}, {Src0});
1827 }
1828
1829 /// Build and insert \p Res = G_FPTOUI \p Src0
1830 MachineInstrBuilder buildFPTOUI(const DstOp &Dst, const SrcOp &Src0) {
1831 return buildInstr(TargetOpcode::G_FPTOUI, {Dst}, {Src0});
1832 }
1833
1834 /// Build and insert \p Res = G_FPTOSI \p Src0
1835 MachineInstrBuilder buildFPTOSI(const DstOp &Dst, const SrcOp &Src0) {
1836 return buildInstr(TargetOpcode::G_FPTOSI, {Dst}, {Src0});
1837 }
1838
1839 /// Build and insert \p Res = G_SMIN \p Op0, \p Op1
1840 MachineInstrBuilder buildSMin(const DstOp &Dst, const SrcOp &Src0,
1841 const SrcOp &Src1) {
1842 return buildInstr(TargetOpcode::G_SMIN, {Dst}, {Src0, Src1});
1843 }
1844
1845 /// Build and insert \p Res = G_SMAX \p Op0, \p Op1
1846 MachineInstrBuilder buildSMax(const DstOp &Dst, const SrcOp &Src0,
1847 const SrcOp &Src1) {
1848 return buildInstr(TargetOpcode::G_SMAX, {Dst}, {Src0, Src1});
1849 }
1850
1851 /// Build and insert \p Res = G_UMIN \p Op0, \p Op1
1852 MachineInstrBuilder buildUMin(const DstOp &Dst, const SrcOp &Src0,
1853 const SrcOp &Src1) {
1854 return buildInstr(TargetOpcode::G_UMIN, {Dst}, {Src0, Src1});
1855 }
1856
1857 /// Build and insert \p Res = G_UMAX \p Op0, \p Op1
1858 MachineInstrBuilder buildUMax(const DstOp &Dst, const SrcOp &Src0,
1859 const SrcOp &Src1) {
1860 return buildInstr(TargetOpcode::G_UMAX, {Dst}, {Src0, Src1});
1861 }
1862
1863 /// Build and insert \p Dst = G_ABS \p Src
1864 MachineInstrBuilder buildAbs(const DstOp &Dst, const SrcOp &Src) {
1865 return buildInstr(TargetOpcode::G_ABS, {Dst}, {Src});
1866 }
1867
1868 /// Build and insert \p Res = G_JUMP_TABLE \p JTI
1869 ///
1870 /// G_JUMP_TABLE sets \p Res to the address of the jump table specified by
1871 /// the jump table index \p JTI.
1872 ///
1873 /// \return a MachineInstrBuilder for the newly created instruction.
1874 MachineInstrBuilder buildJumpTable(const LLT PtrTy, unsigned JTI);
1875
1876 /// Build and insert \p Res = G_VECREDUCE_SEQ_FADD \p ScalarIn, \p VecIn
1877 ///
1878 /// \p ScalarIn is the scalar accumulator input to start the sequential
1879 /// reduction operation of \p VecIn.
1881 const SrcOp &ScalarIn,
1882 const SrcOp &VecIn) {
1883 return buildInstr(TargetOpcode::G_VECREDUCE_SEQ_FADD, {Dst},
1884 {ScalarIn, {VecIn}});
1885 }
1886
1887 /// Build and insert \p Res = G_VECREDUCE_SEQ_FMUL \p ScalarIn, \p VecIn
1888 ///
1889 /// \p ScalarIn is the scalar accumulator input to start the sequential
1890 /// reduction operation of \p VecIn.
1892 const SrcOp &ScalarIn,
1893 const SrcOp &VecIn) {
1894 return buildInstr(TargetOpcode::G_VECREDUCE_SEQ_FMUL, {Dst},
1895 {ScalarIn, {VecIn}});
1896 }
1897
1898 /// Build and insert \p Res = G_VECREDUCE_FADD \p Src
1899 ///
1900 /// \p ScalarIn is the scalar accumulator input to the reduction operation of
1901 /// \p VecIn.
1903 const SrcOp &ScalarIn,
1904 const SrcOp &VecIn) {
1905 return buildInstr(TargetOpcode::G_VECREDUCE_FADD, {Dst}, {ScalarIn, VecIn});
1906 }
1907
1908 /// Build and insert \p Res = G_VECREDUCE_FMUL \p Src
1909 ///
1910 /// \p ScalarIn is the scalar accumulator input to the reduction operation of
1911 /// \p VecIn.
1913 const SrcOp &ScalarIn,
1914 const SrcOp &VecIn) {
1915 return buildInstr(TargetOpcode::G_VECREDUCE_FMUL, {Dst}, {ScalarIn, VecIn});
1916 }
1917
1918 /// Build and insert \p Res = G_VECREDUCE_FMAX \p Src
1920 return buildInstr(TargetOpcode::G_VECREDUCE_FMAX, {Dst}, {Src});
1921 }
1922
1923 /// Build and insert \p Res = G_VECREDUCE_FMIN \p Src
1925 return buildInstr(TargetOpcode::G_VECREDUCE_FMIN, {Dst}, {Src});
1926 }
1927 /// Build and insert \p Res = G_VECREDUCE_ADD \p Src
1929 return buildInstr(TargetOpcode::G_VECREDUCE_ADD, {Dst}, {Src});
1930 }
1931
1932 /// Build and insert \p Res = G_VECREDUCE_MUL \p Src
1934 return buildInstr(TargetOpcode::G_VECREDUCE_MUL, {Dst}, {Src});
1935 }
1936
1937 /// Build and insert \p Res = G_VECREDUCE_AND \p Src
1939 return buildInstr(TargetOpcode::G_VECREDUCE_AND, {Dst}, {Src});
1940 }
1941
1942 /// Build and insert \p Res = G_VECREDUCE_OR \p Src
1944 return buildInstr(TargetOpcode::G_VECREDUCE_OR, {Dst}, {Src});
1945 }
1946
1947 /// Build and insert \p Res = G_VECREDUCE_XOR \p Src
1949 return buildInstr(TargetOpcode::G_VECREDUCE_XOR, {Dst}, {Src});
1950 }
1951
1952 /// Build and insert \p Res = G_VECREDUCE_SMAX \p Src
1954 return buildInstr(TargetOpcode::G_VECREDUCE_SMAX, {Dst}, {Src});
1955 }
1956
1957 /// Build and insert \p Res = G_VECREDUCE_SMIN \p Src
1959 return buildInstr(TargetOpcode::G_VECREDUCE_SMIN, {Dst}, {Src});
1960 }
1961
1962 /// Build and insert \p Res = G_VECREDUCE_UMAX \p Src
1964 return buildInstr(TargetOpcode::G_VECREDUCE_UMAX, {Dst}, {Src});
1965 }
1966
1967 /// Build and insert \p Res = G_VECREDUCE_UMIN \p Src
1969 return buildInstr(TargetOpcode::G_VECREDUCE_UMIN, {Dst}, {Src});
1970 }
1971
1972 /// Build and insert G_MEMCPY or G_MEMMOVE
1973 MachineInstrBuilder buildMemTransferInst(unsigned Opcode, const SrcOp &DstPtr,
1974 const SrcOp &SrcPtr,
1975 const SrcOp &Size,
1976 MachineMemOperand &DstMMO,
1977 MachineMemOperand &SrcMMO) {
1978 auto MIB = buildInstr(
1979 Opcode, {}, {DstPtr, SrcPtr, Size, SrcOp(INT64_C(0) /*isTailCall*/)});
1980 MIB.addMemOperand(&DstMMO);
1981 MIB.addMemOperand(&SrcMMO);
1982 return MIB;
1983 }
1984
1985 MachineInstrBuilder buildMemCpy(const SrcOp &DstPtr, const SrcOp &SrcPtr,
1986 const SrcOp &Size, MachineMemOperand &DstMMO,
1987 MachineMemOperand &SrcMMO) {
1988 return buildMemTransferInst(TargetOpcode::G_MEMCPY, DstPtr, SrcPtr, Size,
1989 DstMMO, SrcMMO);
1990 }
1991
1992 /// Build and insert \p Dst = G_SBFX \p Src, \p LSB, \p Width.
1994 const SrcOp &LSB, const SrcOp &Width) {
1995 return buildInstr(TargetOpcode::G_SBFX, {Dst}, {Src, LSB, Width});
1996 }
1997
1998 /// Build and insert \p Dst = G_UBFX \p Src, \p LSB, \p Width.
2000 const SrcOp &LSB, const SrcOp &Width) {
2001 return buildInstr(TargetOpcode::G_UBFX, {Dst}, {Src, LSB, Width});
2002 }
2003
2004 /// Build and insert \p Dst = G_ROTR \p Src, \p Amt
2006 const SrcOp &Amt) {
2007 return buildInstr(TargetOpcode::G_ROTR, {Dst}, {Src, Amt});
2008 }
2009
2010 /// Build and insert \p Dst = G_ROTL \p Src, \p Amt
2012 const SrcOp &Amt) {
2013 return buildInstr(TargetOpcode::G_ROTL, {Dst}, {Src, Amt});
2014 }
2015
2016 /// Build and insert \p Dst = G_BITREVERSE \p Src
2018 return buildInstr(TargetOpcode::G_BITREVERSE, {Dst}, {Src});
2019 }
2020
2021 virtual MachineInstrBuilder
2022 buildInstr(unsigned Opc, ArrayRef<DstOp> DstOps, ArrayRef<SrcOp> SrcOps,
2023 std::optional<unsigned> Flags = std::nullopt);
2024};
2025
2026} // End namespace llvm.
2027#endif // LLVM_CODEGEN_GLOBALISEL_MACHINEIRBUILDER_H
unsigned const MachineRegisterInfo * MRI
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
static const Function * getParent(const Value *V)
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
uint64_t Addr
uint64_t Size
This contains common code to allow clients to notify changes to machine instr.
IRTranslator LLVM IR MI
unsigned Reg
Module.h This file contains the declarations for the Module class.
#define P(N)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Class for arbitrary precision integers.
Definition: APInt.h:75
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
The address of a basic block.
Definition: Constants.h:875
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:718
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:256
This is the shared class of boolean and integer constants.
Definition: Constants.h:78
This is an important base class in LLVM.
Definition: Constant.h:41
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:114
A debug info location.
Definition: DebugLoc.h:33
DstOp(const LLT T)
DstOp(unsigned R)
DstOp(Register R)
void addDefToMIB(MachineRegisterInfo &MRI, MachineInstrBuilder &MIB) const
LLT getLLTTy(const MachineRegisterInfo &MRI) const
DstOp(const MachineOperand &Op)
DstType getDstOpKind() const
const TargetRegisterClass * RC
const TargetRegisterClass * getRegClass() const
DstOp(const TargetRegisterClass *TRC)
Register getReg() const
The CSE Analysis object.
Definition: CSEInfo.h:69
Abstract class that contains various methods for clients to notify about changes.
virtual void createdInstr(MachineInstr &MI)=0
An instruction has been created and inserted into the function.
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:652
static constexpr LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
Metadata node.
Definition: Metadata.h:943
Function & getFunction()
Return the LLVM function that this machine code represents.
Helper class to build MachineInstr.
MachineInstrBuilder buildLoadFromOffset(const DstOp &Dst, const SrcOp &BasePtr, MachineMemOperand &BaseMMO, int64_t Offset)
Helper to create a load from a constant offset given a base address.
MachineInstrBuilder buildAtomicRMWFMin(const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_FMIN Addr, Val, MMO.
MachineInstrBuilder buildFSub(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_FSUB Op0, Op1.
MachineInstrBuilder buildFPTOSI(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_FPTOSI Src0.
MachineInstrBuilder buildFMul(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
MachineInstrBuilder buildBoolExtInReg(const DstOp &Res, const SrcOp &Op, bool IsVector, bool IsFP)
MachineInstrBuilder insertInstr(MachineInstrBuilder MIB)
Insert an existing instruction at the insertion point.
MachineInstrBuilder buildFreeze(const DstOp &Dst, const SrcOp &Src)
Build and insert Dst = G_FREEZE Src.
MachineInstrBuilder buildAtomicRMWXor(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_XOR Addr, Val, MMO.
MachineInstrBuilder buildGlobalValue(const DstOp &Res, const GlobalValue *GV)
Build and insert Res = G_GLOBAL_VALUE GV.
MachineInstrBuilder buildBr(MachineBasicBlock &Dest)
Build and insert G_BR Dest.
void setInsertPt(MachineBasicBlock &MBB, MachineBasicBlock::iterator II)
Set the insertion point before the specified position.
const MachineFunction & getMF() const
std::optional< MachineInstrBuilder > materializePtrAdd(Register &Res, Register Op0, const LLT ValueTy, uint64_t Value)
Materialize and insert Res = G_PTR_ADD Op0, (G_CONSTANT Value)
MachineInstrBuilder buildAdd(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_ADD Op0, Op1.
MachineInstrBuilder buildUndef(const DstOp &Res)
Build and insert Res = IMPLICIT_DEF.
MachineInstrBuilder buildFPExt(const DstOp &Res, const SrcOp &Op, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_FPEXT Op.
MachineInstrBuilder buildNot(const DstOp &Dst, const SrcOp &Src0)
Build and insert a bitwise not, NegOne = G_CONSTANT -1 Res = G_OR Op0, NegOne.
MachineInstrBuilder buildVecReduceSeqFAdd(const DstOp &Dst, const SrcOp &ScalarIn, const SrcOp &VecIn)
Build and insert Res = G_VECREDUCE_SEQ_FADD ScalarIn, VecIn.
MachineInstrBuilder buildRotateRight(const DstOp &Dst, const SrcOp &Src, const SrcOp &Amt)
Build and insert Dst = G_ROTR Src, Amt.
MachineInstrBuilder buildCTTZ(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_CTTZ Op0, Src0.
virtual ~MachineIRBuilder()=default
MachineInstrBuilder buildVecReduceOr(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_OR Src.
MachineInstrBuilder buildFLog2(const DstOp &Dst, const SrcOp &Src, std::optional< unsigned > Flags=std::nullopt)
Build and insert Dst = G_FLOG2 Src.
MachineInstrBuilder buildAShr(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
MachineInstrBuilder buildJumpTable(const LLT PtrTy, unsigned JTI)
Build and insert Res = G_JUMP_TABLE JTI.
MachineInstrBuilder buildBoolExt(const DstOp &Res, const SrcOp &Op, bool IsFP)
MachineInstrBuilder buildUnmerge(ArrayRef< LLT > Res, const SrcOp &Op)
Build and insert Res0, ... = G_UNMERGE_VALUES Op.
MachineInstrBuilder buildFAbs(const DstOp &Dst, const SrcOp &Src0, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_FABS Op0.
MachineInstrBuilder buildFence(unsigned Ordering, unsigned Scope)
Build and insert G_FENCE Ordering, Scope.
MachineInstrBuilder buildFMinNumIEEE(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
MachineInstrBuilder buildSelect(const DstOp &Res, const SrcOp &Tst, const SrcOp &Op0, const SrcOp &Op1, std::optional< unsigned > Flags=std::nullopt)
Build and insert a Res = G_SELECT Tst, Op0, Op1.
MachineInstrBuilder buildFMA(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, const SrcOp &Src2, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_FMA Op0, Op1, Op2.
MachineInstrBuilder buildAtomicRMWAnd(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_AND Addr, Val, MMO.
MachineInstrBuilder buildZExtInReg(const DstOp &Res, const SrcOp &Op, int64_t ImmOp)
Build and inserts Res = G_AND Op, LowBitsSet(ImmOp) Since there is no G_ZEXT_INREG like G_SEXT_INREG,...
MachineInstrBuilder buildSMulH(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
GISelCSEInfo * getCSEInfo()
MachineInstrBuilder buildAtomicRMWMin(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_MIN Addr, Val, MMO.
MachineInstrBuilder buildVecReduceFMax(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_FMAX Src.
MachineInstrBuilder buildExtract(const DstOp &Res, const SrcOp &Src, uint64_t Index)
Build and insert Res0, ... = G_EXTRACT Src, Idx0.
MachineInstrBuilder buildMul(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_MUL Op0, Op1.
MachineInstrBuilder buildAnd(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_AND Op0, Op1.
MachineInstrBuilder buildICmp(CmpInst::Predicate Pred, const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1)
Build and insert a Res = G_ICMP Pred, Op0, Op1.
MachineInstrBuilder buildCast(const DstOp &Dst, const SrcOp &Src)
Build and insert an appropriate cast between two registers of equal size.
const TargetInstrInfo & getTII()
MachineInstrBuilder buildAtomicRMWFAdd(const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_FADD Addr, Val, MMO.
MachineInstrBuilder buildSAdde(const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1, const SrcOp &CarryIn)
Build and insert Res, CarryOut = G_SADDE Op0, Op1, CarryInp.
MachineInstrBuilder buildAtomicRMWNand(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_NAND Addr, Val, MMO.
MachineInstrBuilder buildURem(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_UREM Op0, Op1.
MachineInstrBuilder buildSAddo(const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1)
Build and insert Res, CarryOut = G_SADDO Op0, Op1.
MachineInstrBuilder buildFPTOUI(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_FPTOUI Src0.
MachineInstrBuilder buildLShr(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
MachineInstrBuilder buildFPow(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
Build and insert Dst = G_FPOW Src0, Src1.
MachineInstrBuilder buildAnyExtOrTrunc(const DstOp &Res, const SrcOp &Op)
Res = COPY Op depending on the differing sizes of Res and Op.
MachineInstrBuilder buildSExt(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_SEXT Op.
MachineInstrBuilder buildIntrinsicTrunc(const DstOp &Dst, const SrcOp &Src0, std::optional< unsigned > Flags=std::nullopt)
Build and insert Dst = G_INTRINSIC_TRUNC Src0.
MachineBasicBlock::iterator getInsertPt()
Current insertion point for new instructions.
MachineInstrBuilder buildSExtOrTrunc(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_SEXT Op, Res = G_TRUNC Op, or Res = COPY Op depending on the differing sizes...
MachineInstrBuilder buildShuffleSplat(const DstOp &Res, const SrcOp &Src)
Build and insert a vector splat of a scalar Src using a G_INSERT_VECTOR_ELT and G_SHUFFLE_VECTOR idio...
MachineInstrBuilder buildAtomicCmpXchgWithSuccess(Register OldValRes, Register SuccessRes, Register Addr, Register CmpVal, Register NewVal, MachineMemOperand &MMO)
Build and insert OldValRes<def>, SuccessRes<def> = G_ATOMIC_CMPXCHG_WITH_SUCCESS Addr,...
MachineInstrBuilder buildConcatVectors(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_CONCAT_VECTORS Op0, ...
MachineInstrBuilder buildAtomicRMW(unsigned Opcode, const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_<Opcode> Addr, Val, MMO.
MachineInstrBuilder buildVecReduceSeqFMul(const DstOp &Dst, const SrcOp &ScalarIn, const SrcOp &VecIn)
Build and insert Res = G_VECREDUCE_SEQ_FMUL ScalarIn, VecIn.
MachineInstrBuilder buildSub(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_SUB Op0, Op1.
void setInstr(MachineInstr &MI)
Set the insertion point to before MI.
MDNode * getPCSections()
Get the current instruction's PC sections metadata.
MachineInstrBuilder buildBSwap(const DstOp &Dst, const SrcOp &Src0)
Build and insert Dst = G_BSWAP Src0.
MachineInstrBuilder buildVecReduceFMul(const DstOp &Dst, const SrcOp &ScalarIn, const SrcOp &VecIn)
Build and insert Res = G_VECREDUCE_FMUL Src.
MachineInstrBuilder buildCTLZ_ZERO_UNDEF(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_CTLZ_ZERO_UNDEF Op0, Src0.
MachineInstrBuilder buildAddrSpaceCast(const DstOp &Dst, const SrcOp &Src)
Build and insert Dst = G_ADDRSPACE_CAST Src.
MachineInstrBuilder buildFExp2(const DstOp &Dst, const SrcOp &Src, std::optional< unsigned > Flags=std::nullopt)
Build and insert Dst = G_FEXP2 Src.
MachineInstrBuilder buildIntToPtr(const DstOp &Dst, const SrcOp &Src)
Build and insert a G_INTTOPTR instruction.
MachineInstrBuilder buildIndirectDbgValue(Register Reg, const MDNode *Variable, const MDNode *Expr)
Build and insert a DBG_VALUE instruction expressing the fact that the associated Variable lives in me...
unsigned getBoolExtOp(bool IsVec, bool IsFP) const
MachineInstrBuilder buildUSubo(const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1)
Build and insert Res, CarryOut = G_USUBO Op0, Op1.
MachineInstrBuilder buildVecReduceFAdd(const DstOp &Dst, const SrcOp &ScalarIn, const SrcOp &VecIn)
Build and insert Res = G_VECREDUCE_FADD Src.
MachineInstrBuilder buildAtomicRMWUmax(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_UMAX Addr, Val, MMO.
MachineInstrBuilder buildBuildVector(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_BUILD_VECTOR Op0, ...
MachineIRBuilder(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsPt)
MachineInstrBuilder buildNeg(const DstOp &Dst, const SrcOp &Src0)
Build and insert integer negation Zero = G_CONSTANT 0 Res = G_SUB Zero, Op0.
MachineInstrBuilder buildVecReduceSMin(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_SMIN Src.
MachineInstrBuilder buildCTLZ(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_CTLZ Op0, Src0.
MachineInstrBuilder buildSMax(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_SMAX Op0, Op1.
MachineInstrBuilder buildConstDbgValue(const Constant &C, const MDNode *Variable, const MDNode *Expr)
Build and insert a DBG_VALUE instructions specifying that Variable is given by C (suitably modified b...
MachineInstrBuilder buildAssertZExt(const DstOp &Res, const SrcOp &Op, unsigned Size)
Build and insert Res = G_ASSERT_ZEXT Op, Size.
void recordInsertion(MachineInstr *InsertedInstr) const
MachineInstrBuilder buildUMulH(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
MachineInstrBuilder buildStrictFAdd(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_STRICT_FADD Op0, Op1.
MachineInstrBuilder buildBrCond(const SrcOp &Tst, MachineBasicBlock &Dest)
Build and insert G_BRCOND Tst, Dest.
MachineInstrBuilder buildVecReduceXor(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_XOR Src.
MachineInstrBuilder buildVecReduceFMin(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_FMIN Src.
MachineInstrBuilder buildFDiv(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_FDIV Op0, Op1.
MachineInstrBuilder buildMergeLikeInstr(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_MERGE_VALUES Op0, ... or Res = G_BUILD_VECTOR Op0, ... or Res = G_CONCAT_VEC...
const GISelCSEInfo * getCSEInfo() const
MachineInstrBuilder buildExtractVectorElement(const DstOp &Res, const SrcOp &Val, const SrcOp &Idx)
Build and insert Res = G_EXTRACT_VECTOR_ELT Val, Idx.
MachineInstrBuilder buildLoad(const DstOp &Res, const SrcOp &Addr, MachineMemOperand &MMO)
Build and insert Res = G_LOAD Addr, MMO.
MachineInstrBuilder buildZExtOrTrunc(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_ZEXT Op, Res = G_TRUNC Op, or Res = COPY Op depending on the differing sizes...
MachineInstrBuilder buildBuildVectorTrunc(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_BUILD_VECTOR_TRUNC Op0, ...
MachineBasicBlock & getMBB()
MachineIRBuilder(MachineInstr &MI)
MachineInstrBuilder buildExtractVectorElementConstant(const DstOp &Res, const SrcOp &Val, const int Idx)
Build and insert Res = G_EXTRACT_VECTOR_ELT Val, Idx.
MachineInstrBuilder buildCTTZ_ZERO_UNDEF(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_CTTZ_ZERO_UNDEF Op0, Src0.
virtual MachineInstrBuilder buildFConstant(const DstOp &Res, const ConstantFP &Val)
Build and insert Res = G_FCONSTANT Val.
MachineInstrBuilder buildBitReverse(const DstOp &Dst, const SrcOp &Src)
Build and insert Dst = G_BITREVERSE Src.
MachineInstrBuilder buildPtrAdd(const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1)
Build and insert Res = G_PTR_ADD Op0, Op1.
MachineInstrBuilder buildShl(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
MachineInstrBuilder buildUITOFP(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_UITOFP Src0.
MachineInstrBuilder buildStore(const SrcOp &Val, const SrcOp &Addr, MachineMemOperand &MMO)
Build and insert G_STORE Val, Addr, MMO.
MachineInstrBuilder buildAtomicCmpXchg(Register OldValRes, Register Addr, Register CmpVal, Register NewVal, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMIC_CMPXCHG Addr, CmpVal, NewVal, MMO.
MachineInstrBuilder buildInstr(unsigned Opcode)
Build and insert <empty> = Opcode <empty>.
MachineInstrBuilder buildSITOFP(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_SITOFP Src0.
MachineIRBuilder(MachineInstr &MI, GISelChangeObserver &Observer)
MachineInstrBuilder buildFMAD(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, const SrcOp &Src2, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_FMAD Op0, Op1, Op2.
MachineInstrBuilder buildPadVectorWithUndefElements(const DstOp &Res, const SrcOp &Op0)
Build and insert a, b, ..., x = G_UNMERGE_VALUES Op0 Res = G_BUILD_VECTOR a, b, .....
MachineInstrBuilder buildFLog(const DstOp &Dst, const SrcOp &Src, std::optional< unsigned > Flags=std::nullopt)
Build and insert Dst = G_FLOG Src.
void validateSelectOp(const LLT ResTy, const LLT TstTy, const LLT Op0Ty, const LLT Op1Ty)
MachineInstrBuilder buildFrameIndex(const DstOp &Res, int Idx)
Build and insert Res = G_FRAME_INDEX Idx.
MachineInstrBuilder buildVecReduceUMax(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_UMAX Src.
MachineInstrBuilder buildDirectDbgValue(Register Reg, const MDNode *Variable, const MDNode *Expr)
Build and insert a DBG_VALUE instruction expressing the fact that the associated Variable lives in Re...
const DebugLoc & getDL()
Getter for DebugLoc.
MachineInstrBuilder buildUbfx(const DstOp &Dst, const SrcOp &Src, const SrcOp &LSB, const SrcOp &Width)
Build and insert Dst = G_UBFX Src, LSB, Width.
const MachineRegisterInfo * getMRI() const
MachineInstrBuilder buildCTPOP(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_CTPOP Op0, Src0.
MachineInstrBuilder buildAbs(const DstOp &Dst, const SrcOp &Src)
Build and insert Dst = G_ABS Src.
MachineInstrBuilder buildBuildVectorConstant(const DstOp &Res, ArrayRef< APInt > Ops)
Build and insert Res = G_BUILD_VECTOR Op0, ... where each OpN is built with G_CONSTANT.
MachineInstrBuilder buildAtomicRMWUmin(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_UMIN Addr, Val, MMO.
void validateBinaryOp(const LLT Res, const LLT Op0, const LLT Op1)
MachineInstrBuilder buildVecReduceAnd(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_AND Src.
void validateShiftOp(const LLT Res, const LLT Op0, const LLT Op1)
MachineInstrBuilder buildZExt(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_ZEXT Op.
MachineFunction & getMF()
Getter for the function we currently build.
MachineIRBuilder(MachineFunction &MF)
MachineIRBuilder(const MachineIRBuilderState &BState)
MachineInstrBuilder buildMemCpy(const SrcOp &DstPtr, const SrcOp &SrcPtr, const SrcOp &Size, MachineMemOperand &DstMMO, MachineMemOperand &SrcMMO)
MachineInstrBuilder buildAssertAlign(const DstOp &Res, const SrcOp &Op, Align AlignVal)
Build and insert Res = G_ASSERT_ALIGN Op, AlignVal.
MachineInstrBuilder buildSbfx(const DstOp &Dst, const SrcOp &Src, const SrcOp &LSB, const SrcOp &Width)
Build and insert Dst = G_SBFX Src, LSB, Width.
MachineInstrBuilder buildFMaxNum(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
MachineInstrBuilder buildSMin(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_SMIN Op0, Op1.
MachineInstrBuilder buildFMinNum(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
MachineInstrBuilder buildDbgLabel(const MDNode *Label)
Build and insert a DBG_LABEL instructions specifying that Label is given.
MachineInstrBuilder buildBrJT(Register TablePtr, unsigned JTI, Register IndexReg)
Build and insert G_BRJT TablePtr, JTI, IndexReg.
MachineInstrBuilder buildInsert(const DstOp &Res, const SrcOp &Src, const SrcOp &Op, unsigned Index)
MachineInstrBuilder buildDynStackAlloc(const DstOp &Res, const SrcOp &Size, Align Alignment)
Build and insert Res = G_DYN_STACKALLOC Size, Align.
MachineInstrBuilder buildVecReduceUMin(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_UMIN Src.
MachineInstrBuilder buildFIDbgValue(int FI, const MDNode *Variable, const MDNode *Expr)
Build and insert a DBG_VALUE instruction expressing the fact that the associated Variable lives in th...
void setInstrAndDebugLoc(MachineInstr &MI)
Set the insertion point to before MI, and set the debug loc to MI's loc.
MachineInstrBuilder buildSSube(const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1, const SrcOp &CarryIn)
Build and insert Res, CarryOut = G_SSUBE Op0, Op1, CarryInp.
void setPCSections(MDNode *MD)
Set the PC sections metadata to MD for all the next build instructions.
MachineInstrBuilder buildExtOrTrunc(unsigned ExtOpc, const DstOp &Res, const SrcOp &Op)
Build and insert Res = ExtOpc, Res = G_TRUNC Op, or Res = COPY Op depending on the differing sizes of...
MachineInstrBuilder buildVecReduceAdd(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_ADD Src.
MachineInstrBuilder buildAtomicRMWSub(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_SUB Addr, Val, MMO.
MachineInstrBuilder buildMergeValues(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_MERGE_VALUES Op0, ...
MachineInstrBuilder buildUAdde(const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1, const SrcOp &CarryIn)
Build and insert Res, CarryOut = G_UADDE Op0, Op1, CarryIn.
MachineInstrBuilder buildAtomicRMWFMax(const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_FMAX Addr, Val, MMO.
void setDebugLoc(const DebugLoc &DL)
Set the debug location to DL for all the next build instructions.
MachineInstrBuilder buildFCopysign(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_FCOPYSIGN Op0, Op1.
MachineInstrBuilder buildSplatVector(const DstOp &Res, const SrcOp &Src)
Build and insert Res = G_BUILD_VECTOR with Src replicated to fill the number of elements.
MachineInstrBuilder buildSSubo(const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1)
Build and insert Res, CarryOut = G_SUBO Op0, Op1.
MachineInstrBuilder buildAtomicRMWOr(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_OR Addr, Val, MMO.
MachineInstrBuilder buildUSube(const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1, const SrcOp &CarryIn)
Build and insert Res, CarryOut = G_USUBE Op0, Op1, CarryInp.
const MachineBasicBlock & getMBB() const
Getter for the basic block we currently build.
MachineInstrBuilder buildFNeg(const DstOp &Dst, const SrcOp &Src0, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_FNEG Op0.
MachineInstrBuilder buildInsertVectorElement(const DstOp &Res, const SrcOp &Val, const SrcOp &Elt, const SrcOp &Idx)
Build and insert Res = G_INSERT_VECTOR_ELT Val, Elt, Idx.
MachineInstrBuilder buildAnyExt(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_ANYEXT Op0.
MachineInstrBuilder buildIntrinsic(Intrinsic::ID ID, ArrayRef< Register > Res, bool HasSideEffects)
Build and insert either a G_INTRINSIC (if HasSideEffects is false) or G_INTRINSIC_W_SIDE_EFFECTS inst...
void setMBB(MachineBasicBlock &MBB)
Set the insertion point to the end of MBB.
MachineInstrBuilder buildBitcast(const DstOp &Dst, const SrcOp &Src)
Build and insert Dst = G_BITCAST Src.
const DebugLoc & getDebugLoc()
Get the current instruction's debug location.
MachineInstrBuilder buildUAddo(const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1)
Build and insert Res, CarryOut = G_UADDO Op0, Op1.
void setCSEInfo(GISelCSEInfo *Info)
MachineInstrBuilder buildFMaxNumIEEE(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
MachineInstrBuilder buildTrunc(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_TRUNC Op.
MachineInstrBuilder buildFFloor(const DstOp &Dst, const SrcOp &Src0, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = GFFLOOR Op0, Op1.
MachineIRBuilder()=default
Some constructors for easy use.
MachineInstrBuilder buildDeleteTrailingVectorElements(const DstOp &Res, const SrcOp &Op0)
Build and insert a, b, ..., x, y, z = G_UNMERGE_VALUES Op0 Res = G_BUILD_VECTOR a,...
MachineRegisterInfo * getMRI()
Getter for MRI.
MachineInstrBuilder buildAtomicRMWAdd(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_ADD Addr, Val, MMO.
MachineInstrBuilder buildFPTrunc(const DstOp &Res, const SrcOp &Op, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_FPTRUNC Op.
MachineInstrBuilder buildOr(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_OR Op0, Op1.
MachineIRBuilderState & getState()
Getter for the State.
MachineInstrBuilder buildShuffleVector(const DstOp &Res, const SrcOp &Src1, const SrcOp &Src2, ArrayRef< int > Mask)
Build and insert Res = G_SHUFFLE_VECTOR Src1, Src2, Mask.
MachineInstrBuilder buildAssertInstr(unsigned Opc, const DstOp &Res, const SrcOp &Op, unsigned Val)
Build and insert G_ASSERT_SEXT, G_ASSERT_ZEXT, or G_ASSERT_ALIGN.
void validateTruncExt(const LLT Dst, const LLT Src, bool IsExtend)
MachineInstrBuilder buildInstrNoInsert(unsigned Opcode)
Build but don't insert <empty> = Opcode <empty>.
MachineInstrBuilder buildPtrMask(const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1)
Build and insert Res = G_PTRMASK Op0, Op1.
MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op)
Build and insert Res = COPY Op.
MachineInstrBuilder buildVecReduceSMax(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_SMAX Src.
MachineInstrBuilder buildMemTransferInst(unsigned Opcode, const SrcOp &DstPtr, const SrcOp &SrcPtr, const SrcOp &Size, MachineMemOperand &DstMMO, MachineMemOperand &SrcMMO)
Build and insert G_MEMCPY or G_MEMMOVE.
void validateUnaryOp(const LLT Res, const LLT Op0)
MachineInstrBuilder buildBlockAddress(Register Res, const BlockAddress *BA)
Build and insert Res = G_BLOCK_ADDR BA.
MachineInstrBuilder buildAtomicRMWMax(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_MAX Addr, Val, MMO.
const DataLayout & getDataLayout() const
MachineInstrBuilder buildBrIndirect(Register Tgt)
Build and insert G_BRINDIRECT Tgt.
MachineInstrBuilder buildLoadInstr(unsigned Opcode, const DstOp &Res, const SrcOp &Addr, MachineMemOperand &MMO)
Build and insert Res = <opcode> Addr, MMO.
void setMF(MachineFunction &MF)
MachineInstrBuilder buildAtomicRMWFSub(const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_FSUB Addr, Val, MMO.
MachineInstrBuilder buildAssertSExt(const DstOp &Res, const SrcOp &Op, unsigned Size)
Build and insert Res = G_ASSERT_SEXT Op, Size.
MachineInstrBuilder buildXor(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_XOR Op0, Op1.
MachineInstrBuilder buildAtomicRMWXchg(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_XCHG Addr, Val, MMO.
void setChangeObserver(GISelChangeObserver &Observer)
MachineInstrBuilder buildMaskLowPtrBits(const DstOp &Res, const SrcOp &Op0, uint32_t NumBits)
Build and insert Res = G_PTRMASK Op0, G_CONSTANT (1 << NumBits) - 1.
virtual MachineInstrBuilder buildConstant(const DstOp &Res, const ConstantInt &Val)
Build and insert Res = G_CONSTANT Val.
MachineInstrBuilder buildVecReduceMul(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_MUL Src.
MachineInstrBuilder buildUMin(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_UMIN Op0, Op1.
MachineInstrBuilder buildUMax(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_UMAX Op0, Op1.
MachineInstrBuilder buildFCmp(CmpInst::Predicate Pred, const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1, std::optional< unsigned > Flags=std::nullopt)
Build and insert a Res = G_FCMP PredOp0, Op1.
MachineInstrBuilder buildFAdd(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_FADD Op0, Op1.
MachineInstrBuilder buildPtrToInt(const DstOp &Dst, const SrcOp &Src)
Build and insert a G_PTRTOINT instruction.
MachineInstrBuilder buildFCanonicalize(const DstOp &Dst, const SrcOp &Src0, std::optional< unsigned > Flags=std::nullopt)
Build and insert Dst = G_FCANONICALIZE Src0.
MachineInstrBuilder buildSExtInReg(const DstOp &Res, const SrcOp &Op, int64_t ImmOp)
Build and insert Res = G_SEXT_INREG Op, ImmOp.
MachineInstrBuilder buildRotateLeft(const DstOp &Dst, const SrcOp &Src, const SrcOp &Amt)
Build and insert Dst = G_ROTL Src, Amt.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & addPredicate(CmpInst::Predicate Pred) const
const MachineInstrBuilder & addUse(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
Representation of each machine instruction.
Definition: MachineInstr.h:68
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:526
A description of a memory reference used in the backend.
Flags
Flags values. These may be or'd together.
MachineOperand class - Representation of each machine instruction operand.
Register getReg() const
getReg - Returns the register number.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
const DataLayout & getDataLayout() const
Get the data layout for the module's target platform.
Definition: Module.cpp:398
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
SrcOp(const MachineInstrBuilder &MIB)
SrcOp(int64_t V)
SrcOp(const CmpInst::Predicate P)
SrcOp(uint64_t V)
SrcOp(int)=delete
MachineInstrBuilder SrcMIB
CmpInst::Predicate getPredicate() const
SrcType getSrcOpKind() const
CmpInst::Predicate Pred
int64_t getImm() const
LLT getLLTTy(const MachineRegisterInfo &MRI) const
SrcOp(const MachineOperand &Op)
void addSrcToMIB(MachineInstrBuilder &MIB) const
SrcOp(unsigned)=delete
Use of registers held in unsigned integer variables (or more rarely signed integers) is no longer per...
Register getReg() const
SrcOp(Register R)
TargetInstrInfo - Interface to description of machine instruction set.
LLVM Value Representation.
Definition: Value.h:74
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
@ ConstantFP
Definition: ISDOpcodes.h:77
@ BlockAddress
Definition: ISDOpcodes.h:84
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:406
A collection of metadata nodes that might be associated with a memory access used by the alias-analys...
Definition: Metadata.h:651
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
uint64_t value() const
This is a hole in the type system and should not be abused.
Definition: Alignment.h:85
Class which stores all the state required in a MachineIRBuilder.
MachineFunction * MF
MachineFunction under construction.
DebugLoc DL
Debug location to be set to any instruction we create.
const TargetInstrInfo * TII
Information used to access the description of the opcodes.
MDNode * PCSections
PC sections metadata to be set to any instruction we create.
MachineBasicBlock::iterator II
MachineRegisterInfo * MRI
Information used to verify types are consistent and to create virtual registers.
GISelChangeObserver * Observer
This class contains a discriminated union of information about pointers in memory operands,...