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MachineIRBuilder.h
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1 //===-- llvm/CodeGen/GlobalISel/MachineIRBuilder.h - MIBuilder --*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file declares the MachineIRBuilder class.
10 /// This is a helper class to build MachineInstr.
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_CODEGEN_GLOBALISEL_MACHINEIRBUILDER_H
14 #define LLVM_CODEGEN_GLOBALISEL_MACHINEIRBUILDER_H
15 
21 #include "llvm/IR/DebugLoc.h"
22 #include "llvm/IR/Module.h"
23 
24 namespace llvm {
25 
26 // Forward declarations.
27 class APInt;
28 class BlockAddress;
29 class Constant;
30 class ConstantFP;
31 class ConstantInt;
32 class DataLayout;
33 class GISelCSEInfo;
34 class GlobalValue;
35 class TargetRegisterClass;
36 class MachineFunction;
37 class MachineInstr;
38 class TargetInstrInfo;
39 class GISelChangeObserver;
40 
41 /// Class which stores all the state required in a MachineIRBuilder.
42 /// Since MachineIRBuilders will only store state in this object, it allows
43 /// to transfer BuilderState between different kinds of MachineIRBuilders.
45  /// MachineFunction under construction.
46  MachineFunction *MF = nullptr;
47  /// Information used to access the description of the opcodes.
48  const TargetInstrInfo *TII = nullptr;
49  /// Information used to verify types are consistent and to create virtual registers.
51  /// Debug location to be set to any instruction we create.
53  /// PC sections metadata to be set to any instruction we create.
54  MDNode *PCSections = nullptr;
55 
56  /// \name Fields describing the insertion point.
57  /// @{
58  MachineBasicBlock *MBB = nullptr;
60  /// @}
61 
63 
64  GISelCSEInfo *CSEInfo = nullptr;
65 };
66 
67 class DstOp {
68  union {
72  };
73 
74 public:
75  enum class DstType { Ty_LLT, Ty_Reg, Ty_RC };
76  DstOp(unsigned R) : Reg(R), Ty(DstType::Ty_Reg) {}
77  DstOp(Register R) : Reg(R), Ty(DstType::Ty_Reg) {}
78  DstOp(const MachineOperand &Op) : Reg(Op.getReg()), Ty(DstType::Ty_Reg) {}
79  DstOp(const LLT T) : LLTTy(T), Ty(DstType::Ty_LLT) {}
80  DstOp(const TargetRegisterClass *TRC) : RC(TRC), Ty(DstType::Ty_RC) {}
81 
83  switch (Ty) {
84  case DstType::Ty_Reg:
85  MIB.addDef(Reg);
86  break;
87  case DstType::Ty_LLT:
88  MIB.addDef(MRI.createGenericVirtualRegister(LLTTy));
89  break;
90  case DstType::Ty_RC:
91  MIB.addDef(MRI.createVirtualRegister(RC));
92  break;
93  }
94  }
95 
97  switch (Ty) {
98  case DstType::Ty_RC:
99  return LLT{};
100  case DstType::Ty_LLT:
101  return LLTTy;
102  case DstType::Ty_Reg:
103  return MRI.getType(Reg);
104  }
105  llvm_unreachable("Unrecognised DstOp::DstType enum");
106  }
107 
108  Register getReg() const {
109  assert(Ty == DstType::Ty_Reg && "Not a register");
110  return Reg;
111  }
112 
114  switch (Ty) {
115  case DstType::Ty_RC:
116  return RC;
117  default:
118  llvm_unreachable("Not a RC Operand");
119  }
120  }
121 
122  DstType getDstOpKind() const { return Ty; }
123 
124 private:
125  DstType Ty;
126 };
127 
128 class SrcOp {
129  union {
133  int64_t Imm;
134  };
135 
136 public:
138  SrcOp(Register R) : Reg(R), Ty(SrcType::Ty_Reg) {}
139  SrcOp(const MachineOperand &Op) : Reg(Op.getReg()), Ty(SrcType::Ty_Reg) {}
140  SrcOp(const MachineInstrBuilder &MIB) : SrcMIB(MIB), Ty(SrcType::Ty_MIB) {}
141  SrcOp(const CmpInst::Predicate P) : Pred(P), Ty(SrcType::Ty_Predicate) {}
142  /// Use of registers held in unsigned integer variables (or more rarely signed
143  /// integers) is no longer permitted to avoid ambiguity with upcoming support
144  /// for immediates.
145  SrcOp(unsigned) = delete;
146  SrcOp(int) = delete;
147  SrcOp(uint64_t V) : Imm(V), Ty(SrcType::Ty_Imm) {}
148  SrcOp(int64_t V) : Imm(V), Ty(SrcType::Ty_Imm) {}
149 
150  void addSrcToMIB(MachineInstrBuilder &MIB) const {
151  switch (Ty) {
153  MIB.addPredicate(Pred);
154  break;
155  case SrcType::Ty_Reg:
156  MIB.addUse(Reg);
157  break;
158  case SrcType::Ty_MIB:
159  MIB.addUse(SrcMIB->getOperand(0).getReg());
160  break;
161  case SrcType::Ty_Imm:
162  MIB.addImm(Imm);
163  break;
164  }
165  }
166 
168  switch (Ty) {
170  case SrcType::Ty_Imm:
171  llvm_unreachable("Not a register operand");
172  case SrcType::Ty_Reg:
173  return MRI.getType(Reg);
174  case SrcType::Ty_MIB:
175  return MRI.getType(SrcMIB->getOperand(0).getReg());
176  }
177  llvm_unreachable("Unrecognised SrcOp::SrcType enum");
178  }
179 
180  Register getReg() const {
181  switch (Ty) {
183  case SrcType::Ty_Imm:
184  llvm_unreachable("Not a register operand");
185  case SrcType::Ty_Reg:
186  return Reg;
187  case SrcType::Ty_MIB:
188  return SrcMIB->getOperand(0).getReg();
189  }
190  llvm_unreachable("Unrecognised SrcOp::SrcType enum");
191  }
192 
194  switch (Ty) {
196  return Pred;
197  default:
198  llvm_unreachable("Not a register operand");
199  }
200  }
201 
202  int64_t getImm() const {
203  switch (Ty) {
204  case SrcType::Ty_Imm:
205  return Imm;
206  default:
207  llvm_unreachable("Not an immediate");
208  }
209  }
210 
211  SrcType getSrcOpKind() const { return Ty; }
212 
213 private:
214  SrcType Ty;
215 };
216 
217 /// Helper class to build MachineInstr.
218 /// It keeps internally the insertion point and debug location for all
219 /// the new instructions we want to create.
220 /// This information can be modify via the related setters.
222 
223  MachineIRBuilderState State;
224 
225 protected:
226  void validateTruncExt(const LLT Dst, const LLT Src, bool IsExtend);
227 
228  void validateUnaryOp(const LLT Res, const LLT Op0);
229  void validateBinaryOp(const LLT Res, const LLT Op0, const LLT Op1);
230  void validateShiftOp(const LLT Res, const LLT Op0, const LLT Op1);
231 
232  void validateSelectOp(const LLT ResTy, const LLT TstTy, const LLT Op0Ty,
233  const LLT Op1Ty);
234 
235  void recordInsertion(MachineInstr *InsertedInstr) const {
236  if (State.Observer)
237  State.Observer->createdInstr(*InsertedInstr);
238  }
239 
240 public:
241  /// Some constructors for easy use.
242  MachineIRBuilder() = default;
244 
246  setMF(*MBB.getParent());
247  setInsertPt(MBB, InsPt);
248  }
249 
251  MachineIRBuilder(*MI.getParent(), MI.getIterator()) {
252  setInstr(MI);
253  setDebugLoc(MI.getDebugLoc());
254  }
255 
258  setChangeObserver(Observer);
259  }
260 
261  virtual ~MachineIRBuilder() = default;
262 
263  MachineIRBuilder(const MachineIRBuilderState &BState) : State(BState) {}
264 
266  assert(State.TII && "TargetInstrInfo is not set");
267  return *State.TII;
268  }
269 
270  /// Getter for the function we currently build.
272  assert(State.MF && "MachineFunction is not set");
273  return *State.MF;
274  }
275 
276  const MachineFunction &getMF() const {
277  assert(State.MF && "MachineFunction is not set");
278  return *State.MF;
279  }
280 
281  const DataLayout &getDataLayout() const {
282  return getMF().getFunction().getParent()->getDataLayout();
283  }
284 
285  /// Getter for DebugLoc
286  const DebugLoc &getDL() { return State.DL; }
287 
288  /// Getter for MRI
289  MachineRegisterInfo *getMRI() { return State.MRI; }
290  const MachineRegisterInfo *getMRI() const { return State.MRI; }
291 
292  /// Getter for the State
293  MachineIRBuilderState &getState() { return State; }
294 
295  /// Getter for the basic block we currently build.
296  const MachineBasicBlock &getMBB() const {
297  assert(State.MBB && "MachineBasicBlock is not set");
298  return *State.MBB;
299  }
300 
302  return const_cast<MachineBasicBlock &>(
303  const_cast<const MachineIRBuilder *>(this)->getMBB());
304  }
305 
306  GISelCSEInfo *getCSEInfo() { return State.CSEInfo; }
307  const GISelCSEInfo *getCSEInfo() const { return State.CSEInfo; }
308 
309  /// Current insertion point for new instructions.
311 
312  /// Set the insertion point before the specified position.
313  /// \pre MBB must be in getMF().
314  /// \pre II must be a valid iterator in MBB.
316  assert(MBB.getParent() == &getMF() &&
317  "Basic block is in a different function");
318  State.MBB = &MBB;
319  State.II = II;
320  }
321 
322  /// @}
323 
325 
326  /// \name Setters for the insertion point.
327  /// @{
328  /// Set the MachineFunction where to build instructions.
329  void setMF(MachineFunction &MF);
330 
331  /// Set the insertion point to the end of \p MBB.
332  /// \pre \p MBB must be contained by getMF().
334  State.MBB = &MBB;
335  State.II = MBB.end();
336  assert(&getMF() == MBB.getParent() &&
337  "Basic block is in a different function");
338  }
339 
340  /// Set the insertion point to before MI.
341  /// \pre MI must be in getMF().
343  assert(MI.getParent() && "Instruction is not part of a basic block");
344  setMBB(*MI.getParent());
345  State.II = MI.getIterator();
346  setPCSections(MI.getPCSections());
347  }
348  /// @}
349 
350  /// Set the insertion point to before MI, and set the debug loc to MI's loc.
351  /// \pre MI must be in getMF().
353  setInstr(MI);
354  setDebugLoc(MI.getDebugLoc());
355  }
356 
358  State.Observer = &Observer;
359  }
360 
361  void stopObservingChanges() { State.Observer = nullptr; }
362  /// @}
363 
364  /// Set the debug location to \p DL for all the next build instructions.
365  void setDebugLoc(const DebugLoc &DL) { this->State.DL = DL; }
366 
367  /// Get the current instruction's debug location.
368  const DebugLoc &getDebugLoc() { return State.DL; }
369 
370  /// Set the PC sections metadata to \p MD for all the next build instructions.
371  void setPCSections(MDNode *MD) { State.PCSections = MD; }
372 
373  /// Get the current instruction's PC sections metadata.
374  MDNode *getPCSections() { return State.PCSections; }
375 
376  /// Build and insert <empty> = \p Opcode <empty>.
377  /// The insertion point is the one set by the last call of either
378  /// setBasicBlock or setMI.
379  ///
380  /// \pre setBasicBlock or setMI must have been called.
381  ///
382  /// \return a MachineInstrBuilder for the newly created instruction.
383  MachineInstrBuilder buildInstr(unsigned Opcode) {
384  return insertInstr(buildInstrNoInsert(Opcode));
385  }
386 
387  /// Build but don't insert <empty> = \p Opcode <empty>.
388  ///
389  /// \pre setMF, setBasicBlock or setMI must have been called.
390  ///
391  /// \return a MachineInstrBuilder for the newly created instruction.
392  MachineInstrBuilder buildInstrNoInsert(unsigned Opcode);
393 
394  /// Insert an existing instruction at the insertion point.
396 
397  /// Build and insert a DBG_VALUE instruction expressing the fact that the
398  /// associated \p Variable lives in \p Reg (suitably modified by \p Expr).
400  const MDNode *Expr);
401 
402  /// Build and insert a DBG_VALUE instruction expressing the fact that the
403  /// associated \p Variable lives in memory at \p Reg (suitably modified by \p
404  /// Expr).
406  const MDNode *Variable,
407  const MDNode *Expr);
408 
409  /// Build and insert a DBG_VALUE instruction expressing the fact that the
410  /// associated \p Variable lives in the stack slot specified by \p FI
411  /// (suitably modified by \p Expr).
412  MachineInstrBuilder buildFIDbgValue(int FI, const MDNode *Variable,
413  const MDNode *Expr);
414 
415  /// Build and insert a DBG_VALUE instructions specifying that \p Variable is
416  /// given by \p C (suitably modified by \p Expr).
418  const MDNode *Variable,
419  const MDNode *Expr);
420 
421  /// Build and insert a DBG_LABEL instructions specifying that \p Label is
422  /// given. Convert "llvm.dbg.label Label" to "DBG_LABEL Label".
424 
425  /// Build and insert \p Res = G_DYN_STACKALLOC \p Size, \p Align
426  ///
427  /// G_DYN_STACKALLOC does a dynamic stack allocation and writes the address of
428  /// the allocated memory into \p Res.
429  /// \pre setBasicBlock or setMI must have been called.
430  /// \pre \p Res must be a generic virtual register with pointer type.
431  ///
432  /// \return a MachineInstrBuilder for the newly created instruction.
433  MachineInstrBuilder buildDynStackAlloc(const DstOp &Res, const SrcOp &Size,
434  Align Alignment);
435 
436  /// Build and insert \p Res = G_FRAME_INDEX \p Idx
437  ///
438  /// G_FRAME_INDEX materializes the address of an alloca value or other
439  /// stack-based object.
440  ///
441  /// \pre setBasicBlock or setMI must have been called.
442  /// \pre \p Res must be a generic virtual register with pointer type.
443  ///
444  /// \return a MachineInstrBuilder for the newly created instruction.
445  MachineInstrBuilder buildFrameIndex(const DstOp &Res, int Idx);
446 
447  /// Build and insert \p Res = G_GLOBAL_VALUE \p GV
448  ///
449  /// G_GLOBAL_VALUE materializes the address of the specified global
450  /// into \p Res.
451  ///
452  /// \pre setBasicBlock or setMI must have been called.
453  /// \pre \p Res must be a generic virtual register with pointer type
454  /// in the same address space as \p GV.
455  ///
456  /// \return a MachineInstrBuilder for the newly created instruction.
457  MachineInstrBuilder buildGlobalValue(const DstOp &Res, const GlobalValue *GV);
458 
459  /// Build and insert \p Res = G_PTR_ADD \p Op0, \p Op1
460  ///
461  /// G_PTR_ADD adds \p Op1 addressible units to the pointer specified by \p Op0,
462  /// storing the resulting pointer in \p Res. Addressible units are typically
463  /// bytes but this can vary between targets.
464  ///
465  /// \pre setBasicBlock or setMI must have been called.
466  /// \pre \p Res and \p Op0 must be generic virtual registers with pointer
467  /// type.
468  /// \pre \p Op1 must be a generic virtual register with scalar type.
469  ///
470  /// \return a MachineInstrBuilder for the newly created instruction.
471  MachineInstrBuilder buildPtrAdd(const DstOp &Res, const SrcOp &Op0,
472  const SrcOp &Op1);
473 
474  /// Materialize and insert \p Res = G_PTR_ADD \p Op0, (G_CONSTANT \p Value)
475  ///
476  /// G_PTR_ADD adds \p Value bytes to the pointer specified by \p Op0,
477  /// storing the resulting pointer in \p Res. If \p Value is zero then no
478  /// G_PTR_ADD or G_CONSTANT will be created and \pre Op0 will be assigned to
479  /// \p Res.
480  ///
481  /// \pre setBasicBlock or setMI must have been called.
482  /// \pre \p Op0 must be a generic virtual register with pointer type.
483  /// \pre \p ValueTy must be a scalar type.
484  /// \pre \p Res must be 0. This is to detect confusion between
485  /// materializePtrAdd() and buildPtrAdd().
486  /// \post \p Res will either be a new generic virtual register of the same
487  /// type as \p Op0 or \p Op0 itself.
488  ///
489  /// \return a MachineInstrBuilder for the newly created instruction.
491  const LLT ValueTy,
492  uint64_t Value);
493 
494  /// Build and insert \p Res = G_PTRMASK \p Op0, \p Op1
495  MachineInstrBuilder buildPtrMask(const DstOp &Res, const SrcOp &Op0,
496  const SrcOp &Op1) {
497  return buildInstr(TargetOpcode::G_PTRMASK, {Res}, {Op0, Op1});
498  }
499 
500  /// Build and insert \p Res = G_PTRMASK \p Op0, \p G_CONSTANT (1 << NumBits) - 1
501  ///
502  /// This clears the low bits of a pointer operand without destroying its
503  /// pointer properties. This has the effect of rounding the address *down* to
504  /// a specified alignment in bits.
505  ///
506  /// \pre setBasicBlock or setMI must have been called.
507  /// \pre \p Res and \p Op0 must be generic virtual registers with pointer
508  /// type.
509  /// \pre \p NumBits must be an integer representing the number of low bits to
510  /// be cleared in \p Op0.
511  ///
512  /// \return a MachineInstrBuilder for the newly created instruction.
513  MachineInstrBuilder buildMaskLowPtrBits(const DstOp &Res, const SrcOp &Op0,
514  uint32_t NumBits);
515 
516  /// Build and insert
517  /// a, b, ..., x = G_UNMERGE_VALUES \p Op0
518  /// \p Res = G_BUILD_VECTOR a, b, ..., x, undef, ..., undef
519  ///
520  /// Pad \p Op0 with undef elements to match number of elements in \p Res.
521  ///
522  /// \pre setBasicBlock or setMI must have been called.
523  /// \pre \p Res and \p Op0 must be generic virtual registers with vector type,
524  /// same vector element type and Op0 must have fewer elements then Res.
525  ///
526  /// \return a MachineInstrBuilder for the newly created build vector instr.
528  const SrcOp &Op0);
529 
530  /// Build and insert
531  /// a, b, ..., x, y, z = G_UNMERGE_VALUES \p Op0
532  /// \p Res = G_BUILD_VECTOR a, b, ..., x
533  ///
534  /// Delete trailing elements in \p Op0 to match number of elements in \p Res.
535  ///
536  /// \pre setBasicBlock or setMI must have been called.
537  /// \pre \p Res and \p Op0 must be generic virtual registers with vector type,
538  /// same vector element type and Op0 must have more elements then Res.
539  ///
540  /// \return a MachineInstrBuilder for the newly created build vector instr.
542  const SrcOp &Op0);
543 
544  /// Build and insert \p Res, \p CarryOut = G_UADDO \p Op0, \p Op1
545  ///
546  /// G_UADDO sets \p Res to \p Op0 + \p Op1 (truncated to the bit width) and
547  /// sets \p CarryOut to 1 if the result overflowed in unsigned arithmetic.
548  ///
549  /// \pre setBasicBlock or setMI must have been called.
550  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers with the
551  /// same scalar type.
552  ////\pre \p CarryOut must be generic virtual register with scalar type
553  ///(typically s1)
554  ///
555  /// \return The newly created instruction.
556  MachineInstrBuilder buildUAddo(const DstOp &Res, const DstOp &CarryOut,
557  const SrcOp &Op0, const SrcOp &Op1) {
558  return buildInstr(TargetOpcode::G_UADDO, {Res, CarryOut}, {Op0, Op1});
559  }
560 
561  /// Build and insert \p Res, \p CarryOut = G_USUBO \p Op0, \p Op1
562  MachineInstrBuilder buildUSubo(const DstOp &Res, const DstOp &CarryOut,
563  const SrcOp &Op0, const SrcOp &Op1) {
564  return buildInstr(TargetOpcode::G_USUBO, {Res, CarryOut}, {Op0, Op1});
565  }
566 
567  /// Build and insert \p Res, \p CarryOut = G_SADDO \p Op0, \p Op1
568  MachineInstrBuilder buildSAddo(const DstOp &Res, const DstOp &CarryOut,
569  const SrcOp &Op0, const SrcOp &Op1) {
570  return buildInstr(TargetOpcode::G_SADDO, {Res, CarryOut}, {Op0, Op1});
571  }
572 
573  /// Build and insert \p Res, \p CarryOut = G_SUBO \p Op0, \p Op1
574  MachineInstrBuilder buildSSubo(const DstOp &Res, const DstOp &CarryOut,
575  const SrcOp &Op0, const SrcOp &Op1) {
576  return buildInstr(TargetOpcode::G_SSUBO, {Res, CarryOut}, {Op0, Op1});
577  }
578 
579  /// Build and insert \p Res, \p CarryOut = G_UADDE \p Op0,
580  /// \p Op1, \p CarryIn
581  ///
582  /// G_UADDE sets \p Res to \p Op0 + \p Op1 + \p CarryIn (truncated to the bit
583  /// width) and sets \p CarryOut to 1 if the result overflowed in unsigned
584  /// arithmetic.
585  ///
586  /// \pre setBasicBlock or setMI must have been called.
587  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
588  /// with the same scalar type.
589  /// \pre \p CarryOut and \p CarryIn must be generic virtual
590  /// registers with the same scalar type (typically s1)
591  ///
592  /// \return The newly created instruction.
593  MachineInstrBuilder buildUAdde(const DstOp &Res, const DstOp &CarryOut,
594  const SrcOp &Op0, const SrcOp &Op1,
595  const SrcOp &CarryIn) {
596  return buildInstr(TargetOpcode::G_UADDE, {Res, CarryOut},
597  {Op0, Op1, CarryIn});
598  }
599 
600  /// Build and insert \p Res, \p CarryOut = G_USUBE \p Op0, \p Op1, \p CarryInp
601  MachineInstrBuilder buildUSube(const DstOp &Res, const DstOp &CarryOut,
602  const SrcOp &Op0, const SrcOp &Op1,
603  const SrcOp &CarryIn) {
604  return buildInstr(TargetOpcode::G_USUBE, {Res, CarryOut},
605  {Op0, Op1, CarryIn});
606  }
607 
608  /// Build and insert \p Res, \p CarryOut = G_SADDE \p Op0, \p Op1, \p CarryInp
609  MachineInstrBuilder buildSAdde(const DstOp &Res, const DstOp &CarryOut,
610  const SrcOp &Op0, const SrcOp &Op1,
611  const SrcOp &CarryIn) {
612  return buildInstr(TargetOpcode::G_SADDE, {Res, CarryOut},
613  {Op0, Op1, CarryIn});
614  }
615 
616  /// Build and insert \p Res, \p CarryOut = G_SSUBE \p Op0, \p Op1, \p CarryInp
617  MachineInstrBuilder buildSSube(const DstOp &Res, const DstOp &CarryOut,
618  const SrcOp &Op0, const SrcOp &Op1,
619  const SrcOp &CarryIn) {
620  return buildInstr(TargetOpcode::G_SSUBE, {Res, CarryOut},
621  {Op0, Op1, CarryIn});
622  }
623 
624  /// Build and insert \p Res = G_ANYEXT \p Op0
625  ///
626  /// G_ANYEXT produces a register of the specified width, with bits 0 to
627  /// sizeof(\p Ty) * 8 set to \p Op. The remaining bits are unspecified
628  /// (i.e. this is neither zero nor sign-extension). For a vector register,
629  /// each element is extended individually.
630  ///
631  /// \pre setBasicBlock or setMI must have been called.
632  /// \pre \p Res must be a generic virtual register with scalar or vector type.
633  /// \pre \p Op must be a generic virtual register with scalar or vector type.
634  /// \pre \p Op must be smaller than \p Res
635  ///
636  /// \return The newly created instruction.
637 
638  MachineInstrBuilder buildAnyExt(const DstOp &Res, const SrcOp &Op);
639 
640  /// Build and insert \p Res = G_SEXT \p Op
641  ///
642  /// G_SEXT produces a register of the specified width, with bits 0 to
643  /// sizeof(\p Ty) * 8 set to \p Op. The remaining bits are duplicated from the
644  /// high bit of \p Op (i.e. 2s-complement sign extended).
645  ///
646  /// \pre setBasicBlock or setMI must have been called.
647  /// \pre \p Res must be a generic virtual register with scalar or vector type.
648  /// \pre \p Op must be a generic virtual register with scalar or vector type.
649  /// \pre \p Op must be smaller than \p Res
650  ///
651  /// \return The newly created instruction.
652  MachineInstrBuilder buildSExt(const DstOp &Res, const SrcOp &Op);
653 
654  /// Build and insert \p Res = G_SEXT_INREG \p Op, ImmOp
655  MachineInstrBuilder buildSExtInReg(const DstOp &Res, const SrcOp &Op, int64_t ImmOp) {
656  return buildInstr(TargetOpcode::G_SEXT_INREG, {Res}, {Op, SrcOp(ImmOp)});
657  }
658 
659  /// Build and insert \p Res = G_FPEXT \p Op
661  Optional<unsigned> Flags = None) {
662  return buildInstr(TargetOpcode::G_FPEXT, {Res}, {Op}, Flags);
663  }
664 
665 
666  /// Build and insert a G_PTRTOINT instruction.
667  MachineInstrBuilder buildPtrToInt(const DstOp &Dst, const SrcOp &Src) {
668  return buildInstr(TargetOpcode::G_PTRTOINT, {Dst}, {Src});
669  }
670 
671  /// Build and insert a G_INTTOPTR instruction.
672  MachineInstrBuilder buildIntToPtr(const DstOp &Dst, const SrcOp &Src) {
673  return buildInstr(TargetOpcode::G_INTTOPTR, {Dst}, {Src});
674  }
675 
676  /// Build and insert \p Dst = G_BITCAST \p Src
677  MachineInstrBuilder buildBitcast(const DstOp &Dst, const SrcOp &Src) {
678  return buildInstr(TargetOpcode::G_BITCAST, {Dst}, {Src});
679  }
680 
681  /// Build and insert \p Dst = G_ADDRSPACE_CAST \p Src
683  return buildInstr(TargetOpcode::G_ADDRSPACE_CAST, {Dst}, {Src});
684  }
685 
686  /// \return The opcode of the extension the target wants to use for boolean
687  /// values.
688  unsigned getBoolExtOp(bool IsVec, bool IsFP) const;
689 
690  // Build and insert \p Res = G_ANYEXT \p Op, \p Res = G_SEXT \p Op, or \p Res
691  // = G_ZEXT \p Op depending on how the target wants to extend boolean values.
692  MachineInstrBuilder buildBoolExt(const DstOp &Res, const SrcOp &Op,
693  bool IsFP);
694 
695  // Build and insert \p Res = G_SEXT_INREG \p Op, 1 or \p Res = G_AND \p Op, 1,
696  // or COPY depending on how the target wants to extend boolean values, using
697  // the original register size.
699  bool IsVector,
700  bool IsFP);
701 
702  /// Build and insert \p Res = G_ZEXT \p Op
703  ///
704  /// G_ZEXT produces a register of the specified width, with bits 0 to
705  /// sizeof(\p Ty) * 8 set to \p Op. The remaining bits are 0. For a vector
706  /// register, each element is extended individually.
707  ///
708  /// \pre setBasicBlock or setMI must have been called.
709  /// \pre \p Res must be a generic virtual register with scalar or vector type.
710  /// \pre \p Op must be a generic virtual register with scalar or vector type.
711  /// \pre \p Op must be smaller than \p Res
712  ///
713  /// \return The newly created instruction.
714  MachineInstrBuilder buildZExt(const DstOp &Res, const SrcOp &Op);
715 
716  /// Build and insert \p Res = G_SEXT \p Op, \p Res = G_TRUNC \p Op, or
717  /// \p Res = COPY \p Op depending on the differing sizes of \p Res and \p Op.
718  /// ///
719  /// \pre setBasicBlock or setMI must have been called.
720  /// \pre \p Res must be a generic virtual register with scalar or vector type.
721  /// \pre \p Op must be a generic virtual register with scalar or vector type.
722  ///
723  /// \return The newly created instruction.
724  MachineInstrBuilder buildSExtOrTrunc(const DstOp &Res, const SrcOp &Op);
725 
726  /// Build and insert \p Res = G_ZEXT \p Op, \p Res = G_TRUNC \p Op, or
727  /// \p Res = COPY \p Op depending on the differing sizes of \p Res and \p Op.
728  /// ///
729  /// \pre setBasicBlock or setMI must have been called.
730  /// \pre \p Res must be a generic virtual register with scalar or vector type.
731  /// \pre \p Op must be a generic virtual register with scalar or vector type.
732  ///
733  /// \return The newly created instruction.
734  MachineInstrBuilder buildZExtOrTrunc(const DstOp &Res, const SrcOp &Op);
735 
736  // Build and insert \p Res = G_ANYEXT \p Op, \p Res = G_TRUNC \p Op, or
737  /// \p Res = COPY \p Op depending on the differing sizes of \p Res and \p Op.
738  /// ///
739  /// \pre setBasicBlock or setMI must have been called.
740  /// \pre \p Res must be a generic virtual register with scalar or vector type.
741  /// \pre \p Op must be a generic virtual register with scalar or vector type.
742  ///
743  /// \return The newly created instruction.
745 
746  /// Build and insert \p Res = \p ExtOpc, \p Res = G_TRUNC \p
747  /// Op, or \p Res = COPY \p Op depending on the differing sizes of \p Res and
748  /// \p Op.
749  /// ///
750  /// \pre setBasicBlock or setMI must have been called.
751  /// \pre \p Res must be a generic virtual register with scalar or vector type.
752  /// \pre \p Op must be a generic virtual register with scalar or vector type.
753  ///
754  /// \return The newly created instruction.
755  MachineInstrBuilder buildExtOrTrunc(unsigned ExtOpc, const DstOp &Res,
756  const SrcOp &Op);
757 
758  /// Build and inserts \p Res = \p G_AND \p Op, \p LowBitsSet(ImmOp)
759  /// Since there is no G_ZEXT_INREG like G_SEXT_INREG, the instruction is
760  /// emulated using G_AND.
761  MachineInstrBuilder buildZExtInReg(const DstOp &Res, const SrcOp &Op,
762  int64_t ImmOp);
763 
764  /// Build and insert an appropriate cast between two registers of equal size.
765  MachineInstrBuilder buildCast(const DstOp &Dst, const SrcOp &Src);
766 
767  /// Build and insert G_BR \p Dest
768  ///
769  /// G_BR is an unconditional branch to \p Dest.
770  ///
771  /// \pre setBasicBlock or setMI must have been called.
772  ///
773  /// \return a MachineInstrBuilder for the newly created instruction.
775 
776  /// Build and insert G_BRCOND \p Tst, \p Dest
777  ///
778  /// G_BRCOND is a conditional branch to \p Dest.
779  ///
780  /// \pre setBasicBlock or setMI must have been called.
781  /// \pre \p Tst must be a generic virtual register with scalar
782  /// type. At the beginning of legalization, this will be a single
783  /// bit (s1). Targets with interesting flags registers may change
784  /// this. For a wider type, whether the branch is taken must only
785  /// depend on bit 0 (for now).
786  ///
787  /// \return The newly created instruction.
789 
790  /// Build and insert G_BRINDIRECT \p Tgt
791  ///
792  /// G_BRINDIRECT is an indirect branch to \p Tgt.
793  ///
794  /// \pre setBasicBlock or setMI must have been called.
795  /// \pre \p Tgt must be a generic virtual register with pointer type.
796  ///
797  /// \return a MachineInstrBuilder for the newly created instruction.
799 
800  /// Build and insert G_BRJT \p TablePtr, \p JTI, \p IndexReg
801  ///
802  /// G_BRJT is a jump table branch using a table base pointer \p TablePtr,
803  /// jump table index \p JTI and index \p IndexReg
804  ///
805  /// \pre setBasicBlock or setMI must have been called.
806  /// \pre \p TablePtr must be a generic virtual register with pointer type.
807  /// \pre \p JTI must be be a jump table index.
808  /// \pre \p IndexReg must be a generic virtual register with pointer type.
809  ///
810  /// \return a MachineInstrBuilder for the newly created instruction.
811  MachineInstrBuilder buildBrJT(Register TablePtr, unsigned JTI,
812  Register IndexReg);
813 
814  /// Build and insert \p Res = G_CONSTANT \p Val
815  ///
816  /// G_CONSTANT is an integer constant with the specified size and value. \p
817  /// Val will be extended or truncated to the size of \p Reg.
818  ///
819  /// \pre setBasicBlock or setMI must have been called.
820  /// \pre \p Res must be a generic virtual register with scalar or pointer
821  /// type.
822  ///
823  /// \return The newly created instruction.
824  virtual MachineInstrBuilder buildConstant(const DstOp &Res,
825  const ConstantInt &Val);
826 
827  /// Build and insert \p Res = G_CONSTANT \p Val
828  ///
829  /// G_CONSTANT is an integer constant with the specified size and value.
830  ///
831  /// \pre setBasicBlock or setMI must have been called.
832  /// \pre \p Res must be a generic virtual register with scalar type.
833  ///
834  /// \return The newly created instruction.
835  MachineInstrBuilder buildConstant(const DstOp &Res, int64_t Val);
836  MachineInstrBuilder buildConstant(const DstOp &Res, const APInt &Val);
837 
838  /// Build and insert \p Res = G_FCONSTANT \p Val
839  ///
840  /// G_FCONSTANT is a floating-point constant with the specified size and
841  /// value.
842  ///
843  /// \pre setBasicBlock or setMI must have been called.
844  /// \pre \p Res must be a generic virtual register with scalar type.
845  ///
846  /// \return The newly created instruction.
847  virtual MachineInstrBuilder buildFConstant(const DstOp &Res,
848  const ConstantFP &Val);
849 
850  MachineInstrBuilder buildFConstant(const DstOp &Res, double Val);
851  MachineInstrBuilder buildFConstant(const DstOp &Res, const APFloat &Val);
852 
853  /// Build and insert \p Res = COPY Op
854  ///
855  /// Register-to-register COPY sets \p Res to \p Op.
856  ///
857  /// \pre setBasicBlock or setMI must have been called.
858  ///
859  /// \return a MachineInstrBuilder for the newly created instruction.
860  MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op);
861 
862 
863  /// Build and insert G_ASSERT_SEXT, G_ASSERT_ZEXT, or G_ASSERT_ALIGN
864  ///
865  /// \return a MachineInstrBuilder for the newly created instruction.
866  MachineInstrBuilder buildAssertOp(unsigned Opc, const DstOp &Res, const SrcOp &Op,
867  unsigned Val) {
868  return buildInstr(Opc, Res, Op).addImm(Val);
869  }
870 
871  /// Build and insert \p Res = G_ASSERT_ZEXT Op, Size
872  ///
873  /// \return a MachineInstrBuilder for the newly created instruction.
875  unsigned Size) {
876  return buildAssertOp(TargetOpcode::G_ASSERT_ZEXT, Res, Op, Size);
877  }
878 
879  /// Build and insert \p Res = G_ASSERT_SEXT Op, Size
880  ///
881  /// \return a MachineInstrBuilder for the newly created instruction.
883  unsigned Size) {
884  return buildAssertOp(TargetOpcode::G_ASSERT_SEXT, Res, Op, Size);
885  }
886 
887  /// Build and insert \p Res = G_ASSERT_ALIGN Op, AlignVal
888  ///
889  /// \return a MachineInstrBuilder for the newly created instruction.
891  Align AlignVal) {
892  return buildAssertOp(TargetOpcode::G_ASSERT_ALIGN, Res, Op, AlignVal.value());
893  }
894 
895  /// Build and insert `Res = G_LOAD Addr, MMO`.
896  ///
897  /// Loads the value stored at \p Addr. Puts the result in \p Res.
898  ///
899  /// \pre setBasicBlock or setMI must have been called.
900  /// \pre \p Res must be a generic virtual register.
901  /// \pre \p Addr must be a generic virtual register with pointer type.
902  ///
903  /// \return a MachineInstrBuilder for the newly created instruction.
905  MachineMemOperand &MMO) {
906  return buildLoadInstr(TargetOpcode::G_LOAD, Res, Addr, MMO);
907  }
908 
909  /// Build and insert a G_LOAD instruction, while constructing the
910  /// MachineMemOperand.
912  buildLoad(const DstOp &Res, const SrcOp &Addr, MachinePointerInfo PtrInfo,
913  Align Alignment,
915  const AAMDNodes &AAInfo = AAMDNodes());
916 
917  /// Build and insert `Res = <opcode> Addr, MMO`.
918  ///
919  /// Loads the value stored at \p Addr. Puts the result in \p Res.
920  ///
921  /// \pre setBasicBlock or setMI must have been called.
922  /// \pre \p Res must be a generic virtual register.
923  /// \pre \p Addr must be a generic virtual register with pointer type.
924  ///
925  /// \return a MachineInstrBuilder for the newly created instruction.
926  MachineInstrBuilder buildLoadInstr(unsigned Opcode, const DstOp &Res,
927  const SrcOp &Addr, MachineMemOperand &MMO);
928 
929  /// Helper to create a load from a constant offset given a base address. Load
930  /// the type of \p Dst from \p Offset from the given base address and memory
931  /// operand.
933  const SrcOp &BasePtr,
934  MachineMemOperand &BaseMMO,
935  int64_t Offset);
936 
937  /// Build and insert `G_STORE Val, Addr, MMO`.
938  ///
939  /// Stores the value \p Val to \p Addr.
940  ///
941  /// \pre setBasicBlock or setMI must have been called.
942  /// \pre \p Val must be a generic virtual register.
943  /// \pre \p Addr must be a generic virtual register with pointer type.
944  ///
945  /// \return a MachineInstrBuilder for the newly created instruction.
946  MachineInstrBuilder buildStore(const SrcOp &Val, const SrcOp &Addr,
947  MachineMemOperand &MMO);
948 
949  /// Build and insert a G_STORE instruction, while constructing the
950  /// MachineMemOperand.
952  buildStore(const SrcOp &Val, const SrcOp &Addr, MachinePointerInfo PtrInfo,
953  Align Alignment,
955  const AAMDNodes &AAInfo = AAMDNodes());
956 
957  /// Build and insert `Res0, ... = G_EXTRACT Src, Idx0`.
958  ///
959  /// \pre setBasicBlock or setMI must have been called.
960  /// \pre \p Res and \p Src must be generic virtual registers.
961  ///
962  /// \return a MachineInstrBuilder for the newly created instruction.
963  MachineInstrBuilder buildExtract(const DstOp &Res, const SrcOp &Src, uint64_t Index);
964 
965  /// Build and insert \p Res = IMPLICIT_DEF.
967 
968  /// Build and insert \p Res = G_MERGE_VALUES \p Op0, ...
969  ///
970  /// G_MERGE_VALUES combines the input elements contiguously into a larger
971  /// register.
972  ///
973  /// \pre setBasicBlock or setMI must have been called.
974  /// \pre The entire register \p Res (and no more) must be covered by the input
975  /// registers.
976  /// \pre The type of all \p Ops registers must be identical.
977  ///
978  /// \return a MachineInstrBuilder for the newly created instruction.
981  std::initializer_list<SrcOp> Ops);
982 
983  /// Build and insert \p Res0, ... = G_UNMERGE_VALUES \p Op
984  ///
985  /// G_UNMERGE_VALUES splits contiguous bits of the input into multiple
986  ///
987  /// \pre setBasicBlock or setMI must have been called.
988  /// \pre The entire register \p Res (and no more) must be covered by the input
989  /// registers.
990  /// \pre The type of all \p Res registers must be identical.
991  ///
992  /// \return a MachineInstrBuilder for the newly created instruction.
995 
996  /// Build and insert an unmerge of \p Res sized pieces to cover \p Op
998 
999  /// Build and insert \p Res = G_BUILD_VECTOR \p Op0, ...
1000  ///
1001  /// G_BUILD_VECTOR creates a vector value from multiple scalar registers.
1002  /// \pre setBasicBlock or setMI must have been called.
1003  /// \pre The entire register \p Res (and no more) must be covered by the
1004  /// input scalar registers.
1005  /// \pre The type of all \p Ops registers must be identical.
1006  ///
1007  /// \return a MachineInstrBuilder for the newly created instruction.
1009  ArrayRef<Register> Ops);
1010 
1011  /// Build and insert \p Res = G_BUILD_VECTOR \p Op0, ... where each OpN is
1012  /// built with G_CONSTANT.
1014  ArrayRef<APInt> Ops);
1015 
1016  /// Build and insert \p Res = G_BUILD_VECTOR with \p Src replicated to fill
1017  /// the number of elements
1019  const SrcOp &Src);
1020 
1021  /// Build and insert \p Res = G_BUILD_VECTOR_TRUNC \p Op0, ...
1022  ///
1023  /// G_BUILD_VECTOR_TRUNC creates a vector value from multiple scalar registers
1024  /// which have types larger than the destination vector element type, and
1025  /// truncates the values to fit.
1026  ///
1027  /// If the operands given are already the same size as the vector elt type,
1028  /// then this method will instead create a G_BUILD_VECTOR instruction.
1029  ///
1030  /// \pre setBasicBlock or setMI must have been called.
1031  /// \pre The type of all \p Ops registers must be identical.
1032  ///
1033  /// \return a MachineInstrBuilder for the newly created instruction.
1035  ArrayRef<Register> Ops);
1036 
1037  /// Build and insert a vector splat of a scalar \p Src using a
1038  /// G_INSERT_VECTOR_ELT and G_SHUFFLE_VECTOR idiom.
1039  ///
1040  /// \pre setBasicBlock or setMI must have been called.
1041  /// \pre \p Src must have the same type as the element type of \p Dst
1042  ///
1043  /// \return a MachineInstrBuilder for the newly created instruction.
1044  MachineInstrBuilder buildShuffleSplat(const DstOp &Res, const SrcOp &Src);
1045 
1046  /// Build and insert \p Res = G_SHUFFLE_VECTOR \p Src1, \p Src2, \p Mask
1047  ///
1048  /// \pre setBasicBlock or setMI must have been called.
1049  ///
1050  /// \return a MachineInstrBuilder for the newly created instruction.
1051  MachineInstrBuilder buildShuffleVector(const DstOp &Res, const SrcOp &Src1,
1052  const SrcOp &Src2, ArrayRef<int> Mask);
1053 
1054  /// Build and insert \p Res = G_CONCAT_VECTORS \p Op0, ...
1055  ///
1056  /// G_CONCAT_VECTORS creates a vector from the concatenation of 2 or more
1057  /// vectors.
1058  ///
1059  /// \pre setBasicBlock or setMI must have been called.
1060  /// \pre The entire register \p Res (and no more) must be covered by the input
1061  /// registers.
1062  /// \pre The type of all source operands must be identical.
1063  ///
1064  /// \return a MachineInstrBuilder for the newly created instruction.
1066  ArrayRef<Register> Ops);
1067 
1068  MachineInstrBuilder buildInsert(const DstOp &Res, const SrcOp &Src,
1069  const SrcOp &Op, unsigned Index);
1070 
1071  /// Build and insert either a G_INTRINSIC (if \p HasSideEffects is false) or
1072  /// G_INTRINSIC_W_SIDE_EFFECTS instruction. Its first operand will be the
1073  /// result register definition unless \p Reg is NoReg (== 0). The second
1074  /// operand will be the intrinsic's ID.
1075  ///
1076  /// Callers are expected to add the required definitions and uses afterwards.
1077  ///
1078  /// \pre setBasicBlock or setMI must have been called.
1079  ///
1080  /// \return a MachineInstrBuilder for the newly created instruction.
1082  bool HasSideEffects);
1084  bool HasSideEffects);
1085 
1086  /// Build and insert \p Res = G_FPTRUNC \p Op
1087  ///
1088  /// G_FPTRUNC converts a floating-point value into one with a smaller type.
1089  ///
1090  /// \pre setBasicBlock or setMI must have been called.
1091  /// \pre \p Res must be a generic virtual register with scalar or vector type.
1092  /// \pre \p Op must be a generic virtual register with scalar or vector type.
1093  /// \pre \p Res must be smaller than \p Op
1094  ///
1095  /// \return The newly created instruction.
1096  MachineInstrBuilder buildFPTrunc(const DstOp &Res, const SrcOp &Op,
1097  Optional<unsigned> Flags = None);
1098 
1099  /// Build and insert \p Res = G_TRUNC \p Op
1100  ///
1101  /// G_TRUNC extracts the low bits of a type. For a vector type each element is
1102  /// truncated independently before being packed into the destination.
1103  ///
1104  /// \pre setBasicBlock or setMI must have been called.
1105  /// \pre \p Res must be a generic virtual register with scalar or vector type.
1106  /// \pre \p Op must be a generic virtual register with scalar or vector type.
1107  /// \pre \p Res must be smaller than \p Op
1108  ///
1109  /// \return The newly created instruction.
1110  MachineInstrBuilder buildTrunc(const DstOp &Res, const SrcOp &Op);
1111 
1112  /// Build and insert a \p Res = G_ICMP \p Pred, \p Op0, \p Op1
1113  ///
1114  /// \pre setBasicBlock or setMI must have been called.
1115 
1116  /// \pre \p Res must be a generic virtual register with scalar or
1117  /// vector type. Typically this starts as s1 or <N x s1>.
1118  /// \pre \p Op0 and Op1 must be generic virtual registers with the
1119  /// same number of elements as \p Res. If \p Res is a scalar,
1120  /// \p Op0 must be either a scalar or pointer.
1121  /// \pre \p Pred must be an integer predicate.
1122  ///
1123  /// \return a MachineInstrBuilder for the newly created instruction.
1125  const SrcOp &Op0, const SrcOp &Op1);
1126 
1127  /// Build and insert a \p Res = G_FCMP \p Pred\p Op0, \p Op1
1128  ///
1129  /// \pre setBasicBlock or setMI must have been called.
1130 
1131  /// \pre \p Res must be a generic virtual register with scalar or
1132  /// vector type. Typically this starts as s1 or <N x s1>.
1133  /// \pre \p Op0 and Op1 must be generic virtual registers with the
1134  /// same number of elements as \p Res (or scalar, if \p Res is
1135  /// scalar).
1136  /// \pre \p Pred must be a floating-point predicate.
1137  ///
1138  /// \return a MachineInstrBuilder for the newly created instruction.
1140  const SrcOp &Op0, const SrcOp &Op1,
1141  Optional<unsigned> Flags = None);
1142 
1143  /// Build and insert a \p Res = G_SELECT \p Tst, \p Op0, \p Op1
1144  ///
1145  /// \pre setBasicBlock or setMI must have been called.
1146  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1147  /// with the same type.
1148  /// \pre \p Tst must be a generic virtual register with scalar, pointer or
1149  /// vector type. If vector then it must have the same number of
1150  /// elements as the other parameters.
1151  ///
1152  /// \return a MachineInstrBuilder for the newly created instruction.
1153  MachineInstrBuilder buildSelect(const DstOp &Res, const SrcOp &Tst,
1154  const SrcOp &Op0, const SrcOp &Op1,
1155  Optional<unsigned> Flags = None);
1156 
1157  /// Build and insert \p Res = G_INSERT_VECTOR_ELT \p Val,
1158  /// \p Elt, \p Idx
1159  ///
1160  /// \pre setBasicBlock or setMI must have been called.
1161  /// \pre \p Res and \p Val must be a generic virtual register
1162  // with the same vector type.
1163  /// \pre \p Elt and \p Idx must be a generic virtual register
1164  /// with scalar type.
1165  ///
1166  /// \return The newly created instruction.
1168  const SrcOp &Val,
1169  const SrcOp &Elt,
1170  const SrcOp &Idx);
1171 
1172  /// Build and insert \p Res = G_EXTRACT_VECTOR_ELT \p Val, \p Idx
1173  ///
1174  /// \pre setBasicBlock or setMI must have been called.
1175  /// \pre \p Res must be a generic virtual register with scalar type.
1176  /// \pre \p Val must be a generic virtual register with vector type.
1177  /// \pre \p Idx must be a generic virtual register with scalar type.
1178  ///
1179  /// \return The newly created instruction.
1181  const SrcOp &Val,
1182  const SrcOp &Idx);
1183 
1184  /// Build and insert `OldValRes<def>, SuccessRes<def> =
1185  /// G_ATOMIC_CMPXCHG_WITH_SUCCESS Addr, CmpVal, NewVal, MMO`.
1186  ///
1187  /// Atomically replace the value at \p Addr with \p NewVal if it is currently
1188  /// \p CmpVal otherwise leaves it unchanged. Puts the original value from \p
1189  /// Addr in \p Res, along with an s1 indicating whether it was replaced.
1190  ///
1191  /// \pre setBasicBlock or setMI must have been called.
1192  /// \pre \p OldValRes must be a generic virtual register of scalar type.
1193  /// \pre \p SuccessRes must be a generic virtual register of scalar type. It
1194  /// will be assigned 0 on failure and 1 on success.
1195  /// \pre \p Addr must be a generic virtual register with pointer type.
1196  /// \pre \p OldValRes, \p CmpVal, and \p NewVal must be generic virtual
1197  /// registers of the same type.
1198  ///
1199  /// \return a MachineInstrBuilder for the newly created instruction.
1201  buildAtomicCmpXchgWithSuccess(Register OldValRes, Register SuccessRes,
1202  Register Addr, Register CmpVal, Register NewVal,
1203  MachineMemOperand &MMO);
1204 
1205  /// Build and insert `OldValRes<def> = G_ATOMIC_CMPXCHG Addr, CmpVal, NewVal,
1206  /// MMO`.
1207  ///
1208  /// Atomically replace the value at \p Addr with \p NewVal if it is currently
1209  /// \p CmpVal otherwise leaves it unchanged. Puts the original value from \p
1210  /// Addr in \p Res.
1211  ///
1212  /// \pre setBasicBlock or setMI must have been called.
1213  /// \pre \p OldValRes must be a generic virtual register of scalar type.
1214  /// \pre \p Addr must be a generic virtual register with pointer type.
1215  /// \pre \p OldValRes, \p CmpVal, and \p NewVal must be generic virtual
1216  /// registers of the same type.
1217  ///
1218  /// \return a MachineInstrBuilder for the newly created instruction.
1220  Register CmpVal, Register NewVal,
1221  MachineMemOperand &MMO);
1222 
1223  /// Build and insert `OldValRes<def> = G_ATOMICRMW_<Opcode> Addr, Val, MMO`.
1224  ///
1225  /// Atomically read-modify-update the value at \p Addr with \p Val. Puts the
1226  /// original value from \p Addr in \p OldValRes. The modification is
1227  /// determined by the opcode.
1228  ///
1229  /// \pre setBasicBlock or setMI must have been called.
1230  /// \pre \p OldValRes must be a generic virtual register.
1231  /// \pre \p Addr must be a generic virtual register with pointer type.
1232  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1233  /// same type.
1234  ///
1235  /// \return a MachineInstrBuilder for the newly created instruction.
1236  MachineInstrBuilder buildAtomicRMW(unsigned Opcode, const DstOp &OldValRes,
1237  const SrcOp &Addr, const SrcOp &Val,
1238  MachineMemOperand &MMO);
1239 
1240  /// Build and insert `OldValRes<def> = G_ATOMICRMW_XCHG Addr, Val, MMO`.
1241  ///
1242  /// Atomically replace the value at \p Addr with \p Val. Puts the original
1243  /// value from \p Addr in \p OldValRes.
1244  ///
1245  /// \pre setBasicBlock or setMI must have been called.
1246  /// \pre \p OldValRes must be a generic virtual register.
1247  /// \pre \p Addr must be a generic virtual register with pointer type.
1248  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1249  /// same type.
1250  ///
1251  /// \return a MachineInstrBuilder for the newly created instruction.
1253  Register Val, MachineMemOperand &MMO);
1254 
1255  /// Build and insert `OldValRes<def> = G_ATOMICRMW_ADD Addr, Val, MMO`.
1256  ///
1257  /// Atomically replace the value at \p Addr with the addition of \p Val and
1258  /// the original value. Puts the original value from \p Addr in \p OldValRes.
1259  ///
1260  /// \pre setBasicBlock or setMI must have been called.
1261  /// \pre \p OldValRes must be a generic virtual register.
1262  /// \pre \p Addr must be a generic virtual register with pointer type.
1263  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1264  /// same type.
1265  ///
1266  /// \return a MachineInstrBuilder for the newly created instruction.
1268  Register Val, MachineMemOperand &MMO);
1269 
1270  /// Build and insert `OldValRes<def> = G_ATOMICRMW_SUB Addr, Val, MMO`.
1271  ///
1272  /// Atomically replace the value at \p Addr with the subtraction of \p Val and
1273  /// the original value. Puts the original value from \p Addr in \p OldValRes.
1274  ///
1275  /// \pre setBasicBlock or setMI must have been called.
1276  /// \pre \p OldValRes must be a generic virtual register.
1277  /// \pre \p Addr must be a generic virtual register with pointer type.
1278  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1279  /// same type.
1280  ///
1281  /// \return a MachineInstrBuilder for the newly created instruction.
1283  Register Val, MachineMemOperand &MMO);
1284 
1285  /// Build and insert `OldValRes<def> = G_ATOMICRMW_AND Addr, Val, MMO`.
1286  ///
1287  /// Atomically replace the value at \p Addr with the bitwise and of \p Val and
1288  /// the original value. Puts the original value from \p Addr in \p OldValRes.
1289  ///
1290  /// \pre setBasicBlock or setMI must have been called.
1291  /// \pre \p OldValRes must be a generic virtual register.
1292  /// \pre \p Addr must be a generic virtual register with pointer type.
1293  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1294  /// same type.
1295  ///
1296  /// \return a MachineInstrBuilder for the newly created instruction.
1298  Register Val, MachineMemOperand &MMO);
1299 
1300  /// Build and insert `OldValRes<def> = G_ATOMICRMW_NAND Addr, Val, MMO`.
1301  ///
1302  /// Atomically replace the value at \p Addr with the bitwise nand of \p Val
1303  /// and the original value. Puts the original value from \p Addr in \p
1304  /// OldValRes.
1305  ///
1306  /// \pre setBasicBlock or setMI must have been called.
1307  /// \pre \p OldValRes must be a generic virtual register.
1308  /// \pre \p Addr must be a generic virtual register with pointer type.
1309  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1310  /// same type.
1311  ///
1312  /// \return a MachineInstrBuilder for the newly created instruction.
1314  Register Val, MachineMemOperand &MMO);
1315 
1316  /// Build and insert `OldValRes<def> = G_ATOMICRMW_OR Addr, Val, MMO`.
1317  ///
1318  /// Atomically replace the value at \p Addr with the bitwise or of \p Val and
1319  /// the original value. Puts the original value from \p Addr in \p OldValRes.
1320  ///
1321  /// \pre setBasicBlock or setMI must have been called.
1322  /// \pre \p OldValRes must be a generic virtual register.
1323  /// \pre \p Addr must be a generic virtual register with pointer type.
1324  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1325  /// same type.
1326  ///
1327  /// \return a MachineInstrBuilder for the newly created instruction.
1329  Register Val, MachineMemOperand &MMO);
1330 
1331  /// Build and insert `OldValRes<def> = G_ATOMICRMW_XOR Addr, Val, MMO`.
1332  ///
1333  /// Atomically replace the value at \p Addr with the bitwise xor of \p Val and
1334  /// the original value. Puts the original value from \p Addr in \p OldValRes.
1335  ///
1336  /// \pre setBasicBlock or setMI must have been called.
1337  /// \pre \p OldValRes must be a generic virtual register.
1338  /// \pre \p Addr must be a generic virtual register with pointer type.
1339  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1340  /// same type.
1341  ///
1342  /// \return a MachineInstrBuilder for the newly created instruction.
1344  Register Val, MachineMemOperand &MMO);
1345 
1346  /// Build and insert `OldValRes<def> = G_ATOMICRMW_MAX Addr, Val, MMO`.
1347  ///
1348  /// Atomically replace the value at \p Addr with the signed maximum of \p
1349  /// Val and the original value. Puts the original value from \p Addr in \p
1350  /// OldValRes.
1351  ///
1352  /// \pre setBasicBlock or setMI must have been called.
1353  /// \pre \p OldValRes must be a generic virtual register.
1354  /// \pre \p Addr must be a generic virtual register with pointer type.
1355  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1356  /// same type.
1357  ///
1358  /// \return a MachineInstrBuilder for the newly created instruction.
1360  Register Val, MachineMemOperand &MMO);
1361 
1362  /// Build and insert `OldValRes<def> = G_ATOMICRMW_MIN Addr, Val, MMO`.
1363  ///
1364  /// Atomically replace the value at \p Addr with the signed minimum of \p
1365  /// Val and the original value. Puts the original value from \p Addr in \p
1366  /// OldValRes.
1367  ///
1368  /// \pre setBasicBlock or setMI must have been called.
1369  /// \pre \p OldValRes must be a generic virtual register.
1370  /// \pre \p Addr must be a generic virtual register with pointer type.
1371  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1372  /// same type.
1373  ///
1374  /// \return a MachineInstrBuilder for the newly created instruction.
1376  Register Val, MachineMemOperand &MMO);
1377 
1378  /// Build and insert `OldValRes<def> = G_ATOMICRMW_UMAX Addr, Val, MMO`.
1379  ///
1380  /// Atomically replace the value at \p Addr with the unsigned maximum of \p
1381  /// Val and the original value. Puts the original value from \p Addr in \p
1382  /// OldValRes.
1383  ///
1384  /// \pre setBasicBlock or setMI must have been called.
1385  /// \pre \p OldValRes must be a generic virtual register.
1386  /// \pre \p Addr must be a generic virtual register with pointer type.
1387  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1388  /// same type.
1389  ///
1390  /// \return a MachineInstrBuilder for the newly created instruction.
1392  Register Val, MachineMemOperand &MMO);
1393 
1394  /// Build and insert `OldValRes<def> = G_ATOMICRMW_UMIN Addr, Val, MMO`.
1395  ///
1396  /// Atomically replace the value at \p Addr with the unsigned minimum of \p
1397  /// Val and the original value. Puts the original value from \p Addr in \p
1398  /// OldValRes.
1399  ///
1400  /// \pre setBasicBlock or setMI must have been called.
1401  /// \pre \p OldValRes must be a generic virtual register.
1402  /// \pre \p Addr must be a generic virtual register with pointer type.
1403  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1404  /// same type.
1405  ///
1406  /// \return a MachineInstrBuilder for the newly created instruction.
1408  Register Val, MachineMemOperand &MMO);
1409 
1410  /// Build and insert `OldValRes<def> = G_ATOMICRMW_FADD Addr, Val, MMO`.
1412  const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val,
1413  MachineMemOperand &MMO);
1414 
1415  /// Build and insert `OldValRes<def> = G_ATOMICRMW_FSUB Addr, Val, MMO`.
1417  const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val,
1418  MachineMemOperand &MMO);
1419 
1420  /// Build and insert `OldValRes<def> = G_ATOMICRMW_FMAX Addr, Val, MMO`.
1421  ///
1422  /// Atomically replace the value at \p Addr with the floating point maximum of
1423  /// \p Val and the original value. Puts the original value from \p Addr in \p
1424  /// OldValRes.
1425  ///
1426  /// \pre setBasicBlock or setMI must have been called.
1427  /// \pre \p OldValRes must be a generic virtual register.
1428  /// \pre \p Addr must be a generic virtual register with pointer type.
1429  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1430  /// same type.
1431  ///
1432  /// \return a MachineInstrBuilder for the newly created instruction.
1434  const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val,
1435  MachineMemOperand &MMO);
1436 
1437  /// Build and insert `OldValRes<def> = G_ATOMICRMW_FMIN Addr, Val, MMO`.
1438  ///
1439  /// Atomically replace the value at \p Addr with the floating point minimum of
1440  /// \p Val and the original value. Puts the original value from \p Addr in \p
1441  /// OldValRes.
1442  ///
1443  /// \pre setBasicBlock or setMI must have been called.
1444  /// \pre \p OldValRes must be a generic virtual register.
1445  /// \pre \p Addr must be a generic virtual register with pointer type.
1446  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1447  /// same type.
1448  ///
1449  /// \return a MachineInstrBuilder for the newly created instruction.
1451  const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val,
1452  MachineMemOperand &MMO);
1453 
1454  /// Build and insert `G_FENCE Ordering, Scope`.
1455  MachineInstrBuilder buildFence(unsigned Ordering, unsigned Scope);
1456 
1457  /// Build and insert \p Dst = G_FREEZE \p Src
1458  MachineInstrBuilder buildFreeze(const DstOp &Dst, const SrcOp &Src) {
1459  return buildInstr(TargetOpcode::G_FREEZE, {Dst}, {Src});
1460  }
1461 
1462  /// Build and insert \p Res = G_BLOCK_ADDR \p BA
1463  ///
1464  /// G_BLOCK_ADDR computes the address of a basic block.
1465  ///
1466  /// \pre setBasicBlock or setMI must have been called.
1467  /// \pre \p Res must be a generic virtual register of a pointer type.
1468  ///
1469  /// \return The newly created instruction.
1471 
1472  /// Build and insert \p Res = G_ADD \p Op0, \p Op1
1473  ///
1474  /// G_ADD sets \p Res to the sum of integer parameters \p Op0 and \p Op1,
1475  /// truncated to their width.
1476  ///
1477  /// \pre setBasicBlock or setMI must have been called.
1478  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1479  /// with the same (scalar or vector) type).
1480  ///
1481  /// \return a MachineInstrBuilder for the newly created instruction.
1482 
1483  MachineInstrBuilder buildAdd(const DstOp &Dst, const SrcOp &Src0,
1484  const SrcOp &Src1,
1485  Optional<unsigned> Flags = None) {
1486  return buildInstr(TargetOpcode::G_ADD, {Dst}, {Src0, Src1}, Flags);
1487  }
1488 
1489  /// Build and insert \p Res = G_SUB \p Op0, \p Op1
1490  ///
1491  /// G_SUB sets \p Res to the difference of integer parameters \p Op0 and
1492  /// \p Op1, truncated to their width.
1493  ///
1494  /// \pre setBasicBlock or setMI must have been called.
1495  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1496  /// with the same (scalar or vector) type).
1497  ///
1498  /// \return a MachineInstrBuilder for the newly created instruction.
1499 
1500  MachineInstrBuilder buildSub(const DstOp &Dst, const SrcOp &Src0,
1501  const SrcOp &Src1,
1502  Optional<unsigned> Flags = None) {
1503  return buildInstr(TargetOpcode::G_SUB, {Dst}, {Src0, Src1}, Flags);
1504  }
1505 
1506  /// Build and insert \p Res = G_MUL \p Op0, \p Op1
1507  ///
1508  /// G_MUL sets \p Res to the product of integer parameters \p Op0 and \p Op1,
1509  /// truncated to their width.
1510  ///
1511  /// \pre setBasicBlock or setMI must have been called.
1512  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1513  /// with the same (scalar or vector) type).
1514  ///
1515  /// \return a MachineInstrBuilder for the newly created instruction.
1516  MachineInstrBuilder buildMul(const DstOp &Dst, const SrcOp &Src0,
1517  const SrcOp &Src1,
1518  Optional<unsigned> Flags = None) {
1519  return buildInstr(TargetOpcode::G_MUL, {Dst}, {Src0, Src1}, Flags);
1520  }
1521 
1522  MachineInstrBuilder buildUMulH(const DstOp &Dst, const SrcOp &Src0,
1523  const SrcOp &Src1,
1524  Optional<unsigned> Flags = None) {
1525  return buildInstr(TargetOpcode::G_UMULH, {Dst}, {Src0, Src1}, Flags);
1526  }
1527 
1528  MachineInstrBuilder buildSMulH(const DstOp &Dst, const SrcOp &Src0,
1529  const SrcOp &Src1,
1530  Optional<unsigned> Flags = None) {
1531  return buildInstr(TargetOpcode::G_SMULH, {Dst}, {Src0, Src1}, Flags);
1532  }
1533 
1534  /// Build and insert \p Res = G_UREM \p Op0, \p Op1
1535  MachineInstrBuilder buildURem(const DstOp &Dst, const SrcOp &Src0,
1536  const SrcOp &Src1,
1537  Optional<unsigned> Flags = None) {
1538  return buildInstr(TargetOpcode::G_UREM, {Dst}, {Src0, Src1}, Flags);
1539  }
1540 
1541  MachineInstrBuilder buildFMul(const DstOp &Dst, const SrcOp &Src0,
1542  const SrcOp &Src1,
1543  Optional<unsigned> Flags = None) {
1544  return buildInstr(TargetOpcode::G_FMUL, {Dst}, {Src0, Src1}, Flags);
1545  }
1546 
1547  MachineInstrBuilder buildFMinNum(const DstOp &Dst, const SrcOp &Src0,
1548  const SrcOp &Src1,
1549  Optional<unsigned> Flags = None) {
1550  return buildInstr(TargetOpcode::G_FMINNUM, {Dst}, {Src0, Src1}, Flags);
1551  }
1552 
1553  MachineInstrBuilder buildFMaxNum(const DstOp &Dst, const SrcOp &Src0,
1554  const SrcOp &Src1,
1555  Optional<unsigned> Flags = None) {
1556  return buildInstr(TargetOpcode::G_FMAXNUM, {Dst}, {Src0, Src1}, Flags);
1557  }
1558 
1560  const SrcOp &Src1,
1561  Optional<unsigned> Flags = None) {
1562  return buildInstr(TargetOpcode::G_FMINNUM_IEEE, {Dst}, {Src0, Src1}, Flags);
1563  }
1564 
1566  const SrcOp &Src1,
1567  Optional<unsigned> Flags = None) {
1568  return buildInstr(TargetOpcode::G_FMAXNUM_IEEE, {Dst}, {Src0, Src1}, Flags);
1569  }
1570 
1571  MachineInstrBuilder buildShl(const DstOp &Dst, const SrcOp &Src0,
1572  const SrcOp &Src1,
1573  Optional<unsigned> Flags = None) {
1574  return buildInstr(TargetOpcode::G_SHL, {Dst}, {Src0, Src1}, Flags);
1575  }
1576 
1577  MachineInstrBuilder buildLShr(const DstOp &Dst, const SrcOp &Src0,
1578  const SrcOp &Src1,
1579  Optional<unsigned> Flags = None) {
1580  return buildInstr(TargetOpcode::G_LSHR, {Dst}, {Src0, Src1}, Flags);
1581  }
1582 
1583  MachineInstrBuilder buildAShr(const DstOp &Dst, const SrcOp &Src0,
1584  const SrcOp &Src1,
1585  Optional<unsigned> Flags = None) {
1586  return buildInstr(TargetOpcode::G_ASHR, {Dst}, {Src0, Src1}, Flags);
1587  }
1588 
1589  /// Build and insert \p Res = G_AND \p Op0, \p Op1
1590  ///
1591  /// G_AND sets \p Res to the bitwise and of integer parameters \p Op0 and \p
1592  /// Op1.
1593  ///
1594  /// \pre setBasicBlock or setMI must have been called.
1595  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1596  /// with the same (scalar or vector) type).
1597  ///
1598  /// \return a MachineInstrBuilder for the newly created instruction.
1599 
1600  MachineInstrBuilder buildAnd(const DstOp &Dst, const SrcOp &Src0,
1601  const SrcOp &Src1) {
1602  return buildInstr(TargetOpcode::G_AND, {Dst}, {Src0, Src1});
1603  }
1604 
1605  /// Build and insert \p Res = G_OR \p Op0, \p Op1
1606  ///
1607  /// G_OR sets \p Res to the bitwise or of integer parameters \p Op0 and \p
1608  /// Op1.
1609  ///
1610  /// \pre setBasicBlock or setMI must have been called.
1611  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1612  /// with the same (scalar or vector) type).
1613  ///
1614  /// \return a MachineInstrBuilder for the newly created instruction.
1615  MachineInstrBuilder buildOr(const DstOp &Dst, const SrcOp &Src0,
1616  const SrcOp &Src1,
1617  Optional<unsigned> Flags = None) {
1618  return buildInstr(TargetOpcode::G_OR, {Dst}, {Src0, Src1}, Flags);
1619  }
1620 
1621  /// Build and insert \p Res = G_XOR \p Op0, \p Op1
1622  MachineInstrBuilder buildXor(const DstOp &Dst, const SrcOp &Src0,
1623  const SrcOp &Src1) {
1624  return buildInstr(TargetOpcode::G_XOR, {Dst}, {Src0, Src1});
1625  }
1626 
1627  /// Build and insert a bitwise not,
1628  /// \p NegOne = G_CONSTANT -1
1629  /// \p Res = G_OR \p Op0, NegOne
1630  MachineInstrBuilder buildNot(const DstOp &Dst, const SrcOp &Src0) {
1631  auto NegOne = buildConstant(Dst.getLLTTy(*getMRI()), -1);
1632  return buildInstr(TargetOpcode::G_XOR, {Dst}, {Src0, NegOne});
1633  }
1634 
1635  /// Build and insert integer negation
1636  /// \p Zero = G_CONSTANT 0
1637  /// \p Res = G_SUB Zero, \p Op0
1638  MachineInstrBuilder buildNeg(const DstOp &Dst, const SrcOp &Src0) {
1639  auto Zero = buildConstant(Dst.getLLTTy(*getMRI()), 0);
1640  return buildInstr(TargetOpcode::G_SUB, {Dst}, {Zero, Src0});
1641  }
1642 
1643  /// Build and insert \p Res = G_CTPOP \p Op0, \p Src0
1644  MachineInstrBuilder buildCTPOP(const DstOp &Dst, const SrcOp &Src0) {
1645  return buildInstr(TargetOpcode::G_CTPOP, {Dst}, {Src0});
1646  }
1647 
1648  /// Build and insert \p Res = G_CTLZ \p Op0, \p Src0
1649  MachineInstrBuilder buildCTLZ(const DstOp &Dst, const SrcOp &Src0) {
1650  return buildInstr(TargetOpcode::G_CTLZ, {Dst}, {Src0});
1651  }
1652 
1653  /// Build and insert \p Res = G_CTLZ_ZERO_UNDEF \p Op0, \p Src0
1655  return buildInstr(TargetOpcode::G_CTLZ_ZERO_UNDEF, {Dst}, {Src0});
1656  }
1657 
1658  /// Build and insert \p Res = G_CTTZ \p Op0, \p Src0
1659  MachineInstrBuilder buildCTTZ(const DstOp &Dst, const SrcOp &Src0) {
1660  return buildInstr(TargetOpcode::G_CTTZ, {Dst}, {Src0});
1661  }
1662 
1663  /// Build and insert \p Res = G_CTTZ_ZERO_UNDEF \p Op0, \p Src0
1665  return buildInstr(TargetOpcode::G_CTTZ_ZERO_UNDEF, {Dst}, {Src0});
1666  }
1667 
1668  /// Build and insert \p Dst = G_BSWAP \p Src0
1669  MachineInstrBuilder buildBSwap(const DstOp &Dst, const SrcOp &Src0) {
1670  return buildInstr(TargetOpcode::G_BSWAP, {Dst}, {Src0});
1671  }
1672 
1673  /// Build and insert \p Res = G_FADD \p Op0, \p Op1
1674  MachineInstrBuilder buildFAdd(const DstOp &Dst, const SrcOp &Src0,
1675  const SrcOp &Src1,
1676  Optional<unsigned> Flags = None) {
1677  return buildInstr(TargetOpcode::G_FADD, {Dst}, {Src0, Src1}, Flags);
1678  }
1679 
1680  /// Build and insert \p Res = G_FSUB \p Op0, \p Op1
1681  MachineInstrBuilder buildFSub(const DstOp &Dst, const SrcOp &Src0,
1682  const SrcOp &Src1,
1683  Optional<unsigned> Flags = None) {
1684  return buildInstr(TargetOpcode::G_FSUB, {Dst}, {Src0, Src1}, Flags);
1685  }
1686 
1687  /// Build and insert \p Res = G_FDIV \p Op0, \p Op1
1688  MachineInstrBuilder buildFDiv(const DstOp &Dst, const SrcOp &Src0,
1689  const SrcOp &Src1,
1690  Optional<unsigned> Flags = None) {
1691  return buildInstr(TargetOpcode::G_FDIV, {Dst}, {Src0, Src1}, Flags);
1692  }
1693 
1694  /// Build and insert \p Res = G_FMA \p Op0, \p Op1, \p Op2
1695  MachineInstrBuilder buildFMA(const DstOp &Dst, const SrcOp &Src0,
1696  const SrcOp &Src1, const SrcOp &Src2,
1697  Optional<unsigned> Flags = None) {
1698  return buildInstr(TargetOpcode::G_FMA, {Dst}, {Src0, Src1, Src2}, Flags);
1699  }
1700 
1701  /// Build and insert \p Res = G_FMAD \p Op0, \p Op1, \p Op2
1702  MachineInstrBuilder buildFMAD(const DstOp &Dst, const SrcOp &Src0,
1703  const SrcOp &Src1, const SrcOp &Src2,
1704  Optional<unsigned> Flags = None) {
1705  return buildInstr(TargetOpcode::G_FMAD, {Dst}, {Src0, Src1, Src2}, Flags);
1706  }
1707 
1708  /// Build and insert \p Res = G_FNEG \p Op0
1709  MachineInstrBuilder buildFNeg(const DstOp &Dst, const SrcOp &Src0,
1710  Optional<unsigned> Flags = None) {
1711  return buildInstr(TargetOpcode::G_FNEG, {Dst}, {Src0}, Flags);
1712  }
1713 
1714  /// Build and insert \p Res = G_FABS \p Op0
1715  MachineInstrBuilder buildFAbs(const DstOp &Dst, const SrcOp &Src0,
1716  Optional<unsigned> Flags = None) {
1717  return buildInstr(TargetOpcode::G_FABS, {Dst}, {Src0}, Flags);
1718  }
1719 
1720  /// Build and insert \p Dst = G_FCANONICALIZE \p Src0
1722  Optional<unsigned> Flags = None) {
1723  return buildInstr(TargetOpcode::G_FCANONICALIZE, {Dst}, {Src0}, Flags);
1724  }
1725 
1726  /// Build and insert \p Dst = G_INTRINSIC_TRUNC \p Src0
1728  Optional<unsigned> Flags = None) {
1729  return buildInstr(TargetOpcode::G_INTRINSIC_TRUNC, {Dst}, {Src0}, Flags);
1730  }
1731 
1732  /// Build and insert \p Res = GFFLOOR \p Op0, \p Op1
1733  MachineInstrBuilder buildFFloor(const DstOp &Dst, const SrcOp &Src0,
1734  Optional<unsigned> Flags = None) {
1735  return buildInstr(TargetOpcode::G_FFLOOR, {Dst}, {Src0}, Flags);
1736  }
1737 
1738  /// Build and insert \p Dst = G_FLOG \p Src
1739  MachineInstrBuilder buildFLog(const DstOp &Dst, const SrcOp &Src,
1740  Optional<unsigned> Flags = None) {
1741  return buildInstr(TargetOpcode::G_FLOG, {Dst}, {Src}, Flags);
1742  }
1743 
1744  /// Build and insert \p Dst = G_FLOG2 \p Src
1745  MachineInstrBuilder buildFLog2(const DstOp &Dst, const SrcOp &Src,
1746  Optional<unsigned> Flags = None) {
1747  return buildInstr(TargetOpcode::G_FLOG2, {Dst}, {Src}, Flags);
1748  }
1749 
1750  /// Build and insert \p Dst = G_FEXP2 \p Src
1751  MachineInstrBuilder buildFExp2(const DstOp &Dst, const SrcOp &Src,
1752  Optional<unsigned> Flags = None) {
1753  return buildInstr(TargetOpcode::G_FEXP2, {Dst}, {Src}, Flags);
1754  }
1755 
1756  /// Build and insert \p Dst = G_FPOW \p Src0, \p Src1
1757  MachineInstrBuilder buildFPow(const DstOp &Dst, const SrcOp &Src0,
1758  const SrcOp &Src1,
1759  Optional<unsigned> Flags = None) {
1760  return buildInstr(TargetOpcode::G_FPOW, {Dst}, {Src0, Src1}, Flags);
1761  }
1762 
1763  /// Build and insert \p Res = G_FCOPYSIGN \p Op0, \p Op1
1765  const SrcOp &Src1) {
1766  return buildInstr(TargetOpcode::G_FCOPYSIGN, {Dst}, {Src0, Src1});
1767  }
1768 
1769  /// Build and insert \p Res = G_UITOFP \p Src0
1770  MachineInstrBuilder buildUITOFP(const DstOp &Dst, const SrcOp &Src0) {
1771  return buildInstr(TargetOpcode::G_UITOFP, {Dst}, {Src0});
1772  }
1773 
1774  /// Build and insert \p Res = G_SITOFP \p Src0
1775  MachineInstrBuilder buildSITOFP(const DstOp &Dst, const SrcOp &Src0) {
1776  return buildInstr(TargetOpcode::G_SITOFP, {Dst}, {Src0});
1777  }
1778 
1779  /// Build and insert \p Res = G_FPTOUI \p Src0
1780  MachineInstrBuilder buildFPTOUI(const DstOp &Dst, const SrcOp &Src0) {
1781  return buildInstr(TargetOpcode::G_FPTOUI, {Dst}, {Src0});
1782  }
1783 
1784  /// Build and insert \p Res = G_FPTOSI \p Src0
1785  MachineInstrBuilder buildFPTOSI(const DstOp &Dst, const SrcOp &Src0) {
1786  return buildInstr(TargetOpcode::G_FPTOSI, {Dst}, {Src0});
1787  }
1788 
1789  /// Build and insert \p Res = G_SMIN \p Op0, \p Op1
1790  MachineInstrBuilder buildSMin(const DstOp &Dst, const SrcOp &Src0,
1791  const SrcOp &Src1) {
1792  return buildInstr(TargetOpcode::G_SMIN, {Dst}, {Src0, Src1});
1793  }
1794 
1795  /// Build and insert \p Res = G_SMAX \p Op0, \p Op1
1796  MachineInstrBuilder buildSMax(const DstOp &Dst, const SrcOp &Src0,
1797  const SrcOp &Src1) {
1798  return buildInstr(TargetOpcode::G_SMAX, {Dst}, {Src0, Src1});
1799  }
1800 
1801  /// Build and insert \p Res = G_UMIN \p Op0, \p Op1
1802  MachineInstrBuilder buildUMin(const DstOp &Dst, const SrcOp &Src0,
1803  const SrcOp &Src1) {
1804  return buildInstr(TargetOpcode::G_UMIN, {Dst}, {Src0, Src1});
1805  }
1806 
1807  /// Build and insert \p Res = G_UMAX \p Op0, \p Op1
1808  MachineInstrBuilder buildUMax(const DstOp &Dst, const SrcOp &Src0,
1809  const SrcOp &Src1) {
1810  return buildInstr(TargetOpcode::G_UMAX, {Dst}, {Src0, Src1});
1811  }
1812 
1813  /// Build and insert \p Dst = G_ABS \p Src
1814  MachineInstrBuilder buildAbs(const DstOp &Dst, const SrcOp &Src) {
1815  return buildInstr(TargetOpcode::G_ABS, {Dst}, {Src});
1816  }
1817 
1818  /// Build and insert \p Res = G_JUMP_TABLE \p JTI
1819  ///
1820  /// G_JUMP_TABLE sets \p Res to the address of the jump table specified by
1821  /// the jump table index \p JTI.
1822  ///
1823  /// \return a MachineInstrBuilder for the newly created instruction.
1824  MachineInstrBuilder buildJumpTable(const LLT PtrTy, unsigned JTI);
1825 
1826  /// Build and insert \p Res = G_VECREDUCE_SEQ_FADD \p ScalarIn, \p VecIn
1827  ///
1828  /// \p ScalarIn is the scalar accumulator input to start the sequential
1829  /// reduction operation of \p VecIn.
1831  const SrcOp &ScalarIn,
1832  const SrcOp &VecIn) {
1833  return buildInstr(TargetOpcode::G_VECREDUCE_SEQ_FADD, {Dst},
1834  {ScalarIn, {VecIn}});
1835  }
1836 
1837  /// Build and insert \p Res = G_VECREDUCE_SEQ_FMUL \p ScalarIn, \p VecIn
1838  ///
1839  /// \p ScalarIn is the scalar accumulator input to start the sequential
1840  /// reduction operation of \p VecIn.
1842  const SrcOp &ScalarIn,
1843  const SrcOp &VecIn) {
1844  return buildInstr(TargetOpcode::G_VECREDUCE_SEQ_FMUL, {Dst},
1845  {ScalarIn, {VecIn}});
1846  }
1847 
1848  /// Build and insert \p Res = G_VECREDUCE_FADD \p Src
1849  ///
1850  /// \p ScalarIn is the scalar accumulator input to the reduction operation of
1851  /// \p VecIn.
1853  const SrcOp &ScalarIn,
1854  const SrcOp &VecIn) {
1855  return buildInstr(TargetOpcode::G_VECREDUCE_FADD, {Dst}, {ScalarIn, VecIn});
1856  }
1857 
1858  /// Build and insert \p Res = G_VECREDUCE_FMUL \p Src
1859  ///
1860  /// \p ScalarIn is the scalar accumulator input to the reduction operation of
1861  /// \p VecIn.
1863  const SrcOp &ScalarIn,
1864  const SrcOp &VecIn) {
1865  return buildInstr(TargetOpcode::G_VECREDUCE_FMUL, {Dst}, {ScalarIn, VecIn});
1866  }
1867 
1868  /// Build and insert \p Res = G_VECREDUCE_FMAX \p Src
1870  return buildInstr(TargetOpcode::G_VECREDUCE_FMAX, {Dst}, {Src});
1871  }
1872 
1873  /// Build and insert \p Res = G_VECREDUCE_FMIN \p Src
1875  return buildInstr(TargetOpcode::G_VECREDUCE_FMIN, {Dst}, {Src});
1876  }
1877  /// Build and insert \p Res = G_VECREDUCE_ADD \p Src
1879  return buildInstr(TargetOpcode::G_VECREDUCE_ADD, {Dst}, {Src});
1880  }
1881 
1882  /// Build and insert \p Res = G_VECREDUCE_MUL \p Src
1884  return buildInstr(TargetOpcode::G_VECREDUCE_MUL, {Dst}, {Src});
1885  }
1886 
1887  /// Build and insert \p Res = G_VECREDUCE_AND \p Src
1889  return buildInstr(TargetOpcode::G_VECREDUCE_AND, {Dst}, {Src});
1890  }
1891 
1892  /// Build and insert \p Res = G_VECREDUCE_OR \p Src
1894  return buildInstr(TargetOpcode::G_VECREDUCE_OR, {Dst}, {Src});
1895  }
1896 
1897  /// Build and insert \p Res = G_VECREDUCE_XOR \p Src
1899  return buildInstr(TargetOpcode::G_VECREDUCE_XOR, {Dst}, {Src});
1900  }
1901 
1902  /// Build and insert \p Res = G_VECREDUCE_SMAX \p Src
1904  return buildInstr(TargetOpcode::G_VECREDUCE_SMAX, {Dst}, {Src});
1905  }
1906 
1907  /// Build and insert \p Res = G_VECREDUCE_SMIN \p Src
1909  return buildInstr(TargetOpcode::G_VECREDUCE_SMIN, {Dst}, {Src});
1910  }
1911 
1912  /// Build and insert \p Res = G_VECREDUCE_UMAX \p Src
1914  return buildInstr(TargetOpcode::G_VECREDUCE_UMAX, {Dst}, {Src});
1915  }
1916 
1917  /// Build and insert \p Res = G_VECREDUCE_UMIN \p Src
1919  return buildInstr(TargetOpcode::G_VECREDUCE_UMIN, {Dst}, {Src});
1920  }
1921 
1922  /// Build and insert G_MEMCPY or G_MEMMOVE
1923  MachineInstrBuilder buildMemTransferInst(unsigned Opcode, const SrcOp &DstPtr,
1924  const SrcOp &SrcPtr,
1925  const SrcOp &Size,
1926  MachineMemOperand &DstMMO,
1927  MachineMemOperand &SrcMMO) {
1928  auto MIB = buildInstr(
1929  Opcode, {}, {DstPtr, SrcPtr, Size, SrcOp(INT64_C(0) /*isTailCall*/)});
1930  MIB.addMemOperand(&DstMMO);
1931  MIB.addMemOperand(&SrcMMO);
1932  return MIB;
1933  }
1934 
1935  MachineInstrBuilder buildMemCpy(const SrcOp &DstPtr, const SrcOp &SrcPtr,
1936  const SrcOp &Size, MachineMemOperand &DstMMO,
1937  MachineMemOperand &SrcMMO) {
1938  return buildMemTransferInst(TargetOpcode::G_MEMCPY, DstPtr, SrcPtr, Size,
1939  DstMMO, SrcMMO);
1940  }
1941 
1942  /// Build and insert \p Dst = G_SBFX \p Src, \p LSB, \p Width.
1943  MachineInstrBuilder buildSbfx(const DstOp &Dst, const SrcOp &Src,
1944  const SrcOp &LSB, const SrcOp &Width) {
1945  return buildInstr(TargetOpcode::G_SBFX, {Dst}, {Src, LSB, Width});
1946  }
1947 
1948  /// Build and insert \p Dst = G_UBFX \p Src, \p LSB, \p Width.
1949  MachineInstrBuilder buildUbfx(const DstOp &Dst, const SrcOp &Src,
1950  const SrcOp &LSB, const SrcOp &Width) {
1951  return buildInstr(TargetOpcode::G_UBFX, {Dst}, {Src, LSB, Width});
1952  }
1953 
1954  /// Build and insert \p Dst = G_ROTR \p Src, \p Amt
1956  const SrcOp &Amt) {
1957  return buildInstr(TargetOpcode::G_ROTR, {Dst}, {Src, Amt});
1958  }
1959 
1960  /// Build and insert \p Dst = G_ROTL \p Src, \p Amt
1962  const SrcOp &Amt) {
1963  return buildInstr(TargetOpcode::G_ROTL, {Dst}, {Src, Amt});
1964  }
1965 
1966  /// Build and insert \p Dst = G_BITREVERSE \p Src
1968  return buildInstr(TargetOpcode::G_BITREVERSE, {Dst}, {Src});
1969  }
1970 
1971  virtual MachineInstrBuilder buildInstr(unsigned Opc, ArrayRef<DstOp> DstOps,
1972  ArrayRef<SrcOp> SrcOps,
1973  Optional<unsigned> Flags = None);
1974 };
1975 
1976 } // End namespace llvm.
1977 #endif // LLVM_CODEGEN_GLOBALISEL_MACHINEIRBUILDER_H
llvm::MachineIRBuilder::buildUSubo
MachineInstrBuilder buildUSubo(const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1)
Build and insert Res, CarryOut = G_USUBO Op0, Op1.
Definition: MachineIRBuilder.h:562
llvm::MachineIRBuilder::buildAtomicRMWFMin
MachineInstrBuilder buildAtomicRMWFMin(const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_FMIN Addr, Val, MMO.
Definition: MachineIRBuilder.cpp:975
llvm::MachineIRBuilder::setMF
void setMF(MachineFunction &MF)
Definition: MachineIRBuilder.cpp:24
llvm::MachineIRBuilder::buildInsertVectorElement
MachineInstrBuilder buildInsertVectorElement(const DstOp &Res, const SrcOp &Val, const SrcOp &Elt, const SrcOp &Idx)
Build and insert Res = G_INSERT_VECTOR_ELT Val, Elt, Idx.
Definition: MachineIRBuilder.cpp:797
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:108
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:131
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::MachineIRBuilder::buildGlobalValue
MachineInstrBuilder buildGlobalValue(const DstOp &Res, const GlobalValue *GV)
Build and insert Res = G_GLOBAL_VALUE GV.
Definition: MachineIRBuilder.cpp:154
llvm::MachineIRBuilder::setPCSections
void setPCSections(MDNode *MD)
Set the PC sections metadata to MD for all the next build instructions.
Definition: MachineIRBuilder.h:371
llvm::DstOp::DstType::Ty_LLT
@ Ty_LLT
llvm::MachineIRBuilder::buildOr
MachineInstrBuilder buildOr(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Build and insert Res = G_OR Op0, Op1.
Definition: MachineIRBuilder.h:1615
llvm::MachineIRBuilder::buildFMul
MachineInstrBuilder buildFMul(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Definition: MachineIRBuilder.h:1541
llvm::MachineIRBuilder::buildAtomicRMW
MachineInstrBuilder buildAtomicRMW(unsigned Opcode, const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_<Opcode> Addr, Val, MMO.
Definition: MachineIRBuilder.cpp:860
llvm::MachineIRBuilder::setDebugLoc
void setDebugLoc(const DebugLoc &DL)
Set the debug location to DL for all the next build instructions.
Definition: MachineIRBuilder.h:365
llvm::MachineIRBuilder::buildIntToPtr
MachineInstrBuilder buildIntToPtr(const DstOp &Dst, const SrcOp &Src)
Build and insert a G_INTTOPTR instruction.
Definition: MachineIRBuilder.h:672
llvm::MachineIRBuilder::buildICmp
MachineInstrBuilder buildICmp(CmpInst::Predicate Pred, const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1)
Build and insert a Res = G_ICMP Pred, Op0, Op1.
Definition: MachineIRBuilder.cpp:771
llvm::MachineIRBuilder::buildSMax
MachineInstrBuilder buildSMax(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_SMAX Op0, Op1.
Definition: MachineIRBuilder.h:1796
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:113
llvm::CmpInst::Predicate
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:719
llvm::MachineIRBuilderState::II
MachineBasicBlock::iterator II
Definition: MachineIRBuilder.h:59
llvm::MachineIRBuilder::buildAShr
MachineInstrBuilder buildAShr(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Definition: MachineIRBuilder.h:1583
llvm::MachineIRBuilder::buildFSub
MachineInstrBuilder buildFSub(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Build and insert Res = G_FSUB Op0, Op1.
Definition: MachineIRBuilder.h:1681
llvm::MachineIRBuilder::buildUSube
MachineInstrBuilder buildUSube(const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1, const SrcOp &CarryIn)
Build and insert Res, CarryOut = G_USUBE Op0, Op1, CarryInp.
Definition: MachineIRBuilder.h:601
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
llvm::MachineIRBuilder::buildSMulH
MachineInstrBuilder buildSMulH(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Definition: MachineIRBuilder.h:1528
llvm::ISD::ConstantFP
@ ConstantFP
Definition: ISDOpcodes.h:77
P
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
Definition: README-SSE.txt:411
llvm::MachineIRBuilder::buildSbfx
MachineInstrBuilder buildSbfx(const DstOp &Dst, const SrcOp &Src, const SrcOp &LSB, const SrcOp &Width)
Build and insert Dst = G_SBFX Src, LSB, Width.
Definition: MachineIRBuilder.h:1943
llvm::MachineIRBuilder::getCSEInfo
GISelCSEInfo * getCSEInfo()
Definition: MachineIRBuilder.h:306
llvm::MachineIRBuilder::buildUMulH
MachineInstrBuilder buildUMulH(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Definition: MachineIRBuilder.h:1522
llvm::MachineIRBuilder::buildBSwap
MachineInstrBuilder buildBSwap(const DstOp &Dst, const SrcOp &Src0)
Build and insert Dst = G_BSWAP Src0.
Definition: MachineIRBuilder.h:1669
llvm::MachineIRBuilder::buildSplatVector
MachineInstrBuilder buildSplatVector(const DstOp &Res, const SrcOp &Src)
Build and insert Res = G_BUILD_VECTOR with Src replicated to fill the number of elements.
Definition: MachineIRBuilder.cpp:664
llvm::MachineIRBuilder::getMRI
MachineRegisterInfo * getMRI()
Getter for MRI.
Definition: MachineIRBuilder.h:289
llvm::MachineIRBuilder::buildZExtInReg
MachineInstrBuilder buildZExtInReg(const DstOp &Res, const SrcOp &Op, int64_t ImmOp)
Build and inserts Res = G_AND Op, LowBitsSet(ImmOp) Since there is no G_ZEXT_INREG like G_SEXT_INREG,...
Definition: MachineIRBuilder.cpp:542
llvm::DstOp::RC
const TargetRegisterClass * RC
Definition: MachineIRBuilder.h:71
llvm::MachineIRBuilder::buildAtomicRMWOr
MachineInstrBuilder buildAtomicRMWOr(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_OR Addr, Val, MMO.
Definition: MachineIRBuilder.cpp:914
llvm::MachineIRBuilder::buildFCanonicalize
MachineInstrBuilder buildFCanonicalize(const DstOp &Dst, const SrcOp &Src0, Optional< unsigned > Flags=None)
Build and insert Dst = G_FCANONICALIZE Src0.
Definition: MachineIRBuilder.h:1721
llvm::GISelCSEInfo
The CSE Analysis object.
Definition: CSEInfo.h:69
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::MachineIRBuilder::buildNeg
MachineInstrBuilder buildNeg(const DstOp &Dst, const SrcOp &Src0)
Build and insert integer negation Zero = G_CONSTANT 0 Res = G_SUB Zero, Op0.
Definition: MachineIRBuilder.h:1638
llvm::MachineIRBuilder::buildFAbs
MachineInstrBuilder buildFAbs(const DstOp &Dst, const SrcOp &Src0, Optional< unsigned > Flags=None)
Build and insert Res = G_FABS Op0.
Definition: MachineIRBuilder.h:1715
llvm::MachineIRBuilder::MachineIRBuilder
MachineIRBuilder(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsPt)
Definition: MachineIRBuilder.h:245
llvm::MachineIRBuilder::buildZExtOrTrunc
MachineInstrBuilder buildZExtOrTrunc(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_ZEXT Op, Res = G_TRUNC Op, or Res = COPY Op depending on the differing sizes...
Definition: MachineIRBuilder.cpp:532
MachineBasicBlock.h
llvm::MachineIRBuilder::buildUMin
MachineInstrBuilder buildUMin(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_UMIN Op0, Op1.
Definition: MachineIRBuilder.h:1802
llvm::AAMDNodes
A collection of metadata nodes that might be associated with a memory access used by the alias-analys...
Definition: Metadata.h:652
llvm::MachineIRBuilder::buildAtomicRMWAdd
MachineInstrBuilder buildAtomicRMWAdd(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_ADD Addr, Val, MMO.
Definition: MachineIRBuilder.cpp:891
llvm::MachineIRBuilder::buildAtomicCmpXchg
MachineInstrBuilder buildAtomicCmpXchg(Register OldValRes, Register Addr, Register CmpVal, Register NewVal, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMIC_CMPXCHG Addr, CmpVal, NewVal, MMO.
Definition: MachineIRBuilder.cpp:836
llvm::MachineIRBuilder::buildDbgLabel
MachineInstrBuilder buildDbgLabel(const MDNode *Label)
Build and insert a DBG_LABEL instructions specifying that Label is given.
Definition: MachineIRBuilder.cpp:125
Module.h
llvm::MachineIRBuilder::buildFMAD
MachineInstrBuilder buildFMAD(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, const SrcOp &Src2, Optional< unsigned > Flags=None)
Build and insert Res = G_FMAD Op0, Op1, Op2.
Definition: MachineIRBuilder.h:1702
llvm::SrcOp::Reg
Register Reg
Definition: MachineIRBuilder.h:131
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition: MachineMemOperand.h:127
llvm::MachineIRBuilder::MachineIRBuilder
MachineIRBuilder()=default
Some constructors for easy use.
llvm::MachineIRBuilder::getDL
const DebugLoc & getDL()
Getter for DebugLoc.
Definition: MachineIRBuilder.h:286
llvm::MachineIRBuilder::buildFPTrunc
MachineInstrBuilder buildFPTrunc(const DstOp &Res, const SrcOp &Op, Optional< unsigned > Flags=None)
Build and insert Res = G_FPTRUNC Op.
Definition: MachineIRBuilder.cpp:765
llvm::MachineIRBuilder::buildVecReduceAdd
MachineInstrBuilder buildVecReduceAdd(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_ADD Src.
Definition: MachineIRBuilder.h:1878
llvm::SrcOp::Imm
int64_t Imm
Definition: MachineIRBuilder.h:133
llvm::MachineIRBuilder::buildCTTZ
MachineInstrBuilder buildCTTZ(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_CTTZ Op0, Src0.
Definition: MachineIRBuilder.h:1659
llvm::Optional
Definition: APInt.h:33
T
#define T
Definition: Mips16ISelLowering.cpp:341
llvm::MachineIRBuilder::buildBuildVector
MachineInstrBuilder buildBuildVector(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_BUILD_VECTOR Op0, ...
Definition: MachineIRBuilder.cpp:644
llvm::MachineIRBuilder::getMF
const MachineFunction & getMF() const
Definition: MachineIRBuilder.h:276
llvm::MachineIRBuilder::buildInstrNoInsert
MachineInstrBuilder buildInstrNoInsert(unsigned Opcode)
Build but don't insert <empty> = Opcode <empty>.
Definition: MachineIRBuilder.cpp:39
llvm::MachineIRBuilder::setInstr
void setInstr(MachineInstr &MI)
Set the insertion point to before MI.
Definition: MachineIRBuilder.h:342
llvm::DstOp::DstOp
DstOp(const TargetRegisterClass *TRC)
Definition: MachineIRBuilder.h:80
llvm::MachineIRBuilder::buildExtOrTrunc
MachineInstrBuilder buildExtOrTrunc(unsigned ExtOpc, const DstOp &Res, const SrcOp &Op)
Build and insert Res = ExtOpc, Res = G_TRUNC Op, or Res = COPY Op depending on the differing sizes of...
Definition: MachineIRBuilder.cpp:503
llvm::MachineIRBuilderState::MBB
MachineBasicBlock * MBB
Definition: MachineIRBuilder.h:58
llvm::MachineIRBuilder::buildVecReduceFMin
MachineInstrBuilder buildVecReduceFMin(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_FMIN Src.
Definition: MachineIRBuilder.h:1874
llvm::MachineIRBuilder::buildPtrMask
MachineInstrBuilder buildPtrMask(const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1)
Build and insert Res = G_PTRMASK Op0, Op1.
Definition: MachineIRBuilder.h:495
llvm::MachineIRBuilder::buildXor
MachineInstrBuilder buildXor(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_XOR Op0, Op1.
Definition: MachineIRBuilder.h:1622
llvm::MachineIRBuilder::buildAtomicRMWFSub
MachineInstrBuilder buildAtomicRMWFSub(const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_FSUB Addr, Val, MMO.
Definition: MachineIRBuilder.cpp:961
llvm::MachineIRBuilder::buildFence
MachineInstrBuilder buildFence(unsigned Ordering, unsigned Scope)
Build and insert G_FENCE Ordering, Scope.
Definition: MachineIRBuilder.cpp:982
llvm::MachineIRBuilder::buildFCopysign
MachineInstrBuilder buildFCopysign(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_FCOPYSIGN Op0, Op1.
Definition: MachineIRBuilder.h:1764
llvm::SrcOp::SrcType::Ty_Predicate
@ Ty_Predicate
llvm::MachineIRBuilder::buildDynStackAlloc
MachineInstrBuilder buildDynStackAlloc(const DstOp &Res, const SrcOp &Size, Align Alignment)
Build and insert Res = G_DYN_STACKALLOC Size, Align.
Definition: MachineIRBuilder.cpp:134
llvm::MachineIRBuilder::getDebugLoc
const DebugLoc & getDebugLoc()
Get the current instruction's debug location.
Definition: MachineIRBuilder.h:368
llvm::MachineIRBuilder::getCSEInfo
const GISelCSEInfo * getCSEInfo() const
Definition: MachineIRBuilder.h:307
llvm::MachineIRBuilder::validateSelectOp
void validateSelectOp(const LLT ResTy, const LLT TstTy, const LLT Op0Ty, const LLT Op1Ty)
Definition: MachineIRBuilder.cpp:1016
llvm::MachineIRBuilderState
Class which stores all the state required in a MachineIRBuilder.
Definition: MachineIRBuilder.h:44
llvm::MachineIRBuilder::buildConstant
virtual MachineInstrBuilder buildConstant(const DstOp &Res, const ConstantInt &Val)
Build and insert Res = G_CONSTANT Val.
Definition: MachineIRBuilder.cpp:293
llvm::MachineIRBuilder::buildURem
MachineInstrBuilder buildURem(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Build and insert Res = G_UREM Op0, Op1.
Definition: MachineIRBuilder.h:1535
llvm::MachineIRBuilder::validateBinaryOp
void validateBinaryOp(const LLT Res, const LLT Op0, const LLT Op1)
Definition: MachineIRBuilder.cpp:178
MachineRegisterInfo.h
llvm::MachineIRBuilder::buildCTLZ_ZERO_UNDEF
MachineInstrBuilder buildCTLZ_ZERO_UNDEF(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_CTLZ_ZERO_UNDEF Op0, Src0.
Definition: MachineIRBuilder.h:1654
llvm::DstOp::getRegClass
const TargetRegisterClass * getRegClass() const
Definition: MachineIRBuilder.h:113
llvm::DstOp::DstOp
DstOp(const LLT T)
Definition: MachineIRBuilder.h:79
llvm::MachineIRBuilder::buildBitReverse
MachineInstrBuilder buildBitReverse(const DstOp &Dst, const SrcOp &Src)
Build and insert Dst = G_BITREVERSE Src.
Definition: MachineIRBuilder.h:1967
llvm::BitmaskEnumDetail::Mask
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::MachineInstrBuilder::addDef
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
Definition: MachineInstrBuilder.h:116
llvm::MachineIRBuilder::setCSEInfo
void setCSEInfo(GISelCSEInfo *Info)
Definition: MachineIRBuilder.h:324
llvm::ConstantInt
This is the shared class of boolean and integer constants.
Definition: Constants.h:79
llvm::MachineIRBuilder::getMRI
const MachineRegisterInfo * getMRI() const
Definition: MachineIRBuilder.h:290
llvm::MachineIRBuilder::buildAtomicCmpXchgWithSuccess
MachineInstrBuilder buildAtomicCmpXchgWithSuccess(Register OldValRes, Register SuccessRes, Register Addr, Register CmpVal, Register NewVal, MachineMemOperand &MMO)
Build and insert OldValRes<def>, SuccessRes<def> = G_ATOMIC_CMPXCHG_WITH_SUCCESS Addr,...
Definition: MachineIRBuilder.cpp:808
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:98
llvm::MachineIRBuilder::buildUnmerge
MachineInstrBuilder buildUnmerge(ArrayRef< LLT > Res, const SrcOp &Op)
Build and insert Res0, ...
Definition: MachineIRBuilder.cpp:617
llvm::MachineIRBuilder::buildAtomicRMWMin
MachineInstrBuilder buildAtomicRMWMin(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_MIN Addr, Val, MMO.
Definition: MachineIRBuilder.cpp:934
llvm::MachineIRBuilder::buildZExt
MachineInstrBuilder buildZExt(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_ZEXT Op.
Definition: MachineIRBuilder.cpp:462
llvm::MachineIRBuilder::buildExtractVectorElement
MachineInstrBuilder buildExtractVectorElement(const DstOp &Res, const SrcOp &Val, const SrcOp &Idx)
Build and insert Res = G_EXTRACT_VECTOR_ELT Val, Idx.
Definition: MachineIRBuilder.cpp:803
llvm::MachineIRBuilder::buildLoad
MachineInstrBuilder buildLoad(const DstOp &Res, const SrcOp &Addr, MachineMemOperand &MMO)
Build and insert Res = G_LOAD Addr, MMO.
Definition: MachineIRBuilder.h:904
llvm::MachineIRBuilder::MachineIRBuilder
MachineIRBuilder(const MachineIRBuilderState &BState)
Definition: MachineIRBuilder.h:263
llvm::ISD::Constant
@ Constant
Definition: ISDOpcodes.h:76
llvm::MachineIRBuilder::buildShl
MachineInstrBuilder buildShl(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Definition: MachineIRBuilder.h:1571
llvm::MachineIRBuilder::setMBB
void setMBB(MachineBasicBlock &MBB)
Set the insertion point to the end of MBB.
Definition: MachineIRBuilder.h:333
llvm::DstOp::LLTTy
LLT LLTTy
Definition: MachineIRBuilder.h:69
llvm::DstOp::addDefToMIB
void addDefToMIB(MachineRegisterInfo &MRI, MachineInstrBuilder &MIB) const
Definition: MachineIRBuilder.h:82
llvm::MachineIRBuilder::buildSAdde
MachineInstrBuilder buildSAdde(const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1, const SrcOp &CarryIn)
Build and insert Res, CarryOut = G_SADDE Op0, Op1, CarryInp.
Definition: MachineIRBuilder.h:609
llvm::DstOp::DstType::Ty_RC
@ Ty_RC
llvm::DstOp::getReg
Register getReg() const
Definition: MachineIRBuilder.h:108
llvm::MachineIRBuilder::buildFLog
MachineInstrBuilder buildFLog(const DstOp &Dst, const SrcOp &Src, Optional< unsigned > Flags=None)
Build and insert Dst = G_FLOG Src.
Definition: MachineIRBuilder.h:1739
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::MachineIRBuilder::buildBoolExt
MachineInstrBuilder buildBoolExt(const DstOp &Res, const SrcOp &Op, bool IsFP)
Definition: MachineIRBuilder.cpp:479
llvm::MachineInstr::getOperand
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:526
llvm::MachineIRBuilder::buildPtrToInt
MachineInstrBuilder buildPtrToInt(const DstOp &Dst, const SrcOp &Src)
Build and insert a G_PTRTOINT instruction.
Definition: MachineIRBuilder.h:667
llvm::MachineIRBuilder::recordInsertion
void recordInsertion(MachineInstr *InsertedInstr) const
Definition: MachineIRBuilder.h:235
llvm::MachineIRBuilder::buildAnyExtOrTrunc
MachineInstrBuilder buildAnyExtOrTrunc(const DstOp &Res, const SrcOp &Op)
Res = COPY Op depending on the differing sizes of Res and Op.
Definition: MachineIRBuilder.cpp:537
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::MachineIRBuilder::buildFCmp
MachineInstrBuilder buildFCmp(CmpInst::Predicate Pred, const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1, Optional< unsigned > Flags=None)
Build and insert a Res = G_FCMP PredOp0, Op1.
Definition: MachineIRBuilder.cpp:778
llvm::MachineIRBuilder::buildFIDbgValue
MachineInstrBuilder buildFIDbgValue(int FI, const MDNode *Variable, const MDNode *Expr)
Build and insert a DBG_VALUE instruction expressing the fact that the associated Variable lives in th...
Definition: MachineIRBuilder.cpp:75
llvm::MachineIRBuilder::buildCTLZ
MachineInstrBuilder buildCTLZ(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_CTLZ Op0, Src0.
Definition: MachineIRBuilder.h:1649
TargetOpcodes.h
llvm::MachineIRBuilder::buildConcatVectors
MachineInstrBuilder buildConcatVectors(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_CONCAT_VECTORS Op0, ...
Definition: MachineIRBuilder.cpp:712
llvm::dwarf::Index
Index
Definition: Dwarf.h:472
llvm::MachineIRBuilder::getDataLayout
const DataLayout & getDataLayout() const
Definition: MachineIRBuilder.h:281
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48
llvm::MachineIRBuilder::MachineIRBuilder
MachineIRBuilder(MachineFunction &MF)
Definition: MachineIRBuilder.h:243
llvm::DstOp::getDstOpKind
DstType getDstOpKind() const
Definition: MachineIRBuilder.h:122
llvm::MachineIRBuilder::buildAtomicRMWAnd
MachineInstrBuilder buildAtomicRMWAnd(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_AND Addr, Val, MMO.
Definition: MachineIRBuilder.cpp:903
llvm::MachineIRBuilder::getMF
MachineFunction & getMF()
Getter for the function we currently build.
Definition: MachineIRBuilder.h:271
llvm::ConstantFP
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:257
llvm::MachineIRBuilder::buildFFloor
MachineInstrBuilder buildFFloor(const DstOp &Dst, const SrcOp &Src0, Optional< unsigned > Flags=None)
Build and insert Res = GFFLOOR Op0, Op1.
Definition: MachineIRBuilder.h:1733
DebugLoc.h
llvm::MachineIRBuilder::buildAnd
MachineInstrBuilder buildAnd(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_AND Op0, Op1.
Definition: MachineIRBuilder.h:1600
llvm::MachineIRBuilder::buildAssertOp
MachineInstrBuilder buildAssertOp(unsigned Opc, const DstOp &Res, const SrcOp &Op, unsigned Val)
Build and insert G_ASSERT_SEXT, G_ASSERT_ZEXT, or G_ASSERT_ALIGN.
Definition: MachineIRBuilder.h:866
llvm::MachineIRBuilder::getMBB
MachineBasicBlock & getMBB()
Definition: MachineIRBuilder.h:301
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::MachineIRBuilder::buildSMin
MachineInstrBuilder buildSMin(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_SMIN Op0, Op1.
Definition: MachineIRBuilder.h:1790
llvm::DstOp::DstOp
DstOp(Register R)
Definition: MachineIRBuilder.h:77
llvm::MachineIRBuilder::buildVecReduceOr
MachineInstrBuilder buildVecReduceOr(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_OR Src.
Definition: MachineIRBuilder.h:1893
llvm::MachineIRBuilder::buildIndirectDbgValue
MachineInstrBuilder buildIndirectDbgValue(Register Reg, const MDNode *Variable, const MDNode *Expr)
Build and insert a DBG_VALUE instruction expressing the fact that the associated Variable lives in me...
Definition: MachineIRBuilder.cpp:63
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::MachineIRBuilder::buildBrCond
MachineInstrBuilder buildBrCond(const SrcOp &Tst, MachineBasicBlock &Dest)
Build and insert G_BRCOND Tst, Dest.
Definition: MachineIRBuilder.cpp:370
llvm::MachineIRBuilder::buildLoadInstr
MachineInstrBuilder buildLoadInstr(unsigned Opcode, const DstOp &Res, const SrcOp &Addr, MachineMemOperand &MMO)
Build and insert Res = <opcode> Addr, MMO.
Definition: MachineIRBuilder.cpp:394
llvm::DstOp::DstOp
DstOp(unsigned R)
Definition: MachineIRBuilder.h:76
llvm::MachineIRBuilder::getPCSections
MDNode * getPCSections()
Get the current instruction's PC sections metadata.
Definition: MachineIRBuilder.h:374
llvm::None
const NoneType None
Definition: None.h:24
llvm::MachineIRBuilder::buildAtomicRMWMax
MachineInstrBuilder buildAtomicRMWMax(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_MAX Addr, Val, MMO.
Definition: MachineIRBuilder.cpp:928
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::MachineIRBuilder::buildBrIndirect
MachineInstrBuilder buildBrIndirect(Register Tgt)
Build and insert G_BRINDIRECT Tgt.
Definition: MachineIRBuilder.cpp:272
llvm::MachineIRBuilder::buildVecReduceFMul
MachineInstrBuilder buildVecReduceFMul(const DstOp &Dst, const SrcOp &ScalarIn, const SrcOp &VecIn)
Build and insert Res = G_VECREDUCE_FMUL Src.
Definition: MachineIRBuilder.h:1862
llvm::MachineIRBuilder::validateUnaryOp
void validateUnaryOp(const LLT Res, const LLT Op0)
Definition: MachineIRBuilder.cpp:173
llvm::MachineIRBuilder::buildFNeg
MachineInstrBuilder buildFNeg(const DstOp &Dst, const SrcOp &Src0, Optional< unsigned > Flags=None)
Build and insert Res = G_FNEG Op0.
Definition: MachineIRBuilder.h:1709
llvm::MachineIRBuilder::buildCTPOP
MachineInstrBuilder buildCTPOP(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_CTPOP Op0, Src0.
Definition: MachineIRBuilder.h:1644
llvm::SrcOp::getImm
int64_t getImm() const
Definition: MachineIRBuilder.h:202
llvm::MachineIRBuilder::buildVecReduceXor
MachineInstrBuilder buildVecReduceXor(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_XOR Src.
Definition: MachineIRBuilder.h:1898
llvm::ISD::BlockAddress
@ BlockAddress
Definition: ISDOpcodes.h:84
llvm::SrcOp::SrcOp
SrcOp(const MachineOperand &Op)
Definition: MachineIRBuilder.h:139
llvm::MachineIRBuilder::buildBr
MachineInstrBuilder buildBr(MachineBasicBlock &Dest)
Build and insert G_BR Dest.
Definition: MachineIRBuilder.cpp:268
llvm::MachineIRBuilder::buildMaskLowPtrBits
MachineInstrBuilder buildMaskLowPtrBits(const DstOp &Res, const SrcOp &Op0, uint32_t NumBits)
Build and insert Res = G_PTRMASK Op0, G_CONSTANT (1 << NumBits) - 1.
Definition: MachineIRBuilder.cpp:216
llvm::APFloat
Definition: APFloat.h:707
llvm::MachineIRBuilder::buildAbs
MachineInstrBuilder buildAbs(const DstOp &Dst, const SrcOp &Src)
Build and insert Dst = G_ABS Src.
Definition: MachineIRBuilder.h:1814
llvm::MachineIRBuilder::buildFAdd
MachineInstrBuilder buildFAdd(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Build and insert Res = G_FADD Op0, Op1.
Definition: MachineIRBuilder.h:1674
llvm::MachineIRBuilder::buildFMinNum
MachineInstrBuilder buildFMinNum(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Definition: MachineIRBuilder.h:1547
llvm::SrcOp::SrcOp
SrcOp(Register R)
Definition: MachineIRBuilder.h:138
llvm::GlobalValue
Definition: GlobalValue.h:44
llvm::MachineIRBuilder::buildFConstant
virtual MachineInstrBuilder buildFConstant(const DstOp &Res, const ConstantFP &Val)
Build and insert Res = G_FCONSTANT Val.
Definition: MachineIRBuilder.cpp:322
llvm::MachineIRBuilder::buildUbfx
MachineInstrBuilder buildUbfx(const DstOp &Dst, const SrcOp &Src, const SrcOp &LSB, const SrcOp &Width)
Build and insert Dst = G_UBFX Src, LSB, Width.
Definition: MachineIRBuilder.h:1949
llvm::Constant
This is an important base class in LLVM.
Definition: Constant.h:41
llvm::MachineIRBuilder::buildBrJT
MachineInstrBuilder buildBrJT(Register TablePtr, unsigned JTI, Register IndexReg)
Build and insert G_BRJT TablePtr, JTI, IndexReg.
Definition: MachineIRBuilder.cpp:277
llvm::MachineIRBuilder::buildSExtOrTrunc
MachineInstrBuilder buildSExtOrTrunc(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_SEXT Op, Res = G_TRUNC Op, or Res = COPY Op depending on the differing sizes...
Definition: MachineIRBuilder.cpp:527
llvm::MachineIRBuilder::setInsertPt
void setInsertPt(MachineBasicBlock &MBB, MachineBasicBlock::iterator II)
Set the insertion point before the specified position.
Definition: MachineIRBuilder.h:315
llvm::MachineIRBuilder
Helper class to build MachineInstr.
Definition: MachineIRBuilder.h:221
llvm::DstOp::Reg
Register Reg
Definition: MachineIRBuilder.h:70
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:69
uint64_t
llvm::SrcOp::SrcType
SrcType
Definition: MachineIRBuilder.h:137
llvm::GlobalValue::getParent
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:650
Addr
uint64_t Addr
Definition: ELFObjHandler.cpp:78
llvm::MachineIRBuilder::buildUMax
MachineInstrBuilder buildUMax(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_UMAX Op0, Op1.
Definition: MachineIRBuilder.h:1808
llvm::MachineIRBuilder::buildBitcast
MachineInstrBuilder buildBitcast(const DstOp &Dst, const SrcOp &Src)
Build and insert Dst = G_BITCAST Src.
Definition: MachineIRBuilder.h:677
llvm::MachineIRBuilder::buildMul
MachineInstrBuilder buildMul(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Build and insert Res = G_MUL Op0, Op1.
Definition: MachineIRBuilder.h:1516
llvm::SrcOp::SrcType::Ty_Reg
@ Ty_Reg
llvm::MachineIRBuilder::getInsertPt
MachineBasicBlock::iterator getInsertPt()
Current insertion point for new instructions.
Definition: MachineIRBuilder.h:310
llvm::MachineIRBuilder::buildIntrinsicTrunc
MachineInstrBuilder buildIntrinsicTrunc(const DstOp &Dst, const SrcOp &Src0, Optional< unsigned > Flags=None)
Build and insert Dst = G_INTRINSIC_TRUNC Src0.
Definition: MachineIRBuilder.h:1727
llvm::MachinePointerInfo
This class contains a discriminated union of information about pointers in memory operands,...
Definition: MachineMemOperand.h:39
llvm::MachineIRBuilder::setInstrAndDebugLoc
void setInstrAndDebugLoc(MachineInstr &MI)
Set the insertion point to before MI, and set the debug loc to MI's loc.
Definition: MachineIRBuilder.h:352
llvm::MachineIRBuilder::buildPtrAdd
MachineInstrBuilder buildPtrAdd(const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1)
Build and insert Res = G_PTR_ADD Op0, Op1.
Definition: MachineIRBuilder.cpp:190
llvm::MachineIRBuilder::buildRotateLeft
MachineInstrBuilder buildRotateLeft(const DstOp &Dst, const SrcOp &Src, const SrcOp &Amt)
Build and insert Dst = G_ROTL Src, Amt.
Definition: MachineIRBuilder.h:1961
llvm::MachineIRBuilder::buildFPTOSI
MachineInstrBuilder buildFPTOSI(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_FPTOSI Src0.
Definition: MachineIRBuilder.h:1785
llvm::MachineIRBuilder::buildAtomicRMWNand
MachineInstrBuilder buildAtomicRMWNand(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_NAND Addr, Val, MMO.
Definition: MachineIRBuilder.cpp:909
llvm::MachineIRBuilder::buildAtomicRMWFMax
MachineInstrBuilder buildAtomicRMWFMax(const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_FMAX Addr, Val, MMO.
Definition: MachineIRBuilder.cpp:968
llvm::MachineIRBuilder::buildSelect
MachineInstrBuilder buildSelect(const DstOp &Res, const SrcOp &Tst, const SrcOp &Op0, const SrcOp &Op1, Optional< unsigned > Flags=None)
Build and insert a Res = G_SELECT Tst, Op0, Op1.
Definition: MachineIRBuilder.cpp:787
llvm::MachineMemOperand::Flags
Flags
Flags values. These may be or'd together.
Definition: MachineMemOperand.h:130
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MachineIRBuilder::buildConstDbgValue
MachineInstrBuilder buildConstDbgValue(const Constant &C, const MDNode *Variable, const MDNode *Expr)
Build and insert a DBG_VALUE instructions specifying that Variable is given by C (suitably modified b...
Definition: MachineIRBuilder.cpp:90
llvm::MachineIRBuilder::buildMemTransferInst
MachineInstrBuilder buildMemTransferInst(unsigned Opcode, const SrcOp &DstPtr, const SrcOp &SrcPtr, const SrcOp &Size, MachineMemOperand &DstMMO, MachineMemOperand &SrcMMO)
Build and insert G_MEMCPY or G_MEMMOVE.
Definition: MachineIRBuilder.h:1923
llvm::MachineIRBuilder::getMBB
const MachineBasicBlock & getMBB() const
Getter for the basic block we currently build.
Definition: MachineIRBuilder.h:296
llvm::MachineInstrBuilder::addMemOperand
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
Definition: MachineInstrBuilder.h:202
llvm::MachineIRBuilder::MachineIRBuilder
MachineIRBuilder(MachineInstr &MI)
Definition: MachineIRBuilder.h:250
llvm::SrcOp::getSrcOpKind
SrcType getSrcOpKind() const
Definition: MachineIRBuilder.h:211
llvm::MachineIRBuilder::MachineIRBuilder
MachineIRBuilder(MachineInstr &MI, GISelChangeObserver &Observer)
Definition: MachineIRBuilder.h:256
llvm::MachineIRBuilder::buildFMaxNumIEEE
MachineInstrBuilder buildFMaxNumIEEE(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Definition: MachineIRBuilder.h:1565
llvm::MachineIRBuilder::buildUAddo
MachineInstrBuilder buildUAddo(const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1)
Build and insert Res, CarryOut = G_UADDO Op0, Op1.
Definition: MachineIRBuilder.h:556
llvm::MachineIRBuilder::buildAssertZExt
MachineInstrBuilder buildAssertZExt(const DstOp &Res, const SrcOp &Op, unsigned Size)
Build and insert Res = G_ASSERT_ZEXT Op, Size.
Definition: MachineIRBuilder.h:874
llvm::MachineInstrBuilder::addUse
const MachineInstrBuilder & addUse(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
Definition: MachineInstrBuilder.h:123
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:359
llvm::MachineIRBuilder::buildAtomicRMWFAdd
MachineInstrBuilder buildAtomicRMWFAdd(const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_FADD Addr, Val, MMO.
Definition: MachineIRBuilder.cpp:953
llvm::MDNode
Metadata node.
Definition: Metadata.h:944
llvm::SrcOp::SrcOp
SrcOp(uint64_t V)
Definition: MachineIRBuilder.h:147
llvm::SrcOp::Pred
CmpInst::Predicate Pred
Definition: MachineIRBuilder.h:132
llvm::MachineIRBuilder::buildFMA
MachineInstrBuilder buildFMA(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, const SrcOp &Src2, Optional< unsigned > Flags=None)
Build and insert Res = G_FMA Op0, Op1, Op2.
Definition: MachineIRBuilder.h:1695
llvm::GISelChangeObserver::createdInstr
virtual void createdInstr(MachineInstr &MI)=0
An instruction has been created and inserted into the function.
llvm::MachineIRBuilder::setChangeObserver
void setChangeObserver(GISelChangeObserver &Observer)
Definition: MachineIRBuilder.h:357
llvm::MachineIRBuilder::buildVecReduceFMax
MachineInstrBuilder buildVecReduceFMax(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_FMAX Src.
Definition: MachineIRBuilder.h:1869
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::MachineIRBuilder::buildVecReduceSMax
MachineInstrBuilder buildVecReduceSMax(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_SMAX Src.
Definition: MachineIRBuilder.h:1903
llvm::MachineIRBuilderState::Observer
GISelChangeObserver * Observer
Definition: MachineIRBuilder.h:62
llvm::MachineIRBuilder::buildInstr
MachineInstrBuilder buildInstr(unsigned Opcode)
Build and insert <empty> = Opcode <empty>.
Definition: MachineIRBuilder.h:383
llvm::BlockAddress
The address of a basic block.
Definition: Constants.h:849
llvm::SrcOp::addSrcToMIB
void addSrcToMIB(MachineInstrBuilder &MIB) const
Definition: MachineIRBuilder.h:150
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::MachineIRBuilder::buildVecReduceFAdd
MachineInstrBuilder buildVecReduceFAdd(const DstOp &Dst, const SrcOp &ScalarIn, const SrcOp &VecIn)
Build and insert Res = G_VECREDUCE_FADD Src.
Definition: MachineIRBuilder.h:1852
llvm::SrcOp::getReg
Register getReg() const
Definition: MachineIRBuilder.h:180
llvm::MachineIRBuilder::insertInstr
MachineInstrBuilder insertInstr(MachineInstrBuilder MIB)
Insert an existing instruction at the insertion point.
Definition: MachineIRBuilder.cpp:43
llvm::MachineIRBuilder::buildAssertAlign
MachineInstrBuilder buildAssertAlign(const DstOp &Res, const SrcOp &Op, Align AlignVal)
Build and insert Res = G_ASSERT_ALIGN Op, AlignVal.
Definition: MachineIRBuilder.h:890
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::MachineIRBuilder::buildCopy
MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op)
Build and insert Res = COPY Op.
Definition: MachineIRBuilder.cpp:288
llvm::MachineIRBuilder::buildFPTOUI
MachineInstrBuilder buildFPTOUI(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_FPTOUI Src0.
Definition: MachineIRBuilder.h:1780
llvm::MachineIRBuilder::buildFPExt
MachineInstrBuilder buildFPExt(const DstOp &Res, const SrcOp &Op, Optional< unsigned > Flags=None)
Build and insert Res = G_FPEXT Op.
Definition: MachineIRBuilder.h:660
getParent
static const Function * getParent(const Value *V)
Definition: BasicAliasAnalysis.cpp:838
uint32_t
llvm::SrcOp::SrcOp
SrcOp(const CmpInst::Predicate P)
Definition: MachineIRBuilder.h:141
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::MachineIRBuilder::buildInsert
MachineInstrBuilder buildInsert(const DstOp &Res, const SrcOp &Src, const SrcOp &Op, unsigned Index)
Definition: MachineIRBuilder.cpp:720
llvm::DstOp::DstOp
DstOp(const MachineOperand &Op)
Definition: MachineIRBuilder.h:78
llvm::MachineIRBuilder::buildFLog2
MachineInstrBuilder buildFLog2(const DstOp &Dst, const SrcOp &Src, Optional< unsigned > Flags=None)
Build and insert Dst = G_FLOG2 Src.
Definition: MachineIRBuilder.h:1745
llvm::MachineIRBuilderState::TII
const TargetInstrInfo * TII
Information used to access the description of the opcodes.
Definition: MachineIRBuilder.h:48
llvm::MachineIRBuilder::buildExtract
MachineInstrBuilder buildExtract(const DstOp &Res, const SrcOp &Src, uint64_t Index)
Build and insert Res0, ...
Definition: MachineIRBuilder.cpp:571
llvm::MachineInstrBuilder::addPredicate
const MachineInstrBuilder & addPredicate(CmpInst::Predicate Pred) const
Definition: MachineInstrBuilder.h:257
llvm::MachineIRBuilder::buildVecReduceUMax
MachineInstrBuilder buildVecReduceUMax(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_UMAX Src.
Definition: MachineIRBuilder.h:1913
llvm::GISelChangeObserver
Abstract class that contains various methods for clients to notify about changes.
Definition: GISelChangeObserver.h:29
llvm::MachineIRBuilder::buildSExtInReg
MachineInstrBuilder buildSExtInReg(const DstOp &Res, const SrcOp &Op, int64_t ImmOp)
Build and insert Res = G_SEXT_INREG Op, ImmOp.
Definition: MachineIRBuilder.h:655
llvm::MachineIRBuilder::buildNot
MachineInstrBuilder buildNot(const DstOp &Dst, const SrcOp &Src0)
Build and insert a bitwise not, NegOne = G_CONSTANT -1 Res = G_OR Op0, NegOne.
Definition: MachineIRBuilder.h:1630
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::MachineIRBuilder::buildAnyExt
MachineInstrBuilder buildAnyExt(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_ANYEXT Op0.
Definition: MachineIRBuilder.cpp:452
llvm::MachineIRBuilder::materializePtrAdd
Optional< MachineInstrBuilder > materializePtrAdd(Register &Res, Register Op0, const LLT ValueTy, uint64_t Value)
Materialize and insert Res = G_PTR_ADD Op0, (G_CONSTANT Value)
Definition: MachineIRBuilder.cpp:201
llvm::MachineIRBuilder::buildJumpTable
MachineInstrBuilder buildJumpTable(const LLT PtrTy, unsigned JTI)
Build and insert Res = G_JUMP_TABLE JTI.
Definition: MachineIRBuilder.cpp:167
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::DstOp::DstType
DstType
Definition: MachineIRBuilder.h:75
llvm::MachineIRBuilder::buildFrameIndex
MachineInstrBuilder buildFrameIndex(const DstOp &Res, int Idx)
Build and insert Res = G_FRAME_INDEX Idx.
Definition: MachineIRBuilder.cpp:145
llvm::SrcOp::SrcMIB
MachineInstrBuilder SrcMIB
Definition: MachineIRBuilder.h:130
llvm::MachineIRBuilder::buildSSube
MachineInstrBuilder buildSSube(const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1, const SrcOp &CarryIn)
Build and insert Res, CarryOut = G_SSUBE Op0, Op1, CarryInp.
Definition: MachineIRBuilder.h:617
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::MachineIRBuilder::buildUAdde
MachineInstrBuilder buildUAdde(const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1, const SrcOp &CarryIn)
Build and insert Res, CarryOut = G_UADDE Op0, Op1, CarryIn.
Definition: MachineIRBuilder.h:593
llvm::MachineIRBuilder::buildUITOFP
MachineInstrBuilder buildUITOFP(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_UITOFP Src0.
Definition: MachineIRBuilder.h:1770
llvm::MachineIRBuilder::buildVecReduceSeqFAdd
MachineInstrBuilder buildVecReduceSeqFAdd(const DstOp &Dst, const SrcOp &ScalarIn, const SrcOp &VecIn)
Build and insert Res = G_VECREDUCE_SEQ_FADD ScalarIn, VecIn.
Definition: MachineIRBuilder.h:1830
llvm::MachineIRBuilder::buildVecReduceAnd
MachineInstrBuilder buildVecReduceAnd(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_AND Src.
Definition: MachineIRBuilder.h:1888
llvm::MachineIRBuilder::buildSAddo
MachineInstrBuilder buildSAddo(const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1)
Build and insert Res, CarryOut = G_SADDO Op0, Op1.
Definition: MachineIRBuilder.h:568
llvm::SrcOp::SrcType::Ty_Imm
@ Ty_Imm
llvm::MachineIRBuilder::buildFPow
MachineInstrBuilder buildFPow(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Build and insert Dst = G_FPOW Src0, Src1.
Definition: MachineIRBuilder.h:1757
llvm::MachineIRBuilder::buildTrunc
MachineInstrBuilder buildTrunc(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_TRUNC Op.
Definition: MachineIRBuilder.cpp:760
llvm::MachineIRBuilder::buildMemCpy
MachineInstrBuilder buildMemCpy(const SrcOp &DstPtr, const SrcOp &SrcPtr, const SrcOp &Size, MachineMemOperand &DstMMO, MachineMemOperand &SrcMMO)
Definition: MachineIRBuilder.h:1935
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:622
llvm::MachineIRBuilder::~MachineIRBuilder
virtual ~MachineIRBuilder()=default
llvm::MachineIRBuilder::buildVecReduceMul
MachineInstrBuilder buildVecReduceMul(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_MUL Src.
Definition: MachineIRBuilder.h:1883
llvm::MachineIRBuilderState::DL
DebugLoc DL
Debug location to be set to any instruction we create.
Definition: MachineIRBuilder.h:52
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:348
llvm::MachineIRBuilder::buildSITOFP
MachineInstrBuilder buildSITOFP(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_SITOFP Src0.
Definition: MachineIRBuilder.h:1775
llvm::Align::value
uint64_t value() const
This is a hole in the type system and should not be abused.
Definition: Alignment.h:85
llvm::MachineIRBuilder::buildUndef
MachineInstrBuilder buildUndef(const DstOp &Res)
Build and insert Res = IMPLICIT_DEF.
Definition: MachineIRBuilder.cpp:596
llvm::MachineIRBuilder::buildDirectDbgValue
MachineInstrBuilder buildDirectDbgValue(Register Reg, const MDNode *Variable, const MDNode *Expr)
Build and insert a DBG_VALUE instruction expressing the fact that the associated Variable lives in Re...
Definition: MachineIRBuilder.cpp:50
llvm::MachineIRBuilder::buildVecReduceUMin
MachineInstrBuilder buildVecReduceUMin(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_UMIN Src.
Definition: MachineIRBuilder.h:1918
llvm::MachineIRBuilder::buildAtomicRMWUmin
MachineInstrBuilder buildAtomicRMWUmin(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_UMIN Addr, Val, MMO.
Definition: MachineIRBuilder.cpp:946
llvm::MachineIRBuilder::buildShuffleVector
MachineInstrBuilder buildShuffleVector(const DstOp &Res, const SrcOp &Src1, const SrcOp &Src2, ArrayRef< int > Mask)
Build and insert Res = G_SHUFFLE_VECTOR Src1, Src2, Mask.
Definition: MachineIRBuilder.cpp:692
llvm::MachineIRBuilder::buildBuildVectorConstant
MachineInstrBuilder buildBuildVectorConstant(const DstOp &Res, ArrayRef< APInt > Ops)
Build and insert Res = G_BUILD_VECTOR Op0, ...
Definition: MachineIRBuilder.cpp:654
llvm::SrcOp::SrcOp
SrcOp(int64_t V)
Definition: MachineIRBuilder.h:148
llvm::MachineIRBuilder::buildAtomicRMWXor
MachineInstrBuilder buildAtomicRMWXor(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_XOR Addr, Val, MMO.
Definition: MachineIRBuilder.cpp:922
llvm::MachineIRBuilder::buildPadVectorWithUndefElements
MachineInstrBuilder buildPadVectorWithUndefElements(const DstOp &Res, const SrcOp &Op0)
Build and insert a, b, ..., x = G_UNMERGE_VALUES Op0 Res = G_BUILD_VECTOR a, b, .....
Definition: MachineIRBuilder.cpp:227
llvm::MachineIRBuilder::getTII
const TargetInstrInfo & getTII()
Definition: MachineIRBuilder.h:265
llvm::MachineIRBuilder::buildRotateRight
MachineInstrBuilder buildRotateRight(const DstOp &Dst, const SrcOp &Src, const SrcOp &Amt)
Build and insert Dst = G_ROTR Src, Amt.
Definition: MachineIRBuilder.h:1955
llvm::MachineIRBuilderState::MF
MachineFunction * MF
MachineFunction under construction.
Definition: MachineIRBuilder.h:46
llvm::SrcOp::getPredicate
CmpInst::Predicate getPredicate() const
Definition: MachineIRBuilder.h:193
llvm::MachineIRBuilderState::PCSections
MDNode * PCSections
PC sections metadata to be set to any instruction we create.
Definition: MachineIRBuilder.h:54
llvm::MachineIRBuilder::buildDeleteTrailingVectorElements
MachineInstrBuilder buildDeleteTrailingVectorElements(const DstOp &Res, const SrcOp &Op0)
Build and insert a, b, ..., x, y, z = G_UNMERGE_VALUES Op0 Res = G_BUILD_VECTOR a,...
Definition: MachineIRBuilder.cpp:250
llvm::AMDGPU::Hwreg::Width
Width
Definition: SIDefines.h:439
llvm::MachineIRBuilder::buildVecReduceSeqFMul
MachineInstrBuilder buildVecReduceSeqFMul(const DstOp &Dst, const SrcOp &ScalarIn, const SrcOp &VecIn)
Build and insert Res = G_VECREDUCE_SEQ_FMUL ScalarIn, VecIn.
Definition: MachineIRBuilder.h:1841
llvm::MachineIRBuilder::buildFMinNumIEEE
MachineInstrBuilder buildFMinNumIEEE(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Definition: MachineIRBuilder.h:1559
llvm::MachineIRBuilder::buildAddrSpaceCast
MachineInstrBuilder buildAddrSpaceCast(const DstOp &Dst, const SrcOp &Src)
Build and insert Dst = G_ADDRSPACE_CAST Src.
Definition: MachineIRBuilder.h:682
llvm::MachineIRBuilder::buildBlockAddress
MachineInstrBuilder buildBlockAddress(Register Res, const BlockAddress *BA)
Build and insert Res = G_BLOCK_ADDR BA.
Definition: MachineIRBuilder.cpp:989
llvm::MachineIRBuilder::validateTruncExt
void validateTruncExt(const LLT Dst, const LLT Src, bool IsExtend)
Definition: MachineIRBuilder.cpp:997
llvm::DstOp::getLLTTy
LLT getLLTTy(const MachineRegisterInfo &MRI) const
Definition: MachineIRBuilder.h:96
llvm::MachineIRBuilder::buildAtomicRMWUmax
MachineInstrBuilder buildAtomicRMWUmax(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_UMAX Addr, Val, MMO.
Definition: MachineIRBuilder.cpp:940
llvm::MachineIRBuilder::buildBoolExtInReg
MachineInstrBuilder buildBoolExtInReg(const DstOp &Res, const SrcOp &Op, bool IsVector, bool IsFP)
Definition: MachineIRBuilder.cpp:486
llvm::MachineIRBuilder::validateShiftOp
void validateShiftOp(const LLT Res, const LLT Op0, const LLT Op1)
Definition: MachineIRBuilder.cpp:184
llvm::MachineIRBuilder::buildIntrinsic
MachineInstrBuilder buildIntrinsic(Intrinsic::ID ID, ArrayRef< Register > Res, bool HasSideEffects)
Build and insert either a G_INTRINSIC (if HasSideEffects is false) or G_INTRINSIC_W_SIDE_EFFECTS inst...
Definition: MachineIRBuilder.cpp:736
llvm::MachineIRBuilder::buildSSubo
MachineInstrBuilder buildSSubo(const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1)
Build and insert Res, CarryOut = G_SUBO Op0, Op1.
Definition: MachineIRBuilder.h:574
MachineInstrBuilder.h
llvm::MachineIRBuilder::buildFExp2
MachineInstrBuilder buildFExp2(const DstOp &Dst, const SrcOp &Src, Optional< unsigned > Flags=None)
Build and insert Dst = G_FEXP2 Src.
Definition: MachineIRBuilder.h:1751
llvm::DstOp::DstType::Ty_Reg
@ Ty_Reg
llvm::MachineIRBuilder::buildSExt
MachineInstrBuilder buildSExt(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_SEXT Op.
Definition: MachineIRBuilder.cpp:457
llvm::MachineIRBuilder::buildAssertSExt
MachineInstrBuilder buildAssertSExt(const DstOp &Res, const SrcOp &Op, unsigned Size)
Build and insert Res = G_ASSERT_SEXT Op, Size.
Definition: MachineIRBuilder.h:882
llvm::DstOp
Definition: MachineIRBuilder.h:67
llvm::MachineIRBuilder::buildFMaxNum
MachineInstrBuilder buildFMaxNum(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Definition: MachineIRBuilder.h:1553
llvm::MachineIRBuilder::buildSub
MachineInstrBuilder buildSub(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Build and insert Res = G_SUB Op0, Op1.
Definition: MachineIRBuilder.h:1500
llvm::SrcOp::SrcOp
SrcOp(const MachineInstrBuilder &MIB)
Definition: MachineIRBuilder.h:140
llvm::MachineIRBuilder::buildLShr
MachineInstrBuilder buildLShr(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Definition: MachineIRBuilder.h:1577
llvm::MachineIRBuilder::buildFDiv
MachineInstrBuilder buildFDiv(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Build and insert Res = G_FDIV Op0, Op1.
Definition: MachineIRBuilder.h:1688
llvm::MachineIRBuilder::buildMerge
MachineInstrBuilder buildMerge(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_MERGE_VALUES Op0, ...
Definition: MachineIRBuilder.cpp:600
llvm::SrcOp::getLLTTy
LLT getLLTTy(const MachineRegisterInfo &MRI) const
Definition: MachineIRBuilder.h:167
llvm::MachineIRBuilder::buildLoadFromOffset
MachineInstrBuilder buildLoadFromOffset(const DstOp &Dst, const SrcOp &BasePtr, MachineMemOperand &BaseMMO, int64_t Offset)
Helper to create a load from a constant offset given a base address.
Definition: MachineIRBuilder.cpp:408
llvm::MachineIRBuilder::buildAtomicRMWSub
MachineInstrBuilder buildAtomicRMWSub(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_SUB Addr, Val, MMO.
Definition: MachineIRBuilder.cpp:897
llvm::Module::getDataLayout
const DataLayout & getDataLayout() const
Get the data layout for the module's target platform.
Definition: Module.cpp:398
llvm::MachineIRBuilder::buildBuildVectorTrunc
MachineInstrBuilder buildBuildVectorTrunc(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_BUILD_VECTOR_TRUNC Op0, ...
Definition: MachineIRBuilder.cpp:671
llvm::MachineIRBuilder::getBoolExtOp
unsigned getBoolExtOp(bool IsVec, bool IsFP) const
Definition: MachineIRBuilder.cpp:467
llvm::MachineIRBuilder::buildFreeze
MachineInstrBuilder buildFreeze(const DstOp &Dst, const SrcOp &Src)
Build and insert Dst = G_FREEZE Src.
Definition: MachineIRBuilder.h:1458
llvm::MachineIRBuilder::getState
MachineIRBuilderState & getState()
Getter for the State.
Definition: MachineIRBuilder.h:293
llvm::MachineIRBuilder::buildCTTZ_ZERO_UNDEF
MachineInstrBuilder buildCTTZ_ZERO_UNDEF(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_CTTZ_ZERO_UNDEF Op0, Src0.
Definition: MachineIRBuilder.h:1664
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
GISelChangeObserver.h
llvm::MachineIRBuilder::buildStore
MachineInstrBuilder buildStore(const SrcOp &Val, const SrcOp &Addr, MachineMemOperand &MMO)
Build and insert G_STORE Val, Addr, MMO.
Definition: MachineIRBuilder.cpp:425
llvm::MachineIRBuilder::buildAtomicRMWXchg
MachineInstrBuilder buildAtomicRMWXchg(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_XCHG Addr, Val, MMO.
Definition: MachineIRBuilder.cpp:885
llvm::MachineIRBuilder::buildAdd
MachineInstrBuilder buildAdd(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Build and insert Res = G_ADD Op0, Op1.
Definition: MachineIRBuilder.h:1483
llvm::MachineIRBuilder::stopObservingChanges
void stopObservingChanges()
Definition: MachineIRBuilder.h:361
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::MachineMemOperand::MONone
@ MONone
Definition: MachineMemOperand.h:132
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::MachineIRBuilderState::CSEInfo
GISelCSEInfo * CSEInfo
Definition: MachineIRBuilder.h:64
llvm::MachineIRBuilderState::MRI
MachineRegisterInfo * MRI
Information used to verify types are consistent and to create virtual registers.
Definition: MachineIRBuilder.h:50
llvm::SrcOp
Definition: MachineIRBuilder.h:128
llvm::SrcOp::SrcType::Ty_MIB
@ Ty_MIB
llvm::MachineIRBuilder::buildCast
MachineInstrBuilder buildCast(const DstOp &Dst, const SrcOp &Src)
Build and insert an appropriate cast between two registers of equal size.
Definition: MachineIRBuilder.cpp:551
llvm::MachineIRBuilder::buildVecReduceSMin
MachineInstrBuilder buildVecReduceSMin(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_SMIN Src.
Definition: MachineIRBuilder.h:1908
llvm::MachineIRBuilder::buildShuffleSplat
MachineInstrBuilder buildShuffleSplat(const DstOp &Res, const SrcOp &Src)
Build and insert a vector splat of a scalar Src using a G_INSERT_VECTOR_ELT and G_SHUFFLE_VECTOR idio...
Definition: MachineIRBuilder.cpp:680
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:38
llvm::LLT
Definition: LowLevelTypeImpl.h:39