LLVM  14.0.0git
MachineIRBuilder.h
Go to the documentation of this file.
1 //===-- llvm/CodeGen/GlobalISel/MachineIRBuilder.h - MIBuilder --*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file declares the MachineIRBuilder class.
10 /// This is a helper class to build MachineInstr.
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_CODEGEN_GLOBALISEL_MACHINEIRBUILDER_H
14 #define LLVM_CODEGEN_GLOBALISEL_MACHINEIRBUILDER_H
15 
22 #include "llvm/IR/Constants.h"
23 #include "llvm/IR/DebugLoc.h"
24 #include "llvm/IR/Module.h"
25 
26 namespace llvm {
27 
28 // Forward declarations.
29 class MachineFunction;
30 class MachineInstr;
31 class TargetInstrInfo;
32 class GISelChangeObserver;
33 
34 /// Class which stores all the state required in a MachineIRBuilder.
35 /// Since MachineIRBuilders will only store state in this object, it allows
36 /// to transfer BuilderState between different kinds of MachineIRBuilders.
38  /// MachineFunction under construction.
39  MachineFunction *MF = nullptr;
40  /// Information used to access the description of the opcodes.
41  const TargetInstrInfo *TII = nullptr;
42  /// Information used to verify types are consistent and to create virtual registers.
44  /// Debug location to be set to any instruction we create.
46 
47  /// \name Fields describing the insertion point.
48  /// @{
49  MachineBasicBlock *MBB = nullptr;
51  /// @}
52 
54 
55  GISelCSEInfo *CSEInfo = nullptr;
56 };
57 
58 class DstOp {
59  union {
63  };
64 
65 public:
66  enum class DstType { Ty_LLT, Ty_Reg, Ty_RC };
67  DstOp(unsigned R) : Reg(R), Ty(DstType::Ty_Reg) {}
68  DstOp(Register R) : Reg(R), Ty(DstType::Ty_Reg) {}
69  DstOp(const MachineOperand &Op) : Reg(Op.getReg()), Ty(DstType::Ty_Reg) {}
70  DstOp(const LLT T) : LLTTy(T), Ty(DstType::Ty_LLT) {}
71  DstOp(const TargetRegisterClass *TRC) : RC(TRC), Ty(DstType::Ty_RC) {}
72 
74  switch (Ty) {
75  case DstType::Ty_Reg:
76  MIB.addDef(Reg);
77  break;
78  case DstType::Ty_LLT:
79  MIB.addDef(MRI.createGenericVirtualRegister(LLTTy));
80  break;
81  case DstType::Ty_RC:
82  MIB.addDef(MRI.createVirtualRegister(RC));
83  break;
84  }
85  }
86 
88  switch (Ty) {
89  case DstType::Ty_RC:
90  return LLT{};
91  case DstType::Ty_LLT:
92  return LLTTy;
93  case DstType::Ty_Reg:
94  return MRI.getType(Reg);
95  }
96  llvm_unreachable("Unrecognised DstOp::DstType enum");
97  }
98 
99  Register getReg() const {
100  assert(Ty == DstType::Ty_Reg && "Not a register");
101  return Reg;
102  }
103 
105  switch (Ty) {
106  case DstType::Ty_RC:
107  return RC;
108  default:
109  llvm_unreachable("Not a RC Operand");
110  }
111  }
112 
113  DstType getDstOpKind() const { return Ty; }
114 
115 private:
116  DstType Ty;
117 };
118 
119 class SrcOp {
120  union {
124  int64_t Imm;
125  };
126 
127 public:
129  SrcOp(Register R) : Reg(R), Ty(SrcType::Ty_Reg) {}
130  SrcOp(const MachineOperand &Op) : Reg(Op.getReg()), Ty(SrcType::Ty_Reg) {}
131  SrcOp(const MachineInstrBuilder &MIB) : SrcMIB(MIB), Ty(SrcType::Ty_MIB) {}
132  SrcOp(const CmpInst::Predicate P) : Pred(P), Ty(SrcType::Ty_Predicate) {}
133  /// Use of registers held in unsigned integer variables (or more rarely signed
134  /// integers) is no longer permitted to avoid ambiguity with upcoming support
135  /// for immediates.
136  SrcOp(unsigned) = delete;
137  SrcOp(int) = delete;
138  SrcOp(uint64_t V) : Imm(V), Ty(SrcType::Ty_Imm) {}
139  SrcOp(int64_t V) : Imm(V), Ty(SrcType::Ty_Imm) {}
140 
141  void addSrcToMIB(MachineInstrBuilder &MIB) const {
142  switch (Ty) {
144  MIB.addPredicate(Pred);
145  break;
146  case SrcType::Ty_Reg:
147  MIB.addUse(Reg);
148  break;
149  case SrcType::Ty_MIB:
150  MIB.addUse(SrcMIB->getOperand(0).getReg());
151  break;
152  case SrcType::Ty_Imm:
153  MIB.addImm(Imm);
154  break;
155  }
156  }
157 
159  switch (Ty) {
161  case SrcType::Ty_Imm:
162  llvm_unreachable("Not a register operand");
163  case SrcType::Ty_Reg:
164  return MRI.getType(Reg);
165  case SrcType::Ty_MIB:
166  return MRI.getType(SrcMIB->getOperand(0).getReg());
167  }
168  llvm_unreachable("Unrecognised SrcOp::SrcType enum");
169  }
170 
171  Register getReg() const {
172  switch (Ty) {
174  case SrcType::Ty_Imm:
175  llvm_unreachable("Not a register operand");
176  case SrcType::Ty_Reg:
177  return Reg;
178  case SrcType::Ty_MIB:
179  return SrcMIB->getOperand(0).getReg();
180  }
181  llvm_unreachable("Unrecognised SrcOp::SrcType enum");
182  }
183 
185  switch (Ty) {
187  return Pred;
188  default:
189  llvm_unreachable("Not a register operand");
190  }
191  }
192 
193  int64_t getImm() const {
194  switch (Ty) {
195  case SrcType::Ty_Imm:
196  return Imm;
197  default:
198  llvm_unreachable("Not an immediate");
199  }
200  }
201 
202  SrcType getSrcOpKind() const { return Ty; }
203 
204 private:
205  SrcType Ty;
206 };
207 
208 /// Helper class to build MachineInstr.
209 /// It keeps internally the insertion point and debug location for all
210 /// the new instructions we want to create.
211 /// This information can be modify via the related setters.
213 
214  MachineIRBuilderState State;
215 
216 protected:
217  void validateTruncExt(const LLT Dst, const LLT Src, bool IsExtend);
218 
219  void validateUnaryOp(const LLT Res, const LLT Op0);
220  void validateBinaryOp(const LLT Res, const LLT Op0, const LLT Op1);
221  void validateShiftOp(const LLT Res, const LLT Op0, const LLT Op1);
222 
223  void validateSelectOp(const LLT ResTy, const LLT TstTy, const LLT Op0Ty,
224  const LLT Op1Ty);
225 
226  void recordInsertion(MachineInstr *InsertedInstr) const {
227  if (State.Observer)
228  State.Observer->createdInstr(*InsertedInstr);
229  }
230 
231 public:
232  /// Some constructors for easy use.
233  MachineIRBuilder() = default;
235 
237  setMF(*MBB.getParent());
238  setInsertPt(MBB, InsPt);
239  }
240 
242  MachineIRBuilder(*MI.getParent(), MI.getIterator()) {
243  setInstr(MI);
244  setDebugLoc(MI.getDebugLoc());
245  }
246 
249  setChangeObserver(Observer);
250  }
251 
252  virtual ~MachineIRBuilder() = default;
253 
254  MachineIRBuilder(const MachineIRBuilderState &BState) : State(BState) {}
255 
257  assert(State.TII && "TargetInstrInfo is not set");
258  return *State.TII;
259  }
260 
261  /// Getter for the function we currently build.
263  assert(State.MF && "MachineFunction is not set");
264  return *State.MF;
265  }
266 
267  const MachineFunction &getMF() const {
268  assert(State.MF && "MachineFunction is not set");
269  return *State.MF;
270  }
271 
272  const DataLayout &getDataLayout() const {
273  return getMF().getFunction().getParent()->getDataLayout();
274  }
275 
276  /// Getter for DebugLoc
277  const DebugLoc &getDL() { return State.DL; }
278 
279  /// Getter for MRI
280  MachineRegisterInfo *getMRI() { return State.MRI; }
281  const MachineRegisterInfo *getMRI() const { return State.MRI; }
282 
283  /// Getter for the State
284  MachineIRBuilderState &getState() { return State; }
285 
286  /// Getter for the basic block we currently build.
287  const MachineBasicBlock &getMBB() const {
288  assert(State.MBB && "MachineBasicBlock is not set");
289  return *State.MBB;
290  }
291 
293  return const_cast<MachineBasicBlock &>(
294  const_cast<const MachineIRBuilder *>(this)->getMBB());
295  }
296 
297  GISelCSEInfo *getCSEInfo() { return State.CSEInfo; }
298  const GISelCSEInfo *getCSEInfo() const { return State.CSEInfo; }
299 
300  /// Current insertion point for new instructions.
302 
303  /// Set the insertion point before the specified position.
304  /// \pre MBB must be in getMF().
305  /// \pre II must be a valid iterator in MBB.
307  assert(MBB.getParent() == &getMF() &&
308  "Basic block is in a different function");
309  State.MBB = &MBB;
310  State.II = II;
311  }
312 
313  /// @}
314 
316 
317  /// \name Setters for the insertion point.
318  /// @{
319  /// Set the MachineFunction where to build instructions.
320  void setMF(MachineFunction &MF);
321 
322  /// Set the insertion point to the end of \p MBB.
323  /// \pre \p MBB must be contained by getMF().
325  State.MBB = &MBB;
326  State.II = MBB.end();
327  assert(&getMF() == MBB.getParent() &&
328  "Basic block is in a different function");
329  }
330 
331  /// Set the insertion point to before MI.
332  /// \pre MI must be in getMF().
334  assert(MI.getParent() && "Instruction is not part of a basic block");
335  setMBB(*MI.getParent());
336  State.II = MI.getIterator();
337  }
338  /// @}
339 
340  /// Set the insertion point to before MI, and set the debug loc to MI's loc.
341  /// \pre MI must be in getMF().
343  setInstr(MI);
344  setDebugLoc(MI.getDebugLoc());
345  }
346 
348  State.Observer = &Observer;
349  }
350 
351  void stopObservingChanges() { State.Observer = nullptr; }
352  /// @}
353 
354  /// Set the debug location to \p DL for all the next build instructions.
355  void setDebugLoc(const DebugLoc &DL) { this->State.DL = DL; }
356 
357  /// Get the current instruction's debug location.
358  const DebugLoc &getDebugLoc() { return State.DL; }
359 
360  /// Build and insert <empty> = \p Opcode <empty>.
361  /// The insertion point is the one set by the last call of either
362  /// setBasicBlock or setMI.
363  ///
364  /// \pre setBasicBlock or setMI must have been called.
365  ///
366  /// \return a MachineInstrBuilder for the newly created instruction.
367  MachineInstrBuilder buildInstr(unsigned Opcode) {
368  return insertInstr(buildInstrNoInsert(Opcode));
369  }
370 
371  /// Build but don't insert <empty> = \p Opcode <empty>.
372  ///
373  /// \pre setMF, setBasicBlock or setMI must have been called.
374  ///
375  /// \return a MachineInstrBuilder for the newly created instruction.
376  MachineInstrBuilder buildInstrNoInsert(unsigned Opcode);
377 
378  /// Insert an existing instruction at the insertion point.
380 
381  /// Build and insert a DBG_VALUE instruction expressing the fact that the
382  /// associated \p Variable lives in \p Reg (suitably modified by \p Expr).
384  const MDNode *Expr);
385 
386  /// Build and insert a DBG_VALUE instruction expressing the fact that the
387  /// associated \p Variable lives in memory at \p Reg (suitably modified by \p
388  /// Expr).
390  const MDNode *Variable,
391  const MDNode *Expr);
392 
393  /// Build and insert a DBG_VALUE instruction expressing the fact that the
394  /// associated \p Variable lives in the stack slot specified by \p FI
395  /// (suitably modified by \p Expr).
396  MachineInstrBuilder buildFIDbgValue(int FI, const MDNode *Variable,
397  const MDNode *Expr);
398 
399  /// Build and insert a DBG_VALUE instructions specifying that \p Variable is
400  /// given by \p C (suitably modified by \p Expr).
402  const MDNode *Variable,
403  const MDNode *Expr);
404 
405  /// Build and insert a DBG_LABEL instructions specifying that \p Label is
406  /// given. Convert "llvm.dbg.label Label" to "DBG_LABEL Label".
408 
409  /// Build and insert \p Res = G_DYN_STACKALLOC \p Size, \p Align
410  ///
411  /// G_DYN_STACKALLOC does a dynamic stack allocation and writes the address of
412  /// the allocated memory into \p Res.
413  /// \pre setBasicBlock or setMI must have been called.
414  /// \pre \p Res must be a generic virtual register with pointer type.
415  ///
416  /// \return a MachineInstrBuilder for the newly created instruction.
418  Align Alignment);
419 
420  /// Build and insert \p Res = G_FRAME_INDEX \p Idx
421  ///
422  /// G_FRAME_INDEX materializes the address of an alloca value or other
423  /// stack-based object.
424  ///
425  /// \pre setBasicBlock or setMI must have been called.
426  /// \pre \p Res must be a generic virtual register with pointer type.
427  ///
428  /// \return a MachineInstrBuilder for the newly created instruction.
429  MachineInstrBuilder buildFrameIndex(const DstOp &Res, int Idx);
430 
431  /// Build and insert \p Res = G_GLOBAL_VALUE \p GV
432  ///
433  /// G_GLOBAL_VALUE materializes the address of the specified global
434  /// into \p Res.
435  ///
436  /// \pre setBasicBlock or setMI must have been called.
437  /// \pre \p Res must be a generic virtual register with pointer type
438  /// in the same address space as \p GV.
439  ///
440  /// \return a MachineInstrBuilder for the newly created instruction.
441  MachineInstrBuilder buildGlobalValue(const DstOp &Res, const GlobalValue *GV);
442 
443  /// Build and insert \p Res = G_PTR_ADD \p Op0, \p Op1
444  ///
445  /// G_PTR_ADD adds \p Op1 addressible units to the pointer specified by \p Op0,
446  /// storing the resulting pointer in \p Res. Addressible units are typically
447  /// bytes but this can vary between targets.
448  ///
449  /// \pre setBasicBlock or setMI must have been called.
450  /// \pre \p Res and \p Op0 must be generic virtual registers with pointer
451  /// type.
452  /// \pre \p Op1 must be a generic virtual register with scalar type.
453  ///
454  /// \return a MachineInstrBuilder for the newly created instruction.
455  MachineInstrBuilder buildPtrAdd(const DstOp &Res, const SrcOp &Op0,
456  const SrcOp &Op1);
457 
458  /// Materialize and insert \p Res = G_PTR_ADD \p Op0, (G_CONSTANT \p Value)
459  ///
460  /// G_PTR_ADD adds \p Value bytes to the pointer specified by \p Op0,
461  /// storing the resulting pointer in \p Res. If \p Value is zero then no
462  /// G_PTR_ADD or G_CONSTANT will be created and \pre Op0 will be assigned to
463  /// \p Res.
464  ///
465  /// \pre setBasicBlock or setMI must have been called.
466  /// \pre \p Op0 must be a generic virtual register with pointer type.
467  /// \pre \p ValueTy must be a scalar type.
468  /// \pre \p Res must be 0. This is to detect confusion between
469  /// materializePtrAdd() and buildPtrAdd().
470  /// \post \p Res will either be a new generic virtual register of the same
471  /// type as \p Op0 or \p Op0 itself.
472  ///
473  /// \return a MachineInstrBuilder for the newly created instruction.
475  const LLT ValueTy,
476  uint64_t Value);
477 
478  /// Build and insert \p Res = G_PTRMASK \p Op0, \p Op1
479  MachineInstrBuilder buildPtrMask(const DstOp &Res, const SrcOp &Op0,
480  const SrcOp &Op1) {
481  return buildInstr(TargetOpcode::G_PTRMASK, {Res}, {Op0, Op1});
482  }
483 
484  /// Build and insert \p Res = G_PTRMASK \p Op0, \p G_CONSTANT (1 << NumBits) - 1
485  ///
486  /// This clears the low bits of a pointer operand without destroying its
487  /// pointer properties. This has the effect of rounding the address *down* to
488  /// a specified alignment in bits.
489  ///
490  /// \pre setBasicBlock or setMI must have been called.
491  /// \pre \p Res and \p Op0 must be generic virtual registers with pointer
492  /// type.
493  /// \pre \p NumBits must be an integer representing the number of low bits to
494  /// be cleared in \p Op0.
495  ///
496  /// \return a MachineInstrBuilder for the newly created instruction.
497  MachineInstrBuilder buildMaskLowPtrBits(const DstOp &Res, const SrcOp &Op0,
498  uint32_t NumBits);
499 
500  /// Build and insert \p Res, \p CarryOut = G_UADDO \p Op0, \p Op1
501  ///
502  /// G_UADDO sets \p Res to \p Op0 + \p Op1 (truncated to the bit width) and
503  /// sets \p CarryOut to 1 if the result overflowed in unsigned arithmetic.
504  ///
505  /// \pre setBasicBlock or setMI must have been called.
506  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers with the
507  /// same scalar type.
508  ////\pre \p CarryOut must be generic virtual register with scalar type
509  ///(typically s1)
510  ///
511  /// \return The newly created instruction.
512  MachineInstrBuilder buildUAddo(const DstOp &Res, const DstOp &CarryOut,
513  const SrcOp &Op0, const SrcOp &Op1) {
514  return buildInstr(TargetOpcode::G_UADDO, {Res, CarryOut}, {Op0, Op1});
515  }
516 
517  /// Build and insert \p Res, \p CarryOut = G_USUBO \p Op0, \p Op1
518  MachineInstrBuilder buildUSubo(const DstOp &Res, const DstOp &CarryOut,
519  const SrcOp &Op0, const SrcOp &Op1) {
520  return buildInstr(TargetOpcode::G_USUBO, {Res, CarryOut}, {Op0, Op1});
521  }
522 
523  /// Build and insert \p Res, \p CarryOut = G_SADDO \p Op0, \p Op1
524  MachineInstrBuilder buildSAddo(const DstOp &Res, const DstOp &CarryOut,
525  const SrcOp &Op0, const SrcOp &Op1) {
526  return buildInstr(TargetOpcode::G_SADDO, {Res, CarryOut}, {Op0, Op1});
527  }
528 
529  /// Build and insert \p Res, \p CarryOut = G_SUBO \p Op0, \p Op1
530  MachineInstrBuilder buildSSubo(const DstOp &Res, const DstOp &CarryOut,
531  const SrcOp &Op0, const SrcOp &Op1) {
532  return buildInstr(TargetOpcode::G_SSUBO, {Res, CarryOut}, {Op0, Op1});
533  }
534 
535  /// Build and insert \p Res, \p CarryOut = G_UADDE \p Op0,
536  /// \p Op1, \p CarryIn
537  ///
538  /// G_UADDE sets \p Res to \p Op0 + \p Op1 + \p CarryIn (truncated to the bit
539  /// width) and sets \p CarryOut to 1 if the result overflowed in unsigned
540  /// arithmetic.
541  ///
542  /// \pre setBasicBlock or setMI must have been called.
543  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
544  /// with the same scalar type.
545  /// \pre \p CarryOut and \p CarryIn must be generic virtual
546  /// registers with the same scalar type (typically s1)
547  ///
548  /// \return The newly created instruction.
549  MachineInstrBuilder buildUAdde(const DstOp &Res, const DstOp &CarryOut,
550  const SrcOp &Op0, const SrcOp &Op1,
551  const SrcOp &CarryIn) {
552  return buildInstr(TargetOpcode::G_UADDE, {Res, CarryOut},
553  {Op0, Op1, CarryIn});
554  }
555 
556  /// Build and insert \p Res, \p CarryOut = G_USUBE \p Op0, \p Op1, \p CarryInp
557  MachineInstrBuilder buildUSube(const DstOp &Res, const DstOp &CarryOut,
558  const SrcOp &Op0, const SrcOp &Op1,
559  const SrcOp &CarryIn) {
560  return buildInstr(TargetOpcode::G_USUBE, {Res, CarryOut},
561  {Op0, Op1, CarryIn});
562  }
563 
564  /// Build and insert \p Res, \p CarryOut = G_SADDE \p Op0, \p Op1, \p CarryInp
565  MachineInstrBuilder buildSAdde(const DstOp &Res, const DstOp &CarryOut,
566  const SrcOp &Op0, const SrcOp &Op1,
567  const SrcOp &CarryIn) {
568  return buildInstr(TargetOpcode::G_SADDE, {Res, CarryOut},
569  {Op0, Op1, CarryIn});
570  }
571 
572  /// Build and insert \p Res, \p CarryOut = G_SSUBE \p Op0, \p Op1, \p CarryInp
573  MachineInstrBuilder buildSSube(const DstOp &Res, const DstOp &CarryOut,
574  const SrcOp &Op0, const SrcOp &Op1,
575  const SrcOp &CarryIn) {
576  return buildInstr(TargetOpcode::G_SSUBE, {Res, CarryOut},
577  {Op0, Op1, CarryIn});
578  }
579 
580  /// Build and insert \p Res = G_ANYEXT \p Op0
581  ///
582  /// G_ANYEXT produces a register of the specified width, with bits 0 to
583  /// sizeof(\p Ty) * 8 set to \p Op. The remaining bits are unspecified
584  /// (i.e. this is neither zero nor sign-extension). For a vector register,
585  /// each element is extended individually.
586  ///
587  /// \pre setBasicBlock or setMI must have been called.
588  /// \pre \p Res must be a generic virtual register with scalar or vector type.
589  /// \pre \p Op must be a generic virtual register with scalar or vector type.
590  /// \pre \p Op must be smaller than \p Res
591  ///
592  /// \return The newly created instruction.
593 
594  MachineInstrBuilder buildAnyExt(const DstOp &Res, const SrcOp &Op);
595 
596  /// Build and insert \p Res = G_SEXT \p Op
597  ///
598  /// G_SEXT produces a register of the specified width, with bits 0 to
599  /// sizeof(\p Ty) * 8 set to \p Op. The remaining bits are duplicated from the
600  /// high bit of \p Op (i.e. 2s-complement sign extended).
601  ///
602  /// \pre setBasicBlock or setMI must have been called.
603  /// \pre \p Res must be a generic virtual register with scalar or vector type.
604  /// \pre \p Op must be a generic virtual register with scalar or vector type.
605  /// \pre \p Op must be smaller than \p Res
606  ///
607  /// \return The newly created instruction.
608  MachineInstrBuilder buildSExt(const DstOp &Res, const SrcOp &Op);
609 
610  /// Build and insert \p Res = G_SEXT_INREG \p Op, ImmOp
611  MachineInstrBuilder buildSExtInReg(const DstOp &Res, const SrcOp &Op, int64_t ImmOp) {
612  return buildInstr(TargetOpcode::G_SEXT_INREG, {Res}, {Op, SrcOp(ImmOp)});
613  }
614 
615  /// Build and insert \p Res = G_FPEXT \p Op
617  Optional<unsigned> Flags = None) {
618  return buildInstr(TargetOpcode::G_FPEXT, {Res}, {Op}, Flags);
619  }
620 
621 
622  /// Build and insert a G_PTRTOINT instruction.
623  MachineInstrBuilder buildPtrToInt(const DstOp &Dst, const SrcOp &Src) {
624  return buildInstr(TargetOpcode::G_PTRTOINT, {Dst}, {Src});
625  }
626 
627  /// Build and insert a G_INTTOPTR instruction.
628  MachineInstrBuilder buildIntToPtr(const DstOp &Dst, const SrcOp &Src) {
629  return buildInstr(TargetOpcode::G_INTTOPTR, {Dst}, {Src});
630  }
631 
632  /// Build and insert \p Dst = G_BITCAST \p Src
633  MachineInstrBuilder buildBitcast(const DstOp &Dst, const SrcOp &Src) {
634  return buildInstr(TargetOpcode::G_BITCAST, {Dst}, {Src});
635  }
636 
637  /// Build and insert \p Dst = G_ADDRSPACE_CAST \p Src
639  return buildInstr(TargetOpcode::G_ADDRSPACE_CAST, {Dst}, {Src});
640  }
641 
642  /// \return The opcode of the extension the target wants to use for boolean
643  /// values.
644  unsigned getBoolExtOp(bool IsVec, bool IsFP) const;
645 
646  // Build and insert \p Res = G_ANYEXT \p Op, \p Res = G_SEXT \p Op, or \p Res
647  // = G_ZEXT \p Op depending on how the target wants to extend boolean values.
648  MachineInstrBuilder buildBoolExt(const DstOp &Res, const SrcOp &Op,
649  bool IsFP);
650 
651  /// Build and insert \p Res = G_ZEXT \p Op
652  ///
653  /// G_ZEXT produces a register of the specified width, with bits 0 to
654  /// sizeof(\p Ty) * 8 set to \p Op. The remaining bits are 0. For a vector
655  /// register, each element is extended individually.
656  ///
657  /// \pre setBasicBlock or setMI must have been called.
658  /// \pre \p Res must be a generic virtual register with scalar or vector type.
659  /// \pre \p Op must be a generic virtual register with scalar or vector type.
660  /// \pre \p Op must be smaller than \p Res
661  ///
662  /// \return The newly created instruction.
663  MachineInstrBuilder buildZExt(const DstOp &Res, const SrcOp &Op);
664 
665  /// Build and insert \p Res = G_SEXT \p Op, \p Res = G_TRUNC \p Op, or
666  /// \p Res = COPY \p Op depending on the differing sizes of \p Res and \p Op.
667  /// ///
668  /// \pre setBasicBlock or setMI must have been called.
669  /// \pre \p Res must be a generic virtual register with scalar or vector type.
670  /// \pre \p Op must be a generic virtual register with scalar or vector type.
671  ///
672  /// \return The newly created instruction.
673  MachineInstrBuilder buildSExtOrTrunc(const DstOp &Res, const SrcOp &Op);
674 
675  /// Build and insert \p Res = G_ZEXT \p Op, \p Res = G_TRUNC \p Op, or
676  /// \p Res = COPY \p Op depending on the differing sizes of \p Res and \p Op.
677  /// ///
678  /// \pre setBasicBlock or setMI must have been called.
679  /// \pre \p Res must be a generic virtual register with scalar or vector type.
680  /// \pre \p Op must be a generic virtual register with scalar or vector type.
681  ///
682  /// \return The newly created instruction.
683  MachineInstrBuilder buildZExtOrTrunc(const DstOp &Res, const SrcOp &Op);
684 
685  // Build and insert \p Res = G_ANYEXT \p Op, \p Res = G_TRUNC \p Op, or
686  /// \p Res = COPY \p Op depending on the differing sizes of \p Res and \p Op.
687  /// ///
688  /// \pre setBasicBlock or setMI must have been called.
689  /// \pre \p Res must be a generic virtual register with scalar or vector type.
690  /// \pre \p Op must be a generic virtual register with scalar or vector type.
691  ///
692  /// \return The newly created instruction.
694 
695  /// Build and insert \p Res = \p ExtOpc, \p Res = G_TRUNC \p
696  /// Op, or \p Res = COPY \p Op depending on the differing sizes of \p Res and
697  /// \p Op.
698  /// ///
699  /// \pre setBasicBlock or setMI must have been called.
700  /// \pre \p Res must be a generic virtual register with scalar or vector type.
701  /// \pre \p Op must be a generic virtual register with scalar or vector type.
702  ///
703  /// \return The newly created instruction.
704  MachineInstrBuilder buildExtOrTrunc(unsigned ExtOpc, const DstOp &Res,
705  const SrcOp &Op);
706 
707  /// Build and inserts \p Res = \p G_AND \p Op, \p LowBitsSet(ImmOp)
708  /// Since there is no G_ZEXT_INREG like G_SEXT_INREG, the instruction is
709  /// emulated using G_AND.
710  MachineInstrBuilder buildZExtInReg(const DstOp &Res, const SrcOp &Op,
711  int64_t ImmOp);
712 
713  /// Build and insert an appropriate cast between two registers of equal size.
714  MachineInstrBuilder buildCast(const DstOp &Dst, const SrcOp &Src);
715 
716  /// Build and insert G_BR \p Dest
717  ///
718  /// G_BR is an unconditional branch to \p Dest.
719  ///
720  /// \pre setBasicBlock or setMI must have been called.
721  ///
722  /// \return a MachineInstrBuilder for the newly created instruction.
724 
725  /// Build and insert G_BRCOND \p Tst, \p Dest
726  ///
727  /// G_BRCOND is a conditional branch to \p Dest.
728  ///
729  /// \pre setBasicBlock or setMI must have been called.
730  /// \pre \p Tst must be a generic virtual register with scalar
731  /// type. At the beginning of legalization, this will be a single
732  /// bit (s1). Targets with interesting flags registers may change
733  /// this. For a wider type, whether the branch is taken must only
734  /// depend on bit 0 (for now).
735  ///
736  /// \return The newly created instruction.
738 
739  /// Build and insert G_BRINDIRECT \p Tgt
740  ///
741  /// G_BRINDIRECT is an indirect branch to \p Tgt.
742  ///
743  /// \pre setBasicBlock or setMI must have been called.
744  /// \pre \p Tgt must be a generic virtual register with pointer type.
745  ///
746  /// \return a MachineInstrBuilder for the newly created instruction.
748 
749  /// Build and insert G_BRJT \p TablePtr, \p JTI, \p IndexReg
750  ///
751  /// G_BRJT is a jump table branch using a table base pointer \p TablePtr,
752  /// jump table index \p JTI and index \p IndexReg
753  ///
754  /// \pre setBasicBlock or setMI must have been called.
755  /// \pre \p TablePtr must be a generic virtual register with pointer type.
756  /// \pre \p JTI must be be a jump table index.
757  /// \pre \p IndexReg must be a generic virtual register with pointer type.
758  ///
759  /// \return a MachineInstrBuilder for the newly created instruction.
760  MachineInstrBuilder buildBrJT(Register TablePtr, unsigned JTI,
761  Register IndexReg);
762 
763  /// Build and insert \p Res = G_CONSTANT \p Val
764  ///
765  /// G_CONSTANT is an integer constant with the specified size and value. \p
766  /// Val will be extended or truncated to the size of \p Reg.
767  ///
768  /// \pre setBasicBlock or setMI must have been called.
769  /// \pre \p Res must be a generic virtual register with scalar or pointer
770  /// type.
771  ///
772  /// \return The newly created instruction.
773  virtual MachineInstrBuilder buildConstant(const DstOp &Res,
774  const ConstantInt &Val);
775 
776  /// Build and insert \p Res = G_CONSTANT \p Val
777  ///
778  /// G_CONSTANT is an integer constant with the specified size and value.
779  ///
780  /// \pre setBasicBlock or setMI must have been called.
781  /// \pre \p Res must be a generic virtual register with scalar type.
782  ///
783  /// \return The newly created instruction.
784  MachineInstrBuilder buildConstant(const DstOp &Res, int64_t Val);
785  MachineInstrBuilder buildConstant(const DstOp &Res, const APInt &Val);
786 
787  /// Build and insert \p Res = G_FCONSTANT \p Val
788  ///
789  /// G_FCONSTANT is a floating-point constant with the specified size and
790  /// value.
791  ///
792  /// \pre setBasicBlock or setMI must have been called.
793  /// \pre \p Res must be a generic virtual register with scalar type.
794  ///
795  /// \return The newly created instruction.
796  virtual MachineInstrBuilder buildFConstant(const DstOp &Res,
797  const ConstantFP &Val);
798 
799  MachineInstrBuilder buildFConstant(const DstOp &Res, double Val);
800  MachineInstrBuilder buildFConstant(const DstOp &Res, const APFloat &Val);
801 
802  /// Build and insert \p Res = COPY Op
803  ///
804  /// Register-to-register COPY sets \p Res to \p Op.
805  ///
806  /// \pre setBasicBlock or setMI must have been called.
807  ///
808  /// \return a MachineInstrBuilder for the newly created instruction.
809  MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op);
810 
811  /// Build and insert \p Res = G_ASSERT_ZEXT Op, Size
812  ///
813  /// \return a MachineInstrBuilder for the newly created instruction.
814  MachineInstrBuilder buildAssertZExt(const DstOp &Res, const SrcOp &Op,
815  unsigned Size);
816 
817  /// Build and insert \p Res = G_ASSERT_SEXT Op, Size
818  ///
819  /// \return a MachineInstrBuilder for the newly created instruction.
820  MachineInstrBuilder buildAssertSExt(const DstOp &Res, const SrcOp &Op,
821  unsigned Size);
822 
823  /// Build and insert `Res = G_LOAD Addr, MMO`.
824  ///
825  /// Loads the value stored at \p Addr. Puts the result in \p Res.
826  ///
827  /// \pre setBasicBlock or setMI must have been called.
828  /// \pre \p Res must be a generic virtual register.
829  /// \pre \p Addr must be a generic virtual register with pointer type.
830  ///
831  /// \return a MachineInstrBuilder for the newly created instruction.
833  MachineMemOperand &MMO) {
834  return buildLoadInstr(TargetOpcode::G_LOAD, Res, Addr, MMO);
835  }
836 
837  /// Build and insert a G_LOAD instruction, while constructing the
838  /// MachineMemOperand.
840  buildLoad(const DstOp &Res, const SrcOp &Addr, MachinePointerInfo PtrInfo,
841  Align Alignment,
843  const AAMDNodes &AAInfo = AAMDNodes());
844 
845  /// Build and insert `Res = <opcode> Addr, MMO`.
846  ///
847  /// Loads the value stored at \p Addr. Puts the result in \p Res.
848  ///
849  /// \pre setBasicBlock or setMI must have been called.
850  /// \pre \p Res must be a generic virtual register.
851  /// \pre \p Addr must be a generic virtual register with pointer type.
852  ///
853  /// \return a MachineInstrBuilder for the newly created instruction.
854  MachineInstrBuilder buildLoadInstr(unsigned Opcode, const DstOp &Res,
855  const SrcOp &Addr, MachineMemOperand &MMO);
856 
857  /// Helper to create a load from a constant offset given a base address. Load
858  /// the type of \p Dst from \p Offset from the given base address and memory
859  /// operand.
861  const SrcOp &BasePtr,
862  MachineMemOperand &BaseMMO,
863  int64_t Offset);
864 
865  /// Build and insert `G_STORE Val, Addr, MMO`.
866  ///
867  /// Stores the value \p Val to \p Addr.
868  ///
869  /// \pre setBasicBlock or setMI must have been called.
870  /// \pre \p Val must be a generic virtual register.
871  /// \pre \p Addr must be a generic virtual register with pointer type.
872  ///
873  /// \return a MachineInstrBuilder for the newly created instruction.
874  MachineInstrBuilder buildStore(const SrcOp &Val, const SrcOp &Addr,
875  MachineMemOperand &MMO);
876 
877  /// Build and insert a G_STORE instruction, while constructing the
878  /// MachineMemOperand.
880  buildStore(const SrcOp &Val, const SrcOp &Addr, MachinePointerInfo PtrInfo,
881  Align Alignment,
883  const AAMDNodes &AAInfo = AAMDNodes());
884 
885  /// Build and insert `Res0, ... = G_EXTRACT Src, Idx0`.
886  ///
887  /// \pre setBasicBlock or setMI must have been called.
888  /// \pre \p Res and \p Src must be generic virtual registers.
889  ///
890  /// \return a MachineInstrBuilder for the newly created instruction.
891  MachineInstrBuilder buildExtract(const DstOp &Res, const SrcOp &Src, uint64_t Index);
892 
893  /// Build and insert \p Res = IMPLICIT_DEF.
895 
896  /// Build and insert instructions to put \p Ops together at the specified p
897  /// Indices to form a larger register.
898  ///
899  /// If the types of the input registers are uniform and cover the entirity of
900  /// \p Res then a G_MERGE_VALUES will be produced. Otherwise an IMPLICIT_DEF
901  /// followed by a sequence of G_INSERT instructions.
902  ///
903  /// \pre setBasicBlock or setMI must have been called.
904  /// \pre The final element of the sequence must not extend past the end of the
905  /// destination register.
906  /// \pre The bits defined by each Op (derived from index and scalar size) must
907  /// not overlap.
908  /// \pre \p Indices must be in ascending order of bit position.
910  ArrayRef<uint64_t> Indices);
911 
912  /// Build and insert \p Res = G_MERGE_VALUES \p Op0, ...
913  ///
914  /// G_MERGE_VALUES combines the input elements contiguously into a larger
915  /// register.
916  ///
917  /// \pre setBasicBlock or setMI must have been called.
918  /// \pre The entire register \p Res (and no more) must be covered by the input
919  /// registers.
920  /// \pre The type of all \p Ops registers must be identical.
921  ///
922  /// \return a MachineInstrBuilder for the newly created instruction.
925  std::initializer_list<SrcOp> Ops);
926 
927  /// Build and insert \p Res0, ... = G_UNMERGE_VALUES \p Op
928  ///
929  /// G_UNMERGE_VALUES splits contiguous bits of the input into multiple
930  ///
931  /// \pre setBasicBlock or setMI must have been called.
932  /// \pre The entire register \p Res (and no more) must be covered by the input
933  /// registers.
934  /// \pre The type of all \p Res registers must be identical.
935  ///
936  /// \return a MachineInstrBuilder for the newly created instruction.
939 
940  /// Build and insert an unmerge of \p Res sized pieces to cover \p Op
942 
943  /// Build and insert \p Res = G_BUILD_VECTOR \p Op0, ...
944  ///
945  /// G_BUILD_VECTOR creates a vector value from multiple scalar registers.
946  /// \pre setBasicBlock or setMI must have been called.
947  /// \pre The entire register \p Res (and no more) must be covered by the
948  /// input scalar registers.
949  /// \pre The type of all \p Ops registers must be identical.
950  ///
951  /// \return a MachineInstrBuilder for the newly created instruction.
953  ArrayRef<Register> Ops);
954 
955  /// Build and insert \p Res = G_BUILD_VECTOR with \p Src replicated to fill
956  /// the number of elements
958  const SrcOp &Src);
959 
960  /// Build and insert \p Res = G_BUILD_VECTOR_TRUNC \p Op0, ...
961  ///
962  /// G_BUILD_VECTOR_TRUNC creates a vector value from multiple scalar registers
963  /// which have types larger than the destination vector element type, and
964  /// truncates the values to fit.
965  ///
966  /// If the operands given are already the same size as the vector elt type,
967  /// then this method will instead create a G_BUILD_VECTOR instruction.
968  ///
969  /// \pre setBasicBlock or setMI must have been called.
970  /// \pre The type of all \p Ops registers must be identical.
971  ///
972  /// \return a MachineInstrBuilder for the newly created instruction.
974  ArrayRef<Register> Ops);
975 
976  /// Build and insert a vector splat of a scalar \p Src using a
977  /// G_INSERT_VECTOR_ELT and G_SHUFFLE_VECTOR idiom.
978  ///
979  /// \pre setBasicBlock or setMI must have been called.
980  /// \pre \p Src must have the same type as the element type of \p Dst
981  ///
982  /// \return a MachineInstrBuilder for the newly created instruction.
983  MachineInstrBuilder buildShuffleSplat(const DstOp &Res, const SrcOp &Src);
984 
985  /// Build and insert \p Res = G_SHUFFLE_VECTOR \p Src1, \p Src2, \p Mask
986  ///
987  /// \pre setBasicBlock or setMI must have been called.
988  ///
989  /// \return a MachineInstrBuilder for the newly created instruction.
990  MachineInstrBuilder buildShuffleVector(const DstOp &Res, const SrcOp &Src1,
991  const SrcOp &Src2, ArrayRef<int> Mask);
992 
993  /// Build and insert \p Res = G_CONCAT_VECTORS \p Op0, ...
994  ///
995  /// G_CONCAT_VECTORS creates a vector from the concatenation of 2 or more
996  /// vectors.
997  ///
998  /// \pre setBasicBlock or setMI must have been called.
999  /// \pre The entire register \p Res (and no more) must be covered by the input
1000  /// registers.
1001  /// \pre The type of all source operands must be identical.
1002  ///
1003  /// \return a MachineInstrBuilder for the newly created instruction.
1005  ArrayRef<Register> Ops);
1006 
1007  MachineInstrBuilder buildInsert(const DstOp &Res, const SrcOp &Src,
1008  const SrcOp &Op, unsigned Index);
1009 
1010  /// Build and insert either a G_INTRINSIC (if \p HasSideEffects is false) or
1011  /// G_INTRINSIC_W_SIDE_EFFECTS instruction. Its first operand will be the
1012  /// result register definition unless \p Reg is NoReg (== 0). The second
1013  /// operand will be the intrinsic's ID.
1014  ///
1015  /// Callers are expected to add the required definitions and uses afterwards.
1016  ///
1017  /// \pre setBasicBlock or setMI must have been called.
1018  ///
1019  /// \return a MachineInstrBuilder for the newly created instruction.
1021  bool HasSideEffects);
1023  bool HasSideEffects);
1024 
1025  /// Build and insert \p Res = G_FPTRUNC \p Op
1026  ///
1027  /// G_FPTRUNC converts a floating-point value into one with a smaller type.
1028  ///
1029  /// \pre setBasicBlock or setMI must have been called.
1030  /// \pre \p Res must be a generic virtual register with scalar or vector type.
1031  /// \pre \p Op must be a generic virtual register with scalar or vector type.
1032  /// \pre \p Res must be smaller than \p Op
1033  ///
1034  /// \return The newly created instruction.
1035  MachineInstrBuilder buildFPTrunc(const DstOp &Res, const SrcOp &Op,
1036  Optional<unsigned> Flags = None);
1037 
1038  /// Build and insert \p Res = G_TRUNC \p Op
1039  ///
1040  /// G_TRUNC extracts the low bits of a type. For a vector type each element is
1041  /// truncated independently before being packed into the destination.
1042  ///
1043  /// \pre setBasicBlock or setMI must have been called.
1044  /// \pre \p Res must be a generic virtual register with scalar or vector type.
1045  /// \pre \p Op must be a generic virtual register with scalar or vector type.
1046  /// \pre \p Res must be smaller than \p Op
1047  ///
1048  /// \return The newly created instruction.
1049  MachineInstrBuilder buildTrunc(const DstOp &Res, const SrcOp &Op);
1050 
1051  /// Build and insert a \p Res = G_ICMP \p Pred, \p Op0, \p Op1
1052  ///
1053  /// \pre setBasicBlock or setMI must have been called.
1054 
1055  /// \pre \p Res must be a generic virtual register with scalar or
1056  /// vector type. Typically this starts as s1 or <N x s1>.
1057  /// \pre \p Op0 and Op1 must be generic virtual registers with the
1058  /// same number of elements as \p Res. If \p Res is a scalar,
1059  /// \p Op0 must be either a scalar or pointer.
1060  /// \pre \p Pred must be an integer predicate.
1061  ///
1062  /// \return a MachineInstrBuilder for the newly created instruction.
1064  const SrcOp &Op0, const SrcOp &Op1);
1065 
1066  /// Build and insert a \p Res = G_FCMP \p Pred\p Op0, \p Op1
1067  ///
1068  /// \pre setBasicBlock or setMI must have been called.
1069 
1070  /// \pre \p Res must be a generic virtual register with scalar or
1071  /// vector type. Typically this starts as s1 or <N x s1>.
1072  /// \pre \p Op0 and Op1 must be generic virtual registers with the
1073  /// same number of elements as \p Res (or scalar, if \p Res is
1074  /// scalar).
1075  /// \pre \p Pred must be a floating-point predicate.
1076  ///
1077  /// \return a MachineInstrBuilder for the newly created instruction.
1079  const SrcOp &Op0, const SrcOp &Op1,
1080  Optional<unsigned> Flags = None);
1081 
1082  /// Build and insert a \p Res = G_SELECT \p Tst, \p Op0, \p Op1
1083  ///
1084  /// \pre setBasicBlock or setMI must have been called.
1085  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1086  /// with the same type.
1087  /// \pre \p Tst must be a generic virtual register with scalar, pointer or
1088  /// vector type. If vector then it must have the same number of
1089  /// elements as the other parameters.
1090  ///
1091  /// \return a MachineInstrBuilder for the newly created instruction.
1092  MachineInstrBuilder buildSelect(const DstOp &Res, const SrcOp &Tst,
1093  const SrcOp &Op0, const SrcOp &Op1,
1094  Optional<unsigned> Flags = None);
1095 
1096  /// Build and insert \p Res = G_INSERT_VECTOR_ELT \p Val,
1097  /// \p Elt, \p Idx
1098  ///
1099  /// \pre setBasicBlock or setMI must have been called.
1100  /// \pre \p Res and \p Val must be a generic virtual register
1101  // with the same vector type.
1102  /// \pre \p Elt and \p Idx must be a generic virtual register
1103  /// with scalar type.
1104  ///
1105  /// \return The newly created instruction.
1107  const SrcOp &Val,
1108  const SrcOp &Elt,
1109  const SrcOp &Idx);
1110 
1111  /// Build and insert \p Res = G_EXTRACT_VECTOR_ELT \p Val, \p Idx
1112  ///
1113  /// \pre setBasicBlock or setMI must have been called.
1114  /// \pre \p Res must be a generic virtual register with scalar type.
1115  /// \pre \p Val must be a generic virtual register with vector type.
1116  /// \pre \p Idx must be a generic virtual register with scalar type.
1117  ///
1118  /// \return The newly created instruction.
1120  const SrcOp &Val,
1121  const SrcOp &Idx);
1122 
1123  /// Build and insert `OldValRes<def>, SuccessRes<def> =
1124  /// G_ATOMIC_CMPXCHG_WITH_SUCCESS Addr, CmpVal, NewVal, MMO`.
1125  ///
1126  /// Atomically replace the value at \p Addr with \p NewVal if it is currently
1127  /// \p CmpVal otherwise leaves it unchanged. Puts the original value from \p
1128  /// Addr in \p Res, along with an s1 indicating whether it was replaced.
1129  ///
1130  /// \pre setBasicBlock or setMI must have been called.
1131  /// \pre \p OldValRes must be a generic virtual register of scalar type.
1132  /// \pre \p SuccessRes must be a generic virtual register of scalar type. It
1133  /// will be assigned 0 on failure and 1 on success.
1134  /// \pre \p Addr must be a generic virtual register with pointer type.
1135  /// \pre \p OldValRes, \p CmpVal, and \p NewVal must be generic virtual
1136  /// registers of the same type.
1137  ///
1138  /// \return a MachineInstrBuilder for the newly created instruction.
1140  buildAtomicCmpXchgWithSuccess(Register OldValRes, Register SuccessRes,
1141  Register Addr, Register CmpVal, Register NewVal,
1142  MachineMemOperand &MMO);
1143 
1144  /// Build and insert `OldValRes<def> = G_ATOMIC_CMPXCHG Addr, CmpVal, NewVal,
1145  /// MMO`.
1146  ///
1147  /// Atomically replace the value at \p Addr with \p NewVal if it is currently
1148  /// \p CmpVal otherwise leaves it unchanged. Puts the original value from \p
1149  /// Addr in \p Res.
1150  ///
1151  /// \pre setBasicBlock or setMI must have been called.
1152  /// \pre \p OldValRes must be a generic virtual register of scalar type.
1153  /// \pre \p Addr must be a generic virtual register with pointer type.
1154  /// \pre \p OldValRes, \p CmpVal, and \p NewVal must be generic virtual
1155  /// registers of the same type.
1156  ///
1157  /// \return a MachineInstrBuilder for the newly created instruction.
1159  Register CmpVal, Register NewVal,
1160  MachineMemOperand &MMO);
1161 
1162  /// Build and insert `OldValRes<def> = G_ATOMICRMW_<Opcode> Addr, Val, MMO`.
1163  ///
1164  /// Atomically read-modify-update the value at \p Addr with \p Val. Puts the
1165  /// original value from \p Addr in \p OldValRes. The modification is
1166  /// determined by the opcode.
1167  ///
1168  /// \pre setBasicBlock or setMI must have been called.
1169  /// \pre \p OldValRes must be a generic virtual register.
1170  /// \pre \p Addr must be a generic virtual register with pointer type.
1171  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1172  /// same type.
1173  ///
1174  /// \return a MachineInstrBuilder for the newly created instruction.
1175  MachineInstrBuilder buildAtomicRMW(unsigned Opcode, const DstOp &OldValRes,
1176  const SrcOp &Addr, const SrcOp &Val,
1177  MachineMemOperand &MMO);
1178 
1179  /// Build and insert `OldValRes<def> = G_ATOMICRMW_XCHG Addr, Val, MMO`.
1180  ///
1181  /// Atomically replace the value at \p Addr with \p Val. Puts the original
1182  /// value from \p Addr in \p OldValRes.
1183  ///
1184  /// \pre setBasicBlock or setMI must have been called.
1185  /// \pre \p OldValRes must be a generic virtual register.
1186  /// \pre \p Addr must be a generic virtual register with pointer type.
1187  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1188  /// same type.
1189  ///
1190  /// \return a MachineInstrBuilder for the newly created instruction.
1192  Register Val, MachineMemOperand &MMO);
1193 
1194  /// Build and insert `OldValRes<def> = G_ATOMICRMW_ADD Addr, Val, MMO`.
1195  ///
1196  /// Atomically replace the value at \p Addr with the addition of \p Val and
1197  /// the original value. Puts the original value from \p Addr in \p OldValRes.
1198  ///
1199  /// \pre setBasicBlock or setMI must have been called.
1200  /// \pre \p OldValRes must be a generic virtual register.
1201  /// \pre \p Addr must be a generic virtual register with pointer type.
1202  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1203  /// same type.
1204  ///
1205  /// \return a MachineInstrBuilder for the newly created instruction.
1207  Register Val, MachineMemOperand &MMO);
1208 
1209  /// Build and insert `OldValRes<def> = G_ATOMICRMW_SUB Addr, Val, MMO`.
1210  ///
1211  /// Atomically replace the value at \p Addr with the subtraction of \p Val and
1212  /// the original value. Puts the original value from \p Addr in \p OldValRes.
1213  ///
1214  /// \pre setBasicBlock or setMI must have been called.
1215  /// \pre \p OldValRes must be a generic virtual register.
1216  /// \pre \p Addr must be a generic virtual register with pointer type.
1217  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1218  /// same type.
1219  ///
1220  /// \return a MachineInstrBuilder for the newly created instruction.
1222  Register Val, MachineMemOperand &MMO);
1223 
1224  /// Build and insert `OldValRes<def> = G_ATOMICRMW_AND Addr, Val, MMO`.
1225  ///
1226  /// Atomically replace the value at \p Addr with the bitwise and of \p Val and
1227  /// the original value. Puts the original value from \p Addr in \p OldValRes.
1228  ///
1229  /// \pre setBasicBlock or setMI must have been called.
1230  /// \pre \p OldValRes must be a generic virtual register.
1231  /// \pre \p Addr must be a generic virtual register with pointer type.
1232  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1233  /// same type.
1234  ///
1235  /// \return a MachineInstrBuilder for the newly created instruction.
1237  Register Val, MachineMemOperand &MMO);
1238 
1239  /// Build and insert `OldValRes<def> = G_ATOMICRMW_NAND Addr, Val, MMO`.
1240  ///
1241  /// Atomically replace the value at \p Addr with the bitwise nand of \p Val
1242  /// and the original value. Puts the original value from \p Addr in \p
1243  /// OldValRes.
1244  ///
1245  /// \pre setBasicBlock or setMI must have been called.
1246  /// \pre \p OldValRes must be a generic virtual register.
1247  /// \pre \p Addr must be a generic virtual register with pointer type.
1248  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1249  /// same type.
1250  ///
1251  /// \return a MachineInstrBuilder for the newly created instruction.
1253  Register Val, MachineMemOperand &MMO);
1254 
1255  /// Build and insert `OldValRes<def> = G_ATOMICRMW_OR Addr, Val, MMO`.
1256  ///
1257  /// Atomically replace the value at \p Addr with the bitwise or of \p Val and
1258  /// the original value. Puts the original value from \p Addr in \p OldValRes.
1259  ///
1260  /// \pre setBasicBlock or setMI must have been called.
1261  /// \pre \p OldValRes must be a generic virtual register.
1262  /// \pre \p Addr must be a generic virtual register with pointer type.
1263  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1264  /// same type.
1265  ///
1266  /// \return a MachineInstrBuilder for the newly created instruction.
1268  Register Val, MachineMemOperand &MMO);
1269 
1270  /// Build and insert `OldValRes<def> = G_ATOMICRMW_XOR Addr, Val, MMO`.
1271  ///
1272  /// Atomically replace the value at \p Addr with the bitwise xor of \p Val and
1273  /// the original value. Puts the original value from \p Addr in \p OldValRes.
1274  ///
1275  /// \pre setBasicBlock or setMI must have been called.
1276  /// \pre \p OldValRes must be a generic virtual register.
1277  /// \pre \p Addr must be a generic virtual register with pointer type.
1278  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1279  /// same type.
1280  ///
1281  /// \return a MachineInstrBuilder for the newly created instruction.
1283  Register Val, MachineMemOperand &MMO);
1284 
1285  /// Build and insert `OldValRes<def> = G_ATOMICRMW_MAX Addr, Val, MMO`.
1286  ///
1287  /// Atomically replace the value at \p Addr with the signed maximum of \p
1288  /// Val and the original value. Puts the original value from \p Addr in \p
1289  /// OldValRes.
1290  ///
1291  /// \pre setBasicBlock or setMI must have been called.
1292  /// \pre \p OldValRes must be a generic virtual register.
1293  /// \pre \p Addr must be a generic virtual register with pointer type.
1294  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1295  /// same type.
1296  ///
1297  /// \return a MachineInstrBuilder for the newly created instruction.
1299  Register Val, MachineMemOperand &MMO);
1300 
1301  /// Build and insert `OldValRes<def> = G_ATOMICRMW_MIN Addr, Val, MMO`.
1302  ///
1303  /// Atomically replace the value at \p Addr with the signed minimum of \p
1304  /// Val and the original value. Puts the original value from \p Addr in \p
1305  /// OldValRes.
1306  ///
1307  /// \pre setBasicBlock or setMI must have been called.
1308  /// \pre \p OldValRes must be a generic virtual register.
1309  /// \pre \p Addr must be a generic virtual register with pointer type.
1310  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1311  /// same type.
1312  ///
1313  /// \return a MachineInstrBuilder for the newly created instruction.
1315  Register Val, MachineMemOperand &MMO);
1316 
1317  /// Build and insert `OldValRes<def> = G_ATOMICRMW_UMAX Addr, Val, MMO`.
1318  ///
1319  /// Atomically replace the value at \p Addr with the unsigned maximum of \p
1320  /// Val and the original value. Puts the original value from \p Addr in \p
1321  /// OldValRes.
1322  ///
1323  /// \pre setBasicBlock or setMI must have been called.
1324  /// \pre \p OldValRes must be a generic virtual register.
1325  /// \pre \p Addr must be a generic virtual register with pointer type.
1326  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1327  /// same type.
1328  ///
1329  /// \return a MachineInstrBuilder for the newly created instruction.
1331  Register Val, MachineMemOperand &MMO);
1332 
1333  /// Build and insert `OldValRes<def> = G_ATOMICRMW_UMIN Addr, Val, MMO`.
1334  ///
1335  /// Atomically replace the value at \p Addr with the unsigned minimum of \p
1336  /// Val and the original value. Puts the original value from \p Addr in \p
1337  /// OldValRes.
1338  ///
1339  /// \pre setBasicBlock or setMI must have been called.
1340  /// \pre \p OldValRes must be a generic virtual register.
1341  /// \pre \p Addr must be a generic virtual register with pointer type.
1342  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1343  /// same type.
1344  ///
1345  /// \return a MachineInstrBuilder for the newly created instruction.
1347  Register Val, MachineMemOperand &MMO);
1348 
1349  /// Build and insert `OldValRes<def> = G_ATOMICRMW_FADD Addr, Val, MMO`.
1351  const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val,
1352  MachineMemOperand &MMO);
1353 
1354  /// Build and insert `OldValRes<def> = G_ATOMICRMW_FSUB Addr, Val, MMO`.
1356  const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val,
1357  MachineMemOperand &MMO);
1358 
1359  /// Build and insert `G_FENCE Ordering, Scope`.
1360  MachineInstrBuilder buildFence(unsigned Ordering, unsigned Scope);
1361 
1362  /// Build and insert \p Dst = G_FREEZE \p Src
1363  MachineInstrBuilder buildFreeze(const DstOp &Dst, const SrcOp &Src) {
1364  return buildInstr(TargetOpcode::G_FREEZE, {Dst}, {Src});
1365  }
1366 
1367  /// Build and insert \p Res = G_BLOCK_ADDR \p BA
1368  ///
1369  /// G_BLOCK_ADDR computes the address of a basic block.
1370  ///
1371  /// \pre setBasicBlock or setMI must have been called.
1372  /// \pre \p Res must be a generic virtual register of a pointer type.
1373  ///
1374  /// \return The newly created instruction.
1376 
1377  /// Build and insert \p Res = G_ADD \p Op0, \p Op1
1378  ///
1379  /// G_ADD sets \p Res to the sum of integer parameters \p Op0 and \p Op1,
1380  /// truncated to their width.
1381  ///
1382  /// \pre setBasicBlock or setMI must have been called.
1383  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1384  /// with the same (scalar or vector) type).
1385  ///
1386  /// \return a MachineInstrBuilder for the newly created instruction.
1387 
1388  MachineInstrBuilder buildAdd(const DstOp &Dst, const SrcOp &Src0,
1389  const SrcOp &Src1,
1390  Optional<unsigned> Flags = None) {
1391  return buildInstr(TargetOpcode::G_ADD, {Dst}, {Src0, Src1}, Flags);
1392  }
1393 
1394  /// Build and insert \p Res = G_SUB \p Op0, \p Op1
1395  ///
1396  /// G_SUB sets \p Res to the sum of integer parameters \p Op0 and \p Op1,
1397  /// truncated to their width.
1398  ///
1399  /// \pre setBasicBlock or setMI must have been called.
1400  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1401  /// with the same (scalar or vector) type).
1402  ///
1403  /// \return a MachineInstrBuilder for the newly created instruction.
1404 
1405  MachineInstrBuilder buildSub(const DstOp &Dst, const SrcOp &Src0,
1406  const SrcOp &Src1,
1407  Optional<unsigned> Flags = None) {
1408  return buildInstr(TargetOpcode::G_SUB, {Dst}, {Src0, Src1}, Flags);
1409  }
1410 
1411  /// Build and insert \p Res = G_MUL \p Op0, \p Op1
1412  ///
1413  /// G_MUL sets \p Res to the sum of integer parameters \p Op0 and \p Op1,
1414  /// truncated to their width.
1415  ///
1416  /// \pre setBasicBlock or setMI must have been called.
1417  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1418  /// with the same (scalar or vector) type).
1419  ///
1420  /// \return a MachineInstrBuilder for the newly created instruction.
1421  MachineInstrBuilder buildMul(const DstOp &Dst, const SrcOp &Src0,
1422  const SrcOp &Src1,
1423  Optional<unsigned> Flags = None) {
1424  return buildInstr(TargetOpcode::G_MUL, {Dst}, {Src0, Src1}, Flags);
1425  }
1426 
1427  MachineInstrBuilder buildUMulH(const DstOp &Dst, const SrcOp &Src0,
1428  const SrcOp &Src1,
1429  Optional<unsigned> Flags = None) {
1430  return buildInstr(TargetOpcode::G_UMULH, {Dst}, {Src0, Src1}, Flags);
1431  }
1432 
1433  MachineInstrBuilder buildSMulH(const DstOp &Dst, const SrcOp &Src0,
1434  const SrcOp &Src1,
1435  Optional<unsigned> Flags = None) {
1436  return buildInstr(TargetOpcode::G_SMULH, {Dst}, {Src0, Src1}, Flags);
1437  }
1438 
1439  /// Build and insert \p Res = G_UREM \p Op0, \p Op1
1440  MachineInstrBuilder buildURem(const DstOp &Dst, const SrcOp &Src0,
1441  const SrcOp &Src1,
1442  Optional<unsigned> Flags = None) {
1443  return buildInstr(TargetOpcode::G_UREM, {Dst}, {Src0, Src1}, Flags);
1444  }
1445 
1446  MachineInstrBuilder buildFMul(const DstOp &Dst, const SrcOp &Src0,
1447  const SrcOp &Src1,
1448  Optional<unsigned> Flags = None) {
1449  return buildInstr(TargetOpcode::G_FMUL, {Dst}, {Src0, Src1}, Flags);
1450  }
1451 
1452  MachineInstrBuilder buildFMinNum(const DstOp &Dst, const SrcOp &Src0,
1453  const SrcOp &Src1,
1454  Optional<unsigned> Flags = None) {
1455  return buildInstr(TargetOpcode::G_FMINNUM, {Dst}, {Src0, Src1}, Flags);
1456  }
1457 
1458  MachineInstrBuilder buildFMaxNum(const DstOp &Dst, const SrcOp &Src0,
1459  const SrcOp &Src1,
1460  Optional<unsigned> Flags = None) {
1461  return buildInstr(TargetOpcode::G_FMAXNUM, {Dst}, {Src0, Src1}, Flags);
1462  }
1463 
1465  const SrcOp &Src1,
1466  Optional<unsigned> Flags = None) {
1467  return buildInstr(TargetOpcode::G_FMINNUM_IEEE, {Dst}, {Src0, Src1}, Flags);
1468  }
1469 
1471  const SrcOp &Src1,
1472  Optional<unsigned> Flags = None) {
1473  return buildInstr(TargetOpcode::G_FMAXNUM_IEEE, {Dst}, {Src0, Src1}, Flags);
1474  }
1475 
1476  MachineInstrBuilder buildShl(const DstOp &Dst, const SrcOp &Src0,
1477  const SrcOp &Src1,
1478  Optional<unsigned> Flags = None) {
1479  return buildInstr(TargetOpcode::G_SHL, {Dst}, {Src0, Src1}, Flags);
1480  }
1481 
1482  MachineInstrBuilder buildLShr(const DstOp &Dst, const SrcOp &Src0,
1483  const SrcOp &Src1,
1484  Optional<unsigned> Flags = None) {
1485  return buildInstr(TargetOpcode::G_LSHR, {Dst}, {Src0, Src1}, Flags);
1486  }
1487 
1488  MachineInstrBuilder buildAShr(const DstOp &Dst, const SrcOp &Src0,
1489  const SrcOp &Src1,
1490  Optional<unsigned> Flags = None) {
1491  return buildInstr(TargetOpcode::G_ASHR, {Dst}, {Src0, Src1}, Flags);
1492  }
1493 
1494  /// Build and insert \p Res = G_AND \p Op0, \p Op1
1495  ///
1496  /// G_AND sets \p Res to the bitwise and of integer parameters \p Op0 and \p
1497  /// Op1.
1498  ///
1499  /// \pre setBasicBlock or setMI must have been called.
1500  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1501  /// with the same (scalar or vector) type).
1502  ///
1503  /// \return a MachineInstrBuilder for the newly created instruction.
1504 
1505  MachineInstrBuilder buildAnd(const DstOp &Dst, const SrcOp &Src0,
1506  const SrcOp &Src1) {
1507  return buildInstr(TargetOpcode::G_AND, {Dst}, {Src0, Src1});
1508  }
1509 
1510  /// Build and insert \p Res = G_OR \p Op0, \p Op1
1511  ///
1512  /// G_OR sets \p Res to the bitwise or of integer parameters \p Op0 and \p
1513  /// Op1.
1514  ///
1515  /// \pre setBasicBlock or setMI must have been called.
1516  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1517  /// with the same (scalar or vector) type).
1518  ///
1519  /// \return a MachineInstrBuilder for the newly created instruction.
1520  MachineInstrBuilder buildOr(const DstOp &Dst, const SrcOp &Src0,
1521  const SrcOp &Src1,
1522  Optional<unsigned> Flags = None) {
1523  return buildInstr(TargetOpcode::G_OR, {Dst}, {Src0, Src1}, Flags);
1524  }
1525 
1526  /// Build and insert \p Res = G_XOR \p Op0, \p Op1
1527  MachineInstrBuilder buildXor(const DstOp &Dst, const SrcOp &Src0,
1528  const SrcOp &Src1) {
1529  return buildInstr(TargetOpcode::G_XOR, {Dst}, {Src0, Src1});
1530  }
1531 
1532  /// Build and insert a bitwise not,
1533  /// \p NegOne = G_CONSTANT -1
1534  /// \p Res = G_OR \p Op0, NegOne
1535  MachineInstrBuilder buildNot(const DstOp &Dst, const SrcOp &Src0) {
1536  auto NegOne = buildConstant(Dst.getLLTTy(*getMRI()), -1);
1537  return buildInstr(TargetOpcode::G_XOR, {Dst}, {Src0, NegOne});
1538  }
1539 
1540  /// Build and insert integer negation
1541  /// \p Zero = G_CONSTANT 0
1542  /// \p Res = G_SUB Zero, \p Op0
1543  MachineInstrBuilder buildNeg(const DstOp &Dst, const SrcOp &Src0) {
1544  auto Zero = buildConstant(Dst.getLLTTy(*getMRI()), 0);
1545  return buildInstr(TargetOpcode::G_SUB, {Dst}, {Zero, Src0});
1546  }
1547 
1548  /// Build and insert \p Res = G_CTPOP \p Op0, \p Src0
1549  MachineInstrBuilder buildCTPOP(const DstOp &Dst, const SrcOp &Src0) {
1550  return buildInstr(TargetOpcode::G_CTPOP, {Dst}, {Src0});
1551  }
1552 
1553  /// Build and insert \p Res = G_CTLZ \p Op0, \p Src0
1554  MachineInstrBuilder buildCTLZ(const DstOp &Dst, const SrcOp &Src0) {
1555  return buildInstr(TargetOpcode::G_CTLZ, {Dst}, {Src0});
1556  }
1557 
1558  /// Build and insert \p Res = G_CTLZ_ZERO_UNDEF \p Op0, \p Src0
1560  return buildInstr(TargetOpcode::G_CTLZ_ZERO_UNDEF, {Dst}, {Src0});
1561  }
1562 
1563  /// Build and insert \p Res = G_CTTZ \p Op0, \p Src0
1564  MachineInstrBuilder buildCTTZ(const DstOp &Dst, const SrcOp &Src0) {
1565  return buildInstr(TargetOpcode::G_CTTZ, {Dst}, {Src0});
1566  }
1567 
1568  /// Build and insert \p Res = G_CTTZ_ZERO_UNDEF \p Op0, \p Src0
1570  return buildInstr(TargetOpcode::G_CTTZ_ZERO_UNDEF, {Dst}, {Src0});
1571  }
1572 
1573  /// Build and insert \p Dst = G_BSWAP \p Src0
1574  MachineInstrBuilder buildBSwap(const DstOp &Dst, const SrcOp &Src0) {
1575  return buildInstr(TargetOpcode::G_BSWAP, {Dst}, {Src0});
1576  }
1577 
1578  /// Build and insert \p Res = G_FADD \p Op0, \p Op1
1579  MachineInstrBuilder buildFAdd(const DstOp &Dst, const SrcOp &Src0,
1580  const SrcOp &Src1,
1581  Optional<unsigned> Flags = None) {
1582  return buildInstr(TargetOpcode::G_FADD, {Dst}, {Src0, Src1}, Flags);
1583  }
1584 
1585  /// Build and insert \p Res = G_FSUB \p Op0, \p Op1
1586  MachineInstrBuilder buildFSub(const DstOp &Dst, const SrcOp &Src0,
1587  const SrcOp &Src1,
1588  Optional<unsigned> Flags = None) {
1589  return buildInstr(TargetOpcode::G_FSUB, {Dst}, {Src0, Src1}, Flags);
1590  }
1591 
1592  /// Build and insert \p Res = G_FDIV \p Op0, \p Op1
1593  MachineInstrBuilder buildFDiv(const DstOp &Dst, const SrcOp &Src0,
1594  const SrcOp &Src1,
1595  Optional<unsigned> Flags = None) {
1596  return buildInstr(TargetOpcode::G_FDIV, {Dst}, {Src0, Src1}, Flags);
1597  }
1598 
1599  /// Build and insert \p Res = G_FMA \p Op0, \p Op1, \p Op2
1600  MachineInstrBuilder buildFMA(const DstOp &Dst, const SrcOp &Src0,
1601  const SrcOp &Src1, const SrcOp &Src2,
1602  Optional<unsigned> Flags = None) {
1603  return buildInstr(TargetOpcode::G_FMA, {Dst}, {Src0, Src1, Src2}, Flags);
1604  }
1605 
1606  /// Build and insert \p Res = G_FMAD \p Op0, \p Op1, \p Op2
1607  MachineInstrBuilder buildFMAD(const DstOp &Dst, const SrcOp &Src0,
1608  const SrcOp &Src1, const SrcOp &Src2,
1609  Optional<unsigned> Flags = None) {
1610  return buildInstr(TargetOpcode::G_FMAD, {Dst}, {Src0, Src1, Src2}, Flags);
1611  }
1612 
1613  /// Build and insert \p Res = G_FNEG \p Op0
1614  MachineInstrBuilder buildFNeg(const DstOp &Dst, const SrcOp &Src0,
1615  Optional<unsigned> Flags = None) {
1616  return buildInstr(TargetOpcode::G_FNEG, {Dst}, {Src0}, Flags);
1617  }
1618 
1619  /// Build and insert \p Res = G_FABS \p Op0
1620  MachineInstrBuilder buildFAbs(const DstOp &Dst, const SrcOp &Src0,
1621  Optional<unsigned> Flags = None) {
1622  return buildInstr(TargetOpcode::G_FABS, {Dst}, {Src0}, Flags);
1623  }
1624 
1625  /// Build and insert \p Dst = G_FCANONICALIZE \p Src0
1627  Optional<unsigned> Flags = None) {
1628  return buildInstr(TargetOpcode::G_FCANONICALIZE, {Dst}, {Src0}, Flags);
1629  }
1630 
1631  /// Build and insert \p Dst = G_INTRINSIC_TRUNC \p Src0
1633  Optional<unsigned> Flags = None) {
1634  return buildInstr(TargetOpcode::G_INTRINSIC_TRUNC, {Dst}, {Src0}, Flags);
1635  }
1636 
1637  /// Build and insert \p Res = GFFLOOR \p Op0, \p Op1
1638  MachineInstrBuilder buildFFloor(const DstOp &Dst, const SrcOp &Src0,
1639  Optional<unsigned> Flags = None) {
1640  return buildInstr(TargetOpcode::G_FFLOOR, {Dst}, {Src0}, Flags);
1641  }
1642 
1643  /// Build and insert \p Dst = G_FLOG \p Src
1644  MachineInstrBuilder buildFLog(const DstOp &Dst, const SrcOp &Src,
1645  Optional<unsigned> Flags = None) {
1646  return buildInstr(TargetOpcode::G_FLOG, {Dst}, {Src}, Flags);
1647  }
1648 
1649  /// Build and insert \p Dst = G_FLOG2 \p Src
1650  MachineInstrBuilder buildFLog2(const DstOp &Dst, const SrcOp &Src,
1651  Optional<unsigned> Flags = None) {
1652  return buildInstr(TargetOpcode::G_FLOG2, {Dst}, {Src}, Flags);
1653  }
1654 
1655  /// Build and insert \p Dst = G_FEXP2 \p Src
1656  MachineInstrBuilder buildFExp2(const DstOp &Dst, const SrcOp &Src,
1657  Optional<unsigned> Flags = None) {
1658  return buildInstr(TargetOpcode::G_FEXP2, {Dst}, {Src}, Flags);
1659  }
1660 
1661  /// Build and insert \p Dst = G_FPOW \p Src0, \p Src1
1662  MachineInstrBuilder buildFPow(const DstOp &Dst, const SrcOp &Src0,
1663  const SrcOp &Src1,
1664  Optional<unsigned> Flags = None) {
1665  return buildInstr(TargetOpcode::G_FPOW, {Dst}, {Src0, Src1}, Flags);
1666  }
1667 
1668  /// Build and insert \p Res = G_FCOPYSIGN \p Op0, \p Op1
1670  const SrcOp &Src1) {
1671  return buildInstr(TargetOpcode::G_FCOPYSIGN, {Dst}, {Src0, Src1});
1672  }
1673 
1674  /// Build and insert \p Res = G_UITOFP \p Src0
1675  MachineInstrBuilder buildUITOFP(const DstOp &Dst, const SrcOp &Src0) {
1676  return buildInstr(TargetOpcode::G_UITOFP, {Dst}, {Src0});
1677  }
1678 
1679  /// Build and insert \p Res = G_SITOFP \p Src0
1680  MachineInstrBuilder buildSITOFP(const DstOp &Dst, const SrcOp &Src0) {
1681  return buildInstr(TargetOpcode::G_SITOFP, {Dst}, {Src0});
1682  }
1683 
1684  /// Build and insert \p Res = G_FPTOUI \p Src0
1685  MachineInstrBuilder buildFPTOUI(const DstOp &Dst, const SrcOp &Src0) {
1686  return buildInstr(TargetOpcode::G_FPTOUI, {Dst}, {Src0});
1687  }
1688 
1689  /// Build and insert \p Res = G_FPTOSI \p Src0
1690  MachineInstrBuilder buildFPTOSI(const DstOp &Dst, const SrcOp &Src0) {
1691  return buildInstr(TargetOpcode::G_FPTOSI, {Dst}, {Src0});
1692  }
1693 
1694  /// Build and insert \p Res = G_SMIN \p Op0, \p Op1
1695  MachineInstrBuilder buildSMin(const DstOp &Dst, const SrcOp &Src0,
1696  const SrcOp &Src1) {
1697  return buildInstr(TargetOpcode::G_SMIN, {Dst}, {Src0, Src1});
1698  }
1699 
1700  /// Build and insert \p Res = G_SMAX \p Op0, \p Op1
1701  MachineInstrBuilder buildSMax(const DstOp &Dst, const SrcOp &Src0,
1702  const SrcOp &Src1) {
1703  return buildInstr(TargetOpcode::G_SMAX, {Dst}, {Src0, Src1});
1704  }
1705 
1706  /// Build and insert \p Res = G_UMIN \p Op0, \p Op1
1707  MachineInstrBuilder buildUMin(const DstOp &Dst, const SrcOp &Src0,
1708  const SrcOp &Src1) {
1709  return buildInstr(TargetOpcode::G_UMIN, {Dst}, {Src0, Src1});
1710  }
1711 
1712  /// Build and insert \p Res = G_UMAX \p Op0, \p Op1
1713  MachineInstrBuilder buildUMax(const DstOp &Dst, const SrcOp &Src0,
1714  const SrcOp &Src1) {
1715  return buildInstr(TargetOpcode::G_UMAX, {Dst}, {Src0, Src1});
1716  }
1717 
1718  /// Build and insert \p Dst = G_ABS \p Src
1719  MachineInstrBuilder buildAbs(const DstOp &Dst, const SrcOp &Src) {
1720  return buildInstr(TargetOpcode::G_ABS, {Dst}, {Src});
1721  }
1722 
1723  /// Build and insert \p Res = G_JUMP_TABLE \p JTI
1724  ///
1725  /// G_JUMP_TABLE sets \p Res to the address of the jump table specified by
1726  /// the jump table index \p JTI.
1727  ///
1728  /// \return a MachineInstrBuilder for the newly created instruction.
1729  MachineInstrBuilder buildJumpTable(const LLT PtrTy, unsigned JTI);
1730 
1731  /// Build and insert \p Res = G_VECREDUCE_SEQ_FADD \p ScalarIn, \p VecIn
1732  ///
1733  /// \p ScalarIn is the scalar accumulator input to start the sequential
1734  /// reduction operation of \p VecIn.
1736  const SrcOp &ScalarIn,
1737  const SrcOp &VecIn) {
1738  return buildInstr(TargetOpcode::G_VECREDUCE_SEQ_FADD, {Dst},
1739  {ScalarIn, {VecIn}});
1740  }
1741 
1742  /// Build and insert \p Res = G_VECREDUCE_SEQ_FMUL \p ScalarIn, \p VecIn
1743  ///
1744  /// \p ScalarIn is the scalar accumulator input to start the sequential
1745  /// reduction operation of \p VecIn.
1747  const SrcOp &ScalarIn,
1748  const SrcOp &VecIn) {
1749  return buildInstr(TargetOpcode::G_VECREDUCE_SEQ_FMUL, {Dst},
1750  {ScalarIn, {VecIn}});
1751  }
1752 
1753  /// Build and insert \p Res = G_VECREDUCE_FADD \p Src
1754  ///
1755  /// \p ScalarIn is the scalar accumulator input to the reduction operation of
1756  /// \p VecIn.
1758  const SrcOp &ScalarIn,
1759  const SrcOp &VecIn) {
1760  return buildInstr(TargetOpcode::G_VECREDUCE_FADD, {Dst}, {ScalarIn, VecIn});
1761  }
1762 
1763  /// Build and insert \p Res = G_VECREDUCE_FMUL \p Src
1764  ///
1765  /// \p ScalarIn is the scalar accumulator input to the reduction operation of
1766  /// \p VecIn.
1768  const SrcOp &ScalarIn,
1769  const SrcOp &VecIn) {
1770  return buildInstr(TargetOpcode::G_VECREDUCE_FMUL, {Dst}, {ScalarIn, VecIn});
1771  }
1772 
1773  /// Build and insert \p Res = G_VECREDUCE_FMAX \p Src
1775  return buildInstr(TargetOpcode::G_VECREDUCE_FMAX, {Dst}, {Src});
1776  }
1777 
1778  /// Build and insert \p Res = G_VECREDUCE_FMIN \p Src
1780  return buildInstr(TargetOpcode::G_VECREDUCE_FMIN, {Dst}, {Src});
1781  }
1782  /// Build and insert \p Res = G_VECREDUCE_ADD \p Src
1784  return buildInstr(TargetOpcode::G_VECREDUCE_ADD, {Dst}, {Src});
1785  }
1786 
1787  /// Build and insert \p Res = G_VECREDUCE_MUL \p Src
1789  return buildInstr(TargetOpcode::G_VECREDUCE_MUL, {Dst}, {Src});
1790  }
1791 
1792  /// Build and insert \p Res = G_VECREDUCE_AND \p Src
1794  return buildInstr(TargetOpcode::G_VECREDUCE_AND, {Dst}, {Src});
1795  }
1796 
1797  /// Build and insert \p Res = G_VECREDUCE_OR \p Src
1799  return buildInstr(TargetOpcode::G_VECREDUCE_OR, {Dst}, {Src});
1800  }
1801 
1802  /// Build and insert \p Res = G_VECREDUCE_XOR \p Src
1804  return buildInstr(TargetOpcode::G_VECREDUCE_XOR, {Dst}, {Src});
1805  }
1806 
1807  /// Build and insert \p Res = G_VECREDUCE_SMAX \p Src
1809  return buildInstr(TargetOpcode::G_VECREDUCE_SMAX, {Dst}, {Src});
1810  }
1811 
1812  /// Build and insert \p Res = G_VECREDUCE_SMIN \p Src
1814  return buildInstr(TargetOpcode::G_VECREDUCE_SMIN, {Dst}, {Src});
1815  }
1816 
1817  /// Build and insert \p Res = G_VECREDUCE_UMAX \p Src
1819  return buildInstr(TargetOpcode::G_VECREDUCE_UMAX, {Dst}, {Src});
1820  }
1821 
1822  /// Build and insert \p Res = G_VECREDUCE_UMIN \p Src
1824  return buildInstr(TargetOpcode::G_VECREDUCE_UMIN, {Dst}, {Src});
1825  }
1826 
1827  /// Build and insert G_MEMCPY or G_MEMMOVE
1828  MachineInstrBuilder buildMemTransferInst(unsigned Opcode, const SrcOp &DstPtr,
1829  const SrcOp &SrcPtr,
1830  const SrcOp &Size,
1831  MachineMemOperand &DstMMO,
1832  MachineMemOperand &SrcMMO) {
1833  auto MIB = buildInstr(
1834  Opcode, {}, {DstPtr, SrcPtr, Size, SrcOp(INT64_C(0) /*isTailCall*/)});
1835  MIB.addMemOperand(&DstMMO);
1836  MIB.addMemOperand(&SrcMMO);
1837  return MIB;
1838  }
1839 
1840  MachineInstrBuilder buildMemCpy(const SrcOp &DstPtr, const SrcOp &SrcPtr,
1841  const SrcOp &Size, MachineMemOperand &DstMMO,
1842  MachineMemOperand &SrcMMO) {
1843  return buildMemTransferInst(TargetOpcode::G_MEMCPY, DstPtr, SrcPtr, Size,
1844  DstMMO, SrcMMO);
1845  }
1846 
1847  /// Build and insert \p Dst = G_SBFX \p Src, \p LSB, \p Width.
1848  MachineInstrBuilder buildSbfx(const DstOp &Dst, const SrcOp &Src,
1849  const SrcOp &LSB, const SrcOp &Width) {
1850  return buildInstr(TargetOpcode::G_SBFX, {Dst}, {Src, LSB, Width});
1851  }
1852 
1853  /// Build and insert \p Dst = G_UBFX \p Src, \p LSB, \p Width.
1854  MachineInstrBuilder buildUbfx(const DstOp &Dst, const SrcOp &Src,
1855  const SrcOp &LSB, const SrcOp &Width) {
1856  return buildInstr(TargetOpcode::G_UBFX, {Dst}, {Src, LSB, Width});
1857  }
1858 
1859  /// Build and insert \p Dst = G_ROTR \p Src, \p Amt
1861  const SrcOp &Amt) {
1862  return buildInstr(TargetOpcode::G_ROTR, {Dst}, {Src, Amt});
1863  }
1864 
1865  /// Build and insert \p Dst = G_ROTL \p Src, \p Amt
1867  const SrcOp &Amt) {
1868  return buildInstr(TargetOpcode::G_ROTL, {Dst}, {Src, Amt});
1869  }
1870 
1871  /// Build and insert \p Dst = G_BITREVERSE \p Src
1873  return buildInstr(TargetOpcode::G_BITREVERSE, {Dst}, {Src});
1874  }
1875 
1876  virtual MachineInstrBuilder buildInstr(unsigned Opc, ArrayRef<DstOp> DstOps,
1877  ArrayRef<SrcOp> SrcOps,
1878  Optional<unsigned> Flags = None);
1879 };
1880 
1881 } // End namespace llvm.
1882 #endif // LLVM_CODEGEN_GLOBALISEL_MACHINEIRBUILDER_H
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
llvm::MachineIRBuilder::buildUSubo
MachineInstrBuilder buildUSubo(const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1)
Build and insert Res, CarryOut = G_USUBO Op0, Op1.
Definition: MachineIRBuilder.h:518
llvm::MachineIRBuilder::setMF
void setMF(MachineFunction &MF)
Definition: MachineIRBuilder.cpp:26
llvm::MachineIRBuilder::buildInsertVectorElement
MachineInstrBuilder buildInsertVectorElement(const DstOp &Res, const SrcOp &Val, const SrcOp &Elt, const SrcOp &Idx)
Build and insert Res = G_INSERT_VECTOR_ELT Val, Elt, Idx.
Definition: MachineIRBuilder.cpp:774
LowLevelType.h
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:103
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:131
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
llvm::MachineIRBuilder::buildGlobalValue
MachineInstrBuilder buildGlobalValue(const DstOp &Res, const GlobalValue *GV)
Build and insert Res = G_GLOBAL_VALUE GV.
Definition: MachineIRBuilder.cpp:146
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::DstOp::DstType::Ty_LLT
@ Ty_LLT
llvm::MachineIRBuilder::buildOr
MachineInstrBuilder buildOr(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Build and insert Res = G_OR Op0, Op1.
Definition: MachineIRBuilder.h:1520
llvm::MachineIRBuilder::buildFMul
MachineInstrBuilder buildFMul(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Definition: MachineIRBuilder.h:1446
llvm::MachineIRBuilder::buildAtomicRMW
MachineInstrBuilder buildAtomicRMW(unsigned Opcode, const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_<Opcode> Addr, Val, MMO.
Definition: MachineIRBuilder.cpp:837
llvm::MachineIRBuilder::setDebugLoc
void setDebugLoc(const DebugLoc &DL)
Set the debug location to DL for all the next build instructions.
Definition: MachineIRBuilder.h:355
llvm::MachineIRBuilder::buildIntToPtr
MachineInstrBuilder buildIntToPtr(const DstOp &Dst, const SrcOp &Src)
Build and insert a G_INTTOPTR instruction.
Definition: MachineIRBuilder.h:628
llvm::MachineIRBuilder::buildICmp
MachineInstrBuilder buildICmp(CmpInst::Predicate Pred, const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1)
Build and insert a Res = G_ICMP Pred, Op0, Op1.
Definition: MachineIRBuilder.cpp:748
llvm::MachineIRBuilder::buildSMax
MachineInstrBuilder buildSMax(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_SMAX Op0, Op1.
Definition: MachineIRBuilder.h:1701
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:112
llvm::CmpInst::Predicate
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:720
llvm::MachineIRBuilderState::II
MachineBasicBlock::iterator II
Definition: MachineIRBuilder.h:50
llvm::MachineIRBuilder::buildAShr
MachineInstrBuilder buildAShr(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Definition: MachineIRBuilder.h:1488
llvm::MachineIRBuilder::buildFSub
MachineInstrBuilder buildFSub(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Build and insert Res = G_FSUB Op0, Op1.
Definition: MachineIRBuilder.h:1586
llvm::MachineIRBuilder::buildUSube
MachineInstrBuilder buildUSube(const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1, const SrcOp &CarryIn)
Build and insert Res, CarryOut = G_USUBE Op0, Op1, CarryInp.
Definition: MachineIRBuilder.h:557
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
llvm::MachineIRBuilder::buildSMulH
MachineInstrBuilder buildSMulH(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Definition: MachineIRBuilder.h:1433
P
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
Definition: README-SSE.txt:411
llvm::MachineIRBuilder::buildSbfx
MachineInstrBuilder buildSbfx(const DstOp &Dst, const SrcOp &Src, const SrcOp &LSB, const SrcOp &Width)
Build and insert Dst = G_SBFX Src, LSB, Width.
Definition: MachineIRBuilder.h:1848
llvm::MachineIRBuilder::getCSEInfo
GISelCSEInfo * getCSEInfo()
Definition: MachineIRBuilder.h:297
llvm::MachineIRBuilder::buildUMulH
MachineInstrBuilder buildUMulH(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Definition: MachineIRBuilder.h:1427
llvm::MachineIRBuilder::buildBSwap
MachineInstrBuilder buildBSwap(const DstOp &Dst, const SrcOp &Src0)
Build and insert Dst = G_BSWAP Src0.
Definition: MachineIRBuilder.h:1574
llvm::MachineIRBuilder::buildSplatVector
MachineInstrBuilder buildSplatVector(const DstOp &Res, const SrcOp &Src)
Build and insert Res = G_BUILD_VECTOR with Src replicated to fill the number of elements.
Definition: MachineIRBuilder.cpp:641
llvm::MachineIRBuilder::getMRI
MachineRegisterInfo * getMRI()
Getter for MRI.
Definition: MachineIRBuilder.h:280
llvm::MachineIRBuilder::buildZExtInReg
MachineInstrBuilder buildZExtInReg(const DstOp &Res, const SrcOp &Op, int64_t ImmOp)
Build and inserts Res = G_AND Op, LowBitsSet(ImmOp) Since there is no G_ZEXT_INREG like G_SEXT_INREG,...
Definition: MachineIRBuilder.cpp:487
llvm::DstOp::RC
const TargetRegisterClass * RC
Definition: MachineIRBuilder.h:62
llvm::MachineIRBuilder::buildAtomicRMWOr
MachineInstrBuilder buildAtomicRMWOr(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_OR Addr, Val, MMO.
Definition: MachineIRBuilder.cpp:891
llvm::MachineIRBuilder::buildFCanonicalize
MachineInstrBuilder buildFCanonicalize(const DstOp &Dst, const SrcOp &Src0, Optional< unsigned > Flags=None)
Build and insert Dst = G_FCANONICALIZE Src0.
Definition: MachineIRBuilder.h:1626
llvm::GISelCSEInfo
The CSE Analysis object.
Definition: CSEInfo.h:69
llvm::MachineIRBuilder::buildNeg
MachineInstrBuilder buildNeg(const DstOp &Dst, const SrcOp &Src0)
Build and insert integer negation Zero = G_CONSTANT 0 Res = G_SUB Zero, Op0.
Definition: MachineIRBuilder.h:1543
llvm::MachineIRBuilder::buildFAbs
MachineInstrBuilder buildFAbs(const DstOp &Dst, const SrcOp &Src0, Optional< unsigned > Flags=None)
Build and insert Res = G_FABS Op0.
Definition: MachineIRBuilder.h:1620
llvm::MachineIRBuilder::MachineIRBuilder
MachineIRBuilder(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsPt)
Definition: MachineIRBuilder.h:236
llvm::MachineIRBuilder::buildZExtOrTrunc
MachineInstrBuilder buildZExtOrTrunc(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_ZEXT Op, Res = G_TRUNC Op, or Res = COPY Op depending on the differing sizes...
Definition: MachineIRBuilder.cpp:477
MachineBasicBlock.h
llvm::MachineIRBuilder::buildUMin
MachineInstrBuilder buildUMin(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_UMIN Op0, Op1.
Definition: MachineIRBuilder.h:1707
llvm::AAMDNodes
A collection of metadata nodes that might be associated with a memory access used by the alias-analys...
Definition: Metadata.h:651
llvm::MachineIRBuilder::buildAtomicRMWAdd
MachineInstrBuilder buildAtomicRMWAdd(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_ADD Addr, Val, MMO.
Definition: MachineIRBuilder.cpp:868
llvm::MachineIRBuilder::buildAtomicCmpXchg
MachineInstrBuilder buildAtomicCmpXchg(Register OldValRes, Register Addr, Register CmpVal, Register NewVal, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMIC_CMPXCHG Addr, CmpVal, NewVal, MMO.
Definition: MachineIRBuilder.cpp:813
llvm::MachineIRBuilder::buildDbgLabel
MachineInstrBuilder buildDbgLabel(const MDNode *Label)
Build and insert a DBG_LABEL instructions specifying that Label is given.
Definition: MachineIRBuilder.cpp:117
Module.h
llvm::MachineIRBuilder::buildFMAD
MachineInstrBuilder buildFMAD(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, const SrcOp &Src2, Optional< unsigned > Flags=None)
Build and insert Res = G_FMAD Op0, Op1, Op2.
Definition: MachineIRBuilder.h:1607
llvm::SrcOp::Reg
Register Reg
Definition: MachineIRBuilder.h:122
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition: MachineMemOperand.h:128
llvm::MachineIRBuilder::MachineIRBuilder
MachineIRBuilder()=default
Some constructors for easy use.
llvm::MachineIRBuilder::getDL
const DebugLoc & getDL()
Getter for DebugLoc.
Definition: MachineIRBuilder.h:277
llvm::MachineIRBuilder::buildFPTrunc
MachineInstrBuilder buildFPTrunc(const DstOp &Res, const SrcOp &Op, Optional< unsigned > Flags=None)
Build and insert Res = G_FPTRUNC Op.
Definition: MachineIRBuilder.cpp:742
llvm::MachineIRBuilder::buildVecReduceAdd
MachineInstrBuilder buildVecReduceAdd(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_ADD Src.
Definition: MachineIRBuilder.h:1783
llvm::SrcOp::Imm
int64_t Imm
Definition: MachineIRBuilder.h:124
llvm::MachineIRBuilder::buildCTTZ
MachineInstrBuilder buildCTTZ(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_CTTZ Op0, Src0.
Definition: MachineIRBuilder.h:1564
llvm::Optional
Definition: APInt.h:33
T
#define T
Definition: Mips16ISelLowering.cpp:341
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
llvm::MachineIRBuilder::buildBuildVector
MachineInstrBuilder buildBuildVector(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_BUILD_VECTOR Op0, ...
Definition: MachineIRBuilder.cpp:632
llvm::MachineIRBuilder::getMF
const MachineFunction & getMF() const
Definition: MachineIRBuilder.h:267
llvm::MachineIRBuilder::buildInstrNoInsert
MachineInstrBuilder buildInstrNoInsert(unsigned Opcode)
Build but don't insert <empty> = Opcode <empty>.
Definition: MachineIRBuilder.cpp:40
llvm::MachineIRBuilder::setInstr
void setInstr(MachineInstr &MI)
Set the insertion point to before MI.
Definition: MachineIRBuilder.h:333
llvm::DstOp::DstOp
DstOp(const TargetRegisterClass *TRC)
Definition: MachineIRBuilder.h:71
llvm::MachineIRBuilder::buildExtOrTrunc
MachineInstrBuilder buildExtOrTrunc(unsigned ExtOpc, const DstOp &Res, const SrcOp &Op)
Build and insert Res = ExtOpc, Res = G_TRUNC Op, or Res = COPY Op depending on the differing sizes of...
Definition: MachineIRBuilder.cpp:448
llvm::MachineIRBuilderState::MBB
MachineBasicBlock * MBB
Definition: MachineIRBuilder.h:49
llvm::MachineIRBuilder::buildVecReduceFMin
MachineInstrBuilder buildVecReduceFMin(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_FMIN Src.
Definition: MachineIRBuilder.h:1779
llvm::MachineIRBuilder::buildPtrMask
MachineInstrBuilder buildPtrMask(const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1)
Build and insert Res = G_PTRMASK Op0, Op1.
Definition: MachineIRBuilder.h:479
llvm::MachineIRBuilder::buildXor
MachineInstrBuilder buildXor(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_XOR Op0, Op1.
Definition: MachineIRBuilder.h:1527
llvm::MachineIRBuilder::buildAtomicRMWFSub
MachineInstrBuilder buildAtomicRMWFSub(const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_FSUB Addr, Val, MMO.
Definition: MachineIRBuilder.cpp:938
llvm::MachineIRBuilder::buildFence
MachineInstrBuilder buildFence(unsigned Ordering, unsigned Scope)
Build and insert G_FENCE Ordering, Scope.
Definition: MachineIRBuilder.cpp:945
llvm::BitmaskEnumDetail::Mask
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::MachineIRBuilder::buildFCopysign
MachineInstrBuilder buildFCopysign(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_FCOPYSIGN Op0, Op1.
Definition: MachineIRBuilder.h:1669
llvm::SrcOp::SrcType::Ty_Predicate
@ Ty_Predicate
llvm::MachineIRBuilder::buildDynStackAlloc
MachineInstrBuilder buildDynStackAlloc(const DstOp &Res, const SrcOp &Size, Align Alignment)
Build and insert Res = G_DYN_STACKALLOC Size, Align.
Definition: MachineIRBuilder.cpp:126
llvm::MachineIRBuilder::getDebugLoc
const DebugLoc & getDebugLoc()
Get the current instruction's debug location.
Definition: MachineIRBuilder.h:358
llvm::MachineIRBuilder::getCSEInfo
const GISelCSEInfo * getCSEInfo() const
Definition: MachineIRBuilder.h:298
llvm::MachineIRBuilder::validateSelectOp
void validateSelectOp(const LLT ResTy, const LLT TstTy, const LLT Op0Ty, const LLT Op1Ty)
Definition: MachineIRBuilder.cpp:979
llvm::MachineIRBuilderState
Class which stores all the state required in a MachineIRBuilder.
Definition: MachineIRBuilder.h:37
llvm::MachineIRBuilder::buildConstant
virtual MachineInstrBuilder buildConstant(const DstOp &Res, const ConstantInt &Val)
Build and insert Res = G_CONSTANT Val.
Definition: MachineIRBuilder.cpp:255
llvm::MachineIRBuilder::buildURem
MachineInstrBuilder buildURem(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Build and insert Res = G_UREM Op0, Op1.
Definition: MachineIRBuilder.h:1440
llvm::MachineIRBuilder::validateBinaryOp
void validateBinaryOp(const LLT Res, const LLT Op0, const LLT Op1)
Definition: MachineIRBuilder.cpp:170
MachineRegisterInfo.h
llvm::MachineIRBuilder::buildCTLZ_ZERO_UNDEF
MachineInstrBuilder buildCTLZ_ZERO_UNDEF(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_CTLZ_ZERO_UNDEF Op0, Src0.
Definition: MachineIRBuilder.h:1559
llvm::DstOp::getRegClass
const TargetRegisterClass * getRegClass() const
Definition: MachineIRBuilder.h:104
CSEInfo.h
llvm::DstOp::DstOp
DstOp(const LLT T)
Definition: MachineIRBuilder.h:70
llvm::MachineIRBuilder::buildBitReverse
MachineInstrBuilder buildBitReverse(const DstOp &Dst, const SrcOp &Src)
Build and insert Dst = G_BITREVERSE Src.
Definition: MachineIRBuilder.h:1872
llvm::MachineInstrBuilder::addDef
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
Definition: MachineInstrBuilder.h:116
llvm::MachineIRBuilder::setCSEInfo
void setCSEInfo(GISelCSEInfo *Info)
Definition: MachineIRBuilder.h:315
llvm::ConstantInt
This is the shared class of boolean and integer constants.
Definition: Constants.h:79
llvm::MachineIRBuilder::getMRI
const MachineRegisterInfo * getMRI() const
Definition: MachineIRBuilder.h:281
llvm::MachineIRBuilder::buildAtomicCmpXchgWithSuccess
MachineInstrBuilder buildAtomicCmpXchgWithSuccess(Register OldValRes, Register SuccessRes, Register Addr, Register CmpVal, Register NewVal, MachineMemOperand &MMO)
Build and insert OldValRes<def>, SuccessRes<def> = G_ATOMIC_CMPXCHG_WITH_SUCCESS Addr,...
Definition: MachineIRBuilder.cpp:785
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:97
llvm::MachineIRBuilder::buildUnmerge
MachineInstrBuilder buildUnmerge(ArrayRef< LLT > Res, const SrcOp &Op)
Build and insert Res0, ...
Definition: MachineIRBuilder.cpp:603
llvm::MachineIRBuilder::buildAtomicRMWMin
MachineInstrBuilder buildAtomicRMWMin(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_MIN Addr, Val, MMO.
Definition: MachineIRBuilder.cpp:911
llvm::MachineIRBuilder::buildZExt
MachineInstrBuilder buildZExt(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_ZEXT Op.
Definition: MachineIRBuilder.cpp:424
llvm::MachineIRBuilder::buildExtractVectorElement
MachineInstrBuilder buildExtractVectorElement(const DstOp &Res, const SrcOp &Val, const SrcOp &Idx)
Build and insert Res = G_EXTRACT_VECTOR_ELT Val, Idx.
Definition: MachineIRBuilder.cpp:780
llvm::MachineIRBuilder::buildLoad
MachineInstrBuilder buildLoad(const DstOp &Res, const SrcOp &Addr, MachineMemOperand &MMO)
Build and insert Res = G_LOAD Addr, MMO.
Definition: MachineIRBuilder.h:832
llvm::MachineIRBuilder::MachineIRBuilder
MachineIRBuilder(const MachineIRBuilderState &BState)
Definition: MachineIRBuilder.h:254
Constants.h
llvm::MachineIRBuilder::buildShl
MachineInstrBuilder buildShl(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Definition: MachineIRBuilder.h:1476
llvm::MachineIRBuilder::setMBB
void setMBB(MachineBasicBlock &MBB)
Set the insertion point to the end of MBB.
Definition: MachineIRBuilder.h:324
llvm::DstOp::LLTTy
LLT LLTTy
Definition: MachineIRBuilder.h:60
llvm::DstOp::addDefToMIB
void addDefToMIB(MachineRegisterInfo &MRI, MachineInstrBuilder &MIB) const
Definition: MachineIRBuilder.h:73
llvm::MachineIRBuilder::buildSAdde
MachineInstrBuilder buildSAdde(const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1, const SrcOp &CarryIn)
Build and insert Res, CarryOut = G_SADDE Op0, Op1, CarryInp.
Definition: MachineIRBuilder.h:565
llvm::DstOp::DstType::Ty_RC
@ Ty_RC
llvm::DstOp::getReg
Register getReg() const
Definition: MachineIRBuilder.h:99
llvm::MachineIRBuilder::buildFLog
MachineInstrBuilder buildFLog(const DstOp &Dst, const SrcOp &Src, Optional< unsigned > Flags=None)
Build and insert Dst = G_FLOG Src.
Definition: MachineIRBuilder.h:1644
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::MachineIRBuilder::buildBoolExt
MachineInstrBuilder buildBoolExt(const DstOp &Res, const SrcOp &Op, bool IsFP)
Definition: MachineIRBuilder.cpp:441
llvm::MachineInstr::getOperand
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:499
llvm::MachineIRBuilder::buildPtrToInt
MachineInstrBuilder buildPtrToInt(const DstOp &Dst, const SrcOp &Src)
Build and insert a G_PTRTOINT instruction.
Definition: MachineIRBuilder.h:623
llvm::MachineIRBuilder::recordInsertion
void recordInsertion(MachineInstr *InsertedInstr) const
Definition: MachineIRBuilder.h:226
llvm::MachineIRBuilder::buildAnyExtOrTrunc
MachineInstrBuilder buildAnyExtOrTrunc(const DstOp &Res, const SrcOp &Op)
Res = COPY Op depending on the differing sizes of Res and Op.
Definition: MachineIRBuilder.cpp:482
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::MachineIRBuilder::buildFCmp
MachineInstrBuilder buildFCmp(CmpInst::Predicate Pred, const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1, Optional< unsigned > Flags=None)
Build and insert a Res = G_FCMP PredOp0, Op1.
Definition: MachineIRBuilder.cpp:755
llvm::MachineIRBuilder::buildFIDbgValue
MachineInstrBuilder buildFIDbgValue(int FI, const MDNode *Variable, const MDNode *Expr)
Build and insert a DBG_VALUE instruction expressing the fact that the associated Variable lives in th...
Definition: MachineIRBuilder.cpp:77
llvm::MachineIRBuilder::buildCTLZ
MachineInstrBuilder buildCTLZ(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_CTLZ Op0, Src0.
Definition: MachineIRBuilder.h:1554
TargetOpcodes.h
llvm::MachineIRBuilder::buildConcatVectors
MachineInstrBuilder buildConcatVectors(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_CONCAT_VECTORS Op0, ...
Definition: MachineIRBuilder.cpp:689
llvm::MachineIRBuilder::getDataLayout
const DataLayout & getDataLayout() const
Definition: MachineIRBuilder.h:272
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
llvm::MachineIRBuilder::MachineIRBuilder
MachineIRBuilder(MachineFunction &MF)
Definition: MachineIRBuilder.h:234
llvm::DstOp::getDstOpKind
DstType getDstOpKind() const
Definition: MachineIRBuilder.h:113
llvm::MachineIRBuilder::buildAtomicRMWAnd
MachineInstrBuilder buildAtomicRMWAnd(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_AND Addr, Val, MMO.
Definition: MachineIRBuilder.cpp:880
llvm::MachineIRBuilder::getMF
MachineFunction & getMF()
Getter for the function we currently build.
Definition: MachineIRBuilder.h:262
llvm::ConstantFP
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:257
llvm::MachineIRBuilder::buildFFloor
MachineInstrBuilder buildFFloor(const DstOp &Dst, const SrcOp &Src0, Optional< unsigned > Flags=None)
Build and insert Res = GFFLOOR Op0, Op1.
Definition: MachineIRBuilder.h:1638
DebugLoc.h
llvm::MachineIRBuilder::buildAnd
MachineInstrBuilder buildAnd(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_AND Op0, Op1.
Definition: MachineIRBuilder.h:1505
llvm::MachineIRBuilder::getMBB
MachineBasicBlock & getMBB()
Definition: MachineIRBuilder.h:292
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::MachineIRBuilder::buildSMin
MachineInstrBuilder buildSMin(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_SMIN Op0, Op1.
Definition: MachineIRBuilder.h:1695
llvm::DstOp::DstOp
DstOp(Register R)
Definition: MachineIRBuilder.h:68
llvm::MachineIRBuilder::buildVecReduceOr
MachineInstrBuilder buildVecReduceOr(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_OR Src.
Definition: MachineIRBuilder.h:1798
llvm::MachineIRBuilder::buildIndirectDbgValue
MachineInstrBuilder buildIndirectDbgValue(Register Reg, const MDNode *Variable, const MDNode *Expr)
Build and insert a DBG_VALUE instruction expressing the fact that the associated Variable lives in me...
Definition: MachineIRBuilder.cpp:65
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::MachineIRBuilder::buildBrCond
MachineInstrBuilder buildBrCond(const SrcOp &Tst, MachineBasicBlock &Dest)
Build and insert G_BRCOND Tst, Dest.
Definition: MachineIRBuilder.cpp:332
llvm::MachineIRBuilder::buildLoadInstr
MachineInstrBuilder buildLoadInstr(unsigned Opcode, const DstOp &Res, const SrcOp &Addr, MachineMemOperand &MMO)
Build and insert Res = <opcode> Addr, MMO.
Definition: MachineIRBuilder.cpp:356
llvm::DstOp::DstOp
DstOp(unsigned R)
Definition: MachineIRBuilder.h:67
llvm::None
const NoneType None
Definition: None.h:23
llvm::MachineIRBuilder::buildAtomicRMWMax
MachineInstrBuilder buildAtomicRMWMax(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_MAX Addr, Val, MMO.
Definition: MachineIRBuilder.cpp:905
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::MachineIRBuilder::buildBrIndirect
MachineInstrBuilder buildBrIndirect(Register Tgt)
Build and insert G_BRINDIRECT Tgt.
Definition: MachineIRBuilder.cpp:222
llvm::MachineIRBuilder::buildVecReduceFMul
MachineInstrBuilder buildVecReduceFMul(const DstOp &Dst, const SrcOp &ScalarIn, const SrcOp &VecIn)
Build and insert Res = G_VECREDUCE_FMUL Src.
Definition: MachineIRBuilder.h:1767
llvm::MachineIRBuilder::validateUnaryOp
void validateUnaryOp(const LLT Res, const LLT Op0)
Definition: MachineIRBuilder.cpp:165
llvm::MachineIRBuilder::buildFNeg
MachineInstrBuilder buildFNeg(const DstOp &Dst, const SrcOp &Src0, Optional< unsigned > Flags=None)
Build and insert Res = G_FNEG Op0.
Definition: MachineIRBuilder.h:1614
llvm::MachineIRBuilder::buildCTPOP
MachineInstrBuilder buildCTPOP(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_CTPOP Op0, Src0.
Definition: MachineIRBuilder.h:1549
llvm::SrcOp::getImm
int64_t getImm() const
Definition: MachineIRBuilder.h:193
llvm::MachineIRBuilder::buildVecReduceXor
MachineInstrBuilder buildVecReduceXor(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_XOR Src.
Definition: MachineIRBuilder.h:1803
llvm::SrcOp::SrcOp
SrcOp(const MachineOperand &Op)
Definition: MachineIRBuilder.h:130
llvm::MachineIRBuilder::buildBr
MachineInstrBuilder buildBr(MachineBasicBlock &Dest)
Build and insert G_BR Dest.
Definition: MachineIRBuilder.cpp:218
llvm::MachineIRBuilder::buildMaskLowPtrBits
MachineInstrBuilder buildMaskLowPtrBits(const DstOp &Res, const SrcOp &Op0, uint32_t NumBits)
Build and insert Res = G_PTRMASK Op0, G_CONSTANT (1 << NumBits) - 1.
Definition: MachineIRBuilder.cpp:208
llvm::APFloat
Definition: APFloat.h:701
llvm::MachineIRBuilder::buildAbs
MachineInstrBuilder buildAbs(const DstOp &Dst, const SrcOp &Src)
Build and insert Dst = G_ABS Src.
Definition: MachineIRBuilder.h:1719
llvm::MachineIRBuilder::buildFAdd
MachineInstrBuilder buildFAdd(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Build and insert Res = G_FADD Op0, Op1.
Definition: MachineIRBuilder.h:1579
llvm::MachineIRBuilder::buildFMinNum
MachineInstrBuilder buildFMinNum(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Definition: MachineIRBuilder.h:1452
llvm::SrcOp::SrcOp
SrcOp(Register R)
Definition: MachineIRBuilder.h:129
llvm::GlobalValue
Definition: GlobalValue.h:44
llvm::MachineIRBuilder::buildFConstant
virtual MachineInstrBuilder buildFConstant(const DstOp &Res, const ConstantFP &Val)
Build and insert Res = G_FCONSTANT Val.
Definition: MachineIRBuilder.cpp:284
llvm::MachineIRBuilder::buildUbfx
MachineInstrBuilder buildUbfx(const DstOp &Dst, const SrcOp &Src, const SrcOp &LSB, const SrcOp &Width)
Build and insert Dst = G_UBFX Src, LSB, Width.
Definition: MachineIRBuilder.h:1854
llvm::Constant
This is an important base class in LLVM.
Definition: Constant.h:41
llvm::MachineIRBuilder::buildBrJT
MachineInstrBuilder buildBrJT(Register TablePtr, unsigned JTI, Register IndexReg)
Build and insert G_BRJT TablePtr, JTI, IndexReg.
Definition: MachineIRBuilder.cpp:227
llvm::MachineIRBuilder::buildSExtOrTrunc
MachineInstrBuilder buildSExtOrTrunc(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_SEXT Op, Res = G_TRUNC Op, or Res = COPY Op depending on the differing sizes...
Definition: MachineIRBuilder.cpp:472
llvm::MachineIRBuilder::setInsertPt
void setInsertPt(MachineBasicBlock &MBB, MachineBasicBlock::iterator II)
Set the insertion point before the specified position.
Definition: MachineIRBuilder.h:306
llvm::MachineIRBuilder
Helper class to build MachineInstr.
Definition: MachineIRBuilder.h:212
llvm::DstOp::Reg
Register Reg
Definition: MachineIRBuilder.h:61
Index
uint32_t Index
Definition: ELFObjHandler.cpp:84
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:69
llvm::MachineIRBuilder::buildAssertSExt
MachineInstrBuilder buildAssertSExt(const DstOp &Res, const SrcOp &Op, unsigned Size)
Build and insert Res = G_ASSERT_SEXT Op, Size.
Definition: MachineIRBuilder.cpp:243
uint64_t
llvm::SrcOp::SrcType
SrcType
Definition: MachineIRBuilder.h:128
llvm::GlobalValue::getParent
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:572
Addr
uint64_t Addr
Definition: ELFObjHandler.cpp:80
llvm::MachineIRBuilder::buildAssertZExt
MachineInstrBuilder buildAssertZExt(const DstOp &Res, const SrcOp &Op, unsigned Size)
Build and insert Res = G_ASSERT_ZEXT Op, Size.
Definition: MachineIRBuilder.cpp:249
llvm::MachineIRBuilder::buildUMax
MachineInstrBuilder buildUMax(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_UMAX Op0, Op1.
Definition: MachineIRBuilder.h:1713
llvm::MachineIRBuilder::buildBitcast
MachineInstrBuilder buildBitcast(const DstOp &Dst, const SrcOp &Src)
Build and insert Dst = G_BITCAST Src.
Definition: MachineIRBuilder.h:633
llvm::MachineIRBuilder::buildMul
MachineInstrBuilder buildMul(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Build and insert Res = G_MUL Op0, Op1.
Definition: MachineIRBuilder.h:1421
llvm::SrcOp::SrcType::Ty_Reg
@ Ty_Reg
llvm::MachineIRBuilder::getInsertPt
MachineBasicBlock::iterator getInsertPt()
Current insertion point for new instructions.
Definition: MachineIRBuilder.h:301
llvm::MachineIRBuilder::buildIntrinsicTrunc
MachineInstrBuilder buildIntrinsicTrunc(const DstOp &Dst, const SrcOp &Src0, Optional< unsigned > Flags=None)
Build and insert Dst = G_INTRINSIC_TRUNC Src0.
Definition: MachineIRBuilder.h:1632
llvm::MachinePointerInfo
This class contains a discriminated union of information about pointers in memory operands,...
Definition: MachineMemOperand.h:38
llvm::MachineIRBuilder::setInstrAndDebugLoc
void setInstrAndDebugLoc(MachineInstr &MI)
Set the insertion point to before MI, and set the debug loc to MI's loc.
Definition: MachineIRBuilder.h:342
llvm::MachineIRBuilder::buildPtrAdd
MachineInstrBuilder buildPtrAdd(const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1)
Build and insert Res = G_PTR_ADD Op0, Op1.
Definition: MachineIRBuilder.cpp:182
llvm::MachineIRBuilder::buildRotateLeft
MachineInstrBuilder buildRotateLeft(const DstOp &Dst, const SrcOp &Src, const SrcOp &Amt)
Build and insert Dst = G_ROTL Src, Amt.
Definition: MachineIRBuilder.h:1866
llvm::MachineIRBuilder::buildFPTOSI
MachineInstrBuilder buildFPTOSI(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_FPTOSI Src0.
Definition: MachineIRBuilder.h:1690
llvm::MachineIRBuilder::buildAtomicRMWNand
MachineInstrBuilder buildAtomicRMWNand(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_NAND Addr, Val, MMO.
Definition: MachineIRBuilder.cpp:886
llvm::MachineIRBuilder::buildSelect
MachineInstrBuilder buildSelect(const DstOp &Res, const SrcOp &Tst, const SrcOp &Op0, const SrcOp &Op1, Optional< unsigned > Flags=None)
Build and insert a Res = G_SELECT Tst, Op0, Op1.
Definition: MachineIRBuilder.cpp:764
llvm::MachineMemOperand::Flags
Flags
Flags values. These may be or'd together.
Definition: MachineMemOperand.h:131
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MachineIRBuilder::buildConstDbgValue
MachineInstrBuilder buildConstDbgValue(const Constant &C, const MDNode *Variable, const MDNode *Expr)
Build and insert a DBG_VALUE instructions specifying that Variable is given by C (suitably modified b...
Definition: MachineIRBuilder.cpp:92
llvm::MachineIRBuilder::buildMemTransferInst
MachineInstrBuilder buildMemTransferInst(unsigned Opcode, const SrcOp &DstPtr, const SrcOp &SrcPtr, const SrcOp &Size, MachineMemOperand &DstMMO, MachineMemOperand &SrcMMO)
Build and insert G_MEMCPY or G_MEMMOVE.
Definition: MachineIRBuilder.h:1828
llvm::MachineIRBuilder::getMBB
const MachineBasicBlock & getMBB() const
Getter for the basic block we currently build.
Definition: MachineIRBuilder.h:287
llvm::MachineInstrBuilder::addMemOperand
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
Definition: MachineInstrBuilder.h:202
llvm::MachineIRBuilder::MachineIRBuilder
MachineIRBuilder(MachineInstr &MI)
Definition: MachineIRBuilder.h:241
llvm::SrcOp::getSrcOpKind
SrcType getSrcOpKind() const
Definition: MachineIRBuilder.h:202
llvm::MachineIRBuilder::MachineIRBuilder
MachineIRBuilder(MachineInstr &MI, GISelChangeObserver &Observer)
Definition: MachineIRBuilder.h:247
llvm::MachineIRBuilder::buildFMaxNumIEEE
MachineInstrBuilder buildFMaxNumIEEE(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Definition: MachineIRBuilder.h:1470
llvm::MachineIRBuilder::buildUAddo
MachineInstrBuilder buildUAddo(const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1)
Build and insert Res, CarryOut = G_UADDO Op0, Op1.
Definition: MachineIRBuilder.h:512
llvm::MachineInstrBuilder::addUse
const MachineInstrBuilder & addUse(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
Definition: MachineInstrBuilder.h:123
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:360
llvm::MachineIRBuilder::buildAtomicRMWFAdd
MachineInstrBuilder buildAtomicRMWFAdd(const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_FADD Addr, Val, MMO.
Definition: MachineIRBuilder.cpp:930
llvm::MDNode
Metadata node.
Definition: Metadata.h:901
llvm::SrcOp::SrcOp
SrcOp(uint64_t V)
Definition: MachineIRBuilder.h:138
llvm::SrcOp::Pred
CmpInst::Predicate Pred
Definition: MachineIRBuilder.h:123
llvm::MachineIRBuilder::buildFMA
MachineInstrBuilder buildFMA(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, const SrcOp &Src2, Optional< unsigned > Flags=None)
Build and insert Res = G_FMA Op0, Op1, Op2.
Definition: MachineIRBuilder.h:1600
llvm::GISelChangeObserver::createdInstr
virtual void createdInstr(MachineInstr &MI)=0
An instruction has been created and inserted into the function.
llvm::MachineIRBuilder::setChangeObserver
void setChangeObserver(GISelChangeObserver &Observer)
Definition: MachineIRBuilder.h:347
llvm::MachineIRBuilder::buildVecReduceFMax
MachineInstrBuilder buildVecReduceFMax(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_FMAX Src.
Definition: MachineIRBuilder.h:1774
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::MachineFunction
Definition: MachineFunction.h:230
llvm::MachineIRBuilder::buildVecReduceSMax
MachineInstrBuilder buildVecReduceSMax(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_SMAX Src.
Definition: MachineIRBuilder.h:1808
llvm::MachineIRBuilderState::Observer
GISelChangeObserver * Observer
Definition: MachineIRBuilder.h:53
llvm::MachineIRBuilder::buildInstr
MachineInstrBuilder buildInstr(unsigned Opcode)
Build and insert <empty> = Opcode <empty>.
Definition: MachineIRBuilder.h:367
llvm::BlockAddress
The address of a basic block.
Definition: Constants.h:848
llvm::SrcOp::addSrcToMIB
void addSrcToMIB(MachineInstrBuilder &MIB) const
Definition: MachineIRBuilder.h:141
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::MachineIRBuilder::buildVecReduceFAdd
MachineInstrBuilder buildVecReduceFAdd(const DstOp &Dst, const SrcOp &ScalarIn, const SrcOp &VecIn)
Build and insert Res = G_VECREDUCE_FADD Src.
Definition: MachineIRBuilder.h:1757
llvm::SrcOp::getReg
Register getReg() const
Definition: MachineIRBuilder.h:171
llvm::MachineIRBuilder::insertInstr
MachineInstrBuilder insertInstr(MachineInstrBuilder MIB)
Insert an existing instruction at the insertion point.
Definition: MachineIRBuilder.cpp:45
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:136
llvm::MachineIRBuilder::buildCopy
MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op)
Build and insert Res = COPY Op.
Definition: MachineIRBuilder.cpp:238
llvm::MachineIRBuilder::buildFPTOUI
MachineInstrBuilder buildFPTOUI(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_FPTOUI Src0.
Definition: MachineIRBuilder.h:1685
llvm::MachineIRBuilder::buildFPExt
MachineInstrBuilder buildFPExt(const DstOp &Res, const SrcOp &Op, Optional< unsigned > Flags=None)
Build and insert Res = G_FPEXT Op.
Definition: MachineIRBuilder.h:616
getParent
static const Function * getParent(const Value *V)
Definition: BasicAliasAnalysis.cpp:776
uint32_t
llvm::SrcOp::SrcOp
SrcOp(const CmpInst::Predicate P)
Definition: MachineIRBuilder.h:132
llvm::MachineIRBuilder::buildSequence
void buildSequence(Register Res, ArrayRef< Register > Ops, ArrayRef< uint64_t > Indices)
Build and insert instructions to put Ops together at the specified p Indices to form a larger registe...
Definition: MachineIRBuilder.cpp:541
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::MachineIRBuilder::buildInsert
MachineInstrBuilder buildInsert(const DstOp &Res, const SrcOp &Src, const SrcOp &Op, unsigned Index)
Definition: MachineIRBuilder.cpp:697
llvm::DstOp::DstOp
DstOp(const MachineOperand &Op)
Definition: MachineIRBuilder.h:69
llvm::MachineIRBuilder::buildFLog2
MachineInstrBuilder buildFLog2(const DstOp &Dst, const SrcOp &Src, Optional< unsigned > Flags=None)
Build and insert Dst = G_FLOG2 Src.
Definition: MachineIRBuilder.h:1650
llvm::MachineIRBuilderState::TII
const TargetInstrInfo * TII
Information used to access the description of the opcodes.
Definition: MachineIRBuilder.h:41
llvm::MachineIRBuilder::buildExtract
MachineInstrBuilder buildExtract(const DstOp &Res, const SrcOp &Src, uint64_t Index)
Build and insert Res0, ...
Definition: MachineIRBuilder.cpp:516
llvm::MachineInstrBuilder::addPredicate
const MachineInstrBuilder & addPredicate(CmpInst::Predicate Pred) const
Definition: MachineInstrBuilder.h:257
llvm::MachineIRBuilder::buildVecReduceUMax
MachineInstrBuilder buildVecReduceUMax(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_UMAX Src.
Definition: MachineIRBuilder.h:1818
llvm::GISelChangeObserver
Abstract class that contains various methods for clients to notify about changes.
Definition: GISelChangeObserver.h:29
llvm::MachineIRBuilder::buildSExtInReg
MachineInstrBuilder buildSExtInReg(const DstOp &Res, const SrcOp &Op, int64_t ImmOp)
Build and insert Res = G_SEXT_INREG Op, ImmOp.
Definition: MachineIRBuilder.h:611
llvm::MachineIRBuilder::buildNot
MachineInstrBuilder buildNot(const DstOp &Dst, const SrcOp &Src0)
Build and insert a bitwise not, NegOne = G_CONSTANT -1 Res = G_OR Op0, NegOne.
Definition: MachineIRBuilder.h:1535
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::MachineIRBuilder::buildAnyExt
MachineInstrBuilder buildAnyExt(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_ANYEXT Op0.
Definition: MachineIRBuilder.cpp:414
llvm::MachineIRBuilder::materializePtrAdd
Optional< MachineInstrBuilder > materializePtrAdd(Register &Res, Register Op0, const LLT ValueTy, uint64_t Value)
Materialize and insert Res = G_PTR_ADD Op0, (G_CONSTANT Value)
Definition: MachineIRBuilder.cpp:193
llvm::MachineIRBuilder::buildJumpTable
MachineInstrBuilder buildJumpTable(const LLT PtrTy, unsigned JTI)
Build and insert Res = G_JUMP_TABLE JTI.
Definition: MachineIRBuilder.cpp:159
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::DstOp::DstType
DstType
Definition: MachineIRBuilder.h:66
llvm::MachineIRBuilder::buildFrameIndex
MachineInstrBuilder buildFrameIndex(const DstOp &Res, int Idx)
Build and insert Res = G_FRAME_INDEX Idx.
Definition: MachineIRBuilder.cpp:137
llvm::SrcOp::SrcMIB
MachineInstrBuilder SrcMIB
Definition: MachineIRBuilder.h:121
llvm::MachineIRBuilder::buildSSube
MachineInstrBuilder buildSSube(const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1, const SrcOp &CarryIn)
Build and insert Res, CarryOut = G_SSUBE Op0, Op1, CarryInp.
Definition: MachineIRBuilder.h:573
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::MachineIRBuilder::buildUAdde
MachineInstrBuilder buildUAdde(const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1, const SrcOp &CarryIn)
Build and insert Res, CarryOut = G_UADDE Op0, Op1, CarryIn.
Definition: MachineIRBuilder.h:549
llvm::MachineIRBuilder::buildUITOFP
MachineInstrBuilder buildUITOFP(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_UITOFP Src0.
Definition: MachineIRBuilder.h:1675
llvm::MachineIRBuilder::buildVecReduceSeqFAdd
MachineInstrBuilder buildVecReduceSeqFAdd(const DstOp &Dst, const SrcOp &ScalarIn, const SrcOp &VecIn)
Build and insert Res = G_VECREDUCE_SEQ_FADD ScalarIn, VecIn.
Definition: MachineIRBuilder.h:1735
llvm::MachineIRBuilder::buildVecReduceAnd
MachineInstrBuilder buildVecReduceAnd(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_AND Src.
Definition: MachineIRBuilder.h:1793
llvm::MachineIRBuilder::buildSAddo
MachineInstrBuilder buildSAddo(const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1)
Build and insert Res, CarryOut = G_SADDO Op0, Op1.
Definition: MachineIRBuilder.h:524
llvm::SrcOp::SrcType::Ty_Imm
@ Ty_Imm
llvm::MachineIRBuilder::buildFPow
MachineInstrBuilder buildFPow(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Build and insert Dst = G_FPOW Src0, Src1.
Definition: MachineIRBuilder.h:1662
llvm::MachineIRBuilder::buildTrunc
MachineInstrBuilder buildTrunc(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_TRUNC Op.
Definition: MachineIRBuilder.cpp:737
llvm::MachineIRBuilder::buildMemCpy
MachineInstrBuilder buildMemCpy(const SrcOp &DstPtr, const SrcOp &SrcPtr, const SrcOp &Size, MachineMemOperand &DstMMO, MachineMemOperand &SrcMMO)
Definition: MachineIRBuilder.h:1840
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:592
llvm::MachineIRBuilder::~MachineIRBuilder
virtual ~MachineIRBuilder()=default
llvm::MachineIRBuilder::buildVecReduceMul
MachineInstrBuilder buildVecReduceMul(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_MUL Src.
Definition: MachineIRBuilder.h:1788
llvm::MachineIRBuilderState::DL
DebugLoc DL
Debug location to be set to any instruction we create.
Definition: MachineIRBuilder.h:45
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:321
llvm::MachineIRBuilder::buildSITOFP
MachineInstrBuilder buildSITOFP(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_SITOFP Src0.
Definition: MachineIRBuilder.h:1680
llvm::MachineIRBuilder::buildUndef
MachineInstrBuilder buildUndef(const DstOp &Res)
Build and insert Res = IMPLICIT_DEF.
Definition: MachineIRBuilder.cpp:582
llvm::MachineIRBuilder::buildDirectDbgValue
MachineInstrBuilder buildDirectDbgValue(Register Reg, const MDNode *Variable, const MDNode *Expr)
Build and insert a DBG_VALUE instruction expressing the fact that the associated Variable lives in Re...
Definition: MachineIRBuilder.cpp:52
llvm::MachineIRBuilder::buildVecReduceUMin
MachineInstrBuilder buildVecReduceUMin(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_UMIN Src.
Definition: MachineIRBuilder.h:1823
llvm::MachineIRBuilder::buildAtomicRMWUmin
MachineInstrBuilder buildAtomicRMWUmin(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_UMIN Addr, Val, MMO.
Definition: MachineIRBuilder.cpp:923
llvm::MachineIRBuilder::buildShuffleVector
MachineInstrBuilder buildShuffleVector(const DstOp &Res, const SrcOp &Src1, const SrcOp &Src2, ArrayRef< int > Mask)
Build and insert Res = G_SHUFFLE_VECTOR Src1, Src2, Mask.
Definition: MachineIRBuilder.cpp:669
llvm::SrcOp::SrcOp
SrcOp(int64_t V)
Definition: MachineIRBuilder.h:139
llvm::MachineIRBuilder::buildAtomicRMWXor
MachineInstrBuilder buildAtomicRMWXor(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_XOR Addr, Val, MMO.
Definition: MachineIRBuilder.cpp:899
llvm::MachineIRBuilder::getTII
const TargetInstrInfo & getTII()
Definition: MachineIRBuilder.h:256
llvm::MachineIRBuilder::buildRotateRight
MachineInstrBuilder buildRotateRight(const DstOp &Dst, const SrcOp &Src, const SrcOp &Amt)
Build and insert Dst = G_ROTR Src, Amt.
Definition: MachineIRBuilder.h:1860
llvm::MachineIRBuilderState::MF
MachineFunction * MF
MachineFunction under construction.
Definition: MachineIRBuilder.h:39
llvm::SrcOp::getPredicate
CmpInst::Predicate getPredicate() const
Definition: MachineIRBuilder.h:184
llvm::AMDGPU::Hwreg::Width
Width
Definition: SIDefines.h:410
llvm::MachineIRBuilder::buildVecReduceSeqFMul
MachineInstrBuilder buildVecReduceSeqFMul(const DstOp &Dst, const SrcOp &ScalarIn, const SrcOp &VecIn)
Build and insert Res = G_VECREDUCE_SEQ_FMUL ScalarIn, VecIn.
Definition: MachineIRBuilder.h:1746
llvm::MachineIRBuilder::buildFMinNumIEEE
MachineInstrBuilder buildFMinNumIEEE(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Definition: MachineIRBuilder.h:1464
llvm::MachineIRBuilder::buildAddrSpaceCast
MachineInstrBuilder buildAddrSpaceCast(const DstOp &Dst, const SrcOp &Src)
Build and insert Dst = G_ADDRSPACE_CAST Src.
Definition: MachineIRBuilder.h:638
llvm::MachineIRBuilder::buildBlockAddress
MachineInstrBuilder buildBlockAddress(Register Res, const BlockAddress *BA)
Build and insert Res = G_BLOCK_ADDR BA.
Definition: MachineIRBuilder.cpp:952
llvm::MachineIRBuilder::validateTruncExt
void validateTruncExt(const LLT Dst, const LLT Src, bool IsExtend)
Definition: MachineIRBuilder.cpp:960
llvm::DstOp::getLLTTy
LLT getLLTTy(const MachineRegisterInfo &MRI) const
Definition: MachineIRBuilder.h:87
llvm::MachineIRBuilder::buildAtomicRMWUmax
MachineInstrBuilder buildAtomicRMWUmax(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_UMAX Addr, Val, MMO.
Definition: MachineIRBuilder.cpp:917
llvm::MachineIRBuilder::validateShiftOp
void validateShiftOp(const LLT Res, const LLT Op0, const LLT Op1)
Definition: MachineIRBuilder.cpp:176
llvm::MachineIRBuilder::buildIntrinsic
MachineInstrBuilder buildIntrinsic(Intrinsic::ID ID, ArrayRef< Register > Res, bool HasSideEffects)
Build and insert either a G_INTRINSIC (if HasSideEffects is false) or G_INTRINSIC_W_SIDE_EFFECTS inst...
Definition: MachineIRBuilder.cpp:713
llvm::MachineIRBuilder::buildSSubo
MachineInstrBuilder buildSSubo(const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1)
Build and insert Res, CarryOut = G_SUBO Op0, Op1.
Definition: MachineIRBuilder.h:530
MachineInstrBuilder.h
llvm::MachineIRBuilder::buildFExp2
MachineInstrBuilder buildFExp2(const DstOp &Dst, const SrcOp &Src, Optional< unsigned > Flags=None)
Build and insert Dst = G_FEXP2 Src.
Definition: MachineIRBuilder.h:1656
llvm::DstOp::DstType::Ty_Reg
@ Ty_Reg
llvm::MachineIRBuilder::buildSExt
MachineInstrBuilder buildSExt(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_SEXT Op.
Definition: MachineIRBuilder.cpp:419
llvm::DstOp
Definition: MachineIRBuilder.h:58
llvm::MachineIRBuilder::buildFMaxNum
MachineInstrBuilder buildFMaxNum(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Definition: MachineIRBuilder.h:1458
llvm::MachineIRBuilder::buildSub
MachineInstrBuilder buildSub(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Build and insert Res = G_SUB Op0, Op1.
Definition: MachineIRBuilder.h:1405
llvm::SrcOp::SrcOp
SrcOp(const MachineInstrBuilder &MIB)
Definition: MachineIRBuilder.h:131
llvm::MachineIRBuilder::buildLShr
MachineInstrBuilder buildLShr(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Definition: MachineIRBuilder.h:1482
llvm::MachineIRBuilder::buildFDiv
MachineInstrBuilder buildFDiv(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Build and insert Res = G_FDIV Op0, Op1.
Definition: MachineIRBuilder.h:1593
llvm::MachineIRBuilder::buildMerge
MachineInstrBuilder buildMerge(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_MERGE_VALUES Op0, ...
Definition: MachineIRBuilder.cpp:586
llvm::SrcOp::getLLTTy
LLT getLLTTy(const MachineRegisterInfo &MRI) const
Definition: MachineIRBuilder.h:158
llvm::MachineIRBuilder::buildLoadFromOffset
MachineInstrBuilder buildLoadFromOffset(const DstOp &Dst, const SrcOp &BasePtr, MachineMemOperand &BaseMMO, int64_t Offset)
Helper to create a load from a constant offset given a base address.
Definition: MachineIRBuilder.cpp:370
llvm::MachineIRBuilder::buildAtomicRMWSub
MachineInstrBuilder buildAtomicRMWSub(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_SUB Addr, Val, MMO.
Definition: MachineIRBuilder.cpp:874
llvm::Module::getDataLayout
const DataLayout & getDataLayout() const
Get the data layout for the module's target platform.
Definition: Module.cpp:401
llvm::MachineIRBuilder::buildBuildVectorTrunc
MachineInstrBuilder buildBuildVectorTrunc(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_BUILD_VECTOR_TRUNC Op0, ...
Definition: MachineIRBuilder.cpp:648
llvm::MachineIRBuilder::getBoolExtOp
unsigned getBoolExtOp(bool IsVec, bool IsFP) const
Definition: MachineIRBuilder.cpp:429
llvm::MachineIRBuilder::buildFreeze
MachineInstrBuilder buildFreeze(const DstOp &Dst, const SrcOp &Src)
Build and insert Dst = G_FREEZE Src.
Definition: MachineIRBuilder.h:1363
llvm::MachineIRBuilder::getState
MachineIRBuilderState & getState()
Getter for the State.
Definition: MachineIRBuilder.h:284
llvm::MachineIRBuilder::buildCTTZ_ZERO_UNDEF
MachineInstrBuilder buildCTTZ_ZERO_UNDEF(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_CTTZ_ZERO_UNDEF Op0, Src0.
Definition: MachineIRBuilder.h:1569
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::MachineIRBuilder::buildStore
MachineInstrBuilder buildStore(const SrcOp &Val, const SrcOp &Addr, MachineMemOperand &MMO)
Build and insert G_STORE Val, Addr, MMO.
Definition: MachineIRBuilder.cpp:387
llvm::MachineIRBuilder::buildAtomicRMWXchg
MachineInstrBuilder buildAtomicRMWXchg(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_XCHG Addr, Val, MMO.
Definition: MachineIRBuilder.cpp:862
llvm::MachineIRBuilder::buildAdd
MachineInstrBuilder buildAdd(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Build and insert Res = G_ADD Op0, Op1.
Definition: MachineIRBuilder.h:1388
llvm::MachineIRBuilder::stopObservingChanges
void stopObservingChanges()
Definition: MachineIRBuilder.h:351
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::MachineMemOperand::MONone
@ MONone
Definition: MachineMemOperand.h:133
llvm::Value
LLVM Value Representation.
Definition: Value.h:75
llvm::MachineIRBuilderState::CSEInfo
GISelCSEInfo * CSEInfo
Definition: MachineIRBuilder.h:55
llvm::MachineIRBuilderState::MRI
MachineRegisterInfo * MRI
Information used to verify types are consistent and to create virtual registers.
Definition: MachineIRBuilder.h:43
llvm::SrcOp
Definition: MachineIRBuilder.h:119
llvm::SrcOp::SrcType::Ty_MIB
@ Ty_MIB
llvm::MachineIRBuilder::buildCast
MachineInstrBuilder buildCast(const DstOp &Dst, const SrcOp &Src)
Build and insert an appropriate cast between two registers of equal size.
Definition: MachineIRBuilder.cpp:496
llvm::MachineIRBuilder::buildVecReduceSMin
MachineInstrBuilder buildVecReduceSMin(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_SMIN Src.
Definition: MachineIRBuilder.h:1813
llvm::MachineIRBuilder::buildShuffleSplat
MachineInstrBuilder buildShuffleSplat(const DstOp &Res, const SrcOp &Src)
Build and insert a vector splat of a scalar Src using a G_INSERT_VECTOR_ELT and G_SHUFFLE_VECTOR idio...
Definition: MachineIRBuilder.cpp:657
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:37
llvm::LLT
Definition: LowLevelTypeImpl.h:40