LLVM  13.0.0git
CombinerHelper.h
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1 //===-- llvm/CodeGen/GlobalISel/CombinerHelper.h --------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===--------------------------------------------------------------------===//
8 /// \file
9 /// This contains common combine transformations that may be used in a combine
10 /// pass,or by the target elsewhere.
11 /// Targets can pick individual opcode transformations from the helper or use
12 /// tryCombine which invokes all transformations. All of the transformations
13 /// return true if the MachineInstruction changed and false otherwise.
14 ///
15 //===--------------------------------------------------------------------===//
16 
17 #ifndef LLVM_CODEGEN_GLOBALISEL_COMBINERHELPER_H
18 #define LLVM_CODEGEN_GLOBALISEL_COMBINERHELPER_H
19 
20 #include "llvm/ADT/APFloat.h"
21 #include "llvm/ADT/DenseMap.h"
23 #include "llvm/CodeGen/Register.h"
24 #include "llvm/Support/Alignment.h"
25 
26 namespace llvm {
27 
28 class GISelChangeObserver;
29 class MachineIRBuilder;
30 class MachineInstrBuilder;
31 class MachineRegisterInfo;
32 class MachineInstr;
33 class MachineOperand;
34 class GISelKnownBits;
35 class MachineDominatorTree;
36 class LegalizerInfo;
37 struct LegalityQuery;
38 class TargetLowering;
39 
41  LLT Ty; // The result type of the extend.
42  unsigned ExtendOpcode; // G_ANYEXT/G_SEXT/G_ZEXT
44 };
45 
50  bool IsPre;
51 };
52 
53 struct PtrAddChain {
54  int64_t Imm;
56 };
57 
60  int64_t Imm;
61 };
62 
67  uint64_t ValSum;
68 };
69 
70 using OperandBuildSteps =
73  unsigned Opcode = 0; /// The opcode for the produced instruction.
74  OperandBuildSteps OperandFns; /// Operands to be added to the instruction.
75  InstructionBuildSteps() = default;
78 };
79 
81  /// Describes instructions to be built during a combine.
83  InstructionStepsMatchInfo() = default;
85  std::initializer_list<InstructionBuildSteps> InstrsToBuild)
87 };
88 
90 protected:
96  const LegalizerInfo *LI;
97 
98 public:
100  GISelKnownBits *KB = nullptr,
101  MachineDominatorTree *MDT = nullptr,
102  const LegalizerInfo *LI = nullptr);
103 
105  return KB;
106  }
107 
108  const TargetLowering &getTargetLowering() const;
109 
110  /// \return true if the combine is running prior to legalization, or if \p
111  /// Query is legal on the target.
112  bool isLegalOrBeforeLegalizer(const LegalityQuery &Query) const;
113 
114  /// MachineRegisterInfo::replaceRegWith() and inform the observer of the changes
115  void replaceRegWith(MachineRegisterInfo &MRI, Register FromReg, Register ToReg) const;
116 
117  /// Replace a single register operand with a new register and inform the
118  /// observer of the changes.
120  Register ToReg) const;
121 
122  /// If \p MI is COPY, try to combine it.
123  /// Returns true if MI changed.
127 
128  /// Returns true if \p DefMI precedes \p UseMI or they are the same
129  /// instruction. Both must be in the same basic block.
130  bool isPredecessor(const MachineInstr &DefMI, const MachineInstr &UseMI);
131 
132  /// Returns true if \p DefMI dominates \p UseMI. By definition an
133  /// instruction dominates itself.
134  ///
135  /// If we haven't been provided with a MachineDominatorTree during
136  /// construction, this function returns a conservative result that tracks just
137  /// a single basic block.
138  bool dominates(const MachineInstr &DefMI, const MachineInstr &UseMI);
139 
140  /// If \p MI is extend that consumes the result of a load, try to combine it.
141  /// Returns true if MI changed.
145 
146  /// Combine \p MI into a pre-indexed or post-indexed load/store operation if
147  /// legal and the surrounding code makes it useful.
151 
154 
155  /// Match sext_inreg(load p), imm -> sextload p
156  bool matchSextInRegOfLoad(MachineInstr &MI, std::tuple<Register, unsigned> &MatchInfo);
157  bool applySextInRegOfLoad(MachineInstr &MI, std::tuple<Register, unsigned> &MatchInfo);
158 
159  /// Try to combine G_[SU]DIV and G_[SU]REM into a single G_[SU]DIVREM
160  /// when their source operands are identical.
163 
164  /// If a brcond's true block is not the fallthrough, make it so by inverting
165  /// the condition and swapping operands.
168 
169  /// If \p MI is G_CONCAT_VECTORS, try to combine it.
170  /// Returns true if MI changed.
171  /// Right now, we support:
172  /// - concat_vector(undef, undef) => undef
173  /// - concat_vector(build_vector(A, B), build_vector(C, D)) =>
174  /// build_vector(A, B, C, D)
175  ///
176  /// \pre MI.getOpcode() == G_CONCAT_VECTORS.
178  /// Check if the G_CONCAT_VECTORS \p MI is undef or if it
179  /// can be flattened into a build_vector.
180  /// In the first case \p IsUndef will be true.
181  /// In the second case \p Ops will contain the operands needed
182  /// to produce the flattened build_vector.
183  ///
184  /// \pre MI.getOpcode() == G_CONCAT_VECTORS.
185  bool matchCombineConcatVectors(MachineInstr &MI, bool &IsUndef,
187  /// Replace \p MI with a flattened build_vector with \p Ops or an
188  /// implicit_def if IsUndef is true.
189  void applyCombineConcatVectors(MachineInstr &MI, bool IsUndef,
190  const ArrayRef<Register> Ops);
191 
192  /// Try to combine G_SHUFFLE_VECTOR into G_CONCAT_VECTORS.
193  /// Returns true if MI changed.
194  ///
195  /// \pre MI.getOpcode() == G_SHUFFLE_VECTOR.
197  /// Check if the G_SHUFFLE_VECTOR \p MI can be replaced by a
198  /// concat_vectors.
199  /// \p Ops will contain the operands needed to produce the flattened
200  /// concat_vectors.
201  ///
202  /// \pre MI.getOpcode() == G_SHUFFLE_VECTOR.
205  /// Replace \p MI with a concat_vectors with \p Ops.
207  const ArrayRef<Register> Ops);
208 
209  /// Optimize memcpy intrinsics et al, e.g. constant len calls.
210  /// /p MaxLen if non-zero specifies the max length of a mem libcall to inline.
211  ///
212  /// For example (pre-indexed):
213  ///
214  /// $addr = G_PTR_ADD $base, $offset
215  /// [...]
216  /// $val = G_LOAD $addr
217  /// [...]
218  /// $whatever = COPY $addr
219  ///
220  /// -->
221  ///
222  /// $val, $addr = G_INDEXED_LOAD $base, $offset, 1 (IsPre)
223  /// [...]
224  /// $whatever = COPY $addr
225  ///
226  /// or (post-indexed):
227  ///
228  /// G_STORE $val, $base
229  /// [...]
230  /// $addr = G_PTR_ADD $base, $offset
231  /// [...]
232  /// $whatever = COPY $addr
233  ///
234  /// -->
235  ///
236  /// $addr = G_INDEXED_STORE $val, $base, $offset
237  /// [...]
238  /// $whatever = COPY $addr
239  bool tryCombineMemCpyFamily(MachineInstr &MI, unsigned MaxLen = 0);
240 
243 
244  /// Fold (shift (shift base, x), y) -> (shift base (x+y))
247 
248  /// If we have a shift-by-constant of a bitwise logic op that itself has a
249  /// shift-by-constant operand with identical opcode, we may be able to convert
250  /// that into 2 independent shifts followed by the logic op.
252  ShiftOfShiftedLogic &MatchInfo);
254  ShiftOfShiftedLogic &MatchInfo);
255 
256  /// Transform a multiply by a power-of-2 value to a left shift.
257  bool matchCombineMulToShl(MachineInstr &MI, unsigned &ShiftVal);
258  bool applyCombineMulToShl(MachineInstr &MI, unsigned &ShiftVal);
259 
260  // Transform a G_SHL with an extended source into a narrower shift if
261  // possible.
264  const RegisterImmPair &MatchData);
265 
266  /// Reduce a shift by a constant to an unmerge and a shift on a half sized
267  /// type. This will not produce a shift smaller than \p TargetShiftSize.
268  bool matchCombineShiftToUnmerge(MachineInstr &MI, unsigned TargetShiftSize,
269  unsigned &ShiftVal);
270  bool applyCombineShiftToUnmerge(MachineInstr &MI, const unsigned &ShiftVal);
271  bool tryCombineShiftToUnmerge(MachineInstr &MI, unsigned TargetShiftAmount);
272 
273  /// Transform <ty,...> G_UNMERGE(G_MERGE ty X, Y, Z) -> ty X, Y, Z.
274  bool
277  bool
280 
281  /// Transform G_UNMERGE Constant -> Constant1, Constant2, ...
283  SmallVectorImpl<APInt> &Csts);
285  SmallVectorImpl<APInt> &Csts);
286 
287  /// Transform X, Y<dead> = G_UNMERGE Z -> X = G_TRUNC Z.
290 
291  /// Transform X, Y = G_UNMERGE(G_ZEXT(Z)) -> X = G_ZEXT(Z); Y = G_CONSTANT 0
294 
295  /// Transform fp_instr(cst) to constant result of the fp operation.
297  Optional<APFloat> &Cst);
299  Optional<APFloat> &Cst);
300 
301  /// Transform IntToPtr(PtrToInt(x)) to x if cast is in the same address space.
304 
305  /// Transform PtrToInt(IntToPtr(x)) to x.
308 
309  /// Transform G_ADD (G_PTRTOINT x), y -> G_PTRTOINT (G_PTR_ADD x, y)
310  /// Transform G_ADD y, (G_PTRTOINT x) -> G_PTRTOINT (G_PTR_ADD x, y)
312  std::pair<Register, bool> &PtrRegAndCommute);
314  std::pair<Register, bool> &PtrRegAndCommute);
315 
316  // Transform G_PTR_ADD (G_PTRTOINT C1), C2 -> C1 + C2
317  bool matchCombineConstPtrAddToI2P(MachineInstr &MI, int64_t &NewCst);
318  bool applyCombineConstPtrAddToI2P(MachineInstr &MI, int64_t &NewCst);
319 
320  /// Transform anyext(trunc(x)) to x.
323 
324  /// Transform zext(trunc(x)) to x.
326 
327  /// Transform [asz]ext([asz]ext(x)) to [asz]ext x.
329  std::tuple<Register, unsigned> &MatchInfo);
331  std::tuple<Register, unsigned> &MatchInfo);
332 
333  /// Transform fneg(fneg(x)) to x.
335 
336  /// Match fabs(fabs(x)) to fabs(x).
339 
340  /// Transform trunc ([asz]ext x) to x or ([asz]ext x) or (trunc x).
342  std::pair<Register, unsigned> &MatchInfo);
344  std::pair<Register, unsigned> &MatchInfo);
345 
346  /// Transform trunc (shl x, K) to shl (trunc x),
347  /// K => K < VT.getScalarSizeInBits().
349  std::pair<Register, Register> &MatchInfo);
351  std::pair<Register, Register> &MatchInfo);
352 
353  /// Transform G_MUL(x, -1) to G_SUB(0, x)
355 
356  /// Return true if any explicit use operand on \p MI is defined by a
357  /// G_IMPLICIT_DEF.
359 
360  /// Return true if all register explicit use operands on \p MI are defined by
361  /// a G_IMPLICIT_DEF.
363 
364  /// Return true if a G_SHUFFLE_VECTOR instruction \p MI has an undef mask.
366 
367  /// Return true if a G_STORE instruction \p MI is storing an undef value.
369 
370  /// Return true if a G_SELECT instruction \p MI has an undef comparison.
372 
373  /// Return true if a G_SELECT instruction \p MI has a constant comparison. If
374  /// true, \p OpIdx will store the operand index of the known selected value.
375  bool matchConstantSelectCmp(MachineInstr &MI, unsigned &OpIdx);
376 
377  /// Replace an instruction with a G_FCONSTANT with value \p C.
378  bool replaceInstWithFConstant(MachineInstr &MI, double C);
379 
380  /// Replace an instruction with a G_CONSTANT with value \p C.
381  bool replaceInstWithConstant(MachineInstr &MI, int64_t C);
382 
383  /// Replace an instruction with a G_IMPLICIT_DEF.
385 
386  /// Delete \p MI and replace all of its uses with its \p OpIdx-th operand.
387  bool replaceSingleDefInstWithOperand(MachineInstr &MI, unsigned OpIdx);
388 
389  /// Delete \p MI and replace all of its uses with \p Replacement.
391 
392  /// Return true if \p MOP1 and \p MOP2 are register operands are defined by
393  /// equivalent instructions.
394  bool matchEqualDefs(const MachineOperand &MOP1, const MachineOperand &MOP2);
395 
396  /// Return true if \p MOP is defined by a G_CONSTANT with a value equal to
397  /// \p C.
398  bool matchConstantOp(const MachineOperand &MOP, int64_t C);
399 
400  /// Optimize (cond ? x : x) -> x
402 
403  /// Optimize (x op x) -> x
405 
406  /// Check if operand \p OpIdx is zero.
407  bool matchOperandIsZero(MachineInstr &MI, unsigned OpIdx);
408 
409  /// Check if operand \p OpIdx is undef.
410  bool matchOperandIsUndef(MachineInstr &MI, unsigned OpIdx);
411 
412  /// Check if operand \p OpIdx is known to be a power of 2.
413  bool matchOperandIsKnownToBeAPowerOfTwo(MachineInstr &MI, unsigned OpIdx);
414 
415  /// Erase \p MI
416  bool eraseInst(MachineInstr &MI);
417 
418  /// Return true if MI is a G_ADD which can be simplified to a G_SUB.
420  std::tuple<Register, Register> &MatchInfo);
422  std::tuple<Register, Register> &MatchInfo);
423 
424  /// Match (logic_op (op x...), (op y...)) -> (op (logic_op x, y))
425  bool
427  InstructionStepsMatchInfo &MatchInfo);
428 
429  /// Replace \p MI with a series of instructions described in \p MatchInfo.
431  InstructionStepsMatchInfo &MatchInfo);
432 
433  /// Match ashr (shl x, C), C -> sext_inreg (C)
435  std::tuple<Register, int64_t> &MatchInfo);
437  std::tuple<Register, int64_t> &MatchInfo);
438  /// \return true if \p MI is a G_AND instruction whose operands are x and y
439  /// where x & y == x or x & y == y. (E.g., one of operands is all-ones value.)
440  ///
441  /// \param [in] MI - The G_AND instruction.
442  /// \param [out] Replacement - A register the G_AND should be replaced with on
443  /// success.
444  bool matchRedundantAnd(MachineInstr &MI, Register &Replacement);
445 
446  /// \return true if \p MI is a G_OR instruction whose operands are x and y
447  /// where x | y == x or x | y == y. (E.g., one of operands is all-zeros
448  /// value.)
449  ///
450  /// \param [in] MI - The G_OR instruction.
451  /// \param [out] Replacement - A register the G_OR should be replaced with on
452  /// success.
453  bool matchRedundantOr(MachineInstr &MI, Register &Replacement);
454 
455  /// \return true if \p MI is a G_SEXT_INREG that can be erased.
457 
458  /// Combine inverting a result of a compare into the opposite cond code.
461 
462  /// Fold (xor (and x, y), y) -> (and (not x), y)
463  ///{
465  std::pair<Register, Register> &MatchInfo);
467  std::pair<Register, Register> &MatchInfo);
468  ///}
469 
470  /// Combine G_PTR_ADD with nullptr to G_INTTOPTR
473 
474  /// Combine G_UREM x, (known power of 2) to an add and bitmasking.
476 
478  SmallVectorImpl<Register> &MatchInfo);
479 
481  SmallVectorImpl<Register> &MatchInfo);
482 
483  /// Match expression trees of the form
484  ///
485  /// \code
486  /// sN *a = ...
487  /// sM val = a[0] | (a[1] << N) | (a[2] << 2N) | (a[3] << 3N) ...
488  /// \endcode
489  ///
490  /// And check if the tree can be replaced with a M-bit load + possibly a
491  /// bswap.
493  std::function<void(MachineIRBuilder &)> &MatchInfo);
494 
497 
500 
502  MachineInstr &MI,
503  SmallVectorImpl<std::pair<Register, MachineInstr *>> &MatchInfo);
505  MachineInstr &MI,
506  SmallVectorImpl<std::pair<Register, MachineInstr *>> &MatchInfo);
507 
508  /// Use a function which takes in a MachineIRBuilder to perform a combine.
510  std::function<void(MachineIRBuilder &)> &MatchInfo);
515 
516  /// Try to transform \p MI by using all of the above
517  /// combine functions. Returns true if changed.
518  bool tryCombine(MachineInstr &MI);
519 
520 private:
521  // Memcpy family optimization helpers.
522  bool optimizeMemcpy(MachineInstr &MI, Register Dst, Register Src,
523  unsigned KnownLen, Align DstAlign, Align SrcAlign,
524  bool IsVolatile);
525  bool optimizeMemmove(MachineInstr &MI, Register Dst, Register Src,
526  unsigned KnownLen, Align DstAlign, Align SrcAlign,
527  bool IsVolatile);
528  bool optimizeMemset(MachineInstr &MI, Register Dst, Register Val,
529  unsigned KnownLen, Align DstAlign, bool IsVolatile);
530 
531  /// Given a non-indexed load or store instruction \p MI, find an offset that
532  /// can be usefully and legally folded into it as a post-indexing operation.
533  ///
534  /// \returns true if a candidate is found.
535  bool findPostIndexCandidate(MachineInstr &MI, Register &Addr, Register &Base,
536  Register &Offset);
537 
538  /// Given a non-indexed load or store instruction \p MI, find an offset that
539  /// can be usefully and legally folded into it as a pre-indexing operation.
540  ///
541  /// \returns true if a candidate is found.
542  bool findPreIndexCandidate(MachineInstr &MI, Register &Addr, Register &Base,
543  Register &Offset);
544 
545  /// Helper function for matchLoadOrCombine. Searches for Registers
546  /// which may have been produced by a load instruction + some arithmetic.
547  ///
548  /// \param [in] Root - The search root.
549  ///
550  /// \returns The Registers found during the search.
552  findCandidatesForLoadOrCombine(const MachineInstr *Root) const;
553 
554  /// Helper function for matchLoadOrCombine.
555  ///
556  /// Checks if every register in \p RegsToVisit is defined by a load
557  /// instruction + some arithmetic.
558  ///
559  /// \param [out] MemOffset2Idx - Maps the byte positions each load ends up
560  /// at to the index of the load.
561  /// \param [in] MemSizeInBits - The number of bits each load should produce.
562  ///
563  /// \returns The lowest-index load found and the lowest index on success.
564  Optional<std::pair<MachineInstr *, int64_t>> findLoadOffsetsForLoadOrCombine(
565  SmallDenseMap<int64_t, int64_t, 8> &MemOffset2Idx,
566  const SmallVector<Register, 8> &RegsToVisit,
567  const unsigned MemSizeInBits);
568 };
569 } // namespace llvm
570 
571 #endif
llvm::CombinerHelper::matchCombineConstPtrAddToI2P
bool matchCombineConstPtrAddToI2P(MachineInstr &MI, int64_t &NewCst)
Definition: CombinerHelper.cpp:2348
llvm::CombinerHelper::matchCombineUnmergeWithDeadLanesToTrunc
bool matchCombineUnmergeWithDeadLanesToTrunc(MachineInstr &MI)
Transform X, Y<dead> = G_UNMERGE Z -> X = G_TRUNC Z.
Definition: CombinerHelper.cpp:2066
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Register Addr
Definition: CombinerHelper.h:47
llvm::CombinerHelper::applyAshShlToSextInreg
bool applyAshShlToSextInreg(MachineInstr &MI, std::tuple< Register, int64_t > &MatchInfo)
Definition: CombinerHelper.cpp:2977
LowLevelType.h
llvm::InstructionBuildSteps::Opcode
unsigned Opcode
Definition: CombinerHelper.h:73
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:100
llvm
Definition: AllocatorList.h:23
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::CombinerHelper::applyExtractVecEltBuildVec
void applyExtractVecEltBuildVec(MachineInstr &MI, Register &Reg)
Definition: CombinerHelper.cpp:3790
llvm::RegisterImmPair
Definition: CombinerHelper.h:58
UseMI
MachineInstrBuilder & UseMI
Definition: AArch64ExpandPseudoInsts.cpp:100
llvm::CombinerHelper::applyCombineI2PToP2I
bool applyCombineI2PToP2I(MachineInstr &MI, Register &Reg)
Definition: CombinerHelper.cpp:2279
llvm::CombinerHelper::matchCombineUnmergeConstant
bool matchCombineUnmergeConstant(MachineInstr &MI, SmallVectorImpl< APInt > &Csts)
Transform G_UNMERGE Constant -> Constant1, Constant2, ...
Definition: CombinerHelper.cpp:2024
llvm::CombinerHelper::MRI
MachineRegisterInfo & MRI
Definition: CombinerHelper.h:92
llvm::CombinerHelper::applyOptBrCondByInvertingCond
void applyOptBrCondByInvertingCond(MachineInstr &MI, MachineInstr *&BrCond)
Definition: CombinerHelper.cpp:1070
llvm::CombinerHelper::matchHoistLogicOpWithSameOpcodeHands
bool matchHoistLogicOpWithSameOpcodeHands(MachineInstr &MI, InstructionStepsMatchInfo &MatchInfo)
Match (logic_op (op x...), (op y...)) -> (op (logic_op x, y))
Definition: CombinerHelper.cpp:2853
llvm::GISelKnownBits
Definition: GISelKnownBits.h:29
llvm::CombinerHelper::applySimplifyURemByPow2
bool applySimplifyURemByPow2(MachineInstr &MI)
Combine G_UREM x, (known power of 2) to an add and bitmasking.
Definition: CombinerHelper.cpp:3289
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MachineInstr * Shift2
Definition: CombinerHelper.h:65
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
llvm::CombinerHelper::eraseInst
bool eraseInst(MachineInstr &MI)
Erase MI.
Definition: CombinerHelper.cpp:2600
llvm::CombinerHelper::applyCombineMulByNegativeOne
bool applyCombineMulByNegativeOne(MachineInstr &MI)
Transform G_MUL(x, -1) to G_SUB(0, x)
Definition: CombinerHelper.cpp:2455
llvm::IndexedLoadStoreMatchInfo::Base
Register Base
Definition: CombinerHelper.h:48
llvm::CombinerHelper::getKnownBits
GISelKnownBits * getKnownBits() const
Definition: CombinerHelper.h:104
llvm::CombinerHelper::matchCombineP2IToI2P
bool matchCombineP2IToI2P(MachineInstr &MI, Register &Reg)
Transform PtrToInt(IntToPtr(x)) to x.
Definition: CombinerHelper.cpp:2288
llvm::SmallVector< std::function< void(MachineInstrBuilder &)>, 4 >
llvm::CombinerHelper::getTargetLowering
const TargetLowering & getTargetLowering() const
Definition: CombinerHelper.cpp:52
llvm::InstructionBuildSteps::InstructionBuildSteps
InstructionBuildSteps(unsigned Opcode, const OperandBuildSteps &OperandFns)
Definition: CombinerHelper.h:76
llvm::CombinerHelper::applyCombineExtOfExt
bool applyCombineExtOfExt(MachineInstr &MI, std::tuple< Register, unsigned > &MatchInfo)
Definition: CombinerHelper.cpp:2421
llvm::CombinerHelper::tryCombineMemCpyFamily
bool tryCombineMemCpyFamily(MachineInstr &MI, unsigned MaxLen=0)
Optimize memcpy intrinsics et al, e.g.
Definition: CombinerHelper.cpp:1534
llvm::CombinerHelper::dominates
bool dominates(const MachineInstr &DefMI, const MachineInstr &UseMI)
Returns true if DefMI dominates UseMI.
Definition: CombinerHelper.cpp:641
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bool applyCombineAddP2IToPtrAdd(MachineInstr &MI, std::pair< Register, bool > &PtrRegAndCommute)
Definition: CombinerHelper.cpp:2328
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Definition: DenseMap.h:880
llvm::CombinerHelper::applyCombineUnmergeWithDeadLanesToTrunc
bool applyCombineUnmergeWithDeadLanesToTrunc(MachineInstr &MI)
Definition: CombinerHelper.cpp:2077
llvm::CombinerHelper::matchConstantSelectCmp
bool matchConstantSelectCmp(MachineInstr &MI, unsigned &OpIdx)
Return true if a G_SELECT instruction MI has a constant comparison.
Definition: CombinerHelper.cpp:2590
llvm::CombinerHelper::applyCombineTruncOfExt
bool applyCombineTruncOfExt(MachineInstr &MI, std::pair< Register, unsigned > &MatchInfo)
Definition: CombinerHelper.cpp:2495
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void applyFunnelShiftToRotate(MachineInstr &MI)
Definition: CombinerHelper.cpp:3884
llvm::CombinerHelper::tryCombineShuffleVector
bool tryCombineShuffleVector(MachineInstr &MI)
Try to combine G_SHUFFLE_VECTOR into G_CONCAT_VECTORS.
Definition: CombinerHelper.cpp:242
llvm::CombinerHelper::matchCombineDivRem
bool matchCombineDivRem(MachineInstr &MI, MachineInstr *&OtherMI)
Try to combine G_[SU]DIV and G_[SU]REM into a single G_[SU]DIVREM when their source operands are iden...
Definition: CombinerHelper.cpp:949
llvm::CombinerHelper::tryCombineIndexedLoadStore
bool tryCombineIndexedLoadStore(MachineInstr &MI)
Combine MI into a pre-indexed or post-indexed load/store operation if legal and the surrounding code ...
Definition: CombinerHelper.cpp:877
DenseMap.h
llvm::InstructionStepsMatchInfo
Definition: CombinerHelper.h:80
llvm::Optional
Definition: APInt.h:33
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
llvm::CombinerHelper::tryCombineShiftToUnmerge
bool tryCombineShiftToUnmerge(MachineInstr &MI, unsigned TargetShiftAmount)
Definition: CombinerHelper.cpp:2259
llvm::CombinerHelper::matchSextTruncSextLoad
bool matchSextTruncSextLoad(MachineInstr &MI)
Definition: CombinerHelper.cpp:653
llvm::CombinerHelper::matchPtrAddZero
bool matchPtrAddZero(MachineInstr &MI)
}
Definition: CombinerHelper.cpp:3262
llvm::CombinerHelper::tryCombineExtendingLoads
bool tryCombineExtendingLoads(MachineInstr &MI)
If MI is extend that consumes the result of a load, try to combine it.
Definition: CombinerHelper.cpp:427
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int64_t Imm
Definition: CombinerHelper.h:54
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Definition: CombinerHelper.cpp:1646
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Definition: CombinerHelper.cpp:151
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Transform G_ADD (G_PTRTOINT x), y -> G_PTRTOINT (G_PTR_ADD x, y) Transform G_ADD y,...
Definition: CombinerHelper.cpp:2303
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Definition: CombinerHelper.h:53
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Definition: CombinerHelper.cpp:2000
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Match ashr (shl x, C), C -> sext_inreg (C)
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Definition: CombinerHelper.h:72
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Definition: CombinerHelper.h:55
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Definition: CombinerHelper.cpp:3183
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Definition: CombinerHelper.h:60
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Match expression trees of the form.
Definition: CombinerHelper.cpp:3537
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bool applyCombineShiftToUnmerge(MachineInstr &MI, const unsigned &ShiftVal)
Definition: CombinerHelper.cpp:2185
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OperandBuildSteps OperandFns
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Definition: CombinerHelper.h:74
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MachineDominatorTree * MDT
Definition: CombinerHelper.h:95
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Check if the G_CONCAT_VECTORS MI is undef or if it can be flattened into a build_vector.
Definition: CombinerHelper.cpp:175
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Definition: CombinerHelper.cpp:3091
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Definition: CombinerHelper.h:63
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Definition: README_ALTIVEC.txt:86
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This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Definition: TargetLowering.h:3143
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Definition: CombinerHelper.h:84
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bool matchAnyExplicitUseIsUndef(MachineInstr &MI)
Return true if any explicit use operand on MI is defined by a G_IMPLICIT_DEF.
Definition: CombinerHelper.cpp:2558
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static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
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MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
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LLT Ty
Definition: CombinerHelper.h:41
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bool matchCombineI2PToP2I(MachineInstr &MI, Register &Reg)
Transform IntToPtr(PtrToInt(x)) to x if cast is in the same address space.
Definition: CombinerHelper.cpp:2270
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bool applyCombineShlOfExtend(MachineInstr &MI, const RegisterImmPair &MatchData)
Definition: CombinerHelper.cpp:1950
APFloat.h
This file declares a class to represent arbitrary precision floating point values and provide a varie...
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bool matchCombineFNegOfFNeg(MachineInstr &MI, Register &Reg)
Transform fneg(fneg(x)) to x.
Definition: CombinerHelper.cpp:2468
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bool applyExtendThroughPhis(MachineInstr &MI, MachineInstr *&ExtMI)
Definition: CombinerHelper.cpp:3706
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Definition: CombinerHelper.h:89
llvm::CombinerHelper::applyCombineConcatVectors
void applyCombineConcatVectors(MachineInstr &MI, bool IsUndef, const ArrayRef< Register > Ops)
Replace MI with a flattened build_vector with Ops or an implicit_def if IsUndef is true.
Definition: CombinerHelper.cpp:220
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bool applyCombineMulToShl(MachineInstr &MI, unsigned &ShiftVal)
Definition: CombinerHelper.cpp:1899
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Check if the G_SHUFFLE_VECTOR MI can be replaced by a concat_vectors.
Definition: CombinerHelper.cpp:251
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This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
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If MI is COPY, try to combine it.
Definition: CombinerHelper.cpp:144
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GISelChangeObserver & Observer
Definition: CombinerHelper.h:93
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bool matchCombineUnmergeZExtToZExt(MachineInstr &MI)
Transform X, Y = G_UNMERGE(G_ZEXT(Z)) -> X = G_ZEXT(Z); Y = G_CONSTANT 0.
Definition: CombinerHelper.cpp:2099
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Return true if a G_SHUFFLE_VECTOR instruction MI has an undef mask.
Definition: CombinerHelper.cpp:2572
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bool applyXorOfAndWithSameReg(MachineInstr &MI, std::pair< Register, Register > &MatchInfo)
Definition: CombinerHelper.cpp:3247
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Definition: CombinerHelper.h:94
Operands
mir Rename Register Operands
Definition: MIRNamerPass.cpp:78
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InstructionStepsMatchInfo()=default
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Register Offset
Definition: CombinerHelper.h:49
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bool applyCombineConstPtrAddToI2P(MachineInstr &MI, int64_t &NewCst)
Definition: CombinerHelper.cpp:2366
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Definition: CombinerHelper.cpp:679
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Definition: CombinerHelper.cpp:2990
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If MI is G_CONCAT_VECTORS, try to combine it.
Definition: CombinerHelper.cpp:165
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bool applyCombineAnyExtTrunc(MachineInstr &MI, Register &Reg)
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Return true if a G_STORE instruction MI is storing an undef value.
Definition: CombinerHelper.cpp:2578
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Helper class to build MachineInstr.
Definition: MachineIRBuilder.h:220
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Representation of each machine instruction.
Definition: MachineInstr.h:64
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Definition: MachineInstrBuilder.h:69
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bool matchUndefSelectCmp(MachineInstr &MI)
Return true if a G_SELECT instruction MI has an undef comparison.
Definition: CombinerHelper.cpp:2584
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uint64_t Addr
Definition: ELFObjHandler.cpp:80
llvm::CombinerHelper::applyShiftImmedChain
bool applyShiftImmedChain(MachineInstr &MI, RegisterImmPair &MatchInfo)
Definition: CombinerHelper.cpp:1737
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void applyRotateOutOfRange(MachineInstr &MI)
Definition: CombinerHelper.cpp:3911
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Register LogicNonShiftReg
Definition: CombinerHelper.h:66
llvm::CombinerHelper::Builder
MachineIRBuilder & Builder
Definition: CombinerHelper.h:91
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bool matchCombineIndexedLoadStore(MachineInstr &MI, IndexedLoadStoreMatchInfo &MatchInfo)
Definition: CombinerHelper.cpp:886
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bool matchCombineConstantFoldFpUnary(MachineInstr &MI, Optional< APFloat > &Cst)
Transform fp_instr(cst) to constant result of the fp operation.
Definition: CombinerHelper.cpp:1625
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bool matchCombineShlOfExtend(MachineInstr &MI, RegisterImmPair &MatchData)
Definition: CombinerHelper.cpp:1913
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bool matchConstantOp(const MachineOperand &MOP, int64_t C)
Return true if MOP is defined by a G_CONSTANT with a value equal to C.
Definition: CombinerHelper.cpp:2677
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bool matchEqualDefs(const MachineOperand &MOP1, const MachineOperand &MOP2)
Return true if MOP1 and MOP2 are register operands are defined by equivalent instructions.
Definition: CombinerHelper.cpp:2605
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bool replaceSingleDefInstWithOperand(MachineInstr &MI, unsigned OpIdx)
Delete MI and replace all of its uses with its OpIdx-th operand.
Definition: CombinerHelper.cpp:2685
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Transform trunc ([asz]ext x) to x or ([asz]ext x) or (trunc x).
Definition: CombinerHelper.cpp:2481
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bool matchCombineMulToShl(MachineInstr &MI, unsigned &ShiftVal)
Transform a multiply by a power-of-2 value to a left shift.
Definition: CombinerHelper.cpp:1887
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unsigned ExtendOpcode
Definition: CombinerHelper.h:42
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Definition: CombinerHelper.cpp:1852
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Definition: MemDepPrinter.cpp:83
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Definition: CombinerHelper.cpp:116
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Replace an instruction with a G_IMPLICIT_DEF.
Definition: CombinerHelper.cpp:2754
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Definition: CombinerHelper.cpp:2782
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bool applyCombineUnmergeConstant(MachineInstr &MI, SmallVectorImpl< APInt > &Csts)
Definition: CombinerHelper.cpp:2049
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Definition: CombinerHelper.h:50
llvm::LegalityQuery
The LegalityQuery object bundles together all the information that's needed to decide whether a given...
Definition: LegalizerInfo.h:124
llvm::CombinerHelper::isPredecessor
bool isPredecessor(const MachineInstr &DefMI, const MachineInstr &UseMI)
Returns true if DefMI precedes UseMI or they are the same instruction.
Definition: CombinerHelper.cpp:625
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bool matchXorOfAndWithSameReg(MachineInstr &MI, std::pair< Register, Register > &MatchInfo)
Fold (xor (and x, y), y) -> (and (not x), y) {.
Definition: CombinerHelper.cpp:3216
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SmallVector< InstructionBuildSteps, 2 > InstrsToBuild
Describes instructions to be built during a combine.
Definition: CombinerHelper.h:82
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::CombinerHelper::applyBuildInstructionSteps
bool applyBuildInstructionSteps(MachineInstr &MI, InstructionStepsMatchInfo &MatchInfo)
Replace MI with a series of instructions described in MatchInfo.
Definition: CombinerHelper.cpp:2944
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bool applySextInRegOfLoad(MachineInstr &MI, std::tuple< Register, unsigned > &MatchInfo)
Definition: CombinerHelper.cpp:722
llvm::CombinerHelper::matchCombineExtOfExt
bool matchCombineExtOfExt(MachineInstr &MI, std::tuple< Register, unsigned > &MatchInfo)
Transform [asz]ext([asz]ext(x)) to [asz]ext x.
Definition: CombinerHelper.cpp:2400
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void replaceRegOpWith(MachineRegisterInfo &MRI, MachineOperand &FromRegOp, Register ToReg) const
Replace a single register operand with a new register and inform the observer of the changes.
Definition: CombinerHelper.cpp:133
llvm::CombinerHelper::matchBinOpSameVal
bool matchBinOpSameVal(MachineInstr &MI)
Optimize (x op x) -> x.
Definition: CombinerHelper.cpp:2714
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bool applyCombineP2IToI2P(MachineInstr &MI, Register &Reg)
Definition: CombinerHelper.cpp:2294
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constexpr char IsVolatile[]
Key for Kernel::Arg::Metadata::mIsVolatile.
Definition: AMDGPUMetadata.h:194
llvm::CombinerHelper::applyCombineExtendingLoads
void applyCombineExtendingLoads(MachineInstr &MI, PreferredTuple &MatchInfo)
Definition: CombinerHelper.cpp:515
llvm::GISelChangeObserver
Abstract class that contains various methods for clients to notify about changes.
Definition: GISelChangeObserver.h:29
llvm::CombinerHelper::matchSelectSameVal
bool matchSelectSameVal(MachineInstr &MI)
Optimize (cond ? x : x) -> x.
Definition: CombinerHelper.cpp:2706
llvm::CombinerHelper::matchOperandIsUndef
bool matchOperandIsUndef(MachineInstr &MI, unsigned OpIdx)
Check if operand OpIdx is undef.
Definition: CombinerHelper.cpp:2726
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Definition: CombinerHelper.cpp:3280
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::CombinerHelper::applySimplifyAddToSub
bool applySimplifyAddToSub(MachineInstr &MI, std::tuple< Register, Register > &MatchInfo)
Definition: CombinerHelper.cpp:2843
llvm::CombinerHelper::matchShiftOfShiftedLogic
bool matchShiftOfShiftedLogic(MachineInstr &MI, ShiftOfShiftedLogic &MatchInfo)
If we have a shift-by-constant of a bitwise logic op that itself has a shift-by-constant operand with...
Definition: CombinerHelper.cpp:1771
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bool matchCombineFAbsOfFAbs(MachineInstr &MI, Register &Src)
Match fabs(fabs(x)) to fabs(x).
Definition: CombinerHelper.cpp:2474
llvm::CombinerHelper::matchCombineAnyExtTrunc
bool matchCombineAnyExtTrunc(MachineInstr &MI, Register &Reg)
Transform anyext(trunc(x)) to x.
Definition: CombinerHelper.cpp:2377
llvm::CombinerHelper::applyPtrAddImmedChain
bool applyPtrAddImmedChain(MachineInstr &MI, PtrAddChain &MatchInfo)
Definition: CombinerHelper.cpp:1679
Alignment.h
llvm::CombinerHelper::CombinerHelper
CombinerHelper(GISelChangeObserver &Observer, MachineIRBuilder &B, GISelKnownBits *KB=nullptr, MachineDominatorTree *MDT=nullptr, const LegalizerInfo *LI=nullptr)
Definition: CombinerHelper.cpp:43
llvm::CombinerHelper::applyCombineUnmergeZExtToZExt
bool applyCombineUnmergeZExtToZExt(MachineInstr &MI)
Definition: CombinerHelper.cpp:2125
llvm::CombinerHelper::matchOperandIsKnownToBeAPowerOfTwo
bool matchOperandIsKnownToBeAPowerOfTwo(MachineInstr &MI, unsigned OpIdx)
Check if operand OpIdx is known to be a power of 2.
Definition: CombinerHelper.cpp:2732
llvm::CombinerHelper::matchSextInRegOfLoad
bool matchSextInRegOfLoad(MachineInstr &MI, std::tuple< Register, unsigned > &MatchInfo)
Match sext_inreg(load p), imm -> sextload p.
Definition: CombinerHelper.cpp:687
llvm::CombinerHelper::matchFunnelShiftToRotate
bool matchFunnelShiftToRotate(MachineInstr &MI)
Match an FSHL or FSHR that can be combined to a ROTR or ROTL rotate.
Definition: CombinerHelper.cpp:3872
llvm::CombinerHelper::matchSimplifyAddToSub
bool matchSimplifyAddToSub(MachineInstr &MI, std::tuple< Register, Register > &MatchInfo)
Return true if MI is a G_ADD which can be simplified to a G_SUB.
Definition: CombinerHelper.cpp:2762
llvm::CombinerHelper::applyCombineTruncOfShl
bool applyCombineTruncOfShl(MachineInstr &MI, std::pair< Register, Register > &MatchInfo)
Definition: CombinerHelper.cpp:2541
llvm::CombinerHelper::LI
const LegalizerInfo * LI
Definition: CombinerHelper.h:96
llvm::CombinerHelper::matchShiftImmedChain
bool matchShiftImmedChain(MachineInstr &MI, RegisterImmPair &MatchInfo)
Fold (shift (shift base, x), y) -> (shift base (x+y))
Definition: CombinerHelper.cpp:1692
llvm::PreferredTuple::MI
MachineInstr * MI
Definition: CombinerHelper.h:43
llvm::RegisterImmPair::Reg
Register Reg
Definition: CombinerHelper.h:59
llvm::IndexedLoadStoreMatchInfo
Definition: CombinerHelper.h:46
llvm::CombinerHelper::matchExtendThroughPhis
bool matchExtendThroughPhis(MachineInstr &MI, MachineInstr *&ExtMI)
Definition: CombinerHelper.cpp:3651
llvm::CombinerHelper::matchCombineShiftToUnmerge
bool matchCombineShiftToUnmerge(MachineInstr &MI, unsigned TargetShiftSize, unsigned &ShiftVal)
Reduce a shift by a constant to an unmerge and a shift on a half sized type.
Definition: CombinerHelper.cpp:2160
llvm::CombinerHelper::applyCombineCopy
void applyCombineCopy(MachineInstr &MI)
Definition: CombinerHelper.cpp:158
llvm::CombinerHelper::tryCombine
bool tryCombine(MachineInstr &MI)
Try to transform MI by using all of the above combine functions.
Definition: CombinerHelper.cpp:3926
llvm::InstructionBuildSteps::InstructionBuildSteps
InstructionBuildSteps()=default
Operands to be added to the instruction.
DefMI
MachineInstrBuilder MachineInstrBuilder & DefMI
Definition: AArch64ExpandPseudoInsts.cpp:101
llvm::CombinerHelper::applyCombineDivRem
void applyCombineDivRem(MachineInstr &MI, MachineInstr *&OtherMI)
Definition: CombinerHelper.cpp:1011
llvm::CombinerHelper::replaceInstWithConstant
bool replaceInstWithConstant(MachineInstr &MI, int64_t C)
Replace an instruction with a G_CONSTANT with value C.
Definition: CombinerHelper.cpp:2746
llvm::CombinerHelper::matchCombineUnmergeMergeToPlainValues
bool matchCombineUnmergeMergeToPlainValues(MachineInstr &MI, SmallVectorImpl< Register > &Operands)
Transform <ty,...> G_UNMERGE(G_MERGE ty X, Y, Z) -> ty X, Y, Z.
Definition: CombinerHelper.cpp:1973
llvm::ShiftOfShiftedLogic::ValSum
uint64_t ValSum
Definition: CombinerHelper.h:67
llvm::CombinerHelper::applyExtractAllEltsFromBuildVector
void applyExtractAllEltsFromBuildVector(MachineInstr &MI, SmallVectorImpl< std::pair< Register, MachineInstr * >> &MatchInfo)
Definition: CombinerHelper.cpp:3851
llvm::CombinerHelper::matchOperandIsZero
bool matchOperandIsZero(MachineInstr &MI, unsigned OpIdx)
Check if operand OpIdx is zero.
Definition: CombinerHelper.cpp:2720
llvm::PreferredTuple
Definition: CombinerHelper.h:40
llvm::CombinerHelper::matchCombineExtendingLoads
bool matchCombineExtendingLoads(MachineInstr &MI, PreferredTuple &MatchInfo)
Definition: CombinerHelper.cpp:436
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
llvm::LegalizerInfo
Definition: LegalizerInfo.h:1041
llvm::CombinerHelper::applyCombineFAbsOfFAbs
bool applyCombineFAbsOfFAbs(MachineInstr &MI, Register &Src)
Register.h
llvm::CombinerHelper::matchAllExplicitUsesAreUndef
bool matchAllExplicitUsesAreUndef(MachineInstr &MI)
Return true if all register explicit use operands on MI are defined by a G_IMPLICIT_DEF.
Definition: CombinerHelper.cpp:2565
llvm::CombinerHelper::replaceSingleDefInstWithReg
bool replaceSingleDefInstWithReg(MachineInstr &MI, Register Replacement)
Delete MI and replace all of its uses with Replacement.
Definition: CombinerHelper.cpp:2696
llvm::CombinerHelper::matchExtractAllEltsFromBuildVector
bool matchExtractAllEltsFromBuildVector(MachineInstr &MI, SmallVectorImpl< std::pair< Register, MachineInstr * >> &MatchInfo)
Definition: CombinerHelper.cpp:3808
llvm::ShiftOfShiftedLogic::Logic
MachineInstr * Logic
Definition: CombinerHelper.h:64
llvm::CombinerHelper::applyCombineIndexedLoadStore
void applyCombineIndexedLoadStore(MachineInstr &MI, IndexedLoadStoreMatchInfo &MatchInfo)
Definition: CombinerHelper.cpp:907
llvm::CombinerHelper::matchRedundantOr
bool matchRedundantOr(MachineInstr &MI, Register &Replacement)
Definition: CombinerHelper.cpp:3045
llvm::MachineDominatorTree
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
Definition: MachineDominators.h:45
llvm::CombinerHelper::matchCombineTruncOfShl
bool matchCombineTruncOfShl(MachineInstr &MI, std::pair< Register, Register > &MatchInfo)
Transform trunc (shl x, K) to shl (trunc x), K => K < VT.getScalarSizeInBits().
Definition: CombinerHelper.cpp:2517
llvm::CombinerHelper::matchOptBrCondByInvertingCond
bool matchOptBrCondByInvertingCond(MachineInstr &MI, MachineInstr *&BrCond)
If a brcond's true block is not the fallthrough, make it so by inverting the condition and swapping o...
Definition: CombinerHelper.cpp:1036
llvm::CombinerHelper::applyCombineInsertVecElts
bool applyCombineInsertVecElts(MachineInstr &MI, SmallVectorImpl< Register > &MatchInfo)
Definition: CombinerHelper.cpp:2823
llvm::CombinerHelper::matchExtractVecEltBuildVec
bool matchExtractVecEltBuildVec(MachineInstr &MI, Register &Reg)
Definition: CombinerHelper.cpp:3753
llvm::CombinerHelper::replaceRegWith
void replaceRegWith(MachineRegisterInfo &MRI, Register FromReg, Register ToReg) const
MachineRegisterInfo::replaceRegWith() and inform the observer of the changes.
Definition: CombinerHelper.cpp:121
llvm::CombinerHelper::replaceInstWithFConstant
bool replaceInstWithFConstant(MachineInstr &MI, double C)
Replace an instruction with a G_FCONSTANT with value C.
Definition: CombinerHelper.cpp:2738
llvm::CombinerHelper::applyCombineConstantFoldFpUnary
bool applyCombineConstantFoldFpUnary(MachineInstr &MI, Optional< APFloat > &Cst)
Definition: CombinerHelper.cpp:1634
llvm::CombinerHelper::applyCombineShuffleVector
void applyCombineShuffleVector(MachineInstr &MI, const ArrayRef< Register > Ops)
Replace MI with a concat_vectors with Ops.
Definition: CombinerHelper.cpp:327
llvm::LLT
Definition: LowLevelTypeImpl.h:40