LLVM 17.0.0git
CombinerHelper.h
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1//===-- llvm/CodeGen/GlobalISel/CombinerHelper.h --------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===--------------------------------------------------------------------===//
8/// \file
9/// This contains common combine transformations that may be used in a combine
10/// pass,or by the target elsewhere.
11/// Targets can pick individual opcode transformations from the helper or use
12/// tryCombine which invokes all transformations. All of the transformations
13/// return true if the MachineInstruction changed and false otherwise.
14///
15//===--------------------------------------------------------------------===//
16
17#ifndef LLVM_CODEGEN_GLOBALISEL_COMBINERHELPER_H
18#define LLVM_CODEGEN_GLOBALISEL_COMBINERHELPER_H
19
20#include "llvm/ADT/DenseMap.h"
24#include "llvm/IR/InstrTypes.h"
25#include <functional>
26
27namespace llvm {
28
29class GISelChangeObserver;
30class APFloat;
31class APInt;
32class ConstantFP;
33class GPtrAdd;
34class GStore;
35class GZExtLoad;
36class MachineIRBuilder;
37class MachineInstrBuilder;
38class MachineRegisterInfo;
39class MachineInstr;
40class MachineOperand;
41class GISelKnownBits;
42class MachineDominatorTree;
43class LegalizerInfo;
44struct LegalityQuery;
45class RegisterBank;
46class RegisterBankInfo;
47class TargetLowering;
48class TargetRegisterInfo;
49
51 LLT Ty; // The result type of the extend.
52 unsigned ExtendOpcode; // G_ANYEXT/G_SEXT/G_ZEXT
54};
55
60 bool IsPre;
61};
62
64 int64_t Imm;
67};
68
71 int64_t Imm;
72};
73
79};
80
81using BuildFnTy = std::function<void(MachineIRBuilder &)>;
82
84 SmallVector<std::function<void(MachineInstrBuilder &)>, 4>;
86 unsigned Opcode = 0; /// The opcode for the produced instruction.
87 OperandBuildSteps OperandFns; /// Operands to be added to the instruction.
91};
92
94 /// Describes instructions to be built during a combine.
98 std::initializer_list<InstructionBuildSteps> InstrsToBuild)
100};
101
103protected:
113
114public:
116 bool IsPreLegalize,
117 GISelKnownBits *KB = nullptr,
118 MachineDominatorTree *MDT = nullptr,
119 const LegalizerInfo *LI = nullptr);
120
122 return KB;
123 }
124
126 return Builder;
127 }
128
129 const TargetLowering &getTargetLowering() const;
130
131 /// \returns true if the combiner is running pre-legalization.
132 bool isPreLegalize() const;
133
134 /// \returns true if \p Query is legal on the target.
135 bool isLegal(const LegalityQuery &Query) const;
136
137 /// \return true if the combine is running prior to legalization, or if \p
138 /// Query is legal on the target.
139 bool isLegalOrBeforeLegalizer(const LegalityQuery &Query) const;
140
141 /// \return true if the combine is running prior to legalization, or if \p Ty
142 /// is a legal integer constant type on the target.
143 bool isConstantLegalOrBeforeLegalizer(const LLT Ty) const;
144
145 /// MachineRegisterInfo::replaceRegWith() and inform the observer of the changes
146 void replaceRegWith(MachineRegisterInfo &MRI, Register FromReg, Register ToReg) const;
147
148 /// Replace a single register operand with a new register and inform the
149 /// observer of the changes.
151 Register ToReg) const;
152
153 /// Replace the opcode in instruction with a new opcode and inform the
154 /// observer of the changes.
155 void replaceOpcodeWith(MachineInstr &FromMI, unsigned ToOpcode) const;
156
157 /// Get the register bank of \p Reg.
158 /// If Reg has not been assigned a register, a register class,
159 /// or a register bank, then this returns nullptr.
160 ///
161 /// \pre Reg.isValid()
162 const RegisterBank *getRegBank(Register Reg) const;
163
164 /// Set the register bank of \p Reg.
165 /// Does nothing if the RegBank is null.
166 /// This is the counterpart to getRegBank.
167 void setRegBank(Register Reg, const RegisterBank *RegBank);
168
169 /// If \p MI is COPY, try to combine it.
170 /// Returns true if MI changed.
174
175 /// Returns true if \p DefMI precedes \p UseMI or they are the same
176 /// instruction. Both must be in the same basic block.
178
179 /// Returns true if \p DefMI dominates \p UseMI. By definition an
180 /// instruction dominates itself.
181 ///
182 /// If we haven't been provided with a MachineDominatorTree during
183 /// construction, this function returns a conservative result that tracks just
184 /// a single basic block.
185 bool dominates(const MachineInstr &DefMI, const MachineInstr &UseMI);
186
187 /// If \p MI is extend that consumes the result of a load, try to combine it.
188 /// Returns true if MI changed.
192
193 /// Match (and (load x), mask) -> zextload x
195
196 /// Combine \p MI into a pre-indexed or post-indexed load/store operation if
197 /// legal and the surrounding code makes it useful.
201
204
205 /// Match sext_inreg(load p), imm -> sextload p
206 bool matchSextInRegOfLoad(MachineInstr &MI, std::tuple<Register, unsigned> &MatchInfo);
207 void applySextInRegOfLoad(MachineInstr &MI, std::tuple<Register, unsigned> &MatchInfo);
208
209 /// Try to combine G_[SU]DIV and G_[SU]REM into a single G_[SU]DIVREM
210 /// when their source operands are identical.
213
214 /// If a brcond's true block is not the fallthrough, make it so by inverting
215 /// the condition and swapping operands.
218
219 /// If \p MI is G_CONCAT_VECTORS, try to combine it.
220 /// Returns true if MI changed.
221 /// Right now, we support:
222 /// - concat_vector(undef, undef) => undef
223 /// - concat_vector(build_vector(A, B), build_vector(C, D)) =>
224 /// build_vector(A, B, C, D)
225 ///
226 /// \pre MI.getOpcode() == G_CONCAT_VECTORS.
228 /// Check if the G_CONCAT_VECTORS \p MI is undef or if it
229 /// can be flattened into a build_vector.
230 /// In the first case \p IsUndef will be true.
231 /// In the second case \p Ops will contain the operands needed
232 /// to produce the flattened build_vector.
233 ///
234 /// \pre MI.getOpcode() == G_CONCAT_VECTORS.
235 bool matchCombineConcatVectors(MachineInstr &MI, bool &IsUndef,
237 /// Replace \p MI with a flattened build_vector with \p Ops or an
238 /// implicit_def if IsUndef is true.
239 void applyCombineConcatVectors(MachineInstr &MI, bool IsUndef,
240 const ArrayRef<Register> Ops);
241
242 /// Try to combine G_SHUFFLE_VECTOR into G_CONCAT_VECTORS.
243 /// Returns true if MI changed.
244 ///
245 /// \pre MI.getOpcode() == G_SHUFFLE_VECTOR.
247 /// Check if the G_SHUFFLE_VECTOR \p MI can be replaced by a
248 /// concat_vectors.
249 /// \p Ops will contain the operands needed to produce the flattened
250 /// concat_vectors.
251 ///
252 /// \pre MI.getOpcode() == G_SHUFFLE_VECTOR.
255 /// Replace \p MI with a concat_vectors with \p Ops.
257 const ArrayRef<Register> Ops);
258
259 /// Optimize memcpy intrinsics et al, e.g. constant len calls.
260 /// /p MaxLen if non-zero specifies the max length of a mem libcall to inline.
261 ///
262 /// For example (pre-indexed):
263 ///
264 /// $addr = G_PTR_ADD $base, $offset
265 /// [...]
266 /// $val = G_LOAD $addr
267 /// [...]
268 /// $whatever = COPY $addr
269 ///
270 /// -->
271 ///
272 /// $val, $addr = G_INDEXED_LOAD $base, $offset, 1 (IsPre)
273 /// [...]
274 /// $whatever = COPY $addr
275 ///
276 /// or (post-indexed):
277 ///
278 /// G_STORE $val, $base
279 /// [...]
280 /// $addr = G_PTR_ADD $base, $offset
281 /// [...]
282 /// $whatever = COPY $addr
283 ///
284 /// -->
285 ///
286 /// $addr = G_INDEXED_STORE $val, $base, $offset
287 /// [...]
288 /// $whatever = COPY $addr
289 bool tryCombineMemCpyFamily(MachineInstr &MI, unsigned MaxLen = 0);
290
293
294 /// Fold (shift (shift base, x), y) -> (shift base (x+y))
297
298 /// If we have a shift-by-constant of a bitwise logic op that itself has a
299 /// shift-by-constant operand with identical opcode, we may be able to convert
300 /// that into 2 independent shifts followed by the logic op.
302 ShiftOfShiftedLogic &MatchInfo);
304 ShiftOfShiftedLogic &MatchInfo);
305
306 bool matchCommuteShift(MachineInstr &MI, BuildFnTy &MatchInfo);
307
308 /// Transform a multiply by a power-of-2 value to a left shift.
309 bool matchCombineMulToShl(MachineInstr &MI, unsigned &ShiftVal);
310 void applyCombineMulToShl(MachineInstr &MI, unsigned &ShiftVal);
311
312 // Transform a G_SHL with an extended source into a narrower shift if
313 // possible.
316 const RegisterImmPair &MatchData);
317
318 /// Fold away a merge of an unmerge of the corresponding values.
320
321 /// Reduce a shift by a constant to an unmerge and a shift on a half sized
322 /// type. This will not produce a shift smaller than \p TargetShiftSize.
323 bool matchCombineShiftToUnmerge(MachineInstr &MI, unsigned TargetShiftSize,
324 unsigned &ShiftVal);
325 void applyCombineShiftToUnmerge(MachineInstr &MI, const unsigned &ShiftVal);
326 bool tryCombineShiftToUnmerge(MachineInstr &MI, unsigned TargetShiftAmount);
327
328 /// Transform <ty,...> G_UNMERGE(G_MERGE ty X, Y, Z) -> ty X, Y, Z.
329 bool
332 void
335
336 /// Transform G_UNMERGE Constant -> Constant1, Constant2, ...
341
342 /// Transform G_UNMERGE G_IMPLICIT_DEF -> G_IMPLICIT_DEF, G_IMPLICIT_DEF, ...
343 bool
345 std::function<void(MachineIRBuilder &)> &MatchInfo);
346
347 /// Transform X, Y<dead> = G_UNMERGE Z -> X = G_TRUNC Z.
350
351 /// Transform X, Y = G_UNMERGE(G_ZEXT(Z)) -> X = G_ZEXT(Z); Y = G_CONSTANT 0
354
355 /// Transform fp_instr(cst) to constant result of the fp operation.
357
358 /// Transform IntToPtr(PtrToInt(x)) to x if cast is in the same address space.
361
362 /// Transform PtrToInt(IntToPtr(x)) to x.
364
365 /// Transform G_ADD (G_PTRTOINT x), y -> G_PTRTOINT (G_PTR_ADD x, y)
366 /// Transform G_ADD y, (G_PTRTOINT x) -> G_PTRTOINT (G_PTR_ADD x, y)
368 std::pair<Register, bool> &PtrRegAndCommute);
370 std::pair<Register, bool> &PtrRegAndCommute);
371
372 // Transform G_PTR_ADD (G_PTRTOINT C1), C2 -> C1 + C2
375
376 /// Transform anyext(trunc(x)) to x.
379
380 /// Transform zext(trunc(x)) to x.
382
383 /// Transform [asz]ext([asz]ext(x)) to [asz]ext x.
385 std::tuple<Register, unsigned> &MatchInfo);
387 std::tuple<Register, unsigned> &MatchInfo);
388
389 /// Transform fabs(fabs(x)) to fabs(x).
391
392 /// Transform fabs(fneg(x)) to fabs(x).
394
395 /// Transform trunc ([asz]ext x) to x or ([asz]ext x) or (trunc x).
397 std::pair<Register, unsigned> &MatchInfo);
399 std::pair<Register, unsigned> &MatchInfo);
400
401 /// Transform trunc (shl x, K) to shl (trunc x), K
402 /// if K < VT.getScalarSizeInBits().
403 ///
404 /// Transforms trunc ([al]shr x, K) to (trunc ([al]shr (MidVT (trunc x)), K))
405 /// if K <= (MidVT.getScalarSizeInBits() - VT.getScalarSizeInBits())
406 /// MidVT is obtained by finding a legal type between the trunc's src and dst
407 /// types.
409 std::pair<MachineInstr *, LLT> &MatchInfo);
411 std::pair<MachineInstr *, LLT> &MatchInfo);
412
413 /// Transform G_MUL(x, -1) to G_SUB(0, x)
415
416 /// Return true if any explicit use operand on \p MI is defined by a
417 /// G_IMPLICIT_DEF.
419
420 /// Return true if all register explicit use operands on \p MI are defined by
421 /// a G_IMPLICIT_DEF.
423
424 /// Return true if a G_SHUFFLE_VECTOR instruction \p MI has an undef mask.
426
427 /// Return true if a G_STORE instruction \p MI is storing an undef value.
429
430 /// Return true if a G_SELECT instruction \p MI has an undef comparison.
432
433 /// Return true if a G_{EXTRACT,INSERT}_VECTOR_ELT has an out of range index.
435
436 /// Return true if a G_SELECT instruction \p MI has a constant comparison. If
437 /// true, \p OpIdx will store the operand index of the known selected value.
438 bool matchConstantSelectCmp(MachineInstr &MI, unsigned &OpIdx);
439
440 /// Replace an instruction with a G_FCONSTANT with value \p C.
442
443 /// Replace an instruction with a G_CONSTANT with value \p C.
445
446 /// Replace an instruction with a G_CONSTANT with value \p C.
448
449 /// Replace an instruction with a G_IMPLICIT_DEF.
451
452 /// Delete \p MI and replace all of its uses with its \p OpIdx-th operand.
453 bool replaceSingleDefInstWithOperand(MachineInstr &MI, unsigned OpIdx);
454
455 /// Delete \p MI and replace all of its uses with \p Replacement.
457
458 /// Return true if \p MOP1 and \p MOP2 are register operands are defined by
459 /// equivalent instructions.
460 bool matchEqualDefs(const MachineOperand &MOP1, const MachineOperand &MOP2);
461
462 /// Return true if \p MOP is defined by a G_CONSTANT with a value equal to
463 /// \p C.
464 bool matchConstantOp(const MachineOperand &MOP, int64_t C);
465
466 /// Optimize (cond ? x : x) -> x
468
469 /// Optimize (x op x) -> x
471
472 /// Check if operand \p OpIdx is zero.
473 bool matchOperandIsZero(MachineInstr &MI, unsigned OpIdx);
474
475 /// Check if operand \p OpIdx is undef.
476 bool matchOperandIsUndef(MachineInstr &MI, unsigned OpIdx);
477
478 /// Check if operand \p OpIdx is known to be a power of 2.
480
481 /// Erase \p MI
483
484 /// Return true if MI is a G_ADD which can be simplified to a G_SUB.
486 std::tuple<Register, Register> &MatchInfo);
488 std::tuple<Register, Register> &MatchInfo);
489
490 /// Match (logic_op (op x...), (op y...)) -> (op (logic_op x, y))
491 bool
493 InstructionStepsMatchInfo &MatchInfo);
494
495 /// Replace \p MI with a series of instructions described in \p MatchInfo.
497 InstructionStepsMatchInfo &MatchInfo);
498
499 /// Match ashr (shl x, C), C -> sext_inreg (C)
501 std::tuple<Register, int64_t> &MatchInfo);
503 std::tuple<Register, int64_t> &MatchInfo);
504
505 /// Fold and(and(x, C1), C2) -> C1&C2 ? and(x, C1&C2) : 0
507 BuildFnTy &MatchInfo);
508
509 /// \return true if \p MI is a G_AND instruction whose operands are x and y
510 /// where x & y == x or x & y == y. (E.g., one of operands is all-ones value.)
511 ///
512 /// \param [in] MI - The G_AND instruction.
513 /// \param [out] Replacement - A register the G_AND should be replaced with on
514 /// success.
515 bool matchRedundantAnd(MachineInstr &MI, Register &Replacement);
516
517 /// \return true if \p MI is a G_OR instruction whose operands are x and y
518 /// where x | y == x or x | y == y. (E.g., one of operands is all-zeros
519 /// value.)
520 ///
521 /// \param [in] MI - The G_OR instruction.
522 /// \param [out] Replacement - A register the G_OR should be replaced with on
523 /// success.
524 bool matchRedundantOr(MachineInstr &MI, Register &Replacement);
525
526 /// \return true if \p MI is a G_SEXT_INREG that can be erased.
528
529 /// Combine inverting a result of a compare into the opposite cond code.
532
533 /// Fold (xor (and x, y), y) -> (and (not x), y)
534 ///{
536 std::pair<Register, Register> &MatchInfo);
538 std::pair<Register, Register> &MatchInfo);
539 ///}
540
541 /// Combine G_PTR_ADD with nullptr to G_INTTOPTR
544
545 /// Combine G_UREM x, (known power of 2) to an add and bitmasking.
547
548 /// Push a binary operator through a select on constants.
549 ///
550 /// binop (select cond, K0, K1), K2 ->
551 /// select cond, (binop K0, K2), (binop K1, K2)
552 bool matchFoldBinOpIntoSelect(MachineInstr &MI, unsigned &SelectOpNo);
553 bool applyFoldBinOpIntoSelect(MachineInstr &MI, const unsigned &SelectOpNo);
554
556 SmallVectorImpl<Register> &MatchInfo);
557
559 SmallVectorImpl<Register> &MatchInfo);
560
561 /// Match expression trees of the form
562 ///
563 /// \code
564 /// sN *a = ...
565 /// sM val = a[0] | (a[1] << N) | (a[2] << 2N) | (a[3] << 3N) ...
566 /// \endcode
567 ///
568 /// And check if the tree can be replaced with a M-bit load + possibly a
569 /// bswap.
570 bool matchLoadOrCombine(MachineInstr &MI, BuildFnTy &MatchInfo);
571
574
577
580 SmallVectorImpl<std::pair<Register, MachineInstr *>> &MatchInfo);
583 SmallVectorImpl<std::pair<Register, MachineInstr *>> &MatchInfo);
584
585 /// Use a function which takes in a MachineIRBuilder to perform a combine.
586 /// By default, it erases the instruction \p MI from the function.
587 void applyBuildFn(MachineInstr &MI, BuildFnTy &MatchInfo);
588 /// Use a function which takes in a MachineIRBuilder to perform a combine.
589 /// This variant does not erase \p MI after calling the build function.
590 void applyBuildFnNoErase(MachineInstr &MI, BuildFnTy &MatchInfo);
591
597
598 /// \returns true if a G_ICMP instruction \p MI can be replaced with a true
599 /// or false constant based off of KnownBits information.
600 bool matchICmpToTrueFalseKnownBits(MachineInstr &MI, int64_t &MatchInfo);
601
602 /// \returns true if a G_ICMP \p MI can be replaced with its LHS based off of
603 /// KnownBits information.
604 bool
606 BuildFnTy &MatchInfo);
607
608 /// \returns true if (and (or x, c1), c2) can be replaced with (and x, c2)
610
612 BuildFnTy &MatchInfo);
613 /// Match: and (lshr x, cst), mask -> ubfx x, cst, width
615
616 /// Match: shr (shl x, n), k -> sbfx/ubfx x, pos, width
618
619 /// Match: shr (and x, n), k -> ubfx x, pos, width
621
622 // Helpers for reassociation:
624 BuildFnTy &MatchInfo);
627 BuildFnTy &MatchInfo);
629 MachineInstr *RHS, BuildFnTy &MatchInfo);
630 /// Reassociate pointer calculations with G_ADD involved, to allow better
631 /// addressing mode usage.
632 bool matchReassocPtrAdd(MachineInstr &MI, BuildFnTy &MatchInfo);
633
634 /// Do constant folding when opportunities are exposed after MIR building.
635 bool matchConstantFold(MachineInstr &MI, APInt &MatchInfo);
636
637 /// \returns true if it is possible to narrow the width of a scalar binop
638 /// feeding a G_AND instruction \p MI.
640
641 /// Given an G_UDIV \p MI expressing a divide by constant, return an
642 /// expression that implements it by multiplying by a magic number.
643 /// Ref: "Hacker's Delight" or "The PowerPC Compiler Writer's Guide".
645 /// Combine G_UDIV by constant into a multiply by magic constant.
648
649 /// Given an G_SDIV \p MI expressing a signed divide by constant, return an
650 /// expression that implements it by multiplying by a magic number.
651 /// Ref: "Hacker's Delight" or "The PowerPC Compiler Writer's Guide".
655
656 // G_UMULH x, (1 << c)) -> x >> (bitwidth - c)
659
660 /// Try to transform \p MI by using all of the above
661 /// combine functions. Returns true if changed.
663
664 /// Emit loads and stores that perform the given memcpy.
665 /// Assumes \p MI is a G_MEMCPY_INLINE
666 /// TODO: implement dynamically sized inline memcpy,
667 /// and rename: s/bool tryEmit/void emit/
669
670 /// Match:
671 /// (G_UMULO x, 2) -> (G_UADDO x, x)
672 /// (G_SMULO x, 2) -> (G_SADDO x, x)
673 bool matchMulOBy2(MachineInstr &MI, BuildFnTy &MatchInfo);
674
675 /// Match:
676 /// (G_*MULO x, 0) -> 0 + no carry out
677 bool matchMulOBy0(MachineInstr &MI, BuildFnTy &MatchInfo);
678
679 /// Match:
680 /// (G_*ADDO x, 0) -> x + no carry out
681 bool matchAddOBy0(MachineInstr &MI, BuildFnTy &MatchInfo);
682
683 /// Match:
684 /// (G_*ADDE x, y, 0) -> (G_*ADDO x, y)
685 /// (G_*SUBE x, y, 0) -> (G_*SUBO x, y)
686 bool matchAddEToAddO(MachineInstr &MI, BuildFnTy &MatchInfo);
687
688 /// Transform (fadd x, fneg(y)) -> (fsub x, y)
689 /// (fadd fneg(x), y) -> (fsub y, x)
690 /// (fsub x, fneg(y)) -> (fadd x, y)
691 /// (fmul fneg(x), fneg(y)) -> (fmul x, y)
692 /// (fdiv fneg(x), fneg(y)) -> (fdiv x, y)
693 /// (fmad fneg(x), fneg(y), z) -> (fmad x, y, z)
694 /// (fma fneg(x), fneg(y), z) -> (fma x, y, z)
696
697 bool matchFsubToFneg(MachineInstr &MI, Register &MatchInfo);
698 void applyFsubToFneg(MachineInstr &MI, Register &MatchInfo);
699
700 bool canCombineFMadOrFMA(MachineInstr &MI, bool &AllowFusionGlobally,
701 bool &HasFMAD, bool &Aggressive,
702 bool CanReassociate = false);
703
704 /// Transform (fadd (fmul x, y), z) -> (fma x, y, z)
705 /// (fadd (fmul x, y), z) -> (fmad x, y, z)
707
708 /// Transform (fadd (fpext (fmul x, y)), z) -> (fma (fpext x), (fpext y), z)
709 /// (fadd (fpext (fmul x, y)), z) -> (fmad (fpext x), (fpext y), z)
711 BuildFnTy &MatchInfo);
712
713 /// Transform (fadd (fma x, y, (fmul u, v)), z) -> (fma x, y, (fma u, v, z))
714 /// (fadd (fmad x, y, (fmul u, v)), z) -> (fmad x, y, (fmad u, v, z))
716 BuildFnTy &MatchInfo);
717
718 // Transform (fadd (fma x, y, (fpext (fmul u, v))), z)
719 // -> (fma x, y, (fma (fpext u), (fpext v), z))
720 // (fadd (fmad x, y, (fpext (fmul u, v))), z)
721 // -> (fmad x, y, (fmad (fpext u), (fpext v), z))
723 BuildFnTy &MatchInfo);
724
725 /// Transform (fsub (fmul x, y), z) -> (fma x, y, -z)
726 /// (fsub (fmul x, y), z) -> (fmad x, y, -z)
728
729 /// Transform (fsub (fneg (fmul, x, y)), z) -> (fma (fneg x), y, (fneg z))
730 /// (fsub (fneg (fmul, x, y)), z) -> (fmad (fneg x), y, (fneg z))
732 BuildFnTy &MatchInfo);
733
734 /// Transform (fsub (fpext (fmul x, y)), z)
735 /// -> (fma (fpext x), (fpext y), (fneg z))
736 /// (fsub (fpext (fmul x, y)), z)
737 /// -> (fmad (fpext x), (fpext y), (fneg z))
739 BuildFnTy &MatchInfo);
740
741 /// Transform (fsub (fpext (fneg (fmul x, y))), z)
742 /// -> (fneg (fma (fpext x), (fpext y), z))
743 /// (fsub (fpext (fneg (fmul x, y))), z)
744 /// -> (fneg (fmad (fpext x), (fpext y), z))
746 BuildFnTy &MatchInfo);
747
748 /// Fold boolean selects to logical operations.
750
751 bool matchCombineFMinMaxNaN(MachineInstr &MI, unsigned &Info);
752
753 /// Transform G_ADD(x, G_SUB(y, x)) to y.
754 /// Transform G_ADD(G_SUB(y, x), x) to y.
756
760
761 /// Transform:
762 /// (x + y) - y -> x
763 /// (x + y) - x -> y
764 /// x - (y + x) -> 0 - y
765 /// x - (x + z) -> 0 - z
766 bool matchSubAddSameReg(MachineInstr &MI, BuildFnTy &MatchInfo);
767
768 /// \returns true if it is possible to simplify a select instruction \p MI
769 /// to a min/max instruction of some sort.
771
772 /// Transform:
773 /// (X + Y) == X -> Y == 0
774 /// (X - Y) == X -> Y == 0
775 /// (X ^ Y) == X -> Y == 0
776 /// (X + Y) != X -> Y != 0
777 /// (X - Y) != X -> Y != 0
778 /// (X ^ Y) != X -> Y != 0
780
781 /// Match shifts greater or equal to the bitwidth of the operation.
783
784private:
785 /// Given a non-indexed load or store instruction \p MI, find an offset that
786 /// can be usefully and legally folded into it as a post-indexing operation.
787 ///
788 /// \returns true if a candidate is found.
789 bool findPostIndexCandidate(MachineInstr &MI, Register &Addr, Register &Base,
791
792 /// Given a non-indexed load or store instruction \p MI, find an offset that
793 /// can be usefully and legally folded into it as a pre-indexing operation.
794 ///
795 /// \returns true if a candidate is found.
796 bool findPreIndexCandidate(MachineInstr &MI, Register &Addr, Register &Base,
798
799 /// Helper function for matchLoadOrCombine. Searches for Registers
800 /// which may have been produced by a load instruction + some arithmetic.
801 ///
802 /// \param [in] Root - The search root.
803 ///
804 /// \returns The Registers found during the search.
805 std::optional<SmallVector<Register, 8>>
806 findCandidatesForLoadOrCombine(const MachineInstr *Root) const;
807
808 /// Helper function for matchLoadOrCombine.
809 ///
810 /// Checks if every register in \p RegsToVisit is defined by a load
811 /// instruction + some arithmetic.
812 ///
813 /// \param [out] MemOffset2Idx - Maps the byte positions each load ends up
814 /// at to the index of the load.
815 /// \param [in] MemSizeInBits - The number of bits each load should produce.
816 ///
817 /// \returns On success, a 3-tuple containing lowest-index load found, the
818 /// lowest index, and the last load in the sequence.
819 std::optional<std::tuple<GZExtLoad *, int64_t, GZExtLoad *>>
820 findLoadOffsetsForLoadOrCombine(
822 const SmallVector<Register, 8> &RegsToVisit,
823 const unsigned MemSizeInBits);
824
825 /// Examines the G_PTR_ADD instruction \p PtrAdd and determines if performing
826 /// a re-association of its operands would break an existing legal addressing
827 /// mode that the address computation currently represents.
828 bool reassociationCanBreakAddressingModePattern(MachineInstr &PtrAdd);
829
830 /// Behavior when a floating point min/max is given one NaN and one
831 /// non-NaN as input.
832 enum class SelectPatternNaNBehaviour {
833 NOT_APPLICABLE = 0, /// NaN behavior not applicable.
834 RETURNS_NAN, /// Given one NaN input, returns the NaN.
835 RETURNS_OTHER, /// Given one NaN input, returns the non-NaN.
836 RETURNS_ANY /// Given one NaN input, can return either (or both operands are
837 /// known non-NaN.)
838 };
839
840 /// \returns which of \p LHS and \p RHS would be the result of a non-equality
841 /// floating point comparison where one of \p LHS and \p RHS may be NaN.
842 ///
843 /// If both \p LHS and \p RHS may be NaN, returns
844 /// SelectPatternNaNBehaviour::NOT_APPLICABLE.
845 SelectPatternNaNBehaviour
846 computeRetValAgainstNaN(Register LHS, Register RHS,
847 bool IsOrderedComparison) const;
848
849 /// Determines the floating point min/max opcode which should be used for
850 /// a G_SELECT fed by a G_FCMP with predicate \p Pred.
851 ///
852 /// \returns 0 if this G_SELECT should not be combined to a floating point
853 /// min or max. If it should be combined, returns one of
854 ///
855 /// * G_FMAXNUM
856 /// * G_FMAXIMUM
857 /// * G_FMINNUM
858 /// * G_FMINIMUM
859 ///
860 /// Helper function for matchFPSelectToMinMax.
861 unsigned getFPMinMaxOpcForSelect(CmpInst::Predicate Pred, LLT DstTy,
862 SelectPatternNaNBehaviour VsNaNRetVal) const;
863
864 /// Handle floating point cases for matchSimplifySelectToMinMax.
865 ///
866 /// E.g.
867 ///
868 /// select (fcmp uge x, 1.0) x, 1.0 -> fmax x, 1.0
869 /// select (fcmp uge x, 1.0) 1.0, x -> fminnm x, 1.0
870 bool matchFPSelectToMinMax(Register Dst, Register Cond, Register TrueVal,
871 Register FalseVal, BuildFnTy &MatchInfo);
872};
873} // namespace llvm
874
875#endif
MachineInstrBuilder & UseMI
MachineInstrBuilder MachineInstrBuilder & DefMI
SmallVector< MachineOperand, 4 > Cond
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
This file defines the DenseMap class.
uint64_t Addr
IRTranslator LLVM IR MI
Implement a low-level type suitable for MachineInstr level instruction selection.
mir Rename Register Operands
unsigned Reg
static cl::opt< bool > Aggressive("aggressive-ext-opt", cl::Hidden, cl::desc("Aggressive extension optimization"))
This file defines the SmallVector class.
Value * RHS
Value * LHS
Class for arbitrary precision integers.
Definition: APInt.h:75
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:711
void applyUDivByConst(MachineInstr &MI)
void applyCombineMulToShl(MachineInstr &MI, unsigned &ShiftVal)
bool matchCombineShuffleVector(MachineInstr &MI, SmallVectorImpl< Register > &Ops)
Check if the G_SHUFFLE_VECTOR MI can be replaced by a concat_vectors.
bool matchPtrAddZero(MachineInstr &MI)
}
bool matchAllExplicitUsesAreUndef(MachineInstr &MI)
Return true if all register explicit use operands on MI are defined by a G_IMPLICIT_DEF.
const RegisterBank * getRegBank(Register Reg) const
Get the register bank of Reg.
bool matchReassocPtrAdd(MachineInstr &MI, BuildFnTy &MatchInfo)
Reassociate pointer calculations with G_ADD involved, to allow better addressing mode usage.
bool matchUDivByConst(MachineInstr &MI)
Combine G_UDIV by constant into a multiply by magic constant.
void applyExtractVecEltBuildVec(MachineInstr &MI, Register &Reg)
bool matchInsertExtractVecEltOutOfBounds(MachineInstr &MI)
Return true if a G_{EXTRACT,INSERT}_VECTOR_ELT has an out of range index.
bool matchShiftsTooBig(MachineInstr &MI)
Match shifts greater or equal to the bitwidth of the operation.
bool tryCombineCopy(MachineInstr &MI)
If MI is COPY, try to combine it.
bool matchTruncLshrBuildVectorFold(MachineInstr &MI, Register &MatchInfo)
bool matchUndefStore(MachineInstr &MI)
Return true if a G_STORE instruction MI is storing an undef value.
bool matchRedundantBinOpInEquality(MachineInstr &MI, BuildFnTy &MatchInfo)
Transform: (X + Y) == X -> Y == 0 (X - Y) == X -> Y == 0 (X ^ Y) == X -> Y == 0 (X + Y) !...
bool matchRedundantSExtInReg(MachineInstr &MI)
bool matchCombineFAddFpExtFMulToFMadOrFMAAggressive(MachineInstr &MI, BuildFnTy &MatchInfo)
bool matchReassocConstantInnerRHS(GPtrAdd &MI, MachineInstr *RHS, BuildFnTy &MatchInfo)
bool replaceInstWithConstant(MachineInstr &MI, int64_t C)
Replace an instruction with a G_CONSTANT with value C.
bool matchSubAddSameReg(MachineInstr &MI, BuildFnTy &MatchInfo)
Transform: (x + y) - y -> x (x + y) - x -> y x - (y + x) -> 0 - y x - (x + z) -> 0 - z.
void applyCombineShiftToUnmerge(MachineInstr &MI, const unsigned &ShiftVal)
void applyCombineUnmergeZExtToZExt(MachineInstr &MI)
bool matchBinOpSameVal(MachineInstr &MI)
Optimize (x op x) -> x.
void applyCombineUnmergeConstant(MachineInstr &MI, SmallVectorImpl< APInt > &Csts)
void applyCombineFAbsOfFAbs(MachineInstr &MI, Register &Src)
Transform fabs(fabs(x)) to fabs(x).
bool matchCombineFSubFNegFMulToFMadOrFMA(MachineInstr &MI, BuildFnTy &MatchInfo)
Transform (fsub (fneg (fmul, x, y)), z) -> (fma (fneg x), y, (fneg z)) (fsub (fneg (fmul,...
bool matchCombineCopy(MachineInstr &MI)
bool matchAddOBy0(MachineInstr &MI, BuildFnTy &MatchInfo)
Match: (G_*ADDO x, 0) -> x + no carry out.
bool matchConstantSelectCmp(MachineInstr &MI, unsigned &OpIdx)
Return true if a G_SELECT instruction MI has a constant comparison.
void replaceRegWith(MachineRegisterInfo &MRI, Register FromReg, Register ToReg) const
MachineRegisterInfo::replaceRegWith() and inform the observer of the changes.
void replaceRegOpWith(MachineRegisterInfo &MRI, MachineOperand &FromRegOp, Register ToReg) const
Replace a single register operand with a new register and inform the observer of the changes.
bool matchCombineFAddFMAFMulToFMadOrFMA(MachineInstr &MI, BuildFnTy &MatchInfo)
Transform (fadd (fma x, y, (fmul u, v)), z) -> (fma x, y, (fma u, v, z)) (fadd (fmad x,...
void applySimplifyAddToSub(MachineInstr &MI, std::tuple< Register, Register > &MatchInfo)
bool applyFoldBinOpIntoSelect(MachineInstr &MI, const unsigned &SelectOpNo)
SelectOperand is the operand in binary operator MI that is the select to fold.
bool matchSimplifySelectToMinMax(MachineInstr &MI, BuildFnTy &MatchInfo)
bool matchAddSubSameReg(MachineInstr &MI, Register &Src)
Transform G_ADD(x, G_SUB(y, x)) to y.
void applyRotateOutOfRange(MachineInstr &MI)
bool matchMulOBy2(MachineInstr &MI, BuildFnTy &MatchInfo)
Match: (G_UMULO x, 2) -> (G_UADDO x, x) (G_SMULO x, 2) -> (G_SADDO x, x)
bool matchRotateOutOfRange(MachineInstr &MI)
void applyCombineConstPtrAddToI2P(MachineInstr &MI, APInt &NewCst)
void applyCombineTruncOfShift(MachineInstr &MI, std::pair< MachineInstr *, LLT > &MatchInfo)
bool matchSelectToLogical(MachineInstr &MI, BuildFnTy &MatchInfo)
Fold boolean selects to logical operations.
void applyCombineShuffleVector(MachineInstr &MI, const ArrayRef< Register > Ops)
Replace MI with a concat_vectors with Ops.
const TargetLowering & getTargetLowering() const
void applyBuildFnNoErase(MachineInstr &MI, BuildFnTy &MatchInfo)
Use a function which takes in a MachineIRBuilder to perform a combine.
bool tryCombineIndexedLoadStore(MachineInstr &MI)
Combine MI into a pre-indexed or post-indexed load/store operation if legal and the surrounding code ...
void applyPtrAddZero(MachineInstr &MI)
bool matchTruncBuildVectorFold(MachineInstr &MI, Register &MatchInfo)
void setRegBank(Register Reg, const RegisterBank *RegBank)
Set the register bank of Reg.
bool matchRedundantAnd(MachineInstr &MI, Register &Replacement)
bool matchAshrShlToSextInreg(MachineInstr &MI, std::tuple< Register, int64_t > &MatchInfo)
Match ashr (shl x, C), C -> sext_inreg (C)
bool tryCombineExtendingLoads(MachineInstr &MI)
If MI is extend that consumes the result of a load, try to combine it.
bool tryCombineShiftToUnmerge(MachineInstr &MI, unsigned TargetShiftAmount)
bool matchCombineUnmergeUndef(MachineInstr &MI, std::function< void(MachineIRBuilder &)> &MatchInfo)
Transform G_UNMERGE G_IMPLICIT_DEF -> G_IMPLICIT_DEF, G_IMPLICIT_DEF, ...
GISelKnownBits * getKnownBits() const
void applySDivByConst(MachineInstr &MI)
bool matchUndefSelectCmp(MachineInstr &MI)
Return true if a G_SELECT instruction MI has an undef comparison.
bool matchRedundantOr(MachineInstr &MI, Register &Replacement)
bool matchOperandIsUndef(MachineInstr &MI, unsigned OpIdx)
Check if operand OpIdx is undef.
void applyBuildFn(MachineInstr &MI, BuildFnTy &MatchInfo)
Use a function which takes in a MachineIRBuilder to perform a combine.
bool matchCombineConstPtrAddToI2P(MachineInstr &MI, APInt &NewCst)
bool matchBitfieldExtractFromSExtInReg(MachineInstr &MI, BuildFnTy &MatchInfo)
Form a G_SBFX from a G_SEXT_INREG fed by a right shift.
bool matchEqualDefs(const MachineOperand &MOP1, const MachineOperand &MOP2)
Return true if MOP1 and MOP2 are register operands are defined by equivalent instructions.
bool matchShiftImmedChain(MachineInstr &MI, RegisterImmPair &MatchInfo)
Fold (shift (shift base, x), y) -> (shift base (x+y))
bool matchPtrAddImmedChain(MachineInstr &MI, PtrAddChain &MatchInfo)
void applyShiftImmedChain(MachineInstr &MI, RegisterImmPair &MatchInfo)
bool replaceSingleDefInstWithReg(MachineInstr &MI, Register Replacement)
Delete MI and replace all of its uses with Replacement.
void applyOptBrCondByInvertingCond(MachineInstr &MI, MachineInstr *&BrCond)
bool matchMulOBy0(MachineInstr &MI, BuildFnTy &MatchInfo)
Match: (G_*MULO x, 0) -> 0 + no carry out.
bool replaceSingleDefInstWithOperand(MachineInstr &MI, unsigned OpIdx)
Delete MI and replace all of its uses with its OpIdx-th operand.
bool matchFunnelShiftToRotate(MachineInstr &MI)
Match an FSHL or FSHR that can be combined to a ROTR or ROTL rotate.
bool matchNotCmp(MachineInstr &MI, SmallVectorImpl< Register > &RegsToNegate)
Combine inverting a result of a compare into the opposite cond code.
void applyCombineExtOfExt(MachineInstr &MI, std::tuple< Register, unsigned > &MatchInfo)
void replaceOpcodeWith(MachineInstr &FromMI, unsigned ToOpcode) const
Replace the opcode in instruction with a new opcode and inform the observer of the changes.
bool matchCombineConcatVectors(MachineInstr &MI, bool &IsUndef, SmallVectorImpl< Register > &Ops)
Check if the G_CONCAT_VECTORS MI is undef or if it can be flattened into a build_vector.
bool matchOperandIsKnownToBeAPowerOfTwo(MachineInstr &MI, unsigned OpIdx)
Check if operand OpIdx is known to be a power of 2.
void applyCombineCopy(MachineInstr &MI)
void applyCombineTruncOfExt(MachineInstr &MI, std::pair< Register, unsigned > &MatchInfo)
bool matchAnyExplicitUseIsUndef(MachineInstr &MI)
Return true if any explicit use operand on MI is defined by a G_IMPLICIT_DEF.
bool matchFsubToFneg(MachineInstr &MI, Register &MatchInfo)
void applyCombineAddP2IToPtrAdd(MachineInstr &MI, std::pair< Register, bool > &PtrRegAndCommute)
bool matchNarrowBinopFeedingAnd(MachineInstr &MI, BuildFnTy &MatchInfo)
bool matchSextTruncSextLoad(MachineInstr &MI)
bool matchShiftOfShiftedLogic(MachineInstr &MI, ShiftOfShiftedLogic &MatchInfo)
If we have a shift-by-constant of a bitwise logic op that itself has a shift-by-constant operand with...
GISelKnownBits * KB
bool matchExtractAllEltsFromBuildVector(MachineInstr &MI, SmallVectorImpl< std::pair< Register, MachineInstr * > > &MatchInfo)
void applyCombineIndexedLoadStore(MachineInstr &MI, IndexedLoadStoreMatchInfo &MatchInfo)
MachineInstr * buildSDivUsingMul(MachineInstr &MI)
Given an G_SDIV MI expressing a signed divide by constant, return an expression that implements it by...
bool isPreLegalize() const
bool matchCombineLoadWithAndMask(MachineInstr &MI, BuildFnTy &MatchInfo)
Match (and (load x), mask) -> zextload x.
bool matchConstantOp(const MachineOperand &MOP, int64_t C)
Return true if MOP is defined by a G_CONSTANT with a value equal to C.
bool matchCombineFSubFMulToFMadOrFMA(MachineInstr &MI, BuildFnTy &MatchInfo)
Transform (fsub (fmul x, y), z) -> (fma x, y, -z) (fsub (fmul x, y), z) -> (fmad x,...
void applyCombineI2PToP2I(MachineInstr &MI, Register &Reg)
void applyNotCmp(MachineInstr &MI, SmallVectorImpl< Register > &RegsToNegate)
void applyCombineExtendingLoads(MachineInstr &MI, PreferredTuple &MatchInfo)
bool matchSimplifyAddToSub(MachineInstr &MI, std::tuple< Register, Register > &MatchInfo)
Return true if MI is a G_ADD which can be simplified to a G_SUB.
bool tryCombineMemCpyFamily(MachineInstr &MI, unsigned MaxLen=0)
Optimize memcpy intrinsics et al, e.g.
bool matchSelectSameVal(MachineInstr &MI)
Optimize (cond ? x : x) -> x.
void applyCombineConstantFoldFpUnary(MachineInstr &MI, const ConstantFP *Cst)
Transform fp_instr(cst) to constant result of the fp operation.
bool matchCombineExtendingLoads(MachineInstr &MI, PreferredTuple &MatchInfo)
bool matchCombineFAbsOfFNeg(MachineInstr &MI, BuildFnTy &MatchInfo)
Transform fabs(fneg(x)) to fabs(x).
void applyCombineMulByNegativeOne(MachineInstr &MI)
Transform G_MUL(x, -1) to G_SUB(0, x)
bool isConstantLegalOrBeforeLegalizer(const LLT Ty) const
bool tryEmitMemcpyInline(MachineInstr &MI)
Emit loads and stores that perform the given memcpy.
void applyXorOfAndWithSameReg(MachineInstr &MI, std::pair< Register, Register > &MatchInfo)
bool matchXorOfAndWithSameReg(MachineInstr &MI, std::pair< Register, Register > &MatchInfo)
Fold (xor (and x, y), y) -> (and (not x), y) {.
bool matchCombineFSubFpExtFMulToFMadOrFMA(MachineInstr &MI, BuildFnTy &MatchInfo)
Transform (fsub (fpext (fmul x, y)), z) -> (fma (fpext x), (fpext y), (fneg z)) (fsub (fpext (fmul x,...
bool matchCombineFMinMaxNaN(MachineInstr &MI, unsigned &Info)
bool matchCombineShlOfExtend(MachineInstr &MI, RegisterImmPair &MatchData)
bool matchBitfieldExtractFromAnd(MachineInstr &MI, BuildFnTy &MatchInfo)
Match: and (lshr x, cst), mask -> ubfx x, cst, width.
void applyShiftOfShiftedLogic(MachineInstr &MI, ShiftOfShiftedLogic &MatchInfo)
bool isLegal(const LegalityQuery &Query) const
void applyCombineConcatVectors(MachineInstr &MI, bool IsUndef, const ArrayRef< Register > Ops)
Replace MI with a flattened build_vector with Ops or an implicit_def if IsUndef is true.
bool matchCombineUnmergeConstant(MachineInstr &MI, SmallVectorImpl< APInt > &Csts)
Transform G_UNMERGE Constant -> Constant1, Constant2, ...
bool matchICmpToTrueFalseKnownBits(MachineInstr &MI, int64_t &MatchInfo)
bool matchCombineAnyExtTrunc(MachineInstr &MI, Register &Reg)
Transform anyext(trunc(x)) to x.
void applySimplifyURemByPow2(MachineInstr &MI)
Combine G_UREM x, (known power of 2) to an add and bitmasking.
bool matchReassocFoldConstantsInSubTree(GPtrAdd &MI, MachineInstr *LHS, MachineInstr *RHS, BuildFnTy &MatchInfo)
MachineRegisterInfo & MRI
void applyUMulHToLShr(MachineInstr &MI)
bool matchLoadOrCombine(MachineInstr &MI, BuildFnTy &MatchInfo)
Match expression trees of the form.
bool matchUndefShuffleVectorMask(MachineInstr &MI)
Return true if a G_SHUFFLE_VECTOR instruction MI has an undef mask.
bool isLegalOrBeforeLegalizer(const LegalityQuery &Query) const
bool matchExtendThroughPhis(MachineInstr &MI, MachineInstr *&ExtMI)
bool matchAndOrDisjointMask(MachineInstr &MI, BuildFnTy &MatchInfo)
bool matchCombineMulToShl(MachineInstr &MI, unsigned &ShiftVal)
Transform a multiply by a power-of-2 value to a left shift.
bool matchBitfieldExtractFromShr(MachineInstr &MI, BuildFnTy &MatchInfo)
Match: shr (shl x, n), k -> sbfx/ubfx x, pos, width.
bool matchBuildVectorIdentityFold(MachineInstr &MI, Register &MatchInfo)
bool matchCombineFAddFMulToFMadOrFMA(MachineInstr &MI, BuildFnTy &MatchInfo)
Transform (fadd (fmul x, y), z) -> (fma x, y, z) (fadd (fmul x, y), z) -> (fmad x,...
bool matchRedundantNegOperands(MachineInstr &MI, BuildFnTy &MatchInfo)
Transform (fadd x, fneg(y)) -> (fsub x, y) (fadd fneg(x), y) -> (fsub y, x) (fsub x,...
bool tryCombineConcatVectors(MachineInstr &MI)
If MI is G_CONCAT_VECTORS, try to combine it.
bool matchCombineMergeUnmerge(MachineInstr &MI, Register &MatchInfo)
Fold away a merge of an unmerge of the corresponding values.
void applyCombineInsertVecElts(MachineInstr &MI, SmallVectorImpl< Register > &MatchInfo)
bool matchCombineUnmergeZExtToZExt(MachineInstr &MI)
Transform X, Y = G_UNMERGE(G_ZEXT(Z)) -> X = G_ZEXT(Z); Y = G_CONSTANT 0.
bool matchCombineUnmergeWithDeadLanesToTrunc(MachineInstr &MI)
Transform X, Y<dead> = G_UNMERGE Z -> X = G_TRUNC Z.
bool matchCombineDivRem(MachineInstr &MI, MachineInstr *&OtherMI)
Try to combine G_[SU]DIV and G_[SU]REM into a single G_[SU]DIVREM when their source operands are iden...
bool matchCombineTruncOfExt(MachineInstr &MI, std::pair< Register, unsigned > &MatchInfo)
Transform trunc ([asz]ext x) to x or ([asz]ext x) or (trunc x).
bool isPredecessor(const MachineInstr &DefMI, const MachineInstr &UseMI)
Returns true if DefMI precedes UseMI or they are the same instruction.
bool matchExtractVecEltBuildVec(MachineInstr &MI, Register &Reg)
bool matchUMulHToLShr(MachineInstr &MI)
bool matchConstantFold(MachineInstr &MI, APInt &MatchInfo)
Do constant folding when opportunities are exposed after MIR building.
bool dominates(const MachineInstr &DefMI, const MachineInstr &UseMI)
Returns true if DefMI dominates UseMI.
MachineInstr * buildUDivUsingMul(MachineInstr &MI)
Given an G_UDIV MI expressing a divide by constant, return an expression that implements it by multip...
bool eraseInst(MachineInstr &MI)
Erase MI.
bool matchCombineZextTrunc(MachineInstr &MI, Register &Reg)
Transform zext(trunc(x)) to x.
void applyCombineShlOfExtend(MachineInstr &MI, const RegisterImmPair &MatchData)
bool canCombineFMadOrFMA(MachineInstr &MI, bool &AllowFusionGlobally, bool &HasFMAD, bool &Aggressive, bool CanReassociate=false)
const LegalizerInfo * LI
void applyCombineUnmergeWithDeadLanesToTrunc(MachineInstr &MI)
MachineDominatorTree * MDT
bool tryCombine(MachineInstr &MI)
Try to transform MI by using all of the above combine functions.
bool matchSDivByConst(MachineInstr &MI)
MachineIRBuilder & getBuilder() const
void applySextInRegOfLoad(MachineInstr &MI, std::tuple< Register, unsigned > &MatchInfo)
bool matchCombineUnmergeMergeToPlainValues(MachineInstr &MI, SmallVectorImpl< Register > &Operands)
Transform <ty,...> G_UNMERGE(G_MERGE ty X, Y, Z) -> ty X, Y, Z.
void applyExtractAllEltsFromBuildVector(MachineInstr &MI, SmallVectorImpl< std::pair< Register, MachineInstr * > > &MatchInfo)
bool matchCombineTruncOfShift(MachineInstr &MI, std::pair< MachineInstr *, LLT > &MatchInfo)
Transform trunc (shl x, K) to shl (trunc x), K if K < VT.getScalarSizeInBits().
const RegisterBankInfo * RBI
bool matchCommuteShift(MachineInstr &MI, BuildFnTy &MatchInfo)
bool matchCombineFAddFpExtFMulToFMadOrFMA(MachineInstr &MI, BuildFnTy &MatchInfo)
Transform (fadd (fpext (fmul x, y)), z) -> (fma (fpext x), (fpext y), z) (fadd (fpext (fmul x,...
bool matchReassocConstantInnerLHS(GPtrAdd &MI, MachineInstr *LHS, MachineInstr *RHS, BuildFnTy &MatchInfo)
void applyExtendThroughPhis(MachineInstr &MI, MachineInstr *&ExtMI)
const TargetRegisterInfo * TRI
bool tryCombineShuffleVector(MachineInstr &MI)
Try to combine G_SHUFFLE_VECTOR into G_CONCAT_VECTORS.
bool matchCombineI2PToP2I(MachineInstr &MI, Register &Reg)
Transform IntToPtr(PtrToInt(x)) to x if cast is in the same address space.
bool matchICmpToLHSKnownBits(MachineInstr &MI, BuildFnTy &MatchInfo)
GISelChangeObserver & Observer
bool matchCombineExtOfExt(MachineInstr &MI, std::tuple< Register, unsigned > &MatchInfo)
Transform [asz]ext([asz]ext(x)) to [asz]ext x.
bool replaceInstWithUndef(MachineInstr &MI)
Replace an instruction with a G_IMPLICIT_DEF.
bool matchOverlappingAnd(MachineInstr &MI, BuildFnTy &MatchInfo)
Fold and(and(x, C1), C2) -> C1&C2 ? and(x, C1&C2) : 0.
bool matchSextInRegOfLoad(MachineInstr &MI, std::tuple< Register, unsigned > &MatchInfo)
Match sext_inreg(load p), imm -> sextload p.
bool matchCombineInsertVecElts(MachineInstr &MI, SmallVectorImpl< Register > &MatchInfo)
bool matchCombineAddP2IToPtrAdd(MachineInstr &MI, std::pair< Register, bool > &PtrRegAndCommute)
Transform G_ADD (G_PTRTOINT x), y -> G_PTRTOINT (G_PTR_ADD x, y) Transform G_ADD y,...
void applyFunnelShiftToRotate(MachineInstr &MI)
void applyCombineUnmergeMergeToPlainValues(MachineInstr &MI, SmallVectorImpl< Register > &Operands)
bool matchOptBrCondByInvertingCond(MachineInstr &MI, MachineInstr *&BrCond)
If a brcond's true block is not the fallthrough, make it so by inverting the condition and swapping o...
bool matchAddEToAddO(MachineInstr &MI, BuildFnTy &MatchInfo)
Match: (G_*ADDE x, y, 0) -> (G_*ADDO x, y) (G_*SUBE x, y, 0) -> (G_*SUBO x, y)
void applyCombineP2IToI2P(MachineInstr &MI, Register &Reg)
Transform PtrToInt(IntToPtr(x)) to x.
bool matchCombineShiftToUnmerge(MachineInstr &MI, unsigned TargetShiftSize, unsigned &ShiftVal)
Reduce a shift by a constant to an unmerge and a shift on a half sized type.
void applyPtrAddImmedChain(MachineInstr &MI, PtrAddChain &MatchInfo)
bool replaceInstWithFConstant(MachineInstr &MI, double C)
Replace an instruction with a G_FCONSTANT with value C.
void applyCombineDivRem(MachineInstr &MI, MachineInstr *&OtherMI)
void applyFsubToFneg(MachineInstr &MI, Register &MatchInfo)
void applyCombineAnyExtTrunc(MachineInstr &MI, Register &Reg)
void applyBuildInstructionSteps(MachineInstr &MI, InstructionStepsMatchInfo &MatchInfo)
Replace MI with a series of instructions described in MatchInfo.
bool matchCombineFSubFpExtFNegFMulToFMadOrFMA(MachineInstr &MI, BuildFnTy &MatchInfo)
Transform (fsub (fpext (fneg (fmul x, y))), z) -> (fneg (fma (fpext x), (fpext y),...
MachineIRBuilder & Builder
bool matchBitfieldExtractFromShrAnd(MachineInstr &MI, BuildFnTy &MatchInfo)
Match: shr (and x, n), k -> ubfx x, pos, width.
bool matchFoldBinOpIntoSelect(MachineInstr &MI, unsigned &SelectOpNo)
Push a binary operator through a select on constants.
bool matchOperandIsZero(MachineInstr &MI, unsigned OpIdx)
Check if operand OpIdx is zero.
bool matchOrShiftToFunnelShift(MachineInstr &MI, BuildFnTy &MatchInfo)
bool matchHoistLogicOpWithSameOpcodeHands(MachineInstr &MI, InstructionStepsMatchInfo &MatchInfo)
Match (logic_op (op x...), (op y...)) -> (op (logic_op x, y))
void applyAshShlToSextInreg(MachineInstr &MI, std::tuple< Register, int64_t > &MatchInfo)
void applySextTruncSextLoad(MachineInstr &MI)
bool matchCombineIndexedLoadStore(MachineInstr &MI, IndexedLoadStoreMatchInfo &MatchInfo)
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:260
Abstract class that contains various methods for clients to notify about changes.
Represents a G_PTR_ADD.
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
Helper class to build MachineInstr.
Representation of each machine instruction.
Definition: MachineInstr.h:68
MachineOperand class - Representation of each machine instruction operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Holds all the information related to register banks.
This class implements the register bank concept.
Definition: RegisterBank.h:28
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:577
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
@ ConstantFP
Definition: ISDOpcodes.h:77
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:406
std::function< void(MachineIRBuilder &)> BuildFnTy
InstructionBuildSteps(unsigned Opcode, const OperandBuildSteps &OperandFns)
InstructionBuildSteps()=default
Operands to be added to the instruction.
OperandBuildSteps OperandFns
The opcode for the produced instruction.
InstructionStepsMatchInfo(std::initializer_list< InstructionBuildSteps > InstrsToBuild)
SmallVector< InstructionBuildSteps, 2 > InstrsToBuild
Describes instructions to be built during a combine.
The LegalityQuery object bundles together all the information that's needed to decide whether a given...
MachineInstr * MI
const RegisterBank * Bank