LLVM  14.0.0git
ARMAsmBackendDarwin.h
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1 //===-- ARMAsmBackendDarwin.h ARM Asm Backend Darwin ----------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #ifndef LLVM_LIB_TARGET_ARM_ARMASMBACKENDDARWIN_H
10 #define LLVM_LIB_TARGET_ARM_ARMASMBACKENDDARWIN_H
11 
12 #include "ARMAsmBackend.h"
14 #include "llvm/MC/MCObjectWriter.h"
15 
16 namespace llvm {
18  const MCRegisterInfo &MRI;
19  Triple TT;
20 public:
23  const MCRegisterInfo &MRI)
24  : ARMAsmBackend(T, STI.getTargetTriple().isThumb(), support::little),
25  MRI(MRI), TT(STI.getTargetTriple()),
27  MachO::getCPUSubType(STI.getTargetTriple()))) {}
28 
29  std::unique_ptr<MCObjectTargetWriter>
30  createObjectTargetWriter() const override {
32  /*Is64Bit=*/false, cantFail(MachO::getCPUType(TT)), Subtype);
33  }
34 
36  ArrayRef<MCCFIInstruction> Instrs) const override;
37 };
38 } // end namespace llvm
39 
40 #endif
llvm::ARMAsmBackend
Definition: ARMAsmBackend.h:20
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:137
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:45
llvm::ARMAsmBackendDarwin
Definition: ARMAsmBackendDarwin.h:17
T
#define T
Definition: Mips16ISelLowering.cpp:341
llvm::MachO::getCPUType
Expected< uint32_t > getCPUType(const Triple &T)
Definition: MachO.cpp:77
llvm::ARMAsmBackendDarwin::generateCompactUnwindEncoding
uint32_t generateCompactUnwindEncoding(ArrayRef< MCCFIInstruction > Instrs) const override
Generate compact unwind encoding for the function based on the CFI instructions.
Definition: ARMAsmBackend.cpp:1110
llvm::ARMAsmBackendDarwin::createObjectTargetWriter
std::unique_ptr< MCObjectTargetWriter > createObjectTargetWriter() const override
Definition: ARMAsmBackendDarwin.h:30
llvm::createARMMachObjectWriter
std::unique_ptr< MCObjectTargetWriter > createARMMachObjectWriter(bool Is64Bit, uint32_t CPUType, uint32_t CPUSubtype)
Construct an ARM Mach-O object writer.
Definition: ARMMachObjectWriter.cpp:507
llvm::support::little
@ little
Definition: Endian.h:27
llvm::ARMAsmBackend::isThumb
bool isThumb() const
Definition: ARMAsmBackend.h:72
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::cantFail
void cantFail(Error Err, const char *Msg=nullptr)
Report a fatal error if Err is a failure value.
Definition: Error.h:737
uint32_t
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition: MCRegisterInfo.h:135
ARMAsmBackend.h
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
MCObjectWriter.h
getCPUSubType
static unsigned getCPUSubType(const MachOObjectFile &O)
Definition: MachOObjectFile.cpp:130
support
Reimplement select in terms of SEL *We would really like to support but we need to prove that the add doesn t need to overflow between the two bit chunks *Implement pre post increment support(e.g. PR935) *Implement smarter const ant generation for binops with large immediates. A few ARMv6T2 ops should be pattern matched
Definition: README.txt:10
llvm::MachO::CPUSubTypeARM
CPUSubTypeARM
Definition: MachO.h:1480
MachO.h
llvm::ARMAsmBackendDarwin::ARMAsmBackendDarwin
ARMAsmBackendDarwin(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI)
Definition: ARMAsmBackendDarwin.h:22
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:75
llvm::ARMAsmBackendDarwin::Subtype
const MachO::CPUSubTypeARM Subtype
Definition: ARMAsmBackendDarwin.h:21