LLVM 19.0.0git
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1//===-- ARMAsmBackend.h - ARM Assembler Backend -----------------*- C++ -*-===//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
18namespace llvm {
21 bool isThumbMode; // Currently emitting Thumb code.
24 : MCAsmBackend(Endian), isThumbMode(isThumb) {}
26 unsigned getNumFixupKinds() const override {
28 }
30 bool hasNOP(const MCSubtargetInfo *STI) const {
31 return STI->hasFeature(ARM::HasV6T2Ops);
32 }
34 std::optional<MCFixupKind> getFixupKind(StringRef Name) const override;
36 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override;
38 bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup,
39 const MCValue &Target,
40 const MCSubtargetInfo *STI) override;
42 unsigned adjustFixupValue(const MCAssembler &Asm, const MCFixup &Fixup,
44 bool IsResolved, MCContext &Ctx,
45 const MCSubtargetInfo *STI) const;
47 void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
49 uint64_t Value, bool IsResolved,
50 const MCSubtargetInfo *STI) const override;
52 unsigned getRelaxedOpcode(unsigned Op, const MCSubtargetInfo &STI) const;
54 bool mayNeedRelaxation(const MCInst &Inst,
55 const MCSubtargetInfo &STI) const override;
57 const char *reasonForFixupRelaxation(const MCFixup &Fixup,
58 uint64_t Value) const;
62 const MCAsmLayout &Layout) const override;
64 void relaxInstruction(MCInst &Inst,
65 const MCSubtargetInfo &STI) const override;
68 const MCSubtargetInfo *STI) const override;
70 void handleAssemblerFlag(MCAssemblerFlag Flag) override;
72 unsigned getPointerSize() const { return 4; }
73 bool isThumb() const { return isThumbMode; }
74 void setIsThumb(bool it) { isThumbMode = it; }
76} // end namespace llvm
static RegisterPass< DebugifyFunctionPass > DF("debugify-function", "Attach debug info to a function")
std::string Name
PowerPC TLS Dynamic Call Fixup
raw_pwrite_stream & OS
bool isThumb() const
Definition: ARMAsmBackend.h:73
const char * reasonForFixupRelaxation(const MCFixup &Fixup, uint64_t Value) const
unsigned getPointerSize() const
Definition: ARMAsmBackend.h:72
void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target, MutableArrayRef< char > Data, uint64_t Value, bool IsResolved, const MCSubtargetInfo *STI) const override
Apply the Value for given Fixup into the provided data fragment, at the offset specified by the fixup...
const MCFixupKindInfo & getFixupKindInfo(MCFixupKind Kind) const override
Get information on a fixup kind.
ARMAsmBackend(const Target &T, bool isThumb, llvm::endianness Endian)
Definition: ARMAsmBackend.h:23
unsigned getNumFixupKinds() const override
Get the number of target specific fixup kinds.
Definition: ARMAsmBackend.h:26
void setIsThumb(bool it)
Definition: ARMAsmBackend.h:74
bool hasNOP(const MCSubtargetInfo *STI) const
Definition: ARMAsmBackend.h:30
unsigned getRelaxedOpcode(unsigned Op, const MCSubtargetInfo &STI) const
bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target, const MCSubtargetInfo *STI) override
Hook to check if a relocation is needed for some target specific reason.
unsigned adjustFixupValue(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target, uint64_t Value, bool IsResolved, MCContext &Ctx, const MCSubtargetInfo *STI) const
bool writeNopData(raw_ostream &OS, uint64_t Count, const MCSubtargetInfo *STI) const override
Write an (optimal) nop sequence of Count bytes to the given output.
std::optional< MCFixupKind > getFixupKind(StringRef Name) const override
Map a relocation name used in .reloc to a fixup kind.
void relaxInstruction(MCInst &Inst, const MCSubtargetInfo &STI) const override
Relax the instruction in the given fragment to the next wider instruction.
bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value, const MCRelaxableFragment *DF, const MCAsmLayout &Layout) const override
Simple predicate for targets where !Resolved implies requiring relaxation.
bool mayNeedRelaxation(const MCInst &Inst, const MCSubtargetInfo &STI) const override
Check whether the given instruction may need relaxation.
void handleAssemblerFlag(MCAssemblerFlag Flag) override
Handle any target-specific assembler flags. By default, do nothing.
This class represents an Operation in the Expression.
Generic interface to target specific assembler backends.
Definition: MCAsmBackend.h:43
const llvm::endianness Endian
Definition: MCAsmBackend.h:52
Encapsulates the layout of an assembly file at a particular point in time.
Definition: MCAsmLayout.h:28
Context object for machine code objects.
Definition: MCContext.h:82
Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...
Definition: MCFixup.h:71
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
A relaxable fragment holds on to its MCInst, since it may need to be relaxed during the assembler lay...
Definition: MCFragment.h:267
Generic base class for all target subtargets.
bool hasFeature(unsigned Feature) const
This represents an "assembler immediate".
Definition: MCValue.h:36
MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...
Definition: ArrayRef.h:307
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
Target - Wrapper for Target specific information.
LLVM Value Representation.
Definition: Value.h:74
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
@ NumTargetFixupKinds
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
Extensible enumeration to represent the type of a fixup.
Definition: MCFixup.h:21
Definition: MCDirectives.h:53
Definition: bit.h:70
Target independent information on a fixup kind.