LLVM 20.0.0git
ARMAsmBackend.cpp
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1//===-- ARMAsmBackend.cpp - ARM Assembler Backend -------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
20#include "llvm/MC/MCAssembler.h"
21#include "llvm/MC/MCContext.h"
24#include "llvm/MC/MCExpr.h"
32#include "llvm/MC/MCValue.h"
33#include "llvm/Support/Debug.h"
36#include "llvm/Support/Format.h"
38using namespace llvm;
39
40namespace {
41class ARMELFObjectWriter : public MCELFObjectTargetWriter {
42public:
43 ARMELFObjectWriter(uint8_t OSABI)
44 : MCELFObjectTargetWriter(/*Is64Bit*/ false, OSABI, ELF::EM_ARM,
45 /*HasRelocationAddend*/ false) {}
46};
47} // end anonymous namespace
48
49std::optional<MCFixupKind> ARMAsmBackend::getFixupKind(StringRef Name) const {
50 return std::nullopt;
51}
52
53std::optional<MCFixupKind>
56#define ELF_RELOC(X, Y) .Case(#X, Y)
57#include "llvm/BinaryFormat/ELFRelocs/ARM.def"
58#undef ELF_RELOC
59 .Case("BFD_RELOC_NONE", ELF::R_ARM_NONE)
60 .Case("BFD_RELOC_8", ELF::R_ARM_ABS8)
61 .Case("BFD_RELOC_16", ELF::R_ARM_ABS16)
62 .Case("BFD_RELOC_32", ELF::R_ARM_ABS32)
63 .Default(-1u);
64 if (Type == -1u)
65 return std::nullopt;
66 return static_cast<MCFixupKind>(FirstLiteralRelocationKind + Type);
67}
68
70 const static MCFixupKindInfo InfosLE[ARM::NumTargetFixupKinds] = {
71 // This table *must* be in the order that the fixup_* kinds are defined in
72 // ARMFixupKinds.h.
73 //
74 // Name Offset (bits) Size (bits) Flags
75 {"fixup_arm_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
76 {"fixup_t2_ldst_pcrel_12", 0, 32,
79 {"fixup_arm_pcrel_10_unscaled", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
80 {"fixup_arm_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
81 {"fixup_t2_pcrel_10", 0, 32,
84 {"fixup_arm_pcrel_9", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
85 {"fixup_t2_pcrel_9", 0, 32,
88 {"fixup_arm_ldst_abs_12", 0, 32, 0},
89 {"fixup_thumb_adr_pcrel_10", 0, 8,
92 {"fixup_arm_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
93 {"fixup_t2_adr_pcrel_12", 0, 32,
96 {"fixup_arm_condbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel},
97 {"fixup_arm_uncondbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel},
98 {"fixup_t2_condbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
99 {"fixup_t2_uncondbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
100 {"fixup_arm_thumb_br", 0, 16, MCFixupKindInfo::FKF_IsPCRel},
101 {"fixup_arm_uncondbl", 0, 24, MCFixupKindInfo::FKF_IsPCRel},
102 {"fixup_arm_condbl", 0, 24, MCFixupKindInfo::FKF_IsPCRel},
103 {"fixup_arm_blx", 0, 24, MCFixupKindInfo::FKF_IsPCRel},
104 {"fixup_arm_thumb_bl", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
105 {"fixup_arm_thumb_blx", 0, 32,
108 {"fixup_arm_thumb_cb", 0, 16, MCFixupKindInfo::FKF_IsPCRel},
109 {"fixup_arm_thumb_cp", 0, 8,
112 {"fixup_arm_thumb_bcc", 0, 8, MCFixupKindInfo::FKF_IsPCRel},
113 // movw / movt: 16-bits immediate but scattered into two chunks 0 - 12, 16
114 // - 19.
115 {"fixup_arm_movt_hi16", 0, 20, 0},
116 {"fixup_arm_movw_lo16", 0, 20, 0},
117 {"fixup_t2_movt_hi16", 0, 20, 0},
118 {"fixup_t2_movw_lo16", 0, 20, 0},
119 {"fixup_arm_thumb_upper_8_15", 0, 8, 0},
120 {"fixup_arm_thumb_upper_0_7", 0, 8, 0},
121 {"fixup_arm_thumb_lower_8_15", 0, 8, 0},
122 {"fixup_arm_thumb_lower_0_7", 0, 8, 0},
123 {"fixup_arm_mod_imm", 0, 12, 0},
124 {"fixup_t2_so_imm", 0, 26, 0},
125 {"fixup_bf_branch", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
126 {"fixup_bf_target", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
127 {"fixup_bfl_target", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
128 {"fixup_bfc_target", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
129 {"fixup_bfcsel_else_target", 0, 32, 0},
130 {"fixup_wls", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
131 {"fixup_le", 0, 32, MCFixupKindInfo::FKF_IsPCRel}};
132 const static MCFixupKindInfo InfosBE[ARM::NumTargetFixupKinds] = {
133 // This table *must* be in the order that the fixup_* kinds are defined in
134 // ARMFixupKinds.h.
135 //
136 // Name Offset (bits) Size (bits) Flags
137 {"fixup_arm_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
138 {"fixup_t2_ldst_pcrel_12", 0, 32,
141 {"fixup_arm_pcrel_10_unscaled", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
142 {"fixup_arm_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
143 {"fixup_t2_pcrel_10", 0, 32,
146 {"fixup_arm_pcrel_9", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
147 {"fixup_t2_pcrel_9", 0, 32,
150 {"fixup_arm_ldst_abs_12", 0, 32, 0},
151 {"fixup_thumb_adr_pcrel_10", 8, 8,
154 {"fixup_arm_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
155 {"fixup_t2_adr_pcrel_12", 0, 32,
158 {"fixup_arm_condbranch", 8, 24, MCFixupKindInfo::FKF_IsPCRel},
159 {"fixup_arm_uncondbranch", 8, 24, MCFixupKindInfo::FKF_IsPCRel},
160 {"fixup_t2_condbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
161 {"fixup_t2_uncondbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
162 {"fixup_arm_thumb_br", 0, 16, MCFixupKindInfo::FKF_IsPCRel},
163 {"fixup_arm_uncondbl", 8, 24, MCFixupKindInfo::FKF_IsPCRel},
164 {"fixup_arm_condbl", 8, 24, MCFixupKindInfo::FKF_IsPCRel},
165 {"fixup_arm_blx", 8, 24, MCFixupKindInfo::FKF_IsPCRel},
166 {"fixup_arm_thumb_bl", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
167 {"fixup_arm_thumb_blx", 0, 32,
170 {"fixup_arm_thumb_cb", 0, 16, MCFixupKindInfo::FKF_IsPCRel},
171 {"fixup_arm_thumb_cp", 8, 8,
174 {"fixup_arm_thumb_bcc", 8, 8, MCFixupKindInfo::FKF_IsPCRel},
175 // movw / movt: 16-bits immediate but scattered into two chunks 0 - 12, 16
176 // - 19.
177 {"fixup_arm_movt_hi16", 12, 20, 0},
178 {"fixup_arm_movw_lo16", 12, 20, 0},
179 {"fixup_t2_movt_hi16", 12, 20, 0},
180 {"fixup_t2_movw_lo16", 12, 20, 0},
181 {"fixup_arm_thumb_upper_8_15", 24, 8, 0},
182 {"fixup_arm_thumb_upper_0_7", 24, 8, 0},
183 {"fixup_arm_thumb_lower_8_15", 24, 8, 0},
184 {"fixup_arm_thumb_lower_0_7", 24, 8, 0},
185 {"fixup_arm_mod_imm", 20, 12, 0},
186 {"fixup_t2_so_imm", 26, 6, 0},
187 {"fixup_bf_branch", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
188 {"fixup_bf_target", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
189 {"fixup_bfl_target", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
190 {"fixup_bfc_target", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
191 {"fixup_bfcsel_else_target", 0, 32, 0},
192 {"fixup_wls", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
193 {"fixup_le", 0, 32, MCFixupKindInfo::FKF_IsPCRel}};
194
195 // Fixup kinds from .reloc directive are like R_ARM_NONE. They do not require
196 // any extra processing.
197 if (Kind >= FirstLiteralRelocationKind)
199
200 if (Kind < FirstTargetFixupKind)
202
203 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
204 "Invalid kind!");
206 ? InfosLE
207 : InfosBE)[Kind - FirstTargetFixupKind];
208}
209
211 switch (Flag) {
212 default:
213 break;
214 case MCAF_Code16:
215 setIsThumb(true);
216 break;
217 case MCAF_Code32:
218 setIsThumb(false);
219 break;
220 }
221}
222
224 const MCSubtargetInfo &STI) const {
225 bool HasThumb2 = STI.hasFeature(ARM::FeatureThumb2);
226 bool HasV8MBaselineOps = STI.hasFeature(ARM::HasV8MBaselineOps);
227
228 switch (Op) {
229 default:
230 return Op;
231 case ARM::tBcc:
232 return HasThumb2 ? (unsigned)ARM::t2Bcc : Op;
233 case ARM::tLDRpci:
234 return HasThumb2 ? (unsigned)ARM::t2LDRpci : Op;
235 case ARM::tADR:
236 return HasThumb2 ? (unsigned)ARM::t2ADR : Op;
237 case ARM::tB:
238 return HasV8MBaselineOps ? (unsigned)ARM::t2B : Op;
239 case ARM::tCBZ:
240 return ARM::tHINT;
241 case ARM::tCBNZ:
242 return ARM::tHINT;
243 }
244}
245
247 const MCSubtargetInfo &STI) const {
248 if (getRelaxedOpcode(Inst.getOpcode(), STI) != Inst.getOpcode())
249 return true;
250 return false;
251}
252
253static const char *checkPCRelOffset(uint64_t Value, int64_t Min, int64_t Max) {
254 int64_t Offset = int64_t(Value) - 4;
255 if (Offset < Min || Offset > Max)
256 return "out of range pc-relative fixup value";
257 return nullptr;
258}
259
261 uint64_t Value) const {
262 switch (Fixup.getTargetKind()) {
264 // Relaxing tB to t2B. tB has a signed 12-bit displacement with the
265 // low bit being an implied zero. There's an implied +4 offset for the
266 // branch, so we adjust the other way here to determine what's
267 // encodable.
268 //
269 // Relax if the value is too big for a (signed) i8.
270 int64_t Offset = int64_t(Value) - 4;
271 if (Offset > 2046 || Offset < -2048)
272 return "out of range pc-relative fixup value";
273 break;
274 }
276 // Relaxing tBcc to t2Bcc. tBcc has a signed 9-bit displacement with the
277 // low bit being an implied zero. There's an implied +4 offset for the
278 // branch, so we adjust the other way here to determine what's
279 // encodable.
280 //
281 // Relax if the value is too big for a (signed) i8.
282 int64_t Offset = int64_t(Value) - 4;
283 if (Offset > 254 || Offset < -256)
284 return "out of range pc-relative fixup value";
285 break;
286 }
289 // If the immediate is negative, greater than 1020, or not a multiple
290 // of four, the wide version of the instruction must be used.
291 int64_t Offset = int64_t(Value) - 4;
292 if (Offset & 3)
293 return "misaligned pc-relative fixup value";
294 else if (Offset > 1020 || Offset < 0)
295 return "out of range pc-relative fixup value";
296 break;
297 }
299 // If we have a Thumb CBZ or CBNZ instruction and its target is the next
300 // instruction it is actually out of range for the instruction.
301 // It will be changed to a NOP.
302 int64_t Offset = (Value & ~1);
303 if (Offset == 2)
304 return "will be converted to nop";
305 break;
306 }
308 return checkPCRelOffset(Value, 0, 30);
310 return checkPCRelOffset(Value, -0x10000, +0xfffe);
312 return checkPCRelOffset(Value, -0x40000, +0x3fffe);
314 return checkPCRelOffset(Value, -0x1000, +0xffe);
315 case ARM::fixup_wls:
316 return checkPCRelOffset(Value, 0, +0xffe);
317 case ARM::fixup_le:
318 // The offset field in the LE and LETP instructions is an 11-bit
319 // value shifted left by 2 (i.e. 0,2,4,...,4094), and it is
320 // interpreted as a negative offset from the value read from pc,
321 // i.e. from instruction_address+4.
322 //
323 // So an LE instruction can in principle address the instruction
324 // immediately after itself, or (not very usefully) the address
325 // half way through the 4-byte LE.
326 return checkPCRelOffset(Value, -0xffe, 0);
328 if (Value != 2 && Value != 4)
329 return "out of range label-relative fixup value";
330 break;
331 }
332
333 default:
334 llvm_unreachable("Unexpected fixup kind in reasonForFixupRelaxation()!");
335 }
336 return nullptr;
337}
338
340 uint64_t Value) const {
342}
343
345 const MCSubtargetInfo &STI) const {
346 unsigned RelaxedOp = getRelaxedOpcode(Inst.getOpcode(), STI);
347
348 // Return a diagnostic if we get here w/ a bogus instruction.
349 if (RelaxedOp == Inst.getOpcode()) {
352 Inst.dump_pretty(OS);
353 OS << "\n";
354 report_fatal_error("unexpected instruction to relax: " + OS.str());
355 }
356
357 // If we are changing Thumb CBZ or CBNZ instruction to a NOP, aka tHINT, we
358 // have to change the operands too.
359 if ((Inst.getOpcode() == ARM::tCBZ || Inst.getOpcode() == ARM::tCBNZ) &&
360 RelaxedOp == ARM::tHINT) {
361 MCInst Res;
362 Res.setOpcode(RelaxedOp);
366 Inst = std::move(Res);
367 return;
368 }
369
370 // The rest of instructions we're relaxing have the same operands.
371 // We just need to update to the proper opcode.
372 Inst.setOpcode(RelaxedOp);
373}
374
376 const MCSubtargetInfo *STI) const {
377 const uint16_t Thumb1_16bitNopEncoding = 0x46c0; // using MOV r8,r8
378 const uint16_t Thumb2_16bitNopEncoding = 0xbf00; // NOP
379 const uint32_t ARMv4_NopEncoding = 0xe1a00000; // using MOV r0,r0
380 const uint32_t ARMv6T2_NopEncoding = 0xe320f000; // NOP
381 if (isThumb()) {
382 const uint16_t nopEncoding =
383 hasNOP(STI) ? Thumb2_16bitNopEncoding : Thumb1_16bitNopEncoding;
384 uint64_t NumNops = Count / 2;
385 for (uint64_t i = 0; i != NumNops; ++i)
386 support::endian::write(OS, nopEncoding, Endian);
387 if (Count & 1)
388 OS << '\0';
389 return true;
390 }
391 // ARM mode
392 const uint32_t nopEncoding =
393 hasNOP(STI) ? ARMv6T2_NopEncoding : ARMv4_NopEncoding;
394 uint64_t NumNops = Count / 4;
395 for (uint64_t i = 0; i != NumNops; ++i)
396 support::endian::write(OS, nopEncoding, Endian);
397 // FIXME: should this function return false when unable to write exactly
398 // 'Count' bytes with NOP encodings?
399 switch (Count % 4) {
400 default:
401 break; // No leftover bytes to write
402 case 1:
403 OS << '\0';
404 break;
405 case 2:
406 OS.write("\0\0", 2);
407 break;
408 case 3:
409 OS.write("\0\0\xa0", 3);
410 break;
411 }
412
413 return true;
414}
415
416static uint32_t swapHalfWords(uint32_t Value, bool IsLittleEndian) {
417 if (IsLittleEndian) {
418 // Note that the halfwords are stored high first and low second in thumb;
419 // so we need to swap the fixup value here to map properly.
420 uint32_t Swapped = (Value & 0xFFFF0000) >> 16;
421 Swapped |= (Value & 0x0000FFFF) << 16;
422 return Swapped;
423 } else
424 return Value;
425}
426
427static uint32_t joinHalfWords(uint32_t FirstHalf, uint32_t SecondHalf,
428 bool IsLittleEndian) {
430
431 if (IsLittleEndian) {
432 Value = (SecondHalf & 0xFFFF) << 16;
433 Value |= (FirstHalf & 0xFFFF);
434 } else {
435 Value = (SecondHalf & 0xFFFF);
436 Value |= (FirstHalf & 0xFFFF) << 16;
437 }
438
439 return Value;
440}
441
443 const MCFixup &Fixup,
445 bool IsResolved, MCContext &Ctx,
446 const MCSubtargetInfo* STI) const {
447 unsigned Kind = Fixup.getKind();
448
449 // MachO tries to make .o files that look vaguely pre-linked, so for MOVW/MOVT
450 // and .word relocations they put the Thumb bit into the addend if possible.
451 // Other relocation types don't want this bit though (branches couldn't encode
452 // it if it *was* present, and no other relocations exist) and it can
453 // interfere with checking valid expressions.
454 if (const MCSymbolRefExpr *A = Target.getSymA()) {
455 if (A->hasSubsectionsViaSymbols() && Asm.isThumbFunc(&A->getSymbol()) &&
456 A->getSymbol().isExternal() &&
457 (Kind == FK_Data_4 || Kind == ARM::fixup_arm_movw_lo16 ||
460 Value |= 1;
461 }
462
463 switch (Kind) {
464 default:
465 return 0;
466 case FK_Data_1:
467 case FK_Data_2:
468 case FK_Data_4:
469 return Value;
470 case FK_SecRel_2:
471 return Value;
472 case FK_SecRel_4:
473 return Value;
475 assert(STI != nullptr);
476 if (IsResolved || !STI->getTargetTriple().isOSBinFormatELF())
477 Value >>= 16;
478 [[fallthrough]];
480 unsigned Hi4 = (Value & 0xF000) >> 12;
481 unsigned Lo12 = Value & 0x0FFF;
482 // inst{19-16} = Hi4;
483 // inst{11-0} = Lo12;
484 Value = (Hi4 << 16) | (Lo12);
485 return Value;
486 }
488 assert(STI != nullptr);
489 if (IsResolved || !STI->getTargetTriple().isOSBinFormatELF())
490 Value >>= 16;
491 [[fallthrough]];
493 unsigned Hi4 = (Value & 0xF000) >> 12;
494 unsigned i = (Value & 0x800) >> 11;
495 unsigned Mid3 = (Value & 0x700) >> 8;
496 unsigned Lo8 = Value & 0x0FF;
497 // inst{19-16} = Hi4;
498 // inst{26} = i;
499 // inst{14-12} = Mid3;
500 // inst{7-0} = Lo8;
501 Value = (Hi4 << 16) | (i << 26) | (Mid3 << 12) | (Lo8);
503 }
505 if (IsResolved || !STI->getTargetTriple().isOSBinFormatELF())
506 return (Value & 0xff000000) >> 24;
507 return Value & 0xff;
509 if (IsResolved || !STI->getTargetTriple().isOSBinFormatELF())
510 return (Value & 0x00ff0000) >> 16;
511 return Value & 0xff;
513 if (IsResolved || !STI->getTargetTriple().isOSBinFormatELF())
514 return (Value & 0x0000ff00) >> 8;
515 return Value & 0xff;
517 return Value & 0x000000ff;
519 // ARM PC-relative values are offset by 8.
520 Value -= 4;
521 [[fallthrough]];
523 // Offset by 4, adjusted by two due to the half-word ordering of thumb.
524 Value -= 4;
525 [[fallthrough]];
527 bool isAdd = true;
528 if ((int64_t)Value < 0) {
529 Value = -Value;
530 isAdd = false;
531 }
532 if (Value >= 4096) {
533 Ctx.reportError(Fixup.getLoc(), "out of range pc-relative fixup value");
534 return 0;
535 }
536 Value |= isAdd << 23;
537
538 // Same addressing mode as fixup_arm_pcrel_10,
539 // but with 16-bit halfwords swapped.
540 if (Kind == ARM::fixup_t2_ldst_pcrel_12)
542
543 return Value;
544 }
546 // ARM PC-relative values are offset by 8.
547 Value -= 8;
548 unsigned opc = 4; // bits {24-21}. Default to add: 0b0100
549 if ((int64_t)Value < 0) {
550 Value = -Value;
551 opc = 2; // 0b0010
552 }
553 if (ARM_AM::getSOImmVal(Value) == -1) {
554 Ctx.reportError(Fixup.getLoc(), "out of range pc-relative fixup value");
555 return 0;
556 }
557 // Encode the immediate and shift the opcode into place.
558 return ARM_AM::getSOImmVal(Value) | (opc << 21);
559 }
560
562 Value -= 4;
563 unsigned opc = 0;
564 if ((int64_t)Value < 0) {
565 Value = -Value;
566 opc = 5;
567 }
568
569 uint32_t out = (opc << 21);
570 out |= (Value & 0x800) << 15;
571 out |= (Value & 0x700) << 4;
572 out |= (Value & 0x0FF);
573
575 }
576
582 // These values don't encode the low two bits since they're always zero.
583 // Offset by 8 just as above.
584 if (const MCSymbolRefExpr *SRE =
585 dyn_cast<MCSymbolRefExpr>(Fixup.getValue()))
586 if (SRE->getKind() == MCSymbolRefExpr::VK_TLSCALL)
587 return 0;
588 return 0xffffff & ((Value - 8) >> 2);
590 if (STI->getTargetTriple().isOSBinFormatCOFF() && !IsResolved &&
591 Value != 4) {
592 // MSVC link.exe and lld do not support this relocation type
593 // with a non-zero offset. ("Value" is offset by 4 at this point.)
594 Ctx.reportError(Fixup.getLoc(),
595 "cannot perform a PC-relative fixup with a non-zero "
596 "symbol offset");
597 }
598 Value = Value - 4;
599 if (!isInt<25>(Value)) {
600 Ctx.reportError(Fixup.getLoc(), "Relocation out of range");
601 return 0;
602 }
603
604 Value >>= 1; // Low bit is not encoded.
605
606 uint32_t out = 0;
607 bool I = Value & 0x800000;
608 bool J1 = Value & 0x400000;
609 bool J2 = Value & 0x200000;
610 J1 ^= I;
611 J2 ^= I;
612
613 out |= I << 26; // S bit
614 out |= !J1 << 13; // J1 bit
615 out |= !J2 << 11; // J2 bit
616 out |= (Value & 0x1FF800) << 5; // imm6 field
617 out |= (Value & 0x0007FF); // imm11 field
618
620 }
622 Value = Value - 4;
623 if (!isInt<21>(Value)) {
624 Ctx.reportError(Fixup.getLoc(), "Relocation out of range");
625 return 0;
626 }
627
628 Value >>= 1; // Low bit is not encoded.
629
630 uint64_t out = 0;
631 out |= (Value & 0x80000) << 7; // S bit
632 out |= (Value & 0x40000) >> 7; // J2 bit
633 out |= (Value & 0x20000) >> 4; // J1 bit
634 out |= (Value & 0x1F800) << 5; // imm6 field
635 out |= (Value & 0x007FF); // imm11 field
636
638 }
640 if (!isInt<25>(Value - 4) ||
641 (!STI->hasFeature(ARM::FeatureThumb2) &&
642 !STI->hasFeature(ARM::HasV8MBaselineOps) &&
643 !STI->hasFeature(ARM::HasV6MOps) &&
644 !isInt<23>(Value - 4))) {
645 Ctx.reportError(Fixup.getLoc(), "Relocation out of range");
646 return 0;
647 }
648 if (STI->getTargetTriple().isOSBinFormatCOFF() && !IsResolved &&
649 Value != 4) {
650 // MSVC link.exe and lld do not support this relocation type
651 // with a non-zero offset. ("Value" is offset by 4 at this point.)
652 Ctx.reportError(Fixup.getLoc(),
653 "cannot perform a PC-relative fixup with a non-zero "
654 "symbol offset");
655 }
656
657 // The value doesn't encode the low bit (always zero) and is offset by
658 // four. The 32-bit immediate value is encoded as
659 // imm32 = SignExtend(S:I1:I2:imm10:imm11:0)
660 // where I1 = NOT(J1 ^ S) and I2 = NOT(J2 ^ S).
661 // The value is encoded into disjoint bit positions in the destination
662 // opcode. x = unchanged, I = immediate value bit, S = sign extension bit,
663 // J = either J1 or J2 bit
664 //
665 // BL: xxxxxSIIIIIIIIII xxJxJIIIIIIIIIII
666 //
667 // Note that the halfwords are stored high first, low second; so we need
668 // to transpose the fixup value here to map properly.
669 uint32_t offset = (Value - 4) >> 1;
670 uint32_t signBit = (offset & 0x800000) >> 23;
671 uint32_t I1Bit = (offset & 0x400000) >> 22;
672 uint32_t J1Bit = (I1Bit ^ 0x1) ^ signBit;
673 uint32_t I2Bit = (offset & 0x200000) >> 21;
674 uint32_t J2Bit = (I2Bit ^ 0x1) ^ signBit;
675 uint32_t imm10Bits = (offset & 0x1FF800) >> 11;
676 uint32_t imm11Bits = (offset & 0x000007FF);
677
678 uint32_t FirstHalf = (((uint16_t)signBit << 10) | (uint16_t)imm10Bits);
679 uint32_t SecondHalf = (((uint16_t)J1Bit << 13) | ((uint16_t)J2Bit << 11) |
680 (uint16_t)imm11Bits);
681 return joinHalfWords(FirstHalf, SecondHalf,
683 }
685 if (STI->getTargetTriple().isOSBinFormatCOFF() && !IsResolved &&
686 Value != 4) {
687 // MSVC link.exe and lld do not support this relocation type
688 // with a non-zero offset. ("Value" is offset by 4 at this point.)
689 Ctx.reportError(Fixup.getLoc(),
690 "cannot perform a PC-relative fixup with a non-zero "
691 "symbol offset");
692 }
693 // The value doesn't encode the low two bits (always zero) and is offset by
694 // four (see fixup_arm_thumb_cp). The 32-bit immediate value is encoded as
695 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:00)
696 // where I1 = NOT(J1 ^ S) and I2 = NOT(J2 ^ S).
697 // The value is encoded into disjoint bit positions in the destination
698 // opcode. x = unchanged, I = immediate value bit, S = sign extension bit,
699 // J = either J1 or J2 bit, 0 = zero.
700 //
701 // BLX: xxxxxSIIIIIIIIII xxJxJIIIIIIIIII0
702 //
703 // Note that the halfwords are stored high first, low second; so we need
704 // to transpose the fixup value here to map properly.
705 if (Value % 4 != 0) {
706 Ctx.reportError(Fixup.getLoc(), "misaligned ARM call destination");
707 return 0;
708 }
709
710 uint32_t offset = (Value - 4) >> 2;
711 if (const MCSymbolRefExpr *SRE =
712 dyn_cast<MCSymbolRefExpr>(Fixup.getValue()))
713 if (SRE->getKind() == MCSymbolRefExpr::VK_TLSCALL)
714 offset = 0;
715 uint32_t signBit = (offset & 0x400000) >> 22;
716 uint32_t I1Bit = (offset & 0x200000) >> 21;
717 uint32_t J1Bit = (I1Bit ^ 0x1) ^ signBit;
718 uint32_t I2Bit = (offset & 0x100000) >> 20;
719 uint32_t J2Bit = (I2Bit ^ 0x1) ^ signBit;
720 uint32_t imm10HBits = (offset & 0xFFC00) >> 10;
721 uint32_t imm10LBits = (offset & 0x3FF);
722
723 uint32_t FirstHalf = (((uint16_t)signBit << 10) | (uint16_t)imm10HBits);
724 uint32_t SecondHalf = (((uint16_t)J1Bit << 13) | ((uint16_t)J2Bit << 11) |
725 ((uint16_t)imm10LBits) << 1);
726 return joinHalfWords(FirstHalf, SecondHalf,
728 }
731 // On CPUs supporting Thumb2, this will be relaxed to an ldr.w, otherwise we
732 // could have an error on our hands.
733 assert(STI != nullptr);
734 if (!STI->hasFeature(ARM::FeatureThumb2) && IsResolved) {
735 const char *FixupDiagnostic = reasonForFixupRelaxation(Fixup, Value);
736 if (FixupDiagnostic) {
737 Ctx.reportError(Fixup.getLoc(), FixupDiagnostic);
738 return 0;
739 }
740 }
741 // Offset by 4, and don't encode the low two bits.
742 return ((Value - 4) >> 2) & 0xff;
744 // CB instructions can only branch to offsets in [4, 126] in multiples of 2
745 // so ensure that the raw value LSB is zero and it lies in [2, 130].
746 // An offset of 2 will be relaxed to a NOP.
747 if ((int64_t)Value < 2 || Value > 0x82 || Value & 1) {
748 Ctx.reportError(Fixup.getLoc(), "out of range pc-relative fixup value");
749 return 0;
750 }
751 // Offset by 4 and don't encode the lower bit, which is always 0.
752 // FIXME: diagnose if no Thumb2
753 uint32_t Binary = (Value - 4) >> 1;
754 return ((Binary & 0x20) << 4) | ((Binary & 0x1f) << 3);
755 }
757 // Offset by 4 and don't encode the lower bit, which is always 0.
758 assert(STI != nullptr);
759 if (!STI->hasFeature(ARM::FeatureThumb2) &&
760 !STI->hasFeature(ARM::HasV8MBaselineOps)) {
761 const char *FixupDiagnostic = reasonForFixupRelaxation(Fixup, Value);
762 if (FixupDiagnostic) {
763 Ctx.reportError(Fixup.getLoc(), FixupDiagnostic);
764 return 0;
765 }
766 }
767 return ((Value - 4) >> 1) & 0x7ff;
769 // Offset by 4 and don't encode the lower bit, which is always 0.
770 assert(STI != nullptr);
771 if (!STI->hasFeature(ARM::FeatureThumb2)) {
772 const char *FixupDiagnostic = reasonForFixupRelaxation(Fixup, Value);
773 if (FixupDiagnostic) {
774 Ctx.reportError(Fixup.getLoc(), FixupDiagnostic);
775 return 0;
776 }
777 }
778 return ((Value - 4) >> 1) & 0xff;
780 Value = Value - 8; // ARM fixups offset by an additional word and don't
781 // need to adjust for the half-word ordering.
782 bool isAdd = true;
783 if ((int64_t)Value < 0) {
784 Value = -Value;
785 isAdd = false;
786 }
787 // The value has the low 4 bits encoded in [3:0] and the high 4 in [11:8].
788 if (Value >= 256) {
789 Ctx.reportError(Fixup.getLoc(), "out of range pc-relative fixup value");
790 return 0;
791 }
792 Value = (Value & 0xf) | ((Value & 0xf0) << 4);
793 return Value | (isAdd << 23);
794 }
796 Value = Value - 4; // ARM fixups offset by an additional word and don't
797 // need to adjust for the half-word ordering.
798 [[fallthrough]];
800 // Offset by 4, adjusted by two due to the half-word ordering of thumb.
801 Value = Value - 4;
802 bool isAdd = true;
803 if ((int64_t)Value < 0) {
804 Value = -Value;
805 isAdd = false;
806 }
807 // These values don't encode the low two bits since they're always zero.
808 Value >>= 2;
809 if (Value >= 256) {
810 Ctx.reportError(Fixup.getLoc(), "out of range pc-relative fixup value");
811 return 0;
812 }
813 Value |= isAdd << 23;
814
815 // Same addressing mode as fixup_arm_pcrel_10, but with 16-bit halfwords
816 // swapped.
817 if (Kind == ARM::fixup_t2_pcrel_10)
819
820 return Value;
821 }
823 Value = Value - 4; // ARM fixups offset by an additional word and don't
824 // need to adjust for the half-word ordering.
825 [[fallthrough]];
827 // Offset by 4, adjusted by two due to the half-word ordering of thumb.
828 Value = Value - 4;
829 bool isAdd = true;
830 if ((int64_t)Value < 0) {
831 Value = -Value;
832 isAdd = false;
833 }
834 // These values don't encode the low bit since it's always zero.
835 if (Value & 1) {
836 Ctx.reportError(Fixup.getLoc(), "invalid value for this fixup");
837 return 0;
838 }
839 Value >>= 1;
840 if (Value >= 256) {
841 Ctx.reportError(Fixup.getLoc(), "out of range pc-relative fixup value");
842 return 0;
843 }
844 Value |= isAdd << 23;
845
846 // Same addressing mode as fixup_arm_pcrel_9, but with 16-bit halfwords
847 // swapped.
848 if (Kind == ARM::fixup_t2_pcrel_9)
850
851 return Value;
852 }
855 if (Value >> 12) {
856 Ctx.reportError(Fixup.getLoc(), "out of range immediate fixup value");
857 return 0;
858 }
859 return Value;
862 if ((int64_t)Value < 0) {
863 Ctx.reportError(Fixup.getLoc(), "out of range immediate fixup value");
864 return 0;
865 }
866 // Value will contain a 12-bit value broken up into a 4-bit shift in bits
867 // 11:8 and the 8-bit immediate in 0:7. The instruction has the immediate
868 // in 0:7. The 4-bit shift is split up into i:imm3 where i is placed at bit
869 // 10 of the upper half-word and imm3 is placed at 14:12 of the lower
870 // half-word.
871 uint64_t EncValue = 0;
872 EncValue |= (Value & 0x800) << 15;
873 EncValue |= (Value & 0x700) << 4;
874 EncValue |= (Value & 0xff);
875 return swapHalfWords(EncValue, Endian == llvm::endianness::little);
876 }
878 const char *FixupDiagnostic = reasonForFixupRelaxation(Fixup, Value);
879 if (FixupDiagnostic) {
880 Ctx.reportError(Fixup.getLoc(), FixupDiagnostic);
881 return 0;
882 }
883 uint32_t out = (((Value - 4) >> 1) & 0xf) << 23;
885 }
889 const char *FixupDiagnostic = reasonForFixupRelaxation(Fixup, Value);
890 if (FixupDiagnostic) {
891 Ctx.reportError(Fixup.getLoc(), FixupDiagnostic);
892 return 0;
893 }
894 uint32_t out = 0;
895 uint32_t HighBitMask = (Kind == ARM::fixup_bf_target ? 0xf800 :
896 Kind == ARM::fixup_bfl_target ? 0x3f800 : 0x800);
897 out |= (((Value - 4) >> 1) & 0x1) << 11;
898 out |= (((Value - 4) >> 1) & 0x7fe);
899 out |= (((Value - 4) >> 1) & HighBitMask) << 5;
901 }
903 // If this is a fixup of a branch future's else target then it should be a
904 // constant MCExpr representing the distance between the branch targetted
905 // and the instruction after that same branch.
906 Value = Target.getConstant();
907
908 const char *FixupDiagnostic = reasonForFixupRelaxation(Fixup, Value);
909 if (FixupDiagnostic) {
910 Ctx.reportError(Fixup.getLoc(), FixupDiagnostic);
911 return 0;
912 }
913 uint32_t out = ((Value >> 2) & 1) << 17;
915 }
916 case ARM::fixup_wls:
917 case ARM::fixup_le: {
918 const char *FixupDiagnostic = reasonForFixupRelaxation(Fixup, Value);
919 if (FixupDiagnostic) {
920 Ctx.reportError(Fixup.getLoc(), FixupDiagnostic);
921 return 0;
922 }
923 uint64_t real_value = Value - 4;
924 uint32_t out = 0;
925 if (Kind == ARM::fixup_le)
926 real_value = -real_value;
927 out |= ((real_value >> 1) & 0x1) << 11;
928 out |= ((real_value >> 1) & 0x7fe);
930 }
931 }
932}
933
935 const MCFixup &Fixup,
936 const MCValue &Target,
937 const MCSubtargetInfo *STI) {
938 const MCSymbolRefExpr *A = Target.getSymA();
939 const MCSymbol *Sym = A ? &A->getSymbol() : nullptr;
940 const unsigned FixupKind = Fixup.getKind();
941 if (FixupKind >= FirstLiteralRelocationKind)
942 return true;
943 if (FixupKind == ARM::fixup_arm_thumb_bl) {
944 assert(Sym && "How did we resolve this?");
945
946 // If the symbol is external the linker will handle it.
947 // FIXME: Should we handle it as an optimization?
948
949 // If the symbol is out of range, produce a relocation and hope the
950 // linker can handle it. GNU AS produces an error in this case.
951 if (Sym->isExternal())
952 return true;
953 }
954 // Create relocations for unconditional branches to function symbols with
955 // different execution mode in ELF binaries.
956 if (Sym && Sym->isELF()) {
957 unsigned Type = cast<MCSymbolELF>(Sym)->getType();
958 if ((Type == ELF::STT_FUNC || Type == ELF::STT_GNU_IFUNC)) {
959 if (Asm.isThumbFunc(Sym) && (FixupKind == ARM::fixup_arm_uncondbranch))
960 return true;
961 if (!Asm.isThumbFunc(Sym) && (FixupKind == ARM::fixup_arm_thumb_br ||
962 FixupKind == ARM::fixup_arm_thumb_bl ||
963 FixupKind == ARM::fixup_t2_condbranch ||
964 FixupKind == ARM::fixup_t2_uncondbranch))
965 return true;
966 }
967 }
968 // We must always generate a relocation for BL/BLX instructions if we have
969 // a symbol to reference, as the linker relies on knowing the destination
970 // symbol's thumb-ness to get interworking right.
971 if (A && (FixupKind == ARM::fixup_arm_thumb_blx ||
972 FixupKind == ARM::fixup_arm_blx ||
973 FixupKind == ARM::fixup_arm_uncondbl ||
974 FixupKind == ARM::fixup_arm_condbl))
975 return true;
976 return false;
977}
978
979/// getFixupKindNumBytes - The number of bytes the fixup may change.
980static unsigned getFixupKindNumBytes(unsigned Kind) {
981 switch (Kind) {
982 default:
983 llvm_unreachable("Unknown fixup kind!");
984
985 case FK_Data_1:
993 return 1;
994
995 case FK_Data_2:
999 return 2;
1000
1009 case ARM::fixup_arm_blx:
1012 return 3;
1013
1014 case FK_Data_4:
1033 case ARM::fixup_wls:
1034 case ARM::fixup_le:
1035 return 4;
1036
1037 case FK_SecRel_2:
1038 return 2;
1039 case FK_SecRel_4:
1040 return 4;
1041 }
1042}
1043
1044/// getFixupKindContainerSizeBytes - The number of bytes of the
1045/// container involved in big endian.
1046static unsigned getFixupKindContainerSizeBytes(unsigned Kind) {
1047 switch (Kind) {
1048 default:
1049 llvm_unreachable("Unknown fixup kind!");
1050
1051 case FK_Data_1:
1052 return 1;
1053 case FK_Data_2:
1054 return 2;
1055 case FK_Data_4:
1056 return 4;
1057
1067 // Instruction size is 2 bytes.
1068 return 2;
1069
1077 case ARM::fixup_arm_blx:
1099 case ARM::fixup_wls:
1100 case ARM::fixup_le:
1101 // Instruction size is 4 bytes.
1102 return 4;
1103 }
1104}
1105
1107 const MCValue &Target,
1109 bool IsResolved,
1110 const MCSubtargetInfo* STI) const {
1111 unsigned Kind = Fixup.getKind();
1112 if (Kind >= FirstLiteralRelocationKind)
1113 return;
1114 MCContext &Ctx = Asm.getContext();
1115 Value = adjustFixupValue(Asm, Fixup, Target, Value, IsResolved, Ctx, STI);
1116 if (!Value)
1117 return; // Doesn't change encoding.
1118 const unsigned NumBytes = getFixupKindNumBytes(Kind);
1119
1120 unsigned Offset = Fixup.getOffset();
1121 assert(Offset + NumBytes <= Data.size() && "Invalid fixup offset!");
1122
1123 // Used to point to big endian bytes.
1124 unsigned FullSizeBytes;
1126 FullSizeBytes = getFixupKindContainerSizeBytes(Kind);
1127 assert((Offset + FullSizeBytes) <= Data.size() && "Invalid fixup size!");
1128 assert(NumBytes <= FullSizeBytes && "Invalid fixup size!");
1129 }
1130
1131 // For each byte of the fragment that the fixup touches, mask in the bits from
1132 // the fixup value. The Value has been "split up" into the appropriate
1133 // bitfields above.
1134 for (unsigned i = 0; i != NumBytes; ++i) {
1135 unsigned Idx =
1136 Endian == llvm::endianness::little ? i : (FullSizeBytes - 1 - i);
1137 Data[Offset + Idx] |= uint8_t((Value >> (i * 8)) & 0xff);
1138 }
1139}
1140
1141namespace CU {
1142
1143/// Compact unwind encoding values.
1149
1151
1155
1161
1163
1166
1167} // end CU namespace
1168
1169/// Generate compact unwind encoding for the function based on the CFI
1170/// instructions. If the CFI instructions describe a frame that cannot be
1171/// encoded in compact unwind, the method returns UNWIND_ARM_MODE_DWARF which
1172/// tells the runtime to fallback and unwind using dwarf.
1174 const MCDwarfFrameInfo *FI, const MCContext *Ctxt) const {
1175 DEBUG_WITH_TYPE("compact-unwind", llvm::dbgs() << "generateCU()\n");
1176 // Only armv7k uses CFI based unwinding.
1178 return 0;
1179 // No .cfi directives means no frame.
1181 if (Instrs.empty())
1182 return 0;
1186
1187 // Start off assuming CFA is at SP+0.
1188 unsigned CFARegister = ARM::SP;
1189 int CFARegisterOffset = 0;
1190 // Mark savable registers as initially unsaved
1191 DenseMap<unsigned, int> RegOffsets;
1192 int FloatRegCount = 0;
1193 // Process each .cfi directive and build up compact unwind info.
1194 for (const MCCFIInstruction &Inst : Instrs) {
1195 unsigned Reg;
1196 switch (Inst.getOperation()) {
1197 case MCCFIInstruction::OpDefCfa: // DW_CFA_def_cfa
1198 CFARegisterOffset = Inst.getOffset();
1199 CFARegister = *MRI.getLLVMRegNum(Inst.getRegister(), true);
1200 break;
1201 case MCCFIInstruction::OpDefCfaOffset: // DW_CFA_def_cfa_offset
1202 CFARegisterOffset = Inst.getOffset();
1203 break;
1204 case MCCFIInstruction::OpDefCfaRegister: // DW_CFA_def_cfa_register
1205 CFARegister = *MRI.getLLVMRegNum(Inst.getRegister(), true);
1206 break;
1207 case MCCFIInstruction::OpOffset: // DW_CFA_offset
1208 Reg = *MRI.getLLVMRegNum(Inst.getRegister(), true);
1209 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
1210 RegOffsets[Reg] = Inst.getOffset();
1211 else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) {
1212 RegOffsets[Reg] = Inst.getOffset();
1213 ++FloatRegCount;
1214 } else {
1215 DEBUG_WITH_TYPE("compact-unwind",
1216 llvm::dbgs() << ".cfi_offset on unknown register="
1217 << Inst.getRegister() << "\n");
1219 }
1220 break;
1221 case MCCFIInstruction::OpRelOffset: // DW_CFA_advance_loc
1222 // Ignore
1223 break;
1224 default:
1225 // Directive not convertable to compact unwind, bail out.
1226 DEBUG_WITH_TYPE("compact-unwind",
1227 llvm::dbgs()
1228 << "CFI directive not compatible with compact "
1229 "unwind encoding, opcode="
1230 << uint8_t(Inst.getOperation()) << "\n");
1232 break;
1233 }
1234 }
1235
1236 // If no frame set up, return no unwind info.
1237 if ((CFARegister == ARM::SP) && (CFARegisterOffset == 0))
1238 return 0;
1239
1240 // Verify standard frame (lr/r7) was used.
1241 if (CFARegister != ARM::R7) {
1242 DEBUG_WITH_TYPE("compact-unwind", llvm::dbgs() << "frame register is "
1243 << CFARegister
1244 << " instead of r7\n");
1246 }
1247 int StackAdjust = CFARegisterOffset - 8;
1248 if (RegOffsets.lookup(ARM::LR) != (-4 - StackAdjust)) {
1249 DEBUG_WITH_TYPE("compact-unwind",
1250 llvm::dbgs()
1251 << "LR not saved as standard frame, StackAdjust="
1252 << StackAdjust
1253 << ", CFARegisterOffset=" << CFARegisterOffset
1254 << ", lr save at offset=" << RegOffsets[14] << "\n");
1256 }
1257 if (RegOffsets.lookup(ARM::R7) != (-8 - StackAdjust)) {
1258 DEBUG_WITH_TYPE("compact-unwind",
1259 llvm::dbgs() << "r7 not saved as standard frame\n");
1261 }
1262 uint32_t CompactUnwindEncoding = CU::UNWIND_ARM_MODE_FRAME;
1263
1264 // If var-args are used, there may be a stack adjust required.
1265 switch (StackAdjust) {
1266 case 0:
1267 break;
1268 case 4:
1269 CompactUnwindEncoding |= 0x00400000;
1270 break;
1271 case 8:
1272 CompactUnwindEncoding |= 0x00800000;
1273 break;
1274 case 12:
1275 CompactUnwindEncoding |= 0x00C00000;
1276 break;
1277 default:
1278 DEBUG_WITH_TYPE("compact-unwind", llvm::dbgs()
1279 << ".cfi_def_cfa stack adjust ("
1280 << StackAdjust << ") out of range\n");
1282 }
1283
1284 // If r6 is saved, it must be right below r7.
1285 static struct {
1286 unsigned Reg;
1287 unsigned Encoding;
1288 } GPRCSRegs[] = {{ARM::R6, CU::UNWIND_ARM_FRAME_FIRST_PUSH_R6},
1296
1297 int CurOffset = -8 - StackAdjust;
1298 for (auto CSReg : GPRCSRegs) {
1299 auto Offset = RegOffsets.find(CSReg.Reg);
1300 if (Offset == RegOffsets.end())
1301 continue;
1302
1303 int RegOffset = Offset->second;
1304 if (RegOffset != CurOffset - 4) {
1305 DEBUG_WITH_TYPE("compact-unwind",
1306 llvm::dbgs() << MRI.getName(CSReg.Reg) << " saved at "
1307 << RegOffset << " but only supported at "
1308 << CurOffset << "\n");
1310 }
1311 CompactUnwindEncoding |= CSReg.Encoding;
1312 CurOffset -= 4;
1313 }
1314
1315 // If no floats saved, we are done.
1316 if (FloatRegCount == 0)
1317 return CompactUnwindEncoding;
1318
1319 // Switch mode to include D register saving.
1320 CompactUnwindEncoding &= ~CU::UNWIND_ARM_MODE_MASK;
1321 CompactUnwindEncoding |= CU::UNWIND_ARM_MODE_FRAME_D;
1322
1323 // FIXME: supporting more than 4 saved D-registers compactly would be trivial,
1324 // but needs coordination with the linker and libunwind.
1325 if (FloatRegCount > 4) {
1326 DEBUG_WITH_TYPE("compact-unwind",
1327 llvm::dbgs() << "unsupported number of D registers saved ("
1328 << FloatRegCount << ")\n");
1330 }
1331
1332 // Floating point registers must either be saved sequentially, or we defer to
1333 // DWARF. No gaps allowed here so check that each saved d-register is
1334 // precisely where it should be.
1335 static unsigned FPRCSRegs[] = { ARM::D8, ARM::D10, ARM::D12, ARM::D14 };
1336 for (int Idx = FloatRegCount - 1; Idx >= 0; --Idx) {
1337 auto Offset = RegOffsets.find(FPRCSRegs[Idx]);
1338 if (Offset == RegOffsets.end()) {
1339 DEBUG_WITH_TYPE("compact-unwind",
1340 llvm::dbgs() << FloatRegCount << " D-regs saved, but "
1341 << MRI.getName(FPRCSRegs[Idx])
1342 << " not saved\n");
1344 } else if (Offset->second != CurOffset - 8) {
1345 DEBUG_WITH_TYPE("compact-unwind",
1346 llvm::dbgs() << FloatRegCount << " D-regs saved, but "
1347 << MRI.getName(FPRCSRegs[Idx])
1348 << " saved at " << Offset->second
1349 << ", expected at " << CurOffset - 8
1350 << "\n");
1352 }
1353 CurOffset -= 8;
1354 }
1355
1356 return CompactUnwindEncoding | ((FloatRegCount - 1) << 8);
1357}
1358
1360 const MCSubtargetInfo &STI,
1361 const MCRegisterInfo &MRI,
1362 const MCTargetOptions &Options,
1363 llvm::endianness Endian) {
1364 const Triple &TheTriple = STI.getTargetTriple();
1365 switch (TheTriple.getObjectFormat()) {
1366 default:
1367 llvm_unreachable("unsupported object format");
1368 case Triple::MachO:
1369 return new ARMAsmBackendDarwin(T, STI, MRI);
1370 case Triple::COFF:
1371 assert(TheTriple.isOSWindows() && "non-Windows ARM COFF is not supported");
1372 return new ARMAsmBackendWinCOFF(T, STI.getTargetTriple().isThumb());
1373 case Triple::ELF:
1374 assert(TheTriple.isOSBinFormatELF() && "using ELF for non-ELF target");
1375 uint8_t OSABI = Options.FDPIC
1378 return new ARMAsmBackendELF(T, STI.getTargetTriple().isThumb(), OSABI,
1379 Endian);
1380 }
1381}
1382
1384 const MCSubtargetInfo &STI,
1385 const MCRegisterInfo &MRI,
1386 const MCTargetOptions &Options) {
1388}
1389
1391 const MCSubtargetInfo &STI,
1392 const MCRegisterInfo &MRI,
1393 const MCTargetOptions &Options) {
1395}
unsigned const MachineRegisterInfo * MRI
static unsigned getFixupKindNumBytes(unsigned Kind)
The number of bytes the fixup may change.
static uint32_t swapHalfWords(uint32_t Value, bool IsLittleEndian)
static unsigned getFixupKindContainerSizeBytes(unsigned Kind)
getFixupKindContainerSizeBytes - The number of bytes of the container involved in big endian.
static MCAsmBackend * createARMAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options, llvm::endianness Endian)
static uint32_t joinHalfWords(uint32_t FirstHalf, uint32_t SecondHalf, bool IsLittleEndian)
static const char * checkPCRelOffset(uint64_t Value, int64_t Min, int64_t Max)
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
#define DEBUG_WITH_TYPE(TYPE, X)
DEBUG_WITH_TYPE macro - This macro should be used by passes to emit debug information.
Definition: Debug.h:64
std::string Name
Symbol * Sym
Definition: ELF_riscv.cpp:479
static LVOptions Options
Definition: LVOptions.cpp:25
#define I(x, y, z)
Definition: MD5.cpp:58
PowerPC TLS Dynamic Call Fixup
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
endianness Endian
raw_pwrite_stream & OS
This file implements the StringSwitch template, which mimics a switch() statement whose cases are str...
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
Definition: Value.cpp:469
uint64_t generateCompactUnwindEncoding(const MCDwarfFrameInfo *FI, const MCContext *Ctxt) const override
Generate compact unwind encoding for the function based on the CFI instructions.
const MachO::CPUSubTypeARM Subtype
std::optional< MCFixupKind > getFixupKind(StringRef Name) const override
Map a relocation name used in .reloc to a fixup kind.
bool isThumb() const
Definition: ARMAsmBackend.h:72
bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value) const override
Simple predicate for targets where !Resolved implies requiring relaxation.
const char * reasonForFixupRelaxation(const MCFixup &Fixup, uint64_t Value) const
void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target, MutableArrayRef< char > Data, uint64_t Value, bool IsResolved, const MCSubtargetInfo *STI) const override
Apply the Value for given Fixup into the provided data fragment, at the offset specified by the fixup...
const MCFixupKindInfo & getFixupKindInfo(MCFixupKind Kind) const override
Get information on a fixup kind.
unsigned getNumFixupKinds() const override
Get the number of target specific fixup kinds.
Definition: ARMAsmBackend.h:26
void setIsThumb(bool it)
Definition: ARMAsmBackend.h:73
bool hasNOP(const MCSubtargetInfo *STI) const
Definition: ARMAsmBackend.h:30
unsigned getRelaxedOpcode(unsigned Op, const MCSubtargetInfo &STI) const
bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target, const MCSubtargetInfo *STI) override
Hook to check if a relocation is needed for some target specific reason.
unsigned adjustFixupValue(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target, uint64_t Value, bool IsResolved, MCContext &Ctx, const MCSubtargetInfo *STI) const
bool writeNopData(raw_ostream &OS, uint64_t Count, const MCSubtargetInfo *STI) const override
Write an (optimal) nop sequence of Count bytes to the given output.
std::optional< MCFixupKind > getFixupKind(StringRef Name) const override
Map a relocation name used in .reloc to a fixup kind.
void relaxInstruction(MCInst &Inst, const MCSubtargetInfo &STI) const override
Relax the instruction in the given fragment to the next wider instruction.
bool mayNeedRelaxation(const MCInst &Inst, const MCSubtargetInfo &STI) const override
Check whether the given instruction may need relaxation.
void handleAssemblerFlag(MCAssemblerFlag Flag) override
Handle any target-specific assembler flags. By default, do nothing.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:160
This class represents an Operation in the Expression.
ValueT lookup(const_arg_type_t< KeyT > Val) const
lookup - Return the entry for the specified key, or a default constructed value if no such entry exis...
Definition: DenseMap.h:194
iterator find(const_arg_type_t< KeyT > Val)
Definition: DenseMap.h:155
iterator end()
Definition: DenseMap.h:84
Generic interface to target specific assembler backends.
Definition: MCAsmBackend.h:42
const llvm::endianness Endian
Definition: MCAsmBackend.h:51
bool isDarwinCanonicalPersonality(const MCSymbol *Sym) const
virtual const MCFixupKindInfo & getFixupKindInfo(MCFixupKind Kind) const
Get information on a fixup kind.
Context object for machine code objects.
Definition: MCContext.h:83
bool emitCompactUnwindNonCanonical() const
Definition: MCContext.cpp:938
void reportError(SMLoc L, const Twine &Msg)
Definition: MCContext.cpp:1068
Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...
Definition: MCFixup.h:71
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
void dump_pretty(raw_ostream &OS, const MCInstPrinter *Printer=nullptr, StringRef Separator=" ", const MCRegisterInfo *RegInfo=nullptr) const
Dump the MCInst as prettily as possible using the additional MC structures, if given.
Definition: MCInst.cpp:84
unsigned getOpcode() const
Definition: MCInst.h:198
void addOperand(const MCOperand Op)
Definition: MCInst.h:210
void setOpcode(unsigned Op)
Definition: MCInst.h:197
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:134
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:141
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
std::optional< unsigned > getLLVMRegNum(unsigned RegNum, bool isEH) const
Map a dwarf register back to a target register.
const char * getName(MCRegister RegNo) const
Return the human-readable symbolic target-specific name for the specified physical register.
Generic base class for all target subtargets.
bool hasFeature(unsigned Feature) const
const Triple & getTargetTriple() const
Represent a reference to a symbol from inside an expression.
Definition: MCExpr.h:188
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
This represents an "assembler immediate".
Definition: MCValue.h:36
MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...
Definition: ArrayRef.h:307
SmallString - A SmallString is just a SmallVector with methods and accessors that make it work better...
Definition: SmallString.h:26
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:44
StringSwitch & Case(StringLiteral S, T Value)
Definition: StringSwitch.h:69
R Default(T Value)
Definition: StringSwitch.h:182
Target - Wrapper for Target specific information.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
bool isThumb() const
Tests whether the target is Thumb (little and big endian).
Definition: Triple.h:852
ObjectFormatType getObjectFormat() const
Get the object format for this triple.
Definition: Triple.h:399
OSType getOS() const
Get the parsed operating system type of this triple.
Definition: Triple.h:382
bool isOSBinFormatCOFF() const
Tests whether the OS uses the COFF binary format.
Definition: Triple.h:724
bool isOSWindows() const
Tests whether the OS is Windows.
Definition: Triple.h:624
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:719
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
LLVM Value Representation.
Definition: Value.h:74
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
raw_ostream & write(unsigned char C)
A raw_ostream that writes to an SmallVector or SmallString.
Definition: raw_ostream.h:691
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
CompactUnwindEncodings
Compact unwind encoding values.
@ UNWIND_ARM_FRAME_SECOND_PUSH_R10
@ UNWIND_ARM_FRAME_FIRST_PUSH_R6
@ UNWIND_ARM_FRAME_SECOND_PUSH_R11
@ UNWIND_ARM_MODE_DWARF
@ UNWIND_ARM_DWARF_SECTION_OFFSET
@ UNWIND_ARM_FRAME_FIRST_PUSH_R4
@ UNWIND_ARM_FRAME_SECOND_PUSH_R9
@ UNWIND_ARM_FRAME_SECOND_PUSH_R8
@ UNWIND_ARM_FRAME_STACK_ADJUST_MASK
@ UNWIND_ARM_MODE_FRAME
@ UNWIND_ARM_FRAME_SECOND_PUSH_R12
@ UNWIND_ARM_FRAME_D_REG_COUNT_MASK
@ UNWIND_ARM_MODE_MASK
@ UNWIND_ARM_MODE_FRAME_D
@ UNWIND_ARM_FRAME_FIRST_PUSH_R5
int getSOImmVal(unsigned Arg)
getSOImmVal - Given a 32-bit immediate, if it is something that can fit into an shifter_operand immed...
int getT2SOImmVal(unsigned Arg)
getT2SOImmVal - Given a 32-bit immediate, if it is something that can fit into a Thumb-2 shifter_oper...
@ fixup_arm_thumb_br
Definition: ARMFixupKinds.h:60
@ fixup_thumb_adr_pcrel_10
Definition: ARMFixupKinds.h:43
@ fixup_arm_thumb_upper_8_15
@ fixup_arm_adr_pcrel_12
Definition: ARMFixupKinds.h:45
@ fixup_arm_pcrel_10
Definition: ARMFixupKinds.h:29
@ fixup_arm_uncondbranch
Definition: ARMFixupKinds.h:51
@ fixup_arm_thumb_cb
Definition: ARMFixupKinds.h:87
@ fixup_arm_movw_lo16
Definition: ARMFixupKinds.h:98
@ fixup_t2_movt_hi16
Definition: ARMFixupKinds.h:99
@ fixup_t2_ldst_pcrel_12
Definition: ARMFixupKinds.h:21
@ fixup_arm_thumb_lower_0_7
@ fixup_arm_ldst_abs_12
Definition: ARMFixupKinds.h:40
@ fixup_arm_pcrel_9
Definition: ARMFixupKinds.h:35
@ fixup_arm_movt_hi16
Definition: ARMFixupKinds.h:97
@ fixup_t2_pcrel_9
Definition: ARMFixupKinds.h:38
@ fixup_t2_pcrel_10
Definition: ARMFixupKinds.h:32
@ fixup_arm_thumb_blx
Definition: ARMFixupKinds.h:84
@ fixup_arm_thumb_cp
Definition: ARMFixupKinds.h:90
@ fixup_t2_uncondbranch
Definition: ARMFixupKinds.h:57
@ NumTargetFixupKinds
@ fixup_arm_uncondbl
Definition: ARMFixupKinds.h:72
@ fixup_arm_pcrel_10_unscaled
Definition: ARMFixupKinds.h:25
@ fixup_arm_thumb_bcc
Definition: ARMFixupKinds.h:93
@ fixup_arm_thumb_upper_0_7
@ fixup_bfcsel_else_target
@ fixup_t2_adr_pcrel_12
Definition: ARMFixupKinds.h:47
@ fixup_t2_condbranch
Definition: ARMFixupKinds.h:54
@ fixup_arm_condbl
Definition: ARMFixupKinds.h:75
@ fixup_arm_ldst_pcrel_12
Definition: ARMFixupKinds.h:18
@ fixup_arm_thumb_lower_8_15
@ fixup_arm_thumb_bl
Definition: ARMFixupKinds.h:81
@ fixup_t2_movw_lo16
@ fixup_arm_condbranch
Definition: ARMFixupKinds.h:49
@ EM_ARM
Definition: ELF.h:157
@ ELFOSABI_ARM_FDPIC
Definition: ELF.h:366
@ STT_FUNC
Definition: ELF.h:1353
@ STT_GNU_IFUNC
Definition: ELF.h:1358
@ CPU_SUBTYPE_ARM_V7K
Definition: MachO.h:1634
void write(void *memory, value_type value, endianness endian)
Write a value to memory with a particular endianness.
Definition: Endian.h:92
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:480
MCAsmBackend * createARMBEAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
MCAsmBackend * createARMLEAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:167
MCFixupKind
Extensible enumeration to represent the type of a fixup.
Definition: MCFixup.h:21
@ FirstTargetFixupKind
Definition: MCFixup.h:45
@ FK_SecRel_2
A two-byte section relative fixup.
Definition: MCFixup.h:41
@ FirstLiteralRelocationKind
The range [FirstLiteralRelocationKind, MaxTargetFixupKind) is used for relocations coming from ....
Definition: MCFixup.h:50
@ FK_Data_1
A one-byte fixup.
Definition: MCFixup.h:23
@ FK_Data_4
A four-byte fixup.
Definition: MCFixup.h:25
@ FK_NONE
A no-op fixup.
Definition: MCFixup.h:22
@ FK_SecRel_4
A four-byte section relative fixup.
Definition: MCFixup.h:42
@ FK_Data_2
A two-byte fixup.
Definition: MCFixup.h:24
MCAssemblerFlag
Definition: MCDirectives.h:53
@ MCAF_Code16
.code16 (X86) / .code 16 (ARM)
Definition: MCDirectives.h:56
@ MCAF_Code32
.code32 (X86) / .code 32 (ARM)
Definition: MCDirectives.h:57
DWARFExpression::Operation Op
endianness
Definition: bit.h:70
const MCSymbol * Personality
Definition: MCDwarf.h:733
std::vector< MCCFIInstruction > Instructions
Definition: MCDwarf.h:735
Target independent information on a fixup kind.
@ FKF_IsAlignedDownTo32Bits
Should this fixup kind force a 4-byte aligned effective PC value?
@ FKF_IsPCRel
Is this fixup kind PCrelative? This is used by the assembler backend to evaluate fixup values in a ta...