43 ARMELFObjectWriter(uint8_t OSABI)
53std::optional<MCFixupKind>
56#define ELF_RELOC(X, Y) .Case(#X, Y)
57#include "llvm/BinaryFormat/ELFRelocs/ARM.def"
59 .
Case(
"BFD_RELOC_NONE", ELF::R_ARM_NONE)
60 .
Case(
"BFD_RELOC_8", ELF::R_ARM_ABS8)
61 .
Case(
"BFD_RELOC_16", ELF::R_ARM_ABS16)
62 .
Case(
"BFD_RELOC_32", ELF::R_ARM_ABS32)
70 unsigned IsPCRelConstant =
77 {
"fixup_arm_ldst_pcrel_12", 0, 32, IsPCRelConstant},
78 {
"fixup_t2_ldst_pcrel_12", 0, 32,
80 {
"fixup_arm_pcrel_10_unscaled", 0, 32, IsPCRelConstant},
81 {
"fixup_arm_pcrel_10", 0, 32, IsPCRelConstant},
82 {
"fixup_t2_pcrel_10", 0, 32,
86 {
"fixup_t2_pcrel_9", 0, 32,
88 {
"fixup_arm_ldst_abs_12", 0, 32, 0},
89 {
"fixup_thumb_adr_pcrel_10", 0, 8,
91 {
"fixup_arm_adr_pcrel_12", 0, 32, IsPCRelConstant},
92 {
"fixup_t2_adr_pcrel_12", 0, 32,
103 {
"fixup_arm_thumb_blx", 0, 32,
107 {
"fixup_arm_thumb_cp", 0, 8,
113 {
"fixup_arm_movt_hi16", 0, 20, 0},
114 {
"fixup_arm_movw_lo16", 0, 20, 0},
115 {
"fixup_t2_movt_hi16", 0, 20, 0},
116 {
"fixup_t2_movw_lo16", 0, 20, 0},
117 {
"fixup_arm_thumb_upper_8_15", 0, 8, 0},
118 {
"fixup_arm_thumb_upper_0_7", 0, 8, 0},
119 {
"fixup_arm_thumb_lower_8_15", 0, 8, 0},
120 {
"fixup_arm_thumb_lower_0_7", 0, 8, 0},
121 {
"fixup_arm_mod_imm", 0, 12, 0},
122 {
"fixup_t2_so_imm", 0, 26, 0},
127 {
"fixup_bfcsel_else_target", 0, 32, 0},
135 {
"fixup_arm_ldst_pcrel_12", 0, 32, IsPCRelConstant},
136 {
"fixup_t2_ldst_pcrel_12", 0, 32,
138 {
"fixup_arm_pcrel_10_unscaled", 0, 32, IsPCRelConstant},
139 {
"fixup_arm_pcrel_10", 0, 32, IsPCRelConstant},
140 {
"fixup_t2_pcrel_10", 0, 32,
144 {
"fixup_t2_pcrel_9", 0, 32,
146 {
"fixup_arm_ldst_abs_12", 0, 32, 0},
147 {
"fixup_thumb_adr_pcrel_10", 8, 8,
149 {
"fixup_arm_adr_pcrel_12", 0, 32, IsPCRelConstant},
150 {
"fixup_t2_adr_pcrel_12", 0, 32,
161 {
"fixup_arm_thumb_blx", 0, 32,
165 {
"fixup_arm_thumb_cp", 8, 8,
171 {
"fixup_arm_movt_hi16", 12, 20, 0},
172 {
"fixup_arm_movw_lo16", 12, 20, 0},
173 {
"fixup_t2_movt_hi16", 12, 20, 0},
174 {
"fixup_t2_movw_lo16", 12, 20, 0},
175 {
"fixup_arm_thumb_upper_8_15", 24, 8, 0},
176 {
"fixup_arm_thumb_upper_0_7", 24, 8, 0},
177 {
"fixup_arm_thumb_lower_8_15", 24, 8, 0},
178 {
"fixup_arm_thumb_lower_0_7", 24, 8, 0},
179 {
"fixup_arm_mod_imm", 20, 12, 0},
180 {
"fixup_t2_so_imm", 26, 6, 0},
185 {
"fixup_bfcsel_else_target", 0, 32, 0},
218 bool HasThumb2 = STI.
hasFeature(ARM::FeatureThumb2);
219 bool HasV8MBaselineOps = STI.
hasFeature(ARM::HasV8MBaselineOps);
227 return HasThumb2 ? (
unsigned)ARM::t2LDRpci :
Op;
231 return HasV8MBaselineOps ? (
unsigned)ARM::t2B :
Op;
248 if (Offset < Min || Offset > Max)
249 return "out of range pc-relative fixup value";
255 switch (
Fixup.getTargetKind()) {
265 return "out of range pc-relative fixup value";
277 return "out of range pc-relative fixup value";
286 return "misaligned pc-relative fixup value";
288 return "out of range pc-relative fixup value";
297 return "will be converted to nop";
322 return "out of range label-relative fixup value";
354 RelaxedOp == ARM::tHINT) {
360 Inst = std::move(Res);
371 const uint16_t Thumb1_16bitNopEncoding = 0x46c0;
372 const uint16_t Thumb2_16bitNopEncoding = 0xbf00;
373 const uint32_t ARMv4_NopEncoding = 0xe1a00000;
374 const uint32_t ARMv6T2_NopEncoding = 0xe320f000;
377 hasNOP(STI) ? Thumb2_16bitNopEncoding : Thumb1_16bitNopEncoding;
379 for (
uint64_t i = 0; i != NumNops; ++i)
387 hasNOP(STI) ? ARMv6T2_NopEncoding : ARMv4_NopEncoding;
389 for (
uint64_t i = 0; i != NumNops; ++i)
411 if (IsLittleEndian) {
415 Swapped |= (
Value & 0x0000FFFF) << 16;
422 bool IsLittleEndian) {
425 if (IsLittleEndian) {
426 Value = (SecondHalf & 0xFFFF) << 16;
427 Value |= (FirstHalf & 0xFFFF);
429 Value = (SecondHalf & 0xFFFF);
430 Value |= (FirstHalf & 0xFFFF) << 16;
441 unsigned Kind =
Fixup.getKind();
449 if (
A->hasSubsectionsViaSymbols() && Asm.isThumbFunc(&
A->getSymbol()) &&
450 A->getSymbol().isExternal() &&
474 unsigned Hi4 = (
Value & 0xF000) >> 12;
475 unsigned Lo12 =
Value & 0x0FFF;
478 Value = (Hi4 << 16) | (Lo12);
487 unsigned Hi4 = (
Value & 0xF000) >> 12;
488 unsigned i = (
Value & 0x800) >> 11;
489 unsigned Mid3 = (
Value & 0x700) >> 8;
490 unsigned Lo8 =
Value & 0x0FF;
495 Value = (Hi4 << 16) | (i << 26) | (Mid3 << 12) | (Lo8);
500 return (
Value & 0xff000000) >> 24;
504 return (
Value & 0x00ff0000) >> 16;
508 return (
Value & 0x0000ff00) >> 8;
511 return Value & 0x000000ff;
522 if ((int64_t)
Value < 0) {
530 Value |= isAdd << 23;
543 if ((int64_t)
Value < 0) {
558 if ((int64_t)
Value < 0) {
564 out |= (
Value & 0x800) << 15;
565 out |= (
Value & 0x700) << 4;
566 out |= (
Value & 0x0FF);
579 dyn_cast<MCSymbolRefExpr>(
Fixup.getValue()))
582 return 0xffffff & ((
Value - 8) >> 2);
585 if (!isInt<25>(
Value)) {
593 bool I =
Value & 0x800000;
594 bool J1 =
Value & 0x400000;
595 bool J2 =
Value & 0x200000;
602 out |= (
Value & 0x1FF800) << 5;
603 out |= (
Value & 0x0007FF);
609 if (!isInt<21>(
Value)) {
617 out |= (
Value & 0x80000) << 7;
618 out |= (
Value & 0x40000) >> 7;
619 out |= (
Value & 0x20000) >> 4;
620 out |= (
Value & 0x1F800) << 5;
621 out |= (
Value & 0x007FF);
626 if (!isInt<25>(
Value - 4) ||
630 !isInt<23>(
Value - 4))) {
648 uint32_t signBit = (offset & 0x800000) >> 23;
649 uint32_t I1Bit = (offset & 0x400000) >> 22;
650 uint32_t J1Bit = (I1Bit ^ 0x1) ^ signBit;
651 uint32_t I2Bit = (offset & 0x200000) >> 21;
652 uint32_t J2Bit = (I2Bit ^ 0x1) ^ signBit;
653 uint32_t imm10Bits = (offset & 0x1FF800) >> 11;
654 uint32_t imm11Bits = (offset & 0x000007FF);
674 if (
Value % 4 != 0) {
681 dyn_cast<MCSymbolRefExpr>(
Fixup.getValue()))
684 uint32_t signBit = (offset & 0x400000) >> 22;
685 uint32_t I1Bit = (offset & 0x200000) >> 21;
686 uint32_t J1Bit = (I1Bit ^ 0x1) ^ signBit;
687 uint32_t I2Bit = (offset & 0x100000) >> 20;
688 uint32_t J2Bit = (I2Bit ^ 0x1) ^ signBit;
689 uint32_t imm10HBits = (offset & 0xFFC00) >> 10;
690 uint32_t imm10LBits = (offset & 0x3FF);
702 if (!STI->
hasFeature(ARM::FeatureThumb2) && IsResolved) {
704 if (FixupDiagnostic) {
710 return ((
Value - 4) >> 2) & 0xff;
715 if ((int64_t)Value < 2 || Value > 0x82 ||
Value & 1) {
722 return ((Binary & 0x20) << 4) | ((Binary & 0x1f) << 3);
730 if (FixupDiagnostic) {
735 return ((
Value - 4) >> 1) & 0x7ff;
741 if (FixupDiagnostic) {
746 return ((
Value - 4) >> 1) & 0xff;
751 if ((int64_t)
Value < 0) {
761 return Value | (isAdd << 23);
771 if ((int64_t)
Value < 0) {
781 Value |= isAdd << 23;
798 if ((int64_t)
Value < 0) {
812 Value |= isAdd << 23;
830 if ((int64_t)
Value < 0) {
840 EncValue |= (
Value & 0x800) << 15;
841 EncValue |= (
Value & 0x700) << 4;
842 EncValue |= (
Value & 0xff);
847 if (FixupDiagnostic) {
858 if (FixupDiagnostic) {
865 out |= (((
Value - 4) >> 1) & 0x1) << 11;
866 out |= (((
Value - 4) >> 1) & 0x7fe);
867 out |= (((
Value - 4) >> 1) & HighBitMask) << 5;
877 if (FixupDiagnostic) {
887 if (FixupDiagnostic) {
894 real_value = -real_value;
895 out |= ((real_value >> 1) & 0x1) << 11;
896 out |= ((real_value >> 1) & 0x7fe);
907 const unsigned FixupKind =
Fixup.getKind();
911 assert(
Sym &&
"How did we resolve this?");
918 if (
Sym->isExternal())
923 if (
Sym &&
Sym->isELF()) {
924 unsigned Type = cast<MCSymbolELF>(
Sym)->getType();
1078 unsigned Kind =
Fixup.getKind();
1091 unsigned FullSizeBytes;
1095 assert(NumBytes <= FullSizeBytes &&
"Invalid fixup size!");
1101 for (
unsigned i = 0; i != NumBytes; ++i) {
1154 unsigned CFARegister = ARM::SP;
1155 int CFARegisterOffset = 0;
1158 int FloatRegCount = 0;
1162 switch (Inst.getOperation()) {
1164 CFARegisterOffset = Inst.getOffset();
1168 CFARegisterOffset = Inst.getOffset();
1175 if (ARMMCRegisterClasses[ARM::GPRRegClassID].
contains(Reg))
1176 RegOffsets[Reg] = Inst.getOffset();
1177 else if (ARMMCRegisterClasses[ARM::DPRRegClassID].
contains(Reg)) {
1178 RegOffsets[Reg] = Inst.getOffset();
1182 llvm::dbgs() <<
".cfi_offset on unknown register="
1183 << Inst.getRegister() <<
"\n");
1194 <<
"CFI directive not compatible with compact "
1195 "unwind encoding, opcode=" << Inst.getOperation()
1203 if ((CFARegister == ARM::SP) && (CFARegisterOffset == 0))
1207 if (CFARegister != ARM::R7) {
1210 <<
" instead of r7\n");
1213 int StackAdjust = CFARegisterOffset - 8;
1214 if (RegOffsets.
lookup(ARM::LR) != (-4 - StackAdjust)) {
1217 <<
"LR not saved as standard frame, StackAdjust="
1219 <<
", CFARegisterOffset=" << CFARegisterOffset
1220 <<
", lr save at offset=" << RegOffsets[14] <<
"\n");
1223 if (RegOffsets.
lookup(ARM::R7) != (-8 - StackAdjust)) {
1225 llvm::dbgs() <<
"r7 not saved as standard frame\n");
1231 switch (StackAdjust) {
1235 CompactUnwindEncoding |= 0x00400000;
1238 CompactUnwindEncoding |= 0x00800000;
1241 CompactUnwindEncoding |= 0x00C00000;
1245 <<
".cfi_def_cfa stack adjust ("
1246 << StackAdjust <<
") out of range\n");
1263 int CurOffset = -8 - StackAdjust;
1264 for (
auto CSReg : GPRCSRegs) {
1269 int RegOffset =
Offset->second;
1270 if (RegOffset != CurOffset - 4) {
1273 << RegOffset <<
" but only supported at "
1274 << CurOffset <<
"\n");
1277 CompactUnwindEncoding |= CSReg.Encoding;
1282 if (FloatRegCount == 0)
1283 return CompactUnwindEncoding;
1286 CompactUnwindEncoding &=
~CU::UNWIND_ARM_MODE_MASK;
1291 if (FloatRegCount > 4) {
1293 llvm::dbgs() <<
"unsupported number of D registers saved ("
1294 << FloatRegCount <<
")\n");
1301 static unsigned FPRCSRegs[] = { ARM::D8, ARM::D10, ARM::D12, ARM::D14 };
1302 for (
int Idx = FloatRegCount - 1;
Idx >= 0; --
Idx) {
1306 llvm::dbgs() << FloatRegCount <<
" D-regs saved, but "
1310 }
else if (
Offset->second != CurOffset - 8) {
1312 llvm::dbgs() << FloatRegCount <<
" D-regs saved, but "
1314 <<
" saved at " <<
Offset->second
1315 <<
", expected at " << CurOffset - 8
1322 return CompactUnwindEncoding | ((FloatRegCount - 1) << 8);
unsigned const MachineRegisterInfo * MRI
static unsigned getFixupKindNumBytes(unsigned Kind)
The number of bytes the fixup may change.
static uint32_t swapHalfWords(uint32_t Value, bool IsLittleEndian)
static MCAsmBackend * createARMAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options, support::endianness Endian)
static unsigned getFixupKindContainerSizeBytes(unsigned Kind)
getFixupKindContainerSizeBytes - The number of bytes of the container involved in big endian.
static uint32_t joinHalfWords(uint32_t FirstHalf, uint32_t SecondHalf, bool IsLittleEndian)
static const char * checkPCRelOffset(uint64_t Value, int64_t Min, int64_t Max)
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
#define DEBUG_WITH_TYPE(TYPE, X)
DEBUG_WITH_TYPE macro - This macro should be used by passes to emit debug information.
static RegisterPass< DebugifyFunctionPass > DF("debugify-function", "Attach debug info to a function")
PowerPC TLS Dynamic Call Fixup
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file implements the StringSwitch template, which mimics a switch() statement whose cases are str...
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
const MachO::CPUSubTypeARM Subtype
uint32_t generateCompactUnwindEncoding(const MCDwarfFrameInfo *FI, const MCContext *Ctxt) const override
Generate compact unwind encoding for the function based on the CFI instructions.
const char * reasonForFixupRelaxation(const MCFixup &Fixup, uint64_t Value) const
void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target, MutableArrayRef< char > Data, uint64_t Value, bool IsResolved, const MCSubtargetInfo *STI) const override
Apply the Value for given Fixup into the provided data fragment, at the offset specified by the fixup...
const MCFixupKindInfo & getFixupKindInfo(MCFixupKind Kind) const override
Get information on a fixup kind.
unsigned getNumFixupKinds() const override
Get the number of target specific fixup kinds.
bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target) override
Hook to check if a relocation is needed for some target specific reason.
bool hasNOP(const MCSubtargetInfo *STI) const
unsigned getRelaxedOpcode(unsigned Op, const MCSubtargetInfo &STI) const
unsigned adjustFixupValue(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target, uint64_t Value, bool IsResolved, MCContext &Ctx, const MCSubtargetInfo *STI) const
bool writeNopData(raw_ostream &OS, uint64_t Count, const MCSubtargetInfo *STI) const override
Write an (optimal) nop sequence of Count bytes to the given output.
std::optional< MCFixupKind > getFixupKind(StringRef Name) const override
Map a relocation name used in .reloc to a fixup kind.
void relaxInstruction(MCInst &Inst, const MCSubtargetInfo &STI) const override
Relax the instruction in the given fragment to the next wider instruction.
bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value, const MCRelaxableFragment *DF, const MCAsmLayout &Layout) const override
Simple predicate for targets where !Resolved implies requiring relaxation.
bool mayNeedRelaxation(const MCInst &Inst, const MCSubtargetInfo &STI) const override
Check whether the given instruction may need relaxation.
void handleAssemblerFlag(MCAssemblerFlag Flag) override
Handle any target-specific assembler flags. By default, do nothing.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
bool empty() const
empty - Check if the array is empty.
This class represents an Operation in the Expression.
ValueT lookup(const_arg_type_t< KeyT > Val) const
lookup - Return the entry for the specified key, or a default constructed value if no such entry exis...
iterator find(const_arg_type_t< KeyT > Val)
Generic interface to target specific assembler backends.
bool isDarwinCanonicalPersonality(const MCSymbol *Sym) const
virtual const MCFixupKindInfo & getFixupKindInfo(MCFixupKind Kind) const
Get information on a fixup kind.
const support::endianness Endian
Encapsulates the layout of an assembly file at a particular point in time.
Context object for machine code objects.
bool emitCompactUnwindNonCanonical() const
void reportError(SMLoc L, const Twine &Msg)
Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...
Instances of this class represent a single low-level machine instruction.
void dump_pretty(raw_ostream &OS, const MCInstPrinter *Printer=nullptr, StringRef Separator=" ", const MCRegisterInfo *RegInfo=nullptr) const
Dump the MCInst as prettily as possible using the additional MC structures, if given.
unsigned getOpcode() const
void addOperand(const MCOperand Op)
void setOpcode(unsigned Op)
static MCOperand createReg(unsigned Reg)
static MCOperand createImm(int64_t Val)
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
std::optional< unsigned > getLLVMRegNum(unsigned RegNum, bool isEH) const
Map a dwarf register back to a target register.
const char * getName(MCRegister RegNo) const
Return the human-readable symbolic target-specific name for the specified physical register.
A relaxable fragment holds on to its MCInst, since it may need to be relaxed during the assembler lay...
Generic base class for all target subtargets.
bool hasFeature(unsigned Feature) const
const Triple & getTargetTriple() const
Represent a reference to a symbol from inside an expression.
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
This represents an "assembler immediate".
MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...
SmallString - A SmallString is just a SmallVector with methods and accessors that make it work better...
StringRef - Represent a constant reference to a string, i.e.
A switch()-like statement whose cases are string literals.
StringSwitch & Case(StringLiteral S, T Value)
Target - Wrapper for Target specific information.
Triple - Helper class for working with autoconf configuration names.
bool isThumb() const
Tests whether the target is Thumb (little and big endian).
ObjectFormatType getObjectFormat() const
Get the object format for this triple.
OSType getOS() const
Get the parsed operating system type of this triple.
bool isOSWindows() const
Tests whether the OS is Windows.
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
The instances of the Type class are immutable: once they are created, they are never changed.
LLVM Value Representation.
This class implements an extremely fast bulk output stream that can only output to a stream.
raw_ostream & write(unsigned char C)
A raw_ostream that writes to an SmallVector or SmallString.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
CompactUnwindEncodings
Compact unwind encoding values.
@ UNWIND_ARM_FRAME_SECOND_PUSH_R10
@ UNWIND_ARM_FRAME_FIRST_PUSH_R6
@ UNWIND_ARM_FRAME_SECOND_PUSH_R11
@ UNWIND_ARM_DWARF_SECTION_OFFSET
@ UNWIND_ARM_FRAME_FIRST_PUSH_R4
@ UNWIND_ARM_FRAME_SECOND_PUSH_R9
@ UNWIND_ARM_FRAME_SECOND_PUSH_R8
@ UNWIND_ARM_FRAME_STACK_ADJUST_MASK
@ UNWIND_ARM_FRAME_SECOND_PUSH_R12
@ UNWIND_ARM_FRAME_D_REG_COUNT_MASK
@ UNWIND_ARM_MODE_FRAME_D
@ UNWIND_ARM_FRAME_FIRST_PUSH_R5
int getSOImmVal(unsigned Arg)
getSOImmVal - Given a 32-bit immediate, if it is something that can fit into an shifter_operand immed...
int getT2SOImmVal(unsigned Arg)
getT2SOImmVal - Given a 32-bit immediate, if it is something that can fit into a Thumb-2 shifter_oper...
@ fixup_thumb_adr_pcrel_10
@ fixup_arm_thumb_upper_8_15
@ fixup_arm_thumb_lower_0_7
@ fixup_arm_pcrel_10_unscaled
@ fixup_arm_thumb_upper_0_7
@ fixup_bfcsel_else_target
@ fixup_arm_ldst_pcrel_12
@ fixup_arm_thumb_lower_8_15
void write(void *memory, value_type value, endianness endian)
Write a value to memory with a particular endianness.
This is an optimization pass for GlobalISel generic memory operations.
MCAsmBackend * createARMBEAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
MCAsmBackend * createARMLEAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
MCFixupKind
Extensible enumeration to represent the type of a fixup.
@ FK_SecRel_2
A two-byte section relative fixup.
@ FirstLiteralRelocationKind
The range [FirstLiteralRelocationKind, MaxTargetFixupKind) is used for relocations coming from ....
@ FK_Data_1
A one-byte fixup.
@ FK_Data_4
A four-byte fixup.
@ FK_SecRel_4
A four-byte section relative fixup.
@ FK_Data_2
A two-byte fixup.
@ MCAF_Code16
.code16 (X86) / .code 16 (ARM)
@ MCAF_Code32
.code32 (X86) / .code 32 (ARM)
DWARFExpression::Operation Op
const MCSymbol * Personality
std::vector< MCCFIInstruction > Instructions
Target independent information on a fixup kind.
@ FKF_IsAlignedDownTo32Bits
Should this fixup kind force a 4-byte aligned effective PC value?
@ FKF_Constant
This fixup kind should be resolved if defined.
@ FKF_IsPCRel
Is this fixup kind PCrelative? This is used by the assembler backend to evaluate fixup values in a ta...