LLVM  14.0.0git
InOrderIssueStage.cpp
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1 //===---------------------- InOrderIssueStage.cpp ---------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 ///
10 /// InOrderIssueStage implements an in-order execution pipeline.
11 ///
12 //===----------------------------------------------------------------------===//
13 
18 #include "llvm/MCA/Instruction.h"
19 
20 #define DEBUG_TYPE "llvm-mca"
21 namespace llvm {
22 namespace mca {
23 
25  IR.invalidate();
26  CyclesLeft = 0;
28 }
29 
30 void StallInfo::update(const InstRef &Inst, unsigned Cycles, StallKind SK) {
31  IR = Inst;
32  CyclesLeft = Cycles;
33  Kind = SK;
34 }
35 
37  if (!isValid())
38  return;
39 
40  if (!CyclesLeft)
41  return;
42 
43  --CyclesLeft;
44 }
45 
46 InOrderIssueStage::InOrderIssueStage(const MCSubtargetInfo &STI,
47  RegisterFile &PRF, CustomBehaviour &CB,
48  LSUnit &LSU)
49  : STI(STI), PRF(PRF), RM(STI.getSchedModel()), CB(CB), LSU(LSU),
50  NumIssued(), SI(), CarryOver(), Bandwidth(), LastWriteBackCycle() {}
51 
53  return STI.getSchedModel().IssueWidth;
54 }
55 
57  return !IssuedInst.empty() || SI.isValid() || CarriedOver;
58 }
59 
61  if (SI.isValid() || CarriedOver)
62  return false;
63 
64  const Instruction &Inst = *IR.getInstruction();
65  unsigned NumMicroOps = Inst.getNumMicroOps();
66  const InstrDesc &Desc = Inst.getDesc();
67 
68  bool ShouldCarryOver = NumMicroOps > getIssueWidth();
69  if (Bandwidth < NumMicroOps && !ShouldCarryOver)
70  return false;
71 
72  // Instruction with BeginGroup must be the first instruction to be issued in a
73  // cycle.
74  if (Desc.BeginGroup && NumIssued != 0)
75  return false;
76 
77  return true;
78 }
79 
80 static bool hasResourceHazard(const ResourceManager &RM, const InstRef &IR) {
81  if (RM.checkAvailability(IR.getInstruction()->getDesc())) {
82  LLVM_DEBUG(dbgs() << "[E] Stall #" << IR << '\n');
83  return true;
84  }
85 
86  return false;
87 }
88 
89 static unsigned findFirstWriteBackCycle(const InstRef &IR) {
90  unsigned FirstWBCycle = IR.getInstruction()->getLatency();
91  for (const WriteState &WS : IR.getInstruction()->getDefs()) {
92  int CyclesLeft = WS.getCyclesLeft();
93  if (CyclesLeft == UNKNOWN_CYCLES)
94  CyclesLeft = WS.getLatency();
95  if (CyclesLeft < 0)
96  CyclesLeft = 0;
97  FirstWBCycle = std::min(FirstWBCycle, (unsigned)CyclesLeft);
98  }
99  return FirstWBCycle;
100 }
101 
102 /// Return a number of cycles left until register requirements of the
103 /// instructions are met.
104 static unsigned checkRegisterHazard(const RegisterFile &PRF,
105  const MCSubtargetInfo &STI,
106  const InstRef &IR) {
107  for (const ReadState &RS : IR.getInstruction()->getUses()) {
108  RegisterFile::RAWHazard Hazard = PRF.checkRAWHazards(STI, RS);
109  if (Hazard.isValid())
110  return Hazard.hasUnknownCycles() ? 1U : Hazard.CyclesLeft;
111  }
112 
113  return 0;
114 }
115 
116 bool InOrderIssueStage::canExecute(const InstRef &IR) {
117  assert(!SI.getCyclesLeft() && "Should not have reached this code!");
118  assert(!SI.isValid() && "Should not have reached this code!");
119 
120  if (unsigned Cycles = checkRegisterHazard(PRF, STI, IR)) {
122  return false;
123  }
124 
125  if (hasResourceHazard(RM, IR)) {
126  SI.update(IR, /* delay */ 1, StallInfo::StallKind::DISPATCH);
127  return false;
128  }
129 
130  if (IR.getInstruction()->isMemOp() && !LSU.isReady(IR)) {
131  // This load (store) aliases with a preceding store (load). Delay
132  // it until the depenency is cleared.
133  SI.update(IR, /* delay */ 1, StallInfo::StallKind::LOAD_STORE);
134  return false;
135  }
136 
137  if (unsigned CustomStallCycles = CB.checkCustomHazard(IssuedInst, IR)) {
138  SI.update(IR, CustomStallCycles, StallInfo::StallKind::CUSTOM_STALL);
139  return false;
140  }
141 
142  if (LastWriteBackCycle) {
143  if (!IR.getInstruction()->getDesc().RetireOOO) {
144  unsigned NextWriteBackCycle = findFirstWriteBackCycle(IR);
145  // Delay the instruction to ensure that writes happen in program order.
146  if (NextWriteBackCycle < LastWriteBackCycle) {
147  SI.update(IR, LastWriteBackCycle - NextWriteBackCycle,
149  return false;
150  }
151  }
152  }
153 
154  return true;
155 }
156 
158  unsigned SourceIndex,
159  const MCSubtargetInfo &STI,
160  SmallVectorImpl<unsigned> &UsedRegs) {
161  assert(!IS.isEliminated());
162 
163  for (ReadState &RS : IS.getUses())
164  PRF.addRegisterRead(RS, STI);
165 
166  for (WriteState &WS : IS.getDefs())
167  PRF.addRegisterWrite(WriteRef(SourceIndex, &WS), UsedRegs);
168 }
169 
170 void InOrderIssueStage::notifyInstructionIssued(const InstRef &IR,
171  ArrayRef<ResourceUse> UsedRes) {
172  notifyEvent<HWInstructionEvent>(
173  HWInstructionEvent(HWInstructionEvent::Ready, IR));
174  notifyEvent<HWInstructionEvent>(HWInstructionIssuedEvent(IR, UsedRes));
175 
176  LLVM_DEBUG(dbgs() << "[E] Issued #" << IR << "\n");
177 }
178 
179 void InOrderIssueStage::notifyInstructionDispatched(
180  const InstRef &IR, unsigned Ops, ArrayRef<unsigned> UsedRegs) {
181  notifyEvent<HWInstructionEvent>(
182  HWInstructionDispatchedEvent(IR, UsedRegs, Ops));
183 
184  LLVM_DEBUG(dbgs() << "[E] Dispatched #" << IR << "\n");
185 }
186 
187 void InOrderIssueStage::notifyInstructionExecuted(const InstRef &IR) {
188  notifyEvent<HWInstructionEvent>(
189  HWInstructionEvent(HWInstructionEvent::Executed, IR));
190  LLVM_DEBUG(dbgs() << "[E] Instruction #" << IR << " is executed\n");
191 }
192 
193 void InOrderIssueStage::notifyInstructionRetired(const InstRef &IR,
194  ArrayRef<unsigned> FreedRegs) {
195  notifyEvent<HWInstructionEvent>(HWInstructionRetiredEvent(IR, FreedRegs));
196  LLVM_DEBUG(dbgs() << "[E] Retired #" << IR << " \n");
197 }
198 
200  Instruction &IS = *IR.getInstruction();
201  if (IS.isMemOp())
202  IS.setLSUTokenID(LSU.dispatch(IR));
203 
204  if (llvm::Error E = tryIssue(IR))
205  return E;
206 
207  if (SI.isValid())
208  notifyStallEvent();
209 
210  return llvm::ErrorSuccess();
211 }
212 
213 llvm::Error InOrderIssueStage::tryIssue(InstRef &IR) {
214  Instruction &IS = *IR.getInstruction();
215  unsigned SourceIndex = IR.getSourceIndex();
216  const InstrDesc &Desc = IS.getDesc();
217 
218  if (!canExecute(IR)) {
219  LLVM_DEBUG(dbgs() << "[N] Stalled #" << SI.getInstruction() << " for "
220  << SI.getCyclesLeft() << " cycles\n");
221  Bandwidth = 0;
222  return llvm::ErrorSuccess();
223  }
224 
225  unsigned RCUTokenID = RetireControlUnit::UnhandledTokenID;
226  IS.dispatch(RCUTokenID);
227 
229  addRegisterReadWrite(PRF, IS, SourceIndex, STI, UsedRegs);
230 
231  unsigned NumMicroOps = IS.getNumMicroOps();
232  notifyInstructionDispatched(IR, NumMicroOps, UsedRegs);
233 
234  SmallVector<ResourceUse, 4> UsedResources;
235  RM.issueInstruction(Desc, UsedResources);
236  IS.execute(SourceIndex);
237 
238  if (IS.isMemOp())
239  LSU.onInstructionIssued(IR);
240 
241  // Replace resource masks with valid resource processor IDs.
242  for (ResourceUse &Use : UsedResources) {
243  uint64_t Mask = Use.first.first;
244  Use.first.first = RM.resolveResourceMask(Mask);
245  }
246  notifyInstructionIssued(IR, UsedResources);
247 
248  bool ShouldCarryOver = NumMicroOps > Bandwidth;
249  if (ShouldCarryOver) {
250  CarryOver = NumMicroOps - Bandwidth;
251  CarriedOver = IR;
252  Bandwidth = 0;
253  NumIssued += Bandwidth;
254  LLVM_DEBUG(dbgs() << "[N] Carry over #" << IR << " \n");
255  } else {
256  NumIssued += NumMicroOps;
257  Bandwidth = Desc.EndGroup ? 0 : Bandwidth - NumMicroOps;
258  }
259 
260  // If the instruction has a latency of 0, we need to handle
261  // the execution and retirement now.
262  if (IS.isExecuted()) {
263  PRF.onInstructionExecuted(&IS);
265  notifyEvent<HWInstructionEvent>(
266  HWInstructionEvent(HWInstructionEvent::Executed, IR));
267  LLVM_DEBUG(dbgs() << "[E] Instruction #" << IR << " is executed\n");
268 
269  retireInstruction(IR);
270  return llvm::ErrorSuccess();
271  }
272 
273  IssuedInst.push_back(IR);
274 
275  if (!IR.getInstruction()->getDesc().RetireOOO)
276  LastWriteBackCycle = IS.getCyclesLeft();
277 
278  return llvm::ErrorSuccess();
279 }
280 
281 void InOrderIssueStage::updateIssuedInst() {
282  // Update other instructions. Executed instructions will be retired during the
283  // next cycle.
284  unsigned NumExecuted = 0;
285  for (auto I = IssuedInst.begin(), E = IssuedInst.end();
286  I != (E - NumExecuted);) {
287  InstRef &IR = *I;
288  Instruction &IS = *IR.getInstruction();
289 
290  IS.cycleEvent();
291  if (!IS.isExecuted()) {
292  LLVM_DEBUG(dbgs() << "[N] Instruction #" << IR
293  << " is still executing\n");
294  ++I;
295  continue;
296  }
297 
298  PRF.onInstructionExecuted(&IS);
300  notifyInstructionExecuted(IR);
301  ++NumExecuted;
302 
303  retireInstruction(*I);
304 
305  std::iter_swap(I, E - NumExecuted);
306  }
307 
308  if (NumExecuted)
309  IssuedInst.resize(IssuedInst.size() - NumExecuted);
310 }
311 
312 void InOrderIssueStage::updateCarriedOver() {
313  if (!CarriedOver)
314  return;
315 
316  assert(!SI.isValid() && "A stalled instruction cannot be carried over.");
317 
318  if (CarryOver > Bandwidth) {
319  CarryOver -= Bandwidth;
320  Bandwidth = 0;
321  LLVM_DEBUG(dbgs() << "[N] Carry over (" << CarryOver << "uops left) #"
322  << CarriedOver << " \n");
323  return;
324  }
325 
326  LLVM_DEBUG(dbgs() << "[N] Carry over (complete) #" << CarriedOver << " \n");
327 
328  if (CarriedOver.getInstruction()->getDesc().EndGroup)
329  Bandwidth = 0;
330  else
331  Bandwidth -= CarryOver;
332 
333  CarriedOver = InstRef();
334  CarryOver = 0;
335 }
336 
337 void InOrderIssueStage::retireInstruction(InstRef &IR) {
338  Instruction &IS = *IR.getInstruction();
339  IS.retire();
340 
342  for (const WriteState &WS : IS.getDefs())
343  PRF.removeRegisterWrite(WS, FreedRegs);
344 
345  if (IS.isMemOp())
347 
348  notifyInstructionRetired(IR, FreedRegs);
349 }
350 
351 void InOrderIssueStage::notifyStallEvent() {
352  assert(SI.getCyclesLeft() && "A zero cycles stall?");
353  assert(SI.isValid() && "Invalid stall information found!");
354 
355  const InstRef &IR = SI.getInstruction();
356 
357  switch (SI.getStallKind()) {
358  default:
359  break;
361  notifyEvent<HWStallEvent>(
362  HWStallEvent(HWStallEvent::RegisterFileStall, IR));
363  notifyEvent<HWPressureEvent>(
364  HWPressureEvent(HWPressureEvent::REGISTER_DEPS, IR));
365  break;
366  }
368  notifyEvent<HWStallEvent>(
369  HWStallEvent(HWStallEvent::DispatchGroupStall, IR));
370  notifyEvent<HWPressureEvent>(
371  HWPressureEvent(HWPressureEvent::RESOURCES, IR));
372  break;
373  }
375  notifyEvent<HWStallEvent>(
376  HWStallEvent(HWStallEvent::CustomBehaviourStall, IR));
377  break;
378  }
379  }
380 }
381 
383  NumIssued = 0;
384  Bandwidth = getIssueWidth();
385 
386  PRF.cycleStart();
387  LSU.cycleEvent();
388 
389  // Release consumed resources.
391  RM.cycleEvent(Freed);
392 
393  updateIssuedInst();
394 
395  // Continue to issue the instruction carried over from the previous cycle
396  updateCarriedOver();
397 
398  // Issue instructions scheduled for this cycle
399  if (SI.isValid()) {
400  if (!SI.getCyclesLeft()) {
401  // Make a copy of the reference, and try issue it again.
402  // Do not take the instruction reference because SI.clear() will
403  // invalidate it.
404  InstRef IR = SI.getInstruction();
405  SI.clear();
406 
407  if (llvm::Error E = tryIssue(IR))
408  return E;
409  }
410 
411  if (SI.getCyclesLeft()) {
412  // The instruction is still stalled, cannot issue any new instructions in
413  // this cycle.
414  notifyStallEvent();
415  Bandwidth = 0;
416  return llvm::ErrorSuccess();
417  }
418  }
419 
420  assert((NumIssued <= getIssueWidth()) && "Overflow.");
421  return llvm::ErrorSuccess();
422 }
423 
425  PRF.cycleEnd();
426  SI.cycleEnd();
427 
428  if (LastWriteBackCycle > 0)
429  --LastWriteBackCycle;
430 
431  return llvm::ErrorSuccess();
432 }
433 
434 } // namespace mca
435 } // namespace llvm
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
llvm::mca::Instruction::dispatch
void dispatch(unsigned RCUTokenID)
Definition: Instruction.cpp:151
llvm::mca::HWStallEvent::CustomBehaviourStall
@ CustomBehaviourStall
Definition: HWEventListener.h:118
llvm::mca::checkRegisterHazard
static unsigned checkRegisterHazard(const RegisterFile &PRF, const MCSubtargetInfo &STI, const InstRef &IR)
Return a number of cycles left until register requirements of the instructions are met.
Definition: InOrderIssueStage.cpp:104
llvm::MCSubtargetInfo::getSchedModel
const MCSchedModel & getSchedModel() const
Get the machine model for this subtarget's CPU.
Definition: MCSubtargetInfo.h:162
llvm::mca::RegisterFile::removeRegisterWrite
void removeRegisterWrite(const WriteState &WS, MutableArrayRef< unsigned > FreedPhysRegs)
Definition: RegisterFile.cpp:332
llvm::mca::StallInfo::getStallKind
StallKind getStallKind() const
Definition: InOrderIssueStage.h:43
llvm::SmallVector< unsigned, 4 >
llvm::mca::RegisterFile::checkRAWHazards
RAWHazard checkRAWHazards(const MCSubtargetInfo &STI, const ReadState &RS) const
Definition: RegisterFile.cpp:568
llvm::mca::StallInfo::getInstruction
const InstRef & getInstruction() const
Definition: InOrderIssueStage.h:45
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A resource manager for processor resource units and groups.
Definition: ResourceManager.h:311
llvm::mca::LSUnit
Default Load/Store Unit (LS Unit) for simulated processors.
Definition: LSUnit.h:401
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int CyclesLeft
Definition: RegisterFile.h:241
RetireControlUnit.h
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Definition: ResourceManager.cpp:166
llvm::mca::HWStallEvent::RegisterFileStall
@ RegisterFileStall
Definition: HWEventListener.h:111
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static void addRegisterReadWrite(RegisterFile &PRF, Instruction &IS, unsigned SourceIndex, const MCSubtargetInfo &STI, SmallVectorImpl< unsigned > &UsedRegs)
Definition: InOrderIssueStage.cpp:157
llvm::mca::Instruction::getCyclesLeft
int getCyclesLeft() const
Definition: Instruction.h:630
llvm::mca::StallInfo::isValid
bool isValid() const
Definition: InOrderIssueStage.h:48
llvm::mca::Instruction
An instruction propagated through the simulated instruction pipeline.
Definition: Instruction.h:569
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Definition: RegisterFile.h:239
llvm::mca::Instruction::isEliminated
bool isEliminated() const
Definition: Instruction.h:657
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std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
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Definition: Instruction.h:479
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Definition: InOrderIssueStage.h:28
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Definition: Instruction.h:524
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void cycleStart()
Definition: RegisterFile.cpp:100
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llvm::mca::RegisterFile::getNumRegisterFiles
unsigned getNumRegisterFiles() const
Definition: RegisterFile.h:293
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bool hasUnknownCycles() const
Definition: RegisterFile.h:245
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dbgs() - This returns a reference to a raw_ostream for debugging messages.
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Definition: InOrderIssueStage.cpp:24
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static const unsigned UnhandledTokenID
Definition: RetireControlUnit.h:109
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Definition: HWEventListener.h:114
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Definition: Instruction.cpp:161
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Definition: RegisterFile.h:302
InOrderIssueStage.h
llvm::mca::ReadState
Tracks register operand latency in cycles.
Definition: Instruction.h:326
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Definition: Lint.cpp:744
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llvm::mca::InOrderIssueStage::cycleEnd
Error cycleEnd() override
Called once at the end of each cycle.
Definition: InOrderIssueStage.cpp:424
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Allocates LS resources for instruction IR.
Definition: LSUnit.cpp:69
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Definition: RegisterFile.h:38
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@ CUSTOM_STALL
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Definition: InOrderIssueStage.cpp:30
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Definition: RegisterFile.h:244
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Definition: HWEventListener.h:139
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const InstrDesc & getDesc() const
Definition: Instruction.h:528
llvm::mca::InstrDesc
An instruction descriptor.
Definition: Instruction.h:447
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Definition: HWEventListener.h:43
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Definition: MCSchedule.h:257
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Class which can be overriden by targets to enforce instruction dependencies and behaviours that aren'...
Definition: CustomBehaviour.h:56
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Definition: Error.h:329
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#define I(x, y, z)
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static bool hasResourceHazard(const ResourceManager &RM, const InstRef &IR)
Definition: InOrderIssueStage.cpp:80
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void onInstructionExecuted(const InstRef &IR) override
Definition: LSUnit.cpp:232
assert
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SI
StandardInstrumentations SI(Debug, VerifyEach)
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Definition: Instruction.h:34
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@ DEFAULT
llvm::mca::InstRef
An InstRef contains both a SourceMgr index and Instruction pair.
Definition: Instruction.h:686
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unsigned getNumMicroOps() const
Definition: Instruction.h:531
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Returns true if some instructions are still executing this stage.
Definition: InOrderIssueStage.cpp:56
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Definition: AArch64ISelLowering.h:472
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virtual unsigned checkCustomHazard(ArrayRef< InstRef > IssuedInst, const InstRef &IR)
Before the llvm-mca pipeline dispatches an instruction, it first checks for any register or resource ...
Definition: CustomBehaviour.cpp:21
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Definition: InOrderIssueStage.h:39
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bool isAvailable(const InstRef &) const override
Returns true if it can execute IR during this cycle.
Definition: InOrderIssueStage.cpp:60
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Definition: RegisterFile.cpp:105
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virtual void onInstructionRetired(const InstRef &IR)
Definition: LSUnit.cpp:213
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virtual void onInstructionIssued(const InstRef &IR)
Definition: LSUnit.h:328
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Definition: InOrderIssueStage.cpp:36
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void addRegisterRead(ReadState &RS, const MCSubtargetInfo &STI) const
Definition: RegisterFile.cpp:618
llvm::mca::RegisterFile
Manages hardware register files, and tracks register definitions for register renaming purposes.
Definition: RegisterFile.h:83
llvm::mca::StallInfo::IR
InstRef IR
Definition: InOrderIssueStage.h:37
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Error execute(InstRef &IR) override
The primary action that this stage performs on instruction IR.
Definition: InOrderIssueStage.cpp:199
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unsigned CyclesLeft
Definition: InOrderIssueStage.h:38
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Lightweight error class with error context and mandatory checking.
Definition: Error.h:157
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std::pair< ResourceRef, ResourceCycles > ResourceUse
Definition: HWEventListener.h:63
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bool isReady(const InstRef &IR) const
Check if a peviously dispatched instruction IR is now ready for execution.
Definition: LSUnit.h:276
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void cycleEvent(SmallVectorImpl< ResourceRef > &ResourcesFreed)
Definition: ResourceManager.cpp:333
llvm::mca::RegisterFile::addRegisterWrite
void addRegisterWrite(WriteRef Write, MutableArrayRef< unsigned > UsedPhysRegs)
Definition: RegisterFile.cpp:228
llvm::mca::InstRef::invalidate
void invalidate()
Invalidate this reference.
Definition: Instruction.h:707
llvm::mca::InstructionBase::getUses
SmallVectorImpl< ReadState > & getUses()
Definition: Instruction.h:526
llvm::mca::InstrDesc::BeginGroup
unsigned BeginGroup
Definition: Instruction.h:478
llvm::mca::StallInfo::StallKind::DISPATCH
@ DISPATCH
llvm::SmallVectorImpl< unsigned >
llvm::mca::StallInfo::StallKind::LOAD_STORE
@ LOAD_STORE
llvm::mca::ResourceManager::issueInstruction
void issueInstruction(const InstrDesc &Desc, SmallVectorImpl< std::pair< ResourceRef, ResourceCycles >> &Pipes)
Definition: ResourceManager.cpp:306
llvm::mca::StallInfo::StallKind::DELAY
@ DELAY
RegisterFile.h
llvm::mca::InstructionBase::isMemOp
bool isMemOp() const
Definition: Instruction.h:562
llvm::mca::StallInfo::getCyclesLeft
unsigned getCyclesLeft() const
Definition: InOrderIssueStage.h:44
llvm::mca::LSUnitBase::cycleEvent
virtual void cycleEvent()
Definition: LSUnit.cpp:44
llvm::mca::HWPressureEvent::REGISTER_DEPS
@ REGISTER_DEPS
Definition: HWEventListener.h:141
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Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:75
llvm::mca::WriteState
Tracks uses of a register definition (e.g.
Definition: Instruction.h:197
llvm::mca::InOrderIssueStage::getIssueWidth
unsigned getIssueWidth() const
Definition: InOrderIssueStage.cpp:52
llvm::mca::Instruction::setLSUTokenID
void setLSUTokenID(unsigned LSUTok)
Definition: Instruction.h:624
llvm::Use
A Use represents the edge between a Value definition and its users.
Definition: Use.h:44
llvm::mca::InOrderIssueStage::cycleStart
Error cycleStart() override
Called once at the start of each cycle.
Definition: InOrderIssueStage.cpp:382
llvm::mca::HWInstructionEvent::Executed
@ Executed
Definition: HWEventListener.h:45
llvm::mca::findFirstWriteBackCycle
static unsigned findFirstWriteBackCycle(const InstRef &IR)
Definition: InOrderIssueStage.cpp:89