LLVM  14.0.0git
NVPTXProxyRegErasure.cpp
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1 //===- NVPTXProxyRegErasure.cpp - NVPTX Proxy Register Instruction Erasure -==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // The pass is needed to remove ProxyReg instructions and restore related
10 // registers. The instructions were needed at instruction selection stage to
11 // make sure that callseq_end nodes won't be removed as "dead nodes". This can
12 // happen when we expand instructions into libcalls and the call site doesn't
13 // care about the libcall chain. Call site cares about data flow only, and the
14 // latest data flow node happens to be before callseq_end. Therefore the node
15 // becomes dangling and "dead". The ProxyReg acts like an additional data flow
16 // node *after* the callseq_end in the chain and ensures that everything will be
17 // preserved.
18 //
19 //===----------------------------------------------------------------------===//
20 
21 #include "NVPTX.h"
27 
28 using namespace llvm;
29 
30 namespace llvm {
32 }
33 
34 namespace {
35 
36 struct NVPTXProxyRegErasure : public MachineFunctionPass {
37 public:
38  static char ID;
39  NVPTXProxyRegErasure() : MachineFunctionPass(ID) {
41  }
42 
43  bool runOnMachineFunction(MachineFunction &MF) override;
44 
45  StringRef getPassName() const override {
46  return "NVPTX Proxy Register Instruction Erasure";
47  }
48 
49  void getAnalysisUsage(AnalysisUsage &AU) const override {
51  }
52 
53 private:
54  void replaceMachineInstructionUsage(MachineFunction &MF, MachineInstr &MI);
55 
56  void replaceRegisterUsage(MachineInstr &Instr, MachineOperand &From,
57  MachineOperand &To);
58 };
59 
60 } // namespace
61 
63 
64 INITIALIZE_PASS(NVPTXProxyRegErasure, "nvptx-proxyreg-erasure", "NVPTX ProxyReg Erasure", false, false)
65 
66 bool NVPTXProxyRegErasure::runOnMachineFunction(MachineFunction &MF) {
68 
69  for (auto &BB : MF) {
70  for (auto &MI : BB) {
71  switch (MI.getOpcode()) {
72  case NVPTX::ProxyRegI1:
73  case NVPTX::ProxyRegI16:
74  case NVPTX::ProxyRegI32:
75  case NVPTX::ProxyRegI64:
76  case NVPTX::ProxyRegF16:
77  case NVPTX::ProxyRegF16x2:
78  case NVPTX::ProxyRegF32:
79  case NVPTX::ProxyRegF64:
80  replaceMachineInstructionUsage(MF, MI);
81  RemoveList.push_back(&MI);
82  break;
83  }
84  }
85  }
86 
87  for (auto *MI : RemoveList) {
88  MI->eraseFromParent();
89  }
90 
91  return !RemoveList.empty();
92 }
93 
94 void NVPTXProxyRegErasure::replaceMachineInstructionUsage(MachineFunction &MF,
95  MachineInstr &MI) {
96  auto &InOp = *MI.uses().begin();
97  auto &OutOp = *MI.defs().begin();
98 
99  assert(InOp.isReg() && "ProxyReg input operand should be a register.");
100  assert(OutOp.isReg() && "ProxyReg output operand should be a register.");
101 
102  for (auto &BB : MF) {
103  for (auto &I : BB) {
104  replaceRegisterUsage(I, OutOp, InOp);
105  }
106  }
107 }
108 
109 void NVPTXProxyRegErasure::replaceRegisterUsage(MachineInstr &Instr,
111  MachineOperand &To) {
112  for (auto &Op : Instr.uses()) {
113  if (Op.isReg() && Op.getReg() == From.getReg()) {
114  Op.setReg(To.getReg());
115  }
116  }
117 }
118 
120  return new NVPTXProxyRegErasure();
121 }
llvm::MachineInstr::uses
iterator_range< mop_iterator > uses()
Returns a range that includes all operands that are register uses.
Definition: MachineInstr.h:666
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:103
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1168
llvm::MachineFunctionPass
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Definition: MachineFunctionPass.h:30
llvm::initializeNVPTXProxyRegErasurePass
void initializeNVPTXProxyRegErasurePass(PassRegistry &)
TargetInstrInfo.h
llvm::MachineFunctionPass::getAnalysisUsage
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
Definition: MachineFunctionPass.cpp:102
NVPTX.h
MachineRegisterInfo.h
llvm::PassRegistry::getPassRegistry
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Definition: PassRegistry.cpp:31
INITIALIZE_PASS
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:37
llvm::AnalysisUsage
Represent the analysis usage information of a pass.
Definition: PassAnalysisSupport.h:47
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
llvm::PassRegistry
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:38
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
I
#define I(x, y, z)
Definition: MD5.cpp:59
MachineFunctionPass.h
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:360
llvm::MachineFunction
Definition: MachineFunction.h:230
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:321
MachineInstrBuilder.h
llvm::createNVPTXProxyRegErasurePass
MachineFunctionPass * createNVPTXProxyRegErasurePass()
Definition: NVPTXProxyRegErasure.cpp:119
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
From
BlockVerifier::State From
Definition: BlockVerifier.cpp:55
TargetRegisterInfo.h
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:37