LLVM  13.0.0git
MachineOperand.h
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1 //===-- llvm/CodeGen/MachineOperand.h - MachineOperand class ----*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the declaration of the MachineOperand class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_CODEGEN_MACHINEOPERAND_H
14 #define LLVM_CODEGEN_MACHINEOPERAND_H
15 
16 #include "llvm/ADT/DenseMap.h"
17 #include "llvm/CodeGen/Register.h"
18 #include "llvm/IR/Intrinsics.h"
19 #include "llvm/Support/DataTypes.h"
21 #include <cassert>
22 
23 namespace llvm {
24 
25 class BlockAddress;
26 class Constant;
27 class ConstantFP;
28 class ConstantInt;
29 class GlobalValue;
30 class MachineBasicBlock;
31 class MachineInstr;
32 class MachineRegisterInfo;
33 class MCCFIInstruction;
34 class MDNode;
35 class ModuleSlotTracker;
36 class TargetIntrinsicInfo;
37 class TargetRegisterInfo;
38 class hash_code;
39 class raw_ostream;
40 class MCSymbol;
41 
42 /// MachineOperand class - Representation of each machine instruction operand.
43 ///
44 /// This class isn't a POD type because it has a private constructor, but its
45 /// destructor must be trivial. Functions like MachineInstr::addOperand(),
46 /// MachineRegisterInfo::moveOperands(), and MF::DeleteMachineInstr() depend on
47 /// not having to call the MachineOperand destructor.
48 ///
50 public:
51  enum MachineOperandType : unsigned char {
52  MO_Register, ///< Register operand.
53  MO_Immediate, ///< Immediate operand
54  MO_CImmediate, ///< Immediate >64bit operand
55  MO_FPImmediate, ///< Floating-point immediate operand
56  MO_MachineBasicBlock, ///< MachineBasicBlock reference
57  MO_FrameIndex, ///< Abstract Stack Frame Index
58  MO_ConstantPoolIndex, ///< Address of indexed Constant in Constant Pool
59  MO_TargetIndex, ///< Target-dependent index+offset operand.
60  MO_JumpTableIndex, ///< Address of indexed Jump Table for switch
61  MO_ExternalSymbol, ///< Name of external global symbol
62  MO_GlobalAddress, ///< Address of a global value
63  MO_BlockAddress, ///< Address of a basic block
64  MO_RegisterMask, ///< Mask of preserved registers.
65  MO_RegisterLiveOut, ///< Mask of live-out registers.
66  MO_Metadata, ///< Metadata reference (for debug info)
67  MO_MCSymbol, ///< MCSymbol reference (for debug/eh info)
68  MO_CFIIndex, ///< MCCFIInstruction index.
69  MO_IntrinsicID, ///< Intrinsic ID for ISel
70  MO_Predicate, ///< Generic predicate for ISel
71  MO_ShuffleMask, ///< Other IR Constant for ISel (shuffle masks)
73  };
74 
75 private:
76  /// OpKind - Specify what kind of operand this is. This discriminates the
77  /// union.
78  unsigned OpKind : 8;
79 
80  /// Subregister number for MO_Register. A value of 0 indicates the
81  /// MO_Register has no subReg.
82  ///
83  /// For all other kinds of operands, this field holds target-specific flags.
84  unsigned SubReg_TargetFlags : 12;
85 
86  /// TiedTo - Non-zero when this register operand is tied to another register
87  /// operand. The encoding of this field is described in the block comment
88  /// before MachineInstr::tieOperands().
89  unsigned TiedTo : 4;
90 
91  /// IsDef - True if this is a def, false if this is a use of the register.
92  /// This is only valid on register operands.
93  ///
94  unsigned IsDef : 1;
95 
96  /// IsImp - True if this is an implicit def or use, false if it is explicit.
97  /// This is only valid on register opderands.
98  ///
99  unsigned IsImp : 1;
100 
101  /// IsDeadOrKill
102  /// For uses: IsKill - True if this instruction is the last use of the
103  /// register on this path through the function.
104  /// For defs: IsDead - True if this register is never used by a subsequent
105  /// instruction.
106  /// This is only valid on register operands.
107  unsigned IsDeadOrKill : 1;
108 
109  /// See isRenamable().
110  unsigned IsRenamable : 1;
111 
112  /// IsUndef - True if this register operand reads an "undef" value, i.e. the
113  /// read value doesn't matter. This flag can be set on both use and def
114  /// operands. On a sub-register def operand, it refers to the part of the
115  /// register that isn't written. On a full-register def operand, it is a
116  /// noop. See readsReg().
117  ///
118  /// This is only valid on registers.
119  ///
120  /// Note that an instruction may have multiple <undef> operands referring to
121  /// the same register. In that case, the instruction may depend on those
122  /// operands reading the same dont-care value. For example:
123  ///
124  /// %1 = XOR undef %2, undef %2
125  ///
126  /// Any register can be used for %2, and its value doesn't matter, but
127  /// the two operands must be the same register.
128  ///
129  unsigned IsUndef : 1;
130 
131  /// IsInternalRead - True if this operand reads a value that was defined
132  /// inside the same instruction or bundle. This flag can be set on both use
133  /// and def operands. On a sub-register def operand, it refers to the part
134  /// of the register that isn't written. On a full-register def operand, it
135  /// is a noop.
136  ///
137  /// When this flag is set, the instruction bundle must contain at least one
138  /// other def of the register. If multiple instructions in the bundle define
139  /// the register, the meaning is target-defined.
140  unsigned IsInternalRead : 1;
141 
142  /// IsEarlyClobber - True if this MO_Register 'def' operand is written to
143  /// by the MachineInstr before all input registers are read. This is used to
144  /// model the GCC inline asm '&' constraint modifier.
145  unsigned IsEarlyClobber : 1;
146 
147  /// IsDebug - True if this MO_Register 'use' operand is in a debug pseudo,
148  /// not a real instruction. Such uses should be ignored during codegen.
149  unsigned IsDebug : 1;
150 
151  /// SmallContents - This really should be part of the Contents union, but
152  /// lives out here so we can get a better packed struct.
153  /// MO_Register: Register number.
154  /// OffsetedInfo: Low bits of offset.
155  union {
156  unsigned RegNo; // For MO_Register.
157  unsigned OffsetLo; // Matches Contents.OffsetedInfo.OffsetHi.
158  } SmallContents;
159 
160  /// ParentMI - This is the instruction that this operand is embedded into.
161  /// This is valid for all operand types, when the operand is in an instr.
162  MachineInstr *ParentMI;
163 
164  /// Contents union - This contains the payload for the various operand types.
165  union ContentsUnion {
166  ContentsUnion() {}
167  MachineBasicBlock *MBB; // For MO_MachineBasicBlock.
168  const ConstantFP *CFP; // For MO_FPImmediate.
169  const ConstantInt *CI; // For MO_CImmediate. Integers > 64bit.
170  int64_t ImmVal; // For MO_Immediate.
171  const uint32_t *RegMask; // For MO_RegisterMask and MO_RegisterLiveOut.
172  const MDNode *MD; // For MO_Metadata.
173  MCSymbol *Sym; // For MO_MCSymbol.
174  unsigned CFIIndex; // For MO_CFI.
175  Intrinsic::ID IntrinsicID; // For MO_IntrinsicID.
176  unsigned Pred; // For MO_Predicate
177  ArrayRef<int> ShuffleMask; // For MO_ShuffleMask
178 
179  struct { // For MO_Register.
180  // Register number is in SmallContents.RegNo.
181  MachineOperand *Prev; // Access list for register. See MRI.
182  MachineOperand *Next;
183  } Reg;
184 
185  /// OffsetedInfo - This struct contains the offset and an object identifier.
186  /// this represent the object as with an optional offset from it.
187  struct {
188  union {
189  int Index; // For MO_*Index - The index itself.
190  const char *SymbolName; // For MO_ExternalSymbol.
191  const GlobalValue *GV; // For MO_GlobalAddress.
192  const BlockAddress *BA; // For MO_BlockAddress.
193  } Val;
194  // Low bits of offset are in SmallContents.OffsetLo.
195  int OffsetHi; // An offset from the object, high 32 bits.
196  } OffsetedInfo;
197  } Contents;
198 
199  explicit MachineOperand(MachineOperandType K)
200  : OpKind(K), SubReg_TargetFlags(0), ParentMI(nullptr) {
201  // Assert that the layout is what we expect. It's easy to grow this object.
202  static_assert(alignof(MachineOperand) <= alignof(int64_t),
203  "MachineOperand shouldn't be more than 8 byte aligned");
204  static_assert(sizeof(Contents) <= 2 * sizeof(void *),
205  "Contents should be at most two pointers");
206  static_assert(sizeof(MachineOperand) <=
207  alignTo<alignof(int64_t)>(2 * sizeof(unsigned) +
208  3 * sizeof(void *)),
209  "MachineOperand too big. Should be Kind, SmallContents, "
210  "ParentMI, and Contents");
211  }
212 
213 public:
214  /// getType - Returns the MachineOperandType for this operand.
215  ///
216  MachineOperandType getType() const { return (MachineOperandType)OpKind; }
217 
218  unsigned getTargetFlags() const {
219  return isReg() ? 0 : SubReg_TargetFlags;
220  }
221  void setTargetFlags(unsigned F) {
222  assert(!isReg() && "Register operands can't have target flags");
223  SubReg_TargetFlags = F;
224  assert(SubReg_TargetFlags == F && "Target flags out of range");
225  }
226  void addTargetFlag(unsigned F) {
227  assert(!isReg() && "Register operands can't have target flags");
228  SubReg_TargetFlags |= F;
229  assert((SubReg_TargetFlags & F) && "Target flags out of range");
230  }
231 
232 
233  /// getParent - Return the instruction that this operand belongs to.
234  ///
235  MachineInstr *getParent() { return ParentMI; }
236  const MachineInstr *getParent() const { return ParentMI; }
237 
238  /// clearParent - Reset the parent pointer.
239  ///
240  /// The MachineOperand copy constructor also copies ParentMI, expecting the
241  /// original to be deleted. If a MachineOperand is ever stored outside a
242  /// MachineInstr, the parent pointer must be cleared.
243  ///
244  /// Never call clearParent() on an operand in a MachineInstr.
245  ///
246  void clearParent() { ParentMI = nullptr; }
247 
248  /// Print a subreg index operand.
249  /// MO_Immediate operands can also be subreg idices. If it's the case, the
250  /// subreg index name will be printed. MachineInstr::isOperandSubregIdx can be
251  /// called to check this.
252  static void printSubRegIdx(raw_ostream &OS, uint64_t Index,
253  const TargetRegisterInfo *TRI);
254 
255  /// Print operand target flags.
256  static void printTargetFlags(raw_ostream& OS, const MachineOperand &Op);
257 
258  /// Print a MCSymbol as an operand.
259  static void printSymbol(raw_ostream &OS, MCSymbol &Sym);
260 
261  /// Print a stack object reference.
262  static void printStackObjectReference(raw_ostream &OS, unsigned FrameIndex,
263  bool IsFixed, StringRef Name);
264 
265  /// Print the offset with explicit +/- signs.
266  static void printOperandOffset(raw_ostream &OS, int64_t Offset);
267 
268  /// Print an IRSlotNumber.
269  static void printIRSlotNumber(raw_ostream &OS, int Slot);
270 
271  /// Print the MachineOperand to \p os.
272  /// Providing a valid \p TRI and \p IntrinsicInfo results in a more
273  /// target-specific printing. If \p TRI and \p IntrinsicInfo are null, the
274  /// function will try to pick it up from the parent.
275  void print(raw_ostream &os, const TargetRegisterInfo *TRI = nullptr,
276  const TargetIntrinsicInfo *IntrinsicInfo = nullptr) const;
277 
278  /// More complex way of printing a MachineOperand.
279  /// \param TypeToPrint specifies the generic type to be printed on uses and
280  /// defs. It can be determined using MachineInstr::getTypeToPrint.
281  /// \param OpIdx - specifies the index of the operand in machine instruction.
282  /// This will be used by target dependent MIR formatter. Could be None if the
283  /// index is unknown, e.g. called by dump().
284  /// \param PrintDef - whether we want to print `def` on an operand which
285  /// isDef. Sometimes, if the operand is printed before '=', we don't print
286  /// `def`.
287  /// \param IsStandalone - whether we want a verbose output of the MO. This
288  /// prints extra information that can be easily inferred when printing the
289  /// whole function, but not when printing only a fragment of it.
290  /// \param ShouldPrintRegisterTies - whether we want to print register ties.
291  /// Sometimes they are easily determined by the instruction's descriptor
292  /// (MachineInstr::hasComplexRegiterTies can determine if it's needed).
293  /// \param TiedOperandIdx - if we need to print register ties this needs to
294  /// provide the index of the tied register. If not, it will be ignored.
295  /// \param TRI - provide more target-specific information to the printer.
296  /// Unlike the previous function, this one will not try and get the
297  /// information from it's parent.
298  /// \param IntrinsicInfo - same as \p TRI.
299  void print(raw_ostream &os, ModuleSlotTracker &MST, LLT TypeToPrint,
300  Optional<unsigned> OpIdx, bool PrintDef, bool IsStandalone,
301  bool ShouldPrintRegisterTies, unsigned TiedOperandIdx,
302  const TargetRegisterInfo *TRI,
303  const TargetIntrinsicInfo *IntrinsicInfo) const;
304 
305  /// Same as print(os, TRI, IntrinsicInfo), but allows to specify the low-level
306  /// type to be printed the same way the full version of print(...) does it.
307  void print(raw_ostream &os, LLT TypeToPrint,
308  const TargetRegisterInfo *TRI = nullptr,
309  const TargetIntrinsicInfo *IntrinsicInfo = nullptr) const;
310 
311  void dump() const;
312 
313  //===--------------------------------------------------------------------===//
314  // Accessors that tell you what kind of MachineOperand you're looking at.
315  //===--------------------------------------------------------------------===//
316 
317  /// isReg - Tests if this is a MO_Register operand.
318  bool isReg() const { return OpKind == MO_Register; }
319  /// isImm - Tests if this is a MO_Immediate operand.
320  bool isImm() const { return OpKind == MO_Immediate; }
321  /// isCImm - Test if this is a MO_CImmediate operand.
322  bool isCImm() const { return OpKind == MO_CImmediate; }
323  /// isFPImm - Tests if this is a MO_FPImmediate operand.
324  bool isFPImm() const { return OpKind == MO_FPImmediate; }
325  /// isMBB - Tests if this is a MO_MachineBasicBlock operand.
326  bool isMBB() const { return OpKind == MO_MachineBasicBlock; }
327  /// isFI - Tests if this is a MO_FrameIndex operand.
328  bool isFI() const { return OpKind == MO_FrameIndex; }
329  /// isCPI - Tests if this is a MO_ConstantPoolIndex operand.
330  bool isCPI() const { return OpKind == MO_ConstantPoolIndex; }
331  /// isTargetIndex - Tests if this is a MO_TargetIndex operand.
332  bool isTargetIndex() const { return OpKind == MO_TargetIndex; }
333  /// isJTI - Tests if this is a MO_JumpTableIndex operand.
334  bool isJTI() const { return OpKind == MO_JumpTableIndex; }
335  /// isGlobal - Tests if this is a MO_GlobalAddress operand.
336  bool isGlobal() const { return OpKind == MO_GlobalAddress; }
337  /// isSymbol - Tests if this is a MO_ExternalSymbol operand.
338  bool isSymbol() const { return OpKind == MO_ExternalSymbol; }
339  /// isBlockAddress - Tests if this is a MO_BlockAddress operand.
340  bool isBlockAddress() const { return OpKind == MO_BlockAddress; }
341  /// isRegMask - Tests if this is a MO_RegisterMask operand.
342  bool isRegMask() const { return OpKind == MO_RegisterMask; }
343  /// isRegLiveOut - Tests if this is a MO_RegisterLiveOut operand.
344  bool isRegLiveOut() const { return OpKind == MO_RegisterLiveOut; }
345  /// isMetadata - Tests if this is a MO_Metadata operand.
346  bool isMetadata() const { return OpKind == MO_Metadata; }
347  bool isMCSymbol() const { return OpKind == MO_MCSymbol; }
348  bool isCFIIndex() const { return OpKind == MO_CFIIndex; }
349  bool isIntrinsicID() const { return OpKind == MO_IntrinsicID; }
350  bool isPredicate() const { return OpKind == MO_Predicate; }
351  bool isShuffleMask() const { return OpKind == MO_ShuffleMask; }
352  //===--------------------------------------------------------------------===//
353  // Accessors for Register Operands
354  //===--------------------------------------------------------------------===//
355 
356  /// getReg - Returns the register number.
357  Register getReg() const {
358  assert(isReg() && "This is not a register operand!");
359  return Register(SmallContents.RegNo);
360  }
361 
362  unsigned getSubReg() const {
363  assert(isReg() && "Wrong MachineOperand accessor");
364  return SubReg_TargetFlags;
365  }
366 
367  bool isUse() const {
368  assert(isReg() && "Wrong MachineOperand accessor");
369  return !IsDef;
370  }
371 
372  bool isDef() const {
373  assert(isReg() && "Wrong MachineOperand accessor");
374  return IsDef;
375  }
376 
377  bool isImplicit() const {
378  assert(isReg() && "Wrong MachineOperand accessor");
379  return IsImp;
380  }
381 
382  bool isDead() const {
383  assert(isReg() && "Wrong MachineOperand accessor");
384  return IsDeadOrKill & IsDef;
385  }
386 
387  bool isKill() const {
388  assert(isReg() && "Wrong MachineOperand accessor");
389  return IsDeadOrKill & !IsDef;
390  }
391 
392  bool isUndef() const {
393  assert(isReg() && "Wrong MachineOperand accessor");
394  return IsUndef;
395  }
396 
397  /// isRenamable - Returns true if this register may be renamed, i.e. it does
398  /// not generate a value that is somehow read in a way that is not represented
399  /// by the Machine IR (e.g. to meet an ABI or ISA requirement). This is only
400  /// valid on physical register operands. Virtual registers are assumed to
401  /// always be renamable regardless of the value of this field.
402  ///
403  /// Operands that are renamable can freely be changed to any other register
404  /// that is a member of the register class returned by
405  /// MI->getRegClassConstraint().
406  ///
407  /// isRenamable can return false for several different reasons:
408  ///
409  /// - ABI constraints (since liveness is not always precisely modeled). We
410  /// conservatively handle these cases by setting all physical register
411  /// operands that didn’t start out as virtual regs to not be renamable.
412  /// Also any physical register operands created after register allocation or
413  /// whose register is changed after register allocation will not be
414  /// renamable. This state is tracked in the MachineOperand::IsRenamable
415  /// bit.
416  ///
417  /// - Opcode/target constraints: for opcodes that have complex register class
418  /// requirements (e.g. that depend on other operands/instructions), we set
419  /// hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq in the machine opcode
420  /// description. Operands belonging to instructions with opcodes that are
421  /// marked hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq return false from
422  /// isRenamable(). Additionally, the AllowRegisterRenaming target property
423  /// prevents any operands from being marked renamable for targets that don't
424  /// have detailed opcode hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq
425  /// values.
426  bool isRenamable() const;
427 
428  bool isInternalRead() const {
429  assert(isReg() && "Wrong MachineOperand accessor");
430  return IsInternalRead;
431  }
432 
433  bool isEarlyClobber() const {
434  assert(isReg() && "Wrong MachineOperand accessor");
435  return IsEarlyClobber;
436  }
437 
438  bool isTied() const {
439  assert(isReg() && "Wrong MachineOperand accessor");
440  return TiedTo;
441  }
442 
443  bool isDebug() const {
444  assert(isReg() && "Wrong MachineOperand accessor");
445  return IsDebug;
446  }
447 
448  /// readsReg - Returns true if this operand reads the previous value of its
449  /// register. A use operand with the <undef> flag set doesn't read its
450  /// register. A sub-register def implicitly reads the other parts of the
451  /// register being redefined unless the <undef> flag is set.
452  ///
453  /// This refers to reading the register value from before the current
454  /// instruction or bundle. Internal bundle reads are not included.
455  bool readsReg() const {
456  assert(isReg() && "Wrong MachineOperand accessor");
457  return !isUndef() && !isInternalRead() && (isUse() || getSubReg());
458  }
459 
460  //===--------------------------------------------------------------------===//
461  // Mutators for Register Operands
462  //===--------------------------------------------------------------------===//
463 
464  /// Change the register this operand corresponds to.
465  ///
466  void setReg(Register Reg);
467 
468  void setSubReg(unsigned subReg) {
469  assert(isReg() && "Wrong MachineOperand mutator");
470  SubReg_TargetFlags = subReg;
471  assert(SubReg_TargetFlags == subReg && "SubReg out of range");
472  }
473 
474  /// substVirtReg - Substitute the current register with the virtual
475  /// subregister Reg:SubReg. Take any existing SubReg index into account,
476  /// using TargetRegisterInfo to compose the subreg indices if necessary.
477  /// Reg must be a virtual register, SubIdx can be 0.
478  ///
479  void substVirtReg(Register Reg, unsigned SubIdx, const TargetRegisterInfo&);
480 
481  /// substPhysReg - Substitute the current register with the physical register
482  /// Reg, taking any existing SubReg into account. For instance,
483  /// substPhysReg(%eax) will change %reg1024:sub_8bit to %al.
484  ///
486 
487  void setIsUse(bool Val = true) { setIsDef(!Val); }
488 
489  /// Change a def to a use, or a use to a def.
490  void setIsDef(bool Val = true);
491 
492  void setImplicit(bool Val = true) {
493  assert(isReg() && "Wrong MachineOperand mutator");
494  IsImp = Val;
495  }
496 
497  void setIsKill(bool Val = true) {
498  assert(isReg() && !IsDef && "Wrong MachineOperand mutator");
499  assert((!Val || !isDebug()) && "Marking a debug operation as kill");
500  IsDeadOrKill = Val;
501  }
502 
503  void setIsDead(bool Val = true) {
504  assert(isReg() && IsDef && "Wrong MachineOperand mutator");
505  IsDeadOrKill = Val;
506  }
507 
508  void setIsUndef(bool Val = true) {
509  assert(isReg() && "Wrong MachineOperand mutator");
510  IsUndef = Val;
511  }
512 
513  void setIsRenamable(bool Val = true);
514 
515  void setIsInternalRead(bool Val = true) {
516  assert(isReg() && "Wrong MachineOperand mutator");
517  IsInternalRead = Val;
518  }
519 
520  void setIsEarlyClobber(bool Val = true) {
521  assert(isReg() && IsDef && "Wrong MachineOperand mutator");
522  IsEarlyClobber = Val;
523  }
524 
525  void setIsDebug(bool Val = true) {
526  assert(isReg() && !IsDef && "Wrong MachineOperand mutator");
527  IsDebug = Val;
528  }
529 
530  //===--------------------------------------------------------------------===//
531  // Accessors for various operand types.
532  //===--------------------------------------------------------------------===//
533 
534  int64_t getImm() const {
535  assert(isImm() && "Wrong MachineOperand accessor");
536  return Contents.ImmVal;
537  }
538 
539  const ConstantInt *getCImm() const {
540  assert(isCImm() && "Wrong MachineOperand accessor");
541  return Contents.CI;
542  }
543 
544  const ConstantFP *getFPImm() const {
545  assert(isFPImm() && "Wrong MachineOperand accessor");
546  return Contents.CFP;
547  }
548 
550  assert(isMBB() && "Wrong MachineOperand accessor");
551  return Contents.MBB;
552  }
553 
554  int getIndex() const {
555  assert((isFI() || isCPI() || isTargetIndex() || isJTI()) &&
556  "Wrong MachineOperand accessor");
557  return Contents.OffsetedInfo.Val.Index;
558  }
559 
560  const GlobalValue *getGlobal() const {
561  assert(isGlobal() && "Wrong MachineOperand accessor");
562  return Contents.OffsetedInfo.Val.GV;
563  }
564 
565  const BlockAddress *getBlockAddress() const {
566  assert(isBlockAddress() && "Wrong MachineOperand accessor");
567  return Contents.OffsetedInfo.Val.BA;
568  }
569 
571  assert(isMCSymbol() && "Wrong MachineOperand accessor");
572  return Contents.Sym;
573  }
574 
575  unsigned getCFIIndex() const {
576  assert(isCFIIndex() && "Wrong MachineOperand accessor");
577  return Contents.CFIIndex;
578  }
579 
581  assert(isIntrinsicID() && "Wrong MachineOperand accessor");
582  return Contents.IntrinsicID;
583  }
584 
585  unsigned getPredicate() const {
586  assert(isPredicate() && "Wrong MachineOperand accessor");
587  return Contents.Pred;
588  }
589 
591  assert(isShuffleMask() && "Wrong MachineOperand accessor");
592  return Contents.ShuffleMask;
593  }
594 
595  /// Return the offset from the symbol in this operand. This always returns 0
596  /// for ExternalSymbol operands.
597  int64_t getOffset() const {
598  assert((isGlobal() || isSymbol() || isMCSymbol() || isCPI() ||
599  isTargetIndex() || isBlockAddress()) &&
600  "Wrong MachineOperand accessor");
601  return int64_t(uint64_t(Contents.OffsetedInfo.OffsetHi) << 32) |
602  SmallContents.OffsetLo;
603  }
604 
605  const char *getSymbolName() const {
606  assert(isSymbol() && "Wrong MachineOperand accessor");
607  return Contents.OffsetedInfo.Val.SymbolName;
608  }
609 
610  /// clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
611  /// It is sometimes necessary to detach the register mask pointer from its
612  /// machine operand. This static method can be used for such detached bit
613  /// mask pointers.
614  static bool clobbersPhysReg(const uint32_t *RegMask, MCRegister PhysReg) {
615  // See TargetRegisterInfo.h.
616  assert(PhysReg < (1u << 30) && "Not a physical register");
617  return !(RegMask[PhysReg / 32] & (1u << PhysReg % 32));
618  }
619 
620  /// clobbersPhysReg - Returns true if this RegMask operand clobbers PhysReg.
621  bool clobbersPhysReg(MCRegister PhysReg) const {
622  return clobbersPhysReg(getRegMask(), PhysReg);
623  }
624 
625  /// getRegMask - Returns a bit mask of registers preserved by this RegMask
626  /// operand.
627  const uint32_t *getRegMask() const {
628  assert(isRegMask() && "Wrong MachineOperand accessor");
629  return Contents.RegMask;
630  }
631 
632  /// Returns number of elements needed for a regmask array.
633  static unsigned getRegMaskSize(unsigned NumRegs) {
634  return (NumRegs + 31) / 32;
635  }
636 
637  /// getRegLiveOut - Returns a bit mask of live-out registers.
638  const uint32_t *getRegLiveOut() const {
639  assert(isRegLiveOut() && "Wrong MachineOperand accessor");
640  return Contents.RegMask;
641  }
642 
643  const MDNode *getMetadata() const {
644  assert(isMetadata() && "Wrong MachineOperand accessor");
645  return Contents.MD;
646  }
647 
648  //===--------------------------------------------------------------------===//
649  // Mutators for various operand types.
650  //===--------------------------------------------------------------------===//
651 
652  void setImm(int64_t immVal) {
653  assert(isImm() && "Wrong MachineOperand mutator");
654  Contents.ImmVal = immVal;
655  }
656 
657  void setCImm(const ConstantInt *CI) {
658  assert(isCImm() && "Wrong MachineOperand mutator");
659  Contents.CI = CI;
660  }
661 
662  void setFPImm(const ConstantFP *CFP) {
663  assert(isFPImm() && "Wrong MachineOperand mutator");
664  Contents.CFP = CFP;
665  }
666 
667  void setOffset(int64_t Offset) {
668  assert((isGlobal() || isSymbol() || isMCSymbol() || isCPI() ||
669  isTargetIndex() || isBlockAddress()) &&
670  "Wrong MachineOperand mutator");
671  SmallContents.OffsetLo = unsigned(Offset);
672  Contents.OffsetedInfo.OffsetHi = int(Offset >> 32);
673  }
674 
675  void setIndex(int Idx) {
676  assert((isFI() || isCPI() || isTargetIndex() || isJTI()) &&
677  "Wrong MachineOperand mutator");
678  Contents.OffsetedInfo.Val.Index = Idx;
679  }
680 
681  void setMetadata(const MDNode *MD) {
682  assert(isMetadata() && "Wrong MachineOperand mutator");
683  Contents.MD = MD;
684  }
685 
687  assert(isMBB() && "Wrong MachineOperand mutator");
688  Contents.MBB = MBB;
689  }
690 
691  /// Sets value of register mask operand referencing Mask. The
692  /// operand does not take ownership of the memory referenced by Mask, it must
693  /// remain valid for the lifetime of the operand. See CreateRegMask().
694  /// Any physreg with a 0 bit in the mask is clobbered by the instruction.
695  void setRegMask(const uint32_t *RegMaskPtr) {
696  assert(isRegMask() && "Wrong MachineOperand mutator");
697  Contents.RegMask = RegMaskPtr;
698  }
699 
701  assert(isIntrinsicID() && "Wrong MachineOperand mutator");
702  Contents.IntrinsicID = IID;
703  }
704 
705  void setPredicate(unsigned Predicate) {
706  assert(isPredicate() && "Wrong MachineOperand mutator");
707  Contents.Pred = Predicate;
708  }
709 
710  //===--------------------------------------------------------------------===//
711  // Other methods.
712  //===--------------------------------------------------------------------===//
713 
714  /// Returns true if this operand is identical to the specified operand except
715  /// for liveness related flags (isKill, isUndef and isDead). Note that this
716  /// should stay in sync with the hash_value overload below.
717  bool isIdenticalTo(const MachineOperand &Other) const;
718 
719  /// MachineOperand hash_value overload.
720  ///
721  /// Note that this includes the same information in the hash that
722  /// isIdenticalTo uses for comparison. It is thus suited for use in hash
723  /// tables which use that function for equality comparisons only. This must
724  /// stay exactly in sync with isIdenticalTo above.
725  friend hash_code hash_value(const MachineOperand &MO);
726 
727  /// ChangeToImmediate - Replace this operand with a new immediate operand of
728  /// the specified value. If an operand is known to be an immediate already,
729  /// the setImm method should be used.
730  void ChangeToImmediate(int64_t ImmVal, unsigned TargetFlags = 0);
731 
732  /// ChangeToFPImmediate - Replace this operand with a new FP immediate operand
733  /// of the specified value. If an operand is known to be an FP immediate
734  /// already, the setFPImm method should be used.
735  void ChangeToFPImmediate(const ConstantFP *FPImm, unsigned TargetFlags = 0);
736 
737  /// ChangeToES - Replace this operand with a new external symbol operand.
738  void ChangeToES(const char *SymName, unsigned TargetFlags = 0);
739 
740  /// ChangeToGA - Replace this operand with a new global address operand.
741  void ChangeToGA(const GlobalValue *GV, int64_t Offset,
742  unsigned TargetFlags = 0);
743 
744  /// ChangeToMCSymbol - Replace this operand with a new MC symbol operand.
745  void ChangeToMCSymbol(MCSymbol *Sym, unsigned TargetFlags = 0);
746 
747  /// Replace this operand with a frame index.
748  void ChangeToFrameIndex(int Idx, unsigned TargetFlags = 0);
749 
750  /// Replace this operand with a target index.
751  void ChangeToTargetIndex(unsigned Idx, int64_t Offset,
752  unsigned TargetFlags = 0);
753 
754  /// ChangeToRegister - Replace this operand with a new register operand of
755  /// the specified value. If an operand is known to be an register already,
756  /// the setReg method should be used.
757  void ChangeToRegister(Register Reg, bool isDef, bool isImp = false,
758  bool isKill = false, bool isDead = false,
759  bool isUndef = false, bool isDebug = false);
760 
761  /// getTargetIndexName - If this MachineOperand is a TargetIndex that has a
762  /// name, attempt to get the name. Returns nullptr if the TargetIndex does not
763  /// have a name. Asserts if MO is not a TargetIndex.
764  const char *getTargetIndexName() const;
765 
766  //===--------------------------------------------------------------------===//
767  // Construction methods.
768  //===--------------------------------------------------------------------===//
769 
770  static MachineOperand CreateImm(int64_t Val) {
772  Op.setImm(Val);
773  return Op;
774  }
775 
778  Op.Contents.CI = CI;
779  return Op;
780  }
781 
782  static MachineOperand CreateFPImm(const ConstantFP *CFP) {
784  Op.Contents.CFP = CFP;
785  return Op;
786  }
787 
788  static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp = false,
789  bool isKill = false, bool isDead = false,
790  bool isUndef = false,
791  bool isEarlyClobber = false,
792  unsigned SubReg = 0, bool isDebug = false,
793  bool isInternalRead = false,
794  bool isRenamable = false) {
795  assert(!(isDead && !isDef) && "Dead flag on non-def");
796  assert(!(isKill && isDef) && "Kill flag on def");
798  Op.IsDef = isDef;
799  Op.IsImp = isImp;
800  Op.IsDeadOrKill = isKill | isDead;
801  Op.IsRenamable = isRenamable;
802  Op.IsUndef = isUndef;
803  Op.IsInternalRead = isInternalRead;
804  Op.IsEarlyClobber = isEarlyClobber;
805  Op.TiedTo = 0;
806  Op.IsDebug = isDebug;
807  Op.SmallContents.RegNo = Reg;
808  Op.Contents.Reg.Prev = nullptr;
809  Op.Contents.Reg.Next = nullptr;
810  Op.setSubReg(SubReg);
811  return Op;
812  }
814  unsigned TargetFlags = 0) {
816  Op.setMBB(MBB);
817  Op.setTargetFlags(TargetFlags);
818  return Op;
819  }
820  static MachineOperand CreateFI(int Idx) {
822  Op.setIndex(Idx);
823  return Op;
824  }
825  static MachineOperand CreateCPI(unsigned Idx, int Offset,
826  unsigned TargetFlags = 0) {
828  Op.setIndex(Idx);
829  Op.setOffset(Offset);
830  Op.setTargetFlags(TargetFlags);
831  return Op;
832  }
833  static MachineOperand CreateTargetIndex(unsigned Idx, int64_t Offset,
834  unsigned TargetFlags = 0) {
836  Op.setIndex(Idx);
837  Op.setOffset(Offset);
838  Op.setTargetFlags(TargetFlags);
839  return Op;
840  }
841  static MachineOperand CreateJTI(unsigned Idx, unsigned TargetFlags = 0) {
843  Op.setIndex(Idx);
844  Op.setTargetFlags(TargetFlags);
845  return Op;
846  }
847  static MachineOperand CreateGA(const GlobalValue *GV, int64_t Offset,
848  unsigned TargetFlags = 0) {
850  Op.Contents.OffsetedInfo.Val.GV = GV;
851  Op.setOffset(Offset);
852  Op.setTargetFlags(TargetFlags);
853  return Op;
854  }
855  static MachineOperand CreateES(const char *SymName,
856  unsigned TargetFlags = 0) {
858  Op.Contents.OffsetedInfo.Val.SymbolName = SymName;
859  Op.setOffset(0); // Offset is always 0.
860  Op.setTargetFlags(TargetFlags);
861  return Op;
862  }
863  static MachineOperand CreateBA(const BlockAddress *BA, int64_t Offset,
864  unsigned TargetFlags = 0) {
866  Op.Contents.OffsetedInfo.Val.BA = BA;
867  Op.setOffset(Offset);
868  Op.setTargetFlags(TargetFlags);
869  return Op;
870  }
871  /// CreateRegMask - Creates a register mask operand referencing Mask. The
872  /// operand does not take ownership of the memory referenced by Mask, it
873  /// must remain valid for the lifetime of the operand.
874  ///
875  /// A RegMask operand represents a set of non-clobbered physical registers
876  /// on an instruction that clobbers many registers, typically a call. The
877  /// bit mask has a bit set for each physreg that is preserved by this
878  /// instruction, as described in the documentation for
879  /// TargetRegisterInfo::getCallPreservedMask().
880  ///
881  /// Any physreg with a 0 bit in the mask is clobbered by the instruction.
882  ///
884  assert(Mask && "Missing register mask");
886  Op.Contents.RegMask = Mask;
887  return Op;
888  }
890  assert(Mask && "Missing live-out register mask");
892  Op.Contents.RegMask = Mask;
893  return Op;
894  }
895  static MachineOperand CreateMetadata(const MDNode *Meta) {
897  Op.Contents.MD = Meta;
898  return Op;
899  }
900 
902  unsigned TargetFlags = 0) {
904  Op.Contents.Sym = Sym;
905  Op.setOffset(0);
906  Op.setTargetFlags(TargetFlags);
907  return Op;
908  }
909 
910  static MachineOperand CreateCFIIndex(unsigned CFIIndex) {
912  Op.Contents.CFIIndex = CFIIndex;
913  return Op;
914  }
915 
918  Op.Contents.IntrinsicID = ID;
919  return Op;
920  }
921 
922  static MachineOperand CreatePredicate(unsigned Pred) {
924  Op.Contents.Pred = Pred;
925  return Op;
926  }
927 
930  Op.Contents.ShuffleMask = Mask;
931  return Op;
932  }
933 
934  friend class MachineInstr;
935  friend class MachineRegisterInfo;
936 
937 private:
938  // If this operand is currently a register operand, and if this is in a
939  // function, deregister the operand from the register's use/def list.
940  void removeRegFromUses();
941 
942  /// Artificial kinds for DenseMap usage.
943  enum : unsigned char {
944  MO_Empty = MO_Last + 1,
945  MO_Tombstone,
946  };
947 
948  friend struct DenseMapInfo<MachineOperand>;
949 
950  //===--------------------------------------------------------------------===//
951  // Methods for handling register use/def lists.
952  //===--------------------------------------------------------------------===//
953 
954  /// isOnRegUseList - Return true if this operand is on a register use/def
955  /// list or false if not. This can only be called for register operands
956  /// that are part of a machine instruction.
957  bool isOnRegUseList() const {
958  assert(isReg() && "Can only add reg operand to use lists");
959  return Contents.Reg.Prev != nullptr;
960  }
961 };
962 
963 template <> struct DenseMapInfo<MachineOperand> {
966  MachineOperand::MO_Empty));
967  }
970  MachineOperand::MO_Tombstone));
971  }
972  static unsigned getHashValue(const MachineOperand &MO) {
973  return hash_value(MO);
974  }
975  static bool isEqual(const MachineOperand &LHS, const MachineOperand &RHS) {
976  if (LHS.getType() == static_cast<MachineOperand::MachineOperandType>(
977  MachineOperand::MO_Empty) ||
978  LHS.getType() == static_cast<MachineOperand::MachineOperandType>(
979  MachineOperand::MO_Tombstone))
980  return LHS.getType() == RHS.getType();
981  return LHS.isIdenticalTo(RHS);
982  }
983 };
984 
986  MO.print(OS);
987  return OS;
988 }
989 
990 // See friend declaration above. This additional declaration is required in
991 // order to compile LLVM with IBM xlC compiler.
992 hash_code hash_value(const MachineOperand &MO);
993 } // namespace llvm
994 
995 #endif
llvm::MachineOperand::CreateCPI
static MachineOperand CreateCPI(unsigned Idx, int Offset, unsigned TargetFlags=0)
Definition: MachineOperand.h:825
llvm::alignTo
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
Definition: Alignment.h:158
llvm::MachineOperand::CreateJTI
static MachineOperand CreateJTI(unsigned Idx, unsigned TargetFlags=0)
Definition: MachineOperand.h:841
llvm::MachineOperand::MO_BlockAddress
@ MO_BlockAddress
Address of a basic block.
Definition: MachineOperand.h:63
llvm::MachineOperand::setRegMask
void setRegMask(const uint32_t *RegMaskPtr)
Sets value of register mask operand referencing Mask.
Definition: MachineOperand.h:695
llvm::MachineOperand::MO_Immediate
@ MO_Immediate
Immediate operand.
Definition: MachineOperand.h:53
llvm
Definition: AllocatorList.h:23
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::MCSymbol
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
llvm::MachineOperand::setIsInternalRead
void setIsInternalRead(bool Val=true)
Definition: MachineOperand.h:515
llvm::MachineOperand::isBlockAddress
bool isBlockAddress() const
isBlockAddress - Tests if this is a MO_BlockAddress operand.
Definition: MachineOperand.h:340
llvm::MachineOperand::CreateReg
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
Definition: MachineOperand.h:788
llvm::MachineOperand::MachineOperandType
MachineOperandType
Definition: MachineOperand.h:51
llvm::MachineOperand::MO_ShuffleMask
@ MO_ShuffleMask
Other IR Constant for ISel (shuffle masks)
Definition: MachineOperand.h:71
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
llvm::MachineOperand::getGlobal
const GlobalValue * getGlobal() const
Definition: MachineOperand.h:560
llvm::MachineOperand::MO_RegisterLiveOut
@ MO_RegisterLiveOut
Mask of live-out registers.
Definition: MachineOperand.h:65
llvm::ISD::ConstantFP
@ ConstantFP
Definition: ISDOpcodes.h:70
llvm::DenseMapInfo< MachineOperand >::getHashValue
static unsigned getHashValue(const MachineOperand &MO)
Definition: MachineOperand.h:972
llvm::MachineOperand::printStackObjectReference
static void printStackObjectReference(raw_ostream &OS, unsigned FrameIndex, bool IsFixed, StringRef Name)
Print a stack object reference.
Definition: MachineOperand.cpp:581
llvm::MachineOperand::printIRSlotNumber
static void printIRSlotNumber(raw_ostream &OS, int Slot)
Print an IRSlotNumber.
Definition: MachineOperand.cpp:604
llvm::MachineOperand::getIntrinsicID
Intrinsic::ID getIntrinsicID() const
Definition: MachineOperand.h:580
llvm::MachineOperand::setIsKill
void setIsKill(bool Val=true)
Definition: MachineOperand.h:497
llvm::MachineOperand::print
void print(raw_ostream &os, const TargetRegisterInfo *TRI=nullptr, const TargetIntrinsicInfo *IntrinsicInfo=nullptr) const
Print the MachineOperand to os.
Definition: MachineOperand.cpp:718
llvm::DenseMapInfo< MachineOperand >::isEqual
static bool isEqual(const MachineOperand &LHS, const MachineOperand &RHS)
Definition: MachineOperand.h:975
llvm::MachineOperand::getBlockAddress
const BlockAddress * getBlockAddress() const
Definition: MachineOperand.h:565
llvm::MachineOperand::isTied
bool isTied() const
Definition: MachineOperand.h:438
llvm::MachineOperand::RegNo
unsigned RegNo
Definition: MachineOperand.h:156
llvm::MachineOperand::setImm
void setImm(int64_t immVal)
Definition: MachineOperand.h:652
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:231
llvm::MachineOperand::setMetadata
void setMetadata(const MDNode *MD)
Definition: MachineOperand.h:681
llvm::MachineOperand::addTargetFlag
void addTargetFlag(unsigned F)
Definition: MachineOperand.h:226
llvm::MachineOperand::isSymbol
bool isSymbol() const
isSymbol - Tests if this is a MO_ExternalSymbol operand.
Definition: MachineOperand.h:338
llvm::MachineOperand::isJTI
bool isJTI() const
isJTI - Tests if this is a MO_JumpTableIndex operand.
Definition: MachineOperand.h:334
llvm::MachineOperand::isMCSymbol
bool isMCSymbol() const
Definition: MachineOperand.h:347
DenseMap.h
llvm::MachineOperand::CreateMetadata
static MachineOperand CreateMetadata(const MDNode *Meta)
Definition: MachineOperand.h:895
llvm::MachineOperand::CreateCFIIndex
static MachineOperand CreateCFIIndex(unsigned CFIIndex)
Definition: MachineOperand.h:910
llvm::MachineOperand::MO_CFIIndex
@ MO_CFIIndex
MCCFIInstruction index.
Definition: MachineOperand.h:68
llvm::MachineOperand::getTargetIndexName
const char * getTargetIndexName() const
getTargetIndexName - If this MachineOperand is a TargetIndex that has a name, attempt to get the name...
Definition: MachineOperand.cpp:423
llvm::MachineOperand::isCImm
bool isCImm() const
isCImm - Test if this is a MO_CImmediate operand.
Definition: MachineOperand.h:322
llvm::MachineOperand::setPredicate
void setPredicate(unsigned Predicate)
Definition: MachineOperand.h:705
llvm::Optional< unsigned >
llvm::MachineOperand::ChangeToTargetIndex
void ChangeToTargetIndex(unsigned Idx, int64_t Offset, unsigned TargetFlags=0)
Replace this operand with a target index.
Definition: MachineOperand.cpp:225
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
llvm::MachineOperand::setIsUse
void setIsUse(bool Val=true)
Definition: MachineOperand.h:487
llvm::MachineOperand::ChangeToFrameIndex
void ChangeToFrameIndex(int Idx, unsigned TargetFlags=0)
Replace this operand with a frame index.
Definition: MachineOperand.cpp:214
llvm::MachineOperand::isFI
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
Definition: MachineOperand.h:328
llvm::hash_value
hash_code hash_value(const APFloat &Arg)
See friend declarations above.
Definition: APFloat.cpp:4803
llvm::BitmaskEnumDetail::Mask
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::MachineOperand::getOffset
int64_t getOffset() const
Return the offset from the symbol in this operand.
Definition: MachineOperand.h:597
llvm::ModuleSlotTracker
Manage lifetime of a slot tracker for printing IR.
Definition: ModuleSlotTracker.h:29
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
llvm::MachineOperand::setCImm
void setCImm(const ConstantInt *CI)
Definition: MachineOperand.h:657
llvm::MachineOperand::dump
void dump() const
Definition: MachineOperand.cpp:961
llvm::MachineOperand::getMCSymbol
MCSymbol * getMCSymbol() const
Definition: MachineOperand.h:570
llvm::MachineOperand::MO_Register
@ MO_Register
Register operand.
Definition: MachineOperand.h:52
F
#define F(x, y, z)
Definition: MD5.cpp:56
llvm::MachineOperand::CreateES
static MachineOperand CreateES(const char *SymName, unsigned TargetFlags=0)
Definition: MachineOperand.h:855
llvm::MachineOperand::printSymbol
static void printSymbol(raw_ostream &OS, MCSymbol &Sym)
Print a MCSymbol as an operand.
Definition: MachineOperand.cpp:577
llvm::TargetIntrinsicInfo
TargetIntrinsicInfo - Interface to description of machine instruction set.
Definition: TargetIntrinsicInfo.h:29
llvm::MachineOperand::clobbersPhysReg
bool clobbersPhysReg(MCRegister PhysReg) const
clobbersPhysReg - Returns true if this RegMask operand clobbers PhysReg.
Definition: MachineOperand.h:621
llvm::MachineOperand::printSubRegIdx
static void printSubRegIdx(raw_ostream &OS, uint64_t Index, const TargetRegisterInfo *TRI)
Print a subreg index operand.
Definition: MachineOperand.cpp:516
llvm::MachineOperand::isKill
bool isKill() const
Definition: MachineOperand.h:387
llvm::MachineOperand::isRenamable
bool isRenamable() const
isRenamable - Returns true if this register may be renamed, i.e.
Definition: MachineOperand.cpp:118
llvm::ConstantInt
This is the shared class of boolean and integer constants.
Definition: Constants.h:77
llvm::DenseMapInfo
Definition: APInt.h:34
llvm::MachineOperand::isImplicit
bool isImplicit() const
Definition: MachineOperand.h:377
llvm::MachineOperand::hash_value
friend hash_code hash_value(const MachineOperand &MO)
MachineOperand hash_value overload.
llvm::ISD::Constant
@ Constant
Definition: ISDOpcodes.h:69
llvm::MachineOperand::CreateImm
static MachineOperand CreateImm(int64_t Val)
Definition: MachineOperand.h:770
llvm::MachineOperand::ChangeToRegister
void ChangeToRegister(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
ChangeToRegister - Replace this operand with a new register operand of the specified value.
Definition: MachineOperand.cpp:241
llvm::MachineOperand::MO_GlobalAddress
@ MO_GlobalAddress
Address of a global value.
Definition: MachineOperand.h:62
llvm::MachineOperand::getImm
int64_t getImm() const
Definition: MachineOperand.h:534
llvm::MachineOperand::getRegMaskSize
static unsigned getRegMaskSize(unsigned NumRegs)
Returns number of elements needed for a regmask array.
Definition: MachineOperand.h:633
llvm::MachineOperand::isUse
bool isUse() const
Definition: MachineOperand.h:367
Intrinsics.h
int
Clang compiles this i1 i64 store i64 i64 store i64 i64 store i64 i64 store i64 align Which gets codegen d xmm0 movaps rbp movaps rbp movaps rbp movaps rbp rbp rbp rbp rbp It would be better to have movq s of instead of the movaps s LLVM produces ret int
Definition: README.txt:536
llvm::MachineOperand::getRegMask
const uint32_t * getRegMask() const
getRegMask - Returns a bit mask of registers preserved by this RegMask operand.
Definition: MachineOperand.h:627
llvm::MachineOperand::setSubReg
void setSubReg(unsigned subReg)
Definition: MachineOperand.h:468
llvm::MachineOperand::MO_FrameIndex
@ MO_FrameIndex
Abstract Stack Frame Index.
Definition: MachineOperand.h:57
llvm::MachineOperand::isMBB
bool isMBB() const
isMBB - Tests if this is a MO_MachineBasicBlock operand.
Definition: MachineOperand.h:326
llvm::MachineOperand::ChangeToImmediate
void ChangeToImmediate(int64_t ImmVal, unsigned TargetFlags=0)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value.
Definition: MachineOperand.cpp:156
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
llvm::MachineOperand::getParent
const MachineInstr * getParent() const
Definition: MachineOperand.h:236
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:50
llvm::ConstantFP
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:255
llvm::MachineOperand::ChangeToMCSymbol
void ChangeToMCSymbol(MCSymbol *Sym, unsigned TargetFlags=0)
ChangeToMCSymbol - Replace this operand with a new MC symbol operand.
Definition: MachineOperand.cpp:203
llvm::operator<<
raw_ostream & operator<<(raw_ostream &OS, const APFixedPoint &FX)
Definition: APFixedPoint.h:230
llvm::MachineOperand::CreateFI
static MachineOperand CreateFI(int Idx)
Definition: MachineOperand.h:820
llvm::MachineOperand::setTargetFlags
void setTargetFlags(unsigned F)
Definition: MachineOperand.h:221
llvm::MachineOperand::getParent
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
Definition: MachineOperand.h:235
llvm::MachineOperand::isRegLiveOut
bool isRegLiveOut() const
isRegLiveOut - Tests if this is a MO_RegisterLiveOut operand.
Definition: MachineOperand.h:344
llvm::MachineOperand::printOperandOffset
static void printOperandOffset(raw_ostream &OS, int64_t Offset)
Print the offset with explicit +/- signs.
Definition: MachineOperand.cpp:594
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
LowLevelTypeImpl.h
llvm::MachineOperand::getMetadata
const MDNode * getMetadata() const
Definition: MachineOperand.h:643
llvm::ISD::BlockAddress
@ BlockAddress
Definition: ISDOpcodes.h:77
llvm::MachineOperand::CreateShuffleMask
static MachineOperand CreateShuffleMask(ArrayRef< int > Mask)
Definition: MachineOperand.h:928
llvm::MachineOperand::MO_Metadata
@ MO_Metadata
Metadata reference (for debug info)
Definition: MachineOperand.h:66
llvm::PPC::Predicate
Predicate
Predicate - These are "(BI << 5) | BO" for various predicates.
Definition: PPCPredicates.h:26
llvm::GlobalValue
Definition: GlobalValue.h:44
llvm::MachineOperand::clobbersPhysReg
static bool clobbersPhysReg(const uint32_t *RegMask, MCRegister PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
Definition: MachineOperand.h:614
llvm::MachineOperand::ChangeToFPImmediate
void ChangeToFPImmediate(const ConstantFP *FPImm, unsigned TargetFlags=0)
ChangeToFPImmediate - Replace this operand with a new FP immediate operand of the specified value.
Definition: MachineOperand.cpp:166
llvm::MachineOperand::isUndef
bool isUndef() const
Definition: MachineOperand.h:392
llvm::MachineOperand::setIsDead
void setIsDead(bool Val=true)
Definition: MachineOperand.h:503
llvm::MachineOperand::getTargetFlags
unsigned getTargetFlags() const
Definition: MachineOperand.h:218
llvm::MachineOperand::substVirtReg
void substVirtReg(Register Reg, unsigned SubIdx, const TargetRegisterInfo &)
substVirtReg - Substitute the current register with the virtual subregister Reg:SubReg.
Definition: MachineOperand.cpp:77
Index
uint32_t Index
Definition: ELFObjHandler.cpp:84
llvm::MachineOperand::isReg
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition: MachineOperand.h:318
llvm::MachineOperand::getCImm
const ConstantInt * getCImm() const
Definition: MachineOperand.h:539
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::MachineOperand::CreateMBB
static MachineOperand CreateMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0)
Definition: MachineOperand.h:813
llvm::DenseMapInfo< MachineOperand >::getTombstoneKey
static MachineOperand getTombstoneKey()
Definition: MachineOperand.h:968
llvm::MachineOperand::isDead
bool isDead() const
Definition: MachineOperand.h:382
llvm::MachineOperand::MO_Predicate
@ MO_Predicate
Generic predicate for ISel.
Definition: MachineOperand.h:70
llvm::MachineOperand::MO_MCSymbol
@ MO_MCSymbol
MCSymbol reference (for debug/eh info)
Definition: MachineOperand.h:67
llvm::MachineOperand::setIntrinsicID
void setIntrinsicID(Intrinsic::ID IID)
Definition: MachineOperand.h:700
llvm::MachineOperand::isCPI
bool isCPI() const
isCPI - Tests if this is a MO_ConstantPoolIndex operand.
Definition: MachineOperand.h:330
llvm::MachineOperand::getType
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
Definition: MachineOperand.h:216
llvm::MachineOperand::getFPImm
const ConstantFP * getFPImm() const
Definition: MachineOperand.h:544
llvm::MachineOperand::getPredicate
unsigned getPredicate() const
Definition: MachineOperand.h:585
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MachineOperand::isEarlyClobber
bool isEarlyClobber() const
Definition: MachineOperand.h:433
llvm::MachineOperand::getShuffleMask
ArrayRef< int > getShuffleMask() const
Definition: MachineOperand.h:590
llvm::MachineOperand::MO_TargetIndex
@ MO_TargetIndex
Target-dependent index+offset operand.
Definition: MachineOperand.h:59
llvm::MachineOperand::CreateBA
static MachineOperand CreateBA(const BlockAddress *BA, int64_t Offset, unsigned TargetFlags=0)
Definition: MachineOperand.h:863
llvm::MachineOperand::isRegMask
bool isRegMask() const
isRegMask - Tests if this is a MO_RegisterMask operand.
Definition: MachineOperand.h:342
llvm::MachineOperand::MO_FPImmediate
@ MO_FPImmediate
Floating-point immediate operand.
Definition: MachineOperand.h:55
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:357
llvm::MDNode
Metadata node.
Definition: Metadata.h:897
llvm::MachineOperand::CreateMCSymbol
static MachineOperand CreateMCSymbol(MCSymbol *Sym, unsigned TargetFlags=0)
Definition: MachineOperand.h:901
llvm::MachineOperand::setIsDebug
void setIsDebug(bool Val=true)
Definition: MachineOperand.h:525
llvm::MachineOperand::isTargetIndex
bool isTargetIndex() const
isTargetIndex - Tests if this is a MO_TargetIndex operand.
Definition: MachineOperand.h:332
llvm::MachineOperand::MO_JumpTableIndex
@ MO_JumpTableIndex
Address of indexed Jump Table for switch.
Definition: MachineOperand.h:60
llvm::MachineOperand::isShuffleMask
bool isShuffleMask() const
Definition: MachineOperand.h:351
llvm::BlockAddress
The address of a basic block.
Definition: Constants.h:847
llvm::MachineOperand::MO_CImmediate
@ MO_CImmediate
Immediate >64bit operand.
Definition: MachineOperand.h:54
llvm::MachineOperand::setIsDef
void setIsDef(bool Val=true)
Change a def to a use, or a use to a def.
Definition: MachineOperand.cpp:101
llvm::MachineOperand::CreateIntrinsicID
static MachineOperand CreateIntrinsicID(Intrinsic::ID ID)
Definition: MachineOperand.h:916
llvm::ArrayRef< int >
llvm::MachineOperand::getMBB
MachineBasicBlock * getMBB() const
Definition: MachineOperand.h:549
llvm::MachineOperand::CreateGA
static MachineOperand CreateGA(const GlobalValue *GV, int64_t Offset, unsigned TargetFlags=0)
Definition: MachineOperand.h:847
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
llvm::MachineOperand::ChangeToES
void ChangeToES(const char *SymName, unsigned TargetFlags=0)
ChangeToES - Replace this operand with a new external symbol operand.
Definition: MachineOperand.cpp:177
llvm::MachineOperand::isIntrinsicID
bool isIntrinsicID() const
Definition: MachineOperand.h:349
llvm::MachineOperand::setIsEarlyClobber
void setIsEarlyClobber(bool Val=true)
Definition: MachineOperand.h:520
llvm::MachineOperand::setIsUndef
void setIsUndef(bool Val=true)
Definition: MachineOperand.h:508
uint32_t
llvm::MachineOperand::setIsRenamable
void setIsRenamable(bool Val=true)
Definition: MachineOperand.cpp:136
llvm::MachineOperand::MO_MachineBasicBlock
@ MO_MachineBasicBlock
MachineBasicBlock reference.
Definition: MachineOperand.h:56
llvm::MachineOperand::MO_Last
@ MO_Last
Definition: MachineOperand.h:72
llvm::MachineOperand::isDef
bool isDef() const
Definition: MachineOperand.h:372
llvm::MachineOperand::MO_IntrinsicID
@ MO_IntrinsicID
Intrinsic ID for ISel.
Definition: MachineOperand.h:69
llvm::MachineOperand::CreateCImm
static MachineOperand CreateCImm(const ConstantInt *CI)
Definition: MachineOperand.h:776
llvm::MachineOperand::setIndex
void setIndex(int Idx)
Definition: MachineOperand.h:675
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::MachineOperand::getSubReg
unsigned getSubReg() const
Definition: MachineOperand.h:362
llvm::DenseMapInfo< MachineOperand >::getEmptyKey
static MachineOperand getEmptyKey()
Definition: MachineOperand.h:964
llvm::ISD::FrameIndex
@ FrameIndex
Definition: ISDOpcodes.h:73
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::MachineOperand::printTargetFlags
static void printTargetFlags(raw_ostream &OS, const MachineOperand &Op)
Print operand target flags.
Definition: MachineOperand.cpp:525
llvm::AMDGPU::HSAMD::Kernel::Key::SymbolName
constexpr char SymbolName[]
Key for Kernel::Metadata::mSymbolName.
Definition: AMDGPUMetadata.h:381
llvm::MachineOperand::ChangeToGA
void ChangeToGA(const GlobalValue *GV, int64_t Offset, unsigned TargetFlags=0)
ChangeToGA - Replace this operand with a new global address operand.
Definition: MachineOperand.cpp:190
llvm::GraphProgram::Name
Name
Definition: GraphWriter.h:52
llvm::MachineOperand::readsReg
bool readsReg() const
readsReg - Returns true if this operand reads the previous value of its register.
Definition: MachineOperand.h:455
llvm::MachineOperand::isMetadata
bool isMetadata() const
isMetadata - Tests if this is a MO_Metadata operand.
Definition: MachineOperand.h:346
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:314
llvm::MachineOperand::MO_ExternalSymbol
@ MO_ExternalSymbol
Name of external global symbol.
Definition: MachineOperand.h:61
llvm::MachineOperand::getIndex
int getIndex() const
Definition: MachineOperand.h:554
llvm::MachineOperand::setFPImm
void setFPImm(const ConstantFP *CFP)
Definition: MachineOperand.h:662
llvm::MachineOperand::getCFIIndex
unsigned getCFIIndex() const
Definition: MachineOperand.h:575
llvm::MachineOperand::isCFIIndex
bool isCFIIndex() const
Definition: MachineOperand.h:348
llvm::MachineOperand::setImplicit
void setImplicit(bool Val=true)
Definition: MachineOperand.h:492
llvm::MachineOperand::isImm
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
Definition: MachineOperand.h:320
llvm::MachineOperand::isDebug
bool isDebug() const
Definition: MachineOperand.h:443
llvm::MachineOperand::isFPImm
bool isFPImm() const
isFPImm - Tests if this is a MO_FPImmediate operand.
Definition: MachineOperand.h:324
llvm::MachineOperand::isPredicate
bool isPredicate() const
Definition: MachineOperand.h:350
llvm::MachineOperand::CreateRegMask
static MachineOperand CreateRegMask(const uint32_t *Mask)
CreateRegMask - Creates a register mask operand referencing Mask.
Definition: MachineOperand.h:883
llvm::MachineOperand::getSymbolName
const char * getSymbolName() const
Definition: MachineOperand.h:605
llvm::MachineOperand::OffsetLo
unsigned OffsetLo
Definition: MachineOperand.h:157
llvm::MachineOperand::setReg
void setReg(Register Reg)
Change the register this operand corresponds to.
Definition: MachineOperand.cpp:55
llvm::MachineOperand::clearParent
void clearParent()
clearParent - Reset the parent pointer.
Definition: MachineOperand.h:246
llvm::MachineOperand::setMBB
void setMBB(MachineBasicBlock *MBB)
Definition: MachineOperand.h:686
llvm::MachineOperand::isInternalRead
bool isInternalRead() const
Definition: MachineOperand.h:428
llvm::MachineOperand::getRegLiveOut
const uint32_t * getRegLiveOut() const
getRegLiveOut - Returns a bit mask of live-out registers.
Definition: MachineOperand.h:638
DataTypes.h
llvm::MachineOperand::substPhysReg
void substPhysReg(MCRegister Reg, const TargetRegisterInfo &)
substPhysReg - Substitute the current register with the physical register Reg, taking any existing Su...
Definition: MachineOperand.cpp:87
Register.h
llvm::MachineOperand::MO_RegisterMask
@ MO_RegisterMask
Mask of preserved registers.
Definition: MachineOperand.h:64
llvm::MachineOperand::CreatePredicate
static MachineOperand CreatePredicate(unsigned Pred)
Definition: MachineOperand.h:922
SubReg
unsigned SubReg
Definition: AArch64AdvSIMDScalarPass.cpp:104
llvm::MachineOperand::CreateFPImm
static MachineOperand CreateFPImm(const ConstantFP *CFP)
Definition: MachineOperand.h:782
llvm::MachineOperand::CreateTargetIndex
static MachineOperand CreateTargetIndex(unsigned Idx, int64_t Offset, unsigned TargetFlags=0)
Definition: MachineOperand.h:833
llvm::ISD::MCSymbol
@ MCSymbol
Definition: ISDOpcodes.h:165
llvm::MachineOperand::isIdenticalTo
bool isIdenticalTo(const MachineOperand &Other) const
Returns true if this operand is identical to the specified operand except for liveness related flags ...
Definition: MachineOperand.cpp:282
llvm::MachineOperand::CreateRegLiveOut
static MachineOperand CreateRegLiveOut(const uint32_t *Mask)
Definition: MachineOperand.h:889
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:22
llvm::MachineOperand::isGlobal
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
Definition: MachineOperand.h:336
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:38
llvm::hash_code
An opaque object representing a hash code.
Definition: Hashing.h:72
llvm::MachineOperand::MO_ConstantPoolIndex
@ MO_ConstantPoolIndex
Address of indexed Constant in Constant Pool.
Definition: MachineOperand.h:58
llvm::LLT
Definition: LowLevelTypeImpl.h:40
llvm::MachineOperand::setOffset
void setOffset(int64_t Offset)
Definition: MachineOperand.h:667