LLVM  14.0.0git
MachineOperand.h
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1 //===-- llvm/CodeGen/MachineOperand.h - MachineOperand class ----*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the declaration of the MachineOperand class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_CODEGEN_MACHINEOPERAND_H
14 #define LLVM_CODEGEN_MACHINEOPERAND_H
15 
16 #include "llvm/ADT/DenseMap.h"
17 #include "llvm/CodeGen/Register.h"
18 #include "llvm/IR/Intrinsics.h"
19 #include "llvm/Support/DataTypes.h"
21 #include <cassert>
22 
23 namespace llvm {
24 
25 class BlockAddress;
26 class Constant;
27 class ConstantFP;
28 class ConstantInt;
29 class GlobalValue;
30 class MachineBasicBlock;
31 class MachineInstr;
32 class MachineRegisterInfo;
33 class MCCFIInstruction;
34 class MDNode;
35 class ModuleSlotTracker;
36 class TargetIntrinsicInfo;
37 class TargetRegisterInfo;
38 class hash_code;
39 class raw_ostream;
40 class MCSymbol;
41 
42 /// MachineOperand class - Representation of each machine instruction operand.
43 ///
44 /// This class isn't a POD type because it has a private constructor, but its
45 /// destructor must be trivial. Functions like MachineInstr::addOperand(),
46 /// MachineRegisterInfo::moveOperands(), and MF::DeleteMachineInstr() depend on
47 /// not having to call the MachineOperand destructor.
48 ///
50 public:
51  enum MachineOperandType : unsigned char {
52  MO_Register, ///< Register operand.
53  MO_Immediate, ///< Immediate operand
54  MO_CImmediate, ///< Immediate >64bit operand
55  MO_FPImmediate, ///< Floating-point immediate operand
56  MO_MachineBasicBlock, ///< MachineBasicBlock reference
57  MO_FrameIndex, ///< Abstract Stack Frame Index
58  MO_ConstantPoolIndex, ///< Address of indexed Constant in Constant Pool
59  MO_TargetIndex, ///< Target-dependent index+offset operand.
60  MO_JumpTableIndex, ///< Address of indexed Jump Table for switch
61  MO_ExternalSymbol, ///< Name of external global symbol
62  MO_GlobalAddress, ///< Address of a global value
63  MO_BlockAddress, ///< Address of a basic block
64  MO_RegisterMask, ///< Mask of preserved registers.
65  MO_RegisterLiveOut, ///< Mask of live-out registers.
66  MO_Metadata, ///< Metadata reference (for debug info)
67  MO_MCSymbol, ///< MCSymbol reference (for debug/eh info)
68  MO_CFIIndex, ///< MCCFIInstruction index.
69  MO_IntrinsicID, ///< Intrinsic ID for ISel
70  MO_Predicate, ///< Generic predicate for ISel
71  MO_ShuffleMask, ///< Other IR Constant for ISel (shuffle masks)
73  };
74 
75 private:
76  /// OpKind - Specify what kind of operand this is. This discriminates the
77  /// union.
78  unsigned OpKind : 8;
79 
80  /// Subregister number for MO_Register. A value of 0 indicates the
81  /// MO_Register has no subReg.
82  ///
83  /// For all other kinds of operands, this field holds target-specific flags.
84  unsigned SubReg_TargetFlags : 12;
85 
86  /// TiedTo - Non-zero when this register operand is tied to another register
87  /// operand. The encoding of this field is described in the block comment
88  /// before MachineInstr::tieOperands().
89  unsigned TiedTo : 4;
90 
91  /// IsDef - True if this is a def, false if this is a use of the register.
92  /// This is only valid on register operands.
93  ///
94  unsigned IsDef : 1;
95 
96  /// IsImp - True if this is an implicit def or use, false if it is explicit.
97  /// This is only valid on register opderands.
98  ///
99  unsigned IsImp : 1;
100 
101  /// IsDeadOrKill
102  /// For uses: IsKill - Conservatively indicates the last use of a register
103  /// on this path through the function. A register operand with true value of
104  /// this flag must be the last use of the register, a register operand with
105  /// false value may or may not be the last use of the register. After regalloc
106  /// we can use recomputeLivenessFlags to get precise kill flags.
107  /// For defs: IsDead - True if this register is never used by a subsequent
108  /// instruction.
109  /// This is only valid on register operands.
110  unsigned IsDeadOrKill : 1;
111 
112  /// See isRenamable().
113  unsigned IsRenamable : 1;
114 
115  /// IsUndef - True if this register operand reads an "undef" value, i.e. the
116  /// read value doesn't matter. This flag can be set on both use and def
117  /// operands. On a sub-register def operand, it refers to the part of the
118  /// register that isn't written. On a full-register def operand, it is a
119  /// noop. See readsReg().
120  ///
121  /// This is only valid on registers.
122  ///
123  /// Note that an instruction may have multiple <undef> operands referring to
124  /// the same register. In that case, the instruction may depend on those
125  /// operands reading the same dont-care value. For example:
126  ///
127  /// %1 = XOR undef %2, undef %2
128  ///
129  /// Any register can be used for %2, and its value doesn't matter, but
130  /// the two operands must be the same register.
131  ///
132  unsigned IsUndef : 1;
133 
134  /// IsInternalRead - True if this operand reads a value that was defined
135  /// inside the same instruction or bundle. This flag can be set on both use
136  /// and def operands. On a sub-register def operand, it refers to the part
137  /// of the register that isn't written. On a full-register def operand, it
138  /// is a noop.
139  ///
140  /// When this flag is set, the instruction bundle must contain at least one
141  /// other def of the register. If multiple instructions in the bundle define
142  /// the register, the meaning is target-defined.
143  unsigned IsInternalRead : 1;
144 
145  /// IsEarlyClobber - True if this MO_Register 'def' operand is written to
146  /// by the MachineInstr before all input registers are read. This is used to
147  /// model the GCC inline asm '&' constraint modifier.
148  unsigned IsEarlyClobber : 1;
149 
150  /// IsDebug - True if this MO_Register 'use' operand is in a debug pseudo,
151  /// not a real instruction. Such uses should be ignored during codegen.
152  unsigned IsDebug : 1;
153 
154  /// SmallContents - This really should be part of the Contents union, but
155  /// lives out here so we can get a better packed struct.
156  /// MO_Register: Register number.
157  /// OffsetedInfo: Low bits of offset.
158  union {
159  unsigned RegNo; // For MO_Register.
160  unsigned OffsetLo; // Matches Contents.OffsetedInfo.OffsetHi.
161  } SmallContents;
162 
163  /// ParentMI - This is the instruction that this operand is embedded into.
164  /// This is valid for all operand types, when the operand is in an instr.
165  MachineInstr *ParentMI;
166 
167  /// Contents union - This contains the payload for the various operand types.
168  union ContentsUnion {
169  ContentsUnion() {}
170  MachineBasicBlock *MBB; // For MO_MachineBasicBlock.
171  const ConstantFP *CFP; // For MO_FPImmediate.
172  const ConstantInt *CI; // For MO_CImmediate. Integers > 64bit.
173  int64_t ImmVal; // For MO_Immediate.
174  const uint32_t *RegMask; // For MO_RegisterMask and MO_RegisterLiveOut.
175  const MDNode *MD; // For MO_Metadata.
176  MCSymbol *Sym; // For MO_MCSymbol.
177  unsigned CFIIndex; // For MO_CFI.
178  Intrinsic::ID IntrinsicID; // For MO_IntrinsicID.
179  unsigned Pred; // For MO_Predicate
180  ArrayRef<int> ShuffleMask; // For MO_ShuffleMask
181 
182  struct { // For MO_Register.
183  // Register number is in SmallContents.RegNo.
184  MachineOperand *Prev; // Access list for register. See MRI.
185  MachineOperand *Next;
186  } Reg;
187 
188  /// OffsetedInfo - This struct contains the offset and an object identifier.
189  /// this represent the object as with an optional offset from it.
190  struct {
191  union {
192  int Index; // For MO_*Index - The index itself.
193  const char *SymbolName; // For MO_ExternalSymbol.
194  const GlobalValue *GV; // For MO_GlobalAddress.
195  const BlockAddress *BA; // For MO_BlockAddress.
196  } Val;
197  // Low bits of offset are in SmallContents.OffsetLo.
198  int OffsetHi; // An offset from the object, high 32 bits.
199  } OffsetedInfo;
200  } Contents;
201 
202  explicit MachineOperand(MachineOperandType K)
203  : OpKind(K), SubReg_TargetFlags(0), ParentMI(nullptr) {
204  // Assert that the layout is what we expect. It's easy to grow this object.
205  static_assert(alignof(MachineOperand) <= alignof(int64_t),
206  "MachineOperand shouldn't be more than 8 byte aligned");
207  static_assert(sizeof(Contents) <= 2 * sizeof(void *),
208  "Contents should be at most two pointers");
209  static_assert(sizeof(MachineOperand) <=
210  alignTo<alignof(int64_t)>(2 * sizeof(unsigned) +
211  3 * sizeof(void *)),
212  "MachineOperand too big. Should be Kind, SmallContents, "
213  "ParentMI, and Contents");
214  }
215 
216 public:
217  /// getType - Returns the MachineOperandType for this operand.
218  ///
219  MachineOperandType getType() const { return (MachineOperandType)OpKind; }
220 
221  unsigned getTargetFlags() const {
222  return isReg() ? 0 : SubReg_TargetFlags;
223  }
224  void setTargetFlags(unsigned F) {
225  assert(!isReg() && "Register operands can't have target flags");
226  SubReg_TargetFlags = F;
227  assert(SubReg_TargetFlags == F && "Target flags out of range");
228  }
229  void addTargetFlag(unsigned F) {
230  assert(!isReg() && "Register operands can't have target flags");
231  SubReg_TargetFlags |= F;
232  assert((SubReg_TargetFlags & F) && "Target flags out of range");
233  }
234 
235 
236  /// getParent - Return the instruction that this operand belongs to.
237  ///
238  MachineInstr *getParent() { return ParentMI; }
239  const MachineInstr *getParent() const { return ParentMI; }
240 
241  /// clearParent - Reset the parent pointer.
242  ///
243  /// The MachineOperand copy constructor also copies ParentMI, expecting the
244  /// original to be deleted. If a MachineOperand is ever stored outside a
245  /// MachineInstr, the parent pointer must be cleared.
246  ///
247  /// Never call clearParent() on an operand in a MachineInstr.
248  ///
249  void clearParent() { ParentMI = nullptr; }
250 
251  /// Print a subreg index operand.
252  /// MO_Immediate operands can also be subreg idices. If it's the case, the
253  /// subreg index name will be printed. MachineInstr::isOperandSubregIdx can be
254  /// called to check this.
255  static void printSubRegIdx(raw_ostream &OS, uint64_t Index,
256  const TargetRegisterInfo *TRI);
257 
258  /// Print operand target flags.
259  static void printTargetFlags(raw_ostream& OS, const MachineOperand &Op);
260 
261  /// Print a MCSymbol as an operand.
262  static void printSymbol(raw_ostream &OS, MCSymbol &Sym);
263 
264  /// Print a stack object reference.
265  static void printStackObjectReference(raw_ostream &OS, unsigned FrameIndex,
266  bool IsFixed, StringRef Name);
267 
268  /// Print the offset with explicit +/- signs.
269  static void printOperandOffset(raw_ostream &OS, int64_t Offset);
270 
271  /// Print an IRSlotNumber.
272  static void printIRSlotNumber(raw_ostream &OS, int Slot);
273 
274  /// Print the MachineOperand to \p os.
275  /// Providing a valid \p TRI and \p IntrinsicInfo results in a more
276  /// target-specific printing. If \p TRI and \p IntrinsicInfo are null, the
277  /// function will try to pick it up from the parent.
278  void print(raw_ostream &os, const TargetRegisterInfo *TRI = nullptr,
279  const TargetIntrinsicInfo *IntrinsicInfo = nullptr) const;
280 
281  /// More complex way of printing a MachineOperand.
282  /// \param TypeToPrint specifies the generic type to be printed on uses and
283  /// defs. It can be determined using MachineInstr::getTypeToPrint.
284  /// \param OpIdx - specifies the index of the operand in machine instruction.
285  /// This will be used by target dependent MIR formatter. Could be None if the
286  /// index is unknown, e.g. called by dump().
287  /// \param PrintDef - whether we want to print `def` on an operand which
288  /// isDef. Sometimes, if the operand is printed before '=', we don't print
289  /// `def`.
290  /// \param IsStandalone - whether we want a verbose output of the MO. This
291  /// prints extra information that can be easily inferred when printing the
292  /// whole function, but not when printing only a fragment of it.
293  /// \param ShouldPrintRegisterTies - whether we want to print register ties.
294  /// Sometimes they are easily determined by the instruction's descriptor
295  /// (MachineInstr::hasComplexRegiterTies can determine if it's needed).
296  /// \param TiedOperandIdx - if we need to print register ties this needs to
297  /// provide the index of the tied register. If not, it will be ignored.
298  /// \param TRI - provide more target-specific information to the printer.
299  /// Unlike the previous function, this one will not try and get the
300  /// information from it's parent.
301  /// \param IntrinsicInfo - same as \p TRI.
302  void print(raw_ostream &os, ModuleSlotTracker &MST, LLT TypeToPrint,
303  Optional<unsigned> OpIdx, bool PrintDef, bool IsStandalone,
304  bool ShouldPrintRegisterTies, unsigned TiedOperandIdx,
305  const TargetRegisterInfo *TRI,
306  const TargetIntrinsicInfo *IntrinsicInfo) const;
307 
308  /// Same as print(os, TRI, IntrinsicInfo), but allows to specify the low-level
309  /// type to be printed the same way the full version of print(...) does it.
310  void print(raw_ostream &os, LLT TypeToPrint,
311  const TargetRegisterInfo *TRI = nullptr,
312  const TargetIntrinsicInfo *IntrinsicInfo = nullptr) const;
313 
314  void dump() const;
315 
316  //===--------------------------------------------------------------------===//
317  // Accessors that tell you what kind of MachineOperand you're looking at.
318  //===--------------------------------------------------------------------===//
319 
320  /// isReg - Tests if this is a MO_Register operand.
321  bool isReg() const { return OpKind == MO_Register; }
322  /// isImm - Tests if this is a MO_Immediate operand.
323  bool isImm() const { return OpKind == MO_Immediate; }
324  /// isCImm - Test if this is a MO_CImmediate operand.
325  bool isCImm() const { return OpKind == MO_CImmediate; }
326  /// isFPImm - Tests if this is a MO_FPImmediate operand.
327  bool isFPImm() const { return OpKind == MO_FPImmediate; }
328  /// isMBB - Tests if this is a MO_MachineBasicBlock operand.
329  bool isMBB() const { return OpKind == MO_MachineBasicBlock; }
330  /// isFI - Tests if this is a MO_FrameIndex operand.
331  bool isFI() const { return OpKind == MO_FrameIndex; }
332  /// isCPI - Tests if this is a MO_ConstantPoolIndex operand.
333  bool isCPI() const { return OpKind == MO_ConstantPoolIndex; }
334  /// isTargetIndex - Tests if this is a MO_TargetIndex operand.
335  bool isTargetIndex() const { return OpKind == MO_TargetIndex; }
336  /// isJTI - Tests if this is a MO_JumpTableIndex operand.
337  bool isJTI() const { return OpKind == MO_JumpTableIndex; }
338  /// isGlobal - Tests if this is a MO_GlobalAddress operand.
339  bool isGlobal() const { return OpKind == MO_GlobalAddress; }
340  /// isSymbol - Tests if this is a MO_ExternalSymbol operand.
341  bool isSymbol() const { return OpKind == MO_ExternalSymbol; }
342  /// isBlockAddress - Tests if this is a MO_BlockAddress operand.
343  bool isBlockAddress() const { return OpKind == MO_BlockAddress; }
344  /// isRegMask - Tests if this is a MO_RegisterMask operand.
345  bool isRegMask() const { return OpKind == MO_RegisterMask; }
346  /// isRegLiveOut - Tests if this is a MO_RegisterLiveOut operand.
347  bool isRegLiveOut() const { return OpKind == MO_RegisterLiveOut; }
348  /// isMetadata - Tests if this is a MO_Metadata operand.
349  bool isMetadata() const { return OpKind == MO_Metadata; }
350  bool isMCSymbol() const { return OpKind == MO_MCSymbol; }
351  bool isCFIIndex() const { return OpKind == MO_CFIIndex; }
352  bool isIntrinsicID() const { return OpKind == MO_IntrinsicID; }
353  bool isPredicate() const { return OpKind == MO_Predicate; }
354  bool isShuffleMask() const { return OpKind == MO_ShuffleMask; }
355  //===--------------------------------------------------------------------===//
356  // Accessors for Register Operands
357  //===--------------------------------------------------------------------===//
358 
359  /// getReg - Returns the register number.
360  Register getReg() const {
361  assert(isReg() && "This is not a register operand!");
362  return Register(SmallContents.RegNo);
363  }
364 
365  unsigned getSubReg() const {
366  assert(isReg() && "Wrong MachineOperand accessor");
367  return SubReg_TargetFlags;
368  }
369 
370  bool isUse() const {
371  assert(isReg() && "Wrong MachineOperand accessor");
372  return !IsDef;
373  }
374 
375  bool isDef() const {
376  assert(isReg() && "Wrong MachineOperand accessor");
377  return IsDef;
378  }
379 
380  bool isImplicit() const {
381  assert(isReg() && "Wrong MachineOperand accessor");
382  return IsImp;
383  }
384 
385  bool isDead() const {
386  assert(isReg() && "Wrong MachineOperand accessor");
387  return IsDeadOrKill & IsDef;
388  }
389 
390  bool isKill() const {
391  assert(isReg() && "Wrong MachineOperand accessor");
392  return IsDeadOrKill & !IsDef;
393  }
394 
395  bool isUndef() const {
396  assert(isReg() && "Wrong MachineOperand accessor");
397  return IsUndef;
398  }
399 
400  /// isRenamable - Returns true if this register may be renamed, i.e. it does
401  /// not generate a value that is somehow read in a way that is not represented
402  /// by the Machine IR (e.g. to meet an ABI or ISA requirement). This is only
403  /// valid on physical register operands. Virtual registers are assumed to
404  /// always be renamable regardless of the value of this field.
405  ///
406  /// Operands that are renamable can freely be changed to any other register
407  /// that is a member of the register class returned by
408  /// MI->getRegClassConstraint().
409  ///
410  /// isRenamable can return false for several different reasons:
411  ///
412  /// - ABI constraints (since liveness is not always precisely modeled). We
413  /// conservatively handle these cases by setting all physical register
414  /// operands that didn’t start out as virtual regs to not be renamable.
415  /// Also any physical register operands created after register allocation or
416  /// whose register is changed after register allocation will not be
417  /// renamable. This state is tracked in the MachineOperand::IsRenamable
418  /// bit.
419  ///
420  /// - Opcode/target constraints: for opcodes that have complex register class
421  /// requirements (e.g. that depend on other operands/instructions), we set
422  /// hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq in the machine opcode
423  /// description. Operands belonging to instructions with opcodes that are
424  /// marked hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq return false from
425  /// isRenamable(). Additionally, the AllowRegisterRenaming target property
426  /// prevents any operands from being marked renamable for targets that don't
427  /// have detailed opcode hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq
428  /// values.
429  bool isRenamable() const;
430 
431  bool isInternalRead() const {
432  assert(isReg() && "Wrong MachineOperand accessor");
433  return IsInternalRead;
434  }
435 
436  bool isEarlyClobber() const {
437  assert(isReg() && "Wrong MachineOperand accessor");
438  return IsEarlyClobber;
439  }
440 
441  bool isTied() const {
442  assert(isReg() && "Wrong MachineOperand accessor");
443  return TiedTo;
444  }
445 
446  bool isDebug() const {
447  assert(isReg() && "Wrong MachineOperand accessor");
448  return IsDebug;
449  }
450 
451  /// readsReg - Returns true if this operand reads the previous value of its
452  /// register. A use operand with the <undef> flag set doesn't read its
453  /// register. A sub-register def implicitly reads the other parts of the
454  /// register being redefined unless the <undef> flag is set.
455  ///
456  /// This refers to reading the register value from before the current
457  /// instruction or bundle. Internal bundle reads are not included.
458  bool readsReg() const {
459  assert(isReg() && "Wrong MachineOperand accessor");
460  return !isUndef() && !isInternalRead() && (isUse() || getSubReg());
461  }
462 
463  //===--------------------------------------------------------------------===//
464  // Mutators for Register Operands
465  //===--------------------------------------------------------------------===//
466 
467  /// Change the register this operand corresponds to.
468  ///
469  void setReg(Register Reg);
470 
471  void setSubReg(unsigned subReg) {
472  assert(isReg() && "Wrong MachineOperand mutator");
473  SubReg_TargetFlags = subReg;
474  assert(SubReg_TargetFlags == subReg && "SubReg out of range");
475  }
476 
477  /// substVirtReg - Substitute the current register with the virtual
478  /// subregister Reg:SubReg. Take any existing SubReg index into account,
479  /// using TargetRegisterInfo to compose the subreg indices if necessary.
480  /// Reg must be a virtual register, SubIdx can be 0.
481  ///
482  void substVirtReg(Register Reg, unsigned SubIdx, const TargetRegisterInfo&);
483 
484  /// substPhysReg - Substitute the current register with the physical register
485  /// Reg, taking any existing SubReg into account. For instance,
486  /// substPhysReg(%eax) will change %reg1024:sub_8bit to %al.
487  ///
489 
490  void setIsUse(bool Val = true) { setIsDef(!Val); }
491 
492  /// Change a def to a use, or a use to a def.
493  void setIsDef(bool Val = true);
494 
495  void setImplicit(bool Val = true) {
496  assert(isReg() && "Wrong MachineOperand mutator");
497  IsImp = Val;
498  }
499 
500  void setIsKill(bool Val = true) {
501  assert(isReg() && !IsDef && "Wrong MachineOperand mutator");
502  assert((!Val || !isDebug()) && "Marking a debug operation as kill");
503  IsDeadOrKill = Val;
504  }
505 
506  void setIsDead(bool Val = true) {
507  assert(isReg() && IsDef && "Wrong MachineOperand mutator");
508  IsDeadOrKill = Val;
509  }
510 
511  void setIsUndef(bool Val = true) {
512  assert(isReg() && "Wrong MachineOperand mutator");
513  IsUndef = Val;
514  }
515 
516  void setIsRenamable(bool Val = true);
517 
518  void setIsInternalRead(bool Val = true) {
519  assert(isReg() && "Wrong MachineOperand mutator");
520  IsInternalRead = Val;
521  }
522 
523  void setIsEarlyClobber(bool Val = true) {
524  assert(isReg() && IsDef && "Wrong MachineOperand mutator");
525  IsEarlyClobber = Val;
526  }
527 
528  void setIsDebug(bool Val = true) {
529  assert(isReg() && !IsDef && "Wrong MachineOperand mutator");
530  IsDebug = Val;
531  }
532 
533  //===--------------------------------------------------------------------===//
534  // Accessors for various operand types.
535  //===--------------------------------------------------------------------===//
536 
537  int64_t getImm() const {
538  assert(isImm() && "Wrong MachineOperand accessor");
539  return Contents.ImmVal;
540  }
541 
542  const ConstantInt *getCImm() const {
543  assert(isCImm() && "Wrong MachineOperand accessor");
544  return Contents.CI;
545  }
546 
547  const ConstantFP *getFPImm() const {
548  assert(isFPImm() && "Wrong MachineOperand accessor");
549  return Contents.CFP;
550  }
551 
553  assert(isMBB() && "Wrong MachineOperand accessor");
554  return Contents.MBB;
555  }
556 
557  int getIndex() const {
558  assert((isFI() || isCPI() || isTargetIndex() || isJTI()) &&
559  "Wrong MachineOperand accessor");
560  return Contents.OffsetedInfo.Val.Index;
561  }
562 
563  const GlobalValue *getGlobal() const {
564  assert(isGlobal() && "Wrong MachineOperand accessor");
565  return Contents.OffsetedInfo.Val.GV;
566  }
567 
568  const BlockAddress *getBlockAddress() const {
569  assert(isBlockAddress() && "Wrong MachineOperand accessor");
570  return Contents.OffsetedInfo.Val.BA;
571  }
572 
574  assert(isMCSymbol() && "Wrong MachineOperand accessor");
575  return Contents.Sym;
576  }
577 
578  unsigned getCFIIndex() const {
579  assert(isCFIIndex() && "Wrong MachineOperand accessor");
580  return Contents.CFIIndex;
581  }
582 
584  assert(isIntrinsicID() && "Wrong MachineOperand accessor");
585  return Contents.IntrinsicID;
586  }
587 
588  unsigned getPredicate() const {
589  assert(isPredicate() && "Wrong MachineOperand accessor");
590  return Contents.Pred;
591  }
592 
594  assert(isShuffleMask() && "Wrong MachineOperand accessor");
595  return Contents.ShuffleMask;
596  }
597 
598  /// Return the offset from the symbol in this operand. This always returns 0
599  /// for ExternalSymbol operands.
600  int64_t getOffset() const {
601  assert((isGlobal() || isSymbol() || isMCSymbol() || isCPI() ||
602  isTargetIndex() || isBlockAddress()) &&
603  "Wrong MachineOperand accessor");
604  return int64_t(uint64_t(Contents.OffsetedInfo.OffsetHi) << 32) |
605  SmallContents.OffsetLo;
606  }
607 
608  const char *getSymbolName() const {
609  assert(isSymbol() && "Wrong MachineOperand accessor");
610  return Contents.OffsetedInfo.Val.SymbolName;
611  }
612 
613  /// clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
614  /// It is sometimes necessary to detach the register mask pointer from its
615  /// machine operand. This static method can be used for such detached bit
616  /// mask pointers.
617  static bool clobbersPhysReg(const uint32_t *RegMask, MCRegister PhysReg) {
618  // See TargetRegisterInfo.h.
619  assert(PhysReg < (1u << 30) && "Not a physical register");
620  return !(RegMask[PhysReg / 32] & (1u << PhysReg % 32));
621  }
622 
623  /// clobbersPhysReg - Returns true if this RegMask operand clobbers PhysReg.
624  bool clobbersPhysReg(MCRegister PhysReg) const {
625  return clobbersPhysReg(getRegMask(), PhysReg);
626  }
627 
628  /// getRegMask - Returns a bit mask of registers preserved by this RegMask
629  /// operand.
630  const uint32_t *getRegMask() const {
631  assert(isRegMask() && "Wrong MachineOperand accessor");
632  return Contents.RegMask;
633  }
634 
635  /// Returns number of elements needed for a regmask array.
636  static unsigned getRegMaskSize(unsigned NumRegs) {
637  return (NumRegs + 31) / 32;
638  }
639 
640  /// getRegLiveOut - Returns a bit mask of live-out registers.
641  const uint32_t *getRegLiveOut() const {
642  assert(isRegLiveOut() && "Wrong MachineOperand accessor");
643  return Contents.RegMask;
644  }
645 
646  const MDNode *getMetadata() const {
647  assert(isMetadata() && "Wrong MachineOperand accessor");
648  return Contents.MD;
649  }
650 
651  //===--------------------------------------------------------------------===//
652  // Mutators for various operand types.
653  //===--------------------------------------------------------------------===//
654 
655  void setImm(int64_t immVal) {
656  assert(isImm() && "Wrong MachineOperand mutator");
657  Contents.ImmVal = immVal;
658  }
659 
660  void setCImm(const ConstantInt *CI) {
661  assert(isCImm() && "Wrong MachineOperand mutator");
662  Contents.CI = CI;
663  }
664 
665  void setFPImm(const ConstantFP *CFP) {
666  assert(isFPImm() && "Wrong MachineOperand mutator");
667  Contents.CFP = CFP;
668  }
669 
670  void setOffset(int64_t Offset) {
671  assert((isGlobal() || isSymbol() || isMCSymbol() || isCPI() ||
672  isTargetIndex() || isBlockAddress()) &&
673  "Wrong MachineOperand mutator");
674  SmallContents.OffsetLo = unsigned(Offset);
675  Contents.OffsetedInfo.OffsetHi = int(Offset >> 32);
676  }
677 
678  void setIndex(int Idx) {
679  assert((isFI() || isCPI() || isTargetIndex() || isJTI()) &&
680  "Wrong MachineOperand mutator");
681  Contents.OffsetedInfo.Val.Index = Idx;
682  }
683 
684  void setMetadata(const MDNode *MD) {
685  assert(isMetadata() && "Wrong MachineOperand mutator");
686  Contents.MD = MD;
687  }
688 
690  assert(isMBB() && "Wrong MachineOperand mutator");
691  Contents.MBB = MBB;
692  }
693 
694  /// Sets value of register mask operand referencing Mask. The
695  /// operand does not take ownership of the memory referenced by Mask, it must
696  /// remain valid for the lifetime of the operand. See CreateRegMask().
697  /// Any physreg with a 0 bit in the mask is clobbered by the instruction.
698  void setRegMask(const uint32_t *RegMaskPtr) {
699  assert(isRegMask() && "Wrong MachineOperand mutator");
700  Contents.RegMask = RegMaskPtr;
701  }
702 
704  assert(isIntrinsicID() && "Wrong MachineOperand mutator");
705  Contents.IntrinsicID = IID;
706  }
707 
708  void setPredicate(unsigned Predicate) {
709  assert(isPredicate() && "Wrong MachineOperand mutator");
710  Contents.Pred = Predicate;
711  }
712 
713  //===--------------------------------------------------------------------===//
714  // Other methods.
715  //===--------------------------------------------------------------------===//
716 
717  /// Returns true if this operand is identical to the specified operand except
718  /// for liveness related flags (isKill, isUndef and isDead). Note that this
719  /// should stay in sync with the hash_value overload below.
720  bool isIdenticalTo(const MachineOperand &Other) const;
721 
722  /// MachineOperand hash_value overload.
723  ///
724  /// Note that this includes the same information in the hash that
725  /// isIdenticalTo uses for comparison. It is thus suited for use in hash
726  /// tables which use that function for equality comparisons only. This must
727  /// stay exactly in sync with isIdenticalTo above.
728  friend hash_code hash_value(const MachineOperand &MO);
729 
730  /// ChangeToImmediate - Replace this operand with a new immediate operand of
731  /// the specified value. If an operand is known to be an immediate already,
732  /// the setImm method should be used.
733  void ChangeToImmediate(int64_t ImmVal, unsigned TargetFlags = 0);
734 
735  /// ChangeToFPImmediate - Replace this operand with a new FP immediate operand
736  /// of the specified value. If an operand is known to be an FP immediate
737  /// already, the setFPImm method should be used.
738  void ChangeToFPImmediate(const ConstantFP *FPImm, unsigned TargetFlags = 0);
739 
740  /// ChangeToES - Replace this operand with a new external symbol operand.
741  void ChangeToES(const char *SymName, unsigned TargetFlags = 0);
742 
743  /// ChangeToGA - Replace this operand with a new global address operand.
744  void ChangeToGA(const GlobalValue *GV, int64_t Offset,
745  unsigned TargetFlags = 0);
746 
747  /// ChangeToMCSymbol - Replace this operand with a new MC symbol operand.
748  void ChangeToMCSymbol(MCSymbol *Sym, unsigned TargetFlags = 0);
749 
750  /// Replace this operand with a frame index.
751  void ChangeToFrameIndex(int Idx, unsigned TargetFlags = 0);
752 
753  /// Replace this operand with a target index.
754  void ChangeToTargetIndex(unsigned Idx, int64_t Offset,
755  unsigned TargetFlags = 0);
756 
757  /// ChangeToRegister - Replace this operand with a new register operand of
758  /// the specified value. If an operand is known to be an register already,
759  /// the setReg method should be used.
760  void ChangeToRegister(Register Reg, bool isDef, bool isImp = false,
761  bool isKill = false, bool isDead = false,
762  bool isUndef = false, bool isDebug = false);
763 
764  /// getTargetIndexName - If this MachineOperand is a TargetIndex that has a
765  /// name, attempt to get the name. Returns nullptr if the TargetIndex does not
766  /// have a name. Asserts if MO is not a TargetIndex.
767  const char *getTargetIndexName() const;
768 
769  //===--------------------------------------------------------------------===//
770  // Construction methods.
771  //===--------------------------------------------------------------------===//
772 
773  static MachineOperand CreateImm(int64_t Val) {
775  Op.setImm(Val);
776  return Op;
777  }
778 
781  Op.Contents.CI = CI;
782  return Op;
783  }
784 
785  static MachineOperand CreateFPImm(const ConstantFP *CFP) {
787  Op.Contents.CFP = CFP;
788  return Op;
789  }
790 
791  static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp = false,
792  bool isKill = false, bool isDead = false,
793  bool isUndef = false,
794  bool isEarlyClobber = false,
795  unsigned SubReg = 0, bool isDebug = false,
796  bool isInternalRead = false,
797  bool isRenamable = false) {
798  assert(!(isDead && !isDef) && "Dead flag on non-def");
799  assert(!(isKill && isDef) && "Kill flag on def");
801  Op.IsDef = isDef;
802  Op.IsImp = isImp;
803  Op.IsDeadOrKill = isKill | isDead;
804  Op.IsRenamable = isRenamable;
805  Op.IsUndef = isUndef;
806  Op.IsInternalRead = isInternalRead;
807  Op.IsEarlyClobber = isEarlyClobber;
808  Op.TiedTo = 0;
809  Op.IsDebug = isDebug;
810  Op.SmallContents.RegNo = Reg;
811  Op.Contents.Reg.Prev = nullptr;
812  Op.Contents.Reg.Next = nullptr;
813  Op.setSubReg(SubReg);
814  return Op;
815  }
817  unsigned TargetFlags = 0) {
819  Op.setMBB(MBB);
820  Op.setTargetFlags(TargetFlags);
821  return Op;
822  }
823  static MachineOperand CreateFI(int Idx) {
825  Op.setIndex(Idx);
826  return Op;
827  }
828  static MachineOperand CreateCPI(unsigned Idx, int Offset,
829  unsigned TargetFlags = 0) {
831  Op.setIndex(Idx);
832  Op.setOffset(Offset);
833  Op.setTargetFlags(TargetFlags);
834  return Op;
835  }
836  static MachineOperand CreateTargetIndex(unsigned Idx, int64_t Offset,
837  unsigned TargetFlags = 0) {
839  Op.setIndex(Idx);
840  Op.setOffset(Offset);
841  Op.setTargetFlags(TargetFlags);
842  return Op;
843  }
844  static MachineOperand CreateJTI(unsigned Idx, unsigned TargetFlags = 0) {
846  Op.setIndex(Idx);
847  Op.setTargetFlags(TargetFlags);
848  return Op;
849  }
850  static MachineOperand CreateGA(const GlobalValue *GV, int64_t Offset,
851  unsigned TargetFlags = 0) {
853  Op.Contents.OffsetedInfo.Val.GV = GV;
854  Op.setOffset(Offset);
855  Op.setTargetFlags(TargetFlags);
856  return Op;
857  }
858  static MachineOperand CreateES(const char *SymName,
859  unsigned TargetFlags = 0) {
861  Op.Contents.OffsetedInfo.Val.SymbolName = SymName;
862  Op.setOffset(0); // Offset is always 0.
863  Op.setTargetFlags(TargetFlags);
864  return Op;
865  }
866  static MachineOperand CreateBA(const BlockAddress *BA, int64_t Offset,
867  unsigned TargetFlags = 0) {
869  Op.Contents.OffsetedInfo.Val.BA = BA;
870  Op.setOffset(Offset);
871  Op.setTargetFlags(TargetFlags);
872  return Op;
873  }
874  /// CreateRegMask - Creates a register mask operand referencing Mask. The
875  /// operand does not take ownership of the memory referenced by Mask, it
876  /// must remain valid for the lifetime of the operand.
877  ///
878  /// A RegMask operand represents a set of non-clobbered physical registers
879  /// on an instruction that clobbers many registers, typically a call. The
880  /// bit mask has a bit set for each physreg that is preserved by this
881  /// instruction, as described in the documentation for
882  /// TargetRegisterInfo::getCallPreservedMask().
883  ///
884  /// Any physreg with a 0 bit in the mask is clobbered by the instruction.
885  ///
887  assert(Mask && "Missing register mask");
889  Op.Contents.RegMask = Mask;
890  return Op;
891  }
893  assert(Mask && "Missing live-out register mask");
895  Op.Contents.RegMask = Mask;
896  return Op;
897  }
898  static MachineOperand CreateMetadata(const MDNode *Meta) {
900  Op.Contents.MD = Meta;
901  return Op;
902  }
903 
905  unsigned TargetFlags = 0) {
907  Op.Contents.Sym = Sym;
908  Op.setOffset(0);
909  Op.setTargetFlags(TargetFlags);
910  return Op;
911  }
912 
913  static MachineOperand CreateCFIIndex(unsigned CFIIndex) {
915  Op.Contents.CFIIndex = CFIIndex;
916  return Op;
917  }
918 
921  Op.Contents.IntrinsicID = ID;
922  return Op;
923  }
924 
925  static MachineOperand CreatePredicate(unsigned Pred) {
927  Op.Contents.Pred = Pred;
928  return Op;
929  }
930 
933  Op.Contents.ShuffleMask = Mask;
934  return Op;
935  }
936 
937  friend class MachineInstr;
938  friend class MachineRegisterInfo;
939 
940 private:
941  // If this operand is currently a register operand, and if this is in a
942  // function, deregister the operand from the register's use/def list.
943  void removeRegFromUses();
944 
945  /// Artificial kinds for DenseMap usage.
946  enum : unsigned char {
947  MO_Empty = MO_Last + 1,
948  MO_Tombstone,
949  };
950 
951  friend struct DenseMapInfo<MachineOperand>;
952 
953  //===--------------------------------------------------------------------===//
954  // Methods for handling register use/def lists.
955  //===--------------------------------------------------------------------===//
956 
957  /// isOnRegUseList - Return true if this operand is on a register use/def
958  /// list or false if not. This can only be called for register operands
959  /// that are part of a machine instruction.
960  bool isOnRegUseList() const {
961  assert(isReg() && "Can only add reg operand to use lists");
962  return Contents.Reg.Prev != nullptr;
963  }
964 };
965 
966 template <> struct DenseMapInfo<MachineOperand> {
969  MachineOperand::MO_Empty));
970  }
973  MachineOperand::MO_Tombstone));
974  }
975  static unsigned getHashValue(const MachineOperand &MO) {
976  return hash_value(MO);
977  }
978  static bool isEqual(const MachineOperand &LHS, const MachineOperand &RHS) {
979  if (LHS.getType() == static_cast<MachineOperand::MachineOperandType>(
980  MachineOperand::MO_Empty) ||
981  LHS.getType() == static_cast<MachineOperand::MachineOperandType>(
982  MachineOperand::MO_Tombstone))
983  return LHS.getType() == RHS.getType();
984  return LHS.isIdenticalTo(RHS);
985  }
986 };
987 
989  MO.print(OS);
990  return OS;
991 }
992 
993 // See friend declaration above. This additional declaration is required in
994 // order to compile LLVM with IBM xlC compiler.
995 hash_code hash_value(const MachineOperand &MO);
996 } // namespace llvm
997 
998 #endif
llvm::MachineOperand::CreateCPI
static MachineOperand CreateCPI(unsigned Idx, int Offset, unsigned TargetFlags=0)
Definition: MachineOperand.h:828
llvm::alignTo
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
Definition: Alignment.h:148
llvm::MachineOperand::CreateJTI
static MachineOperand CreateJTI(unsigned Idx, unsigned TargetFlags=0)
Definition: MachineOperand.h:844
llvm::MachineOperand::MO_BlockAddress
@ MO_BlockAddress
Address of a basic block.
Definition: MachineOperand.h:63
llvm::MachineOperand::setRegMask
void setRegMask(const uint32_t *RegMaskPtr)
Sets value of register mask operand referencing Mask.
Definition: MachineOperand.h:698
llvm::MachineOperand::MO_Immediate
@ MO_Immediate
Immediate operand.
Definition: MachineOperand.h:53
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::MCSymbol
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
llvm::MachineOperand::setIsInternalRead
void setIsInternalRead(bool Val=true)
Definition: MachineOperand.h:518
llvm::MachineOperand::isBlockAddress
bool isBlockAddress() const
isBlockAddress - Tests if this is a MO_BlockAddress operand.
Definition: MachineOperand.h:343
llvm::MachineOperand::CreateReg
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
Definition: MachineOperand.h:791
llvm::MachineOperand::MachineOperandType
MachineOperandType
Definition: MachineOperand.h:51
llvm::MachineOperand::MO_ShuffleMask
@ MO_ShuffleMask
Other IR Constant for ISel (shuffle masks)
Definition: MachineOperand.h:71
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
llvm::MachineOperand::getGlobal
const GlobalValue * getGlobal() const
Definition: MachineOperand.h:563
llvm::MachineOperand::MO_RegisterLiveOut
@ MO_RegisterLiveOut
Mask of live-out registers.
Definition: MachineOperand.h:65
llvm::ISD::ConstantFP
@ ConstantFP
Definition: ISDOpcodes.h:77
llvm::DenseMapInfo< MachineOperand >::getHashValue
static unsigned getHashValue(const MachineOperand &MO)
Definition: MachineOperand.h:975
llvm::MachineOperand::printStackObjectReference
static void printStackObjectReference(raw_ostream &OS, unsigned FrameIndex, bool IsFixed, StringRef Name)
Print a stack object reference.
Definition: MachineOperand.cpp:581
llvm::MachineOperand::printIRSlotNumber
static void printIRSlotNumber(raw_ostream &OS, int Slot)
Print an IRSlotNumber.
Definition: MachineOperand.cpp:604
llvm::MachineOperand::getIntrinsicID
Intrinsic::ID getIntrinsicID() const
Definition: MachineOperand.h:583
llvm::MachineOperand::setIsKill
void setIsKill(bool Val=true)
Definition: MachineOperand.h:500
llvm::MachineOperand::print
void print(raw_ostream &os, const TargetRegisterInfo *TRI=nullptr, const TargetIntrinsicInfo *IntrinsicInfo=nullptr) const
Print the MachineOperand to os.
Definition: MachineOperand.cpp:726
llvm::DenseMapInfo< MachineOperand >::isEqual
static bool isEqual(const MachineOperand &LHS, const MachineOperand &RHS)
Definition: MachineOperand.h:978
llvm::MachineOperand::getBlockAddress
const BlockAddress * getBlockAddress() const
Definition: MachineOperand.h:568
llvm::MachineOperand::isTied
bool isTied() const
Definition: MachineOperand.h:441
llvm::MachineOperand::RegNo
unsigned RegNo
Definition: MachineOperand.h:159
llvm::MachineOperand::setImm
void setImm(int64_t immVal)
Definition: MachineOperand.h:655
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:231
llvm::MachineOperand::setMetadata
void setMetadata(const MDNode *MD)
Definition: MachineOperand.h:684
llvm::MachineOperand::addTargetFlag
void addTargetFlag(unsigned F)
Definition: MachineOperand.h:229
llvm::MachineOperand::isSymbol
bool isSymbol() const
isSymbol - Tests if this is a MO_ExternalSymbol operand.
Definition: MachineOperand.h:341
llvm::MachineOperand::isJTI
bool isJTI() const
isJTI - Tests if this is a MO_JumpTableIndex operand.
Definition: MachineOperand.h:337
llvm::MachineOperand::isMCSymbol
bool isMCSymbol() const
Definition: MachineOperand.h:350
DenseMap.h
llvm::MachineOperand::CreateMetadata
static MachineOperand CreateMetadata(const MDNode *Meta)
Definition: MachineOperand.h:898
llvm::MachineOperand::CreateCFIIndex
static MachineOperand CreateCFIIndex(unsigned CFIIndex)
Definition: MachineOperand.h:913
llvm::MachineOperand::MO_CFIIndex
@ MO_CFIIndex
MCCFIInstruction index.
Definition: MachineOperand.h:68
llvm::MachineOperand::getTargetIndexName
const char * getTargetIndexName() const
getTargetIndexName - If this MachineOperand is a TargetIndex that has a name, attempt to get the name...
Definition: MachineOperand.cpp:423
llvm::MachineOperand::isCImm
bool isCImm() const
isCImm - Test if this is a MO_CImmediate operand.
Definition: MachineOperand.h:325
llvm::MachineOperand::setPredicate
void setPredicate(unsigned Predicate)
Definition: MachineOperand.h:708
llvm::Optional< unsigned >
llvm::MachineOperand::ChangeToTargetIndex
void ChangeToTargetIndex(unsigned Idx, int64_t Offset, unsigned TargetFlags=0)
Replace this operand with a target index.
Definition: MachineOperand.cpp:225
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
llvm::MachineOperand::setIsUse
void setIsUse(bool Val=true)
Definition: MachineOperand.h:490
llvm::MachineOperand::ChangeToFrameIndex
void ChangeToFrameIndex(int Idx, unsigned TargetFlags=0)
Replace this operand with a frame index.
Definition: MachineOperand.cpp:214
llvm::MachineOperand::isFI
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
Definition: MachineOperand.h:331
llvm::hash_value
hash_code hash_value(const APFloat &Arg)
See friend declarations above.
Definition: APFloat.cpp:4810
llvm::BitmaskEnumDetail::Mask
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::MachineOperand::getOffset
int64_t getOffset() const
Return the offset from the symbol in this operand.
Definition: MachineOperand.h:600
llvm::ModuleSlotTracker
Manage lifetime of a slot tracker for printing IR.
Definition: ModuleSlotTracker.h:44
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
llvm::MachineOperand::setCImm
void setCImm(const ConstantInt *CI)
Definition: MachineOperand.h:660
llvm::MachineOperand::dump
void dump() const
Definition: MachineOperand.cpp:969
llvm::MachineOperand::getMCSymbol
MCSymbol * getMCSymbol() const
Definition: MachineOperand.h:573
llvm::MachineOperand::MO_Register
@ MO_Register
Register operand.
Definition: MachineOperand.h:52
F
#define F(x, y, z)
Definition: MD5.cpp:56
llvm::MachineOperand::CreateES
static MachineOperand CreateES(const char *SymName, unsigned TargetFlags=0)
Definition: MachineOperand.h:858
llvm::MachineOperand::printSymbol
static void printSymbol(raw_ostream &OS, MCSymbol &Sym)
Print a MCSymbol as an operand.
Definition: MachineOperand.cpp:577
llvm::TargetIntrinsicInfo
TargetIntrinsicInfo - Interface to description of machine instruction set.
Definition: TargetIntrinsicInfo.h:29
llvm::MachineOperand::clobbersPhysReg
bool clobbersPhysReg(MCRegister PhysReg) const
clobbersPhysReg - Returns true if this RegMask operand clobbers PhysReg.
Definition: MachineOperand.h:624
llvm::MachineOperand::printSubRegIdx
static void printSubRegIdx(raw_ostream &OS, uint64_t Index, const TargetRegisterInfo *TRI)
Print a subreg index operand.
Definition: MachineOperand.cpp:516
llvm::MachineOperand::isKill
bool isKill() const
Definition: MachineOperand.h:390
llvm::MachineOperand::isRenamable
bool isRenamable() const
isRenamable - Returns true if this register may be renamed, i.e.
Definition: MachineOperand.cpp:118
llvm::ConstantInt
This is the shared class of boolean and integer constants.
Definition: Constants.h:79
llvm::DenseMapInfo
Definition: APInt.h:34
llvm::MachineOperand::isImplicit
bool isImplicit() const
Definition: MachineOperand.h:380
llvm::MachineOperand::hash_value
friend hash_code hash_value(const MachineOperand &MO)
MachineOperand hash_value overload.
llvm::ISD::Constant
@ Constant
Definition: ISDOpcodes.h:76
llvm::MachineOperand::CreateImm
static MachineOperand CreateImm(int64_t Val)
Definition: MachineOperand.h:773
llvm::MachineOperand::ChangeToRegister
void ChangeToRegister(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
ChangeToRegister - Replace this operand with a new register operand of the specified value.
Definition: MachineOperand.cpp:241
llvm::MachineOperand::MO_GlobalAddress
@ MO_GlobalAddress
Address of a global value.
Definition: MachineOperand.h:62
llvm::MachineOperand::getImm
int64_t getImm() const
Definition: MachineOperand.h:537
llvm::MachineOperand::getRegMaskSize
static unsigned getRegMaskSize(unsigned NumRegs)
Returns number of elements needed for a regmask array.
Definition: MachineOperand.h:636
llvm::MachineOperand::isUse
bool isUse() const
Definition: MachineOperand.h:370
Intrinsics.h
int
Clang compiles this i1 i64 store i64 i64 store i64 i64 store i64 i64 store i64 align Which gets codegen d xmm0 movaps rbp movaps rbp movaps rbp movaps rbp rbp rbp rbp rbp It would be better to have movq s of instead of the movaps s LLVM produces ret int
Definition: README.txt:536
llvm::MachineOperand::getRegMask
const uint32_t * getRegMask() const
getRegMask - Returns a bit mask of registers preserved by this RegMask operand.
Definition: MachineOperand.h:630
llvm::MachineOperand::setSubReg
void setSubReg(unsigned subReg)
Definition: MachineOperand.h:471
llvm::MachineOperand::MO_FrameIndex
@ MO_FrameIndex
Abstract Stack Frame Index.
Definition: MachineOperand.h:57
llvm::MachineOperand::isMBB
bool isMBB() const
isMBB - Tests if this is a MO_MachineBasicBlock operand.
Definition: MachineOperand.h:329
llvm::MachineOperand::ChangeToImmediate
void ChangeToImmediate(int64_t ImmVal, unsigned TargetFlags=0)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value.
Definition: MachineOperand.cpp:156
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
llvm::MachineOperand::getParent
const MachineInstr * getParent() const
Definition: MachineOperand.h:239
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:53
llvm::ConstantFP
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:257
llvm::MachineOperand::ChangeToMCSymbol
void ChangeToMCSymbol(MCSymbol *Sym, unsigned TargetFlags=0)
ChangeToMCSymbol - Replace this operand with a new MC symbol operand.
Definition: MachineOperand.cpp:203
llvm::operator<<
raw_ostream & operator<<(raw_ostream &OS, const APFixedPoint &FX)
Definition: APFixedPoint.h:230
llvm::MachineOperand::CreateFI
static MachineOperand CreateFI(int Idx)
Definition: MachineOperand.h:823
llvm::MachineOperand::setTargetFlags
void setTargetFlags(unsigned F)
Definition: MachineOperand.h:224
llvm::MachineOperand::getParent
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
Definition: MachineOperand.h:238
llvm::MachineOperand::isRegLiveOut
bool isRegLiveOut() const
isRegLiveOut - Tests if this is a MO_RegisterLiveOut operand.
Definition: MachineOperand.h:347
llvm::MachineOperand::printOperandOffset
static void printOperandOffset(raw_ostream &OS, int64_t Offset)
Print the offset with explicit +/- signs.
Definition: MachineOperand.cpp:594
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
LowLevelTypeImpl.h
llvm::MachineOperand::getMetadata
const MDNode * getMetadata() const
Definition: MachineOperand.h:646
llvm::ISD::BlockAddress
@ BlockAddress
Definition: ISDOpcodes.h:84
llvm::MachineOperand::CreateShuffleMask
static MachineOperand CreateShuffleMask(ArrayRef< int > Mask)
Definition: MachineOperand.h:931
llvm::MachineOperand::MO_Metadata
@ MO_Metadata
Metadata reference (for debug info)
Definition: MachineOperand.h:66
llvm::PPC::Predicate
Predicate
Predicate - These are "(BI << 5) | BO" for various predicates.
Definition: PPCPredicates.h:26
llvm::GlobalValue
Definition: GlobalValue.h:44
llvm::MachineOperand::clobbersPhysReg
static bool clobbersPhysReg(const uint32_t *RegMask, MCRegister PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
Definition: MachineOperand.h:617
llvm::MachineOperand::ChangeToFPImmediate
void ChangeToFPImmediate(const ConstantFP *FPImm, unsigned TargetFlags=0)
ChangeToFPImmediate - Replace this operand with a new FP immediate operand of the specified value.
Definition: MachineOperand.cpp:166
llvm::MachineOperand::isUndef
bool isUndef() const
Definition: MachineOperand.h:395
llvm::MachineOperand::setIsDead
void setIsDead(bool Val=true)
Definition: MachineOperand.h:506
llvm::MachineOperand::getTargetFlags
unsigned getTargetFlags() const
Definition: MachineOperand.h:221
llvm::MachineOperand::substVirtReg
void substVirtReg(Register Reg, unsigned SubIdx, const TargetRegisterInfo &)
substVirtReg - Substitute the current register with the virtual subregister Reg:SubReg.
Definition: MachineOperand.cpp:77
Index
uint32_t Index
Definition: ELFObjHandler.cpp:84
llvm::MachineOperand::isReg
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition: MachineOperand.h:321
llvm::MachineOperand::getCImm
const ConstantInt * getCImm() const
Definition: MachineOperand.h:542
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::MachineOperand::CreateMBB
static MachineOperand CreateMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0)
Definition: MachineOperand.h:816
llvm::DenseMapInfo< MachineOperand >::getTombstoneKey
static MachineOperand getTombstoneKey()
Definition: MachineOperand.h:971
llvm::MachineOperand::isDead
bool isDead() const
Definition: MachineOperand.h:385
llvm::MachineOperand::MO_Predicate
@ MO_Predicate
Generic predicate for ISel.
Definition: MachineOperand.h:70
llvm::MachineOperand::MO_MCSymbol
@ MO_MCSymbol
MCSymbol reference (for debug/eh info)
Definition: MachineOperand.h:67
llvm::MachineOperand::setIntrinsicID
void setIntrinsicID(Intrinsic::ID IID)
Definition: MachineOperand.h:703
llvm::MachineOperand::isCPI
bool isCPI() const
isCPI - Tests if this is a MO_ConstantPoolIndex operand.
Definition: MachineOperand.h:333
llvm::MachineOperand::getType
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
Definition: MachineOperand.h:219
llvm::MachineOperand::getFPImm
const ConstantFP * getFPImm() const
Definition: MachineOperand.h:547
llvm::MachineOperand::getPredicate
unsigned getPredicate() const
Definition: MachineOperand.h:588
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MachineOperand::isEarlyClobber
bool isEarlyClobber() const
Definition: MachineOperand.h:436
llvm::MachineOperand::getShuffleMask
ArrayRef< int > getShuffleMask() const
Definition: MachineOperand.h:593
llvm::MachineOperand::MO_TargetIndex
@ MO_TargetIndex
Target-dependent index+offset operand.
Definition: MachineOperand.h:59
llvm::MachineOperand::CreateBA
static MachineOperand CreateBA(const BlockAddress *BA, int64_t Offset, unsigned TargetFlags=0)
Definition: MachineOperand.h:866
llvm::MachineOperand::isRegMask
bool isRegMask() const
isRegMask - Tests if this is a MO_RegisterMask operand.
Definition: MachineOperand.h:345
llvm::MachineOperand::MO_FPImmediate
@ MO_FPImmediate
Floating-point immediate operand.
Definition: MachineOperand.h:55
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:360
llvm::MDNode
Metadata node.
Definition: Metadata.h:897
llvm::MachineOperand::CreateMCSymbol
static MachineOperand CreateMCSymbol(MCSymbol *Sym, unsigned TargetFlags=0)
Definition: MachineOperand.h:904
llvm::MachineOperand::setIsDebug
void setIsDebug(bool Val=true)
Definition: MachineOperand.h:528
llvm::MachineOperand::isTargetIndex
bool isTargetIndex() const
isTargetIndex - Tests if this is a MO_TargetIndex operand.
Definition: MachineOperand.h:335
llvm::MachineOperand::MO_JumpTableIndex
@ MO_JumpTableIndex
Address of indexed Jump Table for switch.
Definition: MachineOperand.h:60
llvm::MachineOperand::isShuffleMask
bool isShuffleMask() const
Definition: MachineOperand.h:354
llvm::BlockAddress
The address of a basic block.
Definition: Constants.h:848
llvm::MachineOperand::MO_CImmediate
@ MO_CImmediate
Immediate >64bit operand.
Definition: MachineOperand.h:54
llvm::MachineOperand::setIsDef
void setIsDef(bool Val=true)
Change a def to a use, or a use to a def.
Definition: MachineOperand.cpp:101
llvm::MachineOperand::CreateIntrinsicID
static MachineOperand CreateIntrinsicID(Intrinsic::ID ID)
Definition: MachineOperand.h:919
llvm::ArrayRef< int >
llvm::MachineOperand::getMBB
MachineBasicBlock * getMBB() const
Definition: MachineOperand.h:552
llvm::MachineOperand::CreateGA
static MachineOperand CreateGA(const GlobalValue *GV, int64_t Offset, unsigned TargetFlags=0)
Definition: MachineOperand.h:850
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::MachineOperand::ChangeToES
void ChangeToES(const char *SymName, unsigned TargetFlags=0)
ChangeToES - Replace this operand with a new external symbol operand.
Definition: MachineOperand.cpp:177
llvm::MachineOperand::isIntrinsicID
bool isIntrinsicID() const
Definition: MachineOperand.h:352
llvm::MachineOperand::setIsEarlyClobber
void setIsEarlyClobber(bool Val=true)
Definition: MachineOperand.h:523
llvm::MachineOperand::setIsUndef
void setIsUndef(bool Val=true)
Definition: MachineOperand.h:511
uint32_t
llvm::MachineOperand::setIsRenamable
void setIsRenamable(bool Val=true)
Definition: MachineOperand.cpp:136
llvm::MachineOperand::MO_MachineBasicBlock
@ MO_MachineBasicBlock
MachineBasicBlock reference.
Definition: MachineOperand.h:56
llvm::MachineOperand::MO_Last
@ MO_Last
Definition: MachineOperand.h:72
llvm::MachineOperand::isDef
bool isDef() const
Definition: MachineOperand.h:375
llvm::MachineOperand::MO_IntrinsicID
@ MO_IntrinsicID
Intrinsic ID for ISel.
Definition: MachineOperand.h:69
llvm::MachineOperand::CreateCImm
static MachineOperand CreateCImm(const ConstantInt *CI)
Definition: MachineOperand.h:779
llvm::MachineOperand::setIndex
void setIndex(int Idx)
Definition: MachineOperand.h:678
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::MachineOperand::getSubReg
unsigned getSubReg() const
Definition: MachineOperand.h:365
llvm::DenseMapInfo< MachineOperand >::getEmptyKey
static MachineOperand getEmptyKey()
Definition: MachineOperand.h:967
llvm::ISD::FrameIndex
@ FrameIndex
Definition: ISDOpcodes.h:80
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::MachineOperand::printTargetFlags
static void printTargetFlags(raw_ostream &OS, const MachineOperand &Op)
Print operand target flags.
Definition: MachineOperand.cpp:525
llvm::AMDGPU::HSAMD::Kernel::Key::SymbolName
constexpr char SymbolName[]
Key for Kernel::Metadata::mSymbolName.
Definition: AMDGPUMetadata.h:381
llvm::MachineOperand::ChangeToGA
void ChangeToGA(const GlobalValue *GV, int64_t Offset, unsigned TargetFlags=0)
ChangeToGA - Replace this operand with a new global address operand.
Definition: MachineOperand.cpp:190
llvm::GraphProgram::Name
Name
Definition: GraphWriter.h:52
llvm::MachineOperand::readsReg
bool readsReg() const
readsReg - Returns true if this operand reads the previous value of its register.
Definition: MachineOperand.h:458
llvm::MachineOperand::isMetadata
bool isMetadata() const
isMetadata - Tests if this is a MO_Metadata operand.
Definition: MachineOperand.h:349
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:314
llvm::MachineOperand::MO_ExternalSymbol
@ MO_ExternalSymbol
Name of external global symbol.
Definition: MachineOperand.h:61
llvm::MachineOperand::getIndex
int getIndex() const
Definition: MachineOperand.h:557
llvm::MachineOperand::setFPImm
void setFPImm(const ConstantFP *CFP)
Definition: MachineOperand.h:665
llvm::MachineOperand::getCFIIndex
unsigned getCFIIndex() const
Definition: MachineOperand.h:578
llvm::MachineOperand::isCFIIndex
bool isCFIIndex() const
Definition: MachineOperand.h:351
llvm::MachineOperand::setImplicit
void setImplicit(bool Val=true)
Definition: MachineOperand.h:495
llvm::MachineOperand::isImm
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
Definition: MachineOperand.h:323
llvm::MachineOperand::isDebug
bool isDebug() const
Definition: MachineOperand.h:446
llvm::MachineOperand::isFPImm
bool isFPImm() const
isFPImm - Tests if this is a MO_FPImmediate operand.
Definition: MachineOperand.h:327
llvm::MachineOperand::isPredicate
bool isPredicate() const
Definition: MachineOperand.h:353
llvm::MachineOperand::CreateRegMask
static MachineOperand CreateRegMask(const uint32_t *Mask)
CreateRegMask - Creates a register mask operand referencing Mask.
Definition: MachineOperand.h:886
llvm::MachineOperand::getSymbolName
const char * getSymbolName() const
Definition: MachineOperand.h:608
llvm::MachineOperand::OffsetLo
unsigned OffsetLo
Definition: MachineOperand.h:160
llvm::MachineOperand::setReg
void setReg(Register Reg)
Change the register this operand corresponds to.
Definition: MachineOperand.cpp:55
llvm::MachineOperand::clearParent
void clearParent()
clearParent - Reset the parent pointer.
Definition: MachineOperand.h:249
llvm::MachineOperand::setMBB
void setMBB(MachineBasicBlock *MBB)
Definition: MachineOperand.h:689
llvm::MachineOperand::isInternalRead
bool isInternalRead() const
Definition: MachineOperand.h:431
llvm::MachineOperand::getRegLiveOut
const uint32_t * getRegLiveOut() const
getRegLiveOut - Returns a bit mask of live-out registers.
Definition: MachineOperand.h:641
DataTypes.h
llvm::MachineOperand::substPhysReg
void substPhysReg(MCRegister Reg, const TargetRegisterInfo &)
substPhysReg - Substitute the current register with the physical register Reg, taking any existing Su...
Definition: MachineOperand.cpp:87
Register.h
llvm::MachineOperand::MO_RegisterMask
@ MO_RegisterMask
Mask of preserved registers.
Definition: MachineOperand.h:64
llvm::MachineOperand::CreatePredicate
static MachineOperand CreatePredicate(unsigned Pred)
Definition: MachineOperand.h:925
SubReg
unsigned SubReg
Definition: AArch64AdvSIMDScalarPass.cpp:104
llvm::MachineOperand::CreateFPImm
static MachineOperand CreateFPImm(const ConstantFP *CFP)
Definition: MachineOperand.h:785
llvm::MachineOperand::CreateTargetIndex
static MachineOperand CreateTargetIndex(unsigned Idx, int64_t Offset, unsigned TargetFlags=0)
Definition: MachineOperand.h:836
llvm::ISD::MCSymbol
@ MCSymbol
Definition: ISDOpcodes.h:172
llvm::MachineOperand::isIdenticalTo
bool isIdenticalTo(const MachineOperand &Other) const
Returns true if this operand is identical to the specified operand except for liveness related flags ...
Definition: MachineOperand.cpp:282
llvm::MachineOperand::CreateRegLiveOut
static MachineOperand CreateRegLiveOut(const uint32_t *Mask)
Definition: MachineOperand.h:892
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:23
llvm::MachineOperand::isGlobal
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
Definition: MachineOperand.h:339
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:38
llvm::hash_code
An opaque object representing a hash code.
Definition: Hashing.h:72
llvm::MachineOperand::MO_ConstantPoolIndex
@ MO_ConstantPoolIndex
Address of indexed Constant in Constant Pool.
Definition: MachineOperand.h:58
llvm::LLT
Definition: LowLevelTypeImpl.h:40
llvm::MachineOperand::setOffset
void setOffset(int64_t Offset)
Definition: MachineOperand.h:670