LLVM 17.0.0git
PPCDisassembler.cpp
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1//===------ PPCDisassembler.cpp - Disassembler for PowerPC ------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
13#include "llvm/MC/MCInst.h"
16#include "llvm/Support/Endian.h"
17
18using namespace llvm;
19
21
22#define DEBUG_TYPE "ppc-disassembler"
23
25
26namespace {
27class PPCDisassembler : public MCDisassembler {
28 bool IsLittleEndian;
29
30public:
31 PPCDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
32 bool IsLittleEndian)
33 : MCDisassembler(STI, Ctx), IsLittleEndian(IsLittleEndian) {}
34
36 ArrayRef<uint8_t> Bytes, uint64_t Address,
37 raw_ostream &CStream) const override;
38};
39} // end anonymous namespace
40
42 const MCSubtargetInfo &STI,
43 MCContext &Ctx) {
44 return new PPCDisassembler(STI, Ctx, /*IsLittleEndian=*/false);
45}
46
48 const MCSubtargetInfo &STI,
49 MCContext &Ctx) {
50 return new PPCDisassembler(STI, Ctx, /*IsLittleEndian=*/true);
51}
52
54 // Register the disassembler for each target.
63}
64
65static DecodeStatus decodeCondBrTarget(MCInst &Inst, unsigned Imm,
66 uint64_t /*Address*/,
67 const MCDisassembler * /*Decoder*/) {
68 Inst.addOperand(MCOperand::createImm(SignExtend32<14>(Imm)));
70}
71
72static DecodeStatus decodeDirectBrTarget(MCInst &Inst, unsigned Imm,
73 uint64_t /*Address*/,
74 const MCDisassembler * /*Decoder*/) {
75 int32_t Offset = SignExtend32<24>(Imm);
78}
79
80// FIXME: These can be generated by TableGen from the existing register
81// encoding values!
82
83template <std::size_t N>
85 const MCPhysReg (&Regs)[N]) {
86 assert(RegNo < N && "Invalid register number");
87 Inst.addOperand(MCOperand::createReg(Regs[RegNo]));
89}
90
92 uint64_t Address,
93 const MCDisassembler *Decoder) {
94 return decodeRegisterClass(Inst, RegNo, CRRegs);
95}
96
98 uint64_t Address,
99 const MCDisassembler *Decoder) {
100 return decodeRegisterClass(Inst, RegNo, CRBITRegs);
101}
102
104 uint64_t Address,
105 const MCDisassembler *Decoder) {
106 return decodeRegisterClass(Inst, RegNo, FRegs);
107}
108
110 uint64_t Address,
111 const MCDisassembler *Decoder) {
112 return decodeRegisterClass(Inst, RegNo, FRegs);
113}
114
116 uint64_t Address,
117 const MCDisassembler *Decoder) {
118 return decodeRegisterClass(Inst, RegNo, VFRegs);
119}
120
122 uint64_t Address,
123 const MCDisassembler *Decoder) {
124 return decodeRegisterClass(Inst, RegNo, VRegs);
125}
126
128 uint64_t Address,
129 const MCDisassembler *Decoder) {
130 return decodeRegisterClass(Inst, RegNo, VSRegs);
131}
132
134 uint64_t Address,
135 const MCDisassembler *Decoder) {
136 return decodeRegisterClass(Inst, RegNo, VSFRegs);
137}
138
140 uint64_t Address,
141 const MCDisassembler *Decoder) {
142 return decodeRegisterClass(Inst, RegNo, VSSRegs);
143}
144
146 uint64_t Address,
147 const MCDisassembler *Decoder) {
148 return decodeRegisterClass(Inst, RegNo, RRegs);
149}
150
151static DecodeStatus
153 const MCDisassembler *Decoder) {
154 return decodeRegisterClass(Inst, RegNo, RRegsNoR0);
155}
156
158 uint64_t Address,
159 const MCDisassembler *Decoder) {
160 return decodeRegisterClass(Inst, RegNo, XRegs);
161}
162
164 uint64_t Address,
165 const MCDisassembler *Decoder) {
166 return decodeRegisterClass(Inst, RegNo, XRegs);
167}
168
169static DecodeStatus
171 const MCDisassembler *Decoder) {
172 return decodeRegisterClass(Inst, RegNo, XRegsNoX0);
173}
174
175#define DecodePointerLikeRegClass0 DecodeGPRCRegisterClass
176#define DecodePointerLikeRegClass1 DecodeGPRC_NOR0RegisterClass
177
179 uint64_t Address,
180 const MCDisassembler *Decoder) {
181 return decodeRegisterClass(Inst, RegNo, SPERegs);
182}
183
185 uint64_t Address,
186 const MCDisassembler *Decoder) {
187 return decodeRegisterClass(Inst, RegNo, ACCRegs);
188}
189
191 uint64_t Address,
192 const void *Decoder) {
193 return decodeRegisterClass(Inst, RegNo, WACCRegs);
194}
195
197 uint64_t Address,
198 const void *Decoder) {
199 return decodeRegisterClass(Inst, RegNo, WACC_HIRegs);
200}
201
202// TODO: Make this function static when the register class is used by a new
203// instruction.
205 uint64_t Address,
206 const void *Decoder) {
207 return decodeRegisterClass(Inst, RegNo, DMRROWRegs);
208}
209
211 uint64_t Address,
212 const void *Decoder) {
213 return decodeRegisterClass(Inst, RegNo, DMRROWpRegs);
214}
215
217 uint64_t Address,
218 const void *Decoder) {
219 return decodeRegisterClass(Inst, RegNo, DMRRegs);
220}
221
222// TODO: Make this function static when the register class is used by a new
223// instruction.
225 uint64_t Address, const void *Decoder) {
226 return decodeRegisterClass(Inst, RegNo, DMRpRegs);
227}
228
230 uint64_t Address,
231 const MCDisassembler *Decoder) {
232 return decodeRegisterClass(Inst, RegNo, VSRpRegs);
233}
234
235#define DecodeQSRCRegisterClass DecodeQFRCRegisterClass
236#define DecodeQBRCRegisterClass DecodeQFRCRegisterClass
237
238template <unsigned N>
240 int64_t Address,
241 const MCDisassembler *Decoder) {
242 if (!isUInt<N>(Imm))
246}
247
248template <unsigned N>
250 int64_t Address,
251 const MCDisassembler *Decoder) {
252 if (!isUInt<N>(Imm))
254 Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm)));
256}
257
259 int64_t Address,
260 const MCDisassembler *Decoder) {
261 if (Imm != 0)
265}
266
268 uint64_t Address,
269 const MCDisassembler *Decoder) {
270 if (RegNo & 1)
272 Inst.addOperand(MCOperand::createReg(VSRpRegs[RegNo >> 1]));
274}
275
277 int64_t Address,
278 const MCDisassembler *Decoder) {
279 // The rix displacement is an immediate shifted by 2
280 Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Imm << 2)));
282}
283
285 int64_t Address,
286 const MCDisassembler *Decoder) {
287 // Decode the disp field for a hash store or hash check operation.
288 // The field is composed of an immediate value that is 6 bits
289 // and covers the range -8 to -512. The immediate is always negative and 2s
290 // complement which is why we sign extend a 7 bit value.
291 const int64_t Disp = SignExtend64<7>((Imm & 0x3F) + 64) * 8;
292
295}
296
298 int64_t Address,
299 const MCDisassembler *Decoder) {
300 // The rix16 displacement has 12-bits which are shifted by 4.
301 Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Imm << 4)));
303}
304
306 int64_t Address,
307 const MCDisassembler *Decoder) {
308 // Decode the dispSPE8 field, which has 5-bits, 8-byte aligned.
309
310 uint64_t Disp = Imm & 0x1F;
311
312 Inst.addOperand(MCOperand::createImm(Disp << 3));
314}
315
317 int64_t Address,
318 const MCDisassembler *Decoder) {
319 // Decode the dispSPE8 field, which has 5-bits, 4-byte aligned.
320
321 uint64_t Disp = Imm & 0x1F;
322
323 Inst.addOperand(MCOperand::createImm(Disp << 2));
325}
326
328 int64_t Address,
329 const MCDisassembler *Decoder) {
330 // Decode the dispSPE8 field, which has 5-bits, 2-byte aligned.
331
332 uint64_t Disp = Imm & 0x1F;
333 Inst.addOperand(MCOperand::createImm(Disp << 1));
335}
336
338 int64_t Address,
339 const MCDisassembler *Decoder) {
340 // The cr bit encoding is 0x80 >> cr_reg_num.
341
342 unsigned Zeros = llvm::countr_zero(Imm);
343 assert(Zeros < 8 && "Invalid CR bit value");
344
345 Inst.addOperand(MCOperand::createReg(CRRegs[7 - Zeros]));
347}
348
349#include "PPCGenDisassemblerTables.inc"
350
351DecodeStatus PPCDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
352 ArrayRef<uint8_t> Bytes,
353 uint64_t Address,
354 raw_ostream &CS) const {
355 auto *ReadFunc = IsLittleEndian ? support::endian::read32le
357
358 // If this is an 8-byte prefixed instruction, handle it here.
359 // Note: prefixed instructions aren't technically 8-byte entities - the prefix
360 // appears in memory at an address 4 bytes prior to that of the base
361 // instruction regardless of endianness. So we read the two pieces and
362 // rebuild the 8-byte instruction.
363 // TODO: In this function we call decodeInstruction several times with
364 // different decoder tables. It may be possible to only call once by
365 // looking at the top 6 bits of the instruction.
366 if (STI.hasFeature(PPC::FeaturePrefixInstrs) && Bytes.size() >= 8) {
367 uint32_t Prefix = ReadFunc(Bytes.data());
368 uint32_t BaseInst = ReadFunc(Bytes.data() + 4);
369 uint64_t Inst = BaseInst | (uint64_t)Prefix << 32;
370 DecodeStatus result = decodeInstruction(DecoderTable64, MI, Inst, Address,
371 this, STI);
372 if (result != MCDisassembler::Fail) {
373 Size = 8;
374 return result;
375 }
376 }
377
378 // Get the four bytes of the instruction.
379 Size = 4;
380 if (Bytes.size() < 4) {
381 Size = 0;
383 }
384
385 // Read the instruction in the proper endianness.
386 uint64_t Inst = ReadFunc(Bytes.data());
387
388 if (STI.hasFeature(PPC::FeatureSPE)) {
389 DecodeStatus result =
390 decodeInstruction(DecoderTableSPE32, MI, Inst, Address, this, STI);
391 if (result != MCDisassembler::Fail)
392 return result;
393 }
394
395 return decodeInstruction(DecoderTable32, MI, Inst, Address, this, STI);
396}
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:127
uint64_t Size
IRTranslator LLVM IR MI
static DecodeStatus decodeRegisterClass(MCInst &Inst, uint64_t RegNo, const MCPhysReg(&Regs)[N])
static DecodeStatus decodeVSRpEvenOperands(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVSFRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeDispSPE4Operand(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeDMRRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
MCDisassembler::DecodeStatus DecodeStatus
LLVM_EXTERNAL_VISIBILITY void LLVMInitializePowerPCDisassembler()
static DecodeStatus decodeCRBitMOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)
DecodeStatus DecodeDMRpRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus decodeImmZeroOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeCRBITRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPRC_NOR0RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeG8pRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeDispRIHashOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static MCDisassembler * createPPCDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
static DecodeStatus decodeDispSPE2Operand(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVSRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeCondBrTarget(MCInst &Inst, unsigned Imm, uint64_t, const MCDisassembler *)
static DecodeStatus decodeDispSPE8Operand(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVRRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static MCDisassembler * createPPCLEDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
static DecodeStatus decodeDispRIX16Operand(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeCRRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeG8RC_NOX0RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeACCRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVSSRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeWACC_HIRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeVFRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeF8RCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeSPERCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
DecodeStatus DecodeDMRROWRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeWACCRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeG8RCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeDMRROWpRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus decodeDispRIXOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeF4RCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVSRpRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeDirectBrTarget(MCInst &Inst, unsigned Imm, uint64_t, const MCDisassembler *)
#define DEFINE_PPC_REGCLASSES
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:163
const T * data() const
Definition: ArrayRef.h:160
Context object for machine code objects.
Definition: MCContext.h:76
Superclass for all disassemblers.
DecodeStatus
Ternary decode status.
virtual DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CStream) const =0
Returns the disassembly of a single instruction.
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
void addOperand(const MCOperand Op)
Definition: MCInst.h:210
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:134
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:141
Generic base class for all target subtargets.
Target - Wrapper for Target specific information.
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
uint32_t read32be(const void *P)
Definition: Endian.h:384
uint32_t read32le(const void *P)
Definition: Endian.h:381
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:406
Target & getThePPC64LETarget()
Target & getThePPC32Target()
int countr_zero(T Val)
Count number of 0's from the least significant bit to the most stopping at the first 1.
Definition: bit.h:179
Target & getThePPC64Target()
Target & getThePPC32LETarget()
#define N
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.