LLVM  14.0.0git
PPCDisassembler.cpp
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1 //===------ PPCDisassembler.cpp - Disassembler for PowerPC ------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
13 #include "llvm/MC/MCInst.h"
15 #include "llvm/Support/Endian.h"
17 
18 using namespace llvm;
19 
21 
22 #define DEBUG_TYPE "ppc-disassembler"
23 
25 
26 namespace {
27 class PPCDisassembler : public MCDisassembler {
28  bool IsLittleEndian;
29 
30 public:
31  PPCDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
32  bool IsLittleEndian)
33  : MCDisassembler(STI, Ctx), IsLittleEndian(IsLittleEndian) {}
34 
35  DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
36  ArrayRef<uint8_t> Bytes, uint64_t Address,
37  raw_ostream &CStream) const override;
38 };
39 } // end anonymous namespace
40 
42  const MCSubtargetInfo &STI,
43  MCContext &Ctx) {
44  return new PPCDisassembler(STI, Ctx, /*IsLittleEndian=*/false);
45 }
46 
48  const MCSubtargetInfo &STI,
49  MCContext &Ctx) {
50  return new PPCDisassembler(STI, Ctx, /*IsLittleEndian=*/true);
51 }
52 
54  // Register the disassembler for each target.
63 }
64 
65 static DecodeStatus decodeCondBrTarget(MCInst &Inst, unsigned Imm,
66  uint64_t /*Address*/,
67  const void * /*Decoder*/) {
68  Inst.addOperand(MCOperand::createImm(SignExtend32<14>(Imm)));
70 }
71 
72 static DecodeStatus decodeDirectBrTarget(MCInst &Inst, unsigned Imm,
73  uint64_t /*Address*/,
74  const void * /*Decoder*/) {
75  int32_t Offset = SignExtend32<24>(Imm);
78 }
79 
80 // FIXME: These can be generated by TableGen from the existing register
81 // encoding values!
82 
83 template <std::size_t N>
84 static DecodeStatus decodeRegisterClass(MCInst &Inst, uint64_t RegNo,
85  const MCPhysReg (&Regs)[N]) {
86  assert(RegNo < N && "Invalid register number");
87  Inst.addOperand(MCOperand::createReg(Regs[RegNo]));
89 }
90 
91 static DecodeStatus DecodeCRRCRegisterClass(MCInst &Inst, uint64_t RegNo,
92  uint64_t Address,
93  const void *Decoder) {
94  return decodeRegisterClass(Inst, RegNo, CRRegs);
95 }
96 
97 static DecodeStatus DecodeCRBITRCRegisterClass(MCInst &Inst, uint64_t RegNo,
98  uint64_t Address,
99  const void *Decoder) {
100  return decodeRegisterClass(Inst, RegNo, CRBITRegs);
101 }
102 
103 static DecodeStatus DecodeF4RCRegisterClass(MCInst &Inst, uint64_t RegNo,
104  uint64_t Address,
105  const void *Decoder) {
106  return decodeRegisterClass(Inst, RegNo, FRegs);
107 }
108 
109 static DecodeStatus DecodeF8RCRegisterClass(MCInst &Inst, uint64_t RegNo,
110  uint64_t Address,
111  const void *Decoder) {
112  return decodeRegisterClass(Inst, RegNo, FRegs);
113 }
114 
115 static DecodeStatus DecodeVFRCRegisterClass(MCInst &Inst, uint64_t RegNo,
116  uint64_t Address,
117  const void *Decoder) {
118  return decodeRegisterClass(Inst, RegNo, VFRegs);
119 }
120 
121 static DecodeStatus DecodeVRRCRegisterClass(MCInst &Inst, uint64_t RegNo,
122  uint64_t Address,
123  const void *Decoder) {
124  return decodeRegisterClass(Inst, RegNo, VRegs);
125 }
126 
127 static DecodeStatus DecodeVSRCRegisterClass(MCInst &Inst, uint64_t RegNo,
128  uint64_t Address,
129  const void *Decoder) {
130  return decodeRegisterClass(Inst, RegNo, VSRegs);
131 }
132 
133 static DecodeStatus DecodeVSFRCRegisterClass(MCInst &Inst, uint64_t RegNo,
134  uint64_t Address,
135  const void *Decoder) {
136  return decodeRegisterClass(Inst, RegNo, VSFRegs);
137 }
138 
139 static DecodeStatus DecodeVSSRCRegisterClass(MCInst &Inst, uint64_t RegNo,
140  uint64_t Address,
141  const void *Decoder) {
142  return decodeRegisterClass(Inst, RegNo, VSSRegs);
143 }
144 
145 static DecodeStatus DecodeGPRCRegisterClass(MCInst &Inst, uint64_t RegNo,
146  uint64_t Address,
147  const void *Decoder) {
148  return decodeRegisterClass(Inst, RegNo, RRegs);
149 }
150 
151 static DecodeStatus DecodeGPRC_NOR0RegisterClass(MCInst &Inst, uint64_t RegNo,
152  uint64_t Address,
153  const void *Decoder) {
154  return decodeRegisterClass(Inst, RegNo, RRegsNoR0);
155 }
156 
157 static DecodeStatus DecodeG8RCRegisterClass(MCInst &Inst, uint64_t RegNo,
158  uint64_t Address,
159  const void *Decoder) {
160  return decodeRegisterClass(Inst, RegNo, XRegs);
161 }
162 
163 static DecodeStatus DecodeG8pRCRegisterClass(MCInst &Inst, uint64_t RegNo,
164  uint64_t Address,
165  const void *Decoder) {
166  return decodeRegisterClass(Inst, RegNo, XRegs);
167 }
168 
169 static DecodeStatus DecodeG8RC_NOX0RegisterClass(MCInst &Inst, uint64_t RegNo,
170  uint64_t Address,
171  const void *Decoder) {
172  return decodeRegisterClass(Inst, RegNo, XRegsNoX0);
173 }
174 
175 #define DecodePointerLikeRegClass0 DecodeGPRCRegisterClass
176 #define DecodePointerLikeRegClass1 DecodeGPRC_NOR0RegisterClass
177 
178 static DecodeStatus DecodeSPERCRegisterClass(MCInst &Inst, uint64_t RegNo,
179  uint64_t Address,
180  const void *Decoder) {
181  return decodeRegisterClass(Inst, RegNo, SPERegs);
182 }
183 
184 static DecodeStatus DecodeACCRCRegisterClass(MCInst &Inst, uint64_t RegNo,
185  uint64_t Address,
186  const void *Decoder) {
187  return decodeRegisterClass(Inst, RegNo, ACCRegs);
188 }
189 
190 static DecodeStatus DecodeVSRpRCRegisterClass(MCInst &Inst, uint64_t RegNo,
191  uint64_t Address,
192  const void *Decoder) {
193  return decodeRegisterClass(Inst, RegNo, VSRpRegs);
194 }
195 
196 #define DecodeQSRCRegisterClass DecodeQFRCRegisterClass
197 #define DecodeQBRCRegisterClass DecodeQFRCRegisterClass
198 
199 template<unsigned N>
200 static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm,
201  int64_t Address, const void *Decoder) {
202  assert(isUInt<N>(Imm) && "Invalid immediate");
203  Inst.addOperand(MCOperand::createImm(Imm));
205 }
206 
207 template<unsigned N>
208 static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm,
209  int64_t Address, const void *Decoder) {
210  assert(isUInt<N>(Imm) && "Invalid immediate");
211  Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm)));
213 }
214 
215 static DecodeStatus decodeImmZeroOperand(MCInst &Inst, uint64_t Imm,
216  int64_t Address, const void *Decoder) {
217  if (Imm != 0)
218  return MCDisassembler::Fail;
219  Inst.addOperand(MCOperand::createImm(Imm));
221 }
222 
223 static DecodeStatus decodeVSRpEvenOperands(MCInst &Inst, uint64_t RegNo,
224  uint64_t Address,
225  const void *Decoder) {
226  if (RegNo & 1)
227  return MCDisassembler::Fail;
228  Inst.addOperand(MCOperand::createReg(VSRpRegs[RegNo >> 1]));
230 }
231 
232 static DecodeStatus decodeMemRIOperands(MCInst &Inst, uint64_t Imm,
233  int64_t Address, const void *Decoder) {
234  // Decode the memri field (imm, reg), which has the low 16-bits as the
235  // displacement and the next 5 bits as the register #.
236 
237  uint64_t Base = Imm >> 16;
238  uint64_t Disp = Imm & 0xFFFF;
239 
240  assert(Base < 32 && "Invalid base register");
241 
242  switch (Inst.getOpcode()) {
243  default: break;
244  case PPC::LBZU:
245  case PPC::LHAU:
246  case PPC::LHZU:
247  case PPC::LWZU:
248  case PPC::LFSU:
249  case PPC::LFDU:
250  // Add the tied output operand.
251  Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));
252  break;
253  case PPC::STBU:
254  case PPC::STHU:
255  case PPC::STWU:
256  case PPC::STFSU:
257  case PPC::STFDU:
258  Inst.insert(Inst.begin(), MCOperand::createReg(RRegsNoR0[Base]));
259  break;
260  }
261 
262  Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Disp)));
263  Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));
265 }
266 
267 static DecodeStatus decodeMemRIXOperands(MCInst &Inst, uint64_t Imm,
268  int64_t Address, const void *Decoder) {
269  // Decode the memrix field (imm, reg), which has the low 14-bits as the
270  // displacement and the next 5 bits as the register #.
271 
272  uint64_t Base = Imm >> 14;
273  uint64_t Disp = Imm & 0x3FFF;
274 
275  assert(Base < 32 && "Invalid base register");
276 
277  if (Inst.getOpcode() == PPC::LDU)
278  // Add the tied output operand.
279  Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));
280  else if (Inst.getOpcode() == PPC::STDU)
281  Inst.insert(Inst.begin(), MCOperand::createReg(RRegsNoR0[Base]));
282 
283  Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Disp << 2)));
284  Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));
286 }
287 
288 static DecodeStatus decodeMemRIHashOperands(MCInst &Inst, uint64_t Imm,
289  int64_t Address,
290  const void *Decoder) {
291  // Decode the memrix field for a hash store or hash check operation.
292  // The field is composed of a register and an immediate value that is 6 bits
293  // and covers the range -8 to -512. The immediate is always negative and 2s
294  // complement which is why we sign extend a 7 bit value.
295  const uint64_t Base = Imm >> 6;
296  const int64_t Disp = SignExtend64<7>((Imm & 0x3F) + 64) * 8;
297 
298  assert(Base < 32 && "Invalid base register");
299 
300  Inst.addOperand(MCOperand::createImm(Disp));
301  Inst.addOperand(MCOperand::createReg(RRegs[Base]));
303 }
304 
305 static DecodeStatus decodeMemRIX16Operands(MCInst &Inst, uint64_t Imm,
306  int64_t Address, const void *Decoder) {
307  // Decode the memrix16 field (imm, reg), which has the low 12-bits as the
308  // displacement with 16-byte aligned, and the next 5 bits as the register #.
309 
310  uint64_t Base = Imm >> 12;
311  uint64_t Disp = Imm & 0xFFF;
312 
313  assert(Base < 32 && "Invalid base register");
314 
315  Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Disp << 4)));
316  Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));
318 }
319 
320 static DecodeStatus decodeMemRI34PCRelOperands(MCInst &Inst, uint64_t Imm,
321  int64_t Address,
322  const void *Decoder) {
323  // Decode the memri34_pcrel field (imm, reg), which has the low 34-bits as the
324  // displacement, and the next 5 bits as an immediate 0.
325  uint64_t Base = Imm >> 34;
326  uint64_t Disp = Imm & 0x3FFFFFFFFUL;
327 
328  assert(Base < 32 && "Invalid base register");
329 
330  Inst.addOperand(MCOperand::createImm(SignExtend64<34>(Disp)));
331  return decodeImmZeroOperand(Inst, Base, Address, Decoder);
332 }
333 
334 static DecodeStatus decodeMemRI34Operands(MCInst &Inst, uint64_t Imm,
335  int64_t Address,
336  const void *Decoder) {
337  // Decode the memri34 field (imm, reg), which has the low 34-bits as the
338  // displacement, and the next 5 bits as the register #.
339  uint64_t Base = Imm >> 34;
340  uint64_t Disp = Imm & 0x3FFFFFFFFUL;
341 
342  assert(Base < 32 && "Invalid base register");
343 
344  Inst.addOperand(MCOperand::createImm(SignExtend64<34>(Disp)));
345  Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));
347 }
348 
349 static DecodeStatus decodeSPE8Operands(MCInst &Inst, uint64_t Imm,
350  int64_t Address, const void *Decoder) {
351  // Decode the spe8disp field (imm, reg), which has the low 5-bits as the
352  // displacement with 8-byte aligned, and the next 5 bits as the register #.
353 
354  uint64_t Base = Imm >> 5;
355  uint64_t Disp = Imm & 0x1F;
356 
357  assert(Base < 32 && "Invalid base register");
358 
359  Inst.addOperand(MCOperand::createImm(Disp << 3));
360  Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));
362 }
363 
364 static DecodeStatus decodeSPE4Operands(MCInst &Inst, uint64_t Imm,
365  int64_t Address, const void *Decoder) {
366  // Decode the spe4disp field (imm, reg), which has the low 5-bits as the
367  // displacement with 4-byte aligned, and the next 5 bits as the register #.
368 
369  uint64_t Base = Imm >> 5;
370  uint64_t Disp = Imm & 0x1F;
371 
372  assert(Base < 32 && "Invalid base register");
373 
374  Inst.addOperand(MCOperand::createImm(Disp << 2));
375  Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));
377 }
378 
379 static DecodeStatus decodeSPE2Operands(MCInst &Inst, uint64_t Imm,
380  int64_t Address, const void *Decoder) {
381  // Decode the spe2disp field (imm, reg), which has the low 5-bits as the
382  // displacement with 2-byte aligned, and the next 5 bits as the register #.
383 
384  uint64_t Base = Imm >> 5;
385  uint64_t Disp = Imm & 0x1F;
386 
387  assert(Base < 32 && "Invalid base register");
388 
389  Inst.addOperand(MCOperand::createImm(Disp << 1));
390  Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));
392 }
393 
394 static DecodeStatus decodeCRBitMOperand(MCInst &Inst, uint64_t Imm,
395  int64_t Address, const void *Decoder) {
396  // The cr bit encoding is 0x80 >> cr_reg_num.
397 
398  unsigned Zeros = countTrailingZeros(Imm);
399  assert(Zeros < 8 && "Invalid CR bit value");
400 
401  Inst.addOperand(MCOperand::createReg(CRRegs[7 - Zeros]));
403 }
404 
405 #include "PPCGenDisassemblerTables.inc"
406 
407 DecodeStatus PPCDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
408  ArrayRef<uint8_t> Bytes,
409  uint64_t Address,
410  raw_ostream &CS) const {
411  auto *ReadFunc = IsLittleEndian ? support::endian::read32le
413 
414  // If this is an 8-byte prefixed instruction, handle it here.
415  // Note: prefixed instructions aren't technically 8-byte entities - the prefix
416  // appears in memory at an address 4 bytes prior to that of the base
417  // instruction regardless of endianness. So we read the two pieces and
418  // rebuild the 8-byte instruction.
419  // TODO: In this function we call decodeInstruction several times with
420  // different decoder tables. It may be possible to only call once by
421  // looking at the top 6 bits of the instruction.
422  if (STI.getFeatureBits()[PPC::FeaturePrefixInstrs] && Bytes.size() >= 8) {
423  uint32_t Prefix = ReadFunc(Bytes.data());
424  uint32_t BaseInst = ReadFunc(Bytes.data() + 4);
425  uint64_t Inst = BaseInst | (uint64_t)Prefix << 32;
426  DecodeStatus result = decodeInstruction(DecoderTable64, MI, Inst, Address,
427  this, STI);
428  if (result != MCDisassembler::Fail) {
429  Size = 8;
430  return result;
431  }
432  }
433 
434  // Get the four bytes of the instruction.
435  Size = 4;
436  if (Bytes.size() < 4) {
437  Size = 0;
438  return MCDisassembler::Fail;
439  }
440 
441  // Read the instruction in the proper endianness.
442  uint64_t Inst = ReadFunc(Bytes.data());
443 
444  if (STI.getFeatureBits()[PPC::FeatureSPE]) {
446  decodeInstruction(DecoderTableSPE32, MI, Inst, Address, this, STI);
448  return result;
449  }
450 
451  return decodeInstruction(DecoderTable32, MI, Inst, Address, this, STI);
452 }
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
MCFixedLenDisassembler.h
DecodeVSSRCRegisterClass
static DecodeStatus DecodeVSSRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
Definition: PPCDisassembler.cpp:139
decodeSPE4Operands
static DecodeStatus decodeSPE4Operands(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)
Definition: PPCDisassembler.cpp:364
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:102
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
decodeMemRIX16Operands
static DecodeStatus decodeMemRIX16Operands(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)
Definition: PPCDisassembler.cpp:305
MCDisassembler.h
DecodeG8pRCRegisterClass
static DecodeStatus DecodeG8pRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
Definition: PPCDisassembler.cpp:163
llvm::cl::Prefix
@ Prefix
Definition: CommandLine.h:164
decodeMemRIXOperands
static DecodeStatus decodeMemRIXOperands(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)
Definition: PPCDisassembler.cpp:267
llvm::MCOperand::createImm
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:141
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:72
llvm::MCInst::insert
iterator insert(iterator I, const MCOperand &Op)
Definition: MCInst.h:224
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:137
DecodeCRBITRCRegisterClass
static DecodeStatus DecodeCRBITRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
Definition: PPCDisassembler.cpp:97
DecodeVSFRCRegisterClass
static DecodeStatus DecodeVSFRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
Definition: PPCDisassembler.cpp:133
DecodeVRRCRegisterClass
static DecodeStatus DecodeVRRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
Definition: PPCDisassembler.cpp:121
decodeMemRI34PCRelOperands
static DecodeStatus decodeMemRI34PCRelOperands(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)
Definition: PPCDisassembler.cpp:320
llvm::TargetRegistry::RegisterMCDisassembler
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.
Definition: TargetRegistry.h:916
Offset
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Definition: ELFObjHandler.cpp:81
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static DecodeStatus decodeSPE2Operands(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)
Definition: PPCDisassembler.cpp:379
decodeMemRI34Operands
static DecodeStatus decodeMemRI34Operands(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)
Definition: PPCDisassembler.cpp:334
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uint32_t read32be(const void *P)
Definition: Endian.h:384
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
PPCMCTargetDesc.h
LLVMInitializePowerPCDisassembler
LLVM_EXTERNAL_VISIBILITY void LLVMInitializePowerPCDisassembler()
Definition: PPCDisassembler.cpp:53
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const T * data() const
Definition: ArrayRef.h:162
decodeImmZeroOperand
static DecodeStatus decodeImmZeroOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)
Definition: PPCDisassembler.cpp:215
DecodeF4RCRegisterClass
static DecodeStatus DecodeF4RCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
Definition: PPCDisassembler.cpp:103
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Definition: README_P9.txt:256
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Target & getThePPC64LETarget()
Definition: PowerPCTargetInfo.cpp:25
llvm::MCDisassembler::Success
@ Success
Definition: MCDisassembler.h:103
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MCSubtargetInfo.h
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Definition: raw_ostream.h:53
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static MCDisassembler * createPPCLEDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
Definition: PPCDisassembler.cpp:47
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static DecodeStatus DecodeVFRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
Definition: PPCDisassembler.cpp:115
llvm::MCDisassembler::DecodeStatus
DecodeStatus
Ternary decode status.
Definition: MCDisassembler.h:100
llvm::MCInst::addOperand
void addOperand(const MCOperand Op)
Definition: MCInst.h:210
decodeVSRpEvenOperands
static DecodeStatus decodeVSRpEvenOperands(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
Definition: PPCDisassembler.cpp:223
DecodeVSRpRCRegisterClass
static DecodeStatus DecodeVSRpRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
Definition: PPCDisassembler.cpp:190
DecodeVSRCRegisterClass
static DecodeStatus DecodeVSRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
Definition: PPCDisassembler.cpp:127
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MCDisassembler::DecodeStatus DecodeStatus
Definition: PPCDisassembler.cpp:24
DecodeSPERCRegisterClass
static DecodeStatus DecodeSPERCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
Definition: PPCDisassembler.cpp:178
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static DecodeStatus decodeMemRIOperands(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)
Definition: PPCDisassembler.cpp:232
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#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:132
llvm::MCDisassembler
Superclass for all disassemblers.
Definition: MCDisassembler.h:76
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Definition: MCInst.h:219
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uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Definition: MCRegister.h:20
PowerPCTargetInfo.h
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static DecodeStatus DecodeG8RC_NOX0RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
Definition: PPCDisassembler.cpp:169
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static DecodeStatus decodeMemRIHashOperands(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)
Definition: PPCDisassembler.cpp:288
llvm::HighlightColor::Address
@ Address
DecodeGPRC_NOR0RegisterClass
static DecodeStatus DecodeGPRC_NOR0RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
Definition: PPCDisassembler.cpp:151
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static DecodeStatus decodeCondBrTarget(MCInst &Inst, unsigned Imm, uint64_t, const void *)
Definition: PPCDisassembler.cpp:65
assert
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DEFINE_PPC_REGCLASSES
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Definition: PPCDisassembler.cpp:20
llvm::ArrayRef< uint8_t >
DecodeG8RCRegisterClass
static DecodeStatus DecodeG8RCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
Definition: PPCDisassembler.cpp:157
llvm::countTrailingZeros
unsigned countTrailingZeros(T Val, ZeroBehavior ZB=ZB_Width)
Count number of 0's from the least significant bit to the most stopping at the first 1.
Definition: MathExtras.h:156
llvm::MCOperand::createReg
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:134
uint32_t
llvm::MCDisassembler::Fail
@ Fail
Definition: MCDisassembler.h:101
decodeSImmOperand
static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)
Definition: PPCDisassembler.cpp:208
decodeCRBitMOperand
static DecodeStatus decodeCRBitMOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)
Definition: PPCDisassembler.cpp:394
createPPCDisassembler
static MCDisassembler * createPPCDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
Definition: PPCDisassembler.cpp:41
llvm::getThePPC64Target
Target & getThePPC64Target()
Definition: PowerPCTargetInfo.cpp:21
decodeUImmOperand
static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)
Definition: PPCDisassembler.cpp:200
DecodeACCRCRegisterClass
static DecodeStatus DecodeACCRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
Definition: PPCDisassembler.cpp:184
decodeDirectBrTarget
static DecodeStatus decodeDirectBrTarget(MCInst &Inst, unsigned Imm, uint64_t, const void *)
Definition: PPCDisassembler.cpp:72
llvm::MCInst::getOpcode
unsigned getOpcode() const
Definition: MCInst.h:198
llvm::getThePPC32LETarget
Target & getThePPC32LETarget()
Definition: PowerPCTargetInfo.cpp:17
decodeRegisterClass
static DecodeStatus decodeRegisterClass(MCInst &Inst, uint64_t RegNo, const MCPhysReg(&Regs)[N])
Definition: PPCDisassembler.cpp:84
DecodeCRRCRegisterClass
static DecodeStatus DecodeCRRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
Definition: PPCDisassembler.cpp:91
llvm::support::endian::read32le
uint32_t read32le(const void *P)
Definition: Endian.h:381
N
#define N
DecodeF8RCRegisterClass
static DecodeStatus DecodeF8RCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
Definition: PPCDisassembler.cpp:109
llvm::ArrayRef::size
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:165
DecodeGPRCRegisterClass
static DecodeStatus DecodeGPRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
Definition: PPCDisassembler.cpp:145
Endian.h
decodeSPE8Operands
static DecodeStatus decodeSPE8Operands(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)
Definition: PPCDisassembler.cpp:349
TargetRegistry.h
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:75
llvm::sampleprof::Base
@ Base
Definition: Discriminator.h:58
llvm::getThePPC32Target
Target & getThePPC32Target()
Definition: PowerPCTargetInfo.cpp:13