LLVM 23.0.0git
SISpillUtils.cpp
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1//===- SISpillUtils.cpp - SI spill helper functions -----------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#include "SISpillUtils.h"
10#include "llvm/ADT/BitVector.h"
13
14using namespace llvm;
15
18 const BitVector &SpillFIs) {
19 // FIXME: The dead frame indices are replaced with a null register from the
20 // debug value instructions. We should instead update it with the correct
21 // register value. But not sure the register value alone is adequate to lower
22 // the DIExpression. It should be worked out later.
23 for (MachineInstr &MI : MBB) {
24 if (!MI.isDebugValue())
25 continue;
26
27 for (MachineOperand &Op : MI.debug_operands()) {
28 if (Op.isFI() && !MFI.isFixedObjectIndex(Op.getIndex()) &&
29 SpillFIs[Op.getIndex()]) {
30 Op.ChangeToRegister(Register(), /*isDef=*/false);
31 }
32 }
33 }
34}
MachineBasicBlock & MBB
This file implements the BitVector class.
IRTranslator LLVM IR MI
Promote Memory to Register
Definition Mem2Reg.cpp:110
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
bool isFixedObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a fixed stack object.
Representation of each machine instruction.
MachineOperand class - Representation of each machine instruction operand.
This is an optimization pass for GlobalISel generic memory operations.
void clearDebugInfoForSpillFIs(MachineFrameInfo &MFI, MachineBasicBlock &MBB, const BitVector &SpillFIs)
Replace frame index operands with null registers in debug value instructions for the specified spill ...
DWARFExpression::Operation Op