LLVM 17.0.0git
WebAssemblyMCTargetDesc.h
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1//==- WebAssemblyMCTargetDesc.h - WebAssembly Target Descriptions -*- C++ -*-=//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8///
9/// \file
10/// This file provides WebAssembly-specific target descriptions.
11///
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_LIB_TARGET_WEBASSEMBLY_MCTARGETDESC_WEBASSEMBLYMCTARGETDESC_H
15#define LLVM_LIB_TARGET_WEBASSEMBLY_MCTARGETDESC_WEBASSEMBLYMCTARGETDESC_H
16
17#include "../WebAssemblySubtarget.h"
19#include "llvm/MC/MCInstrDesc.h"
21#include <memory>
22
23namespace llvm {
24
25class MCAsmBackend;
26class MCCodeEmitter;
27class MCInstrInfo;
28class MCObjectTargetWriter;
29class Triple;
30
31MCCodeEmitter *createWebAssemblyMCCodeEmitter(const MCInstrInfo &MCII);
32
33MCAsmBackend *createWebAssemblyAsmBackend(const Triple &TT);
34
35std::unique_ptr<MCObjectTargetWriter>
36createWebAssemblyWasmObjectWriter(bool Is64Bit, bool IsEmscripten);
37
38namespace WebAssembly {
39
40// Exception handling / setjmp-longjmp handling command-line options
41extern cl::opt<bool> WasmEnableEmEH; // asm.js-style EH
42extern cl::opt<bool> WasmEnableEmSjLj; // asm.js-style SjLJ
43extern cl::opt<bool> WasmEnableEH; // EH using Wasm EH instructions
44extern cl::opt<bool> WasmEnableSjLj; // SjLj using Wasm EH instructions
45
47 /// Basic block label in a branch construct.
49 /// Local index.
51 /// Global index.
53 /// 32-bit integer immediates.
55 /// 64-bit integer immediates.
57 /// 32-bit floating-point immediates.
59 /// 64-bit floating-point immediates.
61 /// 8-bit vector lane immediate
63 /// 16-bit vector lane immediate
65 /// 32-bit vector lane immediate
67 /// 64-bit vector lane immediate
69 /// 32-bit unsigned function indices.
71 /// 32-bit unsigned memory offsets.
73 /// 64-bit unsigned memory offsets.
75 /// p2align immediate for load and store address alignment.
77 /// signature immediate for block/loop.
79 /// type signature immediate for call_indirect.
81 /// Tag index.
83 /// A list of branch targets for br_list.
85 /// 32-bit unsigned table number.
87};
88} // end namespace WebAssembly
89
90namespace WebAssemblyII {
91
92/// Target Operand Flag enum.
93enum TOF {
95
96 // On a symbol operand this indicates that the immediate is a wasm global
97 // index. The value of the wasm global will be set to the symbol address at
98 // runtime. This adds a level of indirection similar to the GOT on native
99 // platforms.
101
102 // Same as MO_GOT but the address stored in the global is a TLS address.
104
105 // On a symbol operand this indicates that the immediate is the symbol
106 // address relative the __memory_base wasm global.
107 // Only applicable to data symbols.
109
110 // On a symbol operand this indicates that the immediate is the symbol
111 // address relative the __tls_base wasm global.
112 // Only applicable to data symbols.
114
115 // On a symbol operand this indicates that the immediate is the symbol
116 // address relative the __table_base wasm global.
117 // Only applicable to function symbols.
119};
120
121} // end namespace WebAssemblyII
122
123} // end namespace llvm
124
125// Defines symbolic names for WebAssembly registers. This defines a mapping from
126// register name to register number.
127//
128#define GET_REGINFO_ENUM
129#include "WebAssemblyGenRegisterInfo.inc"
130
131// Defines symbolic names for the WebAssembly instructions.
132//
133#define GET_INSTRINFO_ENUM
134#define GET_INSTRINFO_MC_HELPER_DECLS
135#include "WebAssemblyGenInstrInfo.inc"
136
137namespace llvm {
138namespace WebAssembly {
139
140/// Instruction opcodes emitted via means other than CodeGen.
141static const unsigned Nop = 0x01;
142static const unsigned End = 0x0b;
143
144/// Return the default p2align value for a load or store with the given opcode.
145inline unsigned GetDefaultP2AlignAny(unsigned Opc) {
146 switch (Opc) {
147#define WASM_LOAD_STORE(NAME) \
148 case WebAssembly::NAME##_A32: \
149 case WebAssembly::NAME##_A64: \
150 case WebAssembly::NAME##_A32_S: \
151 case WebAssembly::NAME##_A64_S:
152 WASM_LOAD_STORE(LOAD8_S_I32)
153 WASM_LOAD_STORE(LOAD8_U_I32)
154 WASM_LOAD_STORE(LOAD8_S_I64)
155 WASM_LOAD_STORE(LOAD8_U_I64)
156 WASM_LOAD_STORE(ATOMIC_LOAD8_U_I32)
157 WASM_LOAD_STORE(ATOMIC_LOAD8_U_I64)
158 WASM_LOAD_STORE(STORE8_I32)
159 WASM_LOAD_STORE(STORE8_I64)
160 WASM_LOAD_STORE(ATOMIC_STORE8_I32)
161 WASM_LOAD_STORE(ATOMIC_STORE8_I64)
162 WASM_LOAD_STORE(ATOMIC_RMW8_U_ADD_I32)
163 WASM_LOAD_STORE(ATOMIC_RMW8_U_ADD_I64)
164 WASM_LOAD_STORE(ATOMIC_RMW8_U_SUB_I32)
165 WASM_LOAD_STORE(ATOMIC_RMW8_U_SUB_I64)
166 WASM_LOAD_STORE(ATOMIC_RMW8_U_AND_I32)
167 WASM_LOAD_STORE(ATOMIC_RMW8_U_AND_I64)
168 WASM_LOAD_STORE(ATOMIC_RMW8_U_OR_I32)
169 WASM_LOAD_STORE(ATOMIC_RMW8_U_OR_I64)
170 WASM_LOAD_STORE(ATOMIC_RMW8_U_XOR_I32)
171 WASM_LOAD_STORE(ATOMIC_RMW8_U_XOR_I64)
172 WASM_LOAD_STORE(ATOMIC_RMW8_U_XCHG_I32)
173 WASM_LOAD_STORE(ATOMIC_RMW8_U_XCHG_I64)
174 WASM_LOAD_STORE(ATOMIC_RMW8_U_CMPXCHG_I32)
175 WASM_LOAD_STORE(ATOMIC_RMW8_U_CMPXCHG_I64)
176 WASM_LOAD_STORE(LOAD8_SPLAT)
177 WASM_LOAD_STORE(LOAD_LANE_I8x16)
178 WASM_LOAD_STORE(STORE_LANE_I8x16)
179 return 0;
180 WASM_LOAD_STORE(LOAD16_S_I32)
181 WASM_LOAD_STORE(LOAD16_U_I32)
182 WASM_LOAD_STORE(LOAD16_S_I64)
183 WASM_LOAD_STORE(LOAD16_U_I64)
184 WASM_LOAD_STORE(ATOMIC_LOAD16_U_I32)
185 WASM_LOAD_STORE(ATOMIC_LOAD16_U_I64)
186 WASM_LOAD_STORE(STORE16_I32)
187 WASM_LOAD_STORE(STORE16_I64)
188 WASM_LOAD_STORE(ATOMIC_STORE16_I32)
189 WASM_LOAD_STORE(ATOMIC_STORE16_I64)
190 WASM_LOAD_STORE(ATOMIC_RMW16_U_ADD_I32)
191 WASM_LOAD_STORE(ATOMIC_RMW16_U_ADD_I64)
192 WASM_LOAD_STORE(ATOMIC_RMW16_U_SUB_I32)
193 WASM_LOAD_STORE(ATOMIC_RMW16_U_SUB_I64)
194 WASM_LOAD_STORE(ATOMIC_RMW16_U_AND_I32)
195 WASM_LOAD_STORE(ATOMIC_RMW16_U_AND_I64)
196 WASM_LOAD_STORE(ATOMIC_RMW16_U_OR_I32)
197 WASM_LOAD_STORE(ATOMIC_RMW16_U_OR_I64)
198 WASM_LOAD_STORE(ATOMIC_RMW16_U_XOR_I32)
199 WASM_LOAD_STORE(ATOMIC_RMW16_U_XOR_I64)
200 WASM_LOAD_STORE(ATOMIC_RMW16_U_XCHG_I32)
201 WASM_LOAD_STORE(ATOMIC_RMW16_U_XCHG_I64)
202 WASM_LOAD_STORE(ATOMIC_RMW16_U_CMPXCHG_I32)
203 WASM_LOAD_STORE(ATOMIC_RMW16_U_CMPXCHG_I64)
204 WASM_LOAD_STORE(LOAD16_SPLAT)
205 WASM_LOAD_STORE(LOAD_LANE_I16x8)
206 WASM_LOAD_STORE(STORE_LANE_I16x8)
207 return 1;
208 WASM_LOAD_STORE(LOAD_I32)
209 WASM_LOAD_STORE(LOAD_F32)
210 WASM_LOAD_STORE(STORE_I32)
211 WASM_LOAD_STORE(STORE_F32)
212 WASM_LOAD_STORE(LOAD32_S_I64)
213 WASM_LOAD_STORE(LOAD32_U_I64)
214 WASM_LOAD_STORE(STORE32_I64)
215 WASM_LOAD_STORE(ATOMIC_LOAD_I32)
216 WASM_LOAD_STORE(ATOMIC_LOAD32_U_I64)
217 WASM_LOAD_STORE(ATOMIC_STORE_I32)
218 WASM_LOAD_STORE(ATOMIC_STORE32_I64)
219 WASM_LOAD_STORE(ATOMIC_RMW_ADD_I32)
220 WASM_LOAD_STORE(ATOMIC_RMW32_U_ADD_I64)
221 WASM_LOAD_STORE(ATOMIC_RMW_SUB_I32)
222 WASM_LOAD_STORE(ATOMIC_RMW32_U_SUB_I64)
223 WASM_LOAD_STORE(ATOMIC_RMW_AND_I32)
224 WASM_LOAD_STORE(ATOMIC_RMW32_U_AND_I64)
225 WASM_LOAD_STORE(ATOMIC_RMW_OR_I32)
226 WASM_LOAD_STORE(ATOMIC_RMW32_U_OR_I64)
227 WASM_LOAD_STORE(ATOMIC_RMW_XOR_I32)
228 WASM_LOAD_STORE(ATOMIC_RMW32_U_XOR_I64)
229 WASM_LOAD_STORE(ATOMIC_RMW_XCHG_I32)
230 WASM_LOAD_STORE(ATOMIC_RMW32_U_XCHG_I64)
231 WASM_LOAD_STORE(ATOMIC_RMW_CMPXCHG_I32)
232 WASM_LOAD_STORE(ATOMIC_RMW32_U_CMPXCHG_I64)
233 WASM_LOAD_STORE(MEMORY_ATOMIC_NOTIFY)
234 WASM_LOAD_STORE(MEMORY_ATOMIC_WAIT32)
235 WASM_LOAD_STORE(LOAD32_SPLAT)
236 WASM_LOAD_STORE(LOAD_ZERO_I32x4)
237 WASM_LOAD_STORE(LOAD_LANE_I32x4)
238 WASM_LOAD_STORE(STORE_LANE_I32x4)
239 return 2;
240 WASM_LOAD_STORE(LOAD_I64)
241 WASM_LOAD_STORE(LOAD_F64)
242 WASM_LOAD_STORE(STORE_I64)
243 WASM_LOAD_STORE(STORE_F64)
244 WASM_LOAD_STORE(ATOMIC_LOAD_I64)
245 WASM_LOAD_STORE(ATOMIC_STORE_I64)
246 WASM_LOAD_STORE(ATOMIC_RMW_ADD_I64)
247 WASM_LOAD_STORE(ATOMIC_RMW_SUB_I64)
248 WASM_LOAD_STORE(ATOMIC_RMW_AND_I64)
249 WASM_LOAD_STORE(ATOMIC_RMW_OR_I64)
250 WASM_LOAD_STORE(ATOMIC_RMW_XOR_I64)
251 WASM_LOAD_STORE(ATOMIC_RMW_XCHG_I64)
252 WASM_LOAD_STORE(ATOMIC_RMW_CMPXCHG_I64)
253 WASM_LOAD_STORE(MEMORY_ATOMIC_WAIT64)
254 WASM_LOAD_STORE(LOAD64_SPLAT)
255 WASM_LOAD_STORE(LOAD_EXTEND_S_I16x8)
256 WASM_LOAD_STORE(LOAD_EXTEND_U_I16x8)
257 WASM_LOAD_STORE(LOAD_EXTEND_S_I32x4)
258 WASM_LOAD_STORE(LOAD_EXTEND_U_I32x4)
259 WASM_LOAD_STORE(LOAD_EXTEND_S_I64x2)
260 WASM_LOAD_STORE(LOAD_EXTEND_U_I64x2)
261 WASM_LOAD_STORE(LOAD_ZERO_I64x2)
262 WASM_LOAD_STORE(LOAD_LANE_I64x2)
263 WASM_LOAD_STORE(STORE_LANE_I64x2)
264 return 3;
265 WASM_LOAD_STORE(LOAD_V128)
266 WASM_LOAD_STORE(STORE_V128)
267 return 4;
268 default:
269 return -1;
270 }
271#undef WASM_LOAD_STORE
272}
273
274inline unsigned GetDefaultP2Align(unsigned Opc) {
275 auto Align = GetDefaultP2AlignAny(Opc);
276 if (Align == -1U) {
277 llvm_unreachable("Only loads and stores have p2align values");
278 }
279 return Align;
280}
281
282inline bool isConst(unsigned Opc) {
283 switch (Opc) {
284 case WebAssembly::CONST_I32:
285 case WebAssembly::CONST_I32_S:
286 case WebAssembly::CONST_I64:
287 case WebAssembly::CONST_I64_S:
288 case WebAssembly::CONST_F32:
289 case WebAssembly::CONST_F32_S:
290 case WebAssembly::CONST_F64:
291 case WebAssembly::CONST_F64_S:
292 case WebAssembly::CONST_V128_I8x16:
293 case WebAssembly::CONST_V128_I8x16_S:
294 case WebAssembly::CONST_V128_I16x8:
295 case WebAssembly::CONST_V128_I16x8_S:
296 case WebAssembly::CONST_V128_I32x4:
297 case WebAssembly::CONST_V128_I32x4_S:
298 case WebAssembly::CONST_V128_I64x2:
299 case WebAssembly::CONST_V128_I64x2_S:
300 case WebAssembly::CONST_V128_F32x4:
301 case WebAssembly::CONST_V128_F32x4_S:
302 case WebAssembly::CONST_V128_F64x2:
303 case WebAssembly::CONST_V128_F64x2_S:
304 return true;
305 default:
306 return false;
307 }
308}
309
310inline bool isScalarConst(unsigned Opc) {
311 switch (Opc) {
312 case WebAssembly::CONST_I32:
313 case WebAssembly::CONST_I32_S:
314 case WebAssembly::CONST_I64:
315 case WebAssembly::CONST_I64_S:
316 case WebAssembly::CONST_F32:
317 case WebAssembly::CONST_F32_S:
318 case WebAssembly::CONST_F64:
319 case WebAssembly::CONST_F64_S:
320 return true;
321 default:
322 return false;
323 }
324}
325
326inline bool isArgument(unsigned Opc) {
327 switch (Opc) {
328 case WebAssembly::ARGUMENT_i32:
329 case WebAssembly::ARGUMENT_i32_S:
330 case WebAssembly::ARGUMENT_i64:
331 case WebAssembly::ARGUMENT_i64_S:
332 case WebAssembly::ARGUMENT_f32:
333 case WebAssembly::ARGUMENT_f32_S:
334 case WebAssembly::ARGUMENT_f64:
335 case WebAssembly::ARGUMENT_f64_S:
336 case WebAssembly::ARGUMENT_v16i8:
337 case WebAssembly::ARGUMENT_v16i8_S:
338 case WebAssembly::ARGUMENT_v8i16:
339 case WebAssembly::ARGUMENT_v8i16_S:
340 case WebAssembly::ARGUMENT_v4i32:
341 case WebAssembly::ARGUMENT_v4i32_S:
342 case WebAssembly::ARGUMENT_v2i64:
343 case WebAssembly::ARGUMENT_v2i64_S:
344 case WebAssembly::ARGUMENT_v4f32:
345 case WebAssembly::ARGUMENT_v4f32_S:
346 case WebAssembly::ARGUMENT_v2f64:
347 case WebAssembly::ARGUMENT_v2f64_S:
348 case WebAssembly::ARGUMENT_funcref:
349 case WebAssembly::ARGUMENT_funcref_S:
350 case WebAssembly::ARGUMENT_externref:
351 case WebAssembly::ARGUMENT_externref_S:
352 return true;
353 default:
354 return false;
355 }
356}
357
358inline bool isCopy(unsigned Opc) {
359 switch (Opc) {
360 case WebAssembly::COPY_I32:
361 case WebAssembly::COPY_I32_S:
362 case WebAssembly::COPY_I64:
363 case WebAssembly::COPY_I64_S:
364 case WebAssembly::COPY_F32:
365 case WebAssembly::COPY_F32_S:
366 case WebAssembly::COPY_F64:
367 case WebAssembly::COPY_F64_S:
368 case WebAssembly::COPY_V128:
369 case WebAssembly::COPY_V128_S:
370 case WebAssembly::COPY_FUNCREF:
371 case WebAssembly::COPY_FUNCREF_S:
372 case WebAssembly::COPY_EXTERNREF:
373 case WebAssembly::COPY_EXTERNREF_S:
374 return true;
375 default:
376 return false;
377 }
378}
379
380inline bool isTee(unsigned Opc) {
381 switch (Opc) {
382 case WebAssembly::TEE_I32:
383 case WebAssembly::TEE_I32_S:
384 case WebAssembly::TEE_I64:
385 case WebAssembly::TEE_I64_S:
386 case WebAssembly::TEE_F32:
387 case WebAssembly::TEE_F32_S:
388 case WebAssembly::TEE_F64:
389 case WebAssembly::TEE_F64_S:
390 case WebAssembly::TEE_V128:
391 case WebAssembly::TEE_V128_S:
392 case WebAssembly::TEE_FUNCREF:
393 case WebAssembly::TEE_FUNCREF_S:
394 case WebAssembly::TEE_EXTERNREF:
395 case WebAssembly::TEE_EXTERNREF_S:
396 return true;
397 default:
398 return false;
399 }
400}
401
402inline bool isCallDirect(unsigned Opc) {
403 switch (Opc) {
404 case WebAssembly::CALL:
405 case WebAssembly::CALL_S:
406 case WebAssembly::RET_CALL:
407 case WebAssembly::RET_CALL_S:
408 return true;
409 default:
410 return false;
411 }
412}
413
414inline bool isCallIndirect(unsigned Opc) {
415 switch (Opc) {
416 case WebAssembly::CALL_INDIRECT:
417 case WebAssembly::CALL_INDIRECT_S:
418 case WebAssembly::RET_CALL_INDIRECT:
419 case WebAssembly::RET_CALL_INDIRECT_S:
420 return true;
421 default:
422 return false;
423 }
424}
425
426inline bool isBrTable(const MachineInstr &MI) {
427 switch (MI.getOpcode()) {
428 case WebAssembly::BR_TABLE_I32:
429 case WebAssembly::BR_TABLE_I32_S:
430 case WebAssembly::BR_TABLE_I64:
431 case WebAssembly::BR_TABLE_I64_S:
432 return true;
433 default:
434 return false;
435 }
436}
437
438inline bool isMarker(unsigned Opc) {
439 switch (Opc) {
440 case WebAssembly::BLOCK:
441 case WebAssembly::BLOCK_S:
442 case WebAssembly::END_BLOCK:
443 case WebAssembly::END_BLOCK_S:
444 case WebAssembly::LOOP:
445 case WebAssembly::LOOP_S:
446 case WebAssembly::END_LOOP:
447 case WebAssembly::END_LOOP_S:
448 case WebAssembly::TRY:
449 case WebAssembly::TRY_S:
450 case WebAssembly::END_TRY:
451 case WebAssembly::END_TRY_S:
452 return true;
453 default:
454 return false;
455 }
456}
457
458inline bool isCatch(unsigned Opc) {
459 switch (Opc) {
460 case WebAssembly::CATCH:
461 case WebAssembly::CATCH_S:
462 case WebAssembly::CATCH_ALL:
463 case WebAssembly::CATCH_ALL_S:
464 return true;
465 default:
466 return false;
467 }
468}
469
470inline bool isLocalGet(unsigned Opc) {
471 switch (Opc) {
472 case WebAssembly::LOCAL_GET_I32:
473 case WebAssembly::LOCAL_GET_I32_S:
474 case WebAssembly::LOCAL_GET_I64:
475 case WebAssembly::LOCAL_GET_I64_S:
476 case WebAssembly::LOCAL_GET_F32:
477 case WebAssembly::LOCAL_GET_F32_S:
478 case WebAssembly::LOCAL_GET_F64:
479 case WebAssembly::LOCAL_GET_F64_S:
480 case WebAssembly::LOCAL_GET_V128:
481 case WebAssembly::LOCAL_GET_V128_S:
482 case WebAssembly::LOCAL_GET_FUNCREF:
483 case WebAssembly::LOCAL_GET_FUNCREF_S:
484 case WebAssembly::LOCAL_GET_EXTERNREF:
485 case WebAssembly::LOCAL_GET_EXTERNREF_S:
486 return true;
487 default:
488 return false;
489 }
490}
491
492inline bool isLocalSet(unsigned Opc) {
493 switch (Opc) {
494 case WebAssembly::LOCAL_SET_I32:
495 case WebAssembly::LOCAL_SET_I32_S:
496 case WebAssembly::LOCAL_SET_I64:
497 case WebAssembly::LOCAL_SET_I64_S:
498 case WebAssembly::LOCAL_SET_F32:
499 case WebAssembly::LOCAL_SET_F32_S:
500 case WebAssembly::LOCAL_SET_F64:
501 case WebAssembly::LOCAL_SET_F64_S:
502 case WebAssembly::LOCAL_SET_V128:
503 case WebAssembly::LOCAL_SET_V128_S:
504 case WebAssembly::LOCAL_SET_FUNCREF:
505 case WebAssembly::LOCAL_SET_FUNCREF_S:
506 case WebAssembly::LOCAL_SET_EXTERNREF:
507 case WebAssembly::LOCAL_SET_EXTERNREF_S:
508 return true;
509 default:
510 return false;
511 }
512}
513
514inline bool isLocalTee(unsigned Opc) {
515 switch (Opc) {
516 case WebAssembly::LOCAL_TEE_I32:
517 case WebAssembly::LOCAL_TEE_I32_S:
518 case WebAssembly::LOCAL_TEE_I64:
519 case WebAssembly::LOCAL_TEE_I64_S:
520 case WebAssembly::LOCAL_TEE_F32:
521 case WebAssembly::LOCAL_TEE_F32_S:
522 case WebAssembly::LOCAL_TEE_F64:
523 case WebAssembly::LOCAL_TEE_F64_S:
524 case WebAssembly::LOCAL_TEE_V128:
525 case WebAssembly::LOCAL_TEE_V128_S:
526 case WebAssembly::LOCAL_TEE_FUNCREF:
527 case WebAssembly::LOCAL_TEE_FUNCREF_S:
528 case WebAssembly::LOCAL_TEE_EXTERNREF:
529 case WebAssembly::LOCAL_TEE_EXTERNREF_S:
530 return true;
531 default:
532 return false;
533 }
534}
535
536} // end namespace WebAssembly
537} // end namespace llvm
538
539#endif
IRTranslator LLVM IR MI
#define WASM_LOAD_STORE(NAME)
Representation of each machine instruction.
Definition: MachineInstr.h:68
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ OPERAND_FIRST_TARGET
Definition: MCInstrDesc.h:78
TOF
Target Operand Flag enum.
bool isLocalTee(unsigned Opc)
bool isBrTable(const MachineInstr &MI)
bool isArgument(unsigned Opc)
bool isCallIndirect(unsigned Opc)
unsigned GetDefaultP2Align(unsigned Opc)
bool isMarker(unsigned Opc)
bool isCatch(unsigned Opc)
static const unsigned Nop
Instruction opcodes emitted via means other than CodeGen.
cl::opt< bool > WasmEnableEH
bool isCopy(unsigned Opc)
cl::opt< bool > WasmEnableSjLj
bool isTee(unsigned Opc)
static const unsigned End
bool isConst(unsigned Opc)
cl::opt< bool > WasmEnableEmEH
@ OPERAND_GLOBAL
Global index.
@ OPERAND_OFFSET64
64-bit unsigned memory offsets.
@ OPERAND_I32IMM
32-bit integer immediates.
@ OPERAND_P2ALIGN
p2align immediate for load and store address alignment.
@ OPERAND_TABLE
32-bit unsigned table number.
@ OPERAND_VEC_I64IMM
64-bit vector lane immediate
@ OPERAND_VEC_I16IMM
16-bit vector lane immediate
@ OPERAND_TYPEINDEX
type signature immediate for call_indirect.
@ OPERAND_FUNCTION32
32-bit unsigned function indices.
@ OPERAND_F32IMM
32-bit floating-point immediates.
@ OPERAND_BASIC_BLOCK
Basic block label in a branch construct.
@ OPERAND_VEC_I32IMM
32-bit vector lane immediate
@ OPERAND_BRLIST
A list of branch targets for br_list.
@ OPERAND_F64IMM
64-bit floating-point immediates.
@ OPERAND_VEC_I8IMM
8-bit vector lane immediate
@ OPERAND_SIGNATURE
signature immediate for block/loop.
@ OPERAND_I64IMM
64-bit integer immediates.
@ OPERAND_OFFSET32
32-bit unsigned memory offsets.
unsigned GetDefaultP2AlignAny(unsigned Opc)
Return the default p2align value for a load or store with the given opcode.
cl::opt< bool > WasmEnableEmSjLj
bool isCallDirect(unsigned Opc)
bool isScalarConst(unsigned Opc)
bool isLocalSet(unsigned Opc)
bool isLocalGet(unsigned Opc)
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
MCAsmBackend * createWebAssemblyAsmBackend(const Triple &TT)
MCCodeEmitter * createWebAssemblyMCCodeEmitter(const MCInstrInfo &MCII)
std::unique_ptr< MCObjectTargetWriter > createWebAssemblyWasmObjectWriter(bool Is64Bit, bool IsEmscripten)
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39