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ARMISelLowering.h
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1 //===- ARMISelLowering.h - ARM DAG Lowering Interface -----------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the interfaces that ARM uses to lower LLVM code into a
10 // selection DAG.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H
15 #define LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H
16 
18 #include "llvm/ADT/SmallVector.h"
19 #include "llvm/ADT/StringRef.h"
26 #include "llvm/IR/Attributes.h"
27 #include "llvm/IR/CallingConv.h"
28 #include "llvm/IR/Function.h"
29 #include "llvm/IR/IRBuilder.h"
30 #include "llvm/IR/InlineAsm.h"
31 #include "llvm/Support/CodeGen.h"
33 #include <utility>
34 
35 namespace llvm {
36 
37 class ARMSubtarget;
38 class DataLayout;
39 class FastISel;
40 class FunctionLoweringInfo;
41 class GlobalValue;
42 class InstrItineraryData;
43 class Instruction;
44 class MachineBasicBlock;
45 class MachineInstr;
46 class SelectionDAG;
47 class TargetLibraryInfo;
48 class TargetMachine;
49 class TargetRegisterInfo;
50 class VectorType;
51 
52  namespace ARMISD {
53 
54  // ARM Specific DAG Nodes
55  enum NodeType : unsigned {
56  // Start the numbering where the builtin ops and target ops leave off.
58 
59  Wrapper, // Wrapper - A wrapper node for TargetConstantPool,
60  // TargetExternalSymbol, and TargetGlobalAddress.
61  WrapperPIC, // WrapperPIC - A wrapper node for TargetGlobalAddress in
62  // PIC mode.
63  WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable
64 
65  // Add pseudo op to model memcpy for struct byval.
67 
68  CALL, // Function call.
69  CALL_PRED, // Function call that's predicable.
70  CALL_NOLINK, // Function call with branch not branch-and-link.
71  BRCOND, // Conditional branch.
72  BR_JT, // Jumptable branch.
73  BR2_JT, // Jumptable branch (2 level - jumptable entry is a jump).
74  RET_FLAG, // Return with a flag operand.
75  INTRET_FLAG, // Interrupt return with an LR-offset and a flag operand.
76 
77  PIC_ADD, // Add with a PC operand and a PIC label.
78 
79  ASRL, // MVE long arithmetic shift right.
80  LSRL, // MVE long shift right.
81  LSLL, // MVE long shift left.
82 
83  CMP, // ARM compare instructions.
84  CMN, // ARM CMN instructions.
85  CMPZ, // ARM compare that sets only Z flag.
86  CMPFP, // ARM VFP compare instruction, sets FPSCR.
87  CMPFPw0, // ARM VFP compare against zero instruction, sets FPSCR.
88  FMSTAT, // ARM fmstat instruction.
89 
90  CMOV, // ARM conditional move instructions.
91  SUBS, // Flag-setting subtraction.
92 
93  SSAT, // Signed saturation
94  USAT, // Unsigned saturation
95 
97 
98  SRL_FLAG, // V,Flag = srl_flag X -> srl X, 1 + save carry out.
99  SRA_FLAG, // V,Flag = sra_flag X -> sra X, 1 + save carry out.
100  RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag.
101 
102  ADDC, // Add with carry
103  ADDE, // Add using carry
104  SUBC, // Sub with carry
105  SUBE, // Sub using carry
106  LSLS, // Shift left producing carry
107 
108  VMOVRRD, // double to two gprs.
109  VMOVDRR, // Two gprs to double.
110  VMOVSR, // move gpr to single, used for f32 literal constructed in a gpr
111 
112  EH_SJLJ_SETJMP, // SjLj exception handling setjmp.
113  EH_SJLJ_LONGJMP, // SjLj exception handling longjmp.
114  EH_SJLJ_SETUP_DISPATCH, // SjLj exception handling setup_dispatch.
115 
116  TC_RETURN, // Tail call return pseudo.
117 
119 
120  DYN_ALLOC, // Dynamic allocation on the stack.
121 
122  MEMBARRIER_MCR, // Memory barrier (MCR)
123 
124  PRELOAD, // Preload
125 
126  WIN__CHKSTK, // Windows' __chkstk call to do stack probing.
127  WIN__DBZCHK, // Windows' divide by zero check
128 
129  WLS, // Low-overhead loops, While Loop Start
130  LOOP_DEC, // Really a part of LE, performs the sub
131  LE, // Low-overhead loops, Loop End
132 
133  PREDICATE_CAST, // Predicate cast for MVE i1 types
134 
135  VCMP, // Vector compare.
136  VCMPZ, // Vector compare to zero.
137  VTST, // Vector test bits.
138 
139  // Vector shift by vector
140  VSHLs, // ...left/right by signed
141  VSHLu, // ...left/right by unsigned
142 
143  // Vector shift by immediate:
144  VSHLIMM, // ...left
145  VSHRsIMM, // ...right (signed)
146  VSHRuIMM, // ...right (unsigned)
147 
148  // Vector rounding shift by immediate:
149  VRSHRsIMM, // ...right (signed)
150  VRSHRuIMM, // ...right (unsigned)
151  VRSHRNIMM, // ...right narrow
152 
153  // Vector saturating shift by immediate:
154  VQSHLsIMM, // ...left (signed)
155  VQSHLuIMM, // ...left (unsigned)
156  VQSHLsuIMM, // ...left (signed to unsigned)
157  VQSHRNsIMM, // ...right narrow (signed)
158  VQSHRNuIMM, // ...right narrow (unsigned)
159  VQSHRNsuIMM, // ...right narrow (signed to unsigned)
160 
161  // Vector saturating rounding shift by immediate:
162  VQRSHRNsIMM, // ...right narrow (signed)
163  VQRSHRNuIMM, // ...right narrow (unsigned)
164  VQRSHRNsuIMM, // ...right narrow (signed to unsigned)
165 
166  // Vector shift and insert:
167  VSLIIMM, // ...left
168  VSRIIMM, // ...right
169 
170  // Vector get lane (VMOV scalar to ARM core register)
171  // (These are used for 8- and 16-bit element types only.)
172  VGETLANEu, // zero-extend vector extract element
173  VGETLANEs, // sign-extend vector extract element
174 
175  // Vector move immediate and move negated immediate:
178 
179  // Vector move f32 immediate:
181 
182  // Move H <-> R, clearing top 16 bits
185 
186  // Vector duplicate:
189 
190  // Vector shuffles:
191  VEXT, // extract
192  VREV64, // reverse elements within 64-bit doublewords
193  VREV32, // reverse elements within 32-bit words
194  VREV16, // reverse elements within 16-bit halfwords
195  VZIP, // zip (interleave)
196  VUZP, // unzip (deinterleave)
197  VTRN, // transpose
198  VTBL1, // 1-register shuffle with mask
199  VTBL2, // 2-register shuffle with mask
200 
201  // Vector multiply long:
202  VMULLs, // ...signed
203  VMULLu, // ...unsigned
204 
205  SMULWB, // Signed multiply word by half word, bottom
206  SMULWT, // Signed multiply word by half word, top
207  UMLAL, // 64bit Unsigned Accumulate Multiply
208  SMLAL, // 64bit Signed Accumulate Multiply
209  UMAAL, // 64-bit Unsigned Accumulate Accumulate Multiply
210  SMLALBB, // 64-bit signed accumulate multiply bottom, bottom 16
211  SMLALBT, // 64-bit signed accumulate multiply bottom, top 16
212  SMLALTB, // 64-bit signed accumulate multiply top, bottom 16
213  SMLALTT, // 64-bit signed accumulate multiply top, top 16
214  SMLALD, // Signed multiply accumulate long dual
215  SMLALDX, // Signed multiply accumulate long dual exchange
216  SMLSLD, // Signed multiply subtract long dual
217  SMLSLDX, // Signed multiply subtract long dual exchange
218  SMMLAR, // Signed multiply long, round and add
219  SMMLSR, // Signed multiply long, subtract and round
220 
221  // Operands of the standard BUILD_VECTOR node are not legalized, which
222  // is fine if BUILD_VECTORs are always lowered to shuffles or other
223  // operations, but for ARM some BUILD_VECTORs are legal as-is and their
224  // operands need to be legalized. Define an ARM-specific version of
225  // BUILD_VECTOR for this purpose.
227 
228  // Bit-field insert
230 
231  // Vector OR with immediate
233  // Vector AND with NOT of immediate
235 
236  // Vector bitwise select
238 
239  // Pseudo-instruction representing a memory copy using ldm/stm
240  // instructions.
242 
243  // V8.1MMainline condition select
244  CSINV, // Conditional select invert.
245  CSNEG, // Conditional select negate.
246  CSINC, // Conditional select increment.
247 
248  // Vector load N-element structure to all lanes:
253 
254  // NEON loads with post-increment base updates:
266 
267  // NEON stores with post-increment base updates:
275  };
276 
277  } // end namespace ARMISD
278 
279  /// Define some predicates that are used for node matching.
280  namespace ARM {
281 
282  bool isBitFieldInvertedMask(unsigned v);
283 
284  } // end namespace ARM
285 
286  //===--------------------------------------------------------------------===//
287  // ARMTargetLowering - ARM Implementation of the TargetLowering interface
288 
290  public:
291  explicit ARMTargetLowering(const TargetMachine &TM,
292  const ARMSubtarget &STI);
293 
294  unsigned getJumpTableEncoding() const override;
295  bool useSoftFloat() const override;
296 
297  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
298 
299  /// ReplaceNodeResults - Replace the results of node with an illegal result
300  /// type with new values built out of custom code.
301  void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
302  SelectionDAG &DAG) const override;
303 
304  const char *getTargetNodeName(unsigned Opcode) const override;
305 
306  bool isSelectSupported(SelectSupportKind Kind) const override {
307  // ARM does not support scalar condition selects on vectors.
308  return (Kind != ScalarCondVectorVal);
309  }
310 
311  bool isReadOnly(const GlobalValue *GV) const;
312 
313  /// getSetCCResultType - Return the value type to use for ISD::SETCC.
314  EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
315  EVT VT) const override;
316 
318  EmitInstrWithCustomInserter(MachineInstr &MI,
319  MachineBasicBlock *MBB) const override;
320 
321  void AdjustInstrPostInstrSelection(MachineInstr &MI,
322  SDNode *Node) const override;
323 
324  SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const;
325  SDValue PerformBRCONDCombine(SDNode *N, SelectionDAG &DAG) const;
326  SDValue PerformCMOVToBFICombine(SDNode *N, SelectionDAG &DAG) const;
327  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
328 
329  bool isDesirableToTransformToIntegerOp(unsigned Opc, EVT VT) const override;
330 
331  /// allowsMisalignedMemoryAccesses - Returns true if the target allows
332  /// unaligned memory accesses of the specified type. Returns whether it
333  /// is "fast" by reference in the second argument.
334  bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace,
335  unsigned Align,
337  bool *Fast) const override;
338 
339  EVT getOptimalMemOpType(uint64_t Size,
340  unsigned DstAlign, unsigned SrcAlign,
341  bool IsMemset, bool ZeroMemset,
342  bool MemcpyStrSrc,
343  const AttributeList &FuncAttributes) const override;
344 
345  bool isTruncateFree(Type *SrcTy, Type *DstTy) const override;
346  bool isTruncateFree(EVT SrcVT, EVT DstVT) const override;
347  bool isZExtFree(SDValue Val, EVT VT2) const override;
348  bool shouldSinkOperands(Instruction *I,
349  SmallVectorImpl<Use *> &Ops) const override;
350 
351  bool isFNegFree(EVT VT) const override;
352 
353  bool isVectorLoadExtDesirable(SDValue ExtVal) const override;
354 
355  bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override;
356 
357 
358  /// isLegalAddressingMode - Return true if the addressing mode represented
359  /// by AM is legal for this target, for a load/store of the specified type.
360  bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
361  Type *Ty, unsigned AS,
362  Instruction *I = nullptr) const override;
363 
364  /// getScalingFactorCost - Return the cost of the scaling used in
365  /// addressing mode represented by AM.
366  /// If the AM is supported, the return value must be >= 0.
367  /// If the AM is not supported, the return value must be negative.
368  int getScalingFactorCost(const DataLayout &DL, const AddrMode &AM, Type *Ty,
369  unsigned AS) const override;
370 
371  bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
372 
373  /// Returns true if the addresing mode representing by AM is legal
374  /// for the Thumb1 target, for a load/store of the specified type.
375  bool isLegalT1ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
376 
377  /// isLegalICmpImmediate - Return true if the specified immediate is legal
378  /// icmp immediate, that is the target has icmp instructions which can
379  /// compare a register against the immediate without having to materialize
380  /// the immediate into a register.
381  bool isLegalICmpImmediate(int64_t Imm) const override;
382 
383  /// isLegalAddImmediate - Return true if the specified immediate is legal
384  /// add immediate, that is the target has add instructions which can
385  /// add a register and the immediate without having to materialize
386  /// the immediate into a register.
387  bool isLegalAddImmediate(int64_t Imm) const override;
388 
389  /// getPreIndexedAddressParts - returns true by value, base pointer and
390  /// offset pointer and addressing mode by reference if the node's address
391  /// can be legally represented as pre-indexed load / store address.
392  bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset,
394  SelectionDAG &DAG) const override;
395 
396  /// getPostIndexedAddressParts - returns true by value, base pointer and
397  /// offset pointer and addressing mode by reference if this node can be
398  /// combined with a load / store to form a post-indexed load / store.
399  bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base,
400  SDValue &Offset, ISD::MemIndexedMode &AM,
401  SelectionDAG &DAG) const override;
402 
403  void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known,
404  const APInt &DemandedElts,
405  const SelectionDAG &DAG,
406  unsigned Depth) const override;
407 
408  bool targetShrinkDemandedConstant(SDValue Op, const APInt &Demanded,
409  TargetLoweringOpt &TLO) const override;
410 
411 
412  bool ExpandInlineAsm(CallInst *CI) const override;
413 
414  ConstraintType getConstraintType(StringRef Constraint) const override;
415 
416  /// Examine constraint string and operand type and determine a weight value.
417  /// The operand object must already have been set up with the operand type.
418  ConstraintWeight getSingleConstraintMatchWeight(
419  AsmOperandInfo &info, const char *constraint) const override;
420 
421  std::pair<unsigned, const TargetRegisterClass *>
422  getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
423  StringRef Constraint, MVT VT) const override;
424 
425  const char *LowerXConstraint(EVT ConstraintVT) const override;
426 
427  /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
428  /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
429  /// true it means one of the asm constraint of the inline asm instruction
430  /// being processed is 'm'.
431  void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
432  std::vector<SDValue> &Ops,
433  SelectionDAG &DAG) const override;
434 
435  unsigned
436  getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
437  if (ConstraintCode == "Q")
439  else if (ConstraintCode == "o")
441  else if (ConstraintCode.size() == 2) {
442  if (ConstraintCode[0] == 'U') {
443  switch(ConstraintCode[1]) {
444  default:
445  break;
446  case 'm':
448  case 'n':
450  case 'q':
452  case 's':
454  case 't':
456  case 'v':
458  case 'y':
460  }
461  }
462  }
463  return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
464  }
465 
466  const ARMSubtarget* getSubtarget() const {
467  return Subtarget;
468  }
469 
470  /// getRegClassFor - Return the register class that should be used for the
471  /// specified value type.
472  const TargetRegisterClass *
473  getRegClassFor(MVT VT, bool isDivergent = false) const override;
474 
475  /// Returns true if a cast between SrcAS and DestAS is a noop.
476  bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {
477  // Addrspacecasts are always noops.
478  return true;
479  }
480 
481  bool shouldAlignPointerArgs(CallInst *CI, unsigned &MinSize,
482  unsigned &PrefAlign) const override;
483 
484  /// createFastISel - This method returns a target specific FastISel object,
485  /// or null if the target does not support "fast" ISel.
487  const TargetLibraryInfo *libInfo) const override;
488 
489  Sched::Preference getSchedulingPreference(SDNode *N) const override;
490 
491  bool
492  isShuffleMaskLegal(ArrayRef<int> M, EVT VT) const override;
493  bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
494 
495  /// isFPImmLegal - Returns true if the target can instruction select the
496  /// specified FP immediate natively. If false, the legalizer will
497  /// materialize the FP immediate as a load from a constant pool.
498  bool isFPImmLegal(const APFloat &Imm, EVT VT,
499  bool ForCodeSize = false) const override;
500 
501  bool getTgtMemIntrinsic(IntrinsicInfo &Info,
502  const CallInst &I,
503  MachineFunction &MF,
504  unsigned Intrinsic) const override;
505 
506  /// Returns true if it is beneficial to convert a load of a constant
507  /// to just the constant itself.
508  bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
509  Type *Ty) const override;
510 
511  /// Return true if EXTRACT_SUBVECTOR is cheap for this result type
512  /// with this index.
513  bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
514  unsigned Index) const override;
515 
516  /// Returns true if an argument of type Ty needs to be passed in a
517  /// contiguous block of registers in calling convention CallConv.
518  bool functionArgumentNeedsConsecutiveRegisters(
519  Type *Ty, CallingConv::ID CallConv, bool isVarArg) const override;
520 
521  /// If a physical register, this returns the register that receives the
522  /// exception address on entry to an EH pad.
523  unsigned
524  getExceptionPointerRegister(const Constant *PersonalityFn) const override;
525 
526  /// If a physical register, this returns the register that receives the
527  /// exception typeid on entry to a landing pad.
528  unsigned
529  getExceptionSelectorRegister(const Constant *PersonalityFn) const override;
530 
531  Instruction *makeDMB(IRBuilder<> &Builder, ARM_MB::MemBOpt Domain) const;
532  Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
533  AtomicOrdering Ord) const override;
534  Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val,
535  Value *Addr, AtomicOrdering Ord) const override;
536 
537  void emitAtomicCmpXchgNoStoreLLBalance(IRBuilder<> &Builder) const override;
538 
539  Instruction *emitLeadingFence(IRBuilder<> &Builder, Instruction *Inst,
540  AtomicOrdering Ord) const override;
541  Instruction *emitTrailingFence(IRBuilder<> &Builder, Instruction *Inst,
542  AtomicOrdering Ord) const override;
543 
544  unsigned getMaxSupportedInterleaveFactor() const override;
545 
546  bool lowerInterleavedLoad(LoadInst *LI,
548  ArrayRef<unsigned> Indices,
549  unsigned Factor) const override;
550  bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI,
551  unsigned Factor) const override;
552 
553  bool shouldInsertFencesForAtomic(const Instruction *I) const override;
555  shouldExpandAtomicLoadInIR(LoadInst *LI) const override;
556  bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
558  shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
560  shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override;
561 
562  bool useLoadStackGuardNode() const override;
563 
564  void insertSSPDeclarations(Module &M) const override;
565  Value *getSDagStackGuard(const Module &M) const override;
566  Function *getSSPStackGuardCheck(const Module &M) const override;
567 
568  bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx,
569  unsigned &Cost) const override;
570 
571  bool canMergeStoresTo(unsigned AddressSpace, EVT MemVT,
572  const SelectionDAG &DAG) const override {
573  // Do not merge to larger than i32.
574  return (MemVT.getSizeInBits() <= 32);
575  }
576 
577  bool isCheapToSpeculateCttz() const override;
578  bool isCheapToSpeculateCtlz() const override;
579 
580  bool convertSetCCLogicToBitwiseLogic(EVT VT) const override {
581  return VT.isScalarInteger();
582  }
583 
584  bool supportSwiftError() const override {
585  return true;
586  }
587 
588  bool hasStandaloneRem(EVT VT) const override {
589  return HasStandaloneRem;
590  }
591 
592  bool shouldExpandShift(SelectionDAG &DAG, SDNode *N) const override;
593 
594  CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool isVarArg) const;
595  CCAssignFn *CCAssignFnForReturn(CallingConv::ID CC, bool isVarArg) const;
596 
597  /// Returns true if \p VecTy is a legal interleaved access type. This
598  /// function checks the vector element type and the overall width of the
599  /// vector.
600  bool isLegalInterleavedAccessType(VectorType *VecTy,
601  const DataLayout &DL) const;
602 
603  bool alignLoopsWithOptSize() const override;
604 
605  /// Returns the number of interleaved accesses that will be generated when
606  /// lowering accesses of the given type.
607  unsigned getNumInterleavedAccesses(VectorType *VecTy,
608  const DataLayout &DL) const;
609 
610  void finalizeLowering(MachineFunction &MF) const override;
611 
612  /// Return the correct alignment for the current calling convention.
613  unsigned getABIAlignmentForCallingConv(Type *ArgTy,
614  DataLayout DL) const override;
615 
616  bool isDesirableToCommuteWithShift(const SDNode *N,
617  CombineLevel Level) const override;
618 
619  bool shouldFoldConstantShiftPairToMask(const SDNode *N,
620  CombineLevel Level) const override;
621 
622  bool preferIncOfAddToSubOfNot(EVT VT) const override;
623 
624  protected:
625  std::pair<const TargetRegisterClass *, uint8_t>
626  findRepresentativeClass(const TargetRegisterInfo *TRI,
627  MVT VT) const override;
628 
629  private:
630  /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
631  /// make the right decision when generating code for different targets.
632  const ARMSubtarget *Subtarget;
633 
635 
636  const InstrItineraryData *Itins;
637 
638  /// ARMPCLabelIndex - Keep track of the number of ARM PC labels created.
639  unsigned ARMPCLabelIndex;
640 
641  // TODO: remove this, and have shouldInsertFencesForAtomic do the proper
642  // check.
643  bool InsertFencesForAtomic;
644 
645  bool HasStandaloneRem = true;
646 
647  void addTypeForNEON(MVT VT, MVT PromotedLdStVT, MVT PromotedBitwiseVT);
648  void addDRTypeForNEON(MVT VT);
649  void addQRTypeForNEON(MVT VT);
650  std::pair<SDValue, SDValue> getARMXALUOOp(SDValue Op, SelectionDAG &DAG, SDValue &ARMcc) const;
651 
653 
654  void PassF64ArgInRegs(const SDLoc &dl, SelectionDAG &DAG, SDValue Chain,
655  SDValue &Arg, RegsToPassVector &RegsToPass,
656  CCValAssign &VA, CCValAssign &NextVA,
657  SDValue &StackPtr,
658  SmallVectorImpl<SDValue> &MemOpChains,
659  ISD::ArgFlagsTy Flags) const;
660  SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
661  SDValue &Root, SelectionDAG &DAG,
662  const SDLoc &dl) const;
663 
664  CallingConv::ID getEffectiveCallingConv(CallingConv::ID CC,
665  bool isVarArg) const;
666  CCAssignFn *CCAssignFnForNode(CallingConv::ID CC, bool Return,
667  bool isVarArg) const;
668  SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
669  const SDLoc &dl, SelectionDAG &DAG,
670  const CCValAssign &VA,
671  ISD::ArgFlagsTy Flags) const;
672  SDValue LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
673  SDValue LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
674  SDValue LowerEH_SJLJ_SETUP_DISPATCH(SDValue Op, SelectionDAG &DAG) const;
675  SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG,
676  const ARMSubtarget *Subtarget) const;
677  SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
678  const ARMSubtarget *Subtarget) const;
679  SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
680  SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
681  SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
682  SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG) const;
683  SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) const;
684  SDValue LowerGlobalAddressWindows(SDValue Op, SelectionDAG &DAG) const;
685  SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
686  SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
687  SelectionDAG &DAG) const;
688  SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA,
689  SelectionDAG &DAG,
690  TLSModel::Model model) const;
691  SDValue LowerGlobalTLSAddressDarwin(SDValue Op, SelectionDAG &DAG) const;
692  SDValue LowerGlobalTLSAddressWindows(SDValue Op, SelectionDAG &DAG) const;
693  SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const;
694  SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
695  SDValue LowerSignedALUO(SDValue Op, SelectionDAG &DAG) const;
696  SDValue LowerUnsignedALUO(SDValue Op, SelectionDAG &DAG) const;
697  SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
698  SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
699  SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
700  SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
701  SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
703  SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
704  SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const;
705  SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
706  SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
707  SDValue LowerConstantFP(SDValue Op, SelectionDAG &DAG,
708  const ARMSubtarget *ST) const;
709  SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
710  const ARMSubtarget *ST) const;
711  SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
712  SDValue LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const;
713  SDValue LowerDivRem(SDValue Op, SelectionDAG &DAG) const;
714  SDValue LowerDIV_Windows(SDValue Op, SelectionDAG &DAG, bool Signed) const;
715  void ExpandDIV_Windows(SDValue Op, SelectionDAG &DAG, bool Signed,
716  SmallVectorImpl<SDValue> &Results) const;
717  SDValue LowerWindowsDIVLibCall(SDValue Op, SelectionDAG &DAG, bool Signed,
718  SDValue &Chain) const;
719  SDValue LowerREM(SDNode *N, SelectionDAG &DAG) const;
721  SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
722  SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const;
723  SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
724  SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
725  void lowerABS(SDNode *N, SmallVectorImpl<SDValue> &Results,
726  SelectionDAG &DAG) const;
727 
728  Register getRegisterByName(const char* RegName, EVT VT,
729  const MachineFunction &MF) const override;
730 
731  SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
732  SmallVectorImpl<SDNode *> &Created) const override;
733 
734  /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster
735  /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be
736  /// expanded to FMAs when this method returns true, otherwise fmuladd is
737  /// expanded to fmul + fadd.
738  ///
739  /// ARM supports both fused and unfused multiply-add operations; we already
740  /// lower a pair of fmul and fadd to the latter so it's not clear that there
741  /// would be a gain or that the gain would be worthwhile enough to risk
742  /// correctness bugs.
743  bool isFMAFasterThanFMulAndFAdd(EVT VT) const override { return false; }
744 
745  SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const;
746 
747  SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
748  CallingConv::ID CallConv, bool isVarArg,
750  const SDLoc &dl, SelectionDAG &DAG,
751  SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
752  SDValue ThisVal) const;
753 
754  bool supportSplitCSR(MachineFunction *MF) const override {
756  MF->getFunction().hasFnAttribute(Attribute::NoUnwind);
757  }
758 
759  void initializeSplitCSR(MachineBasicBlock *Entry) const override;
760  void insertCopiesSplitCSR(
761  MachineBasicBlock *Entry,
762  const SmallVectorImpl<MachineBasicBlock *> &Exits) const override;
763 
764  SDValue
765  LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
767  const SDLoc &dl, SelectionDAG &DAG,
768  SmallVectorImpl<SDValue> &InVals) const override;
769 
770  int StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG, const SDLoc &dl,
771  SDValue &Chain, const Value *OrigArg,
772  unsigned InRegsParamRecordIdx, int ArgOffset,
773  unsigned ArgSize) const;
774 
775  void VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
776  const SDLoc &dl, SDValue &Chain,
777  unsigned ArgOffset, unsigned TotalArgRegsSaveSize,
778  bool ForceMutable = false) const;
779 
781  SmallVectorImpl<SDValue> &InVals) const override;
782 
783  /// HandleByVal - Target-specific cleanup for ByVal support.
784  void HandleByVal(CCState *, unsigned &, unsigned) const override;
785 
786  /// IsEligibleForTailCallOptimization - Check whether the call is eligible
787  /// for tail call optimization. Targets which want to do tail call
788  /// optimization should implement this function.
789  bool IsEligibleForTailCallOptimization(
790  SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
791  bool isCalleeStructRet, bool isCallerStructRet,
793  const SmallVectorImpl<SDValue> &OutVals,
795  const bool isIndirect) const;
796 
797  bool CanLowerReturn(CallingConv::ID CallConv,
798  MachineFunction &MF, bool isVarArg,
800  LLVMContext &Context) const override;
801 
802  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
804  const SmallVectorImpl<SDValue> &OutVals,
805  const SDLoc &dl, SelectionDAG &DAG) const override;
806 
807  bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
808 
809  bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
810 
811  bool shouldConsiderGEPOffsetSplit() const override { return true; }
812 
813  bool isUnsupportedFloatingType(EVT VT) const;
814 
815  SDValue getCMOV(const SDLoc &dl, EVT VT, SDValue FalseVal, SDValue TrueVal,
816  SDValue ARMcc, SDValue CCR, SDValue Cmp,
817  SelectionDAG &DAG) const;
818  SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
819  SDValue &ARMcc, SelectionDAG &DAG, const SDLoc &dl) const;
820  SDValue getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
821  const SDLoc &dl) const;
822  SDValue duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const;
823 
824  SDValue OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const;
825 
826  void SetupEntryBlockForSjLj(MachineInstr &MI, MachineBasicBlock *MBB,
827  MachineBasicBlock *DispatchBB, int FI) const;
828 
829  void EmitSjLjDispatchBlock(MachineInstr &MI, MachineBasicBlock *MBB) const;
830 
831  bool RemapAddSubWithFlags(MachineInstr &MI, MachineBasicBlock *BB) const;
832 
833  MachineBasicBlock *EmitStructByval(MachineInstr &MI,
834  MachineBasicBlock *MBB) const;
835 
836  MachineBasicBlock *EmitLowered__chkstk(MachineInstr &MI,
837  MachineBasicBlock *MBB) const;
838  MachineBasicBlock *EmitLowered__dbzchk(MachineInstr &MI,
839  MachineBasicBlock *MBB) const;
840  void addMVEVectorTypes(bool HasMVEFP);
841  void addAllExtLoads(const MVT From, const MVT To, LegalizeAction Action);
842  void setAllExpand(MVT VT);
843  };
844 
850  };
851 
852  namespace ARM {
853 
855  const TargetLibraryInfo *libInfo);
856 
857  } // end namespace ARM
858 
859 } // end namespace llvm
860 
861 #endif // LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H
static SDValue LowerCallResult(SDValue Chain, SDValue InFlag, const SmallVectorImpl< CCValAssign > &RVLocs, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals)
LowerCallResult - Lower the result values of a call into the appropriate copies out of appropriate ph...
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:914
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:112
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...
LLVMContext & Context
This class represents lattice values for constants.
Definition: AllocatorList.h:23
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:65
An instruction that atomically checks whether a specified value is in a memory location, and, if it is, stores a new value there.
Definition: Instructions.h:538
static void LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain, SDValue Arg, SDValue PtrOff, int SPDiff, unsigned ArgOffset, bool isPPC64, bool isTailCall, bool isVector, SmallVectorImpl< SDValue > &MemOpChains, SmallVectorImpl< TailCallArgumentInfo > &TailCallArguments, const SDLoc &dl)
LowerMemOpCallTo - Store the argument to the stack or remember it in case of tail calls...
bool isScalarInteger() const
Return true if this is an integer, but not a vector.
Definition: ValueTypes.h:145
This class represents a function call, abstracting a target machine&#39;s calling convention.
bool hasStandaloneRem(EVT VT) const override
Return true if the target can handle a standalone remainder operation.
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change...
Function Alias Analysis Results
This instruction constructs a fixed permutation of two input vectors.
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.h:323
unsigned const TargetRegisterInfo * TRI
An instruction for reading from memory.
Definition: Instructions.h:169
an instruction that atomically reads a memory location, combines it with another value, and then stores the result back.
Definition: Instructions.h:701
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override
Returns true if a cast between SrcAS and DestAS is a noop.
A convenience struct that encapsulates a DAG, and two SDValues for returning information from TargetL...
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
This provides a uniform API for creating instructions and inserting them into a basic block: either a...
Definition: IRBuilder.h:779
This file contains the simple types necessary to represent the attributes associated with functions a...
static SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, const SparcSubtarget *Subtarget)
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
AtomicOrdering
Atomic ordering for LLVM&#39;s memory model.
This is a fast-path instruction selection class that generates poor code and doesn&#39;t support illegal ...
Definition: FastISel.h:66
unsigned getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:291
This contains information for each constraint that we are lowering.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
LLVM_NODISCARD size_t size() const
size - Get the string size.
Definition: StringRef.h:144
Itinerary data supplied by a subtarget to be used by a target.
An instruction for storing to memory.
Definition: Instructions.h:325
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
Definition: ISDOpcodes.h:1013
virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const
Analysis containing CSE Info
Definition: CSEInfo.cpp:20
Machine Value Type.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:46
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:64
This is an important base class in LLVM.
Definition: Constant.h:41
CombineLevel
Definition: DAGCombine.h:15
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:42
static SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget)
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
const ARMSubtarget * getSubtarget() const
static SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget)
lazy value info
Extended Value Type.
Definition: ValueTypes.h:33
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This structure contains all information that is necessary for lowering calls.
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:40
bool canMergeStoresTo(unsigned AddressSpace, EVT MemVT, const SelectionDAG &DAG) const override
Returns if it&#39;s reasonable to merge stores to MemVT size.
LegalizeAction
This enum indicates whether operations are valid for a target, and if not, what action should be used...
CCState - This class holds information needed while lowering arguments and return values...
BlockVerifier::State From
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:212
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:221
bool supportSwiftError() const override
Return true if the target supports swifterror attribute.
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:837
Provides information about what library functions are available for the current target.
CCValAssign - Represent assignment of one arg/retval to a location.
AddressSpace
Definition: NVPTXBaseInfo.h:21
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override
static const int FIRST_TARGET_MEMORY_OPCODE
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
Definition: ISDOpcodes.h:921
Represents one node in the SelectionDAG.
const Function & getFunction() const
Return the LLVM function that this machine code represents.
Class to represent vector types.
Definition: DerivedTypes.h:432
Class for arbitrary precision integers.
Definition: APInt.h:69
amdgpu Simplify well known AMD library false FunctionCallee Callee
static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad)
Flags
Flags values. These may be or&#39;d together.
static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad)
Representation of each machine instruction.
Definition: MachineInstr.h:64
static unsigned getScalingFactorCost(const TargetTransformInfo &TTI, const LSRUse &LU, const Formula &F, const Loop &L)
SelectSupportKind
Enum that describes what type of support for selects the target has.
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
uint32_t Size
Definition: Profile.cpp:46
bool isSelectSupported(SelectSupportKind Kind) const override
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo)
LLVM Value Representation.
Definition: Value.h:73
static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG)
bool convertSetCCLogicToBitwiseLogic(EVT VT) const override
Use bitwise logic to make pairs of compares more efficient.
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:65
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget &Subtarget, SelectionDAG &DAG)
bool isBitFieldInvertedMask(unsigned v)
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
This file describes how to lower LLVM code to machine code.
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.
Definition: ISDOpcodes.h:951