LLVM  10.0.0svn
InstrEmitter.cpp
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1 //==--- InstrEmitter.cpp - Emit MachineInstrs for the SelectionDAG class ---==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This implements the Emit routines for the SelectionDAG class, which creates
10 // MachineInstrs based on the decisions of the SelectionDAG instruction
11 // selection.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "InstrEmitter.h"
16 #include "SDNodeDbgValue.h"
17 #include "llvm/ADT/Statistic.h"
22 #include "llvm/CodeGen/StackMaps.h"
26 #include "llvm/IR/DataLayout.h"
27 #include "llvm/IR/DebugInfo.h"
28 #include "llvm/Support/Debug.h"
31 using namespace llvm;
32 
33 #define DEBUG_TYPE "instr-emitter"
34 
35 /// MinRCSize - Smallest register class we allow when constraining virtual
36 /// registers. If satisfying all register class constraints would require
37 /// using a smaller register class, emit a COPY to a new virtual register
38 /// instead.
39 const unsigned MinRCSize = 4;
40 
41 /// CountResults - The results of target nodes have register or immediate
42 /// operands first, then an optional chain, and optional glue operands (which do
43 /// not go into the resulting MachineInstr).
45  unsigned N = Node->getNumValues();
46  while (N && Node->getValueType(N - 1) == MVT::Glue)
47  --N;
48  if (N && Node->getValueType(N - 1) == MVT::Other)
49  --N; // Skip over chain result.
50  return N;
51 }
52 
53 /// countOperands - The inputs to target nodes have any actual inputs first,
54 /// followed by an optional chain operand, then an optional glue operand.
55 /// Compute the number of actual operands that will go into the resulting
56 /// MachineInstr.
57 ///
58 /// Also count physreg RegisterSDNode and RegisterMaskSDNode operands preceding
59 /// the chain and glue. These operands may be implicit on the machine instr.
60 static unsigned countOperands(SDNode *Node, unsigned NumExpUses,
61  unsigned &NumImpUses) {
62  unsigned N = Node->getNumOperands();
63  while (N && Node->getOperand(N - 1).getValueType() == MVT::Glue)
64  --N;
65  if (N && Node->getOperand(N - 1).getValueType() == MVT::Other)
66  --N; // Ignore chain if it exists.
67 
68  // Count RegisterSDNode and RegisterMaskSDNode operands for NumImpUses.
69  NumImpUses = N - NumExpUses;
70  for (unsigned I = N; I > NumExpUses; --I) {
71  if (isa<RegisterMaskSDNode>(Node->getOperand(I - 1)))
72  continue;
73  if (RegisterSDNode *RN = dyn_cast<RegisterSDNode>(Node->getOperand(I - 1)))
74  if (Register::isPhysicalRegister(RN->getReg()))
75  continue;
76  NumImpUses = N - I;
77  break;
78  }
79 
80  return N;
81 }
82 
83 /// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an
84 /// implicit physical register output.
85 void InstrEmitter::
86 EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone, bool IsCloned,
87  unsigned SrcReg, DenseMap<SDValue, unsigned> &VRBaseMap) {
88  unsigned VRBase = 0;
89  if (Register::isVirtualRegister(SrcReg)) {
90  // Just use the input register directly!
91  SDValue Op(Node, ResNo);
92  if (IsClone)
93  VRBaseMap.erase(Op);
94  bool isNew = VRBaseMap.insert(std::make_pair(Op, SrcReg)).second;
95  (void)isNew; // Silence compiler warning.
96  assert(isNew && "Node emitted out of order - early");
97  return;
98  }
99 
100  // If the node is only used by a CopyToReg and the dest reg is a vreg, use
101  // the CopyToReg'd destination register instead of creating a new vreg.
102  bool MatchReg = true;
103  const TargetRegisterClass *UseRC = nullptr;
104  MVT VT = Node->getSimpleValueType(ResNo);
105 
106  // Stick to the preferred register classes for legal types.
107  if (TLI->isTypeLegal(VT))
108  UseRC = TLI->getRegClassFor(VT, Node->isDivergent());
109 
110  if (!IsClone && !IsCloned)
111  for (SDNode *User : Node->uses()) {
112  bool Match = true;
113  if (User->getOpcode() == ISD::CopyToReg &&
114  User->getOperand(2).getNode() == Node &&
115  User->getOperand(2).getResNo() == ResNo) {
116  unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
117  if (Register::isVirtualRegister(DestReg)) {
118  VRBase = DestReg;
119  Match = false;
120  } else if (DestReg != SrcReg)
121  Match = false;
122  } else {
123  for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
124  SDValue Op = User->getOperand(i);
125  if (Op.getNode() != Node || Op.getResNo() != ResNo)
126  continue;
127  MVT VT = Node->getSimpleValueType(Op.getResNo());
128  if (VT == MVT::Other || VT == MVT::Glue)
129  continue;
130  Match = false;
131  if (User->isMachineOpcode()) {
132  const MCInstrDesc &II = TII->get(User->getMachineOpcode());
133  const TargetRegisterClass *RC = nullptr;
134  if (i+II.getNumDefs() < II.getNumOperands()) {
135  RC = TRI->getAllocatableClass(
136  TII->getRegClass(II, i+II.getNumDefs(), TRI, *MF));
137  }
138  if (!UseRC)
139  UseRC = RC;
140  else if (RC) {
141  const TargetRegisterClass *ComRC =
142  TRI->getCommonSubClass(UseRC, RC);
143  // If multiple uses expect disjoint register classes, we emit
144  // copies in AddRegisterOperand.
145  if (ComRC)
146  UseRC = ComRC;
147  }
148  }
149  }
150  }
151  MatchReg &= Match;
152  if (VRBase)
153  break;
154  }
155 
156  const TargetRegisterClass *SrcRC = nullptr, *DstRC = nullptr;
157  SrcRC = TRI->getMinimalPhysRegClass(SrcReg, VT);
158 
159  // Figure out the register class to create for the destreg.
160  if (VRBase) {
161  DstRC = MRI->getRegClass(VRBase);
162  } else if (UseRC) {
163  assert(TRI->isTypeLegalForClass(*UseRC, VT) &&
164  "Incompatible phys register def and uses!");
165  DstRC = UseRC;
166  } else {
167  DstRC = TLI->getRegClassFor(VT, Node->isDivergent());
168  }
169 
170  // If all uses are reading from the src physical register and copying the
171  // register is either impossible or very expensive, then don't create a copy.
172  if (MatchReg && SrcRC->getCopyCost() < 0) {
173  VRBase = SrcReg;
174  } else {
175  // Create the reg, emit the copy.
176  VRBase = MRI->createVirtualRegister(DstRC);
177  BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
178  VRBase).addReg(SrcReg);
179  }
180 
181  SDValue Op(Node, ResNo);
182  if (IsClone)
183  VRBaseMap.erase(Op);
184  bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
185  (void)isNew; // Silence compiler warning.
186  assert(isNew && "Node emitted out of order - early");
187 }
188 
189 void InstrEmitter::CreateVirtualRegisters(SDNode *Node,
190  MachineInstrBuilder &MIB,
191  const MCInstrDesc &II,
192  bool IsClone, bool IsCloned,
193  DenseMap<SDValue, unsigned> &VRBaseMap) {
194  assert(Node->getMachineOpcode() != TargetOpcode::IMPLICIT_DEF &&
195  "IMPLICIT_DEF should have been handled as a special case elsewhere!");
196 
197  unsigned NumResults = CountResults(Node);
198  for (unsigned i = 0; i < II.getNumDefs(); ++i) {
199  // If the specific node value is only used by a CopyToReg and the dest reg
200  // is a vreg in the same register class, use the CopyToReg'd destination
201  // register instead of creating a new vreg.
202  unsigned VRBase = 0;
203  const TargetRegisterClass *RC =
204  TRI->getAllocatableClass(TII->getRegClass(II, i, TRI, *MF));
205  // Always let the value type influence the used register class. The
206  // constraints on the instruction may be too lax to represent the value
207  // type correctly. For example, a 64-bit float (X86::FR64) can't live in
208  // the 32-bit float super-class (X86::FR32).
209  if (i < NumResults && TLI->isTypeLegal(Node->getSimpleValueType(i))) {
210  const TargetRegisterClass *VTRC = TLI->getRegClassFor(
211  Node->getSimpleValueType(i),
212  (Node->isDivergent() || (RC && TRI->isDivergentRegClass(RC))));
213  if (RC)
214  VTRC = TRI->getCommonSubClass(RC, VTRC);
215  if (VTRC)
216  RC = VTRC;
217  }
218 
219  if (II.OpInfo[i].isOptionalDef()) {
220  // Optional def must be a physical register.
221  VRBase = cast<RegisterSDNode>(Node->getOperand(i-NumResults))->getReg();
223  MIB.addReg(VRBase, RegState::Define);
224  }
225 
226  if (!VRBase && !IsClone && !IsCloned)
227  for (SDNode *User : Node->uses()) {
228  if (User->getOpcode() == ISD::CopyToReg &&
229  User->getOperand(2).getNode() == Node &&
230  User->getOperand(2).getResNo() == i) {
231  unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
232  if (Register::isVirtualRegister(Reg)) {
233  const TargetRegisterClass *RegRC = MRI->getRegClass(Reg);
234  if (RegRC == RC) {
235  VRBase = Reg;
236  MIB.addReg(VRBase, RegState::Define);
237  break;
238  }
239  }
240  }
241  }
242 
243  // Create the result registers for this node and add the result regs to
244  // the machine instruction.
245  if (VRBase == 0) {
246  assert(RC && "Isn't a register operand!");
247  VRBase = MRI->createVirtualRegister(RC);
248  MIB.addReg(VRBase, RegState::Define);
249  }
250 
251  // If this def corresponds to a result of the SDNode insert the VRBase into
252  // the lookup map.
253  if (i < NumResults) {
254  SDValue Op(Node, i);
255  if (IsClone)
256  VRBaseMap.erase(Op);
257  bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
258  (void)isNew; // Silence compiler warning.
259  assert(isNew && "Node emitted out of order - early");
260  }
261  }
262 }
263 
264 /// getVR - Return the virtual register corresponding to the specified result
265 /// of the specified node.
266 unsigned InstrEmitter::getVR(SDValue Op,
267  DenseMap<SDValue, unsigned> &VRBaseMap) {
268  if (Op.isMachineOpcode() &&
269  Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) {
270  // Add an IMPLICIT_DEF instruction before every use.
271  // IMPLICIT_DEF can produce any type of result so its MCInstrDesc
272  // does not include operand register class info.
273  const TargetRegisterClass *RC = TLI->getRegClassFor(
274  Op.getSimpleValueType(), Op.getNode()->isDivergent());
275  Register VReg = MRI->createVirtualRegister(RC);
276  BuildMI(*MBB, InsertPos, Op.getDebugLoc(),
277  TII->get(TargetOpcode::IMPLICIT_DEF), VReg);
278  return VReg;
279  }
280 
282  assert(I != VRBaseMap.end() && "Node emitted out of order - late");
283  return I->second;
284 }
285 
286 
287 /// AddRegisterOperand - Add the specified register as an operand to the
288 /// specified machine instr. Insert register copies if the register is
289 /// not in the required register class.
290 void
291 InstrEmitter::AddRegisterOperand(MachineInstrBuilder &MIB,
292  SDValue Op,
293  unsigned IIOpNum,
294  const MCInstrDesc *II,
295  DenseMap<SDValue, unsigned> &VRBaseMap,
296  bool IsDebug, bool IsClone, bool IsCloned) {
297  assert(Op.getValueType() != MVT::Other &&
298  Op.getValueType() != MVT::Glue &&
299  "Chain and glue operands should occur at end of operand list!");
300  // Get/emit the operand.
301  unsigned VReg = getVR(Op, VRBaseMap);
302 
303  const MCInstrDesc &MCID = MIB->getDesc();
304  bool isOptDef = IIOpNum < MCID.getNumOperands() &&
305  MCID.OpInfo[IIOpNum].isOptionalDef();
306 
307  // If the instruction requires a register in a different class, create
308  // a new virtual register and copy the value into it, but first attempt to
309  // shrink VReg's register class within reason. For example, if VReg == GR32
310  // and II requires a GR32_NOSP, just constrain VReg to GR32_NOSP.
311  if (II) {
312  const TargetRegisterClass *OpRC = nullptr;
313  if (IIOpNum < II->getNumOperands())
314  OpRC = TII->getRegClass(*II, IIOpNum, TRI, *MF);
315 
316  if (OpRC) {
317  const TargetRegisterClass *ConstrainedRC
318  = MRI->constrainRegClass(VReg, OpRC, MinRCSize);
319  if (!ConstrainedRC) {
320  OpRC = TRI->getAllocatableClass(OpRC);
321  assert(OpRC && "Constraints cannot be fulfilled for allocation");
322  Register NewVReg = MRI->createVirtualRegister(OpRC);
323  BuildMI(*MBB, InsertPos, Op.getNode()->getDebugLoc(),
324  TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg);
325  VReg = NewVReg;
326  } else {
327  assert(ConstrainedRC->isAllocatable() &&
328  "Constraining an allocatable VReg produced an unallocatable class?");
329  }
330  }
331  }
332 
333  // If this value has only one use, that use is a kill. This is a
334  // conservative approximation. InstrEmitter does trivial coalescing
335  // with CopyFromReg nodes, so don't emit kill flags for them.
336  // Avoid kill flags on Schedule cloned nodes, since there will be
337  // multiple uses.
338  // Tied operands are never killed, so we need to check that. And that
339  // means we need to determine the index of the operand.
340  bool isKill = Op.hasOneUse() &&
341  Op.getNode()->getOpcode() != ISD::CopyFromReg &&
342  !IsDebug &&
343  !(IsClone || IsCloned);
344  if (isKill) {
345  unsigned Idx = MIB->getNumOperands();
346  while (Idx > 0 &&
347  MIB->getOperand(Idx-1).isReg() &&
348  MIB->getOperand(Idx-1).isImplicit())
349  --Idx;
350  bool isTied = MCID.getOperandConstraint(Idx, MCOI::TIED_TO) != -1;
351  if (isTied)
352  isKill = false;
353  }
354 
355  MIB.addReg(VReg, getDefRegState(isOptDef) | getKillRegState(isKill) |
356  getDebugRegState(IsDebug));
357 }
358 
359 /// AddOperand - Add the specified operand to the specified machine instr. II
360 /// specifies the instruction information for the node, and IIOpNum is the
361 /// operand number (in the II) that we are adding.
362 void InstrEmitter::AddOperand(MachineInstrBuilder &MIB,
363  SDValue Op,
364  unsigned IIOpNum,
365  const MCInstrDesc *II,
366  DenseMap<SDValue, unsigned> &VRBaseMap,
367  bool IsDebug, bool IsClone, bool IsCloned) {
368  if (Op.isMachineOpcode()) {
369  AddRegisterOperand(MIB, Op, IIOpNum, II, VRBaseMap,
370  IsDebug, IsClone, IsCloned);
371  } else if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
372  MIB.addImm(C->getSExtValue());
373  } else if (ConstantFPSDNode *F = dyn_cast<ConstantFPSDNode>(Op)) {
374  MIB.addFPImm(F->getConstantFPValue());
375  } else if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Op)) {
376  unsigned VReg = R->getReg();
377  MVT OpVT = Op.getSimpleValueType();
378  const TargetRegisterClass *IIRC =
379  II ? TRI->getAllocatableClass(TII->getRegClass(*II, IIOpNum, TRI, *MF))
380  : nullptr;
381  const TargetRegisterClass *OpRC =
382  TLI->isTypeLegal(OpVT)
383  ? TLI->getRegClassFor(OpVT,
384  Op.getNode()->isDivergent() ||
385  (IIRC && TRI->isDivergentRegClass(IIRC)))
386  : nullptr;
387 
388  if (OpRC && IIRC && OpRC != IIRC && Register::isVirtualRegister(VReg)) {
389  Register NewVReg = MRI->createVirtualRegister(IIRC);
390  BuildMI(*MBB, InsertPos, Op.getNode()->getDebugLoc(),
391  TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg);
392  VReg = NewVReg;
393  }
394  // Turn additional physreg operands into implicit uses on non-variadic
395  // instructions. This is used by call and return instructions passing
396  // arguments in registers.
397  bool Imp = II && (IIOpNum >= II->getNumOperands() && !II->isVariadic());
398  MIB.addReg(VReg, getImplRegState(Imp));
399  } else if (RegisterMaskSDNode *RM = dyn_cast<RegisterMaskSDNode>(Op)) {
400  MIB.addRegMask(RM->getRegMask());
401  } else if (GlobalAddressSDNode *TGA = dyn_cast<GlobalAddressSDNode>(Op)) {
402  MIB.addGlobalAddress(TGA->getGlobal(), TGA->getOffset(),
403  TGA->getTargetFlags());
404  } else if (BasicBlockSDNode *BBNode = dyn_cast<BasicBlockSDNode>(Op)) {
405  MIB.addMBB(BBNode->getBasicBlock());
406  } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Op)) {
407  MIB.addFrameIndex(FI->getIndex());
408  } else if (JumpTableSDNode *JT = dyn_cast<JumpTableSDNode>(Op)) {
409  MIB.addJumpTableIndex(JT->getIndex(), JT->getTargetFlags());
410  } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op)) {
411  int Offset = CP->getOffset();
412  unsigned Align = CP->getAlignment();
413  Type *Type = CP->getType();
414  // MachineConstantPool wants an explicit alignment.
415  if (Align == 0) {
416  Align = MF->getDataLayout().getPrefTypeAlignment(Type);
417  if (Align == 0) {
418  // Alignment of vector types. FIXME!
419  Align = MF->getDataLayout().getTypeAllocSize(Type);
420  }
421  }
422 
423  unsigned Idx;
425  if (CP->isMachineConstantPoolEntry())
426  Idx = MCP->getConstantPoolIndex(CP->getMachineCPVal(), Align);
427  else
428  Idx = MCP->getConstantPoolIndex(CP->getConstVal(), Align);
429  MIB.addConstantPoolIndex(Idx, Offset, CP->getTargetFlags());
430  } else if (ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op)) {
431  MIB.addExternalSymbol(ES->getSymbol(), ES->getTargetFlags());
432  } else if (auto *SymNode = dyn_cast<MCSymbolSDNode>(Op)) {
433  MIB.addSym(SymNode->getMCSymbol());
434  } else if (BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(Op)) {
435  MIB.addBlockAddress(BA->getBlockAddress(),
436  BA->getOffset(),
437  BA->getTargetFlags());
438  } else if (TargetIndexSDNode *TI = dyn_cast<TargetIndexSDNode>(Op)) {
439  MIB.addTargetIndex(TI->getIndex(), TI->getOffset(), TI->getTargetFlags());
440  } else {
441  assert(Op.getValueType() != MVT::Other &&
442  Op.getValueType() != MVT::Glue &&
443  "Chain and glue operands should occur at end of operand list!");
444  AddRegisterOperand(MIB, Op, IIOpNum, II, VRBaseMap,
445  IsDebug, IsClone, IsCloned);
446  }
447 }
448 
449 unsigned InstrEmitter::ConstrainForSubReg(unsigned VReg, unsigned SubIdx,
450  MVT VT, bool isDivergent, const DebugLoc &DL) {
451  const TargetRegisterClass *VRC = MRI->getRegClass(VReg);
452  const TargetRegisterClass *RC = TRI->getSubClassWithSubReg(VRC, SubIdx);
453 
454  // RC is a sub-class of VRC that supports SubIdx. Try to constrain VReg
455  // within reason.
456  if (RC && RC != VRC)
457  RC = MRI->constrainRegClass(VReg, RC, MinRCSize);
458 
459  // VReg has been adjusted. It can be used with SubIdx operands now.
460  if (RC)
461  return VReg;
462 
463  // VReg couldn't be reasonably constrained. Emit a COPY to a new virtual
464  // register instead.
465  RC = TRI->getSubClassWithSubReg(TLI->getRegClassFor(VT, isDivergent), SubIdx);
466  assert(RC && "No legal register class for VT supports that SubIdx");
467  Register NewReg = MRI->createVirtualRegister(RC);
468  BuildMI(*MBB, InsertPos, DL, TII->get(TargetOpcode::COPY), NewReg)
469  .addReg(VReg);
470  return NewReg;
471 }
472 
473 /// EmitSubregNode - Generate machine code for subreg nodes.
474 ///
475 void InstrEmitter::EmitSubregNode(SDNode *Node,
476  DenseMap<SDValue, unsigned> &VRBaseMap,
477  bool IsClone, bool IsCloned) {
478  unsigned VRBase = 0;
479  unsigned Opc = Node->getMachineOpcode();
480 
481  // If the node is only used by a CopyToReg and the dest reg is a vreg, use
482  // the CopyToReg'd destination register instead of creating a new vreg.
483  for (SDNode *User : Node->uses()) {
484  if (User->getOpcode() == ISD::CopyToReg &&
485  User->getOperand(2).getNode() == Node) {
486  unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
487  if (Register::isVirtualRegister(DestReg)) {
488  VRBase = DestReg;
489  break;
490  }
491  }
492  }
493 
494  if (Opc == TargetOpcode::EXTRACT_SUBREG) {
495  // EXTRACT_SUBREG is lowered as %dst = COPY %src:sub. There are no
496  // constraints on the %dst register, COPY can target all legal register
497  // classes.
498  unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
499  const TargetRegisterClass *TRC =
500  TLI->getRegClassFor(Node->getSimpleValueType(0), Node->isDivergent());
501 
502  unsigned Reg;
505  if (R && Register::isPhysicalRegister(R->getReg())) {
506  Reg = R->getReg();
507  DefMI = nullptr;
508  } else {
509  Reg = R ? R->getReg() : getVR(Node->getOperand(0), VRBaseMap);
510  DefMI = MRI->getVRegDef(Reg);
511  }
512 
513  unsigned SrcReg, DstReg, DefSubIdx;
514  if (DefMI &&
515  TII->isCoalescableExtInstr(*DefMI, SrcReg, DstReg, DefSubIdx) &&
516  SubIdx == DefSubIdx &&
517  TRC == MRI->getRegClass(SrcReg)) {
518  // Optimize these:
519  // r1025 = s/zext r1024, 4
520  // r1026 = extract_subreg r1025, 4
521  // to a copy
522  // r1026 = copy r1024
523  VRBase = MRI->createVirtualRegister(TRC);
524  BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
525  TII->get(TargetOpcode::COPY), VRBase).addReg(SrcReg);
526  MRI->clearKillFlags(SrcReg);
527  } else {
528  // Reg may not support a SubIdx sub-register, and we may need to
529  // constrain its register class or issue a COPY to a compatible register
530  // class.
532  Reg = ConstrainForSubReg(Reg, SubIdx,
533  Node->getOperand(0).getSimpleValueType(),
534  Node->isDivergent(), Node->getDebugLoc());
535  // Create the destreg if it is missing.
536  if (VRBase == 0)
537  VRBase = MRI->createVirtualRegister(TRC);
538 
539  // Create the extract_subreg machine instruction.
540  MachineInstrBuilder CopyMI =
541  BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
542  TII->get(TargetOpcode::COPY), VRBase);
544  CopyMI.addReg(Reg, 0, SubIdx);
545  else
546  CopyMI.addReg(TRI->getSubReg(Reg, SubIdx));
547  }
548  } else if (Opc == TargetOpcode::INSERT_SUBREG ||
549  Opc == TargetOpcode::SUBREG_TO_REG) {
550  SDValue N0 = Node->getOperand(0);
551  SDValue N1 = Node->getOperand(1);
552  SDValue N2 = Node->getOperand(2);
553  unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue();
554 
555  // Figure out the register class to create for the destreg. It should be
556  // the largest legal register class supporting SubIdx sub-registers.
557  // RegisterCoalescer will constrain it further if it decides to eliminate
558  // the INSERT_SUBREG instruction.
559  //
560  // %dst = INSERT_SUBREG %src, %sub, SubIdx
561  //
562  // is lowered by TwoAddressInstructionPass to:
563  //
564  // %dst = COPY %src
565  // %dst:SubIdx = COPY %sub
566  //
567  // There is no constraint on the %src register class.
568  //
569  const TargetRegisterClass *SRC =
570  TLI->getRegClassFor(Node->getSimpleValueType(0), Node->isDivergent());
571  SRC = TRI->getSubClassWithSubReg(SRC, SubIdx);
572  assert(SRC && "No register class supports VT and SubIdx for INSERT_SUBREG");
573 
574  if (VRBase == 0 || !SRC->hasSubClassEq(MRI->getRegClass(VRBase)))
575  VRBase = MRI->createVirtualRegister(SRC);
576 
577  // Create the insert_subreg or subreg_to_reg machine instruction.
578  MachineInstrBuilder MIB =
579  BuildMI(*MF, Node->getDebugLoc(), TII->get(Opc), VRBase);
580 
581  // If creating a subreg_to_reg, then the first input operand
582  // is an implicit value immediate, otherwise it's a register
583  if (Opc == TargetOpcode::SUBREG_TO_REG) {
584  const ConstantSDNode *SD = cast<ConstantSDNode>(N0);
585  MIB.addImm(SD->getZExtValue());
586  } else
587  AddOperand(MIB, N0, 0, nullptr, VRBaseMap, /*IsDebug=*/false,
588  IsClone, IsCloned);
589  // Add the subregister being inserted
590  AddOperand(MIB, N1, 0, nullptr, VRBaseMap, /*IsDebug=*/false,
591  IsClone, IsCloned);
592  MIB.addImm(SubIdx);
593  MBB->insert(InsertPos, MIB);
594  } else
595  llvm_unreachable("Node is not insert_subreg, extract_subreg, or subreg_to_reg");
596 
597  SDValue Op(Node, 0);
598  bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
599  (void)isNew; // Silence compiler warning.
600  assert(isNew && "Node emitted out of order - early");
601 }
602 
603 /// EmitCopyToRegClassNode - Generate machine code for COPY_TO_REGCLASS nodes.
604 /// COPY_TO_REGCLASS is just a normal copy, except that the destination
605 /// register is constrained to be in a particular register class.
606 ///
607 void
608 InstrEmitter::EmitCopyToRegClassNode(SDNode *Node,
609  DenseMap<SDValue, unsigned> &VRBaseMap) {
610  unsigned VReg = getVR(Node->getOperand(0), VRBaseMap);
611 
612  // Create the new VReg in the destination class and emit a copy.
613  unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
614  const TargetRegisterClass *DstRC =
615  TRI->getAllocatableClass(TRI->getRegClass(DstRCIdx));
616  Register NewVReg = MRI->createVirtualRegister(DstRC);
617  BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
618  NewVReg).addReg(VReg);
619 
620  SDValue Op(Node, 0);
621  bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second;
622  (void)isNew; // Silence compiler warning.
623  assert(isNew && "Node emitted out of order - early");
624 }
625 
626 /// EmitRegSequence - Generate machine code for REG_SEQUENCE nodes.
627 ///
628 void InstrEmitter::EmitRegSequence(SDNode *Node,
629  DenseMap<SDValue, unsigned> &VRBaseMap,
630  bool IsClone, bool IsCloned) {
631  unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue();
632  const TargetRegisterClass *RC = TRI->getRegClass(DstRCIdx);
633  Register NewVReg = MRI->createVirtualRegister(TRI->getAllocatableClass(RC));
634  const MCInstrDesc &II = TII->get(TargetOpcode::REG_SEQUENCE);
635  MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(), II, NewVReg);
636  unsigned NumOps = Node->getNumOperands();
637  // If the input pattern has a chain, then the root of the corresponding
638  // output pattern will get a chain as well. This can happen to be a
639  // REG_SEQUENCE (which is not "guarded" by countOperands/CountResults).
640  if (NumOps && Node->getOperand(NumOps-1).getValueType() == MVT::Other)
641  --NumOps; // Ignore chain if it exists.
642 
643  assert((NumOps & 1) == 1 &&
644  "REG_SEQUENCE must have an odd number of operands!");
645  for (unsigned i = 1; i != NumOps; ++i) {
646  SDValue Op = Node->getOperand(i);
647  if ((i & 1) == 0) {
649  // Skip physical registers as they don't have a vreg to get and we'll
650  // insert copies for them in TwoAddressInstructionPass anyway.
651  if (!R || !Register::isPhysicalRegister(R->getReg())) {
652  unsigned SubIdx = cast<ConstantSDNode>(Op)->getZExtValue();
653  unsigned SubReg = getVR(Node->getOperand(i-1), VRBaseMap);
654  const TargetRegisterClass *TRC = MRI->getRegClass(SubReg);
655  const TargetRegisterClass *SRC =
656  TRI->getMatchingSuperRegClass(RC, TRC, SubIdx);
657  if (SRC && SRC != RC) {
658  MRI->setRegClass(NewVReg, SRC);
659  RC = SRC;
660  }
661  }
662  }
663  AddOperand(MIB, Op, i+1, &II, VRBaseMap, /*IsDebug=*/false,
664  IsClone, IsCloned);
665  }
666 
667  MBB->insert(InsertPos, MIB);
668  SDValue Op(Node, 0);
669  bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second;
670  (void)isNew; // Silence compiler warning.
671  assert(isNew && "Node emitted out of order - early");
672 }
673 
674 /// EmitDbgValue - Generate machine instruction for a dbg_value node.
675 ///
676 MachineInstr *
678  DenseMap<SDValue, unsigned> &VRBaseMap) {
679  MDNode *Var = SD->getVariable();
680  MDNode *Expr = SD->getExpression();
681  DebugLoc DL = SD->getDebugLoc();
682  assert(cast<DILocalVariable>(Var)->isValidLocationForIntrinsic(DL) &&
683  "Expected inlined-at fields to agree");
684 
685  SD->setIsEmitted();
686 
687  if (SD->isInvalidated()) {
688  // An invalidated SDNode must generate an undef DBG_VALUE: although the
689  // original value is no longer computed, earlier DBG_VALUEs live ranges
690  // must not leak into later code.
691  auto MIB = BuildMI(*MF, DL, TII->get(TargetOpcode::DBG_VALUE));
692  MIB.addReg(0U);
693  MIB.addReg(0U, RegState::Debug);
694  MIB.addMetadata(Var);
695  MIB.addMetadata(Expr);
696  return &*MIB;
697  }
698 
699  if (SD->getKind() == SDDbgValue::FRAMEIX) {
700  // Stack address; this needs to be lowered in target-dependent fashion.
701  // EmitTargetCodeForFrameDebugValue is responsible for allocation.
702  auto FrameMI = BuildMI(*MF, DL, TII->get(TargetOpcode::DBG_VALUE))
703  .addFrameIndex(SD->getFrameIx());
704  if (SD->isIndirect())
705  // Push [fi + 0] onto the DIExpression stack.
706  FrameMI.addImm(0);
707  else
708  // Push fi onto the DIExpression stack.
709  FrameMI.addReg(0);
710  return FrameMI.addMetadata(Var).addMetadata(Expr);
711  }
712  // Otherwise, we're going to create an instruction here.
713  const MCInstrDesc &II = TII->get(TargetOpcode::DBG_VALUE);
714  MachineInstrBuilder MIB = BuildMI(*MF, DL, II);
715  if (SD->getKind() == SDDbgValue::SDNODE) {
716  SDNode *Node = SD->getSDNode();
717  SDValue Op = SDValue(Node, SD->getResNo());
718  // It's possible we replaced this SDNode with other(s) and therefore
719  // didn't generate code for it. It's better to catch these cases where
720  // they happen and transfer the debug info, but trying to guarantee that
721  // in all cases would be very fragile; this is a safeguard for any
722  // that were missed.
724  if (I==VRBaseMap.end())
725  MIB.addReg(0U); // undef
726  else
727  AddOperand(MIB, Op, (*MIB).getNumOperands(), &II, VRBaseMap,
728  /*IsDebug=*/true, /*IsClone=*/false, /*IsCloned=*/false);
729  } else if (SD->getKind() == SDDbgValue::VREG) {
730  MIB.addReg(SD->getVReg(), RegState::Debug);
731  } else if (SD->getKind() == SDDbgValue::CONST) {
732  const Value *V = SD->getConst();
733  if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
734  if (CI->getBitWidth() > 64)
735  MIB.addCImm(CI);
736  else
737  MIB.addImm(CI->getSExtValue());
738  } else if (const ConstantFP *CF = dyn_cast<ConstantFP>(V)) {
739  MIB.addFPImm(CF);
740  } else if (isa<ConstantPointerNull>(V)) {
741  // Note: This assumes that all nullptr constants are zero-valued.
742  MIB.addImm(0);
743  } else {
744  // Could be an Undef. In any case insert an Undef so we can see what we
745  // dropped.
746  MIB.addReg(0U);
747  }
748  } else {
749  // Insert an Undef so we can see what we dropped.
750  MIB.addReg(0U);
751  }
752 
753  // Indirect addressing is indicated by an Imm as the second parameter.
754  if (SD->isIndirect())
755  MIB.addImm(0U);
756  else
757  MIB.addReg(0U, RegState::Debug);
758 
759  MIB.addMetadata(Var);
760  MIB.addMetadata(Expr);
761 
762  return &*MIB;
763 }
764 
765 MachineInstr *
767  MDNode *Label = SD->getLabel();
768  DebugLoc DL = SD->getDebugLoc();
769  assert(cast<DILabel>(Label)->isValidLocationForIntrinsic(DL) &&
770  "Expected inlined-at fields to agree");
771 
772  const MCInstrDesc &II = TII->get(TargetOpcode::DBG_LABEL);
773  MachineInstrBuilder MIB = BuildMI(*MF, DL, II);
774  MIB.addMetadata(Label);
775 
776  return &*MIB;
777 }
778 
779 /// EmitMachineNode - Generate machine code for a target-specific node and
780 /// needed dependencies.
781 ///
782 void InstrEmitter::
783 EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned,
784  DenseMap<SDValue, unsigned> &VRBaseMap) {
785  unsigned Opc = Node->getMachineOpcode();
786 
787  // Handle subreg insert/extract specially
788  if (Opc == TargetOpcode::EXTRACT_SUBREG ||
789  Opc == TargetOpcode::INSERT_SUBREG ||
790  Opc == TargetOpcode::SUBREG_TO_REG) {
791  EmitSubregNode(Node, VRBaseMap, IsClone, IsCloned);
792  return;
793  }
794 
795  // Handle COPY_TO_REGCLASS specially.
796  if (Opc == TargetOpcode::COPY_TO_REGCLASS) {
797  EmitCopyToRegClassNode(Node, VRBaseMap);
798  return;
799  }
800 
801  // Handle REG_SEQUENCE specially.
802  if (Opc == TargetOpcode::REG_SEQUENCE) {
803  EmitRegSequence(Node, VRBaseMap, IsClone, IsCloned);
804  return;
805  }
806 
807  if (Opc == TargetOpcode::IMPLICIT_DEF)
808  // We want a unique VR for each IMPLICIT_DEF use.
809  return;
810 
811  const MCInstrDesc &II = TII->get(Opc);
812  unsigned NumResults = CountResults(Node);
813  unsigned NumDefs = II.getNumDefs();
814  const MCPhysReg *ScratchRegs = nullptr;
815 
816  // Handle STACKMAP and PATCHPOINT specially and then use the generic code.
817  if (Opc == TargetOpcode::STACKMAP || Opc == TargetOpcode::PATCHPOINT) {
818  // Stackmaps do not have arguments and do not preserve their calling
819  // convention. However, to simplify runtime support, they clobber the same
820  // scratch registers as AnyRegCC.
821  unsigned CC = CallingConv::AnyReg;
822  if (Opc == TargetOpcode::PATCHPOINT) {
824  NumDefs = NumResults;
825  }
826  ScratchRegs = TLI->getScratchRegisters((CallingConv::ID) CC);
827  }
828 
829  unsigned NumImpUses = 0;
830  unsigned NodeOperands =
831  countOperands(Node, II.getNumOperands() - NumDefs, NumImpUses);
832  bool HasPhysRegOuts = NumResults > NumDefs && II.getImplicitDefs()!=nullptr;
833 #ifndef NDEBUG
834  unsigned NumMIOperands = NodeOperands + NumResults;
835  if (II.isVariadic())
836  assert(NumMIOperands >= II.getNumOperands() &&
837  "Too few operands for a variadic node!");
838  else
839  assert(NumMIOperands >= II.getNumOperands() &&
840  NumMIOperands <= II.getNumOperands() + II.getNumImplicitDefs() +
841  NumImpUses &&
842  "#operands for dag node doesn't match .td file!");
843 #endif
844 
845  // Create the new machine instruction.
846  MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(), II);
847 
848  // Add result register values for things that are defined by this
849  // instruction.
850  if (NumResults) {
851  CreateVirtualRegisters(Node, MIB, II, IsClone, IsCloned, VRBaseMap);
852 
853  // Transfer any IR flags from the SDNode to the MachineInstr
854  MachineInstr *MI = MIB.getInstr();
855  const SDNodeFlags Flags = Node->getFlags();
856  if (Flags.hasNoSignedZeros())
857  MI->setFlag(MachineInstr::MIFlag::FmNsz);
858 
859  if (Flags.hasAllowReciprocal())
860  MI->setFlag(MachineInstr::MIFlag::FmArcp);
861 
862  if (Flags.hasNoNaNs())
863  MI->setFlag(MachineInstr::MIFlag::FmNoNans);
864 
865  if (Flags.hasNoInfs())
866  MI->setFlag(MachineInstr::MIFlag::FmNoInfs);
867 
868  if (Flags.hasAllowContract())
869  MI->setFlag(MachineInstr::MIFlag::FmContract);
870 
871  if (Flags.hasApproximateFuncs())
872  MI->setFlag(MachineInstr::MIFlag::FmAfn);
873 
874  if (Flags.hasAllowReassociation())
875  MI->setFlag(MachineInstr::MIFlag::FmReassoc);
876 
877  if (Flags.hasNoUnsignedWrap())
878  MI->setFlag(MachineInstr::MIFlag::NoUWrap);
879 
880  if (Flags.hasNoSignedWrap())
881  MI->setFlag(MachineInstr::MIFlag::NoSWrap);
882 
883  if (Flags.hasExact())
884  MI->setFlag(MachineInstr::MIFlag::IsExact);
885 
886  if (Flags.hasFPExcept())
887  MI->setFlag(MachineInstr::MIFlag::FPExcept);
888  }
889 
890  // Emit all of the actual operands of this instruction, adding them to the
891  // instruction as appropriate.
892  bool HasOptPRefs = NumDefs > NumResults;
893  assert((!HasOptPRefs || !HasPhysRegOuts) &&
894  "Unable to cope with optional defs and phys regs defs!");
895  unsigned NumSkip = HasOptPRefs ? NumDefs - NumResults : 0;
896  for (unsigned i = NumSkip; i != NodeOperands; ++i)
897  AddOperand(MIB, Node->getOperand(i), i-NumSkip+NumDefs, &II,
898  VRBaseMap, /*IsDebug=*/false, IsClone, IsCloned);
899 
900  // Add scratch registers as implicit def and early clobber
901  if (ScratchRegs)
902  for (unsigned i = 0; ScratchRegs[i]; ++i)
903  MIB.addReg(ScratchRegs[i], RegState::ImplicitDefine |
905 
906  // Set the memory reference descriptions of this instruction now that it is
907  // part of the function.
908  MIB.setMemRefs(cast<MachineSDNode>(Node)->memoperands());
909 
910  // Insert the instruction into position in the block. This needs to
911  // happen before any custom inserter hook is called so that the
912  // hook knows where in the block to insert the replacement code.
913  MBB->insert(InsertPos, MIB);
914 
915  // The MachineInstr may also define physregs instead of virtregs. These
916  // physreg values can reach other instructions in different ways:
917  //
918  // 1. When there is a use of a Node value beyond the explicitly defined
919  // virtual registers, we emit a CopyFromReg for one of the implicitly
920  // defined physregs. This only happens when HasPhysRegOuts is true.
921  //
922  // 2. A CopyFromReg reading a physreg may be glued to this instruction.
923  //
924  // 3. A glued instruction may implicitly use a physreg.
925  //
926  // 4. A glued instruction may use a RegisterSDNode operand.
927  //
928  // Collect all the used physreg defs, and make sure that any unused physreg
929  // defs are marked as dead.
930  SmallVector<Register, 8> UsedRegs;
931 
932  // Additional results must be physical register defs.
933  if (HasPhysRegOuts) {
934  for (unsigned i = NumDefs; i < NumResults; ++i) {
935  Register Reg = II.getImplicitDefs()[i - NumDefs];
936  if (!Node->hasAnyUseOfValue(i))
937  continue;
938  // This implicitly defined physreg has a use.
939  UsedRegs.push_back(Reg);
940  EmitCopyFromReg(Node, i, IsClone, IsCloned, Reg, VRBaseMap);
941  }
942  }
943 
944  // Scan the glue chain for any used physregs.
945  if (Node->getValueType(Node->getNumValues()-1) == MVT::Glue) {
946  for (SDNode *F = Node->getGluedUser(); F; F = F->getGluedUser()) {
947  if (F->getOpcode() == ISD::CopyFromReg) {
948  UsedRegs.push_back(cast<RegisterSDNode>(F->getOperand(1))->getReg());
949  continue;
950  } else if (F->getOpcode() == ISD::CopyToReg) {
951  // Skip CopyToReg nodes that are internal to the glue chain.
952  continue;
953  }
954  // Collect declared implicit uses.
955  const MCInstrDesc &MCID = TII->get(F->getMachineOpcode());
956  UsedRegs.append(MCID.getImplicitUses(),
957  MCID.getImplicitUses() + MCID.getNumImplicitUses());
958  // In addition to declared implicit uses, we must also check for
959  // direct RegisterSDNode operands.
960  for (unsigned i = 0, e = F->getNumOperands(); i != e; ++i)
961  if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(F->getOperand(i))) {
962  Register Reg = R->getReg();
963  if (Reg.isPhysical())
964  UsedRegs.push_back(Reg);
965  }
966  }
967  }
968 
969  // Finally mark unused registers as dead.
970  if (!UsedRegs.empty() || II.getImplicitDefs() || II.hasOptionalDef())
971  MIB->setPhysRegsDeadExcept(UsedRegs, *TRI);
972 
973  // Run post-isel target hook to adjust this instruction if needed.
974  if (II.hasPostISelHook())
975  TLI->AdjustInstrPostInstrSelection(*MIB, Node);
976 }
977 
978 /// EmitSpecialNode - Generate machine code for a target-independent node and
979 /// needed dependencies.
980 void InstrEmitter::
981 EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned,
982  DenseMap<SDValue, unsigned> &VRBaseMap) {
983  switch (Node->getOpcode()) {
984  default:
985 #ifndef NDEBUG
986  Node->dump();
987 #endif
988  llvm_unreachable("This target-independent node should have been selected!");
989  case ISD::EntryToken:
990  llvm_unreachable("EntryToken should have been excluded from the schedule!");
991  case ISD::MERGE_VALUES:
992  case ISD::TokenFactor: // fall thru
993  break;
994  case ISD::CopyToReg: {
995  unsigned DestReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
996  SDValue SrcVal = Node->getOperand(2);
997  if (Register::isVirtualRegister(DestReg) && SrcVal.isMachineOpcode() &&
998  SrcVal.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) {
999  // Instead building a COPY to that vreg destination, build an
1000  // IMPLICIT_DEF instruction instead.
1001  BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
1002  TII->get(TargetOpcode::IMPLICIT_DEF), DestReg);
1003  break;
1004  }
1005  unsigned SrcReg;
1006  if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(SrcVal))
1007  SrcReg = R->getReg();
1008  else
1009  SrcReg = getVR(SrcVal, VRBaseMap);
1010 
1011  if (SrcReg == DestReg) // Coalesced away the copy? Ignore.
1012  break;
1013 
1014  BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
1015  DestReg).addReg(SrcReg);
1016  break;
1017  }
1018  case ISD::CopyFromReg: {
1019  unsigned SrcReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
1020  EmitCopyFromReg(Node, 0, IsClone, IsCloned, SrcReg, VRBaseMap);
1021  break;
1022  }
1023  case ISD::EH_LABEL:
1024  case ISD::ANNOTATION_LABEL: {
1025  unsigned Opc = (Node->getOpcode() == ISD::EH_LABEL)
1028  MCSymbol *S = cast<LabelSDNode>(Node)->getLabel();
1029  BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
1030  TII->get(Opc)).addSym(S);
1031  break;
1032  }
1033 
1034  case ISD::LIFETIME_START:
1035  case ISD::LIFETIME_END: {
1036  unsigned TarOp = (Node->getOpcode() == ISD::LIFETIME_START) ?
1038 
1040  BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TarOp))
1041  .addFrameIndex(FI->getIndex());
1042  break;
1043  }
1044 
1045  case ISD::INLINEASM:
1046  case ISD::INLINEASM_BR: {
1047  unsigned NumOps = Node->getNumOperands();
1048  if (Node->getOperand(NumOps-1).getValueType() == MVT::Glue)
1049  --NumOps; // Ignore the glue operand.
1050 
1051  // Create the inline asm machine instruction.
1052  unsigned TgtOpc = Node->getOpcode() == ISD::INLINEASM_BR
1055  MachineInstrBuilder MIB =
1056  BuildMI(*MF, Node->getDebugLoc(), TII->get(TgtOpc));
1057 
1058  // Add the asm string as an external symbol operand.
1059  SDValue AsmStrV = Node->getOperand(InlineAsm::Op_AsmString);
1060  const char *AsmStr = cast<ExternalSymbolSDNode>(AsmStrV)->getSymbol();
1061  MIB.addExternalSymbol(AsmStr);
1062 
1063  // Add the HasSideEffect, isAlignStack, AsmDialect, MayLoad and MayStore
1064  // bits.
1065  int64_t ExtraInfo =
1066  cast<ConstantSDNode>(Node->getOperand(InlineAsm::Op_ExtraInfo))->
1067  getZExtValue();
1068  MIB.addImm(ExtraInfo);
1069 
1070  // Remember to operand index of the group flags.
1071  SmallVector<unsigned, 8> GroupIdx;
1072 
1073  // Remember registers that are part of early-clobber defs.
1074  SmallVector<unsigned, 8> ECRegs;
1075 
1076  // Add all of the operand registers to the instruction.
1077  for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
1078  unsigned Flags =
1079  cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue();
1080  const unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
1081 
1082  GroupIdx.push_back(MIB->getNumOperands());
1083  MIB.addImm(Flags);
1084  ++i; // Skip the ID value.
1085 
1086  switch (InlineAsm::getKind(Flags)) {
1087  default: llvm_unreachable("Bad flags!");
1089  for (unsigned j = 0; j != NumVals; ++j, ++i) {
1090  unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
1091  // FIXME: Add dead flags for physical and virtual registers defined.
1092  // For now, mark physical register defs as implicit to help fast
1093  // regalloc. This makes inline asm look a lot like calls.
1094  MIB.addReg(Reg,
1097  }
1098  break;
1101  for (unsigned j = 0; j != NumVals; ++j, ++i) {
1102  unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
1103  MIB.addReg(Reg,
1106  ECRegs.push_back(Reg);
1107  }
1108  break;
1109  case InlineAsm::Kind_RegUse: // Use of register.
1110  case InlineAsm::Kind_Imm: // Immediate.
1111  case InlineAsm::Kind_Mem: // Addressing mode.
1112  // The addressing mode has been selected, just add all of the
1113  // operands to the machine instruction.
1114  for (unsigned j = 0; j != NumVals; ++j, ++i)
1115  AddOperand(MIB, Node->getOperand(i), 0, nullptr, VRBaseMap,
1116  /*IsDebug=*/false, IsClone, IsCloned);
1117 
1118  // Manually set isTied bits.
1120  unsigned DefGroup = 0;
1121  if (InlineAsm::isUseOperandTiedToDef(Flags, DefGroup)) {
1122  unsigned DefIdx = GroupIdx[DefGroup] + 1;
1123  unsigned UseIdx = GroupIdx.back() + 1;
1124  for (unsigned j = 0; j != NumVals; ++j)
1125  MIB->tieOperands(DefIdx + j, UseIdx + j);
1126  }
1127  }
1128  break;
1129  }
1130  }
1131 
1132  // GCC inline assembly allows input operands to also be early-clobber
1133  // output operands (so long as the operand is written only after it's
1134  // used), but this does not match the semantics of our early-clobber flag.
1135  // If an early-clobber operand register is also an input operand register,
1136  // then remove the early-clobber flag.
1137  for (unsigned Reg : ECRegs) {
1138  if (MIB->readsRegister(Reg, TRI)) {
1139  MachineOperand *MO =
1140  MIB->findRegisterDefOperand(Reg, false, false, TRI);
1141  assert(MO && "No def operand for clobbered register?");
1142  MO->setIsEarlyClobber(false);
1143  }
1144  }
1145 
1146  // Get the mdnode from the asm if it exists and add it to the instruction.
1148  const MDNode *MD = cast<MDNodeSDNode>(MDV)->getMD();
1149  if (MD)
1150  MIB.addMetadata(MD);
1151 
1152  MBB->insert(InsertPos, MIB);
1153  break;
1154  }
1155  }
1156 }
1157 
1158 /// InstrEmitter - Construct an InstrEmitter and set it to start inserting
1159 /// at the given position in the given block.
1161  MachineBasicBlock::iterator insertpos)
1162  : MF(mbb->getParent()), MRI(&MF->getRegInfo()),
1163  TII(MF->getSubtarget().getInstrInfo()),
1164  TRI(MF->getSubtarget().getRegisterInfo()),
1165  TLI(MF->getSubtarget().getTargetLowering()), MBB(mbb),
1166  InsertPos(insertpos) {}
ANNOTATION_LABEL - Represents a mid basic block label used by annotations.
Definition: ISDOpcodes.h:710
uint64_t CallInst * C
unsigned getNumImplicitUses() const
Return the number of implicit uses this instruction has.
Definition: MCInstrDesc.h:551
const MachineInstrBuilder & addMetadata(const MDNode *MD) const
constexpr char Align[]
Key for Kernel::Arg::Metadata::mAlign.
EVT getValueType() const
Return the ValueType of the referenced return value.
The MachineConstantPool class keeps track of constants referenced by a function which must be spilled...
bool hasNoSignedZeros() const
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
InstrEmitter(MachineBasicBlock *mbb, MachineBasicBlock::iterator insertpos)
InstrEmitter - Construct an InstrEmitter and set it to start inserting at the given position in the g...
unsigned getNumImplicitDefs() const
Return the number of implicit defs this instruct has.
Definition: MCInstrDesc.h:573
This class represents lattice values for constants.
Definition: AllocatorList.h:23
SDNode * getSDNode() const
Returns the SDNode* for a register ref.
bool isInvalidated() const
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:63
const MCPhysReg * getImplicitUses() const
Return a list of registers that are potentially read by any instance of this machine instruction...
Definition: MCInstrDesc.h:548
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:179
void setIsEmitted()
setIsEmitted / isEmitted - Getter/Setter for flag indicating that this SDDbgValue has been emitted to...
unsigned Reg
const MachineInstrBuilder & addJumpTableIndex(unsigned Idx, unsigned TargetFlags=0) const
Completely target-dependent object reference.
const Value * getConst() const
Returns the Value* for a constant.
static unsigned CountResults(SDNode *Node)
CountResults - The results of target nodes have register or immediate operands first, then an optional chain, and optional flag operands (which do not go into the machine instrs.)
A debug info location.
Definition: DebugLoc.h:33
Metadata node.
Definition: Metadata.h:863
MVT getSimpleValueType(unsigned ResNo) const
Return the type of a specified result as a simple type.
F(f)
const SDNodeFlags getFlags() const
SDNode * getNode() const
get the SDNode which holds the desired result
const DebugLoc & getDebugLoc() const
Return the source location info.
EntryToken - This is the marker used to indicate the start of a region.
Definition: ISDOpcodes.h:44
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
static bool isUseOperandTiedToDef(unsigned Flag, unsigned &Idx)
isUseOperandTiedToDef - Return true if the flag of the inline asm operand indicates it is an use oper...
Definition: InlineAsm.h:342
bool hasOneUse() const
Return true if there is exactly one node using value ResNo of Node.
Value is a virtual register.
const DebugLoc & getDebugLoc() const
unsigned getResNo() const
Returns the ResNo for a register ref.
const TargetRegisterClass * getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
bool hasApproximateFuncs() const
unsigned getVReg() const
Returns the Virtual Register for a VReg.
const unsigned MinRCSize
MinRCSize - Smallest register class we allow when constraining virtual registers. ...
std::pair< iterator, bool > insert(const std::pair< KeyT, ValueT > &KV)
Definition: DenseMap.h:195
unsigned getFrameIx() const
Returns the FrameIx for a stack object.
This file declares the MachineConstantPool class which is an abstract constant pool to keep track of ...
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:226
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:414
virtual const TargetRegisterClass * getRegClass(const MCInstrDesc &MCID, unsigned OpNum, const TargetRegisterInfo *TRI, const MachineFunction &MF) const
Given a machine instruction descriptor, returns the register class constraint for OpNum...
CopyToReg - This node has three operands: a chain, a register number to set to this value...
Definition: ISDOpcodes.h:169
unsigned SubReg
virtual const TargetRegisterClass * getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const
Returns the largest legal sub-class of RC that supports the sub-register index Idx.
INLINEASM - Represents an inline asm block.
Definition: ISDOpcodes.h:696
MachineInstr * getVRegDef(unsigned Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
const MachineInstrBuilder & addConstantPoolIndex(unsigned Idx, int Offset=0, unsigned TargetFlags=0) const
void setIsEarlyClobber(bool Val=true)
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:408
Value is contents of a stack location.
virtual const TargetRegisterClass * getRegClassFor(MVT VT, bool isDivergent=false) const
Return the register class that should be used for the specified value type.
void clearKillFlags(unsigned Reg) const
clearKillFlags - Iterate over all the uses of the given register and clear the kill flag from the Mac...
Register getSubReg(MCRegister Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo...
DIVariable * getVariable() const
Returns the DIVariable pointer for the variable.
virtual bool isDivergentRegClass(const TargetRegisterClass *RC) const
Returns true if the register class is considered divergent.
const MachineInstrBuilder & addFPImm(const ConstantFP *Val) const
bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:95
const MachineInstrBuilder & addGlobalAddress(const GlobalValue *GV, int64_t Offset=0, unsigned TargetFlags=0) const
DbgValueKind getKind() const
Returns the kind.
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
bool isTypeLegalForClass(const TargetRegisterClass &RC, MVT T) const
Return true if the given TargetRegisterClass has the ValueType T.
const TargetRegisterClass * constrainRegClass(unsigned Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
Value * getOperand(unsigned i) const
Definition: User.h:169
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
unsigned getKillRegState(bool B)
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Definition: MCRegister.h:19
unsigned getDebugRegState(bool B)
bool hasAllowReciprocal() const
This corresponds to the llvm.lifetime.
Definition: ISDOpcodes.h:878
MVT getSimpleValueType() const
Return the simple ValueType of the referenced return value.
bool hasAllowContract() const
unsigned getDefRegState(bool B)
unsigned getNumValues() const
Return the number of values defined/returned by this operator.
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
const MCPhysReg * getImplicitDefs() const
Return a list of registers that are potentially written by any instance of this machine instruction...
Definition: MCInstrDesc.h:570
Machine Value Type.
const MachineInstrBuilder & addCImm(const ConstantInt *Val) const
bool isOptionalDef() const
Set if this operand is a optional def.
Definition: MCInstrDesc.h:99
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:46
bool isVariadic() const
Return true if this instruction can have a variable number of operands.
Definition: MCInstrDesc.h:254
bool hasAnyUseOfValue(unsigned Value) const
Return true if there are any use of the indicated value.
bool isMachineOpcode() const
SDNode * getGluedUser() const
If this node has a glue value with a user, return the user (there is at most one).
const SDValue & getOperand(unsigned Num) const
TypeSize getTypeAllocSize(Type *Ty) const
Returns the offset in bytes between successive objects of the specified type, including alignment pad...
Definition: DataLayout.h:487
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:263
static unsigned getNumOperandRegisters(unsigned Flag)
getNumOperandRegisters - Extract the number of registers field from the inline asm operand flag...
Definition: InlineAsm.h:336
unsigned getPrefTypeAlignment(Type *Ty) const
Returns the preferred stack/global alignment for the specified type.
Definition: DataLayout.cpp:765
void setFlag(MIFlag Flag)
Set a MI flag.
Definition: MachineInstr.h:302
unsigned getMachineOpcode() const
bool hasNoNaNs() const
const MachineInstrBuilder & addRegMask(const uint32_t *Mask) const
constexpr double e
Definition: MathExtras.h:57
static unsigned getKind(unsigned Flags)
Definition: InlineAsm.h:325
virtual const TargetRegisterClass * getMatchingSuperRegClass(const TargetRegisterClass *A, const TargetRegisterClass *B, unsigned Idx) const
Return a subclass of the specified register class A so that each register in it has a sub-register of...
const MachineInstrBuilder & addSym(MCSymbol *Sym, unsigned char TargetFlags=0) const
MachineConstantPool * getConstantPool()
getConstantPool - Return the constant pool object for the current function.
const MachineInstrBuilder & addFrameIndex(int Idx) const
DebugLoc getDebugLoc() const
Returns the DebugLoc.
unsigned getNumOperands() const
Return the number of values used by this operation.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:40
bool hasSubClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a sub-class of or equal to this class.
MachineOperand * findRegisterDefOperand(Register Reg, bool isDead=false, bool Overlap=false, const TargetRegisterInfo *TRI=nullptr)
Wrapper for findRegisterDefOperandIdx, it returns a pointer to the MachineOperand rather than an inde...
EH_LABEL - Represents a label in mid basic block used to track locations needed for debug and excepti...
Definition: ISDOpcodes.h:704
virtual const MCPhysReg * getScratchRegisters(CallingConv::ID CC) const
Returns a 0 terminated array of registers that can be safely used as scratch registers.
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specific constraint if it is set.
Definition: MCInstrDesc.h:203
TokenFactor - This node takes multiple tokens as input and produces a single token result...
Definition: ISDOpcodes.h:49
void dump() const
Dump this node, for debugging.
bool readsRegister(Register Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr reads the specified register.
DIExpression * getExpression() const
Returns the DIExpression pointer for the expression.
unsigned getNumOperands() const
Definition: User.h:191
This is the shared class of boolean and integer constants.
Definition: Constants.h:83
DebugLoc getDebugLoc() const
Returns the DebugLoc.
Value is a constant.
MachineOperand class - Representation of each machine instruction operand.
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:837
MachineInstrBuilder MachineInstrBuilder & DefMI
int getCopyCost() const
Return the cost of copying a value between two registers in this class.
bool isDivergent() const
bool hasFPExcept() const
virtual bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg, unsigned &SubIdx) const
Return true if the instruction is a "coalescable" extension instruction.
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Definition: MCInstrDesc.h:241
Represents one node in the SelectionDAG.
virtual void AdjustInstrPostInstrSelection(MachineInstr &MI, SDNode *Node) const
This method should be implemented by targets that mark instructions with the &#39;hasPostISelHook&#39; flag...
bool isTypeLegal(EVT VT) const
Return true if the target has native support for the specified value type.
iterator_range< use_iterator > uses()
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
void append(in_iter in_start, in_iter in_end)
Add the specified range to the end of the SmallVector.
Definition: SmallVector.h:387
bool hasNoSignedWrap() const
const TargetRegisterClass * getCommonSubClass(const TargetRegisterClass *A, const TargetRegisterClass *B) const
Find the largest common subclass of A and B.
Representation of each machine instruction.
Definition: MachineInstr.h:64
These are IR-level optimization flags that may be propagated to SDNodes.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Value is the result of an expression.
Holds the information from a dbg_label node through SDISel.
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:55
static unsigned countOperands(SDNode *Node, unsigned NumExpUses, unsigned &NumImpUses)
countOperands - The inputs to target nodes have any actual inputs first, followed by an optional chai...
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:44
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
unsigned getImplRegState(bool B)
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:332
MachineInstr * EmitDbgLabel(SDDbgLabel *SD)
Generate machine instruction for a dbg_label node.
bool isAllocatable() const
Return true if this register class may be used to create virtual registers.
MDNode * getLabel() const
Returns the MDNode pointer for the label.
CopyFromReg - This node indicates that the input value is a virtual or physical register that is defi...
Definition: ISDOpcodes.h:174
const TargetRegisterClass * getMinimalPhysRegClass(unsigned Reg, MVT VT=MVT::Other) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
bool isReg() const
isReg - Tests if this is a MO_Register operand.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
unsigned getReg() const
MachineInstr * EmitDbgValue(SDDbgValue *SD, DenseMap< SDValue, unsigned > &VRBaseMap)
EmitDbgValue - Generate machine instruction for a dbg_value node.
INLINEASM_BR - Terminator version of inline asm. Used by asm-goto.
Definition: ISDOpcodes.h:699
const TargetRegisterClass * getAllocatableClass(const TargetRegisterClass *RC) const
Return the maximal subclass of the given register class that is allocatable or NULL.
LLVM Value Representation.
Definition: Value.h:73
uint64_t getConstantOperandVal(unsigned Num) const
Helper method returns the integer value of a ConstantSDNode operand.
unsigned getResNo() const
get the index which selects a specific result in the SDNode
unsigned getMachineOpcode() const
This may only be called if isMachineOpcode returns true.
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:69
bool hasNoUnsignedWrap() const
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:190
static const Function * getParent(const Value *V)
bool hasAllowReassociation() const
IRTranslator LLVM IR MI
bool hasNoInfs() const
void setRegClass(unsigned Reg, const TargetRegisterClass *RC)
setRegClass - Set the register class of the specified virtual register.
MERGE_VALUES - This node takes multiple discrete operands and returns them all as its individual resu...
Definition: ISDOpcodes.h:197
unsigned getNumOperands() const
bool isIndirect() const
Returns whether this is an indirect value.
uint64_t getZExtValue() const
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:416
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
Holds the information from a dbg_value node through SDISel.
const MachineInstrBuilder & addTargetIndex(unsigned Idx, int64_t Offset=0, unsigned TargetFlags=0) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
unsigned getConstantPoolIndex(const Constant *C, unsigned Alignment)
getConstantPoolIndex - Create a new entry in the constant pool or return an existing one...
const MachineInstrBuilder & addExternalSymbol(const char *FnName, unsigned TargetFlags=0) const
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
This file describes how to lower LLVM code to machine code.
bool isImplicit() const
const MachineInstrBuilder & addBlockAddress(const BlockAddress *BA, int64_t Offset=0, unsigned TargetFlags=0) const
void tieOperands(unsigned DefIdx, unsigned UseIdx)
Add a tie between the register operands at DefIdx and UseIdx.