LLVM  9.0.0svn
InstrEmitter.cpp
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1 //==--- InstrEmitter.cpp - Emit MachineInstrs for the SelectionDAG class ---==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This implements the Emit routines for the SelectionDAG class, which creates
10 // MachineInstrs based on the decisions of the SelectionDAG instruction
11 // selection.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "InstrEmitter.h"
16 #include "SDNodeDbgValue.h"
17 #include "llvm/ADT/Statistic.h"
22 #include "llvm/CodeGen/StackMaps.h"
26 #include "llvm/IR/DataLayout.h"
27 #include "llvm/IR/DebugInfo.h"
28 #include "llvm/Support/Debug.h"
31 using namespace llvm;
32 
33 #define DEBUG_TYPE "instr-emitter"
34 
35 /// MinRCSize - Smallest register class we allow when constraining virtual
36 /// registers. If satisfying all register class constraints would require
37 /// using a smaller register class, emit a COPY to a new virtual register
38 /// instead.
39 const unsigned MinRCSize = 4;
40 
41 /// CountResults - The results of target nodes have register or immediate
42 /// operands first, then an optional chain, and optional glue operands (which do
43 /// not go into the resulting MachineInstr).
45  unsigned N = Node->getNumValues();
46  while (N && Node->getValueType(N - 1) == MVT::Glue)
47  --N;
48  if (N && Node->getValueType(N - 1) == MVT::Other)
49  --N; // Skip over chain result.
50  return N;
51 }
52 
53 /// countOperands - The inputs to target nodes have any actual inputs first,
54 /// followed by an optional chain operand, then an optional glue operand.
55 /// Compute the number of actual operands that will go into the resulting
56 /// MachineInstr.
57 ///
58 /// Also count physreg RegisterSDNode and RegisterMaskSDNode operands preceding
59 /// the chain and glue. These operands may be implicit on the machine instr.
60 static unsigned countOperands(SDNode *Node, unsigned NumExpUses,
61  unsigned &NumImpUses) {
62  unsigned N = Node->getNumOperands();
63  while (N && Node->getOperand(N - 1).getValueType() == MVT::Glue)
64  --N;
65  if (N && Node->getOperand(N - 1).getValueType() == MVT::Other)
66  --N; // Ignore chain if it exists.
67 
68  // Count RegisterSDNode and RegisterMaskSDNode operands for NumImpUses.
69  NumImpUses = N - NumExpUses;
70  for (unsigned I = N; I > NumExpUses; --I) {
71  if (isa<RegisterMaskSDNode>(Node->getOperand(I - 1)))
72  continue;
73  if (RegisterSDNode *RN = dyn_cast<RegisterSDNode>(Node->getOperand(I - 1)))
75  continue;
76  NumImpUses = N - I;
77  break;
78  }
79 
80  return N;
81 }
82 
83 /// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an
84 /// implicit physical register output.
85 void InstrEmitter::
86 EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone, bool IsCloned,
87  unsigned SrcReg, DenseMap<SDValue, unsigned> &VRBaseMap) {
88  unsigned VRBase = 0;
90  // Just use the input register directly!
91  SDValue Op(Node, ResNo);
92  if (IsClone)
93  VRBaseMap.erase(Op);
94  bool isNew = VRBaseMap.insert(std::make_pair(Op, SrcReg)).second;
95  (void)isNew; // Silence compiler warning.
96  assert(isNew && "Node emitted out of order - early");
97  return;
98  }
99 
100  // If the node is only used by a CopyToReg and the dest reg is a vreg, use
101  // the CopyToReg'd destination register instead of creating a new vreg.
102  bool MatchReg = true;
103  const TargetRegisterClass *UseRC = nullptr;
104  MVT VT = Node->getSimpleValueType(ResNo);
105 
106  // Stick to the preferred register classes for legal types.
107  if (TLI->isTypeLegal(VT))
108  UseRC = TLI->getRegClassFor(VT);
109 
110  if (!IsClone && !IsCloned)
111  for (SDNode *User : Node->uses()) {
112  bool Match = true;
113  if (User->getOpcode() == ISD::CopyToReg &&
114  User->getOperand(2).getNode() == Node &&
115  User->getOperand(2).getResNo() == ResNo) {
116  unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
118  VRBase = DestReg;
119  Match = false;
120  } else if (DestReg != SrcReg)
121  Match = false;
122  } else {
123  for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
124  SDValue Op = User->getOperand(i);
125  if (Op.getNode() != Node || Op.getResNo() != ResNo)
126  continue;
127  MVT VT = Node->getSimpleValueType(Op.getResNo());
128  if (VT == MVT::Other || VT == MVT::Glue)
129  continue;
130  Match = false;
131  if (User->isMachineOpcode()) {
132  const MCInstrDesc &II = TII->get(User->getMachineOpcode());
133  const TargetRegisterClass *RC = nullptr;
134  if (i+II.getNumDefs() < II.getNumOperands()) {
135  RC = TRI->getAllocatableClass(
136  TII->getRegClass(II, i+II.getNumDefs(), TRI, *MF));
137  }
138  if (!UseRC)
139  UseRC = RC;
140  else if (RC) {
141  const TargetRegisterClass *ComRC =
142  TRI->getCommonSubClass(UseRC, RC, VT.SimpleTy);
143  // If multiple uses expect disjoint register classes, we emit
144  // copies in AddRegisterOperand.
145  if (ComRC)
146  UseRC = ComRC;
147  }
148  }
149  }
150  }
151  MatchReg &= Match;
152  if (VRBase)
153  break;
154  }
155 
156  const TargetRegisterClass *SrcRC = nullptr, *DstRC = nullptr;
157  SrcRC = TRI->getMinimalPhysRegClass(SrcReg, VT);
158 
159  // Figure out the register class to create for the destreg.
160  if (VRBase) {
161  DstRC = MRI->getRegClass(VRBase);
162  } else if (UseRC) {
163  assert(TRI->isTypeLegalForClass(*UseRC, VT) &&
164  "Incompatible phys register def and uses!");
165  DstRC = UseRC;
166  } else {
167  DstRC = TLI->getRegClassFor(VT);
168  }
169 
170  // If all uses are reading from the src physical register and copying the
171  // register is either impossible or very expensive, then don't create a copy.
172  if (MatchReg && SrcRC->getCopyCost() < 0) {
173  VRBase = SrcReg;
174  } else {
175  // Create the reg, emit the copy.
176  VRBase = MRI->createVirtualRegister(DstRC);
177  BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
178  VRBase).addReg(SrcReg);
179  }
180 
181  SDValue Op(Node, ResNo);
182  if (IsClone)
183  VRBaseMap.erase(Op);
184  bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
185  (void)isNew; // Silence compiler warning.
186  assert(isNew && "Node emitted out of order - early");
187 }
188 
189 /// getDstOfCopyToRegUse - If the only use of the specified result number of
190 /// node is a CopyToReg, return its destination register. Return 0 otherwise.
191 unsigned InstrEmitter::getDstOfOnlyCopyToRegUse(SDNode *Node,
192  unsigned ResNo) const {
193  if (!Node->hasOneUse())
194  return 0;
195 
196  SDNode *User = *Node->use_begin();
197  if (User->getOpcode() == ISD::CopyToReg &&
198  User->getOperand(2).getNode() == Node &&
199  User->getOperand(2).getResNo() == ResNo) {
200  unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
202  return Reg;
203  }
204  return 0;
205 }
206 
207 void InstrEmitter::CreateVirtualRegisters(SDNode *Node,
208  MachineInstrBuilder &MIB,
209  const MCInstrDesc &II,
210  bool IsClone, bool IsCloned,
211  DenseMap<SDValue, unsigned> &VRBaseMap) {
212  assert(Node->getMachineOpcode() != TargetOpcode::IMPLICIT_DEF &&
213  "IMPLICIT_DEF should have been handled as a special case elsewhere!");
214 
215  unsigned NumResults = CountResults(Node);
216  for (unsigned i = 0; i < II.getNumDefs(); ++i) {
217  // If the specific node value is only used by a CopyToReg and the dest reg
218  // is a vreg in the same register class, use the CopyToReg'd destination
219  // register instead of creating a new vreg.
220  unsigned VRBase = 0;
221  const TargetRegisterClass *RC =
222  TRI->getAllocatableClass(TII->getRegClass(II, i, TRI, *MF));
223  // Always let the value type influence the used register class. The
224  // constraints on the instruction may be too lax to represent the value
225  // type correctly. For example, a 64-bit float (X86::FR64) can't live in
226  // the 32-bit float super-class (X86::FR32).
227  if (i < NumResults && TLI->isTypeLegal(Node->getSimpleValueType(i))) {
228  const TargetRegisterClass *VTRC =
229  TLI->getRegClassFor(Node->getSimpleValueType(i));
230  if (RC)
231  VTRC = TRI->getCommonSubClass(RC, VTRC);
232  if (VTRC)
233  RC = VTRC;
234  }
235 
236  if (II.OpInfo[i].isOptionalDef()) {
237  // Optional def must be a physical register.
238  VRBase = cast<RegisterSDNode>(Node->getOperand(i-NumResults))->getReg();
240  MIB.addReg(VRBase, RegState::Define);
241  }
242 
243  if (!VRBase && !IsClone && !IsCloned)
244  for (SDNode *User : Node->uses()) {
245  if (User->getOpcode() == ISD::CopyToReg &&
246  User->getOperand(2).getNode() == Node &&
247  User->getOperand(2).getResNo() == i) {
248  unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
250  const TargetRegisterClass *RegRC = MRI->getRegClass(Reg);
251  if (RegRC == RC) {
252  VRBase = Reg;
253  MIB.addReg(VRBase, RegState::Define);
254  break;
255  }
256  }
257  }
258  }
259 
260  // Create the result registers for this node and add the result regs to
261  // the machine instruction.
262  if (VRBase == 0) {
263  assert(RC && "Isn't a register operand!");
264  VRBase = MRI->createVirtualRegister(RC);
265  MIB.addReg(VRBase, RegState::Define);
266  }
267 
268  // If this def corresponds to a result of the SDNode insert the VRBase into
269  // the lookup map.
270  if (i < NumResults) {
271  SDValue Op(Node, i);
272  if (IsClone)
273  VRBaseMap.erase(Op);
274  bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
275  (void)isNew; // Silence compiler warning.
276  assert(isNew && "Node emitted out of order - early");
277  }
278  }
279 }
280 
281 /// getVR - Return the virtual register corresponding to the specified result
282 /// of the specified node.
283 unsigned InstrEmitter::getVR(SDValue Op,
284  DenseMap<SDValue, unsigned> &VRBaseMap) {
285  if (Op.isMachineOpcode() &&
286  Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) {
287  // Add an IMPLICIT_DEF instruction before every use.
288  unsigned VReg = getDstOfOnlyCopyToRegUse(Op.getNode(), Op.getResNo());
289  // IMPLICIT_DEF can produce any type of result so its MCInstrDesc
290  // does not include operand register class info.
291  if (!VReg) {
292  const TargetRegisterClass *RC =
294  VReg = MRI->createVirtualRegister(RC);
295  }
296  BuildMI(*MBB, InsertPos, Op.getDebugLoc(),
297  TII->get(TargetOpcode::IMPLICIT_DEF), VReg);
298  return VReg;
299  }
300 
302  assert(I != VRBaseMap.end() && "Node emitted out of order - late");
303  return I->second;
304 }
305 
306 
307 /// AddRegisterOperand - Add the specified register as an operand to the
308 /// specified machine instr. Insert register copies if the register is
309 /// not in the required register class.
310 void
311 InstrEmitter::AddRegisterOperand(MachineInstrBuilder &MIB,
312  SDValue Op,
313  unsigned IIOpNum,
314  const MCInstrDesc *II,
315  DenseMap<SDValue, unsigned> &VRBaseMap,
316  bool IsDebug, bool IsClone, bool IsCloned) {
317  assert(Op.getValueType() != MVT::Other &&
318  Op.getValueType() != MVT::Glue &&
319  "Chain and glue operands should occur at end of operand list!");
320  // Get/emit the operand.
321  unsigned VReg = getVR(Op, VRBaseMap);
322 
323  const MCInstrDesc &MCID = MIB->getDesc();
324  bool isOptDef = IIOpNum < MCID.getNumOperands() &&
325  MCID.OpInfo[IIOpNum].isOptionalDef();
326 
327  // If the instruction requires a register in a different class, create
328  // a new virtual register and copy the value into it, but first attempt to
329  // shrink VReg's register class within reason. For example, if VReg == GR32
330  // and II requires a GR32_NOSP, just constrain VReg to GR32_NOSP.
331  if (II) {
332  const TargetRegisterClass *OpRC = nullptr;
333  if (IIOpNum < II->getNumOperands())
334  OpRC = TII->getRegClass(*II, IIOpNum, TRI, *MF);
335 
336  if (OpRC) {
337  const TargetRegisterClass *ConstrainedRC
338  = MRI->constrainRegClass(VReg, OpRC, MinRCSize);
339  if (!ConstrainedRC) {
340  OpRC = TRI->getAllocatableClass(OpRC);
341  assert(OpRC && "Constraints cannot be fulfilled for allocation");
342  unsigned NewVReg = MRI->createVirtualRegister(OpRC);
343  BuildMI(*MBB, InsertPos, Op.getNode()->getDebugLoc(),
344  TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg);
345  VReg = NewVReg;
346  } else {
347  assert(ConstrainedRC->isAllocatable() &&
348  "Constraining an allocatable VReg produced an unallocatable class?");
349  }
350  }
351  }
352 
353  // If this value has only one use, that use is a kill. This is a
354  // conservative approximation. InstrEmitter does trivial coalescing
355  // with CopyFromReg nodes, so don't emit kill flags for them.
356  // Avoid kill flags on Schedule cloned nodes, since there will be
357  // multiple uses.
358  // Tied operands are never killed, so we need to check that. And that
359  // means we need to determine the index of the operand.
360  bool isKill = Op.hasOneUse() &&
361  Op.getNode()->getOpcode() != ISD::CopyFromReg &&
362  !IsDebug &&
363  !(IsClone || IsCloned);
364  if (isKill) {
365  unsigned Idx = MIB->getNumOperands();
366  while (Idx > 0 &&
367  MIB->getOperand(Idx-1).isReg() &&
368  MIB->getOperand(Idx-1).isImplicit())
369  --Idx;
370  bool isTied = MCID.getOperandConstraint(Idx, MCOI::TIED_TO) != -1;
371  if (isTied)
372  isKill = false;
373  }
374 
375  MIB.addReg(VReg, getDefRegState(isOptDef) | getKillRegState(isKill) |
376  getDebugRegState(IsDebug));
377 }
378 
379 /// AddOperand - Add the specified operand to the specified machine instr. II
380 /// specifies the instruction information for the node, and IIOpNum is the
381 /// operand number (in the II) that we are adding.
382 void InstrEmitter::AddOperand(MachineInstrBuilder &MIB,
383  SDValue Op,
384  unsigned IIOpNum,
385  const MCInstrDesc *II,
386  DenseMap<SDValue, unsigned> &VRBaseMap,
387  bool IsDebug, bool IsClone, bool IsCloned) {
388  if (Op.isMachineOpcode()) {
389  AddRegisterOperand(MIB, Op, IIOpNum, II, VRBaseMap,
390  IsDebug, IsClone, IsCloned);
391  } else if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
392  MIB.addImm(C->getSExtValue());
393  } else if (ConstantFPSDNode *F = dyn_cast<ConstantFPSDNode>(Op)) {
394  MIB.addFPImm(F->getConstantFPValue());
395  } else if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Op)) {
396  unsigned VReg = R->getReg();
397  MVT OpVT = Op.getSimpleValueType();
398  const TargetRegisterClass *OpRC =
399  TLI->isTypeLegal(OpVT) ? TLI->getRegClassFor(OpVT) : nullptr;
400  const TargetRegisterClass *IIRC =
401  II ? TRI->getAllocatableClass(TII->getRegClass(*II, IIOpNum, TRI, *MF))
402  : nullptr;
403 
404  if (OpRC && IIRC && OpRC != IIRC &&
406  unsigned NewVReg = MRI->createVirtualRegister(IIRC);
407  BuildMI(*MBB, InsertPos, Op.getNode()->getDebugLoc(),
408  TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg);
409  VReg = NewVReg;
410  }
411  // Turn additional physreg operands into implicit uses on non-variadic
412  // instructions. This is used by call and return instructions passing
413  // arguments in registers.
414  bool Imp = II && (IIOpNum >= II->getNumOperands() && !II->isVariadic());
415  MIB.addReg(VReg, getImplRegState(Imp));
416  } else if (RegisterMaskSDNode *RM = dyn_cast<RegisterMaskSDNode>(Op)) {
417  MIB.addRegMask(RM->getRegMask());
418  } else if (GlobalAddressSDNode *TGA = dyn_cast<GlobalAddressSDNode>(Op)) {
419  MIB.addGlobalAddress(TGA->getGlobal(), TGA->getOffset(),
420  TGA->getTargetFlags());
421  } else if (BasicBlockSDNode *BBNode = dyn_cast<BasicBlockSDNode>(Op)) {
422  MIB.addMBB(BBNode->getBasicBlock());
423  } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Op)) {
424  MIB.addFrameIndex(FI->getIndex());
425  } else if (JumpTableSDNode *JT = dyn_cast<JumpTableSDNode>(Op)) {
426  MIB.addJumpTableIndex(JT->getIndex(), JT->getTargetFlags());
427  } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op)) {
428  int Offset = CP->getOffset();
429  unsigned Align = CP->getAlignment();
430  Type *Type = CP->getType();
431  // MachineConstantPool wants an explicit alignment.
432  if (Align == 0) {
433  Align = MF->getDataLayout().getPrefTypeAlignment(Type);
434  if (Align == 0) {
435  // Alignment of vector types. FIXME!
436  Align = MF->getDataLayout().getTypeAllocSize(Type);
437  }
438  }
439 
440  unsigned Idx;
442  if (CP->isMachineConstantPoolEntry())
443  Idx = MCP->getConstantPoolIndex(CP->getMachineCPVal(), Align);
444  else
445  Idx = MCP->getConstantPoolIndex(CP->getConstVal(), Align);
446  MIB.addConstantPoolIndex(Idx, Offset, CP->getTargetFlags());
447  } else if (ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op)) {
448  MIB.addExternalSymbol(ES->getSymbol(), ES->getTargetFlags());
449  } else if (auto *SymNode = dyn_cast<MCSymbolSDNode>(Op)) {
450  MIB.addSym(SymNode->getMCSymbol());
451  } else if (BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(Op)) {
452  MIB.addBlockAddress(BA->getBlockAddress(),
453  BA->getOffset(),
454  BA->getTargetFlags());
455  } else if (TargetIndexSDNode *TI = dyn_cast<TargetIndexSDNode>(Op)) {
456  MIB.addTargetIndex(TI->getIndex(), TI->getOffset(), TI->getTargetFlags());
457  } else {
458  assert(Op.getValueType() != MVT::Other &&
459  Op.getValueType() != MVT::Glue &&
460  "Chain and glue operands should occur at end of operand list!");
461  AddRegisterOperand(MIB, Op, IIOpNum, II, VRBaseMap,
462  IsDebug, IsClone, IsCloned);
463  }
464 }
465 
466 unsigned InstrEmitter::ConstrainForSubReg(unsigned VReg, unsigned SubIdx,
467  MVT VT, const DebugLoc &DL) {
468  const TargetRegisterClass *VRC = MRI->getRegClass(VReg);
469  const TargetRegisterClass *RC = TRI->getSubClassWithSubReg(VRC, SubIdx);
470 
471  // RC is a sub-class of VRC that supports SubIdx. Try to constrain VReg
472  // within reason.
473  if (RC && RC != VRC)
474  RC = MRI->constrainRegClass(VReg, RC, MinRCSize);
475 
476  // VReg has been adjusted. It can be used with SubIdx operands now.
477  if (RC)
478  return VReg;
479 
480  // VReg couldn't be reasonably constrained. Emit a COPY to a new virtual
481  // register instead.
482  RC = TRI->getSubClassWithSubReg(TLI->getRegClassFor(VT), SubIdx);
483  assert(RC && "No legal register class for VT supports that SubIdx");
484  unsigned NewReg = MRI->createVirtualRegister(RC);
485  BuildMI(*MBB, InsertPos, DL, TII->get(TargetOpcode::COPY), NewReg)
486  .addReg(VReg);
487  return NewReg;
488 }
489 
490 /// EmitSubregNode - Generate machine code for subreg nodes.
491 ///
492 void InstrEmitter::EmitSubregNode(SDNode *Node,
493  DenseMap<SDValue, unsigned> &VRBaseMap,
494  bool IsClone, bool IsCloned) {
495  unsigned VRBase = 0;
496  unsigned Opc = Node->getMachineOpcode();
497 
498  // If the node is only used by a CopyToReg and the dest reg is a vreg, use
499  // the CopyToReg'd destination register instead of creating a new vreg.
500  for (SDNode *User : Node->uses()) {
501  if (User->getOpcode() == ISD::CopyToReg &&
502  User->getOperand(2).getNode() == Node) {
503  unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
505  VRBase = DestReg;
506  break;
507  }
508  }
509  }
510 
511  if (Opc == TargetOpcode::EXTRACT_SUBREG) {
512  // EXTRACT_SUBREG is lowered as %dst = COPY %src:sub. There are no
513  // constraints on the %dst register, COPY can target all legal register
514  // classes.
515  unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
516  const TargetRegisterClass *TRC =
517  TLI->getRegClassFor(Node->getSimpleValueType(0));
518 
519  unsigned Reg;
523  Reg = R->getReg();
524  DefMI = nullptr;
525  } else {
526  Reg = R ? R->getReg() : getVR(Node->getOperand(0), VRBaseMap);
527  DefMI = MRI->getVRegDef(Reg);
528  }
529 
530  unsigned SrcReg, DstReg, DefSubIdx;
531  if (DefMI &&
532  TII->isCoalescableExtInstr(*DefMI, SrcReg, DstReg, DefSubIdx) &&
533  SubIdx == DefSubIdx &&
534  TRC == MRI->getRegClass(SrcReg)) {
535  // Optimize these:
536  // r1025 = s/zext r1024, 4
537  // r1026 = extract_subreg r1025, 4
538  // to a copy
539  // r1026 = copy r1024
540  VRBase = MRI->createVirtualRegister(TRC);
541  BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
542  TII->get(TargetOpcode::COPY), VRBase).addReg(SrcReg);
543  MRI->clearKillFlags(SrcReg);
544  } else {
545  // Reg may not support a SubIdx sub-register, and we may need to
546  // constrain its register class or issue a COPY to a compatible register
547  // class.
549  Reg = ConstrainForSubReg(Reg, SubIdx,
550  Node->getOperand(0).getSimpleValueType(),
551  Node->getDebugLoc());
552 
553  // Create the destreg if it is missing.
554  if (VRBase == 0)
555  VRBase = MRI->createVirtualRegister(TRC);
556 
557  // Create the extract_subreg machine instruction.
558  MachineInstrBuilder CopyMI =
559  BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
560  TII->get(TargetOpcode::COPY), VRBase);
562  CopyMI.addReg(Reg, 0, SubIdx);
563  else
564  CopyMI.addReg(TRI->getSubReg(Reg, SubIdx));
565  }
566  } else if (Opc == TargetOpcode::INSERT_SUBREG ||
567  Opc == TargetOpcode::SUBREG_TO_REG) {
568  SDValue N0 = Node->getOperand(0);
569  SDValue N1 = Node->getOperand(1);
570  SDValue N2 = Node->getOperand(2);
571  unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue();
572 
573  // Figure out the register class to create for the destreg. It should be
574  // the largest legal register class supporting SubIdx sub-registers.
575  // RegisterCoalescer will constrain it further if it decides to eliminate
576  // the INSERT_SUBREG instruction.
577  //
578  // %dst = INSERT_SUBREG %src, %sub, SubIdx
579  //
580  // is lowered by TwoAddressInstructionPass to:
581  //
582  // %dst = COPY %src
583  // %dst:SubIdx = COPY %sub
584  //
585  // There is no constraint on the %src register class.
586  //
587  const TargetRegisterClass *SRC = TLI->getRegClassFor(Node->getSimpleValueType(0));
588  SRC = TRI->getSubClassWithSubReg(SRC, SubIdx);
589  assert(SRC && "No register class supports VT and SubIdx for INSERT_SUBREG");
590 
591  if (VRBase == 0 || !SRC->hasSubClassEq(MRI->getRegClass(VRBase)))
592  VRBase = MRI->createVirtualRegister(SRC);
593 
594  // Create the insert_subreg or subreg_to_reg machine instruction.
595  MachineInstrBuilder MIB =
596  BuildMI(*MF, Node->getDebugLoc(), TII->get(Opc), VRBase);
597 
598  // If creating a subreg_to_reg, then the first input operand
599  // is an implicit value immediate, otherwise it's a register
600  if (Opc == TargetOpcode::SUBREG_TO_REG) {
601  const ConstantSDNode *SD = cast<ConstantSDNode>(N0);
602  MIB.addImm(SD->getZExtValue());
603  } else
604  AddOperand(MIB, N0, 0, nullptr, VRBaseMap, /*IsDebug=*/false,
605  IsClone, IsCloned);
606  // Add the subregister being inserted
607  AddOperand(MIB, N1, 0, nullptr, VRBaseMap, /*IsDebug=*/false,
608  IsClone, IsCloned);
609  MIB.addImm(SubIdx);
610  MBB->insert(InsertPos, MIB);
611  } else
612  llvm_unreachable("Node is not insert_subreg, extract_subreg, or subreg_to_reg");
613 
614  SDValue Op(Node, 0);
615  bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
616  (void)isNew; // Silence compiler warning.
617  assert(isNew && "Node emitted out of order - early");
618 }
619 
620 /// EmitCopyToRegClassNode - Generate machine code for COPY_TO_REGCLASS nodes.
621 /// COPY_TO_REGCLASS is just a normal copy, except that the destination
622 /// register is constrained to be in a particular register class.
623 ///
624 void
625 InstrEmitter::EmitCopyToRegClassNode(SDNode *Node,
626  DenseMap<SDValue, unsigned> &VRBaseMap) {
627  unsigned VReg = getVR(Node->getOperand(0), VRBaseMap);
628 
629  // Create the new VReg in the destination class and emit a copy.
630  unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
631  const TargetRegisterClass *DstRC =
632  TRI->getAllocatableClass(TRI->getRegClass(DstRCIdx));
633  unsigned NewVReg = MRI->createVirtualRegister(DstRC);
634  BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
635  NewVReg).addReg(VReg);
636 
637  SDValue Op(Node, 0);
638  bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second;
639  (void)isNew; // Silence compiler warning.
640  assert(isNew && "Node emitted out of order - early");
641 }
642 
643 /// EmitRegSequence - Generate machine code for REG_SEQUENCE nodes.
644 ///
645 void InstrEmitter::EmitRegSequence(SDNode *Node,
646  DenseMap<SDValue, unsigned> &VRBaseMap,
647  bool IsClone, bool IsCloned) {
648  unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue();
649  const TargetRegisterClass *RC = TRI->getRegClass(DstRCIdx);
650  unsigned NewVReg = MRI->createVirtualRegister(TRI->getAllocatableClass(RC));
651  const MCInstrDesc &II = TII->get(TargetOpcode::REG_SEQUENCE);
652  MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(), II, NewVReg);
653  unsigned NumOps = Node->getNumOperands();
654  // If the input pattern has a chain, then the root of the corresponding
655  // output pattern will get a chain as well. This can happen to be a
656  // REG_SEQUENCE (which is not "guarded" by countOperands/CountResults).
657  if (NumOps && Node->getOperand(NumOps-1).getValueType() == MVT::Other)
658  --NumOps; // Ignore chain if it exists.
659 
660  assert((NumOps & 1) == 1 &&
661  "REG_SEQUENCE must have an odd number of operands!");
662  for (unsigned i = 1; i != NumOps; ++i) {
663  SDValue Op = Node->getOperand(i);
664  if ((i & 1) == 0) {
666  // Skip physical registers as they don't have a vreg to get and we'll
667  // insert copies for them in TwoAddressInstructionPass anyway.
669  unsigned SubIdx = cast<ConstantSDNode>(Op)->getZExtValue();
670  unsigned SubReg = getVR(Node->getOperand(i-1), VRBaseMap);
671  const TargetRegisterClass *TRC = MRI->getRegClass(SubReg);
672  const TargetRegisterClass *SRC =
673  TRI->getMatchingSuperRegClass(RC, TRC, SubIdx);
674  if (SRC && SRC != RC) {
675  MRI->setRegClass(NewVReg, SRC);
676  RC = SRC;
677  }
678  }
679  }
680  AddOperand(MIB, Op, i+1, &II, VRBaseMap, /*IsDebug=*/false,
681  IsClone, IsCloned);
682  }
683 
684  MBB->insert(InsertPos, MIB);
685  SDValue Op(Node, 0);
686  bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second;
687  (void)isNew; // Silence compiler warning.
688  assert(isNew && "Node emitted out of order - early");
689 }
690 
691 /// EmitDbgValue - Generate machine instruction for a dbg_value node.
692 ///
693 MachineInstr *
695  DenseMap<SDValue, unsigned> &VRBaseMap) {
696  MDNode *Var = SD->getVariable();
697  MDNode *Expr = SD->getExpression();
698  DebugLoc DL = SD->getDebugLoc();
699  assert(cast<DILocalVariable>(Var)->isValidLocationForIntrinsic(DL) &&
700  "Expected inlined-at fields to agree");
701 
702  SD->setIsEmitted();
703 
704  if (SD->isInvalidated()) {
705  // An invalidated SDNode must generate an undef DBG_VALUE: although the
706  // original value is no longer computed, earlier DBG_VALUEs live ranges
707  // must not leak into later code.
708  auto MIB = BuildMI(*MF, DL, TII->get(TargetOpcode::DBG_VALUE));
709  MIB.addReg(0U);
710  MIB.addReg(0U, RegState::Debug);
711  MIB.addMetadata(Var);
712  MIB.addMetadata(Expr);
713  return &*MIB;
714  }
715 
716  if (SD->getKind() == SDDbgValue::FRAMEIX) {
717  // Stack address; this needs to be lowered in target-dependent fashion.
718  // EmitTargetCodeForFrameDebugValue is responsible for allocation.
719  auto FrameMI = BuildMI(*MF, DL, TII->get(TargetOpcode::DBG_VALUE))
720  .addFrameIndex(SD->getFrameIx());
721  if (SD->isIndirect())
722  // Push [fi + 0] onto the DIExpression stack.
723  FrameMI.addImm(0);
724  else
725  // Push fi onto the DIExpression stack.
726  FrameMI.addReg(0);
727  return FrameMI.addMetadata(Var).addMetadata(Expr);
728  }
729  // Otherwise, we're going to create an instruction here.
730  const MCInstrDesc &II = TII->get(TargetOpcode::DBG_VALUE);
731  MachineInstrBuilder MIB = BuildMI(*MF, DL, II);
732  if (SD->getKind() == SDDbgValue::SDNODE) {
733  SDNode *Node = SD->getSDNode();
734  SDValue Op = SDValue(Node, SD->getResNo());
735  // It's possible we replaced this SDNode with other(s) and therefore
736  // didn't generate code for it. It's better to catch these cases where
737  // they happen and transfer the debug info, but trying to guarantee that
738  // in all cases would be very fragile; this is a safeguard for any
739  // that were missed.
741  if (I==VRBaseMap.end())
742  MIB.addReg(0U); // undef
743  else
744  AddOperand(MIB, Op, (*MIB).getNumOperands(), &II, VRBaseMap,
745  /*IsDebug=*/true, /*IsClone=*/false, /*IsCloned=*/false);
746  } else if (SD->getKind() == SDDbgValue::VREG) {
747  MIB.addReg(SD->getVReg(), RegState::Debug);
748  } else if (SD->getKind() == SDDbgValue::CONST) {
749  const Value *V = SD->getConst();
750  if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
751  if (CI->getBitWidth() > 64)
752  MIB.addCImm(CI);
753  else
754  MIB.addImm(CI->getSExtValue());
755  } else if (const ConstantFP *CF = dyn_cast<ConstantFP>(V)) {
756  MIB.addFPImm(CF);
757  } else if (isa<ConstantPointerNull>(V)) {
758  // Note: This assumes that all nullptr constants are zero-valued.
759  MIB.addImm(0);
760  } else {
761  // Could be an Undef. In any case insert an Undef so we can see what we
762  // dropped.
763  MIB.addReg(0U);
764  }
765  } else {
766  // Insert an Undef so we can see what we dropped.
767  MIB.addReg(0U);
768  }
769 
770  // Indirect addressing is indicated by an Imm as the second parameter.
771  if (SD->isIndirect())
772  MIB.addImm(0U);
773  else
774  MIB.addReg(0U, RegState::Debug);
775 
776  MIB.addMetadata(Var);
777  MIB.addMetadata(Expr);
778 
779  return &*MIB;
780 }
781 
782 MachineInstr *
784  MDNode *Label = SD->getLabel();
785  DebugLoc DL = SD->getDebugLoc();
786  assert(cast<DILabel>(Label)->isValidLocationForIntrinsic(DL) &&
787  "Expected inlined-at fields to agree");
788 
789  const MCInstrDesc &II = TII->get(TargetOpcode::DBG_LABEL);
790  MachineInstrBuilder MIB = BuildMI(*MF, DL, II);
791  MIB.addMetadata(Label);
792 
793  return &*MIB;
794 }
795 
796 /// EmitMachineNode - Generate machine code for a target-specific node and
797 /// needed dependencies.
798 ///
799 void InstrEmitter::
800 EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned,
801  DenseMap<SDValue, unsigned> &VRBaseMap) {
802  unsigned Opc = Node->getMachineOpcode();
803 
804  // Handle subreg insert/extract specially
805  if (Opc == TargetOpcode::EXTRACT_SUBREG ||
806  Opc == TargetOpcode::INSERT_SUBREG ||
807  Opc == TargetOpcode::SUBREG_TO_REG) {
808  EmitSubregNode(Node, VRBaseMap, IsClone, IsCloned);
809  return;
810  }
811 
812  // Handle COPY_TO_REGCLASS specially.
813  if (Opc == TargetOpcode::COPY_TO_REGCLASS) {
814  EmitCopyToRegClassNode(Node, VRBaseMap);
815  return;
816  }
817 
818  // Handle REG_SEQUENCE specially.
819  if (Opc == TargetOpcode::REG_SEQUENCE) {
820  EmitRegSequence(Node, VRBaseMap, IsClone, IsCloned);
821  return;
822  }
823 
824  if (Opc == TargetOpcode::IMPLICIT_DEF)
825  // We want a unique VR for each IMPLICIT_DEF use.
826  return;
827 
828  const MCInstrDesc &II = TII->get(Opc);
829  unsigned NumResults = CountResults(Node);
830  unsigned NumDefs = II.getNumDefs();
831  const MCPhysReg *ScratchRegs = nullptr;
832 
833  // Handle STACKMAP and PATCHPOINT specially and then use the generic code.
834  if (Opc == TargetOpcode::STACKMAP || Opc == TargetOpcode::PATCHPOINT) {
835  // Stackmaps do not have arguments and do not preserve their calling
836  // convention. However, to simplify runtime support, they clobber the same
837  // scratch registers as AnyRegCC.
838  unsigned CC = CallingConv::AnyReg;
839  if (Opc == TargetOpcode::PATCHPOINT) {
841  NumDefs = NumResults;
842  }
843  ScratchRegs = TLI->getScratchRegisters((CallingConv::ID) CC);
844  }
845 
846  unsigned NumImpUses = 0;
847  unsigned NodeOperands =
848  countOperands(Node, II.getNumOperands() - NumDefs, NumImpUses);
849  bool HasPhysRegOuts = NumResults > NumDefs && II.getImplicitDefs()!=nullptr;
850 #ifndef NDEBUG
851  unsigned NumMIOperands = NodeOperands + NumResults;
852  if (II.isVariadic())
853  assert(NumMIOperands >= II.getNumOperands() &&
854  "Too few operands for a variadic node!");
855  else
856  assert(NumMIOperands >= II.getNumOperands() &&
857  NumMIOperands <= II.getNumOperands() + II.getNumImplicitDefs() +
858  NumImpUses &&
859  "#operands for dag node doesn't match .td file!");
860 #endif
861 
862  // Create the new machine instruction.
863  MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(), II);
864 
865  // Add result register values for things that are defined by this
866  // instruction.
867  if (NumResults) {
868  CreateVirtualRegisters(Node, MIB, II, IsClone, IsCloned, VRBaseMap);
869 
870  // Transfer any IR flags from the SDNode to the MachineInstr
871  MachineInstr *MI = MIB.getInstr();
872  const SDNodeFlags Flags = Node->getFlags();
873  if (Flags.hasNoSignedZeros())
874  MI->setFlag(MachineInstr::MIFlag::FmNsz);
875 
876  if (Flags.hasAllowReciprocal())
877  MI->setFlag(MachineInstr::MIFlag::FmArcp);
878 
879  if (Flags.hasNoNaNs())
880  MI->setFlag(MachineInstr::MIFlag::FmNoNans);
881 
882  if (Flags.hasNoInfs())
883  MI->setFlag(MachineInstr::MIFlag::FmNoInfs);
884 
885  if (Flags.hasAllowContract())
886  MI->setFlag(MachineInstr::MIFlag::FmContract);
887 
888  if (Flags.hasApproximateFuncs())
889  MI->setFlag(MachineInstr::MIFlag::FmAfn);
890 
891  if (Flags.hasAllowReassociation())
892  MI->setFlag(MachineInstr::MIFlag::FmReassoc);
893 
894  if (Flags.hasNoUnsignedWrap())
895  MI->setFlag(MachineInstr::MIFlag::NoUWrap);
896 
897  if (Flags.hasNoSignedWrap())
898  MI->setFlag(MachineInstr::MIFlag::NoSWrap);
899 
900  if (Flags.hasExact())
901  MI->setFlag(MachineInstr::MIFlag::IsExact);
902  }
903 
904  // Emit all of the actual operands of this instruction, adding them to the
905  // instruction as appropriate.
906  bool HasOptPRefs = NumDefs > NumResults;
907  assert((!HasOptPRefs || !HasPhysRegOuts) &&
908  "Unable to cope with optional defs and phys regs defs!");
909  unsigned NumSkip = HasOptPRefs ? NumDefs - NumResults : 0;
910  for (unsigned i = NumSkip; i != NodeOperands; ++i)
911  AddOperand(MIB, Node->getOperand(i), i-NumSkip+NumDefs, &II,
912  VRBaseMap, /*IsDebug=*/false, IsClone, IsCloned);
913 
914  // Add scratch registers as implicit def and early clobber
915  if (ScratchRegs)
916  for (unsigned i = 0; ScratchRegs[i]; ++i)
917  MIB.addReg(ScratchRegs[i], RegState::ImplicitDefine |
919 
920  // Set the memory reference descriptions of this instruction now that it is
921  // part of the function.
922  MIB.setMemRefs(cast<MachineSDNode>(Node)->memoperands());
923 
924  // Insert the instruction into position in the block. This needs to
925  // happen before any custom inserter hook is called so that the
926  // hook knows where in the block to insert the replacement code.
927  MBB->insert(InsertPos, MIB);
928 
929  // The MachineInstr may also define physregs instead of virtregs. These
930  // physreg values can reach other instructions in different ways:
931  //
932  // 1. When there is a use of a Node value beyond the explicitly defined
933  // virtual registers, we emit a CopyFromReg for one of the implicitly
934  // defined physregs. This only happens when HasPhysRegOuts is true.
935  //
936  // 2. A CopyFromReg reading a physreg may be glued to this instruction.
937  //
938  // 3. A glued instruction may implicitly use a physreg.
939  //
940  // 4. A glued instruction may use a RegisterSDNode operand.
941  //
942  // Collect all the used physreg defs, and make sure that any unused physreg
943  // defs are marked as dead.
944  SmallVector<unsigned, 8> UsedRegs;
945 
946  // Additional results must be physical register defs.
947  if (HasPhysRegOuts) {
948  for (unsigned i = NumDefs; i < NumResults; ++i) {
949  unsigned Reg = II.getImplicitDefs()[i - NumDefs];
950  if (!Node->hasAnyUseOfValue(i))
951  continue;
952  // This implicitly defined physreg has a use.
953  UsedRegs.push_back(Reg);
954  EmitCopyFromReg(Node, i, IsClone, IsCloned, Reg, VRBaseMap);
955  }
956  }
957 
958  // Scan the glue chain for any used physregs.
959  if (Node->getValueType(Node->getNumValues()-1) == MVT::Glue) {
960  for (SDNode *F = Node->getGluedUser(); F; F = F->getGluedUser()) {
961  if (F->getOpcode() == ISD::CopyFromReg) {
962  UsedRegs.push_back(cast<RegisterSDNode>(F->getOperand(1))->getReg());
963  continue;
964  } else if (F->getOpcode() == ISD::CopyToReg) {
965  // Skip CopyToReg nodes that are internal to the glue chain.
966  continue;
967  }
968  // Collect declared implicit uses.
969  const MCInstrDesc &MCID = TII->get(F->getMachineOpcode());
970  UsedRegs.append(MCID.getImplicitUses(),
971  MCID.getImplicitUses() + MCID.getNumImplicitUses());
972  // In addition to declared implicit uses, we must also check for
973  // direct RegisterSDNode operands.
974  for (unsigned i = 0, e = F->getNumOperands(); i != e; ++i)
975  if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(F->getOperand(i))) {
976  unsigned Reg = R->getReg();
978  UsedRegs.push_back(Reg);
979  }
980  }
981  }
982 
983  // Finally mark unused registers as dead.
984  if (!UsedRegs.empty() || II.getImplicitDefs() || II.hasOptionalDef())
985  MIB->setPhysRegsDeadExcept(UsedRegs, *TRI);
986 
987  // Run post-isel target hook to adjust this instruction if needed.
988  if (II.hasPostISelHook())
989  TLI->AdjustInstrPostInstrSelection(*MIB, Node);
990 }
991 
992 /// EmitSpecialNode - Generate machine code for a target-independent node and
993 /// needed dependencies.
994 void InstrEmitter::
995 EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned,
996  DenseMap<SDValue, unsigned> &VRBaseMap) {
997  switch (Node->getOpcode()) {
998  default:
999 #ifndef NDEBUG
1000  Node->dump();
1001 #endif
1002  llvm_unreachable("This target-independent node should have been selected!");
1003  case ISD::EntryToken:
1004  llvm_unreachable("EntryToken should have been excluded from the schedule!");
1005  case ISD::MERGE_VALUES:
1006  case ISD::TokenFactor: // fall thru
1007  break;
1008  case ISD::CopyToReg: {
1009  unsigned SrcReg;
1010  SDValue SrcVal = Node->getOperand(2);
1011  if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(SrcVal))
1012  SrcReg = R->getReg();
1013  else
1014  SrcReg = getVR(SrcVal, VRBaseMap);
1015 
1016  unsigned DestReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
1017  if (SrcReg == DestReg) // Coalesced away the copy? Ignore.
1018  break;
1019 
1020  BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
1021  DestReg).addReg(SrcReg);
1022  break;
1023  }
1024  case ISD::CopyFromReg: {
1025  unsigned SrcReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
1026  EmitCopyFromReg(Node, 0, IsClone, IsCloned, SrcReg, VRBaseMap);
1027  break;
1028  }
1029  case ISD::EH_LABEL:
1030  case ISD::ANNOTATION_LABEL: {
1031  unsigned Opc = (Node->getOpcode() == ISD::EH_LABEL)
1034  MCSymbol *S = cast<LabelSDNode>(Node)->getLabel();
1035  BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
1036  TII->get(Opc)).addSym(S);
1037  break;
1038  }
1039 
1040  case ISD::LIFETIME_START:
1041  case ISD::LIFETIME_END: {
1042  unsigned TarOp = (Node->getOpcode() == ISD::LIFETIME_START) ?
1044 
1046  BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TarOp))
1047  .addFrameIndex(FI->getIndex());
1048  break;
1049  }
1050 
1051  case ISD::INLINEASM:
1052  case ISD::INLINEASM_BR: {
1053  unsigned NumOps = Node->getNumOperands();
1054  if (Node->getOperand(NumOps-1).getValueType() == MVT::Glue)
1055  --NumOps; // Ignore the glue operand.
1056 
1057  // Create the inline asm machine instruction.
1058  unsigned TgtOpc = Node->getOpcode() == ISD::INLINEASM_BR
1061  MachineInstrBuilder MIB =
1062  BuildMI(*MF, Node->getDebugLoc(), TII->get(TgtOpc));
1063 
1064  // Add the asm string as an external symbol operand.
1065  SDValue AsmStrV = Node->getOperand(InlineAsm::Op_AsmString);
1066  const char *AsmStr = cast<ExternalSymbolSDNode>(AsmStrV)->getSymbol();
1067  MIB.addExternalSymbol(AsmStr);
1068 
1069  // Add the HasSideEffect, isAlignStack, AsmDialect, MayLoad and MayStore
1070  // bits.
1071  int64_t ExtraInfo =
1072  cast<ConstantSDNode>(Node->getOperand(InlineAsm::Op_ExtraInfo))->
1073  getZExtValue();
1074  MIB.addImm(ExtraInfo);
1075 
1076  // Remember to operand index of the group flags.
1077  SmallVector<unsigned, 8> GroupIdx;
1078 
1079  // Remember registers that are part of early-clobber defs.
1080  SmallVector<unsigned, 8> ECRegs;
1081 
1082  // Add all of the operand registers to the instruction.
1083  for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
1084  unsigned Flags =
1085  cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue();
1086  const unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
1087 
1088  GroupIdx.push_back(MIB->getNumOperands());
1089  MIB.addImm(Flags);
1090  ++i; // Skip the ID value.
1091 
1092  switch (InlineAsm::getKind(Flags)) {
1093  default: llvm_unreachable("Bad flags!");
1095  for (unsigned j = 0; j != NumVals; ++j, ++i) {
1096  unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
1097  // FIXME: Add dead flags for physical and virtual registers defined.
1098  // For now, mark physical register defs as implicit to help fast
1099  // regalloc. This makes inline asm look a lot like calls.
1100  MIB.addReg(Reg, RegState::Define |
1102  }
1103  break;
1106  for (unsigned j = 0; j != NumVals; ++j, ++i) {
1107  unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
1110  ECRegs.push_back(Reg);
1111  }
1112  break;
1113  case InlineAsm::Kind_RegUse: // Use of register.
1114  case InlineAsm::Kind_Imm: // Immediate.
1115  case InlineAsm::Kind_Mem: // Addressing mode.
1116  // The addressing mode has been selected, just add all of the
1117  // operands to the machine instruction.
1118  for (unsigned j = 0; j != NumVals; ++j, ++i)
1119  AddOperand(MIB, Node->getOperand(i), 0, nullptr, VRBaseMap,
1120  /*IsDebug=*/false, IsClone, IsCloned);
1121 
1122  // Manually set isTied bits.
1124  unsigned DefGroup = 0;
1125  if (InlineAsm::isUseOperandTiedToDef(Flags, DefGroup)) {
1126  unsigned DefIdx = GroupIdx[DefGroup] + 1;
1127  unsigned UseIdx = GroupIdx.back() + 1;
1128  for (unsigned j = 0; j != NumVals; ++j)
1129  MIB->tieOperands(DefIdx + j, UseIdx + j);
1130  }
1131  }
1132  break;
1133  }
1134  }
1135 
1136  // GCC inline assembly allows input operands to also be early-clobber
1137  // output operands (so long as the operand is written only after it's
1138  // used), but this does not match the semantics of our early-clobber flag.
1139  // If an early-clobber operand register is also an input operand register,
1140  // then remove the early-clobber flag.
1141  for (unsigned Reg : ECRegs) {
1142  if (MIB->readsRegister(Reg, TRI)) {
1143  MachineOperand *MO =
1144  MIB->findRegisterDefOperand(Reg, false, false, TRI);
1145  assert(MO && "No def operand for clobbered register?");
1146  MO->setIsEarlyClobber(false);
1147  }
1148  }
1149 
1150  // Get the mdnode from the asm if it exists and add it to the instruction.
1152  const MDNode *MD = cast<MDNodeSDNode>(MDV)->getMD();
1153  if (MD)
1154  MIB.addMetadata(MD);
1155 
1156  MBB->insert(InsertPos, MIB);
1157  break;
1158  }
1159  }
1160 }
1161 
1162 /// InstrEmitter - Construct an InstrEmitter and set it to start inserting
1163 /// at the given position in the given block.
1165  MachineBasicBlock::iterator insertpos)
1166  : MF(mbb->getParent()), MRI(&MF->getRegInfo()),
1167  TII(MF->getSubtarget().getInstrInfo()),
1168  TRI(MF->getSubtarget().getRegisterInfo()),
1169  TLI(MF->getSubtarget().getTargetLowering()), MBB(mbb),
1170  InsertPos(insertpos) {}
ANNOTATION_LABEL - Represents a mid basic block label used by annotations.
Definition: ISDOpcodes.h:682
uint64_t CallInst * C
unsigned getNumImplicitUses() const
Return the number of implicit uses this instruction has.
Definition: MCInstrDesc.h:526
const TargetRegisterClass * getCommonSubClass(const TargetRegisterClass *A, const TargetRegisterClass *B, const MVT::SimpleValueType SVT=MVT::SimpleValueType::Any) const
Find the largest common subclass of A and B.
const MachineInstrBuilder & addMetadata(const MDNode *MD) const
MachineOperand * findRegisterDefOperand(unsigned Reg, bool isDead=false, bool Overlap=false, const TargetRegisterInfo *TRI=nullptr)
Wrapper for findRegisterDefOperandIdx, it returns a pointer to the MachineOperand rather than an inde...
constexpr char Align[]
Key for Kernel::Arg::Metadata::mAlign.
EVT getValueType() const
Return the ValueType of the referenced return value.
The MachineConstantPool class keeps track of constants referenced by a function which must be spilled...
bool hasNoSignedZeros() const
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
InstrEmitter(MachineBasicBlock *mbb, MachineBasicBlock::iterator insertpos)
InstrEmitter - Construct an InstrEmitter and set it to start inserting at the given position in the g...
const TargetRegisterClass * getRegClass(unsigned Reg) const
Return the register class of the specified virtual register.
unsigned getNumImplicitDefs() const
Return the number of implicit defs this instruct has.
Definition: MCInstrDesc.h:548
This class represents lattice values for constants.
Definition: AllocatorList.h:23
SDNode * getSDNode() const
Returns the SDNode* for a register ref.
bool isInvalidated() const
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
void push_back(const T &Elt)
Definition: SmallVector.h:211
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
const MCPhysReg * getImplicitUses() const
Return a list of registers that are potentially read by any instance of this machine instruction...
Definition: MCInstrDesc.h:523
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
void setIsEmitted()
setIsEmitted / isEmitted - Getter/Setter for flag indicating that this SDDbgValue has been emitted to...
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
unsigned Reg
Completely target-dependent object reference.
const Value * getConst() const
Returns the Value* for a constant.
static unsigned CountResults(SDNode *Node)
CountResults - The results of target nodes have register or immediate operands first, then an optional chain, and optional flag operands (which do not go into the machine instrs.)
virtual const TargetRegisterClass * getRegClassFor(MVT VT) const
Return the register class that should be used for the specified value type.
A debug info location.
Definition: DebugLoc.h:33
Metadata node.
Definition: Metadata.h:863
MVT getSimpleValueType(unsigned ResNo) const
Return the type of a specified result as a simple type.
F(f)
const SDNodeFlags getFlags() const
SDNode * getNode() const
get the SDNode which holds the desired result
const MachineInstrBuilder & addGlobalAddress(const GlobalValue *GV, int64_t Offset=0, unsigned char TargetFlags=0) const
const MachineInstrBuilder & addTargetIndex(unsigned Idx, int64_t Offset=0, unsigned char TargetFlags=0) const
const DebugLoc & getDebugLoc() const
Return the source location info.
EntryToken - This is the marker used to indicate the start of a region.
Definition: ISDOpcodes.h:44
static bool isUseOperandTiedToDef(unsigned Flag, unsigned &Idx)
isUseOperandTiedToDef - Return true if the flag of the inline asm operand indicates it is an use oper...
Definition: InlineAsm.h:341
bool hasOneUse() const
Return true if there is exactly one node using value ResNo of Node.
Value is a virtual register.
const DebugLoc & getDebugLoc() const
unsigned getResNo() const
Returns the ResNo for a register ref.
const TargetRegisterClass * getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
bool hasApproximateFuncs() const
unsigned getVReg() const
Returns the Virtual Register for a VReg.
const unsigned MinRCSize
MinRCSize - Smallest register class we allow when constraining virtual registers. ...
std::pair< iterator, bool > insert(const std::pair< KeyT, ValueT > &KV)
Definition: DenseMap.h:221
bool hasOneUse() const
Return true if there is exactly one use of this node.
unsigned getFrameIx() const
Returns the FrameIx for a stack object.
This file declares the MachineConstantPool class which is an abstract constant pool to keep track of ...
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:210
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:411
const TargetRegisterClass * getRegClass(const MCInstrDesc &MCID, unsigned OpNum, const TargetRegisterInfo *TRI, const MachineFunction &MF) const
Given a machine instruction descriptor, returns the register class constraint for OpNum...
CopyToReg - This node has three operands: a chain, a register number to set to this value...
Definition: ISDOpcodes.h:169
unsigned SubReg
SimpleValueType SimpleTy
virtual const TargetRegisterClass * getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const
Returns the largest legal sub-class of RC that supports the sub-register index Idx.
INLINEASM - Represents an inline asm block.
Definition: ISDOpcodes.h:668
MachineInstr * getVRegDef(unsigned Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
void setIsEarlyClobber(bool Val=true)
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:405
Value is contents of a stack location.
void clearKillFlags(unsigned Reg) const
clearKillFlags - Iterate over all the uses of the given register and clear the kill flag from the Mac...
DIVariable * getVariable() const
Returns the DIVariable pointer for the variable.
const MachineInstrBuilder & addFPImm(const ConstantFP *Val) const
DbgValueKind getKind() const
Returns the kind.
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
bool isTypeLegalForClass(const TargetRegisterClass &RC, MVT T) const
Return true if the given TargetRegisterClass has the ValueType T.
Expected< const typename ELFT::Sym * > getSymbol(typename ELFT::SymRange Symbols, uint32_t Index)
Definition: ELF.h:336
const TargetRegisterClass * constrainRegClass(unsigned Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
Value * getOperand(unsigned i) const
Definition: User.h:169
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
unsigned getKillRegState(bool B)
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
unsigned getDebugRegState(bool B)
bool hasAllowReciprocal() const
This corresponds to the llvm.lifetime.
Definition: ISDOpcodes.h:850
MVT getSimpleValueType() const
Return the simple ValueType of the referenced return value.
bool hasAllowContract() const
unsigned getDefRegState(bool B)
unsigned getNumValues() const
Return the number of values defined/returned by this operator.
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
const MCPhysReg * getImplicitDefs() const
Return a list of registers that are potentially written by any instance of this machine instruction...
Definition: MCInstrDesc.h:545
use_iterator use_begin() const
Provide iteration support to walk over all uses of an SDNode.
const MachineInstrBuilder & addBlockAddress(const BlockAddress *BA, int64_t Offset=0, unsigned char TargetFlags=0) const
Machine Value Type.
const MachineInstrBuilder & addCImm(const ConstantInt *Val) const
bool isOptionalDef() const
Set if this operand is a optional def.
Definition: MCInstrDesc.h:95
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
bool isVariadic() const
Return true if this instruction can have a variable number of operands.
Definition: MCInstrDesc.h:234
bool hasAnyUseOfValue(unsigned Value) const
Return true if there are any use of the indicated value.
bool isMachineOpcode() const
SDNode * getGluedUser() const
If this node has a glue value with a user, return the user (there is at most one).
const SDValue & getOperand(unsigned Num) const
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:263
unsigned getSubReg(unsigned Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo...
static unsigned getNumOperandRegisters(unsigned Flag)
getNumOperandRegisters - Extract the number of registers field from the inline asm operand flag...
Definition: InlineAsm.h:335
unsigned getPrefTypeAlignment(Type *Ty) const
Returns the preferred stack/global alignment for the specified type.
Definition: DataLayout.cpp:759
void setFlag(MIFlag Flag)
Set a MI flag.
Definition: MachineInstr.h:299
unsigned getMachineOpcode() const
bool hasNoNaNs() const
const MachineInstrBuilder & addRegMask(const uint32_t *Mask) const
static unsigned getKind(unsigned Flags)
Definition: InlineAsm.h:324
virtual const TargetRegisterClass * getMatchingSuperRegClass(const TargetRegisterClass *A, const TargetRegisterClass *B, unsigned Idx) const
Return a subclass of the specified register class A so that each register in it has a sub-register of...
const MachineInstrBuilder & addSym(MCSymbol *Sym, unsigned char TargetFlags=0) const
MachineConstantPool * getConstantPool()
getConstantPool - Return the constant pool object for the current function.
const MachineInstrBuilder & addFrameIndex(int Idx) const
DebugLoc getDebugLoc() const
Returns the DebugLoc.
unsigned getNumOperands() const
Return the number of values used by this operation.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
bool hasSubClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a sub-class of or equal to this class.
EH_LABEL - Represents a label in mid basic block used to track locations needed for debug and excepti...
Definition: ISDOpcodes.h:676
virtual const MCPhysReg * getScratchRegisters(CallingConv::ID CC) const
Returns a 0 terminated array of registers that can be safely used as scratch registers.
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specific constraint if it is set.
Definition: MCInstrDesc.h:187
TokenFactor - This node takes multiple tokens as input and produces a single token result...
Definition: ISDOpcodes.h:49
void dump() const
Dump this node, for debugging.
DIExpression * getExpression() const
Returns the DIExpression pointer for the expression.
unsigned getNumOperands() const
Definition: User.h:191
This is the shared class of boolean and integer constants.
Definition: Constants.h:83
DebugLoc getDebugLoc() const
Returns the DebugLoc.
Value is a constant.
MachineOperand class - Representation of each machine instruction operand.
MachineInstrBuilder MachineInstrBuilder & DefMI
int getCopyCost() const
Return the cost of copying a value between two registers in this class.
const MachineInstrBuilder & addConstantPoolIndex(unsigned Idx, int Offset=0, unsigned char TargetFlags=0) const
virtual bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg, unsigned &SubIdx) const
Return true if the instruction is a "coalescable" extension instruction.
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Definition: MCInstrDesc.h:225
Represents one node in the SelectionDAG.
virtual void AdjustInstrPostInstrSelection(MachineInstr &MI, SDNode *Node) const
This method should be implemented by targets that mark instructions with the &#39;hasPostISelHook&#39; flag...
bool isTypeLegal(EVT VT) const
Return true if the target has native support for the specified value type.
iterator_range< use_iterator > uses()
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
bool readsRegister(unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr reads the specified register.
void append(in_iter in_start, in_iter in_end)
Add the specified range to the end of the SmallVector.
Definition: SmallVector.h:387
bool hasNoSignedWrap() const
uint64_t getTypeAllocSize(Type *Ty) const
Returns the offset in bytes between successive objects of the specified type, including alignment pad...
Definition: DataLayout.h:461
Representation of each machine instruction.
Definition: MachineInstr.h:63
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
These are IR-level optimization flags that may be propagated to SDNodes.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Value is the result of an expression.
Holds the information from a dbg_label node through SDISel.
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:55
static unsigned countOperands(SDNode *Node, unsigned NumExpUses, unsigned &NumImpUses)
countOperands - The inputs to target nodes have any actual inputs first, followed by an optional chai...
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:44
const MachineInstrBuilder & addExternalSymbol(const char *FnName, unsigned char TargetFlags=0) const
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
unsigned getImplRegState(bool B)
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:322
MachineInstr * EmitDbgLabel(SDDbgLabel *SD)
Generate machine instruction for a dbg_label node.
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
bool isAllocatable() const
Return true if this register class may be used to create virtual registers.
MDNode * getLabel() const
Returns the MDNode pointer for the label.
CopyFromReg - This node indicates that the input value is a virtual or physical register that is defi...
Definition: ISDOpcodes.h:174
const TargetRegisterClass * getMinimalPhysRegClass(unsigned Reg, MVT VT=MVT::Other) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
bool isReg() const
isReg - Tests if this is a MO_Register operand.
const MachineInstrBuilder & addJumpTableIndex(unsigned Idx, unsigned char TargetFlags=0) const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
unsigned getReg() const
MachineInstr * EmitDbgValue(SDDbgValue *SD, DenseMap< SDValue, unsigned > &VRBaseMap)
EmitDbgValue - Generate machine instruction for a dbg_value node.
INLINEASM_BR - Terminator version of inline asm. Used by asm-goto.
Definition: ISDOpcodes.h:671
const TargetRegisterClass * getAllocatableClass(const TargetRegisterClass *RC) const
Return the maximal subclass of the given register class that is allocatable or NULL.
LLVM Value Representation.
Definition: Value.h:72
uint64_t getConstantOperandVal(unsigned Num) const
Helper method returns the integer value of a ConstantSDNode operand.
unsigned getResNo() const
get the index which selects a specific result in the SDNode
unsigned getMachineOpcode() const
This may only be called if isMachineOpcode returns true.
bool hasNoUnsignedWrap() const
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:174
static const Function * getParent(const Value *V)
bool hasAllowReassociation() const
IRTranslator LLVM IR MI
bool hasNoInfs() const
void setRegClass(unsigned Reg, const TargetRegisterClass *RC)
setRegClass - Set the register class of the specified virtual register.
MERGE_VALUES - This node takes multiple discrete operands and returns them all as its individual resu...
Definition: ISDOpcodes.h:197
unsigned getNumOperands() const
bool isIndirect() const
Returns whether this is an indirect value.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
uint64_t getZExtValue() const
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:413
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
Holds the information from a dbg_value node through SDISel.
unsigned getConstantPoolIndex(const Constant *C, unsigned Alignment)
getConstantPoolIndex - Create a new entry in the constant pool or return an existing one...
unsigned createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
This file describes how to lower LLVM code to machine code.
bool isImplicit() const
void tieOperands(unsigned DefIdx, unsigned UseIdx)
Add a tie between the register operands at DefIdx and UseIdx.