LLVM  9.0.0svn
HexagonInstrInfo.cpp
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1 //===- HexagonInstrInfo.cpp - Hexagon Instruction Information -------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the Hexagon implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "HexagonInstrInfo.h"
14 #include "Hexagon.h"
15 #include "HexagonFrameLowering.h"
17 #include "HexagonRegisterInfo.h"
18 #include "HexagonSubtarget.h"
19 #include "llvm/ADT/ArrayRef.h"
20 #include "llvm/ADT/SmallPtrSet.h"
21 #include "llvm/ADT/SmallVector.h"
22 #include "llvm/ADT/StringRef.h"
41 #include "llvm/IR/DebugLoc.h"
42 #include "llvm/MC/MCAsmInfo.h"
43 #include "llvm/MC/MCInstrDesc.h"
45 #include "llvm/MC/MCRegisterInfo.h"
48 #include "llvm/Support/Debug.h"
54 #include <cassert>
55 #include <cctype>
56 #include <cstdint>
57 #include <cstring>
58 #include <iterator>
59 #include <string>
60 #include <utility>
61 
62 using namespace llvm;
63 
64 #define DEBUG_TYPE "hexagon-instrinfo"
65 
66 #define GET_INSTRINFO_CTOR_DTOR
67 #define GET_INSTRMAP_INFO
69 #include "HexagonGenDFAPacketizer.inc"
70 #include "HexagonGenInstrInfo.inc"
71 
72 cl::opt<bool> ScheduleInlineAsm("hexagon-sched-inline-asm", cl::Hidden,
73  cl::init(false), cl::desc("Do not consider inline-asm a scheduling/"
74  "packetization boundary."));
75 
76 static cl::opt<bool> EnableBranchPrediction("hexagon-enable-branch-prediction",
77  cl::Hidden, cl::init(true), cl::desc("Enable branch prediction"));
78 
79 static cl::opt<bool> DisableNVSchedule("disable-hexagon-nv-schedule",
81  cl::desc("Disable schedule adjustment for new value stores."));
82 
84  "enable-timing-class-latency", cl::Hidden, cl::init(false),
85  cl::desc("Enable timing class latency"));
86 
88  "enable-alu-forwarding", cl::Hidden, cl::init(true),
89  cl::desc("Enable vec alu forwarding"));
90 
92  "enable-acc-forwarding", cl::Hidden, cl::init(true),
93  cl::desc("Enable vec acc forwarding"));
94 
95 static cl::opt<bool> BranchRelaxAsmLarge("branch-relax-asm-large",
96  cl::init(true), cl::Hidden, cl::ZeroOrMore, cl::desc("branch relax asm"));
97 
98 static cl::opt<bool> UseDFAHazardRec("dfa-hazard-rec",
100  cl::desc("Use the DFA based hazard recognizer."));
101 
102 /// Constants for Hexagon instructions.
103 const int Hexagon_MEMW_OFFSET_MAX = 4095;
104 const int Hexagon_MEMW_OFFSET_MIN = -4096;
105 const int Hexagon_MEMD_OFFSET_MAX = 8191;
106 const int Hexagon_MEMD_OFFSET_MIN = -8192;
107 const int Hexagon_MEMH_OFFSET_MAX = 2047;
108 const int Hexagon_MEMH_OFFSET_MIN = -2048;
109 const int Hexagon_MEMB_OFFSET_MAX = 1023;
110 const int Hexagon_MEMB_OFFSET_MIN = -1024;
111 const int Hexagon_ADDI_OFFSET_MAX = 32767;
112 const int Hexagon_ADDI_OFFSET_MIN = -32768;
113 
114 // Pin the vtable to this file.
115 void HexagonInstrInfo::anchor() {}
116 
118  : HexagonGenInstrInfo(Hexagon::ADJCALLSTACKDOWN, Hexagon::ADJCALLSTACKUP),
119  Subtarget(ST) {}
120 
121 static bool isIntRegForSubInst(unsigned Reg) {
122  return (Reg >= Hexagon::R0 && Reg <= Hexagon::R7) ||
123  (Reg >= Hexagon::R16 && Reg <= Hexagon::R23);
124 }
125 
126 static bool isDblRegForSubInst(unsigned Reg, const HexagonRegisterInfo &HRI) {
127  return isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::isub_lo)) &&
128  isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::isub_hi));
129 }
130 
131 /// Calculate number of instructions excluding the debug instructions.
134  unsigned Count = 0;
135  for (; MIB != MIE; ++MIB) {
136  if (!MIB->isDebugInstr())
137  ++Count;
138  }
139  return Count;
140 }
141 
142 /// Find the hardware loop instruction used to set-up the specified loop.
143 /// On Hexagon, we have two instructions used to set-up the hardware loop
144 /// (LOOP0, LOOP1) with corresponding endloop (ENDLOOP0, ENDLOOP1) instructions
145 /// to indicate the end of a loop.
147  unsigned EndLoopOp, MachineBasicBlock *TargetBB,
148  SmallPtrSet<MachineBasicBlock *, 8> &Visited) const {
149  unsigned LOOPi;
150  unsigned LOOPr;
151  if (EndLoopOp == Hexagon::ENDLOOP0) {
152  LOOPi = Hexagon::J2_loop0i;
153  LOOPr = Hexagon::J2_loop0r;
154  } else { // EndLoopOp == Hexagon::EndLOOP1
155  LOOPi = Hexagon::J2_loop1i;
156  LOOPr = Hexagon::J2_loop1r;
157  }
158 
159  // The loop set-up instruction will be in a predecessor block
160  for (MachineBasicBlock *PB : BB->predecessors()) {
161  // If this has been visited, already skip it.
162  if (!Visited.insert(PB).second)
163  continue;
164  if (PB == BB)
165  continue;
166  for (auto I = PB->instr_rbegin(), E = PB->instr_rend(); I != E; ++I) {
167  unsigned Opc = I->getOpcode();
168  if (Opc == LOOPi || Opc == LOOPr)
169  return &*I;
170  // We've reached a different loop, which means the loop01 has been
171  // removed.
172  if (Opc == EndLoopOp && I->getOperand(0).getMBB() != TargetBB)
173  return nullptr;
174  }
175  // Check the predecessors for the LOOP instruction.
176  if (MachineInstr *Loop = findLoopInstr(PB, EndLoopOp, TargetBB, Visited))
177  return Loop;
178  }
179  return nullptr;
180 }
181 
182 /// Gather register def/uses from MI.
183 /// This treats possible (predicated) defs as actually happening ones
184 /// (conservatively).
185 static inline void parseOperands(const MachineInstr &MI,
187  Defs.clear();
188  Uses.clear();
189 
190  for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
191  const MachineOperand &MO = MI.getOperand(i);
192 
193  if (!MO.isReg())
194  continue;
195 
196  unsigned Reg = MO.getReg();
197  if (!Reg)
198  continue;
199 
200  if (MO.isUse())
201  Uses.push_back(MO.getReg());
202 
203  if (MO.isDef())
204  Defs.push_back(MO.getReg());
205  }
206 }
207 
208 // Position dependent, so check twice for swap.
209 static bool isDuplexPairMatch(unsigned Ga, unsigned Gb) {
210  switch (Ga) {
212  default:
213  return false;
214  case HexagonII::HSIG_L1:
215  return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_A);
216  case HexagonII::HSIG_L2:
217  return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_L2 ||
218  Gb == HexagonII::HSIG_A);
219  case HexagonII::HSIG_S1:
220  return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_L2 ||
221  Gb == HexagonII::HSIG_S1 || Gb == HexagonII::HSIG_A);
222  case HexagonII::HSIG_S2:
223  return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_L2 ||
224  Gb == HexagonII::HSIG_S1 || Gb == HexagonII::HSIG_S2 ||
225  Gb == HexagonII::HSIG_A);
226  case HexagonII::HSIG_A:
227  return (Gb == HexagonII::HSIG_A);
229  return (Gb == HexagonII::HSIG_Compound);
230  }
231  return false;
232 }
233 
234 /// isLoadFromStackSlot - If the specified machine instruction is a direct
235 /// load from a stack slot, return the virtual or physical register number of
236 /// the destination along with the FrameIndex of the loaded stack slot. If
237 /// not, return 0. This predicate must return 0 if the instruction has
238 /// any side effects other than loading from the stack slot.
240  int &FrameIndex) const {
241  switch (MI.getOpcode()) {
242  default:
243  break;
244  case Hexagon::L2_loadri_io:
245  case Hexagon::L2_loadrd_io:
246  case Hexagon::V6_vL32b_ai:
247  case Hexagon::V6_vL32b_nt_ai:
248  case Hexagon::V6_vL32Ub_ai:
249  case Hexagon::LDriw_pred:
250  case Hexagon::LDriw_ctr:
251  case Hexagon::PS_vloadrq_ai:
252  case Hexagon::PS_vloadrw_ai:
253  case Hexagon::PS_vloadrw_nt_ai: {
254  const MachineOperand OpFI = MI.getOperand(1);
255  if (!OpFI.isFI())
256  return 0;
257  const MachineOperand OpOff = MI.getOperand(2);
258  if (!OpOff.isImm() || OpOff.getImm() != 0)
259  return 0;
260  FrameIndex = OpFI.getIndex();
261  return MI.getOperand(0).getReg();
262  }
263 
264  case Hexagon::L2_ploadrit_io:
265  case Hexagon::L2_ploadrif_io:
266  case Hexagon::L2_ploadrdt_io:
267  case Hexagon::L2_ploadrdf_io: {
268  const MachineOperand OpFI = MI.getOperand(2);
269  if (!OpFI.isFI())
270  return 0;
271  const MachineOperand OpOff = MI.getOperand(3);
272  if (!OpOff.isImm() || OpOff.getImm() != 0)
273  return 0;
274  FrameIndex = OpFI.getIndex();
275  return MI.getOperand(0).getReg();
276  }
277  }
278 
279  return 0;
280 }
281 
282 /// isStoreToStackSlot - If the specified machine instruction is a direct
283 /// store to a stack slot, return the virtual or physical register number of
284 /// the source reg along with the FrameIndex of the loaded stack slot. If
285 /// not, return 0. This predicate must return 0 if the instruction has
286 /// any side effects other than storing to the stack slot.
288  int &FrameIndex) const {
289  switch (MI.getOpcode()) {
290  default:
291  break;
292  case Hexagon::S2_storerb_io:
293  case Hexagon::S2_storerh_io:
294  case Hexagon::S2_storeri_io:
295  case Hexagon::S2_storerd_io:
296  case Hexagon::V6_vS32b_ai:
297  case Hexagon::V6_vS32Ub_ai:
298  case Hexagon::STriw_pred:
299  case Hexagon::STriw_ctr:
300  case Hexagon::PS_vstorerq_ai:
301  case Hexagon::PS_vstorerw_ai: {
302  const MachineOperand &OpFI = MI.getOperand(0);
303  if (!OpFI.isFI())
304  return 0;
305  const MachineOperand &OpOff = MI.getOperand(1);
306  if (!OpOff.isImm() || OpOff.getImm() != 0)
307  return 0;
308  FrameIndex = OpFI.getIndex();
309  return MI.getOperand(2).getReg();
310  }
311 
312  case Hexagon::S2_pstorerbt_io:
313  case Hexagon::S2_pstorerbf_io:
314  case Hexagon::S2_pstorerht_io:
315  case Hexagon::S2_pstorerhf_io:
316  case Hexagon::S2_pstorerit_io:
317  case Hexagon::S2_pstorerif_io:
318  case Hexagon::S2_pstorerdt_io:
319  case Hexagon::S2_pstorerdf_io: {
320  const MachineOperand &OpFI = MI.getOperand(1);
321  if (!OpFI.isFI())
322  return 0;
323  const MachineOperand &OpOff = MI.getOperand(2);
324  if (!OpOff.isImm() || OpOff.getImm() != 0)
325  return 0;
326  FrameIndex = OpFI.getIndex();
327  return MI.getOperand(3).getReg();
328  }
329  }
330 
331  return 0;
332 }
333 
334 /// This function checks if the instruction or bundle of instructions
335 /// has load from stack slot and returns frameindex and machine memory
336 /// operand of that instruction if true.
338  const MachineInstr &MI,
340  if (MI.isBundle()) {
341  const MachineBasicBlock *MBB = MI.getParent();
343  for (++MII; MII != MBB->instr_end() && MII->isInsideBundle(); ++MII)
344  if (TargetInstrInfo::hasLoadFromStackSlot(*MII, Accesses))
345  return true;
346  return false;
347  }
348 
349  return TargetInstrInfo::hasLoadFromStackSlot(MI, Accesses);
350 }
351 
352 /// This function checks if the instruction or bundle of instructions
353 /// has store to stack slot and returns frameindex and machine memory
354 /// operand of that instruction if true.
356  const MachineInstr &MI,
358  if (MI.isBundle()) {
359  const MachineBasicBlock *MBB = MI.getParent();
361  for (++MII; MII != MBB->instr_end() && MII->isInsideBundle(); ++MII)
362  if (TargetInstrInfo::hasStoreToStackSlot(*MII, Accesses))
363  return true;
364  return false;
365  }
366 
367  return TargetInstrInfo::hasStoreToStackSlot(MI, Accesses);
368 }
369 
370 /// This function can analyze one/two way branching only and should (mostly) be
371 /// called by target independent side.
372 /// First entry is always the opcode of the branching instruction, except when
373 /// the Cond vector is supposed to be empty, e.g., when AnalyzeBranch fails, a
374 /// BB with only unconditional jump. Subsequent entries depend upon the opcode,
375 /// e.g. Jump_c p will have
376 /// Cond[0] = Jump_c
377 /// Cond[1] = p
378 /// HW-loop ENDLOOP:
379 /// Cond[0] = ENDLOOP
380 /// Cond[1] = MBB
381 /// New value jump:
382 /// Cond[0] = Hexagon::CMPEQri_f_Jumpnv_t_V4 -- specific opcode
383 /// Cond[1] = R
384 /// Cond[2] = Imm
386  MachineBasicBlock *&TBB,
387  MachineBasicBlock *&FBB,
389  bool AllowModify) const {
390  TBB = nullptr;
391  FBB = nullptr;
392  Cond.clear();
393 
394  // If the block has no terminators, it just falls into the block after it.
396  if (I == MBB.instr_begin())
397  return false;
398 
399  // A basic block may looks like this:
400  //
401  // [ insn
402  // EH_LABEL
403  // insn
404  // insn
405  // insn
406  // EH_LABEL
407  // insn ]
408  //
409  // It has two succs but does not have a terminator
410  // Don't know how to handle it.
411  do {
412  --I;
413  if (I->isEHLabel())
414  // Don't analyze EH branches.
415  return true;
416  } while (I != MBB.instr_begin());
417 
418  I = MBB.instr_end();
419  --I;
420 
421  while (I->isDebugInstr()) {
422  if (I == MBB.instr_begin())
423  return false;
424  --I;
425  }
426 
427  bool JumpToBlock = I->getOpcode() == Hexagon::J2_jump &&
428  I->getOperand(0).isMBB();
429  // Delete the J2_jump if it's equivalent to a fall-through.
430  if (AllowModify && JumpToBlock &&
431  MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
432  LLVM_DEBUG(dbgs() << "\nErasing the jump to successor block\n";);
433  I->eraseFromParent();
434  I = MBB.instr_end();
435  if (I == MBB.instr_begin())
436  return false;
437  --I;
438  }
439  if (!isUnpredicatedTerminator(*I))
440  return false;
441 
442  // Get the last instruction in the block.
443  MachineInstr *LastInst = &*I;
444  MachineInstr *SecondLastInst = nullptr;
445  // Find one more terminator if present.
446  while (true) {
447  if (&*I != LastInst && !I->isBundle() && isUnpredicatedTerminator(*I)) {
448  if (!SecondLastInst)
449  SecondLastInst = &*I;
450  else
451  // This is a third branch.
452  return true;
453  }
454  if (I == MBB.instr_begin())
455  break;
456  --I;
457  }
458 
459  int LastOpcode = LastInst->getOpcode();
460  int SecLastOpcode = SecondLastInst ? SecondLastInst->getOpcode() : 0;
461  // If the branch target is not a basic block, it could be a tail call.
462  // (It is, if the target is a function.)
463  if (LastOpcode == Hexagon::J2_jump && !LastInst->getOperand(0).isMBB())
464  return true;
465  if (SecLastOpcode == Hexagon::J2_jump &&
466  !SecondLastInst->getOperand(0).isMBB())
467  return true;
468 
469  bool LastOpcodeHasJMP_c = PredOpcodeHasJMP_c(LastOpcode);
470  bool LastOpcodeHasNVJump = isNewValueJump(*LastInst);
471 
472  if (LastOpcodeHasJMP_c && !LastInst->getOperand(1).isMBB())
473  return true;
474 
475  // If there is only one terminator instruction, process it.
476  if (LastInst && !SecondLastInst) {
477  if (LastOpcode == Hexagon::J2_jump) {
478  TBB = LastInst->getOperand(0).getMBB();
479  return false;
480  }
481  if (isEndLoopN(LastOpcode)) {
482  TBB = LastInst->getOperand(0).getMBB();
483  Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
484  Cond.push_back(LastInst->getOperand(0));
485  return false;
486  }
487  if (LastOpcodeHasJMP_c) {
488  TBB = LastInst->getOperand(1).getMBB();
489  Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
490  Cond.push_back(LastInst->getOperand(0));
491  return false;
492  }
493  // Only supporting rr/ri versions of new-value jumps.
494  if (LastOpcodeHasNVJump && (LastInst->getNumExplicitOperands() == 3)) {
495  TBB = LastInst->getOperand(2).getMBB();
496  Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
497  Cond.push_back(LastInst->getOperand(0));
498  Cond.push_back(LastInst->getOperand(1));
499  return false;
500  }
501  LLVM_DEBUG(dbgs() << "\nCant analyze " << printMBBReference(MBB)
502  << " with one jump\n";);
503  // Otherwise, don't know what this is.
504  return true;
505  }
506 
507  bool SecLastOpcodeHasJMP_c = PredOpcodeHasJMP_c(SecLastOpcode);
508  bool SecLastOpcodeHasNVJump = isNewValueJump(*SecondLastInst);
509  if (SecLastOpcodeHasJMP_c && (LastOpcode == Hexagon::J2_jump)) {
510  if (!SecondLastInst->getOperand(1).isMBB())
511  return true;
512  TBB = SecondLastInst->getOperand(1).getMBB();
513  Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
514  Cond.push_back(SecondLastInst->getOperand(0));
515  FBB = LastInst->getOperand(0).getMBB();
516  return false;
517  }
518 
519  // Only supporting rr/ri versions of new-value jumps.
520  if (SecLastOpcodeHasNVJump &&
521  (SecondLastInst->getNumExplicitOperands() == 3) &&
522  (LastOpcode == Hexagon::J2_jump)) {
523  TBB = SecondLastInst->getOperand(2).getMBB();
524  Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
525  Cond.push_back(SecondLastInst->getOperand(0));
526  Cond.push_back(SecondLastInst->getOperand(1));
527  FBB = LastInst->getOperand(0).getMBB();
528  return false;
529  }
530 
531  // If the block ends with two Hexagon:JMPs, handle it. The second one is not
532  // executed, so remove it.
533  if (SecLastOpcode == Hexagon::J2_jump && LastOpcode == Hexagon::J2_jump) {
534  TBB = SecondLastInst->getOperand(0).getMBB();
535  I = LastInst->getIterator();
536  if (AllowModify)
537  I->eraseFromParent();
538  return false;
539  }
540 
541  // If the block ends with an ENDLOOP, and J2_jump, handle it.
542  if (isEndLoopN(SecLastOpcode) && LastOpcode == Hexagon::J2_jump) {
543  TBB = SecondLastInst->getOperand(0).getMBB();
544  Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
545  Cond.push_back(SecondLastInst->getOperand(0));
546  FBB = LastInst->getOperand(0).getMBB();
547  return false;
548  }
549  LLVM_DEBUG(dbgs() << "\nCant analyze " << printMBBReference(MBB)
550  << " with two jumps";);
551  // Otherwise, can't handle this.
552  return true;
553 }
554 
556  int *BytesRemoved) const {
557  assert(!BytesRemoved && "code size not handled");
558 
559  LLVM_DEBUG(dbgs() << "\nRemoving branches out of " << printMBBReference(MBB));
561  unsigned Count = 0;
562  while (I != MBB.begin()) {
563  --I;
564  if (I->isDebugInstr())
565  continue;
566  // Only removing branches from end of MBB.
567  if (!I->isBranch())
568  return Count;
569  if (Count && (I->getOpcode() == Hexagon::J2_jump))
570  llvm_unreachable("Malformed basic block: unconditional branch not last");
571  MBB.erase(&MBB.back());
572  I = MBB.end();
573  ++Count;
574  }
575  return Count;
576 }
577 
579  MachineBasicBlock *TBB,
580  MachineBasicBlock *FBB,
582  const DebugLoc &DL,
583  int *BytesAdded) const {
584  unsigned BOpc = Hexagon::J2_jump;
585  unsigned BccOpc = Hexagon::J2_jumpt;
586  assert(validateBranchCond(Cond) && "Invalid branching condition");
587  assert(TBB && "insertBranch must not be told to insert a fallthrough");
588  assert(!BytesAdded && "code size not handled");
589 
590  // Check if reverseBranchCondition has asked to reverse this branch
591  // If we want to reverse the branch an odd number of times, we want
592  // J2_jumpf.
593  if (!Cond.empty() && Cond[0].isImm())
594  BccOpc = Cond[0].getImm();
595 
596  if (!FBB) {
597  if (Cond.empty()) {
598  // Due to a bug in TailMerging/CFG Optimization, we need to add a
599  // special case handling of a predicated jump followed by an
600  // unconditional jump. If not, Tail Merging and CFG Optimization go
601  // into an infinite loop.
602  MachineBasicBlock *NewTBB, *NewFBB;
604  auto Term = MBB.getFirstTerminator();
605  if (Term != MBB.end() && isPredicated(*Term) &&
606  !analyzeBranch(MBB, NewTBB, NewFBB, Cond, false) &&
607  MachineFunction::iterator(NewTBB) == ++MBB.getIterator()) {
609  removeBranch(MBB);
610  return insertBranch(MBB, TBB, nullptr, Cond, DL);
611  }
612  BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
613  } else if (isEndLoopN(Cond[0].getImm())) {
614  int EndLoopOp = Cond[0].getImm();
615  assert(Cond[1].isMBB());
616  // Since we're adding an ENDLOOP, there better be a LOOP instruction.
617  // Check for it, and change the BB target if needed.
619  MachineInstr *Loop = findLoopInstr(TBB, EndLoopOp, Cond[1].getMBB(),
620  VisitedBBs);
621  assert(Loop != nullptr && "Inserting an ENDLOOP without a LOOP");
622  Loop->getOperand(0).setMBB(TBB);
623  // Add the ENDLOOP after the finding the LOOP0.
624  BuildMI(&MBB, DL, get(EndLoopOp)).addMBB(TBB);
625  } else if (isNewValueJump(Cond[0].getImm())) {
626  assert((Cond.size() == 3) && "Only supporting rr/ri version of nvjump");
627  // New value jump
628  // (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset)
629  // (ins IntRegs:$src1, u5Imm:$src2, brtarget:$offset)
630  unsigned Flags1 = getUndefRegState(Cond[1].isUndef());
631  LLVM_DEBUG(dbgs() << "\nInserting NVJump for "
632  << printMBBReference(MBB););
633  if (Cond[2].isReg()) {
634  unsigned Flags2 = getUndefRegState(Cond[2].isUndef());
635  BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[1].getReg(), Flags1).
636  addReg(Cond[2].getReg(), Flags2).addMBB(TBB);
637  } else if(Cond[2].isImm()) {
638  BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[1].getReg(), Flags1).
639  addImm(Cond[2].getImm()).addMBB(TBB);
640  } else
641  llvm_unreachable("Invalid condition for branching");
642  } else {
643  assert((Cond.size() == 2) && "Malformed cond vector");
644  const MachineOperand &RO = Cond[1];
645  unsigned Flags = getUndefRegState(RO.isUndef());
646  BuildMI(&MBB, DL, get(BccOpc)).addReg(RO.getReg(), Flags).addMBB(TBB);
647  }
648  return 1;
649  }
650  assert((!Cond.empty()) &&
651  "Cond. cannot be empty when multiple branchings are required");
652  assert((!isNewValueJump(Cond[0].getImm())) &&
653  "NV-jump cannot be inserted with another branch");
654  // Special case for hardware loops. The condition is a basic block.
655  if (isEndLoopN(Cond[0].getImm())) {
656  int EndLoopOp = Cond[0].getImm();
657  assert(Cond[1].isMBB());
658  // Since we're adding an ENDLOOP, there better be a LOOP instruction.
659  // Check for it, and change the BB target if needed.
661  MachineInstr *Loop = findLoopInstr(TBB, EndLoopOp, Cond[1].getMBB(),
662  VisitedBBs);
663  assert(Loop != nullptr && "Inserting an ENDLOOP without a LOOP");
664  Loop->getOperand(0).setMBB(TBB);
665  // Add the ENDLOOP after the finding the LOOP0.
666  BuildMI(&MBB, DL, get(EndLoopOp)).addMBB(TBB);
667  } else {
668  const MachineOperand &RO = Cond[1];
669  unsigned Flags = getUndefRegState(RO.isUndef());
670  BuildMI(&MBB, DL, get(BccOpc)).addReg(RO.getReg(), Flags).addMBB(TBB);
671  }
672  BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
673 
674  return 2;
675 }
676 
677 /// Analyze the loop code to find the loop induction variable and compare used
678 /// to compute the number of iterations. Currently, we analyze loop that are
679 /// controlled using hardware loops. In this case, the induction variable
680 /// instruction is null. For all other cases, this function returns true, which
681 /// means we're unable to analyze it.
683  MachineInstr *&IndVarInst,
684  MachineInstr *&CmpInst) const {
685 
686  MachineBasicBlock *LoopEnd = L.getBottomBlock();
688  // We really "analyze" only hardware loops right now.
689  if (I != LoopEnd->end() && isEndLoopN(I->getOpcode())) {
690  IndVarInst = nullptr;
691  CmpInst = &*I;
692  return false;
693  }
694  return true;
695 }
696 
697 /// Generate code to reduce the loop iteration by one and check if the loop is
698 /// finished. Return the value/register of the new loop count. this function
699 /// assumes the nth iteration is peeled first.
701  MachineInstr *IndVar, MachineInstr &Cmp,
704  unsigned Iter, unsigned MaxIter) const {
705  // We expect a hardware loop currently. This means that IndVar is set
706  // to null, and the compare is the ENDLOOP instruction.
707  assert((!IndVar) && isEndLoopN(Cmp.getOpcode())
708  && "Expecting a hardware loop");
709  MachineFunction *MF = MBB.getParent();
710  DebugLoc DL = Cmp.getDebugLoc();
712  MachineInstr *Loop = findLoopInstr(&MBB, Cmp.getOpcode(),
713  Cmp.getOperand(0).getMBB(), VisitedBBs);
714  if (!Loop)
715  return 0;
716  // If the loop trip count is a compile-time value, then just change the
717  // value.
718  if (Loop->getOpcode() == Hexagon::J2_loop0i ||
719  Loop->getOpcode() == Hexagon::J2_loop1i) {
720  int64_t Offset = Loop->getOperand(1).getImm();
721  if (Offset <= 1)
722  Loop->eraseFromParent();
723  else
724  Loop->getOperand(1).setImm(Offset - 1);
725  return Offset - 1;
726  }
727  // The loop trip count is a run-time value. We generate code to subtract
728  // one from the trip count, and update the loop instruction.
729  assert(Loop->getOpcode() == Hexagon::J2_loop0r && "Unexpected instruction");
730  unsigned LoopCount = Loop->getOperand(1).getReg();
731  // Check if we're done with the loop.
732  unsigned LoopEnd = createVR(MF, MVT::i1);
733  MachineInstr *NewCmp = BuildMI(&MBB, DL, get(Hexagon::C2_cmpgtui), LoopEnd).
734  addReg(LoopCount).addImm(1);
735  unsigned NewLoopCount = createVR(MF, MVT::i32);
736  MachineInstr *NewAdd = BuildMI(&MBB, DL, get(Hexagon::A2_addi), NewLoopCount).
737  addReg(LoopCount).addImm(-1);
738  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
739  // Update the previously generated instructions with the new loop counter.
741  E = PrevInsts.end(); I != E; ++I)
742  (*I)->substituteRegister(LoopCount, NewLoopCount, 0, HRI);
743  PrevInsts.clear();
744  PrevInsts.push_back(NewCmp);
745  PrevInsts.push_back(NewAdd);
746  // Insert the new loop instruction if this is the last time the loop is
747  // decremented.
748  if (Iter == MaxIter)
749  BuildMI(&MBB, DL, get(Hexagon::J2_loop0r)).
750  addMBB(Loop->getOperand(0).getMBB()).addReg(NewLoopCount);
751  // Delete the old loop instruction.
752  if (Iter == 0)
753  Loop->eraseFromParent();
754  Cond.push_back(MachineOperand::CreateImm(Hexagon::J2_jumpf));
755  Cond.push_back(NewCmp->getOperand(0));
756  return NewLoopCount;
757 }
758 
760  unsigned NumCycles, unsigned ExtraPredCycles,
761  BranchProbability Probability) const {
762  return nonDbgBBSize(&MBB) <= 3;
763 }
764 
766  unsigned NumTCycles, unsigned ExtraTCycles, MachineBasicBlock &FMBB,
767  unsigned NumFCycles, unsigned ExtraFCycles, BranchProbability Probability)
768  const {
769  return nonDbgBBSize(&TMBB) <= 3 && nonDbgBBSize(&FMBB) <= 3;
770 }
771 
773  unsigned NumInstrs, BranchProbability Probability) const {
774  return NumInstrs <= 4;
775 }
776 
779  const DebugLoc &DL, unsigned DestReg,
780  unsigned SrcReg, bool KillSrc) const {
781  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
782  unsigned KillFlag = getKillRegState(KillSrc);
783 
784  if (Hexagon::IntRegsRegClass.contains(SrcReg, DestReg)) {
785  BuildMI(MBB, I, DL, get(Hexagon::A2_tfr), DestReg)
786  .addReg(SrcReg, KillFlag);
787  return;
788  }
789  if (Hexagon::DoubleRegsRegClass.contains(SrcReg, DestReg)) {
790  BuildMI(MBB, I, DL, get(Hexagon::A2_tfrp), DestReg)
791  .addReg(SrcReg, KillFlag);
792  return;
793  }
794  if (Hexagon::PredRegsRegClass.contains(SrcReg, DestReg)) {
795  // Map Pd = Ps to Pd = or(Ps, Ps).
796  BuildMI(MBB, I, DL, get(Hexagon::C2_or), DestReg)
797  .addReg(SrcReg).addReg(SrcReg, KillFlag);
798  return;
799  }
800  if (Hexagon::CtrRegsRegClass.contains(DestReg) &&
801  Hexagon::IntRegsRegClass.contains(SrcReg)) {
802  BuildMI(MBB, I, DL, get(Hexagon::A2_tfrrcr), DestReg)
803  .addReg(SrcReg, KillFlag);
804  return;
805  }
806  if (Hexagon::IntRegsRegClass.contains(DestReg) &&
807  Hexagon::CtrRegsRegClass.contains(SrcReg)) {
808  BuildMI(MBB, I, DL, get(Hexagon::A2_tfrcrr), DestReg)
809  .addReg(SrcReg, KillFlag);
810  return;
811  }
812  if (Hexagon::ModRegsRegClass.contains(DestReg) &&
813  Hexagon::IntRegsRegClass.contains(SrcReg)) {
814  BuildMI(MBB, I, DL, get(Hexagon::A2_tfrrcr), DestReg)
815  .addReg(SrcReg, KillFlag);
816  return;
817  }
818  if (Hexagon::PredRegsRegClass.contains(SrcReg) &&
819  Hexagon::IntRegsRegClass.contains(DestReg)) {
820  BuildMI(MBB, I, DL, get(Hexagon::C2_tfrpr), DestReg)
821  .addReg(SrcReg, KillFlag);
822  return;
823  }
824  if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
825  Hexagon::PredRegsRegClass.contains(DestReg)) {
826  BuildMI(MBB, I, DL, get(Hexagon::C2_tfrrp), DestReg)
827  .addReg(SrcReg, KillFlag);
828  return;
829  }
830  if (Hexagon::PredRegsRegClass.contains(SrcReg) &&
831  Hexagon::IntRegsRegClass.contains(DestReg)) {
832  BuildMI(MBB, I, DL, get(Hexagon::C2_tfrpr), DestReg)
833  .addReg(SrcReg, KillFlag);
834  return;
835  }
836  if (Hexagon::HvxVRRegClass.contains(SrcReg, DestReg)) {
837  BuildMI(MBB, I, DL, get(Hexagon::V6_vassign), DestReg).
838  addReg(SrcReg, KillFlag);
839  return;
840  }
841  if (Hexagon::HvxWRRegClass.contains(SrcReg, DestReg)) {
842  unsigned LoSrc = HRI.getSubReg(SrcReg, Hexagon::vsub_lo);
843  unsigned HiSrc = HRI.getSubReg(SrcReg, Hexagon::vsub_hi);
844  BuildMI(MBB, I, DL, get(Hexagon::V6_vcombine), DestReg)
845  .addReg(HiSrc, KillFlag)
846  .addReg(LoSrc, KillFlag);
847  return;
848  }
849  if (Hexagon::HvxQRRegClass.contains(SrcReg, DestReg)) {
850  BuildMI(MBB, I, DL, get(Hexagon::V6_pred_and), DestReg)
851  .addReg(SrcReg)
852  .addReg(SrcReg, KillFlag);
853  return;
854  }
855  if (Hexagon::HvxQRRegClass.contains(SrcReg) &&
856  Hexagon::HvxVRRegClass.contains(DestReg)) {
857  llvm_unreachable("Unimplemented pred to vec");
858  return;
859  }
860  if (Hexagon::HvxQRRegClass.contains(DestReg) &&
861  Hexagon::HvxVRRegClass.contains(SrcReg)) {
862  llvm_unreachable("Unimplemented vec to pred");
863  return;
864  }
865 
866 #ifndef NDEBUG
867  // Show the invalid registers to ease debugging.
868  dbgs() << "Invalid registers for copy in " << printMBBReference(MBB) << ": "
869  << printReg(DestReg, &HRI) << " = " << printReg(SrcReg, &HRI) << '\n';
870 #endif
871  llvm_unreachable("Unimplemented");
872 }
873 
875  MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI,
876  const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const {
877  DebugLoc DL = MBB.findDebugLoc(I);
878  MachineFunction &MF = *MBB.getParent();
879  MachineFrameInfo &MFI = MF.getFrameInfo();
880  unsigned SlotAlign = MFI.getObjectAlignment(FI);
881  unsigned RegAlign = TRI->getSpillAlignment(*RC);
882  unsigned KillFlag = getKillRegState(isKill);
883  bool HasAlloca = MFI.hasVarSizedObjects();
884  const HexagonFrameLowering &HFI = *Subtarget.getFrameLowering();
885 
888  MFI.getObjectSize(FI), SlotAlign);
889 
890  if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {
891  BuildMI(MBB, I, DL, get(Hexagon::S2_storeri_io))
892  .addFrameIndex(FI).addImm(0)
893  .addReg(SrcReg, KillFlag).addMemOperand(MMO);
894  } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {
895  BuildMI(MBB, I, DL, get(Hexagon::S2_storerd_io))
896  .addFrameIndex(FI).addImm(0)
897  .addReg(SrcReg, KillFlag).addMemOperand(MMO);
898  } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {
899  BuildMI(MBB, I, DL, get(Hexagon::STriw_pred))
900  .addFrameIndex(FI).addImm(0)
901  .addReg(SrcReg, KillFlag).addMemOperand(MMO);
902  } else if (Hexagon::ModRegsRegClass.hasSubClassEq(RC)) {
903  BuildMI(MBB, I, DL, get(Hexagon::STriw_ctr))
904  .addFrameIndex(FI).addImm(0)
905  .addReg(SrcReg, KillFlag).addMemOperand(MMO);
906  } else if (Hexagon::HvxQRRegClass.hasSubClassEq(RC)) {
907  BuildMI(MBB, I, DL, get(Hexagon::PS_vstorerq_ai))
908  .addFrameIndex(FI).addImm(0)
909  .addReg(SrcReg, KillFlag).addMemOperand(MMO);
910  } else if (Hexagon::HvxVRRegClass.hasSubClassEq(RC)) {
911  // If there are variable-sized objects, spills will not be aligned.
912  if (HasAlloca)
913  SlotAlign = HFI.getStackAlignment();
914  unsigned Opc = SlotAlign < RegAlign ? Hexagon::V6_vS32Ub_ai
915  : Hexagon::V6_vS32b_ai;
918  MFI.getObjectSize(FI), SlotAlign);
919  BuildMI(MBB, I, DL, get(Opc))
920  .addFrameIndex(FI).addImm(0)
921  .addReg(SrcReg, KillFlag).addMemOperand(MMOA);
922  } else if (Hexagon::HvxWRRegClass.hasSubClassEq(RC)) {
923  // If there are variable-sized objects, spills will not be aligned.
924  if (HasAlloca)
925  SlotAlign = HFI.getStackAlignment();
926  unsigned Opc = SlotAlign < RegAlign ? Hexagon::PS_vstorerwu_ai
927  : Hexagon::PS_vstorerw_ai;
930  MFI.getObjectSize(FI), SlotAlign);
931  BuildMI(MBB, I, DL, get(Opc))
932  .addFrameIndex(FI).addImm(0)
933  .addReg(SrcReg, KillFlag).addMemOperand(MMOA);
934  } else {
935  llvm_unreachable("Unimplemented");
936  }
937 }
938 
940  MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg,
941  int FI, const TargetRegisterClass *RC,
942  const TargetRegisterInfo *TRI) const {
943  DebugLoc DL = MBB.findDebugLoc(I);
944  MachineFunction &MF = *MBB.getParent();
945  MachineFrameInfo &MFI = MF.getFrameInfo();
946  unsigned SlotAlign = MFI.getObjectAlignment(FI);
947  unsigned RegAlign = TRI->getSpillAlignment(*RC);
948  bool HasAlloca = MFI.hasVarSizedObjects();
949  const HexagonFrameLowering &HFI = *Subtarget.getFrameLowering();
950 
953  MFI.getObjectSize(FI), SlotAlign);
954 
955  if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {
956  BuildMI(MBB, I, DL, get(Hexagon::L2_loadri_io), DestReg)
957  .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
958  } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {
959  BuildMI(MBB, I, DL, get(Hexagon::L2_loadrd_io), DestReg)
960  .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
961  } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {
962  BuildMI(MBB, I, DL, get(Hexagon::LDriw_pred), DestReg)
963  .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
964  } else if (Hexagon::ModRegsRegClass.hasSubClassEq(RC)) {
965  BuildMI(MBB, I, DL, get(Hexagon::LDriw_ctr), DestReg)
966  .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
967  } else if (Hexagon::HvxQRRegClass.hasSubClassEq(RC)) {
968  BuildMI(MBB, I, DL, get(Hexagon::PS_vloadrq_ai), DestReg)
969  .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
970  } else if (Hexagon::HvxVRRegClass.hasSubClassEq(RC)) {
971  // If there are variable-sized objects, spills will not be aligned.
972  if (HasAlloca)
973  SlotAlign = HFI.getStackAlignment();
974  unsigned Opc = SlotAlign < RegAlign ? Hexagon::V6_vL32Ub_ai
975  : Hexagon::V6_vL32b_ai;
978  MFI.getObjectSize(FI), SlotAlign);
979  BuildMI(MBB, I, DL, get(Opc), DestReg)
980  .addFrameIndex(FI).addImm(0).addMemOperand(MMOA);
981  } else if (Hexagon::HvxWRRegClass.hasSubClassEq(RC)) {
982  // If there are variable-sized objects, spills will not be aligned.
983  if (HasAlloca)
984  SlotAlign = HFI.getStackAlignment();
985  unsigned Opc = SlotAlign < RegAlign ? Hexagon::PS_vloadrwu_ai
986  : Hexagon::PS_vloadrw_ai;
989  MFI.getObjectSize(FI), SlotAlign);
990  BuildMI(MBB, I, DL, get(Opc), DestReg)
991  .addFrameIndex(FI).addImm(0).addMemOperand(MMOA);
992  } else {
993  llvm_unreachable("Can't store this register to stack slot");
994  }
995 }
996 
997 static void getLiveRegsAt(LivePhysRegs &Regs, const MachineInstr &MI) {
998  const MachineBasicBlock &B = *MI.getParent();
999  Regs.addLiveOuts(B);
1000  auto E = ++MachineBasicBlock::const_iterator(MI.getIterator()).getReverse();
1001  for (auto I = B.rbegin(); I != E; ++I)
1002  Regs.stepBackward(*I);
1003 }
1004 
1005 /// expandPostRAPseudo - This function is called for all pseudo instructions
1006 /// that remain after register allocation. Many pseudo instructions are
1007 /// created to help register allocation. This is the place to convert them
1008 /// into real instructions. The target can edit MI in place, or it can insert
1009 /// new instructions and erase MI. The function should return true if
1010 /// anything was changed.
1012  MachineBasicBlock &MBB = *MI.getParent();
1013  MachineFunction &MF = *MBB.getParent();
1015  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
1016  DebugLoc DL = MI.getDebugLoc();
1017  unsigned Opc = MI.getOpcode();
1018 
1019  auto RealCirc = [&](unsigned Opc, bool HasImm, unsigned MxOp) {
1020  unsigned Mx = MI.getOperand(MxOp).getReg();
1021  unsigned CSx = (Mx == Hexagon::M0 ? Hexagon::CS0 : Hexagon::CS1);
1022  BuildMI(MBB, MI, DL, get(Hexagon::A2_tfrrcr), CSx)
1023  .add(MI.getOperand((HasImm ? 5 : 4)));
1024  auto MIB = BuildMI(MBB, MI, DL, get(Opc)).add(MI.getOperand(0))
1025  .add(MI.getOperand(1)).add(MI.getOperand(2)).add(MI.getOperand(3));
1026  if (HasImm)
1027  MIB.add(MI.getOperand(4));
1028  MIB.addReg(CSx, RegState::Implicit);
1029  MBB.erase(MI);
1030  return true;
1031  };
1032 
1033  switch (Opc) {
1034  case TargetOpcode::COPY: {
1035  MachineOperand &MD = MI.getOperand(0);
1036  MachineOperand &MS = MI.getOperand(1);
1038  if (MD.getReg() != MS.getReg() && !MS.isUndef()) {
1039  copyPhysReg(MBB, MI, DL, MD.getReg(), MS.getReg(), MS.isKill());
1040  std::prev(MBBI)->copyImplicitOps(*MBB.getParent(), MI);
1041  }
1042  MBB.erase(MBBI);
1043  return true;
1044  }
1045  case Hexagon::PS_aligna:
1046  BuildMI(MBB, MI, DL, get(Hexagon::A2_andir), MI.getOperand(0).getReg())
1047  .addReg(HRI.getFrameRegister())
1048  .addImm(-MI.getOperand(1).getImm());
1049  MBB.erase(MI);
1050  return true;
1051  case Hexagon::V6_vassignp: {
1052  unsigned SrcReg = MI.getOperand(1).getReg();
1053  unsigned DstReg = MI.getOperand(0).getReg();
1054  unsigned Kill = getKillRegState(MI.getOperand(1).isKill());
1055  BuildMI(MBB, MI, DL, get(Hexagon::V6_vcombine), DstReg)
1056  .addReg(HRI.getSubReg(SrcReg, Hexagon::vsub_hi), Kill)
1057  .addReg(HRI.getSubReg(SrcReg, Hexagon::vsub_lo), Kill);
1058  MBB.erase(MI);
1059  return true;
1060  }
1061  case Hexagon::V6_lo: {
1062  unsigned SrcReg = MI.getOperand(1).getReg();
1063  unsigned DstReg = MI.getOperand(0).getReg();
1064  unsigned SrcSubLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo);
1065  copyPhysReg(MBB, MI, DL, DstReg, SrcSubLo, MI.getOperand(1).isKill());
1066  MBB.erase(MI);
1067  MRI.clearKillFlags(SrcSubLo);
1068  return true;
1069  }
1070  case Hexagon::V6_hi: {
1071  unsigned SrcReg = MI.getOperand(1).getReg();
1072  unsigned DstReg = MI.getOperand(0).getReg();
1073  unsigned SrcSubHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi);
1074  copyPhysReg(MBB, MI, DL, DstReg, SrcSubHi, MI.getOperand(1).isKill());
1075  MBB.erase(MI);
1076  MRI.clearKillFlags(SrcSubHi);
1077  return true;
1078  }
1079  case Hexagon::PS_vstorerw_ai:
1080  case Hexagon::PS_vstorerwu_ai: {
1081  bool Aligned = Opc == Hexagon::PS_vstorerw_ai;
1082  unsigned SrcReg = MI.getOperand(2).getReg();
1083  unsigned SrcSubHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi);
1084  unsigned SrcSubLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo);
1085  unsigned NewOpc = Aligned ? Hexagon::V6_vS32b_ai : Hexagon::V6_vS32Ub_ai;
1086  unsigned Offset = HRI.getSpillSize(Hexagon::HvxVRRegClass);
1087 
1088  MachineInstr *MI1New = BuildMI(MBB, MI, DL, get(NewOpc))
1089  .add(MI.getOperand(0))
1090  .addImm(MI.getOperand(1).getImm())
1091  .addReg(SrcSubLo)
1092  .cloneMemRefs(MI);
1093  MI1New->getOperand(0).setIsKill(false);
1094  BuildMI(MBB, MI, DL, get(NewOpc))
1095  .add(MI.getOperand(0))
1096  // The Vectors are indexed in multiples of vector size.
1097  .addImm(MI.getOperand(1).getImm() + Offset)
1098  .addReg(SrcSubHi)
1099  .cloneMemRefs(MI);
1100  MBB.erase(MI);
1101  return true;
1102  }
1103  case Hexagon::PS_vloadrw_ai:
1104  case Hexagon::PS_vloadrwu_ai: {
1105  bool Aligned = Opc == Hexagon::PS_vloadrw_ai;
1106  unsigned DstReg = MI.getOperand(0).getReg();
1107  unsigned NewOpc = Aligned ? Hexagon::V6_vL32b_ai : Hexagon::V6_vL32Ub_ai;
1108  unsigned Offset = HRI.getSpillSize(Hexagon::HvxVRRegClass);
1109 
1110  MachineInstr *MI1New = BuildMI(MBB, MI, DL, get(NewOpc),
1111  HRI.getSubReg(DstReg, Hexagon::vsub_lo))
1112  .add(MI.getOperand(1))
1113  .addImm(MI.getOperand(2).getImm())
1114  .cloneMemRefs(MI);
1115  MI1New->getOperand(1).setIsKill(false);
1116  BuildMI(MBB, MI, DL, get(NewOpc), HRI.getSubReg(DstReg, Hexagon::vsub_hi))
1117  .add(MI.getOperand(1))
1118  // The Vectors are indexed in multiples of vector size.
1119  .addImm(MI.getOperand(2).getImm() + Offset)
1120  .cloneMemRefs(MI);
1121  MBB.erase(MI);
1122  return true;
1123  }
1124  case Hexagon::PS_true: {
1125  unsigned Reg = MI.getOperand(0).getReg();
1126  BuildMI(MBB, MI, DL, get(Hexagon::C2_orn), Reg)
1127  .addReg(Reg, RegState::Undef)
1128  .addReg(Reg, RegState::Undef);
1129  MBB.erase(MI);
1130  return true;
1131  }
1132  case Hexagon::PS_false: {
1133  unsigned Reg = MI.getOperand(0).getReg();
1134  BuildMI(MBB, MI, DL, get(Hexagon::C2_andn), Reg)
1135  .addReg(Reg, RegState::Undef)
1136  .addReg(Reg, RegState::Undef);
1137  MBB.erase(MI);
1138  return true;
1139  }
1140  case Hexagon::PS_qtrue: {
1141  BuildMI(MBB, MI, DL, get(Hexagon::V6_veqw), MI.getOperand(0).getReg())
1142  .addReg(Hexagon::V0, RegState::Undef)
1143  .addReg(Hexagon::V0, RegState::Undef);
1144  MBB.erase(MI);
1145  return true;
1146  }
1147  case Hexagon::PS_qfalse: {
1148  BuildMI(MBB, MI, DL, get(Hexagon::V6_vgtw), MI.getOperand(0).getReg())
1149  .addReg(Hexagon::V0, RegState::Undef)
1150  .addReg(Hexagon::V0, RegState::Undef);
1151  MBB.erase(MI);
1152  return true;
1153  }
1154  case Hexagon::PS_vdd0: {
1155  unsigned Vd = MI.getOperand(0).getReg();
1156  BuildMI(MBB, MI, DL, get(Hexagon::V6_vsubw_dv), Vd)
1157  .addReg(Vd, RegState::Undef)
1158  .addReg(Vd, RegState::Undef);
1159  MBB.erase(MI);
1160  return true;
1161  }
1162  case Hexagon::PS_vmulw: {
1163  // Expand a 64-bit vector multiply into 2 32-bit scalar multiplies.
1164  unsigned DstReg = MI.getOperand(0).getReg();
1165  unsigned Src1Reg = MI.getOperand(1).getReg();
1166  unsigned Src2Reg = MI.getOperand(2).getReg();
1167  unsigned Src1SubHi = HRI.getSubReg(Src1Reg, Hexagon::isub_hi);
1168  unsigned Src1SubLo = HRI.getSubReg(Src1Reg, Hexagon::isub_lo);
1169  unsigned Src2SubHi = HRI.getSubReg(Src2Reg, Hexagon::isub_hi);
1170  unsigned Src2SubLo = HRI.getSubReg(Src2Reg, Hexagon::isub_lo);
1171  BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_mpyi),
1172  HRI.getSubReg(DstReg, Hexagon::isub_hi))
1173  .addReg(Src1SubHi)
1174  .addReg(Src2SubHi);
1175  BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_mpyi),
1176  HRI.getSubReg(DstReg, Hexagon::isub_lo))
1177  .addReg(Src1SubLo)
1178  .addReg(Src2SubLo);
1179  MBB.erase(MI);
1180  MRI.clearKillFlags(Src1SubHi);
1181  MRI.clearKillFlags(Src1SubLo);
1182  MRI.clearKillFlags(Src2SubHi);
1183  MRI.clearKillFlags(Src2SubLo);
1184  return true;
1185  }
1186  case Hexagon::PS_vmulw_acc: {
1187  // Expand 64-bit vector multiply with addition into 2 scalar multiplies.
1188  unsigned DstReg = MI.getOperand(0).getReg();
1189  unsigned Src1Reg = MI.getOperand(1).getReg();
1190  unsigned Src2Reg = MI.getOperand(2).getReg();
1191  unsigned Src3Reg = MI.getOperand(3).getReg();
1192  unsigned Src1SubHi = HRI.getSubReg(Src1Reg, Hexagon::isub_hi);
1193  unsigned Src1SubLo = HRI.getSubReg(Src1Reg, Hexagon::isub_lo);
1194  unsigned Src2SubHi = HRI.getSubReg(Src2Reg, Hexagon::isub_hi);
1195  unsigned Src2SubLo = HRI.getSubReg(Src2Reg, Hexagon::isub_lo);
1196  unsigned Src3SubHi = HRI.getSubReg(Src3Reg, Hexagon::isub_hi);
1197  unsigned Src3SubLo = HRI.getSubReg(Src3Reg, Hexagon::isub_lo);
1198  BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_maci),
1199  HRI.getSubReg(DstReg, Hexagon::isub_hi))
1200  .addReg(Src1SubHi)
1201  .addReg(Src2SubHi)
1202  .addReg(Src3SubHi);
1203  BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_maci),
1204  HRI.getSubReg(DstReg, Hexagon::isub_lo))
1205  .addReg(Src1SubLo)
1206  .addReg(Src2SubLo)
1207  .addReg(Src3SubLo);
1208  MBB.erase(MI);
1209  MRI.clearKillFlags(Src1SubHi);
1210  MRI.clearKillFlags(Src1SubLo);
1211  MRI.clearKillFlags(Src2SubHi);
1212  MRI.clearKillFlags(Src2SubLo);
1213  MRI.clearKillFlags(Src3SubHi);
1214  MRI.clearKillFlags(Src3SubLo);
1215  return true;
1216  }
1217  case Hexagon::PS_pselect: {
1218  const MachineOperand &Op0 = MI.getOperand(0);
1219  const MachineOperand &Op1 = MI.getOperand(1);
1220  const MachineOperand &Op2 = MI.getOperand(2);
1221  const MachineOperand &Op3 = MI.getOperand(3);
1222  unsigned Rd = Op0.getReg();
1223  unsigned Pu = Op1.getReg();
1224  unsigned Rs = Op2.getReg();
1225  unsigned Rt = Op3.getReg();
1226  DebugLoc DL = MI.getDebugLoc();
1227  unsigned K1 = getKillRegState(Op1.isKill());
1228  unsigned K2 = getKillRegState(Op2.isKill());
1229  unsigned K3 = getKillRegState(Op3.isKill());
1230  if (Rd != Rs)
1231  BuildMI(MBB, MI, DL, get(Hexagon::A2_tfrpt), Rd)
1232  .addReg(Pu, (Rd == Rt) ? K1 : 0)
1233  .addReg(Rs, K2);
1234  if (Rd != Rt)
1235  BuildMI(MBB, MI, DL, get(Hexagon::A2_tfrpf), Rd)
1236  .addReg(Pu, K1)
1237  .addReg(Rt, K3);
1238  MBB.erase(MI);
1239  return true;
1240  }
1241  case Hexagon::PS_vselect: {
1242  const MachineOperand &Op0 = MI.getOperand(0);
1243  const MachineOperand &Op1 = MI.getOperand(1);
1244  const MachineOperand &Op2 = MI.getOperand(2);
1245  const MachineOperand &Op3 = MI.getOperand(3);
1246  LivePhysRegs LiveAtMI(HRI);
1247  getLiveRegsAt(LiveAtMI, MI);
1248  bool IsDestLive = !LiveAtMI.available(MRI, Op0.getReg());
1249  unsigned PReg = Op1.getReg();
1250  assert(Op1.getSubReg() == 0);
1251  unsigned PState = getRegState(Op1);
1252 
1253  if (Op0.getReg() != Op2.getReg()) {
1254  unsigned S = Op0.getReg() != Op3.getReg() ? PState & ~RegState::Kill
1255  : PState;
1256  auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vcmov))
1257  .add(Op0)
1258  .addReg(PReg, S)
1259  .add(Op2);
1260  if (IsDestLive)
1261  T.addReg(Op0.getReg(), RegState::Implicit);
1262  IsDestLive = true;
1263  }
1264  if (Op0.getReg() != Op3.getReg()) {
1265  auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vncmov))
1266  .add(Op0)
1267  .addReg(PReg, PState)
1268  .add(Op3);
1269  if (IsDestLive)
1270  T.addReg(Op0.getReg(), RegState::Implicit);
1271  }
1272  MBB.erase(MI);
1273  return true;
1274  }
1275  case Hexagon::PS_wselect: {
1276  MachineOperand &Op0 = MI.getOperand(0);
1277  MachineOperand &Op1 = MI.getOperand(1);
1278  MachineOperand &Op2 = MI.getOperand(2);
1279  MachineOperand &Op3 = MI.getOperand(3);
1280  LivePhysRegs LiveAtMI(HRI);
1281  getLiveRegsAt(LiveAtMI, MI);
1282  bool IsDestLive = !LiveAtMI.available(MRI, Op0.getReg());
1283  unsigned PReg = Op1.getReg();
1284  assert(Op1.getSubReg() == 0);
1285  unsigned PState = getRegState(Op1);
1286 
1287  if (Op0.getReg() != Op2.getReg()) {
1288  unsigned S = Op0.getReg() != Op3.getReg() ? PState & ~RegState::Kill
1289  : PState;
1290  unsigned SrcLo = HRI.getSubReg(Op2.getReg(), Hexagon::vsub_lo);
1291  unsigned SrcHi = HRI.getSubReg(Op2.getReg(), Hexagon::vsub_hi);
1292  auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vccombine))
1293  .add(Op0)
1294  .addReg(PReg, S)
1295  .addReg(SrcHi)
1296  .addReg(SrcLo);
1297  if (IsDestLive)
1298  T.addReg(Op0.getReg(), RegState::Implicit);
1299  IsDestLive = true;
1300  }
1301  if (Op0.getReg() != Op3.getReg()) {
1302  unsigned SrcLo = HRI.getSubReg(Op3.getReg(), Hexagon::vsub_lo);
1303  unsigned SrcHi = HRI.getSubReg(Op3.getReg(), Hexagon::vsub_hi);
1304  auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vnccombine))
1305  .add(Op0)
1306  .addReg(PReg, PState)
1307  .addReg(SrcHi)
1308  .addReg(SrcLo);
1309  if (IsDestLive)
1310  T.addReg(Op0.getReg(), RegState::Implicit);
1311  }
1312  MBB.erase(MI);
1313  return true;
1314  }
1315 
1316  case Hexagon::PS_crash: {
1317  // Generate a misaligned load that is guaranteed to cause a crash.
1318  class CrashPseudoSourceValue : public PseudoSourceValue {
1319  public:
1320  CrashPseudoSourceValue(const TargetInstrInfo &TII)
1321  : PseudoSourceValue(TargetCustom, TII) {}
1322 
1323  bool isConstant(const MachineFrameInfo *) const override {
1324  return false;
1325  }
1326  bool isAliased(const MachineFrameInfo *) const override {
1327  return false;
1328  }
1329  bool mayAlias(const MachineFrameInfo *) const override {
1330  return false;
1331  }
1332  void printCustom(raw_ostream &OS) const override {
1333  OS << "MisalignedCrash";
1334  }
1335  };
1336 
1337  static const CrashPseudoSourceValue CrashPSV(*this);
1339  MachinePointerInfo(&CrashPSV),
1341  BuildMI(MBB, MI, DL, get(Hexagon::PS_loadrdabs), Hexagon::D13)
1342  .addImm(0xBADC0FEE) // Misaligned load.
1343  .addMemOperand(MMO);
1344  MBB.erase(MI);
1345  return true;
1346  }
1347 
1348  case Hexagon::PS_tailcall_i:
1349  MI.setDesc(get(Hexagon::J2_jump));
1350  return true;
1351  case Hexagon::PS_tailcall_r:
1352  case Hexagon::PS_jmpret:
1353  MI.setDesc(get(Hexagon::J2_jumpr));
1354  return true;
1355  case Hexagon::PS_jmprett:
1356  MI.setDesc(get(Hexagon::J2_jumprt));
1357  return true;
1358  case Hexagon::PS_jmpretf:
1359  MI.setDesc(get(Hexagon::J2_jumprf));
1360  return true;
1361  case Hexagon::PS_jmprettnewpt:
1362  MI.setDesc(get(Hexagon::J2_jumprtnewpt));
1363  return true;
1364  case Hexagon::PS_jmpretfnewpt:
1365  MI.setDesc(get(Hexagon::J2_jumprfnewpt));
1366  return true;
1367  case Hexagon::PS_jmprettnew:
1368  MI.setDesc(get(Hexagon::J2_jumprtnew));
1369  return true;
1370  case Hexagon::PS_jmpretfnew:
1371  MI.setDesc(get(Hexagon::J2_jumprfnew));
1372  return true;
1373 
1374  case Hexagon::PS_loadrub_pci:
1375  return RealCirc(Hexagon::L2_loadrub_pci, /*HasImm*/true, /*MxOp*/4);
1376  case Hexagon::PS_loadrb_pci:
1377  return RealCirc(Hexagon::L2_loadrb_pci, /*HasImm*/true, /*MxOp*/4);
1378  case Hexagon::PS_loadruh_pci:
1379  return RealCirc(Hexagon::L2_loadruh_pci, /*HasImm*/true, /*MxOp*/4);
1380  case Hexagon::PS_loadrh_pci:
1381  return RealCirc(Hexagon::L2_loadrh_pci, /*HasImm*/true, /*MxOp*/4);
1382  case Hexagon::PS_loadri_pci:
1383  return RealCirc(Hexagon::L2_loadri_pci, /*HasImm*/true, /*MxOp*/4);
1384  case Hexagon::PS_loadrd_pci:
1385  return RealCirc(Hexagon::L2_loadrd_pci, /*HasImm*/true, /*MxOp*/4);
1386  case Hexagon::PS_loadrub_pcr:
1387  return RealCirc(Hexagon::L2_loadrub_pcr, /*HasImm*/false, /*MxOp*/3);
1388  case Hexagon::PS_loadrb_pcr:
1389  return RealCirc(Hexagon::L2_loadrb_pcr, /*HasImm*/false, /*MxOp*/3);
1390  case Hexagon::PS_loadruh_pcr:
1391  return RealCirc(Hexagon::L2_loadruh_pcr, /*HasImm*/false, /*MxOp*/3);
1392  case Hexagon::PS_loadrh_pcr:
1393  return RealCirc(Hexagon::L2_loadrh_pcr, /*HasImm*/false, /*MxOp*/3);
1394  case Hexagon::PS_loadri_pcr:
1395  return RealCirc(Hexagon::L2_loadri_pcr, /*HasImm*/false, /*MxOp*/3);
1396  case Hexagon::PS_loadrd_pcr:
1397  return RealCirc(Hexagon::L2_loadrd_pcr, /*HasImm*/false, /*MxOp*/3);
1398  case Hexagon::PS_storerb_pci:
1399  return RealCirc(Hexagon::S2_storerb_pci, /*HasImm*/true, /*MxOp*/3);
1400  case Hexagon::PS_storerh_pci:
1401  return RealCirc(Hexagon::S2_storerh_pci, /*HasImm*/true, /*MxOp*/3);
1402  case Hexagon::PS_storerf_pci:
1403  return RealCirc(Hexagon::S2_storerf_pci, /*HasImm*/true, /*MxOp*/3);
1404  case Hexagon::PS_storeri_pci:
1405  return RealCirc(Hexagon::S2_storeri_pci, /*HasImm*/true, /*MxOp*/3);
1406  case Hexagon::PS_storerd_pci:
1407  return RealCirc(Hexagon::S2_storerd_pci, /*HasImm*/true, /*MxOp*/3);
1408  case Hexagon::PS_storerb_pcr:
1409  return RealCirc(Hexagon::S2_storerb_pcr, /*HasImm*/false, /*MxOp*/2);
1410  case Hexagon::PS_storerh_pcr:
1411  return RealCirc(Hexagon::S2_storerh_pcr, /*HasImm*/false, /*MxOp*/2);
1412  case Hexagon::PS_storerf_pcr:
1413  return RealCirc(Hexagon::S2_storerf_pcr, /*HasImm*/false, /*MxOp*/2);
1414  case Hexagon::PS_storeri_pcr:
1415  return RealCirc(Hexagon::S2_storeri_pcr, /*HasImm*/false, /*MxOp*/2);
1416  case Hexagon::PS_storerd_pcr:
1417  return RealCirc(Hexagon::S2_storerd_pcr, /*HasImm*/false, /*MxOp*/2);
1418  }
1419 
1420  return false;
1421 }
1422 
1425  MachineBasicBlock &MBB = *MI.getParent();
1426  const DebugLoc &DL = MI.getDebugLoc();
1427  unsigned Opc = MI.getOpcode();
1429 
1430  switch (Opc) {
1431  case Hexagon::V6_vgathermh_pseudo:
1432  First = BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermh))
1433  .add(MI.getOperand(1))
1434  .add(MI.getOperand(2))
1435  .add(MI.getOperand(3));
1436  BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1437  .add(MI.getOperand(0))
1438  .addImm(0)
1439  .addReg(Hexagon::VTMP);
1440  MBB.erase(MI);
1441  return First.getInstrIterator();
1442 
1443  case Hexagon::V6_vgathermw_pseudo:
1444  First = BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermw))
1445  .add(MI.getOperand(1))
1446  .add(MI.getOperand(2))
1447  .add(MI.getOperand(3));
1448  BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1449  .add(MI.getOperand(0))
1450  .addImm(0)
1451  .addReg(Hexagon::VTMP);
1452  MBB.erase(MI);
1453  return First.getInstrIterator();
1454 
1455  case Hexagon::V6_vgathermhw_pseudo:
1456  First = BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermhw))
1457  .add(MI.getOperand(1))
1458  .add(MI.getOperand(2))
1459  .add(MI.getOperand(3));
1460  BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1461  .add(MI.getOperand(0))
1462  .addImm(0)
1463  .addReg(Hexagon::VTMP);
1464  MBB.erase(MI);
1465  return First.getInstrIterator();
1466 
1467  case Hexagon::V6_vgathermhq_pseudo:
1468  First = BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermhq))
1469  .add(MI.getOperand(1))
1470  .add(MI.getOperand(2))
1471  .add(MI.getOperand(3))
1472  .add(MI.getOperand(4));
1473  BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1474  .add(MI.getOperand(0))
1475  .addImm(0)
1476  .addReg(Hexagon::VTMP);
1477  MBB.erase(MI);
1478  return First.getInstrIterator();
1479 
1480  case Hexagon::V6_vgathermwq_pseudo:
1481  First = BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermwq))
1482  .add(MI.getOperand(1))
1483  .add(MI.getOperand(2))
1484  .add(MI.getOperand(3))
1485  .add(MI.getOperand(4));
1486  BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1487  .add(MI.getOperand(0))
1488  .addImm(0)
1489  .addReg(Hexagon::VTMP);
1490  MBB.erase(MI);
1491  return First.getInstrIterator();
1492 
1493  case Hexagon::V6_vgathermhwq_pseudo:
1494  First = BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermhwq))
1495  .add(MI.getOperand(1))
1496  .add(MI.getOperand(2))
1497  .add(MI.getOperand(3))
1498  .add(MI.getOperand(4));
1499  BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1500  .add(MI.getOperand(0))
1501  .addImm(0)
1502  .addReg(Hexagon::VTMP);
1503  MBB.erase(MI);
1504  return First.getInstrIterator();
1505  }
1506 
1507  return MI.getIterator();
1508 }
1509 
1510 // We indicate that we want to reverse the branch by
1511 // inserting the reversed branching opcode.
1513  SmallVectorImpl<MachineOperand> &Cond) const {
1514  if (Cond.empty())
1515  return true;
1516  assert(Cond[0].isImm() && "First entry in the cond vector not imm-val");
1517  unsigned opcode = Cond[0].getImm();
1518  //unsigned temp;
1519  assert(get(opcode).isBranch() && "Should be a branching condition.");
1520  if (isEndLoopN(opcode))
1521  return true;
1522  unsigned NewOpcode = getInvertedPredicatedOpcode(opcode);
1523  Cond[0].setImm(NewOpcode);
1524  return false;
1525 }
1526 
1529  DebugLoc DL;
1530  BuildMI(MBB, MI, DL, get(Hexagon::A2_nop));
1531 }
1532 
1534  return getAddrMode(MI) == HexagonII::PostInc;
1535 }
1536 
1537 // Returns true if an instruction is predicated irrespective of the predicate
1538 // sense. For example, all of the following will return true.
1539 // if (p0) R1 = add(R2, R3)
1540 // if (!p0) R1 = add(R2, R3)
1541 // if (p0.new) R1 = add(R2, R3)
1542 // if (!p0.new) R1 = add(R2, R3)
1543 // Note: New-value stores are not included here as in the current
1544 // implementation, we don't need to check their predicate sense.
1546  const uint64_t F = MI.getDesc().TSFlags;
1548 }
1549 
1551  MachineInstr &MI, ArrayRef<MachineOperand> Cond) const {
1552  if (Cond.empty() || isNewValueJump(Cond[0].getImm()) ||
1553  isEndLoopN(Cond[0].getImm())) {
1554  LLVM_DEBUG(dbgs() << "\nCannot predicate:"; MI.dump(););
1555  return false;
1556  }
1557  int Opc = MI.getOpcode();
1558  assert (isPredicable(MI) && "Expected predicable instruction");
1559  bool invertJump = predOpcodeHasNot(Cond);
1560 
1561  // We have to predicate MI "in place", i.e. after this function returns,
1562  // MI will need to be transformed into a predicated form. To avoid com-
1563  // plicated manipulations with the operands (handling tied operands,
1564  // etc.), build a new temporary instruction, then overwrite MI with it.
1565 
1566  MachineBasicBlock &B = *MI.getParent();
1567  DebugLoc DL = MI.getDebugLoc();
1568  unsigned PredOpc = getCondOpcode(Opc, invertJump);
1569  MachineInstrBuilder T = BuildMI(B, MI, DL, get(PredOpc));
1570  unsigned NOp = 0, NumOps = MI.getNumOperands();
1571  while (NOp < NumOps) {
1572  MachineOperand &Op = MI.getOperand(NOp);
1573  if (!Op.isReg() || !Op.isDef() || Op.isImplicit())
1574  break;
1575  T.add(Op);
1576  NOp++;
1577  }
1578 
1579  unsigned PredReg, PredRegPos, PredRegFlags;
1580  bool GotPredReg = getPredReg(Cond, PredReg, PredRegPos, PredRegFlags);
1581  (void)GotPredReg;
1582  assert(GotPredReg);
1583  T.addReg(PredReg, PredRegFlags);
1584  while (NOp < NumOps)
1585  T.add(MI.getOperand(NOp++));
1586 
1587  MI.setDesc(get(PredOpc));
1588  while (unsigned n = MI.getNumOperands())
1589  MI.RemoveOperand(n-1);
1590  for (unsigned i = 0, n = T->getNumOperands(); i < n; ++i)
1591  MI.addOperand(T->getOperand(i));
1592 
1594  B.erase(TI);
1595 
1597  MRI.clearKillFlags(PredReg);
1598  return true;
1599 }
1600 
1602  ArrayRef<MachineOperand> Pred2) const {
1603  // TODO: Fix this
1604  return false;
1605 }
1606 
1608  std::vector<MachineOperand> &Pred) const {
1609  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
1610 
1611  for (unsigned oper = 0; oper < MI.getNumOperands(); ++oper) {
1612  MachineOperand MO = MI.getOperand(oper);
1613  if (MO.isReg()) {
1614  if (!MO.isDef())
1615  continue;
1616  const TargetRegisterClass* RC = HRI.getMinimalPhysRegClass(MO.getReg());
1617  if (RC == &Hexagon::PredRegsRegClass) {
1618  Pred.push_back(MO);
1619  return true;
1620  }
1621  continue;
1622  } else if (MO.isRegMask()) {
1623  for (unsigned PR : Hexagon::PredRegsRegClass) {
1624  if (!MI.modifiesRegister(PR, &HRI))
1625  continue;
1626  Pred.push_back(MO);
1627  return true;
1628  }
1629  }
1630  }
1631  return false;
1632 }
1633 
1635  if (!MI.getDesc().isPredicable())
1636  return false;
1637 
1638  if (MI.isCall() || isTailCall(MI)) {
1639  if (!Subtarget.usePredicatedCalls())
1640  return false;
1641  }
1642 
1643  // HVX loads are not predicable on v60, but are on v62.
1644  if (!Subtarget.hasV62Ops()) {
1645  switch (MI.getOpcode()) {
1646  case Hexagon::V6_vL32b_ai:
1647  case Hexagon::V6_vL32b_pi:
1648  case Hexagon::V6_vL32b_ppu:
1649  case Hexagon::V6_vL32b_cur_ai:
1650  case Hexagon::V6_vL32b_cur_pi:
1651  case Hexagon::V6_vL32b_cur_ppu:
1652  case Hexagon::V6_vL32b_nt_ai:
1653  case Hexagon::V6_vL32b_nt_pi:
1654  case Hexagon::V6_vL32b_nt_ppu:
1655  case Hexagon::V6_vL32b_tmp_ai:
1656  case Hexagon::V6_vL32b_tmp_pi:
1657  case Hexagon::V6_vL32b_tmp_ppu:
1658  case Hexagon::V6_vL32b_nt_cur_ai:
1659  case Hexagon::V6_vL32b_nt_cur_pi:
1660  case Hexagon::V6_vL32b_nt_cur_ppu:
1661  case Hexagon::V6_vL32b_nt_tmp_ai:
1662  case Hexagon::V6_vL32b_nt_tmp_pi:
1663  case Hexagon::V6_vL32b_nt_tmp_ppu:
1664  return false;
1665  }
1666  }
1667  return true;
1668 }
1669 
1671  const MachineBasicBlock *MBB,
1672  const MachineFunction &MF) const {
1673  // Debug info is never a scheduling boundary. It's necessary to be explicit
1674  // due to the special treatment of IT instructions below, otherwise a
1675  // dbg_value followed by an IT will result in the IT instruction being
1676  // considered a scheduling hazard, which is wrong. It should be the actual
1677  // instruction preceding the dbg_value instruction(s), just like it is
1678  // when debug info is not present.
1679  if (MI.isDebugInstr())
1680  return false;
1681 
1682  // Throwing call is a boundary.
1683  if (MI.isCall()) {
1684  // Don't mess around with no return calls.
1685  if (doesNotReturn(MI))
1686  return true;
1687  // If any of the block's successors is a landing pad, this could be a
1688  // throwing call.
1689  for (auto I : MBB->successors())
1690  if (I->isEHPad())
1691  return true;
1692  }
1693 
1694  // Terminators and labels can't be scheduled around.
1695  if (MI.getDesc().isTerminator() || MI.isPosition())
1696  return true;
1697 
1698  if (MI.isInlineAsm() && !ScheduleInlineAsm)
1699  return true;
1700 
1701  return false;
1702 }
1703 
1704 /// Measure the specified inline asm to determine an approximation of its
1705 /// length.
1706 /// Comments (which run till the next SeparatorString or newline) do not
1707 /// count as an instruction.
1708 /// Any other non-whitespace text is considered an instruction, with
1709 /// multiple instructions separated by SeparatorString or newlines.
1710 /// Variable-length instructions are not handled here; this function
1711 /// may be overloaded in the target code to do that.
1712 /// Hexagon counts the number of ##'s and adjust for that many
1713 /// constant exenders.
1714 unsigned HexagonInstrInfo::getInlineAsmLength(const char *Str,
1715  const MCAsmInfo &MAI) const {
1716  StringRef AStr(Str);
1717  // Count the number of instructions in the asm.
1718  bool atInsnStart = true;
1719  unsigned Length = 0;
1720  for (; *Str; ++Str) {
1721  if (*Str == '\n' || strncmp(Str, MAI.getSeparatorString(),
1722  strlen(MAI.getSeparatorString())) == 0)
1723  atInsnStart = true;
1724  if (atInsnStart && !std::isspace(static_cast<unsigned char>(*Str))) {
1725  Length += MAI.getMaxInstLength();
1726  atInsnStart = false;
1727  }
1728  if (atInsnStart && strncmp(Str, MAI.getCommentString().data(),
1729  MAI.getCommentString().size()) == 0)
1730  atInsnStart = false;
1731  }
1732 
1733  // Add to size number of constant extenders seen * 4.
1734  StringRef Occ("##");
1735  Length += AStr.count(Occ)*4;
1736  return Length;
1737 }
1738 
1741  const InstrItineraryData *II, const ScheduleDAG *DAG) const {
1742  if (UseDFAHazardRec)
1743  return new HexagonHazardRecognizer(II, this, Subtarget);
1745 }
1746 
1747 /// For a comparison instruction, return the source registers in
1748 /// \p SrcReg and \p SrcReg2 if having two register operands, and the value it
1749 /// compares against in CmpValue. Return true if the comparison instruction
1750 /// can be analyzed.
1751 bool HexagonInstrInfo::analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
1752  unsigned &SrcReg2, int &Mask,
1753  int &Value) const {
1754  unsigned Opc = MI.getOpcode();
1755 
1756  // Set mask and the first source register.
1757  switch (Opc) {
1758  case Hexagon::C2_cmpeq:
1759  case Hexagon::C2_cmpeqp:
1760  case Hexagon::C2_cmpgt:
1761  case Hexagon::C2_cmpgtp:
1762  case Hexagon::C2_cmpgtu:
1763  case Hexagon::C2_cmpgtup:
1764  case Hexagon::C4_cmpneq:
1765  case Hexagon::C4_cmplte:
1766  case Hexagon::C4_cmplteu:
1767  case Hexagon::C2_cmpeqi:
1768  case Hexagon::C2_cmpgti:
1769  case Hexagon::C2_cmpgtui:
1770  case Hexagon::C4_cmpneqi:
1771  case Hexagon::C4_cmplteui:
1772  case Hexagon::C4_cmpltei:
1773  SrcReg = MI.getOperand(1).getReg();
1774  Mask = ~0;
1775  break;
1776  case Hexagon::A4_cmpbeq:
1777  case Hexagon::A4_cmpbgt:
1778  case Hexagon::A4_cmpbgtu:
1779  case Hexagon::A4_cmpbeqi:
1780  case Hexagon::A4_cmpbgti:
1781  case Hexagon::A4_cmpbgtui:
1782  SrcReg = MI.getOperand(1).getReg();
1783  Mask = 0xFF;
1784  break;
1785  case Hexagon::A4_cmpheq:
1786  case Hexagon::A4_cmphgt:
1787  case Hexagon::A4_cmphgtu:
1788  case Hexagon::A4_cmpheqi:
1789  case Hexagon::A4_cmphgti:
1790  case Hexagon::A4_cmphgtui:
1791  SrcReg = MI.getOperand(1).getReg();
1792  Mask = 0xFFFF;
1793  break;
1794  }
1795 
1796  // Set the value/second source register.
1797  switch (Opc) {
1798  case Hexagon::C2_cmpeq:
1799  case Hexagon::C2_cmpeqp:
1800  case Hexagon::C2_cmpgt:
1801  case Hexagon::C2_cmpgtp:
1802  case Hexagon::C2_cmpgtu:
1803  case Hexagon::C2_cmpgtup:
1804  case Hexagon::A4_cmpbeq:
1805  case Hexagon::A4_cmpbgt:
1806  case Hexagon::A4_cmpbgtu:
1807  case Hexagon::A4_cmpheq:
1808  case Hexagon::A4_cmphgt:
1809  case Hexagon::A4_cmphgtu:
1810  case Hexagon::C4_cmpneq:
1811  case Hexagon::C4_cmplte:
1812  case Hexagon::C4_cmplteu:
1813  SrcReg2 = MI.getOperand(2).getReg();
1814  return true;
1815 
1816  case Hexagon::C2_cmpeqi:
1817  case Hexagon::C2_cmpgtui:
1818  case Hexagon::C2_cmpgti:
1819  case Hexagon::C4_cmpneqi:
1820  case Hexagon::C4_cmplteui:
1821  case Hexagon::C4_cmpltei:
1822  case Hexagon::A4_cmpbeqi:
1823  case Hexagon::A4_cmpbgti:
1824  case Hexagon::A4_cmpbgtui:
1825  case Hexagon::A4_cmpheqi:
1826  case Hexagon::A4_cmphgti:
1827  case Hexagon::A4_cmphgtui: {
1828  SrcReg2 = 0;
1829  const MachineOperand &Op2 = MI.getOperand(2);
1830  if (!Op2.isImm())
1831  return false;
1832  Value = MI.getOperand(2).getImm();
1833  return true;
1834  }
1835  }
1836 
1837  return false;
1838 }
1839 
1841  const MachineInstr &MI,
1842  unsigned *PredCost) const {
1843  return getInstrTimingClassLatency(ItinData, MI);
1844 }
1845 
1847  const TargetSubtargetInfo &STI) const {
1848  const InstrItineraryData *II = STI.getInstrItineraryData();
1849  return static_cast<const HexagonSubtarget&>(STI).createDFAPacketizer(II);
1850 }
1851 
1852 // Inspired by this pair:
1853 // %r13 = L2_loadri_io %r29, 136; mem:LD4[FixedStack0]
1854 // S2_storeri_io %r29, 132, killed %r1; flags: mem:ST4[FixedStack1]
1855 // Currently AA considers the addresses in these instructions to be aliasing.
1857  const MachineInstr &MIa, const MachineInstr &MIb,
1858  AliasAnalysis *AA) const {
1859  if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects() ||
1861  return false;
1862 
1863  // Instructions that are pure loads, not loads and stores like memops are not
1864  // dependent.
1865  if (MIa.mayLoad() && !isMemOp(MIa) && MIb.mayLoad() && !isMemOp(MIb))
1866  return true;
1867 
1868  // Get the base register in MIa.
1869  unsigned BasePosA, OffsetPosA;
1870  if (!getBaseAndOffsetPosition(MIa, BasePosA, OffsetPosA))
1871  return false;
1872  const MachineOperand &BaseA = MIa.getOperand(BasePosA);
1873  unsigned BaseRegA = BaseA.getReg();
1874  unsigned BaseSubA = BaseA.getSubReg();
1875 
1876  // Get the base register in MIb.
1877  unsigned BasePosB, OffsetPosB;
1878  if (!getBaseAndOffsetPosition(MIb, BasePosB, OffsetPosB))
1879  return false;
1880  const MachineOperand &BaseB = MIb.getOperand(BasePosB);
1881  unsigned BaseRegB = BaseB.getReg();
1882  unsigned BaseSubB = BaseB.getSubReg();
1883 
1884  if (BaseRegA != BaseRegB || BaseSubA != BaseSubB)
1885  return false;
1886 
1887  // Get the access sizes.
1888  unsigned SizeA = getMemAccessSize(MIa);
1889  unsigned SizeB = getMemAccessSize(MIb);
1890 
1891  // Get the offsets. Handle immediates only for now.
1892  const MachineOperand &OffA = MIa.getOperand(OffsetPosA);
1893  const MachineOperand &OffB = MIb.getOperand(OffsetPosB);
1894  if (!MIa.getOperand(OffsetPosA).isImm() ||
1895  !MIb.getOperand(OffsetPosB).isImm())
1896  return false;
1897  int OffsetA = isPostIncrement(MIa) ? 0 : OffA.getImm();
1898  int OffsetB = isPostIncrement(MIb) ? 0 : OffB.getImm();
1899 
1900  // This is a mem access with the same base register and known offsets from it.
1901  // Reason about it.
1902  if (OffsetA > OffsetB) {
1903  uint64_t OffDiff = (uint64_t)((int64_t)OffsetA - (int64_t)OffsetB);
1904  return SizeB <= OffDiff;
1905  }
1906  if (OffsetA < OffsetB) {
1907  uint64_t OffDiff = (uint64_t)((int64_t)OffsetB - (int64_t)OffsetA);
1908  return SizeA <= OffDiff;
1909  }
1910 
1911  return false;
1912 }
1913 
1914 /// If the instruction is an increment of a constant value, return the amount.
1916  int &Value) const {
1917  if (isPostIncrement(MI)) {
1918  unsigned BasePos = 0, OffsetPos = 0;
1919  if (!getBaseAndOffsetPosition(MI, BasePos, OffsetPos))
1920  return false;
1921  const MachineOperand &OffsetOp = MI.getOperand(OffsetPos);
1922  if (OffsetOp.isImm()) {
1923  Value = OffsetOp.getImm();
1924  return true;
1925  }
1926  } else if (MI.getOpcode() == Hexagon::A2_addi) {
1927  const MachineOperand &AddOp = MI.getOperand(2);
1928  if (AddOp.isImm()) {
1929  Value = AddOp.getImm();
1930  return true;
1931  }
1932  }
1933 
1934  return false;
1935 }
1936 
1937 std::pair<unsigned, unsigned>
1939  return std::make_pair(TF & ~HexagonII::MO_Bitmasks,
1940  TF & HexagonII::MO_Bitmasks);
1941 }
1942 
1945  using namespace HexagonII;
1946 
1947  static const std::pair<unsigned, const char*> Flags[] = {
1948  {MO_PCREL, "hexagon-pcrel"},
1949  {MO_GOT, "hexagon-got"},
1950  {MO_LO16, "hexagon-lo16"},
1951  {MO_HI16, "hexagon-hi16"},
1952  {MO_GPREL, "hexagon-gprel"},
1953  {MO_GDGOT, "hexagon-gdgot"},
1954  {MO_GDPLT, "hexagon-gdplt"},
1955  {MO_IE, "hexagon-ie"},
1956  {MO_IEGOT, "hexagon-iegot"},
1957  {MO_TPREL, "hexagon-tprel"}
1958  };
1959  return makeArrayRef(Flags);
1960 }
1961 
1964  using namespace HexagonII;
1965 
1966  static const std::pair<unsigned, const char*> Flags[] = {
1967  {HMOTF_ConstExtended, "hexagon-ext"}
1968  };
1969  return makeArrayRef(Flags);
1970 }
1971 
1974  const TargetRegisterClass *TRC;
1975  if (VT == MVT::i1) {
1976  TRC = &Hexagon::PredRegsRegClass;
1977  } else if (VT == MVT::i32 || VT == MVT::f32) {
1978  TRC = &Hexagon::IntRegsRegClass;
1979  } else if (VT == MVT::i64 || VT == MVT::f64) {
1980  TRC = &Hexagon::DoubleRegsRegClass;
1981  } else {
1982  llvm_unreachable("Cannot handle this register class");
1983  }
1984 
1985  unsigned NewReg = MRI.createVirtualRegister(TRC);
1986  return NewReg;
1987 }
1988 
1990  return (getAddrMode(MI) == HexagonII::AbsoluteSet);
1991 }
1992 
1994  const uint64_t F = MI.getDesc().TSFlags;
1996 }
1997 
1999  return getAddrMode(MI) == HexagonII::BaseImmOffset;
2000 }
2001 
2003  return !isTC1(MI) && !isTC2Early(MI) && !MI.getDesc().mayLoad() &&
2004  !MI.getDesc().mayStore() &&
2005  MI.getDesc().getOpcode() != Hexagon::S2_allocframe &&
2006  MI.getDesc().getOpcode() != Hexagon::L2_deallocframe &&
2007  !isMemOp(MI) && !MI.isBranch() && !MI.isReturn() && !MI.isCall();
2008 }
2009 
2010 // Return true if the instruction is a compund branch instruction.
2012  return getType(MI) == HexagonII::TypeCJ && MI.isBranch();
2013 }
2014 
2015 // TODO: In order to have isExtendable for fpimm/f32Ext, we need to handle
2016 // isFPImm and later getFPImm as well.
2018  const uint64_t F = MI.getDesc().TSFlags;
2020  if (isExtended) // Instruction must be extended.
2021  return true;
2022 
2023  unsigned isExtendable =
2025  if (!isExtendable)
2026  return false;
2027 
2028  if (MI.isCall())
2029  return false;
2030 
2031  short ExtOpNum = getCExtOpNum(MI);
2032  const MachineOperand &MO = MI.getOperand(ExtOpNum);
2033  // Use MO operand flags to determine if MO
2034  // has the HMOTF_ConstExtended flag set.
2036  return true;
2037  // If this is a Machine BB address we are talking about, and it is
2038  // not marked as extended, say so.
2039  if (MO.isMBB())
2040  return false;
2041 
2042  // We could be using an instruction with an extendable immediate and shoehorn
2043  // a global address into it. If it is a global address it will be constant
2044  // extended. We do this for COMBINE.
2045  if (MO.isGlobal() || MO.isSymbol() || MO.isBlockAddress() ||
2046  MO.isJTI() || MO.isCPI() || MO.isFPImm())
2047  return true;
2048 
2049  // If the extendable operand is not 'Immediate' type, the instruction should
2050  // have 'isExtended' flag set.
2051  assert(MO.isImm() && "Extendable operand must be Immediate type");
2052 
2053  int MinValue = getMinValue(MI);
2054  int MaxValue = getMaxValue(MI);
2055  int ImmValue = MO.getImm();
2056 
2057  return (ImmValue < MinValue || ImmValue > MaxValue);
2058 }
2059 
2061  switch (MI.getOpcode()) {
2062  case Hexagon::L4_return:
2063  case Hexagon::L4_return_t:
2064  case Hexagon::L4_return_f:
2065  case Hexagon::L4_return_tnew_pnt:
2066  case Hexagon::L4_return_fnew_pnt:
2067  case Hexagon::L4_return_tnew_pt:
2068  case Hexagon::L4_return_fnew_pt:
2069  return true;
2070  }
2071  return false;
2072 }
2073 
2074 // Return true when ConsMI uses a register defined by ProdMI.
2076  const MachineInstr &ConsMI) const {
2077  if (!ProdMI.getDesc().getNumDefs())
2078  return false;
2079  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
2080 
2085 
2086  parseOperands(ProdMI, DefsA, UsesA);
2087  parseOperands(ConsMI, DefsB, UsesB);
2088 
2089  for (auto &RegA : DefsA)
2090  for (auto &RegB : UsesB) {
2091  // True data dependency.
2092  if (RegA == RegB)
2093  return true;
2094 
2096  for (MCSubRegIterator SubRegs(RegA, &HRI); SubRegs.isValid(); ++SubRegs)
2097  if (RegB == *SubRegs)
2098  return true;
2099 
2101  for (MCSubRegIterator SubRegs(RegB, &HRI); SubRegs.isValid(); ++SubRegs)
2102  if (RegA == *SubRegs)
2103  return true;
2104  }
2105 
2106  return false;
2107 }
2108 
2109 // Returns true if the instruction is alread a .cur.
2111  switch (MI.getOpcode()) {
2112  case Hexagon::V6_vL32b_cur_pi:
2113  case Hexagon::V6_vL32b_cur_ai:
2114  return true;
2115  }
2116  return false;
2117 }
2118 
2119 // Returns true, if any one of the operands is a dot new
2120 // insn, whether it is predicated dot new or register dot new.
2122  if (isNewValueInst(MI) || (isPredicated(MI) && isPredicatedNew(MI)))
2123  return true;
2124 
2125  return false;
2126 }
2127 
2128 /// Symmetrical. See if these two instructions are fit for duplex pair.
2130  const MachineInstr &MIb) const {
2133  return (isDuplexPairMatch(MIaG, MIbG) || isDuplexPairMatch(MIbG, MIaG));
2134 }
2135 
2137  if (MI.mayLoad() || MI.mayStore() || MI.isCompare())
2138  return true;
2139 
2140  // Multiply
2141  unsigned SchedClass = MI.getDesc().getSchedClass();
2142  return is_TC4x(SchedClass) || is_TC3x(SchedClass);
2143 }
2144 
2145 bool HexagonInstrInfo::isEndLoopN(unsigned Opcode) const {
2146  return (Opcode == Hexagon::ENDLOOP0 ||
2147  Opcode == Hexagon::ENDLOOP1);
2148 }
2149 
2150 bool HexagonInstrInfo::isExpr(unsigned OpType) const {
2151  switch(OpType) {
2158  return true;
2159  default:
2160  return false;
2161  }
2162 }
2163 
2165  const MCInstrDesc &MID = MI.getDesc();
2166  const uint64_t F = MID.TSFlags;
2168  return true;
2169 
2170  // TODO: This is largely obsolete now. Will need to be removed
2171  // in consecutive patches.
2172  switch (MI.getOpcode()) {
2173  // PS_fi and PS_fia remain special cases.
2174  case Hexagon::PS_fi:
2175  case Hexagon::PS_fia:
2176  return true;
2177  default:
2178  return false;
2179  }
2180  return false;
2181 }
2182 
2183 // This returns true in two cases:
2184 // - The OP code itself indicates that this is an extended instruction.
2185 // - One of MOs has been marked with HMOTF_ConstExtended flag.
2187  // First check if this is permanently extended op code.
2188  const uint64_t F = MI.getDesc().TSFlags;
2190  return true;
2191  // Use MO operand flags to determine if one of MI's operands
2192  // has HMOTF_ConstExtended flag set.
2193  for (const MachineOperand &MO : MI.operands())
2194  if (MO.getTargetFlags() & HexagonII::HMOTF_ConstExtended)
2195  return true;
2196  return false;
2197 }
2198 
2200  unsigned Opcode = MI.getOpcode();
2201  const uint64_t F = get(Opcode).TSFlags;
2202  return (F >> HexagonII::FPPos) & HexagonII::FPMask;
2203 }
2204 
2205 // No V60 HVX VMEM with A_INDIRECT.
2207  const MachineInstr &J) const {
2208  if (!isHVXVec(I))
2209  return false;
2210  if (!I.mayLoad() && !I.mayStore())
2211  return false;
2212  return J.isIndirectBranch() || isIndirectCall(J) || isIndirectL4Return(J);
2213 }
2214 
2216  switch (MI.getOpcode()) {
2217  case Hexagon::J2_callr:
2218  case Hexagon::J2_callrf:
2219  case Hexagon::J2_callrt:
2220  case Hexagon::PS_call_nr:
2221  return true;
2222  }
2223  return false;
2224 }
2225 
2227  switch (MI.getOpcode()) {
2228  case Hexagon::L4_return:
2229  case Hexagon::L4_return_t:
2230  case Hexagon::L4_return_f:
2231  case Hexagon::L4_return_fnew_pnt:
2232  case Hexagon::L4_return_fnew_pt:
2233  case Hexagon::L4_return_tnew_pnt:
2234  case Hexagon::L4_return_tnew_pt:
2235  return true;
2236  }
2237  return false;
2238 }
2239 
2241  switch (MI.getOpcode()) {
2242  case Hexagon::J2_jumpr:
2243  case Hexagon::J2_jumprt:
2244  case Hexagon::J2_jumprf:
2245  case Hexagon::J2_jumprtnewpt:
2246  case Hexagon::J2_jumprfnewpt:
2247  case Hexagon::J2_jumprtnew:
2248  case Hexagon::J2_jumprfnew:
2249  return true;
2250  }
2251  return false;
2252 }
2253 
2254 // Return true if a given MI can accommodate given offset.
2255 // Use abs estimate as oppose to the exact number.
2256 // TODO: This will need to be changed to use MC level
2257 // definition of instruction extendable field size.
2259  unsigned offset) const {
2260  // This selection of jump instructions matches to that what
2261  // analyzeBranch can parse, plus NVJ.
2262  if (isNewValueJump(MI)) // r9:2
2263  return isInt<11>(offset);
2264 
2265  switch (MI.getOpcode()) {
2266  // Still missing Jump to address condition on register value.
2267  default:
2268  return false;
2269  case Hexagon::J2_jump: // bits<24> dst; // r22:2
2270  case Hexagon::J2_call:
2271  case Hexagon::PS_call_nr:
2272  return isInt<24>(offset);
2273  case Hexagon::J2_jumpt: //bits<17> dst; // r15:2
2274  case Hexagon::J2_jumpf:
2275  case Hexagon::J2_jumptnew:
2276  case Hexagon::J2_jumptnewpt:
2277  case Hexagon::J2_jumpfnew:
2278  case Hexagon::J2_jumpfnewpt:
2279  case Hexagon::J2_callt:
2280  case Hexagon::J2_callf:
2281  return isInt<17>(offset);
2282  case Hexagon::J2_loop0i:
2283  case Hexagon::J2_loop0iext:
2284  case Hexagon::J2_loop0r:
2285  case Hexagon::J2_loop0rext:
2286  case Hexagon::J2_loop1i:
2287  case Hexagon::J2_loop1iext:
2288  case Hexagon::J2_loop1r:
2289  case Hexagon::J2_loop1rext:
2290  return isInt<9>(offset);
2291  // TODO: Add all the compound branches here. Can we do this in Relation model?
2292  case Hexagon::J4_cmpeqi_tp0_jump_nt:
2293  case Hexagon::J4_cmpeqi_tp1_jump_nt:
2294  case Hexagon::J4_cmpeqn1_tp0_jump_nt:
2295  case Hexagon::J4_cmpeqn1_tp1_jump_nt:
2296  return isInt<11>(offset);
2297  }
2298 }
2299 
2301  const MachineInstr &ESMI) const {
2302  bool isLate = isLateResultInstr(LRMI);
2303  bool isEarly = isEarlySourceInstr(ESMI);
2304 
2305  LLVM_DEBUG(dbgs() << "V60" << (isLate ? "-LR " : " -- "));
2306  LLVM_DEBUG(LRMI.dump());
2307  LLVM_DEBUG(dbgs() << "V60" << (isEarly ? "-ES " : " -- "));
2308  LLVM_DEBUG(ESMI.dump());
2309 
2310  if (isLate && isEarly) {
2311  LLVM_DEBUG(dbgs() << "++Is Late Result feeding Early Source\n");
2312  return true;
2313  }
2314 
2315  return false;
2316 }
2317 
2319  switch (MI.getOpcode()) {
2320  case TargetOpcode::EXTRACT_SUBREG:
2321  case TargetOpcode::INSERT_SUBREG:
2322  case TargetOpcode::SUBREG_TO_REG:
2323  case TargetOpcode::REG_SEQUENCE:
2324  case TargetOpcode::IMPLICIT_DEF:
2325  case TargetOpcode::COPY:
2327  case TargetOpcode::PHI:
2328  return false;
2329  default:
2330  break;
2331  }
2332 
2333  unsigned SchedClass = MI.getDesc().getSchedClass();
2334  return !is_TC1(SchedClass);
2335 }
2336 
2338  // Instructions with iclass A_CVI_VX and attribute A_CVI_LATE uses a multiply
2339  // resource, but all operands can be received late like an ALU instruction.
2340  return getType(MI) == HexagonII::TypeCVI_VX_LATE;
2341 }
2342 
2344  unsigned Opcode = MI.getOpcode();
2345  return Opcode == Hexagon::J2_loop0i ||
2346  Opcode == Hexagon::J2_loop0r ||
2347  Opcode == Hexagon::J2_loop0iext ||
2348  Opcode == Hexagon::J2_loop0rext ||
2349  Opcode == Hexagon::J2_loop1i ||
2350  Opcode == Hexagon::J2_loop1r ||
2351  Opcode == Hexagon::J2_loop1iext ||
2352  Opcode == Hexagon::J2_loop1rext;
2353 }
2354 
2356  switch (MI.getOpcode()) {
2357  default: return false;
2358  case Hexagon::L4_iadd_memopw_io:
2359  case Hexagon::L4_isub_memopw_io:
2360  case Hexagon::L4_add_memopw_io:
2361  case Hexagon::L4_sub_memopw_io:
2362  case Hexagon::L4_and_memopw_io:
2363  case Hexagon::L4_or_memopw_io:
2364  case Hexagon::L4_iadd_memoph_io:
2365  case Hexagon::L4_isub_memoph_io:
2366  case Hexagon::L4_add_memoph_io:
2367  case Hexagon::L4_sub_memoph_io:
2368  case Hexagon::L4_and_memoph_io:
2369  case Hexagon::L4_or_memoph_io:
2370  case Hexagon::L4_iadd_memopb_io:
2371  case Hexagon::L4_isub_memopb_io:
2372  case Hexagon::L4_add_memopb_io:
2373  case Hexagon::L4_sub_memopb_io:
2374  case Hexagon::L4_and_memopb_io:
2375  case Hexagon::L4_or_memopb_io:
2376  case Hexagon::L4_ior_memopb_io:
2377  case Hexagon::L4_ior_memoph_io:
2378  case Hexagon::L4_ior_memopw_io:
2379  case Hexagon::L4_iand_memopb_io:
2380  case Hexagon::L4_iand_memoph_io:
2381  case Hexagon::L4_iand_memopw_io:
2382  return true;
2383  }
2384  return false;
2385 }
2386 
2388  const uint64_t F = MI.getDesc().TSFlags;
2390 }
2391 
2392 bool HexagonInstrInfo::isNewValue(unsigned Opcode) const {
2393  const uint64_t F = get(Opcode).TSFlags;
2395 }
2396 
2398  return isNewValueJump(MI) || isNewValueStore(MI);
2399 }
2400 
2402  return isNewValue(MI) && MI.isBranch();
2403 }
2404 
2405 bool HexagonInstrInfo::isNewValueJump(unsigned Opcode) const {
2406  return isNewValue(Opcode) && get(Opcode).isBranch() && isPredicated(Opcode);
2407 }
2408 
2410  const uint64_t F = MI.getDesc().TSFlags;
2412 }
2413 
2414 bool HexagonInstrInfo::isNewValueStore(unsigned Opcode) const {
2415  const uint64_t F = get(Opcode).TSFlags;
2417 }
2418 
2419 // Returns true if a particular operand is extendable for an instruction.
2421  unsigned OperandNum) const {
2422  const uint64_t F = MI.getDesc().TSFlags;
2424  == OperandNum;
2425 }
2426 
2428  const uint64_t F = MI.getDesc().TSFlags;
2429  assert(isPredicated(MI));
2431 }
2432 
2433 bool HexagonInstrInfo::isPredicatedNew(unsigned Opcode) const {
2434  const uint64_t F = get(Opcode).TSFlags;
2435  assert(isPredicated(Opcode));
2437 }
2438 
2440  const uint64_t F = MI.getDesc().TSFlags;
2441  return !((F >> HexagonII::PredicatedFalsePos) &
2443 }
2444 
2445 bool HexagonInstrInfo::isPredicatedTrue(unsigned Opcode) const {
2446  const uint64_t F = get(Opcode).TSFlags;
2447  // Make sure that the instruction is predicated.
2449  return !((F >> HexagonII::PredicatedFalsePos) &
2451 }
2452 
2453 bool HexagonInstrInfo::isPredicated(unsigned Opcode) const {
2454  const uint64_t F = get(Opcode).TSFlags;
2456 }
2457 
2458 bool HexagonInstrInfo::isPredicateLate(unsigned Opcode) const {
2459  const uint64_t F = get(Opcode).TSFlags;
2461 }
2462 
2463 bool HexagonInstrInfo::isPredictedTaken(unsigned Opcode) const {
2464  const uint64_t F = get(Opcode).TSFlags;
2465  assert(get(Opcode).isBranch() &&
2466  (isPredicatedNew(Opcode) || isNewValue(Opcode)));
2467  return (F >> HexagonII::TakenPos) & HexagonII::TakenMask;
2468 }
2469 
2471  return MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4 ||
2472  MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_EXT ||
2473  MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_PIC ||
2474  MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_EXT_PIC;
2475 }
2476 
2478  switch (MI.getOpcode()) {
2479  // Byte
2480  case Hexagon::L2_loadrb_io:
2481  case Hexagon::L4_loadrb_ur:
2482  case Hexagon::L4_loadrb_ap:
2483  case Hexagon::L2_loadrb_pr:
2484  case Hexagon::L2_loadrb_pbr:
2485  case Hexagon::L2_loadrb_pi:
2486  case Hexagon::L2_loadrb_pci:
2487  case Hexagon::L2_loadrb_pcr:
2488  case Hexagon::L2_loadbsw2_io:
2489  case Hexagon::L4_loadbsw2_ur:
2490  case Hexagon::L4_loadbsw2_ap:
2491  case Hexagon::L2_loadbsw2_pr:
2492  case Hexagon::L2_loadbsw2_pbr:
2493  case Hexagon::L2_loadbsw2_pi:
2494  case Hexagon::L2_loadbsw2_pci:
2495  case Hexagon::L2_loadbsw2_pcr:
2496  case Hexagon::L2_loadbsw4_io:
2497  case Hexagon::L4_loadbsw4_ur:
2498  case Hexagon::L4_loadbsw4_ap:
2499  case Hexagon::L2_loadbsw4_pr:
2500  case Hexagon::L2_loadbsw4_pbr:
2501  case Hexagon::L2_loadbsw4_pi:
2502  case Hexagon::L2_loadbsw4_pci:
2503  case Hexagon::L2_loadbsw4_pcr:
2504  case Hexagon::L4_loadrb_rr:
2505  case Hexagon::L2_ploadrbt_io:
2506  case Hexagon::L2_ploadrbt_pi:
2507  case Hexagon::L2_ploadrbf_io:
2508  case Hexagon::L2_ploadrbf_pi:
2509  case Hexagon::L2_ploadrbtnew_io:
2510  case Hexagon::L2_ploadrbfnew_io:
2511  case Hexagon::L4_ploadrbt_rr:
2512  case Hexagon::L4_ploadrbf_rr:
2513  case Hexagon::L4_ploadrbtnew_rr:
2514  case Hexagon::L4_ploadrbfnew_rr:
2515  case Hexagon::L2_ploadrbtnew_pi:
2516  case Hexagon::L2_ploadrbfnew_pi:
2517  case Hexagon::L4_ploadrbt_abs:
2518  case Hexagon::L4_ploadrbf_abs:
2519  case Hexagon::L4_ploadrbtnew_abs:
2520  case Hexagon::L4_ploadrbfnew_abs:
2521  case Hexagon::L2_loadrbgp:
2522  // Half
2523  case Hexagon::L2_loadrh_io:
2524  case Hexagon::L4_loadrh_ur:
2525  case Hexagon::L4_loadrh_ap:
2526  case Hexagon::L2_loadrh_pr:
2527  case Hexagon::L2_loadrh_pbr:
2528  case Hexagon::L2_loadrh_pi:
2529  case Hexagon::L2_loadrh_pci:
2530  case Hexagon::L2_loadrh_pcr:
2531  case Hexagon::L4_loadrh_rr:
2532  case Hexagon::L2_ploadrht_io:
2533  case Hexagon::L2_ploadrht_pi:
2534  case Hexagon::L2_ploadrhf_io:
2535  case Hexagon::L2_ploadrhf_pi:
2536  case Hexagon::L2_ploadrhtnew_io:
2537  case Hexagon::L2_ploadrhfnew_io:
2538  case Hexagon::L4_ploadrht_rr:
2539  case Hexagon::L4_ploadrhf_rr:
2540  case Hexagon::L4_ploadrhtnew_rr:
2541  case Hexagon::L4_ploadrhfnew_rr:
2542  case Hexagon::L2_ploadrhtnew_pi:
2543  case Hexagon::L2_ploadrhfnew_pi:
2544  case Hexagon::L4_ploadrht_abs:
2545  case Hexagon::L4_ploadrhf_abs:
2546  case Hexagon::L4_ploadrhtnew_abs:
2547  case Hexagon::L4_ploadrhfnew_abs:
2548  case Hexagon::L2_loadrhgp:
2549  return true;
2550  default:
2551  return false;
2552  }
2553 }
2554 
2556  const uint64_t F = MI.getDesc().TSFlags;
2557  return (F >> HexagonII::SoloPos) & HexagonII::SoloMask;
2558 }
2559 
2561  switch (MI.getOpcode()) {
2562  case Hexagon::STriw_pred:
2563  case Hexagon::LDriw_pred:
2564  return true;
2565  default:
2566  return false;
2567  }
2568 }
2569 
2571  if (!MI.isBranch())
2572  return false;
2573 
2574  for (auto &Op : MI.operands())
2575  if (Op.isGlobal() || Op.isSymbol())
2576  return true;
2577  return false;
2578 }
2579 
2580 // Returns true when SU has a timing class TC1.
2582  unsigned SchedClass = MI.getDesc().getSchedClass();
2583  return is_TC1(SchedClass);
2584 }
2585 
2587  unsigned SchedClass = MI.getDesc().getSchedClass();
2588  return is_TC2(SchedClass);
2589 }
2590 
2592  unsigned SchedClass = MI.getDesc().getSchedClass();
2593  return is_TC2early(SchedClass);
2594 }
2595 
2597  unsigned SchedClass = MI.getDesc().getSchedClass();
2598  return is_TC4x(SchedClass);
2599 }
2600 
2601 // Schedule this ASAP.
2603  const MachineInstr &MI2) const {
2604  if (mayBeCurLoad(MI1)) {
2605  // if (result of SU is used in Next) return true;
2606  unsigned DstReg = MI1.getOperand(0).getReg();
2607  int N = MI2.getNumOperands();
2608  for (int I = 0; I < N; I++)
2609  if (MI2.getOperand(I).isReg() && DstReg == MI2.getOperand(I).getReg())
2610  return true;
2611  }
2612  if (mayBeNewStore(MI2))
2613  if (MI2.getOpcode() == Hexagon::V6_vS32b_pi)
2614  if (MI1.getOperand(0).isReg() && MI2.getOperand(3).isReg() &&
2615  MI1.getOperand(0).getReg() == MI2.getOperand(3).getReg())
2616  return true;
2617  return false;
2618 }
2619 
2621  const uint64_t V = getType(MI);
2623 }
2624 
2625 // Check if the Offset is a valid auto-inc imm by Load/Store Type.
2627  int Size = VT.getSizeInBits() / 8;
2628  if (Offset % Size != 0)
2629  return false;
2630  int Count = Offset / Size;
2631 
2632  switch (VT.getSimpleVT().SimpleTy) {
2633  // For scalars the auto-inc is s4
2634  case MVT::i8:
2635  case MVT::i16:
2636  case MVT::i32:
2637  case MVT::i64:
2638  case MVT::f32:
2639  case MVT::f64:
2640  case MVT::v2i16:
2641  case MVT::v2i32:
2642  case MVT::v4i8:
2643  case MVT::v4i16:
2644  case MVT::v8i8:
2645  return isInt<4>(Count);
2646  // For HVX vectors the auto-inc is s3
2647  case MVT::v64i8:
2648  case MVT::v32i16:
2649  case MVT::v16i32:
2650  case MVT::v8i64:
2651  case MVT::v128i8:
2652  case MVT::v64i16:
2653  case MVT::v32i32:
2654  case MVT::v16i64:
2655  return isInt<3>(Count);
2656  default:
2657  break;
2658  }
2659 
2660  llvm_unreachable("Not an valid type!");
2661 }
2662 
2663 bool HexagonInstrInfo::isValidOffset(unsigned Opcode, int Offset,
2664  const TargetRegisterInfo *TRI, bool Extend) const {
2665  // This function is to check whether the "Offset" is in the correct range of
2666  // the given "Opcode". If "Offset" is not in the correct range, "A2_addi" is
2667  // inserted to calculate the final address. Due to this reason, the function
2668  // assumes that the "Offset" has correct alignment.
2669  // We used to assert if the offset was not properly aligned, however,
2670  // there are cases where a misaligned pointer recast can cause this
2671  // problem, and we need to allow for it. The front end warns of such
2672  // misaligns with respect to load size.
2673  switch (Opcode) {
2674  case Hexagon::PS_vstorerq_ai:
2675  case Hexagon::PS_vstorerw_ai:
2676  case Hexagon::PS_vstorerw_nt_ai:
2677  case Hexagon::PS_vloadrq_ai:
2678  case Hexagon::PS_vloadrw_ai:
2679  case Hexagon::PS_vloadrw_nt_ai:
2680  case Hexagon::V6_vL32b_ai:
2681  case Hexagon::V6_vS32b_ai:
2682  case Hexagon::V6_vL32b_nt_ai:
2683  case Hexagon::V6_vS32b_nt_ai:
2684  case Hexagon::V6_vL32Ub_ai:
2685  case Hexagon::V6_vS32Ub_ai: {
2686  unsigned VectorSize = TRI->getSpillSize(Hexagon::HvxVRRegClass);
2687  assert(isPowerOf2_32(VectorSize));
2688  if (Offset & (VectorSize-1))
2689  return false;
2690  return isInt<4>(Offset >> Log2_32(VectorSize));
2691  }
2692 
2693  case Hexagon::J2_loop0i:
2694  case Hexagon::J2_loop1i:
2695  return isUInt<10>(Offset);
2696 
2697  case Hexagon::S4_storeirb_io:
2698  case Hexagon::S4_storeirbt_io:
2699  case Hexagon::S4_storeirbf_io:
2700  return isUInt<6>(Offset);
2701 
2702  case Hexagon::S4_storeirh_io:
2703  case Hexagon::S4_storeirht_io:
2704  case Hexagon::S4_storeirhf_io:
2705  return isShiftedUInt<6,1>(Offset);
2706 
2707  case Hexagon::S4_storeiri_io:
2708  case Hexagon::S4_storeirit_io:
2709  case Hexagon::S4_storeirif_io:
2710  return isShiftedUInt<6,2>(Offset);
2711  }
2712 
2713  if (Extend)
2714  return true;
2715 
2716  switch (Opcode) {
2717  case Hexagon::L2_loadri_io:
2718  case Hexagon::S2_storeri_io:
2719  return (Offset >= Hexagon_MEMW_OFFSET_MIN) &&
2720  (Offset <= Hexagon_MEMW_OFFSET_MAX);
2721 
2722  case Hexagon::L2_loadrd_io:
2723  case Hexagon::S2_storerd_io:
2724  return (Offset >= Hexagon_MEMD_OFFSET_MIN) &&
2725  (Offset <= Hexagon_MEMD_OFFSET_MAX);
2726 
2727  case Hexagon::L2_loadrh_io:
2728  case Hexagon::L2_loadruh_io:
2729  case Hexagon::S2_storerh_io:
2730  case Hexagon::S2_storerf_io:
2731  return (Offset >= Hexagon_MEMH_OFFSET_MIN) &&
2732  (Offset <= Hexagon_MEMH_OFFSET_MAX);
2733 
2734  case Hexagon::L2_loadrb_io:
2735  case Hexagon::L2_loadrub_io:
2736  case Hexagon::S2_storerb_io:
2737  return (Offset >= Hexagon_MEMB_OFFSET_MIN) &&
2738  (Offset <= Hexagon_MEMB_OFFSET_MAX);
2739 
2740  case Hexagon::A2_addi:
2741  return (Offset >= Hexagon_ADDI_OFFSET_MIN) &&
2742  (Offset <= Hexagon_ADDI_OFFSET_MAX);
2743 
2744  case Hexagon::L4_iadd_memopw_io:
2745  case Hexagon::L4_isub_memopw_io:
2746  case Hexagon::L4_add_memopw_io:
2747  case Hexagon::L4_sub_memopw_io:
2748  case Hexagon::L4_and_memopw_io:
2749  case Hexagon::L4_or_memopw_io:
2750  return (0 <= Offset && Offset <= 255);
2751 
2752  case Hexagon::L4_iadd_memoph_io:
2753  case Hexagon::L4_isub_memoph_io:
2754  case Hexagon::L4_add_memoph_io:
2755  case Hexagon::L4_sub_memoph_io:
2756  case Hexagon::L4_and_memoph_io:
2757  case Hexagon::L4_or_memoph_io:
2758  return (0 <= Offset && Offset <= 127);
2759 
2760  case Hexagon::L4_iadd_memopb_io:
2761  case Hexagon::L4_isub_memopb_io:
2762  case Hexagon::L4_add_memopb_io:
2763  case Hexagon::L4_sub_memopb_io:
2764  case Hexagon::L4_and_memopb_io:
2765  case Hexagon::L4_or_memopb_io:
2766  return (0 <= Offset && Offset <= 63);
2767 
2768  // LDriw_xxx and STriw_xxx are pseudo operations, so it has to take offset of
2769  // any size. Later pass knows how to handle it.
2770  case Hexagon::STriw_pred:
2771  case Hexagon::LDriw_pred:
2772  case Hexagon::STriw_ctr:
2773  case Hexagon::LDriw_ctr:
2774  return true;
2775 
2776  case Hexagon::PS_fi:
2777  case Hexagon::PS_fia:
2778  case Hexagon::INLINEASM:
2779  return true;
2780 
2781  case Hexagon::L2_ploadrbt_io:
2782  case Hexagon::L2_ploadrbf_io:
2783  case Hexagon::L2_ploadrubt_io:
2784  case Hexagon::L2_ploadrubf_io:
2785  case Hexagon::S2_pstorerbt_io:
2786  case Hexagon::S2_pstorerbf_io:
2787  return isUInt<6>(Offset);
2788 
2789  case Hexagon::L2_ploadrht_io:
2790  case Hexagon::L2_ploadrhf_io:
2791  case Hexagon::L2_ploadruht_io:
2792  case Hexagon::L2_ploadruhf_io:
2793  case Hexagon::S2_pstorerht_io:
2794  case Hexagon::S2_pstorerhf_io:
2795  return isShiftedUInt<6,1>(Offset);
2796 
2797  case Hexagon::L2_ploadrit_io:
2798  case Hexagon::L2_ploadrif_io:
2799  case Hexagon::S2_pstorerit_io:
2800  case Hexagon::S2_pstorerif_io:
2801  return isShiftedUInt<6,2>(Offset);
2802 
2803  case Hexagon::L2_ploadrdt_io:
2804  case Hexagon::L2_ploadrdf_io:
2805  case Hexagon::S2_pstorerdt_io:
2806  case Hexagon::S2_pstorerdf_io:
2807  return isShiftedUInt<6,3>(Offset);
2808  } // switch
2809 
2810  llvm_unreachable("No offset range is defined for this opcode. "
2811  "Please define it in the above switch statement!");
2812 }
2813 
2815  return isHVXVec(MI) && isAccumulator(MI);
2816 }
2817 
2819  const uint64_t F = get(MI.getOpcode()).TSFlags;
2820  const uint64_t V = ((F >> HexagonII::TypePos) & HexagonII::TypeMask);
2821  return
2822  V == HexagonII::TypeCVI_VA ||
2824 }
2825 
2827  const MachineInstr &ConsMI) const {
2828  if (EnableACCForwarding && isVecAcc(ProdMI) && isVecAcc(ConsMI))
2829  return true;
2830 
2831  if (EnableALUForwarding && (isVecALU(ConsMI) || isLateSourceInstr(ConsMI)))
2832  return true;
2833 
2834  if (mayBeNewStore(ConsMI))
2835  return true;
2836 
2837  return false;
2838 }
2839 
2841  switch (MI.getOpcode()) {
2842  // Byte
2843  case Hexagon::L2_loadrub_io:
2844  case Hexagon::L4_loadrub_ur:
2845  case Hexagon::L4_loadrub_ap:
2846  case Hexagon::L2_loadrub_pr:
2847  case Hexagon::L2_loadrub_pbr:
2848  case Hexagon::L2_loadrub_pi:
2849  case Hexagon::L2_loadrub_pci:
2850  case Hexagon::L2_loadrub_pcr:
2851  case Hexagon::L2_loadbzw2_io:
2852  case Hexagon::L4_loadbzw2_ur:
2853  case Hexagon::L4_loadbzw2_ap:
2854  case Hexagon::L2_loadbzw2_pr:
2855  case Hexagon::L2_loadbzw2_pbr:
2856  case Hexagon::L2_loadbzw2_pi:
2857  case Hexagon::L2_loadbzw2_pci:
2858  case Hexagon::L2_loadbzw2_pcr:
2859  case Hexagon::L2_loadbzw4_io:
2860  case Hexagon::L4_loadbzw4_ur:
2861  case Hexagon::L4_loadbzw4_ap:
2862  case Hexagon::L2_loadbzw4_pr:
2863  case Hexagon::L2_loadbzw4_pbr:
2864  case Hexagon::L2_loadbzw4_pi:
2865  case Hexagon::L2_loadbzw4_pci:
2866  case Hexagon::L2_loadbzw4_pcr:
2867  case Hexagon::L4_loadrub_rr:
2868  case Hexagon::L2_ploadrubt_io:
2869  case Hexagon::L2_ploadrubt_pi:
2870  case Hexagon::L2_ploadrubf_io:
2871  case Hexagon::L2_ploadrubf_pi:
2872  case Hexagon::L2_ploadrubtnew_io:
2873  case Hexagon::L2_ploadrubfnew_io:
2874  case Hexagon::L4_ploadrubt_rr:
2875  case Hexagon::L4_ploadrubf_rr:
2876  case Hexagon::L4_ploadrubtnew_rr:
2877  case Hexagon::L4_ploadrubfnew_rr:
2878  case Hexagon::L2_ploadrubtnew_pi:
2879  case Hexagon::L2_ploadrubfnew_pi:
2880  case Hexagon::L4_ploadrubt_abs:
2881  case Hexagon::L4_ploadrubf_abs:
2882  case Hexagon::L4_ploadrubtnew_abs:
2883  case Hexagon::L4_ploadrubfnew_abs:
2884  case Hexagon::L2_loadrubgp:
2885  // Half
2886  case Hexagon::L2_loadruh_io:
2887  case Hexagon::L4_loadruh_ur:
2888  case Hexagon::L4_loadruh_ap:
2889  case Hexagon::L2_loadruh_pr:
2890  case Hexagon::L2_loadruh_pbr:
2891  case Hexagon::L2_loadruh_pi:
2892  case Hexagon::L2_loadruh_pci:
2893  case Hexagon::L2_loadruh_pcr:
2894  case Hexagon::L4_loadruh_rr:
2895  case Hexagon::L2_ploadruht_io:
2896  case Hexagon::L2_ploadruht_pi:
2897  case Hexagon::L2_ploadruhf_io:
2898  case Hexagon::L2_ploadruhf_pi:
2899  case Hexagon::L2_ploadruhtnew_io:
2900  case Hexagon::L2_ploadruhfnew_io:
2901  case Hexagon::L4_ploadruht_rr:
2902  case Hexagon::L4_ploadruhf_rr:
2903  case Hexagon::L4_ploadruhtnew_rr:
2904  case Hexagon::L4_ploadruhfnew_rr:
2905  case Hexagon::L2_ploadruhtnew_pi:
2906  case Hexagon::L2_ploadruhfnew_pi:
2907  case Hexagon::L4_ploadruht_abs:
2908  case Hexagon::L4_ploadruhf_abs:
2909  case Hexagon::L4_ploadruhtnew_abs:
2910  case Hexagon::L4_ploadruhfnew_abs:
2911  case Hexagon::L2_loadruhgp:
2912  return true;
2913  default:
2914  return false;
2915  }
2916 }
2917 
2918 // Add latency to instruction.
2920  const MachineInstr &MI2) const {
2921  if (isHVXVec(MI1) && isHVXVec(MI2))
2922  if (!isVecUsableNextPacket(MI1, MI2))
2923  return true;
2924  return false;
2925 }
2926 
2927 /// Get the base register and byte offset of a load/store instr.
2929  const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset,
2930  const TargetRegisterInfo *TRI) const {
2931  unsigned AccessSize = 0;
2932  BaseOp = getBaseAndOffset(LdSt, Offset, AccessSize);
2933  assert((!BaseOp || BaseOp->isReg()) &&
2934  "getMemOperandWithOffset only supports base "
2935  "operands of type register.");
2936  return BaseOp != nullptr;
2937 }
2938 
2939 /// Can these instructions execute at the same time in a bundle.
2941  const MachineInstr &Second) const {
2942  if (Second.mayStore() && First.getOpcode() == Hexagon::S2_allocframe) {
2943  const MachineOperand &Op = Second.getOperand(0);
2944  if (Op.isReg() && Op.isUse() && Op.getReg() == Hexagon::R29)
2945  return true;
2946  }
2947  if (DisableNVSchedule)
2948  return false;
2949  if (mayBeNewStore(Second)) {
2950  // Make sure the definition of the first instruction is the value being
2951  // stored.
2952  const MachineOperand &Stored =
2953  Second.getOperand(Second.getNumOperands() - 1);
2954  if (!Stored.isReg())
2955  return false;
2956  for (unsigned i = 0, e = First.getNumOperands(); i < e; ++i) {
2957  const MachineOperand &Op = First.getOperand(i);
2958  if (Op.isReg() && Op.isDef() && Op.getReg() == Stored.getReg())
2959  return true;
2960  }
2961  }
2962  return false;
2963 }
2964 
2966  unsigned Opc = CallMI.getOpcode();
2967  return Opc == Hexagon::PS_call_nr || Opc == Hexagon::PS_callr_nr;
2968 }
2969 
2971  for (auto &I : *B)
2972  if (I.isEHLabel())
2973  return true;
2974  return false;
2975 }
2976 
2977 // Returns true if an instruction can be converted into a non-extended
2978 // equivalent instruction.
2980  short NonExtOpcode;
2981  // Check if the instruction has a register form that uses register in place
2982  // of the extended operand, if so return that as the non-extended form.
2983  if (Hexagon::getRegForm(MI.getOpcode()) >= 0)
2984  return true;
2985 
2986  if (MI.getDesc().mayLoad() || MI.getDesc().mayStore()) {
2987  // Check addressing mode and retrieve non-ext equivalent instruction.
2988 
2989  switch (getAddrMode(MI)) {
2990  case HexagonII::Absolute:
2991  // Load/store with absolute addressing mode can be converted into
2992  // base+offset mode.
2993  NonExtOpcode = Hexagon::changeAddrMode_abs_io(MI.getOpcode());
2994  break;
2996  // Load/store with base+offset addressing mode can be converted into
2997  // base+register offset addressing mode. However left shift operand should
2998  // be set to 0.
2999  NonExtOpcode = Hexagon::changeAddrMode_io_rr(MI.getOpcode());
3000  break;
3002  NonExtOpcode = Hexagon::changeAddrMode_ur_rr(MI.getOpcode());
3003  break;
3004  default:
3005  return false;
3006  }
3007  if (NonExtOpcode < 0)
3008  return false;
3009  return true;
3010  }
3011  return false;
3012 }
3013 
3015  return Hexagon::getRealHWInstr(MI.getOpcode(),
3016  Hexagon::InstrType_Pseudo) >= 0;
3017 }
3018 
3020  const {
3022  while (I != E) {
3023  if (I->isBarrier())
3024  return true;
3025  ++I;
3026  }
3027  return false;
3028 }
3029 
3030 // Returns true, if a LD insn can be promoted to a cur load.
3032  const uint64_t F = MI.getDesc().TSFlags;
3034  Subtarget.hasV60Ops();
3035 }
3036 
3037 // Returns true, if a ST insn can be promoted to a new-value store.
3039  if (MI.mayStore() && !Subtarget.useNewValueStores())
3040  return false;
3041 
3042  const uint64_t F = MI.getDesc().TSFlags;
3044 }
3045 
3047  const MachineInstr &ConsMI) const {
3048  // There is no stall when ProdMI is not a V60 vector.
3049  if (!isHVXVec(ProdMI))
3050  return false;
3051 
3052  // There is no stall when ProdMI and ConsMI are not dependent.
3053  if (!isDependent(ProdMI, ConsMI))
3054  return false;
3055 
3056  // When Forward Scheduling is enabled, there is no stall if ProdMI and ConsMI
3057  // are scheduled in consecutive packets.
3058  if (isVecUsableNextPacket(ProdMI, ConsMI))
3059  return false;
3060 
3061  return true;
3062 }
3063 
3066  // There is no stall when I is not a V60 vector.
3067  if (!isHVXVec(MI))
3068  return false;
3069 
3071  MachineBasicBlock::const_instr_iterator MIE = MII->getParent()->instr_end();
3072 
3073  if (!MII->isBundle())
3074  return producesStall(*MII, MI);
3075 
3076  for (++MII; MII != MIE && MII->isInsideBundle(); ++MII) {
3077  const MachineInstr &J = *MII;
3078  if (producesStall(J, MI))
3079  return true;
3080  }
3081  return false;
3082 }
3083 
3085  unsigned PredReg) const {
3086  for (const MachineOperand &MO : MI.operands()) {
3087  // Predicate register must be explicitly defined.
3088  if (MO.isRegMask() && MO.clobbersPhysReg(PredReg))
3089  return false;
3090  if (MO.isReg() && MO.isDef() && MO.isImplicit() && (MO.getReg() == PredReg))
3091  return false;
3092  }
3093 
3094  // Instruction that produce late predicate cannot be used as sources of
3095  // dot-new.
3096  switch (MI.getOpcode()) {
3097  case Hexagon::A4_addp_c:
3098  case Hexagon::A4_subp_c:
3099  case Hexagon::A4_tlbmatch:
3100  case Hexagon::A5_ACS:
3101  case Hexagon::F2_sfinvsqrta:
3102  case Hexagon::F2_sfrecipa:
3103  case Hexagon::J2_endloop0:
3104  case Hexagon::J2_endloop01:
3105  case Hexagon::J2_ploop1si:
3106  case Hexagon::J2_ploop1sr:
3107  case Hexagon::J2_ploop2si:
3108  case Hexagon::J2_ploop2sr:
3109  case Hexagon::J2_ploop3si:
3110  case Hexagon::J2_ploop3sr:
3111  case Hexagon::S2_cabacdecbin:
3112  case Hexagon::S2_storew_locked:
3113  case Hexagon::S4_stored_locked:
3114  return false;
3115  }
3116  return true;
3117 }
3118 
3119 bool HexagonInstrInfo::PredOpcodeHasJMP_c(unsigned Opcode) const {
3120  return Opcode == Hexagon::J2_jumpt ||
3121  Opcode == Hexagon::J2_jumptpt ||
3122  Opcode == Hexagon::J2_jumpf ||
3123  Opcode == Hexagon::J2_jumpfpt ||
3124  Opcode == Hexagon::J2_jumptnew ||
3125  Opcode == Hexagon::J2_jumpfnew ||
3126  Opcode == Hexagon::J2_jumptnewpt ||
3127  Opcode == Hexagon::J2_jumpfnewpt;
3128 }
3129 
3131  if (Cond.empty() || !isPredicated(Cond[0].getImm()))
3132  return false;
3133  return !isPredicatedTrue(Cond[0].getImm());
3134 }
3135 
3137  const uint64_t F = MI.getDesc().TSFlags;
3139 }
3140 
3141 // Returns the base register in a memory access (load/store). The offset is
3142 // returned in Offset and the access size is returned in AccessSize.
3143 // If the base operand has a subregister or the offset field does not contain
3144 // an immediate value, return nullptr.
3146  int64_t &Offset,
3147  unsigned &AccessSize) const {
3148  // Return if it is not a base+offset type instruction or a MemOp.
3151  !isMemOp(MI) && !isPostIncrement(MI))
3152  return nullptr;
3153 
3154  AccessSize = getMemAccessSize(MI);
3155 
3156  unsigned BasePos = 0, OffsetPos = 0;
3157  if (!getBaseAndOffsetPosition(MI, BasePos, OffsetPos))
3158  return nullptr;
3159 
3160  // Post increment updates its EA after the mem access,
3161  // so we need to treat its offset as zero.
3162  if (isPostIncrement(MI)) {
3163  Offset = 0;
3164  } else {
3165  const MachineOperand &OffsetOp = MI.getOperand(OffsetPos);
3166  if (!OffsetOp.isImm())
3167  return nullptr;
3168  Offset = OffsetOp.getImm();
3169  }
3170 
3171  const MachineOperand &BaseOp = MI.getOperand(BasePos);
3172  if (BaseOp.getSubReg() != 0)
3173  return nullptr;
3174  return &const_cast<MachineOperand&>(BaseOp);
3175 }
3176 
3177 /// Return the position of the base and offset operands for this instruction.
3179  unsigned &BasePos, unsigned &OffsetPos) const {
3180  if (!isAddrModeWithOffset(MI) && !isPostIncrement(MI))
3181  return false;
3182 
3183  // Deal with memops first.
3184  if (isMemOp(MI)) {
3185  BasePos = 0;
3186  OffsetPos = 1;
3187  } else if (MI.mayStore()) {
3188  BasePos = 0;
3189  OffsetPos = 1;
3190  } else if (MI.mayLoad()) {
3191  BasePos = 1;
3192  OffsetPos = 2;
3193  } else
3194  return false;
3195 
3196  if (isPredicated(MI)) {
3197  BasePos++;
3198  OffsetPos++;
3199  }
3200  if (isPostIncrement(MI)) {
3201  BasePos++;
3202  OffsetPos++;
3203  }
3204 
3205  if (!MI.getOperand(BasePos).isReg() || !MI.getOperand(OffsetPos).isImm())
3206  return false;
3207 
3208  return true;
3209 }
3210 
3211 // Inserts branching instructions in reverse order of their occurrence.
3212 // e.g. jump_t t1 (i1)
3213 // jump t2 (i2)
3214 // Jumpers = {i2, i1}
3216  MachineBasicBlock& MBB) const {
3218  // If the block has no terminators, it just falls into the block after it.
3220  if (I == MBB.instr_begin())
3221  return Jumpers;
3222 
3223  // A basic block may looks like this:
3224  //
3225  // [ insn
3226  // EH_LABEL
3227  // insn
3228  // insn
3229  // insn
3230  // EH_LABEL
3231  // insn ]
3232  //
3233  // It has two succs but does not have a terminator
3234  // Don't know how to handle it.
3235  do {
3236  --I;
3237  if (I->isEHLabel())
3238  return Jumpers;
3239  } while (I != MBB.instr_begin());
3240 
3241  I = MBB.instr_end();
3242  --I;
3243 
3244  while (I->isDebugInstr()) {
3245  if (I == MBB.instr_begin())
3246  return Jumpers;
3247  --I;
3248  }
3249  if (!isUnpredicatedTerminator(*I))
3250  return Jumpers;
3251 
3252  // Get the last instruction in the block.
3253  MachineInstr *LastInst = &*I;
3254  Jumpers.push_back(LastInst);
3255  MachineInstr *SecondLastInst = nullptr;
3256  // Find one more terminator if present.
3257  do {
3258  if (&*I != LastInst && !I->isBundle() && isUnpredicatedTerminator(*I)) {
3259  if (!SecondLastInst) {
3260  SecondLastInst = &*I;
3261  Jumpers.push_back(SecondLastInst);
3262  } else // This is a third branch.
3263  return Jumpers;
3264  }
3265  if (I == MBB.instr_begin())
3266  break;
3267  --I;
3268  } while (true);
3269  return Jumpers;
3270 }
3271 
3272 // Returns Operand Index for the constant extended instruction.
3274  const uint64_t F = MI.getDesc().TSFlags;
3276 }
3277 
3278 // See if instruction could potentially be a duplex candidate.
3279 // If so, return its group. Zero otherwise.
3281  const MachineInstr &MI) const {
3282  unsigned DstReg, SrcReg, Src1Reg, Src2Reg;
3283 
3284  switch (MI.getOpcode()) {
3285  default:
3286  return HexagonII::HCG_None;
3287  //
3288  // Compound pairs.
3289  // "p0=cmp.eq(Rs16,Rt16); if (p0.new) jump:nt #r9:2"
3290  // "Rd16=#U6 ; jump #r9:2"
3291  // "Rd16=Rs16 ; jump #r9:2"
3292  //
3293  case Hexagon::C2_cmpeq:
3294  case Hexagon::C2_cmpgt:
3295  case Hexagon::C2_cmpgtu:
3296  DstReg = MI.getOperand(0).getReg();
3297  Src1Reg = MI.getOperand(1).getReg();
3298  Src2Reg = MI.getOperand(2).getReg();
3299  if (Hexagon::PredRegsRegClass.contains(DstReg) &&
3300  (Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
3301  isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg))
3302  return HexagonII::HCG_A;
3303  break;
3304  case Hexagon::C2_cmpeqi:
3305  case Hexagon::C2_cmpgti:
3306  case Hexagon::C2_cmpgtui:
3307  // P0 = cmp.eq(Rs,#u2)
3308  DstReg = MI.getOperand(0).getReg();
3309  SrcReg = MI.getOperand(1).getReg();
3310  if (Hexagon::PredRegsRegClass.contains(DstReg) &&
3311  (Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
3312  isIntRegForSubInst(SrcReg) && MI.getOperand(2).isImm() &&
3313  ((isUInt<5>(MI.getOperand(2).getImm())) ||
3314  (MI.getOperand(2).getImm() == -1)))
3315  return HexagonII::HCG_A;
3316  break;
3317  case Hexagon::A2_tfr:
3318  // Rd = Rs
3319  DstReg = MI.getOperand(0).getReg();
3320  SrcReg = MI.getOperand(1).getReg();
3321  if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg))
3322  return HexagonII::HCG_A;
3323  break;
3324  case Hexagon::A2_tfrsi:
3325  // Rd = #u6
3326  // Do not test for #u6 size since the const is getting extended
3327  // regardless and compound could be formed.
3328  DstReg = MI.getOperand(0).getReg();
3329  if (isIntRegForSubInst(DstReg))
3330  return HexagonII::HCG_A;
3331  break;
3332  case Hexagon::S2_tstbit_i:
3333  DstReg = MI.getOperand(0).getReg();
3334  Src1Reg = MI.getOperand(1).getReg();
3335  if (Hexagon::PredRegsRegClass.contains(DstReg) &&
3336  (Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
3337  MI.getOperand(2).isImm() &&
3338  isIntRegForSubInst(Src1Reg) && (MI.getOperand(2).getImm() == 0))
3339  return HexagonII::HCG_A;
3340  break;
3341  // The fact that .new form is used pretty much guarantees
3342  // that predicate register will match. Nevertheless,
3343  // there could be some false positives without additional
3344  // checking.
3345  case Hexagon::J2_jumptnew:
3346  case Hexagon::J2_jumpfnew:
3347  case Hexagon::J2_jumptnewpt:
3348  case Hexagon::J2_jumpfnewpt:
3349  Src1Reg = MI.getOperand(0).getReg();
3350  if (Hexagon::PredRegsRegClass.contains(Src1Reg) &&
3351  (Hexagon::P0 == Src1Reg || Hexagon::P1 == Src1Reg))
3352  return HexagonII::HCG_B;
3353  break;
3354  // Transfer and jump:
3355  // Rd=#U6 ; jump #r9:2
3356  // Rd=Rs ; jump #r9:2
3357  // Do not test for jump range here.
3358  case Hexagon::J2_jump:
3359  case Hexagon::RESTORE_DEALLOC_RET_JMP_V4:
3360  case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC:
3361  return HexagonII::HCG_C;
3362  }
3363 
3364  return HexagonII::HCG_None;
3365 }
3366 
3367 // Returns -1 when there is no opcode found.
3369  const MachineInstr &GB) const {
3372  if ((GA.getOpcode() != Hexagon::C2_cmpeqi) ||
3373  (GB.getOpcode() != Hexagon::J2_jumptnew))
3374  return -1u;
3375  unsigned DestReg = GA.getOperand(0).getReg();
3376  if (!GB.readsRegister(DestReg))
3377  return -1u;
3378  if (DestReg != Hexagon::P0 && DestReg != Hexagon::P1)
3379  return -1u;
3380  // The value compared against must be either u5 or -1.
3381  const MachineOperand &CmpOp = GA.getOperand(2);
3382  if (!CmpOp.isImm())
3383  return -1u;
3384  int V = CmpOp.getImm();
3385  if (V == -1)
3386  return DestReg == Hexagon::P0 ? Hexagon::J4_cmpeqn1_tp0_jump_nt
3387  : Hexagon::J4_cmpeqn1_tp1_jump_nt;
3388  if (!isUInt<5>(V))
3389  return -1u;
3390  return DestReg == Hexagon::P0 ? Hexagon::J4_cmpeqi_tp0_jump_nt
3391  : Hexagon::J4_cmpeqi_tp1_jump_nt;
3392 }
3393 
3394 int HexagonInstrInfo::getCondOpcode(int Opc, bool invertPredicate) const {
3395  enum Hexagon::PredSense inPredSense;
3396  inPredSense = invertPredicate ? Hexagon::PredSense_false :
3397  Hexagon::PredSense_true;
3398  int CondOpcode = Hexagon::getPredOpcode(Opc, inPredSense);
3399  if (CondOpcode >= 0) // Valid Conditional opcode/instruction
3400  return CondOpcode;
3401 
3402  llvm_unreachable("Unexpected predicable instruction");
3403 }
3404 
3405 // Return the cur value instruction for a given store.
3407  switch (MI.getOpcode()) {
3408  default: llvm_unreachable("Unknown .cur type");
3409  case Hexagon::V6_vL32b_pi:
3410  return Hexagon::V6_vL32b_cur_pi;
3411  case Hexagon::V6_vL32b_ai:
3412  return Hexagon::V6_vL32b_cur_ai;
3413  case Hexagon::V6_vL32b_nt_pi:
3414  return Hexagon::V6_vL32b_nt_cur_pi;
3415  case Hexagon::V6_vL32b_nt_ai:
3416  return Hexagon::V6_vL32b_nt_cur_ai;
3417  }
3418  return 0;
3419 }
3420 
3421 // Return the regular version of the .cur instruction.
3423  switch (MI.getOpcode()) {
3424  default: llvm_unreachable("Unknown .cur type");
3425  case Hexagon::V6_vL32b_cur_pi:
3426  return Hexagon::V6_vL32b_pi;
3427  case Hexagon::V6_vL32b_cur_ai:
3428  return Hexagon::V6_vL32b_ai;
3429  case Hexagon::V6_vL32b_nt_cur_pi:
3430  return Hexagon::V6_vL32b_nt_pi;
3431  case Hexagon::V6_vL32b_nt_cur_ai:
3432  return Hexagon::V6_vL32b_nt_ai;
3433  }
3434  return 0;
3435 }
3436 
3437 // The diagram below shows the steps involved in the conversion of a predicated
3438 // store instruction to its .new predicated new-value form.
3439 //
3440 // Note: It doesn't include conditional new-value stores as they can't be
3441 // converted to .new predicate.
3442 //
3443 // p.new NV store [ if(p0.new)memw(R0+#0)=R2.new ]
3444 // ^ ^
3445 // / \ (not OK. it will cause new-value store to be
3446 // / X conditional on p0.new while R2 producer is
3447 // / \ on p0)
3448 // / \.
3449 // p.new store p.old NV store
3450 // [if(p0.new)memw(R0+#0)=R2] [if(p0)memw(R0+#0)=R2.new]
3451 // ^ ^
3452 // \ /
3453 // \ /
3454 // \ /
3455 // p.old store
3456 // [if (p0)memw(R0+#0)=R2]
3457 //
3458 // The following set of instructions further explains the scenario where
3459 // conditional new-value store becomes invalid when promoted to .new predicate
3460 // form.
3461 //
3462 // { 1) if (p0) r0 = add(r1, r2)
3463 // 2) p0 = cmp.eq(r3, #0) }
3464 //
3465 // 3) if (p0) memb(r1+#0) = r0 --> this instruction can't be grouped with
3466 // the first two instructions because in instr 1, r0 is conditional on old value
3467 // of p0 but its use in instr 3 is conditional on p0 modified by instr 2 which
3468 // is not valid for new-value stores.
3469 // Predicated new value stores (i.e. if (p0) memw(..)=r0.new) are excluded
3470 // from the "Conditional Store" list. Because a predicated new value store
3471 // would NOT be promoted to a double dot new store. See diagram below:
3472 // This function returns yes for those stores that are predicated but not
3473 // yet promoted to predicate dot new instructions.
3474 //
3475 // +---------------------+
3476 // /-----| if (p0) memw(..)=r0 |---------\~
3477 // || +---------------------+ ||
3478 // promote || /\ /\ || promote
3479 // || /||\ /||\ ||
3480 // \||/ demote || \||/
3481 // \/ || || \/
3482 // +-------------------------+ || +-------------------------+
3483 // | if (p0.new) memw(..)=r0 | || | if (p0) memw(..)=r0.new |
3484 // +-------------------------+ || +-------------------------+
3485 // || || ||
3486 // || demote \||/
3487 // promote || \/ NOT possible
3488 // || || /\~
3489 // \||/ || /||\~
3490 // \/ || ||
3491 // +-----------------------------+
3492 // | if (p0.new) memw(..)=r0.new |
3493 // +-----------------------------+
3494 // Double Dot New Store
3495 //
3496 // Returns the most basic instruction for the .new predicated instructions and
3497 // new-value stores.
3498 // For example, all of the following instructions will be converted back to the
3499 // same instruction:
3500 // 1) if (p0.new) memw(R0+#0) = R1.new --->
3501 // 2) if (p0) memw(R0+#0)= R1.new -------> if (p0) memw(R0+#0) = R1
3502 // 3) if (p0.new) memw(R0+#0) = R1 --->
3503 //
3504 // To understand the translation of instruction 1 to its original form, consider
3505 // a packet with 3 instructions.
3506 // { p0 = cmp.eq(R0,R1)
3507 // if (p0.new) R2 = add(R3, R4)
3508 // R5 = add (R3, R1)
3509 // }
3510 // if (p0) memw(R5+#0) = R2 <--- trying to include it in the previous packet
3511 //
3512 // This instruction can be part of the previous packet only if both p0 and R2
3513 // are promoted to .new values. This promotion happens in steps, first
3514 // predicate register is promoted to .new and in the next iteration R2 is
3515 // promoted. Therefore, in case of dependence check failure (due to R5) during
3516 // next iteration, it should be converted back to its most basic form.
3517 
3518 // Return the new value instruction for a given store.
3520  int NVOpcode = Hexagon::getNewValueOpcode(MI.getOpcode());
3521  if (NVOpcode >= 0) // Valid new-value store instruction.
3522  return NVOpcode;
3523 
3524  switch (MI.getOpcode()) {
3525  default:
3526  report_fatal_error(std::string("Unknown .new type: ") +
3527  std::to_string(MI.getOpcode()));
3528  case Hexagon::S4_storerb_ur:
3529  return Hexagon::S4_storerbnew_ur;
3530 
3531  case Hexagon::S2_storerb_pci:
3532  return Hexagon::S2_storerb_pci;
3533 
3534  case Hexagon::S2_storeri_pci:
3535  return Hexagon::S2_storeri_pci;
3536 
3537  case Hexagon::S2_storerh_pci:
3538  return Hexagon::S2_storerh_pci;
3539 
3540  case Hexagon::S2_storerd_pci:
3541  return Hexagon::S2_storerd_pci;
3542 
3543  case Hexagon::S2_storerf_pci:
3544  return Hexagon::S2_storerf_pci;
3545 
3546  case Hexagon::V6_vS32b_ai:
3547  return Hexagon::V6_vS32b_new_ai;
3548 
3549  case Hexagon::V6_vS32b_pi:
3550  return Hexagon::V6_vS32b_new_pi;
3551  }
3552  return 0;
3553 }
3554 
3555 // Returns the opcode to use when converting MI, which is a conditional jump,
3556 // into a conditional instruction which uses the .new value of the predicate.
3557 // We also use branch probabilities to add a hint to the jump.
3558 // If MBPI is null, all edges will be treated as equally likely for the
3559 // purposes of establishing a predication hint.
3561  const MachineBranchProbabilityInfo *MBPI) const {
3562  // We assume that block can have at most two successors.
3563  const MachineBasicBlock *Src = MI.getParent();
3564  const MachineOperand &BrTarget = MI.getOperand(1);
3565  bool Taken = false;
3566  const BranchProbability OneHalf(1, 2);
3567 
3568  auto getEdgeProbability = [MBPI] (const MachineBasicBlock *Src,
3569  const MachineBasicBlock *Dst) {
3570  if (MBPI)
3571  return MBPI->getEdgeProbability(Src, Dst);
3572  return BranchProbability(1, Src->succ_size());
3573  };
3574 
3575  if (BrTarget.isMBB()) {
3576  const MachineBasicBlock *Dst = BrTarget.getMBB();
3577  Taken = getEdgeProbability(Src, Dst) >= OneHalf;
3578  } else {
3579  // The branch target is not a basic block (most likely a function).
3580  // Since BPI only gives probabilities for targets that are basic blocks,
3581  // try to identify another target of this branch (potentially a fall-
3582  // -through) and check the probability of that target.
3583  //
3584  // The only handled branch combinations are:
3585  // - one conditional branch,
3586  // - one conditional branch followed by one unconditional branch.
3587  // Otherwise, assume not-taken.
3589  const MachineBasicBlock &B = *MI.getParent();
3590  bool SawCond = false, Bad = false;
3591  for (const MachineInstr &I : B) {
3592  if (!I.isBranch())
3593  continue;
3594  if (I.isConditionalBranch()) {
3595  SawCond = true;
3596  if (&I != &MI) {
3597  Bad = true;
3598  break;
3599  }
3600  }
3601  if (I.isUnconditionalBranch() && !SawCond) {
3602  Bad = true;
3603  break;
3604  }
3605  }
3606  if (!Bad) {
3608  MachineBasicBlock::const_instr_iterator NextIt = std::next(It);
3609  if (NextIt == B.instr_end()) {
3610  // If this branch is the last, look for the fall-through block.
3611  for (const MachineBasicBlock *SB : B.successors()) {
3612  if (!B.isLayoutSuccessor(SB))
3613  continue;
3614  Taken = getEdgeProbability(Src, SB) < OneHalf;
3615  break;
3616  }
3617  } else {
3618  assert(NextIt->isUnconditionalBranch());
3619  // Find the first MBB operand and assume it's the target.
3620  const MachineBasicBlock *BT = nullptr;
3621  for (const MachineOperand &Op : NextIt->operands()) {
3622  if (!Op.isMBB())
3623  continue;
3624  BT = Op.getMBB();
3625  break;
3626  }
3627  Taken = BT && getEdgeProbability(Src, BT) < OneHalf;
3628  }
3629  } // if (!Bad)
3630  }
3631 
3632  // The Taken flag should be set to something reasonable by this point.
3633 
3634  switch (MI.getOpcode()) {
3635  case Hexagon::J2_jumpt:
3636  return Taken ? Hexagon::J2_jumptnewpt : Hexagon::J2_jumptnew;
3637  case Hexagon::J2_jumpf:
3638  return Taken ? Hexagon::J2_jumpfnewpt : Hexagon::J2_jumpfnew;
3639 
3640  default:
3641  llvm_unreachable("Unexpected jump instruction.");
3642  }
3643 }
3644 
3645 // Return .new predicate version for an instruction.
3647  const MachineBranchProbabilityInfo *MBPI) const {
3648  switch (MI.getOpcode()) {
3649  // Condtional Jumps
3650  case Hexagon::J2_jumpt:
3651  case Hexagon::J2_jumpf:
3652  return getDotNewPredJumpOp(MI, MBPI);
3653  }
3654 
3655  int NewOpcode = Hexagon::getPredNewOpcode(MI.getOpcode());
3656  if (NewOpcode >= 0)
3657  return NewOpcode;
3658  return 0;
3659 }
3660 
3662  int NewOp = MI.getOpcode();
3663  if (isPredicated(NewOp) && isPredicatedNew(NewOp)) { // Get predicate old form
3664  NewOp = Hexagon::getPredOldOpcode(NewOp);
3665  // All Hexagon architectures have prediction bits on dot-new branches,
3666  // but only Hexagon V60+ has prediction bits on dot-old ones. Make sure
3667  // to pick the right opcode when converting back to dot-old.
3668  if (!Subtarget.getFeatureBits()[Hexagon::ArchV60]) {
3669  switch (NewOp) {
3670  case Hexagon::J2_jumptpt:
3671  NewOp = Hexagon::J2_jumpt;
3672  break;
3673  case Hexagon::J2_jumpfpt:
3674  NewOp = Hexagon::J2_jumpf;
3675  break;
3676  case Hexagon::J2_jumprtpt:
3677  NewOp = Hexagon::J2_jumprt;
3678  break;
3679  case Hexagon::J2_jumprfpt:
3680  NewOp = Hexagon::J2_jumprf;
3681  break;
3682  }
3683  }
3684  assert(NewOp >= 0 &&
3685  "Couldn't change predicate new instruction to its old form.");
3686  }
3687 
3688  if (isNewValueStore(NewOp)) { // Convert into non-new-value format
3689  NewOp = Hexagon::getNonNVStore(NewOp);
3690  assert(NewOp >= 0 && "Couldn't change new-value store to its old form.");
3691  }
3692 
3693  if (Subtarget.hasV60Ops())
3694  return NewOp;
3695 
3696  // Subtargets prior to V60 didn't support 'taken' forms of predicated jumps.
3697  switch (NewOp) {
3698  case Hexagon::J2_jumpfpt:
3699  return Hexagon::J2_jumpf;
3700  case Hexagon::J2_jumptpt:
3701  return Hexagon::J2_jumpt;
3702  case Hexagon::J2_jumprfpt:
3703  return Hexagon::J2_jumprf;
3704  case Hexagon::J2_jumprtpt:
3705  return Hexagon::J2_jumprt;
3706  }
3707  return NewOp;
3708 }
3709 
3710 // See if instruction could potentially be a duplex candidate.
3711 // If so, return its group. Zero otherwise.
3713  const MachineInstr &MI) const {
3714  unsigned DstReg, SrcReg, Src1Reg, Src2Reg;
3715  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
3716 
3717  switch (MI.getOpcode()) {
3718  default:
3719  return HexagonII::HSIG_None;
3720  //
3721  // Group L1:
3722  //
3723  // Rd = memw(Rs+#u4:2)
3724  // Rd = memub(Rs+#u4:0)
3725  case Hexagon::L2_loadri_io:
3726  DstReg = MI.getOperand(0).getReg();
3727  SrcReg = MI.getOperand(1).getReg();
3728  // Special case this one from Group L2.
3729  // Rd = memw(r29+#u5:2)
3730  if (isIntRegForSubInst(DstReg)) {
3731  if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
3732  HRI.getStackRegister() == SrcReg &&
3733  MI.getOperand(2).isImm() &&
3734  isShiftedUInt<5,2>(MI.getOperand(2).getImm()))
3735  return HexagonII::HSIG_L2;
3736  // Rd = memw(Rs+#u4:2)
3737  if (isIntRegForSubInst(SrcReg) &&
3738  (MI.getOperand(2).isImm() &&
3739  isShiftedUInt<4,2>(MI.getOperand(2).getImm())))
3740  return HexagonII::HSIG_L1;
3741  }
3742  break;
3743  case Hexagon::L2_loadrub_io:
3744  // Rd = memub(Rs+#u4:0)
3745  DstReg = MI.getOperand(0).getReg();
3746  SrcReg = MI.getOperand(1).getReg();
3747  if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg) &&
3748  MI.getOperand(2).isImm() && isUInt<4>(MI.getOperand(2).getImm()))
3749  return HexagonII::HSIG_L1;
3750  break;
3751  //
3752  // Group L2:
3753  //
3754  // Rd = memh/memuh(Rs+#u3:1)
3755  // Rd = memb(Rs+#u3:0)
3756  // Rd = memw(r29+#u5:2) - Handled above.
3757  // Rdd = memd(r29+#u5:3)
3758  // deallocframe
3759  // [if ([!]p0[.new])] dealloc_return
3760  // [if ([!]p0[.new])] jumpr r31
3761  case Hexagon::L2_loadrh_io:
3762  case Hexagon::L2_loadruh_io:
3763  // Rd = memh/memuh(Rs+#u3:1)
3764  DstReg = MI.getOperand(0).getReg();
3765  SrcReg = MI.getOperand(1).getReg();
3766  if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg) &&
3767  MI.getOperand(2).isImm() &&
3768  isShiftedUInt<3,1>(MI.getOperand(2).getImm()))
3769  return HexagonII::HSIG_L2;
3770  break;
3771  case Hexagon::L2_loadrb_io:
3772  // Rd = memb(Rs+#u3:0)
3773  DstReg = MI.getOperand(0).getReg();
3774  SrcReg = MI.getOperand(1).getReg();
3775  if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg) &&
3776  MI.getOperand(2).isImm() &&
3777  isUInt<3>(MI.getOperand(2).getImm()))
3778  return HexagonII::HSIG_L2;
3779  break;
3780  case Hexagon::L2_loadrd_io:
3781  // Rdd = memd(r29+#u5:3)
3782  DstReg = MI.getOperand(0).getReg();
3783  SrcReg = MI.getOperand(1).getReg();
3784  if (isDblRegForSubInst(DstReg, HRI) &&
3785  Hexagon::IntRegsRegClass.contains(SrcReg) &&
3786  HRI.getStackRegister() == SrcReg &&
3787  MI.getOperand(2).isImm() &&
3788  isShiftedUInt<5,3>(MI.getOperand(2).getImm()))
3789  return HexagonII::HSIG_L2;
3790  break;
3791  // dealloc_return is not documented in Hexagon Manual, but marked
3792  // with A_SUBINSN attribute in iset_v4classic.py.
3793  case Hexagon::RESTORE_DEALLOC_RET_JMP_V4:
3794  case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC:
3795  case Hexagon::L4_return:
3796  case Hexagon::L2_deallocframe:
3797  return HexagonII::HSIG_L2;
3798  case Hexagon::EH_RETURN_JMPR:
3799  case Hexagon::PS_jmpret:
3800  case Hexagon::SL2_jumpr31:
3801  // jumpr r31
3802  // Actual form JMPR implicit-def %pc, implicit %r31, implicit internal %r0
3803  DstReg = MI.getOperand(0).getReg();
3804  if (Hexagon::IntRegsRegClass.contains(DstReg) && (Hexagon::R31 == DstReg))
3805  return HexagonII::HSIG_L2;
3806  break;
3807  case Hexagon::PS_jmprett:
3808  case Hexagon::PS_jmpretf:
3809  case Hexagon::PS_jmprettnewpt:
3810  case Hexagon::PS_jmpretfnewpt:
3811  case Hexagon::PS_jmprettnew:
3812  case Hexagon::PS_jmpretfnew:
3813  case Hexagon::SL2_jumpr31_t:
3814  case Hexagon::SL2_jumpr31_f:
3815  case Hexagon::SL2_jumpr31_tnew:
3816  DstReg = MI.getOperand(1).getReg();
3817  SrcReg = MI.getOperand(0).getReg();
3818  // [if ([!]p0[.new])] jumpr r31
3819  if ((Hexagon::PredRegsRegClass.contains(SrcReg) &&
3820  (Hexagon::P0 == SrcReg)) &&
3821  (Hexagon::IntRegsRegClass.contains(DstReg) && (Hexagon::R31 == DstReg)))
3822  return HexagonII::HSIG_L2;
3823  break;
3824  case Hexagon::L4_return_t:
3825  case Hexagon::L4_return_f:
3826  case Hexagon::L4_return_tnew_pnt:
3827  case Hexagon::L4_return_fnew_pnt:
3828  case Hexagon::L4_return_tnew_pt:
3829  case Hexagon::L4_return_fnew_pt:
3830  // [if ([!]p0[.new])] dealloc_return
3831  SrcReg = MI.getOperand(0).getReg();
3832  if (Hexagon::PredRegsRegClass.contains(SrcReg) && (Hexagon::P0 == SrcReg))
3833  return HexagonII::HSIG_L2;
3834  break;
3835  //
3836  // Group S1:
3837  //
3838  // memw(Rs+#u4:2) = Rt
3839  // memb(Rs+#u4:0) = Rt
3840  case Hexagon::S2_storeri_io:
3841  // Special case this one from Group S2.
3842  // memw(r29+#u5:2) = Rt
3843  Src1Reg = MI.getOperand(0).getReg();
3844  Src2Reg = MI.getOperand(2).getReg();
3845  if (Hexagon::IntRegsRegClass.contains(Src1Reg) &&
3846  isIntRegForSubInst(Src2Reg) &&
3847  HRI.getStackRegister() == Src1Reg && MI.getOperand(1).isImm() &&
3848  isShiftedUInt<5,2>(MI.getOperand(1).getImm()))
3849  return HexagonII::HSIG_S2;
3850  // memw(Rs+#u4:2) = Rt
3851  if (isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg) &&
3852  MI.getOperand(1).isImm() &&
3853  isShiftedUInt<4,2>(MI.getOperand(1).getImm()))
3854  return HexagonII::HSIG_S1;
3855  break;
3856  case Hexagon::S2_storerb_io:
3857  // memb(Rs+#u4:0) = Rt
3858  Src1Reg = MI.getOperand(0).getReg();
3859  Src2Reg = MI.getOperand(2).getReg();
3860  if (isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg) &&
3861  MI.getOperand(1).isImm() && isUInt<4>(MI.getOperand(1).getImm()))
3862  return HexagonII::HSIG_S1;
3863  break;
3864  //
3865  // Group S2:
3866  //
3867  // memh(Rs+#u3:1) = Rt
3868  // memw(r29+#u5:2) = Rt
3869  // memd(r29+#s6:3) = Rtt
3870  // memw(Rs+#u4:2) = #U1
3871  // memb(Rs+#u4) = #U1
3872  // allocframe(#u5:3)
3873  case Hexagon::S2_storerh_io:
3874  // memh(Rs+#u3:1) = Rt
3875  Src1Reg = MI.getOperand(0).getReg();
3876  Src2Reg = MI.getOperand(2).getReg();
3877  if (isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg) &&
3878  MI.getOperand(1).isImm() &&
3879  isShiftedUInt<3,1>(MI.getOperand(1).getImm()))
3880  return HexagonII::HSIG_S1;
3881  break;
3882  case Hexagon::S2_storerd_io:
3883  // memd(r29+#s6:3) = Rtt
3884  Src1Reg = MI.getOperand(0).getReg();
3885  Src2Reg = MI.getOperand(2).getReg();
3886  if (isDblRegForSubInst(Src2Reg, HRI) &&
3887  Hexagon::IntRegsRegClass.contains(Src1Reg) &&
3888  HRI.getStackRegister() == Src1Reg && MI.getOperand(1).isImm() &&
3889  isShiftedInt<6,3>(MI.getOperand(1).getImm()))
3890  return HexagonII::HSIG_S2;
3891  break;
3892  case Hexagon::S4_storeiri_io:
3893  // memw(Rs+#u4:2) = #U1
3894  Src1Reg = MI.getOperand(0).getReg();
3895  if (isIntRegForSubInst(Src1Reg) && MI.getOperand(1).isImm() &&
3896  isShiftedUInt<4,2>(MI.getOperand(1).getImm()) &&
3897  MI.getOperand(2).isImm() && isUInt<1>(MI.getOperand(2).getImm()))
3898  return HexagonII::HSIG_S2;
3899  break;
3900  case Hexagon::S4_storeirb_io:
3901  // memb(Rs+#u4) = #U1
3902  Src1Reg = MI.getOperand(0).getReg();
3903  if (isIntRegForSubInst(Src1Reg) &&
3904  MI.getOperand(1).isImm() && isUInt<4>(MI.getOperand(1).getImm()) &&
3905  MI.getOperand(2).isImm() && isUInt<1>(MI.getOperand(2).getImm()))
3906  return HexagonII::HSIG_S2;
3907  break;
3908  case Hexagon::S2_allocframe:
3909  if (MI.getOperand(2).isImm() &&
3910  isShiftedUInt<5,3>(MI.getOperand(2).getImm()))
3911  return HexagonII::HSIG_S1;
3912  break;
3913  //
3914  // Group A:
3915  //
3916  // Rx = add(Rx,#s7)
3917  // Rd = Rs
3918  // Rd = #u6
3919  // Rd = #-1
3920  // if ([!]P0[.new]) Rd = #0
3921  // Rd = add(r29,#u6:2)
3922  // Rx = add(Rx,Rs)
3923  // P0 = cmp.eq(Rs,#u2)
3924  // Rdd = combine(#0,Rs)
3925  // Rdd = combine(Rs,#0)
3926  // Rdd = combine(#u2,#U2)
3927  // Rd = add(Rs,#1)
3928  // Rd = add(Rs,#-1)
3929  // Rd = sxth/sxtb/zxtb/zxth(Rs)
3930  // Rd = and(Rs,#1)
3931  case Hexagon::A2_addi:
3932  DstReg = MI.getOperand(0).getReg();
3933  SrcReg = MI.getOperand(1).getReg();
3934  if (isIntRegForSubInst(DstReg)) {
3935  // Rd = add(r29,#u6:2)
3936  if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
3937  HRI.getStackRegister() == SrcReg && MI.getOperand(2).isImm() &&
3938  isShiftedUInt<6,2>(MI.getOperand(2).getImm()))
3939  return HexagonII::HSIG_A;
3940  // Rx = add(Rx,#s7)
3941  if ((DstReg == SrcReg) && MI.getOperand(2).isImm() &&
3942  isInt<7>(MI.getOperand(2).getImm()))
3943  return HexagonII::HSIG_A;
3944  // Rd = add(Rs,#1)
3945  // Rd = add(Rs,#-1)
3946  if (isIntRegForSubInst(SrcReg) && MI.getOperand(2).isImm() &&
3947  ((MI.getOperand(2).getImm() == 1) ||
3948  (MI.getOperand(2).getImm() == -1)))
3949  return HexagonII::HSIG_A;
3950  }
3951  break;
3952  case Hexagon::A2_add:
3953  // Rx = add(Rx,Rs)
3954  DstReg = MI.getOperand(0).getReg();
3955  Src1Reg = MI.getOperand(1).getReg();
3956  Src2Reg = MI.getOperand(2).getReg();
3957  if (isIntRegForSubInst(DstReg) && (DstReg == Src1Reg) &&
3958  isIntRegForSubInst(Src2Reg))
3959  return HexagonII::HSIG_A;
3960  break;
3961  case Hexagon::A2_andir:
3962  // Same as zxtb.
3963  // Rd16=and(Rs16,#255)
3964  // Rd16=and(Rs16,#1)
3965  DstReg = MI.getOperand(0).getReg();
3966  SrcReg = MI.getOperand(1).getReg();
3967  if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg) &&
3968  MI.getOperand(2).isImm() &&
3969  ((MI.getOperand(2).getImm() == 1) ||
3970  (MI.getOperand(2).getImm() == 255)))
3971  return HexagonII::HSIG_A;
3972  break;
3973  case Hexagon::A2_tfr:
3974  // Rd = Rs
3975  DstReg = MI.getOperand(0).getReg();
3976  SrcReg = MI.getOperand(1).getReg();
3977  if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg))
3978  return HexagonII::HSIG_A;
3979  break;
3980  case Hexagon::A2_tfrsi:
3981  // Rd = #u6
3982  // Do not test for #u6 size since the const is getting extended
3983  // regardless and compound could be formed.
3984  // Rd = #-1
3985  DstReg = MI.getOperand(0).getReg();
3986  if (isIntRegForSubInst(DstReg))
3987  return HexagonII::HSIG_A;
3988  break;
3989  case Hexagon::C2_cmoveit:
3990  case Hexagon::C2_cmovenewit:
3991  case Hexagon::C2_cmoveif:
3992  case Hexagon::C2_cmovenewif:
3993  // if ([!]P0[.new]) Rd = #0
3994  // Actual form:
3995  // %r16 = C2_cmovenewit internal %p0, 0, implicit undef %r16;
3996  DstReg = MI.getOperand(0).getReg();
3997  SrcReg = MI.getOperand(1).getReg();
3998  if (isIntRegForSubInst(DstReg) &&
3999  Hexagon::PredRegsRegClass.contains(SrcReg) && Hexagon::P0 == SrcReg &&
4000  MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0)
4001  return HexagonII::HSIG_A;
4002  break;
4003  case Hexagon::C2_cmpeqi:
4004  // P0 = cmp.eq(Rs,#u2)
4005  DstReg = MI.getOperand(0).getReg();
4006  SrcReg = MI.getOperand(1).getReg();
4007  if (Hexagon::PredRegsRegClass.contains(DstReg) &&
4008  Hexagon::P0 == DstReg && isIntRegForSubInst(SrcReg) &&
4009  MI.getOperand(2).isImm() && isUInt<2>(MI.getOperand(2).getImm()))
4010  return HexagonII::HSIG_A;
4011  break;
4012  case Hexagon::A2_combineii:
4013  case Hexagon::A4_combineii:
4014  // Rdd = combine(#u2,#U2)
4015  DstReg = MI.getOperand(0).getReg();
4016  if (isDblRegForSubInst(DstReg, HRI) &&
4017  ((MI.getOperand(1).isImm() && isUInt<2>(MI.getOperand(1).getImm())) ||
4018  (MI.getOperand(1).isGlobal() &&
4019  isUInt<2>(MI.getOperand(1).getOffset()))) &&
4020  ((MI.getOperand(2).isImm() && isUInt<2>(MI.getOperand(2).getImm())) ||
4021  (MI.getOperand(2).isGlobal() &&
4022  isUInt<2>(MI.getOperand(2).getOffset()))))
4023  return HexagonII::HSIG_A;
4024  break;
4025  case Hexagon::A4_combineri:
4026  // Rdd = combine(Rs,#0)
4027  DstReg = MI.getOperand(0).getReg();
4028  SrcReg = MI.getOperand(1).getReg();
4029  if (isDblRegForSubInst(DstReg, HRI) && isIntRegForSubInst(SrcReg) &&
4030  ((MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0) ||
4031  (MI.getOperand(2).isGlobal() && MI.getOperand(2).getOffset() == 0)))
4032  return HexagonII::HSIG_A;
4033  break;
4034  case Hexagon::A4_combineir:
4035  // Rdd = combine(#0,Rs)
4036  DstReg = MI.getOperand(0).getReg();
4037  SrcReg = MI.getOperand(2).getReg();
4038  if (isDblRegForSubInst(DstReg, HRI) && isIntRegForSubInst(SrcReg) &&
4039  ((MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == 0) ||
4040  (MI.getOperand(1).isGlobal() && MI.getOperand(1).getOffset() == 0)))
4041  return HexagonII::HSIG_A;
4042  break;
4043  case Hexagon::A2_sxtb:
4044  case Hexagon::A2_sxth:
4045  case Hexagon::A2_zxtb:
4046  case Hexagon::A2_zxth:
4047  // Rd = sxth/sxtb/zxtb/zxth(Rs)
4048  DstReg = MI.getOperand(0).getReg();
4049  SrcReg = MI.getOperand(1).getReg();
4050  if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg))
4051  return HexagonII::HSIG_A;
4052  break;
4053  }
4054 
4055  return HexagonII::HSIG_None;
4056 }
4057 
4059  return Hexagon::getRealHWInstr(MI.getOpcode(), Hexagon::InstrType_Real);
4060 }
4061 
4063  const InstrItineraryData *ItinData, const MachineInstr &MI) const {
4064  // Default to one cycle for no itinerary. However, an "empty" itinerary may
4065  // still have a MinLatency property, which getStageLatency checks.
4066  if (!ItinData)
4067  return getInstrLatency(ItinData, MI);
4068 
4069  if (MI.isTransient())
4070  return 0;
4071  return ItinData->getStageLatency(MI.getDesc().getSchedClass());
4072 }
4073 
4074 /// getOperandLatency - Compute and return the use operand latency of a given
4075 /// pair of def and use.
4076 /// In most cases, the static scheduling itinerary was enough to determine the
4077 /// operand latency. But it may not be possible for instructions with variable
4078 /// number of defs / uses.
4079 ///
4080 /// This is a raw interface to the itinerary that may be directly overriden by
4081 /// a target. Use computeOperandLatency to get the best estimate of latency.
4083  const MachineInstr &DefMI,
4084  unsigned DefIdx,
4085  const MachineInstr &UseMI,
4086  unsigned UseIdx) const {
4087  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
4088 
4089  // Get DefIdx and UseIdx for super registers.
4090  const MachineOperand &DefMO = DefMI.getOperand(DefIdx);
4091 
4092  if (DefMO.isReg() && HRI.isPhysicalRegister(DefMO.getReg())) {
4093  if (DefMO.isImplicit()) {
4094  for (MCSuperRegIterator SR(DefMO.getReg(), &HRI); SR.isValid(); ++SR) {
4095  int Idx = DefMI.findRegisterDefOperandIdx(*SR, false, false, &HRI);
4096  if (Idx != -1) {
4097  DefIdx = Idx;
4098  break;
4099  }
4100  }
4101  }
4102 
4103  const MachineOperand &UseMO = UseMI.getOperand(UseIdx);
4104  if (UseMO.isImplicit()) {
4105  for (MCSuperRegIterator SR(UseMO.getReg(), &HRI); SR.isValid(); ++SR) {
4106  int Idx = UseMI.findRegisterUseOperandIdx(*SR, false, &HRI);
4107  if (Idx != -1) {
4108  UseIdx = Idx;
4109  break;
4110  }
4111  }
4112  }
4113  }
4114 
4115  int Latency = TargetInstrInfo::getOperandLatency(ItinData, DefMI, DefIdx,
4116  UseMI, UseIdx);
4117  if (!Latency)
4118  // We should never have 0 cycle latency between two instructions unless
4119  // they can be packetized together. However, this decision can't be made
4120  // here.
4121  Latency = 1;
4122  return Latency;
4123 }
4124 
4125 // inverts the predication logic.
4126 // p -> NotP
4127 // NotP -> P
4129  SmallVectorImpl<MachineOperand> &Cond) const {
4130  if (Cond.empty())
4131  return false;
4132  unsigned Opc = getInvertedPredicatedOpcode(Cond[0].getImm());
4133  Cond[0].setImm(Opc);
4134  return true;
4135 }
4136 
4137 unsigned HexagonInstrInfo::getInvertedPredicatedOpcode(const int Opc) const {
4138  int InvPredOpcode;
4139  InvPredOpcode = isPredicatedTrue(Opc) ? Hexagon::getFalsePredOpcode(Opc)
4140  : Hexagon::getTruePredOpcode(Opc);
4141  if (InvPredOpcode >= 0) // Valid instruction with the inverted predicate.
4142  return InvPredOpcode;
4143 
4144  llvm_unreachable("Unexpected predicated instruction");
4145 }
4146 
4147 // Returns the max value that doesn't need to be extended.
4149  const uint64_t F = MI.getDesc().TSFlags;
4150  unsigned isSigned = (F >> HexagonII::ExtentSignedPos)
4152  unsigned bits = (F >> HexagonII::ExtentBitsPos)
4154 
4155  if (isSigned) // if value is signed
4156  return ~(-1U << (bits - 1));
4157  else
4158  return ~(-1U << bits);
4159 }
4160 
4161 
4163  switch (MI.getOpcode()) {
4164  case Hexagon::L2_loadrbgp:
4165  case Hexagon::L2_loadrdgp:
4166  case Hexagon::L2_loadrhgp:
4167  case Hexagon::L2_loadrigp:
4168  case Hexagon::L2_loadrubgp:
4169  case Hexagon::L2_loadruhgp:
4170  case Hexagon::S2_storerbgp:
4171  case Hexagon::S2_storerbnewgp:
4172  case Hexagon::S2_storerhgp:
4173  case Hexagon::S2_storerhnewgp:
4174  case Hexagon::S2_storerigp:
4175  case Hexagon::S2_storerinewgp:
4176  case Hexagon::S2_storerdgp:
4177  case Hexagon::S2_storerfgp:
4178  return true;
4179  }
4180  const uint64_t F = MI.getDesc().TSFlags;
4181  unsigned addrMode =
4183  // Disallow any base+offset instruction. The assembler does not yet reorder
4184  // based up any zero offset instruction.
4185  return (addrMode == HexagonII::BaseRegOffset ||
4186  addrMode == HexagonII::BaseImmOffset ||
4187  addrMode == HexagonII::BaseLongOffset);
4188 }
4189 
4191  using namespace HexagonII;
4192 
4193  const uint64_t F = MI.getDesc().TSFlags;
4194  unsigned S = (F >> MemAccessSizePos) & MemAccesSizeMask;
4196  if (Size != 0)
4197  return Size;
4198 
4199  // Handle vector access sizes.
4200  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
4201  switch (S) {
4203  return HRI.getSpillSize(Hexagon::HvxVRRegClass);
4204  default:
4205  llvm_unreachable("Unexpected instruction");
4206  }
4207 }
4208 
4209 // Returns the min value that doesn't need to be extended.
4211  const uint64_t F = MI.getDesc().TSFlags;
4212  unsigned isSigned = (F >> HexagonII::ExtentSignedPos)
4214  unsigned bits = (F >> HexagonII::ExtentBitsPos)
4216 
4217  if (isSigned) // if value is signed
4218  return -1U << (bits - 1);
4219  else
4220  return 0;
4221 }
4222 
4223 // Returns opcode of the non-extended equivalent instruction.
4225  // Check if the instruction has a register form that uses register in place
4226  // of the extended operand, if so return that as the non-extended form.
4227  short NonExtOpcode = Hexagon::getRegForm(MI.getOpcode());
4228  if (NonExtOpcode >= 0)
4229  return NonExtOpcode;
4230 
4231  if (MI.getDesc().mayLoad() || MI.getDesc().mayStore()) {
4232  // Check addressing mode and retrieve non-ext equivalent instruction.
4233  switch (getAddrMode(MI)) {
4234  case HexagonII::Absolute:
4235  return Hexagon::changeAddrMode_abs_io(MI.getOpcode());
4237  return Hexagon::changeAddrMode_io_rr(MI.getOpcode());
4239  return Hexagon::changeAddrMode_ur_rr(MI.getOpcode());
4240 
4241  default:
4242  return -1;
4243  }
4244  }
4245  return -1;
4246 }
4247 
4249  unsigned &PredReg, unsigned &PredRegPos, unsigned &PredRegFlags) const {
4250  if (Cond.empty())
4251  return false;
4252  assert(Cond.size() == 2);
4253  if (isNewValueJump(Cond[0].getImm()) || Cond[1].isMBB()) {
4254  LLVM_DEBUG(dbgs() << "No predregs for new-value jumps/endloop");
4255  return false;
4256  }
4257  PredReg = Cond[1].getReg();
4258  PredRegPos = 1;
4259  // See IfConversion.cpp why we add RegState::Implicit | RegState::Undef
4260  PredRegFlags = 0;
4261  if (Cond[1].isImplicit())
4262  PredRegFlags = RegState::Implicit;
4263  if (Cond[1].isUndef())
4264  PredRegFlags |= RegState::Undef;
4265  return true;
4266 }
4267 
4269  return Hexagon::getRealHWInstr(MI.getOpcode(), Hexagon::InstrType_Pseudo);
4270 }
4271 
4273  return Hexagon::getRegForm(MI.getOpcode());
4274 }
4275 
4276 // Return the number of bytes required to encode the instruction.
4277 // Hexagon instructions are fixed length, 4 bytes, unless they
4278 // use a constant extender, which requires another 4 bytes.
4279 // For debug instructions and prolog labels, return 0.
4281  if (MI.isDebugInstr() || MI.isPosition())
4282  return 0;
4283 
4284  unsigned Size = MI.getDesc().getSize();
4285  if (!Size)
4286  // Assume the default insn size in case it cannot be determined
4287  // for whatever reason.
4288  Size = HEXAGON_INSTR_SIZE;
4289 
4290  if (isConstExtended(MI) || isExtended(MI))
4291  Size += HEXAGON_INSTR_SIZE;
4292 
4293  // Try and compute number of instructions in asm.
4295  const MachineBasicBlock &MBB = *MI.getParent();
4296  const MachineFunction *MF = MBB.getParent();
4297  const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
4298 
4299  // Count the number of register definitions to find the asm string.
4300  unsigned NumDefs = 0;
4301  for (; MI.getOperand(NumDefs).isReg() && MI.getOperand(NumDefs).isDef();
4302  ++NumDefs)
4303  assert(NumDefs != MI.getNumOperands()-2 && "No asm string?");
4304 
4305  assert(MI.getOperand(NumDefs).isSymbol() && "No asm string?");
4306  // Disassemble the AsmStr and approximate number of instructions.
4307  const char *AsmStr = MI.getOperand(NumDefs).getSymbolName();
4308  Size = getInlineAsmLength(AsmStr, *MAI);
4309  }
4310 
4311  return Size;
4312 }
4313 
4315  const uint64_t F = MI.getDesc().TSFlags;
4316  return (F >> HexagonII::TypePos) & HexagonII::TypeMask;
4317 }
4318 
4320  const InstrItineraryData &II = *Subtarget.getInstrItineraryData();
4321  const InstrStage &IS = *II.beginStage(MI.getDesc().getSchedClass());
4322 
4323  return IS.getUnits();
4324 }
4325 
4326 // Calculate size of the basic block without debug instructions.
4328  return nonDbgMICount(BB->instr_begin(), BB->instr_end());
4329 }
4330 
4332  MachineBasicBlock::const_iterator BundleHead) const {
4333  assert(BundleHead->isBundle() && "Not a bundle header");
4334  auto MII = BundleHead.getInstrIterator();
4335  // Skip the bundle header.
4336  return nonDbgMICount(++MII, getBundleEnd(BundleHead.getInstrIterator()));
4337 }
4338 
4339 /// immediateExtend - Changes the instruction in place to one using an immediate
4340 /// extender.
4342  assert((isExtendable(MI)||isConstExtended(MI)) &&
4343  "Instruction must be extendable");
4344  // Find which operand is extendable.
4345  short ExtOpNum = getCExtOpNum(MI);
4346  MachineOperand &MO = MI.getOperand(ExtOpNum);
4347  // This needs to be something we understand.
4348  assert((MO.isMBB() || MO.isImm()) &&
4349  "Branch with unknown extendable field type");
4350  // Mark given operand as extended.
4352 }
4353 
4355  MachineInstr &MI, MachineBasicBlock *NewTarget) const {
4356  LLVM_DEBUG(dbgs() << "\n[invertAndChangeJumpTarget] to "
4357  << printMBBReference(*NewTarget);
4358  MI.dump(););
4359  assert(MI.isBranch());
4360  unsigned NewOpcode = getInvertedPredicatedOpcode(MI.getOpcode());
4361  int TargetPos = MI.getNumOperands() - 1;
4362  // In general branch target is the last operand,
4363  // but some implicit defs added at the end might change it.
4364  while ((TargetPos > -1) && !MI.getOperand(TargetPos).isMBB())
4365  --TargetPos;
4366  assert((TargetPos >= 0) && MI.getOperand(TargetPos).isMBB());
4367  MI.getOperand(TargetPos).setMBB(NewTarget);
4369  NewOpcode = reversePrediction(NewOpcode);
4370  }
4371  MI.setDesc(get(NewOpcode));
4372  return true;
4373 }
4374 
4376  /* +++ The code below is used to generate complete set of Hexagon Insn +++ */
4378  MachineBasicBlock &B = *A;
4380  DebugLoc DL = I->getDebugLoc();
4381  MachineInstr *NewMI;
4382 
4383  for (unsigned insn = TargetOpcode::GENERIC_OP_END+1;
4384  insn < Hexagon::INSTRUCTION_LIST_END; ++insn) {
4385  NewMI = BuildMI(B, I, DL, get(insn));
4386  LLVM_DEBUG(dbgs() << "\n"
4387  << getName(NewMI->getOpcode())
4388  << " Class: " << NewMI->getDesc().getSchedClass());
4389  NewMI->eraseFromParent();
4390  }
4391  /* --- The code above is used to generate complete set of Hexagon Insn --- */
4392 }
4393 
4394 // inverts the predication logic.
4395 // p -> NotP
4396 // NotP -> P
4398  LLVM_DEBUG(dbgs() << "\nTrying to reverse pred. sense of:"; MI.dump());
4400  return true;
4401 }
4402 
4403 // Reverse the branch prediction.
4404 unsigned HexagonInstrInfo::reversePrediction(unsigned Opcode) const {
4405  int PredRevOpcode = -1;
4406  if (isPredictedTaken(Opcode))
4407  PredRevOpcode = Hexagon::notTakenBranchPrediction(Opcode);
4408  else
4409  PredRevOpcode = Hexagon::takenBranchPrediction(Opcode);
4410  assert(PredRevOpcode > 0);
4411  return PredRevOpcode;
4412 }
4413 
4414 // TODO: Add more rigorous validation.
4416  const {
4417  return Cond.empty() || (Cond[0].isImm() && (Cond.size() != 1));
4418 }
4419 
4420 void HexagonInstrInfo::
4422  assert(MIB->isBundle());
4423  MachineOperand &Operand = MIB->getOperand(0);
4424  if (Operand.isImm())
4425  Operand.setImm(Operand.getImm() | memShufDisabledMask);
4426  else
4427  MIB->addOperand(MachineOperand::CreateImm(memShufDisabledMask));
4428 }
4429 
4431  assert(MIB.isBundle());
4432  const MachineOperand &Operand = MIB.getOperand(0);
4433  return (Operand.isImm() && (Operand.getImm() & memShufDisabledMask) != 0);
4434 }
4435 
4436 // Addressing mode relations.
4438  return Opc >= 0 ? Hexagon::changeAddrMode_abs_io(Opc) : Opc;
4439 }
4440 
4442  return Opc >= 0 ? Hexagon::changeAddrMode_io_abs(Opc) : Opc;
4443 }
4444 
4446  return Opc >= 0 ? Hexagon::changeAddrMode_io_pi(Opc) : Opc;
4447 }
4448 
4450  return Opc >= 0 ? Hexagon::changeAddrMode_io_rr(Opc) : Opc;
4451 }
4452 
4454  return Opc >= 0 ? Hexagon::changeAddrMode_pi_io(Opc) : Opc;
4455 }
4456 
4458  return Opc >= 0 ? Hexagon::changeAddrMode_rr_io(Opc) : Opc;
4459 }
4460 
4462  return Opc >= 0 ? Hexagon::changeAddrMode_rr_ur(Opc) : Opc;
4463 }
4464 
4466  return Opc >= 0 ? Hexagon::changeAddrMode_ur_rr(Opc) : Opc;
4467 }
static bool isReg(const MCInst &MI, unsigned OpNo)
unsigned getTargetFlags() const
bool isRegMask() const
isRegMask - Tests if this is a MO_RegisterMask operand.
short getNonExtOpcode(const MachineInstr &MI) const
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
Return an array that contains the direct target flag values and their names.
bool isVecALU(const MachineInstr &MI) const
const MachineInstrBuilder & add(const MachineOperand &MO) const
bool DefinesPredicate(MachineInstr &MI, std::vector< MachineOperand > &Pred) const override
If the specified instruction defines any predicate or condition code register(s) used for predication...
This class is the base class for the comparison instructions.
Definition: InstrTypes.h:699
short changeAddrMode_rr_io(short Opc) const
static bool isConstant(const MachineInstr &MI)
bool modifiesRegister(unsigned Reg, const TargetRegisterInfo *TRI) const
Return true if the MachineInstr modifies (fully define or partially define) the specified register...
instr_iterator instr_begin()
const int Hexagon_MEMH_OFFSET_MAX
bool is_TC2early(unsigned SchedClass)
bool isCall(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:632
unsigned nonDbgBBSize(const MachineBasicBlock *BB) const
getInstrTimingClassLatency - Compute the instruction latency of a given instruction using Timing Clas...
instr_iterator instr_end()
MachineBasicBlock * getMBB() const
const int Hexagon_ADDI_OFFSET_MAX
unsigned getFrameRegister(const MachineFunction &MF) const override
unsigned getRegState(const MachineOperand &RegOp)
Get all register state flags from machine operand RegOp.
const int Hexagon_MEMH_OFFSET_MIN
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:139
This class represents lattice values for constants.
Definition: AllocatorList.h:23
const InstrStage * beginStage(unsigned ItinClassIndx) const
Return the first stage of the itinerary.
static void parseOperands(const MachineInstr &MI, SmallVector< unsigned, 4 > &Defs, SmallVector< unsigned, 8 > &Uses)
Gather register def/uses from MI.
static bool mayAlias(MachineInstr &MIa, MachineInstr &MIb, AliasAnalysis *AA)
static cl::opt< bool > UseDFAHazardRec("dfa-hazard-rec", cl::init(true), cl::Hidden, cl::ZeroOrMore, cl::desc("Use the DFA based hazard recognizer."))
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Store the specified register of the given register class to the specified stack frame index...
void setBundleNoShuf(MachineBasicBlock::instr_iterator MIB) const
short getEquivalentHWInstr(const MachineInstr &MI) const
DFAPacketizer * CreateTargetScheduleState(const TargetSubtargetInfo &STI) const override
Create machine specific model for scheduling.
void push_back(const T &Elt)
Definition: SmallVector.h:211
bool isAbsoluteSet(const MachineInstr &MI) const
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:382
bool isJumpR(const MachineInstr &MI) const
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
bool SubsumesPredicate(ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const override
Returns true if the first specified predicate subsumes the second, e.g.
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
unsigned getUnits() const
Returns the choice of FUs.
bool isConstExtended(const MachineInstr &MI) const
unsigned getReg() const
getReg - Returns the register number.
bool getInvertedPredSense(SmallVectorImpl< MachineOperand > &Cond) const
Address of indexed Jump Table for switch.
unsigned Reg
unsigned nonDbgBundleSize(MachineBasicBlock::const_iterator BundleHead) const
unsigned getSubReg() const
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:252
bool isInlineAsm() const
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
Reverses the branch condition of the specified condition list, returning false on success and true if...
int getMaxValue(const MachineInstr &MI) const
ArrayRef< std::pair< unsigned, const char * > > getSerializableBitmaskMachineOperandTargetFlags() const override
Return an array that contains the bitmask target flag values and their names.
const int Hexagon_ADDI_OFFSET_MIN
bool reversePredSense(MachineInstr &MI) const
int getDotNewPredOp(const MachineInstr &MI, const MachineBranchProbabilityInfo *MBPI) const
bool isTransient() const
Return true if this is a transient instruction that is either very likely to be eliminated during reg...
demanded bits
MachineBasicBlock reference.
#define HEXAGON_INSTR_SIZE
bool isExpr(unsigned OpType) const
bool isTailCall(const MachineInstr &MI) const override
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:33
F(f)
unsigned reduceLoopCount(MachineBasicBlock &MBB, MachineInstr *IndVar, MachineInstr &Cmp, SmallVectorImpl< MachineOperand > &Cond, SmallVectorImpl< MachineInstr *> &PrevInsts, unsigned Iter, unsigned MaxIter) const override
Generate code to reduce the loop iteration by one and check if the loop is finished.
bool isCPI() const
isCPI - Tests if this is a MO_ConstantPoolIndex operand.
bool producesStall(const MachineInstr &ProdMI, const MachineInstr &ConsMI) const
MachineInstrBundleIterator< const MachineInstr > const_iterator
const HexagonFrameLowering * getFrameLowering() const override
unsigned getMemAccessSize(const MachineInstr &MI) const
const int Hexagon_MEMD_OFFSET_MAX
unsigned getSize(const MachineInstr &MI) const
int getDotCurOp(const MachineInstr &MI) const
bool mayLoad() const
Return true if this instruction could possibly read memory.
Definition: MCInstrDesc.h:398
bool isLateResultInstr(const MachineInstr &MI) const
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:458
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
bool is_TC1(unsigned SchedClass)
void immediateExtend(MachineInstr &MI) const
immediateExtend - Changes the instruction in place to one using an immediate extender.
int getDotNewPredJumpOp(const MachineInstr &MI, const MachineBranchProbabilityInfo *MBPI) const
short changeAddrMode_ur_rr(short Opc) const
bool hasLoadFromStackSlot(const MachineInstr &MI, SmallVectorImpl< const MachineMemOperand *> &Accesses) const override
Check if the instruction or the bundle of instructions has load from stack slots. ...
unsigned getSpillSize(const TargetRegisterClass &RC) const
Return the size in bytes of the stack slot allocated to hold a spilled copy of a register from class ...
return AArch64::GPR64RegClass contains(Reg)
iterator_range< succ_iterator > successors()
bool isToBeScheduledASAP(const MachineInstr &MI1, const MachineInstr &MI2) const
void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
Insert a noop into the instruction stream at the specified point.
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
Analyze the branching code at the end of MBB, returning true if it cannot be understood (e...
bool isHVXVec(const MachineInstr &MI) const
static cl::opt< bool > BranchRelaxAsmLarge("branch-relax-asm-large", cl::init(true), cl::Hidden, cl::ZeroOrMore, cl::desc("branch relax asm"))
bool isComplex(const MachineInstr &MI) const
unsigned getSpillAlignment(const TargetRegisterClass &RC) const
Return the minimum required alignment in bytes for a spill slot for a register of this class...
static cl::opt< bool > DisableNVSchedule("disable-hexagon-nv-schedule", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("Disable schedule adjustment for new value stores."))
A description of a memory reference used in the backend.
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Load the specified register of the given register class from the specified stack frame index...
unsigned getInvertedPredicatedOpcode(const int Opc) const
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
MCSuperRegIterator enumerates all super-registers of Reg.
ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, const ScheduleDAG *DAG) const override
Allocate and return a hazard recognizer to use for this target when scheduling the machine instructio...
const HexagonInstrInfo * TII
Printable printMBBReference(const MachineBasicBlock &MBB)
Prints a machine basic block reference.
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
Definition: ArrayRef.h:450
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:411
Printable printReg(unsigned Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
LLVM_NODISCARD size_t count(char C) const
Return the number of occurrences of C in the string.
Definition: StringRef.h:457
unsigned getCompoundOpcode(const MachineInstr &GA, const MachineInstr &GB) const
bool isPredicatedNew(const MachineInstr &MI) const
bool canExecuteInBundle(const MachineInstr &First, const MachineInstr &Second) const
Can these instructions execute at the same time in a bundle.
bool predOpcodeHasNot(ArrayRef< MachineOperand > Cond) const
const HexagonRegisterInfo * getRegisterInfo() const override
MachineBasicBlock * getBottomBlock()
Return the "bottom" block in the loop, which is the last block in the linear layout, ignoring any parts of the loop not contiguous with the part that contains the header.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
bool isVecUsableNextPacket(const MachineInstr &ProdMI, const MachineInstr &ConsMI) const
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
Name of external global symbol.
static StringRef getName(Value *V)
SimpleValueType SimpleTy
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
bool isDotNewInst(const MachineInstr &MI) const
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:408
bool isDeallocRet(const MachineInstr &MI) const
bool isExtended(const MachineInstr &MI) const
bool hasStoreToStackSlot(const MachineInstr &MI, SmallVectorImpl< const MachineMemOperand *> &Accesses) const override
Check if the instruction or the bundle of instructions has store to stack slots.
const char * getSymbolName() const
bool is_TC2(unsigned SchedClass)
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, unsigned base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
INLINEASM - Represents an inline asm block.
Definition: ISDOpcodes.h:695
bool isSolo(const MachineInstr &MI) const
bool isLateInstrFeedsEarlyInstr(const MachineInstr &LRMI, const MachineInstr &ESMI) const
MachineBasicBlock::instr_iterator expandVGatherPseudo(MachineInstr &MI) const
bool expandPostRAPseudo(MachineInstr &MI) const override
This function is called for all pseudo instructions that remain after register allocation.
bool PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Cond) const override
Convert the instruction into a predicated instruction.
bool predCanBeUsedAsDotNew(const MachineInstr &MI, unsigned PredReg) const
MachineInstr * findLoopInstr(MachineBasicBlock *BB, unsigned EndLoopOp, MachineBasicBlock *TargetBB, SmallPtrSet< MachineBasicBlock *, 8 > &Visited) const
Find the hardware loop instruction used to set-up the specified loop.
SmallVector< MachineInstr *, 2 > getBranchingInstrs(MachineBasicBlock &MBB) const
bool doesNotReturn(const MachineInstr &CallMI) const
unsigned getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:291
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:405
bool isIndirectBranch(QueryType Type=AnyInBundle) const
Return true if this is an indirect branch, such as a branch through a register.
Definition: MachineInstr.h:662
bool isEndLoopN(unsigned Opcode) const
bool isBundle() const
bool isCompoundBranchInstr(const MachineInstr &MI) const
void clearKillFlags(unsigned Reg) const
clearKillFlags - Iterate over all the uses of the given register and clear the kill flag from the Mac...
MO_GOT - This flag indicates that a symbol operand represents the address of the GOT entry for the sy...
short changeAddrMode_io_rr(short Opc) const
bool isPredictedTaken(unsigned Opcode) const
int getMinValue(const MachineInstr &MI) const
bool getBundleNoShuf(const MachineInstr &MIB) const
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
LLVM_NODISCARD size_t size() const
size - Get the string size.
Definition: StringRef.h:130
bool isFPImm() const
isFPImm - Tests if this is a MO_FPImmediate operand.
Itinerary data supplied by a subtarget to be used by a target.
short changeAddrMode_io_pi(short Opc) const
bool isTC1(const MachineInstr &MI) const
unsigned getUndefRegState(bool B)
unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const override
Compute the instruction latency of a given instruction.
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
unsigned getStageLatency(unsigned ItinClassIndx) const
Return the total stage latency of the given class.
short changeAddrMode_rr_ur(short Opc) const
reverse_iterator rbegin()
bool isBranch(QueryType Type=AnyInBundle) const
Returns true if this is a conditional, unconditional, or indirect branch.
Definition: MachineInstr.h:656
bool getPredReg(ArrayRef< MachineOperand > Cond, unsigned &PredReg, unsigned &PredRegPos, unsigned &PredRegFlags) const
BasicBlockListType::iterator iterator
unsigned getKillRegState(bool B)
virtual const InstrItineraryData * getInstrItineraryData() const
getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget...
unsigned getCExtOpNum(const MachineInstr &MI) const
const int Hexagon_MEMD_OFFSET_MIN
MachineOperand * getBaseAndOffset(const MachineInstr &MI, int64_t &Offset, unsigned &AccessSize) const
TargetInstrInfo - Interface to description of machine instruction set.
bool isReturn(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:622
bool is_TC3x(unsigned SchedClass)
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:55
static cl::opt< bool > EnableBranchPrediction("hexagon-enable-branch-prediction", cl::Hidden, cl::init(true), cl::desc("Enable branch prediction"))
bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const override
Return true if it&#39;s profitable for if-converter to duplicate instructions of specified accumulated in...
The memory access is volatile.
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
unsigned getSchedClass() const
Return the scheduling class for this instruction.
Definition: MCInstrDesc.h:576
unsigned getObjectAlignment(int ObjectIdx) const
Return the alignment of the specified stack object.
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
Definition: MachineInstr.h:819
Address of a global value.
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:432
const int Hexagon_MEMW_OFFSET_MAX
Constants for Hexagon instructions.
bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb, AliasAnalysis *AA=nullptr) const override
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
unsigned const MachineRegisterInfo * MRI
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
Definition: MathExtras.h:428
Machine Value Type.