LLVM  10.0.0svn
HexagonInstrInfo.cpp
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1 //===- HexagonInstrInfo.cpp - Hexagon Instruction Information -------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the Hexagon implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "HexagonInstrInfo.h"
14 #include "Hexagon.h"
15 #include "HexagonFrameLowering.h"
17 #include "HexagonRegisterInfo.h"
18 #include "HexagonSubtarget.h"
19 #include "llvm/ADT/ArrayRef.h"
20 #include "llvm/ADT/SmallPtrSet.h"
21 #include "llvm/ADT/SmallVector.h"
22 #include "llvm/ADT/StringRef.h"
41 #include "llvm/IR/DebugLoc.h"
42 #include "llvm/MC/MCAsmInfo.h"
43 #include "llvm/MC/MCInstrDesc.h"
45 #include "llvm/MC/MCRegisterInfo.h"
48 #include "llvm/Support/Debug.h"
54 #include <cassert>
55 #include <cctype>
56 #include <cstdint>
57 #include <cstring>
58 #include <iterator>
59 #include <string>
60 #include <utility>
61 
62 using namespace llvm;
63 
64 #define DEBUG_TYPE "hexagon-instrinfo"
65 
66 #define GET_INSTRINFO_CTOR_DTOR
67 #define GET_INSTRMAP_INFO
69 #include "HexagonGenDFAPacketizer.inc"
70 #include "HexagonGenInstrInfo.inc"
71 
72 cl::opt<bool> ScheduleInlineAsm("hexagon-sched-inline-asm", cl::Hidden,
73  cl::init(false), cl::desc("Do not consider inline-asm a scheduling/"
74  "packetization boundary."));
75 
76 static cl::opt<bool> EnableBranchPrediction("hexagon-enable-branch-prediction",
77  cl::Hidden, cl::init(true), cl::desc("Enable branch prediction"));
78 
79 static cl::opt<bool> DisableNVSchedule("disable-hexagon-nv-schedule",
81  cl::desc("Disable schedule adjustment for new value stores."));
82 
84  "enable-timing-class-latency", cl::Hidden, cl::init(false),
85  cl::desc("Enable timing class latency"));
86 
88  "enable-alu-forwarding", cl::Hidden, cl::init(true),
89  cl::desc("Enable vec alu forwarding"));
90 
92  "enable-acc-forwarding", cl::Hidden, cl::init(true),
93  cl::desc("Enable vec acc forwarding"));
94 
95 static cl::opt<bool> BranchRelaxAsmLarge("branch-relax-asm-large",
96  cl::init(true), cl::Hidden, cl::ZeroOrMore, cl::desc("branch relax asm"));
97 
98 static cl::opt<bool> UseDFAHazardRec("dfa-hazard-rec",
100  cl::desc("Use the DFA based hazard recognizer."));
101 
102 /// Constants for Hexagon instructions.
103 const int Hexagon_MEMW_OFFSET_MAX = 4095;
104 const int Hexagon_MEMW_OFFSET_MIN = -4096;
105 const int Hexagon_MEMD_OFFSET_MAX = 8191;
106 const int Hexagon_MEMD_OFFSET_MIN = -8192;
107 const int Hexagon_MEMH_OFFSET_MAX = 2047;
108 const int Hexagon_MEMH_OFFSET_MIN = -2048;
109 const int Hexagon_MEMB_OFFSET_MAX = 1023;
110 const int Hexagon_MEMB_OFFSET_MIN = -1024;
111 const int Hexagon_ADDI_OFFSET_MAX = 32767;
112 const int Hexagon_ADDI_OFFSET_MIN = -32768;
113 
114 // Pin the vtable to this file.
115 void HexagonInstrInfo::anchor() {}
116 
118  : HexagonGenInstrInfo(Hexagon::ADJCALLSTACKDOWN, Hexagon::ADJCALLSTACKUP),
119  Subtarget(ST) {}
120 
121 static bool isIntRegForSubInst(unsigned Reg) {
122  return (Reg >= Hexagon::R0 && Reg <= Hexagon::R7) ||
123  (Reg >= Hexagon::R16 && Reg <= Hexagon::R23);
124 }
125 
126 static bool isDblRegForSubInst(unsigned Reg, const HexagonRegisterInfo &HRI) {
127  return isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::isub_lo)) &&
128  isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::isub_hi));
129 }
130 
131 /// Calculate number of instructions excluding the debug instructions.
134  unsigned Count = 0;
135  for (; MIB != MIE; ++MIB) {
136  if (!MIB->isDebugInstr())
137  ++Count;
138  }
139  return Count;
140 }
141 
142 /// Find the hardware loop instruction used to set-up the specified loop.
143 /// On Hexagon, we have two instructions used to set-up the hardware loop
144 /// (LOOP0, LOOP1) with corresponding endloop (ENDLOOP0, ENDLOOP1) instructions
145 /// to indicate the end of a loop.
147  unsigned EndLoopOp, MachineBasicBlock *TargetBB,
148  SmallPtrSet<MachineBasicBlock *, 8> &Visited) const {
149  unsigned LOOPi;
150  unsigned LOOPr;
151  if (EndLoopOp == Hexagon::ENDLOOP0) {
152  LOOPi = Hexagon::J2_loop0i;
153  LOOPr = Hexagon::J2_loop0r;
154  } else { // EndLoopOp == Hexagon::EndLOOP1
155  LOOPi = Hexagon::J2_loop1i;
156  LOOPr = Hexagon::J2_loop1r;
157  }
158 
159  // The loop set-up instruction will be in a predecessor block
160  for (MachineBasicBlock *PB : BB->predecessors()) {
161  // If this has been visited, already skip it.
162  if (!Visited.insert(PB).second)
163  continue;
164  if (PB == BB)
165  continue;
166  for (auto I = PB->instr_rbegin(), E = PB->instr_rend(); I != E; ++I) {
167  unsigned Opc = I->getOpcode();
168  if (Opc == LOOPi || Opc == LOOPr)
169  return &*I;
170  // We've reached a different loop, which means the loop01 has been
171  // removed.
172  if (Opc == EndLoopOp && I->getOperand(0).getMBB() != TargetBB)
173  return nullptr;
174  }
175  // Check the predecessors for the LOOP instruction.
176  if (MachineInstr *Loop = findLoopInstr(PB, EndLoopOp, TargetBB, Visited))
177  return Loop;
178  }
179  return nullptr;
180 }
181 
182 /// Gather register def/uses from MI.
183 /// This treats possible (predicated) defs as actually happening ones
184 /// (conservatively).
185 static inline void parseOperands(const MachineInstr &MI,
187  Defs.clear();
188  Uses.clear();
189 
190  for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
191  const MachineOperand &MO = MI.getOperand(i);
192 
193  if (!MO.isReg())
194  continue;
195 
196  Register Reg = MO.getReg();
197  if (!Reg)
198  continue;
199 
200  if (MO.isUse())
201  Uses.push_back(MO.getReg());
202 
203  if (MO.isDef())
204  Defs.push_back(MO.getReg());
205  }
206 }
207 
208 // Position dependent, so check twice for swap.
209 static bool isDuplexPairMatch(unsigned Ga, unsigned Gb) {
210  switch (Ga) {
212  default:
213  return false;
214  case HexagonII::HSIG_L1:
215  return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_A);
216  case HexagonII::HSIG_L2:
217  return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_L2 ||
218  Gb == HexagonII::HSIG_A);
219  case HexagonII::HSIG_S1:
220  return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_L2 ||
221  Gb == HexagonII::HSIG_S1 || Gb == HexagonII::HSIG_A);
222  case HexagonII::HSIG_S2:
223  return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_L2 ||
224  Gb == HexagonII::HSIG_S1 || Gb == HexagonII::HSIG_S2 ||
225  Gb == HexagonII::HSIG_A);
226  case HexagonII::HSIG_A:
227  return (Gb == HexagonII::HSIG_A);
229  return (Gb == HexagonII::HSIG_Compound);
230  }
231  return false;
232 }
233 
234 /// isLoadFromStackSlot - If the specified machine instruction is a direct
235 /// load from a stack slot, return the virtual or physical register number of
236 /// the destination along with the FrameIndex of the loaded stack slot. If
237 /// not, return 0. This predicate must return 0 if the instruction has
238 /// any side effects other than loading from the stack slot.
240  int &FrameIndex) const {
241  switch (MI.getOpcode()) {
242  default:
243  break;
244  case Hexagon::L2_loadri_io:
245  case Hexagon::L2_loadrd_io:
246  case Hexagon::V6_vL32b_ai:
247  case Hexagon::V6_vL32b_nt_ai:
248  case Hexagon::V6_vL32Ub_ai:
249  case Hexagon::LDriw_pred:
250  case Hexagon::LDriw_ctr:
251  case Hexagon::PS_vloadrq_ai:
252  case Hexagon::PS_vloadrw_ai:
253  case Hexagon::PS_vloadrw_nt_ai: {
254  const MachineOperand OpFI = MI.getOperand(1);
255  if (!OpFI.isFI())
256  return 0;
257  const MachineOperand OpOff = MI.getOperand(2);
258  if (!OpOff.isImm() || OpOff.getImm() != 0)
259  return 0;
260  FrameIndex = OpFI.getIndex();
261  return MI.getOperand(0).getReg();
262  }
263 
264  case Hexagon::L2_ploadrit_io:
265  case Hexagon::L2_ploadrif_io:
266  case Hexagon::L2_ploadrdt_io:
267  case Hexagon::L2_ploadrdf_io: {
268  const MachineOperand OpFI = MI.getOperand(2);
269  if (!OpFI.isFI())
270  return 0;
271  const MachineOperand OpOff = MI.getOperand(3);
272  if (!OpOff.isImm() || OpOff.getImm() != 0)
273  return 0;
274  FrameIndex = OpFI.getIndex();
275  return MI.getOperand(0).getReg();
276  }
277  }
278 
279  return 0;
280 }
281 
282 /// isStoreToStackSlot - If the specified machine instruction is a direct
283 /// store to a stack slot, return the virtual or physical register number of
284 /// the source reg along with the FrameIndex of the loaded stack slot. If
285 /// not, return 0. This predicate must return 0 if the instruction has
286 /// any side effects other than storing to the stack slot.
288  int &FrameIndex) const {
289  switch (MI.getOpcode()) {
290  default:
291  break;
292  case Hexagon::S2_storerb_io:
293  case Hexagon::S2_storerh_io:
294  case Hexagon::S2_storeri_io:
295  case Hexagon::S2_storerd_io:
296  case Hexagon::V6_vS32b_ai:
297  case Hexagon::V6_vS32Ub_ai:
298  case Hexagon::STriw_pred:
299  case Hexagon::STriw_ctr:
300  case Hexagon::PS_vstorerq_ai:
301  case Hexagon::PS_vstorerw_ai: {
302  const MachineOperand &OpFI = MI.getOperand(0);
303  if (!OpFI.isFI())
304  return 0;
305  const MachineOperand &OpOff = MI.getOperand(1);
306  if (!OpOff.isImm() || OpOff.getImm() != 0)
307  return 0;
308  FrameIndex = OpFI.getIndex();
309  return MI.getOperand(2).getReg();
310  }
311 
312  case Hexagon::S2_pstorerbt_io:
313  case Hexagon::S2_pstorerbf_io:
314  case Hexagon::S2_pstorerht_io:
315  case Hexagon::S2_pstorerhf_io:
316  case Hexagon::S2_pstorerit_io:
317  case Hexagon::S2_pstorerif_io:
318  case Hexagon::S2_pstorerdt_io:
319  case Hexagon::S2_pstorerdf_io: {
320  const MachineOperand &OpFI = MI.getOperand(1);
321  if (!OpFI.isFI())
322  return 0;
323  const MachineOperand &OpOff = MI.getOperand(2);
324  if (!OpOff.isImm() || OpOff.getImm() != 0)
325  return 0;
326  FrameIndex = OpFI.getIndex();
327  return MI.getOperand(3).getReg();
328  }
329  }
330 
331  return 0;
332 }
333 
334 /// This function checks if the instruction or bundle of instructions
335 /// has load from stack slot and returns frameindex and machine memory
336 /// operand of that instruction if true.
338  const MachineInstr &MI,
340  if (MI.isBundle()) {
341  const MachineBasicBlock *MBB = MI.getParent();
343  for (++MII; MII != MBB->instr_end() && MII->isInsideBundle(); ++MII)
344  if (TargetInstrInfo::hasLoadFromStackSlot(*MII, Accesses))
345  return true;
346  return false;
347  }
348 
349  return TargetInstrInfo::hasLoadFromStackSlot(MI, Accesses);
350 }
351 
352 /// This function checks if the instruction or bundle of instructions
353 /// has store to stack slot and returns frameindex and machine memory
354 /// operand of that instruction if true.
356  const MachineInstr &MI,
358  if (MI.isBundle()) {
359  const MachineBasicBlock *MBB = MI.getParent();
361  for (++MII; MII != MBB->instr_end() && MII->isInsideBundle(); ++MII)
362  if (TargetInstrInfo::hasStoreToStackSlot(*MII, Accesses))
363  return true;
364  return false;
365  }
366 
367  return TargetInstrInfo::hasStoreToStackSlot(MI, Accesses);
368 }
369 
370 /// This function can analyze one/two way branching only and should (mostly) be
371 /// called by target independent side.
372 /// First entry is always the opcode of the branching instruction, except when
373 /// the Cond vector is supposed to be empty, e.g., when AnalyzeBranch fails, a
374 /// BB with only unconditional jump. Subsequent entries depend upon the opcode,
375 /// e.g. Jump_c p will have
376 /// Cond[0] = Jump_c
377 /// Cond[1] = p
378 /// HW-loop ENDLOOP:
379 /// Cond[0] = ENDLOOP
380 /// Cond[1] = MBB
381 /// New value jump:
382 /// Cond[0] = Hexagon::CMPEQri_f_Jumpnv_t_V4 -- specific opcode
383 /// Cond[1] = R
384 /// Cond[2] = Imm
386  MachineBasicBlock *&TBB,
387  MachineBasicBlock *&FBB,
389  bool AllowModify) const {
390  TBB = nullptr;
391  FBB = nullptr;
392  Cond.clear();
393 
394  // If the block has no terminators, it just falls into the block after it.
396  if (I == MBB.instr_begin())
397  return false;
398 
399  // A basic block may looks like this:
400  //
401  // [ insn
402  // EH_LABEL
403  // insn
404  // insn
405  // insn
406  // EH_LABEL
407  // insn ]
408  //
409  // It has two succs but does not have a terminator
410  // Don't know how to handle it.
411  do {
412  --I;
413  if (I->isEHLabel())
414  // Don't analyze EH branches.
415  return true;
416  } while (I != MBB.instr_begin());
417 
418  I = MBB.instr_end();
419  --I;
420 
421  while (I->isDebugInstr()) {
422  if (I == MBB.instr_begin())
423  return false;
424  --I;
425  }
426 
427  bool JumpToBlock = I->getOpcode() == Hexagon::J2_jump &&
428  I->getOperand(0).isMBB();
429  // Delete the J2_jump if it's equivalent to a fall-through.
430  if (AllowModify && JumpToBlock &&
431  MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
432  LLVM_DEBUG(dbgs() << "\nErasing the jump to successor block\n";);
433  I->eraseFromParent();
434  I = MBB.instr_end();
435  if (I == MBB.instr_begin())
436  return false;
437  --I;
438  }
439  if (!isUnpredicatedTerminator(*I))
440  return false;
441 
442  // Get the last instruction in the block.
443  MachineInstr *LastInst = &*I;
444  MachineInstr *SecondLastInst = nullptr;
445  // Find one more terminator if present.
446  while (true) {
447  if (&*I != LastInst && !I->isBundle() && isUnpredicatedTerminator(*I)) {
448  if (!SecondLastInst)
449  SecondLastInst = &*I;
450  else
451  // This is a third branch.
452  return true;
453  }
454  if (I == MBB.instr_begin())
455  break;
456  --I;
457  }
458 
459  int LastOpcode = LastInst->getOpcode();
460  int SecLastOpcode = SecondLastInst ? SecondLastInst->getOpcode() : 0;
461  // If the branch target is not a basic block, it could be a tail call.
462  // (It is, if the target is a function.)
463  if (LastOpcode == Hexagon::J2_jump && !LastInst->getOperand(0).isMBB())
464  return true;
465  if (SecLastOpcode == Hexagon::J2_jump &&
466  !SecondLastInst->getOperand(0).isMBB())
467  return true;
468 
469  bool LastOpcodeHasJMP_c = PredOpcodeHasJMP_c(LastOpcode);
470  bool LastOpcodeHasNVJump = isNewValueJump(*LastInst);
471 
472  if (LastOpcodeHasJMP_c && !LastInst->getOperand(1).isMBB())
473  return true;
474 
475  // If there is only one terminator instruction, process it.
476  if (LastInst && !SecondLastInst) {
477  if (LastOpcode == Hexagon::J2_jump) {
478  TBB = LastInst->getOperand(0).getMBB();
479  return false;
480  }
481  if (isEndLoopN(LastOpcode)) {
482  TBB = LastInst->getOperand(0).getMBB();
483  Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
484  Cond.push_back(LastInst->getOperand(0));
485  return false;
486  }
487  if (LastOpcodeHasJMP_c) {
488  TBB = LastInst->getOperand(1).getMBB();
489  Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
490  Cond.push_back(LastInst->getOperand(0));
491  return false;
492  }
493  // Only supporting rr/ri versions of new-value jumps.
494  if (LastOpcodeHasNVJump && (LastInst->getNumExplicitOperands() == 3)) {
495  TBB = LastInst->getOperand(2).getMBB();
496  Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
497  Cond.push_back(LastInst->getOperand(0));
498  Cond.push_back(LastInst->getOperand(1));
499  return false;
500  }
501  LLVM_DEBUG(dbgs() << "\nCant analyze " << printMBBReference(MBB)
502  << " with one jump\n";);
503  // Otherwise, don't know what this is.
504  return true;
505  }
506 
507  bool SecLastOpcodeHasJMP_c = PredOpcodeHasJMP_c(SecLastOpcode);
508  bool SecLastOpcodeHasNVJump = isNewValueJump(*SecondLastInst);
509  if (SecLastOpcodeHasJMP_c && (LastOpcode == Hexagon::J2_jump)) {
510  if (!SecondLastInst->getOperand(1).isMBB())
511  return true;
512  TBB = SecondLastInst->getOperand(1).getMBB();
513  Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
514  Cond.push_back(SecondLastInst->getOperand(0));
515  FBB = LastInst->getOperand(0).getMBB();
516  return false;
517  }
518 
519  // Only supporting rr/ri versions of new-value jumps.
520  if (SecLastOpcodeHasNVJump &&
521  (SecondLastInst->getNumExplicitOperands() == 3) &&
522  (LastOpcode == Hexagon::J2_jump)) {
523  TBB = SecondLastInst->getOperand(2).getMBB();
524  Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
525  Cond.push_back(SecondLastInst->getOperand(0));
526  Cond.push_back(SecondLastInst->getOperand(1));
527  FBB = LastInst->getOperand(0).getMBB();
528  return false;
529  }
530 
531  // If the block ends with two Hexagon:JMPs, handle it. The second one is not
532  // executed, so remove it.
533  if (SecLastOpcode == Hexagon::J2_jump && LastOpcode == Hexagon::J2_jump) {
534  TBB = SecondLastInst->getOperand(0).getMBB();
535  I = LastInst->getIterator();
536  if (AllowModify)
537  I->eraseFromParent();
538  return false;
539  }
540 
541  // If the block ends with an ENDLOOP, and J2_jump, handle it.
542  if (isEndLoopN(SecLastOpcode) && LastOpcode == Hexagon::J2_jump) {
543  TBB = SecondLastInst->getOperand(0).getMBB();
544  Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
545  Cond.push_back(SecondLastInst->getOperand(0));
546  FBB = LastInst->getOperand(0).getMBB();
547  return false;
548  }
549  LLVM_DEBUG(dbgs() << "\nCant analyze " << printMBBReference(MBB)
550  << " with two jumps";);
551  // Otherwise, can't handle this.
552  return true;
553 }
554 
556  int *BytesRemoved) const {
557  assert(!BytesRemoved && "code size not handled");
558 
559  LLVM_DEBUG(dbgs() << "\nRemoving branches out of " << printMBBReference(MBB));
561  unsigned Count = 0;
562  while (I != MBB.begin()) {
563  --I;
564  if (I->isDebugInstr())
565  continue;
566  // Only removing branches from end of MBB.
567  if (!I->isBranch())
568  return Count;
569  if (Count && (I->getOpcode() == Hexagon::J2_jump))
570  llvm_unreachable("Malformed basic block: unconditional branch not last");
571  MBB.erase(&MBB.back());
572  I = MBB.end();
573  ++Count;
574  }
575  return Count;
576 }
577 
579  MachineBasicBlock *TBB,
580  MachineBasicBlock *FBB,
582  const DebugLoc &DL,
583  int *BytesAdded) const {
584  unsigned BOpc = Hexagon::J2_jump;
585  unsigned BccOpc = Hexagon::J2_jumpt;
586  assert(validateBranchCond(Cond) && "Invalid branching condition");
587  assert(TBB && "insertBranch must not be told to insert a fallthrough");
588  assert(!BytesAdded && "code size not handled");
589 
590  // Check if reverseBranchCondition has asked to reverse this branch
591  // If we want to reverse the branch an odd number of times, we want
592  // J2_jumpf.
593  if (!Cond.empty() && Cond[0].isImm())
594  BccOpc = Cond[0].getImm();
595 
596  if (!FBB) {
597  if (Cond.empty()) {
598  // Due to a bug in TailMerging/CFG Optimization, we need to add a
599  // special case handling of a predicated jump followed by an
600  // unconditional jump. If not, Tail Merging and CFG Optimization go
601  // into an infinite loop.
602  MachineBasicBlock *NewTBB, *NewFBB;
604  auto Term = MBB.getFirstTerminator();
605  if (Term != MBB.end() && isPredicated(*Term) &&
606  !analyzeBranch(MBB, NewTBB, NewFBB, Cond, false) &&
607  MachineFunction::iterator(NewTBB) == ++MBB.getIterator()) {
609  removeBranch(MBB);
610  return insertBranch(MBB, TBB, nullptr, Cond, DL);
611  }
612  BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
613  } else if (isEndLoopN(Cond[0].getImm())) {
614  int EndLoopOp = Cond[0].getImm();
615  assert(Cond[1].isMBB());
616  // Since we're adding an ENDLOOP, there better be a LOOP instruction.
617  // Check for it, and change the BB target if needed.
619  MachineInstr *Loop = findLoopInstr(TBB, EndLoopOp, Cond[1].getMBB(),
620  VisitedBBs);
621  assert(Loop != nullptr && "Inserting an ENDLOOP without a LOOP");
622  Loop->getOperand(0).setMBB(TBB);
623  // Add the ENDLOOP after the finding the LOOP0.
624  BuildMI(&MBB, DL, get(EndLoopOp)).addMBB(TBB);
625  } else if (isNewValueJump(Cond[0].getImm())) {
626  assert((Cond.size() == 3) && "Only supporting rr/ri version of nvjump");
627  // New value jump
628  // (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset)
629  // (ins IntRegs:$src1, u5Imm:$src2, brtarget:$offset)
630  unsigned Flags1 = getUndefRegState(Cond[1].isUndef());
631  LLVM_DEBUG(dbgs() << "\nInserting NVJump for "
632  << printMBBReference(MBB););
633  if (Cond[2].isReg()) {
634  unsigned Flags2 = getUndefRegState(Cond[2].isUndef());
635  BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[1].getReg(), Flags1).
636  addReg(Cond[2].getReg(), Flags2).addMBB(TBB);
637  } else if(Cond[2].isImm()) {
638  BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[1].getReg(), Flags1).
639  addImm(Cond[2].getImm()).addMBB(TBB);
640  } else
641  llvm_unreachable("Invalid condition for branching");
642  } else {
643  assert((Cond.size() == 2) && "Malformed cond vector");
644  const MachineOperand &RO = Cond[1];
645  unsigned Flags = getUndefRegState(RO.isUndef());
646  BuildMI(&MBB, DL, get(BccOpc)).addReg(RO.getReg(), Flags).addMBB(TBB);
647  }
648  return 1;
649  }
650  assert((!Cond.empty()) &&
651  "Cond. cannot be empty when multiple branchings are required");
652  assert((!isNewValueJump(Cond[0].getImm())) &&
653  "NV-jump cannot be inserted with another branch");
654  // Special case for hardware loops. The condition is a basic block.
655  if (isEndLoopN(Cond[0].getImm())) {
656  int EndLoopOp = Cond[0].getImm();
657  assert(Cond[1].isMBB());
658  // Since we're adding an ENDLOOP, there better be a LOOP instruction.
659  // Check for it, and change the BB target if needed.
661  MachineInstr *Loop = findLoopInstr(TBB, EndLoopOp, Cond[1].getMBB(),
662  VisitedBBs);
663  assert(Loop != nullptr && "Inserting an ENDLOOP without a LOOP");
664  Loop->getOperand(0).setMBB(TBB);
665  // Add the ENDLOOP after the finding the LOOP0.
666  BuildMI(&MBB, DL, get(EndLoopOp)).addMBB(TBB);
667  } else {
668  const MachineOperand &RO = Cond[1];
669  unsigned Flags = getUndefRegState(RO.isUndef());
670  BuildMI(&MBB, DL, get(BccOpc)).addReg(RO.getReg(), Flags).addMBB(TBB);
671  }
672  BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
673 
674  return 2;
675 }
676 
677 namespace {
678 class HexagonPipelinerLoopInfo : public TargetInstrInfo::PipelinerLoopInfo {
679  MachineInstr *Loop, *EndLoop;
680  MachineFunction *MF;
681  const HexagonInstrInfo *TII;
682  int64_t TripCount;
683  Register LoopCount;
684  DebugLoc DL;
685 
686 public:
687  HexagonPipelinerLoopInfo(MachineInstr *Loop, MachineInstr *EndLoop)
688  : Loop(Loop), EndLoop(EndLoop), MF(Loop->getParent()->getParent()),
690  DL(Loop->getDebugLoc()) {
691  // Inspect the Loop instruction up-front, as it may be deleted when we call
692  // createTripCountGreaterCondition.
693  TripCount = Loop->getOpcode() == Hexagon::J2_loop0r
694  ? -1
695  : Loop->getOperand(1).getImm();
696  if (TripCount == -1)
697  LoopCount = Loop->getOperand(1).getReg();
698  }
699 
700  bool shouldIgnoreForPipelining(const MachineInstr *MI) const override {
701  // Only ignore the terminator.
702  return MI == EndLoop;
703  }
704 
706  createTripCountGreaterCondition(int TC, MachineBasicBlock &MBB,
707  SmallVectorImpl<MachineOperand> &Cond) override {
708  if (TripCount == -1) {
709  // Check if we're done with the loop.
710  unsigned Done = TII->createVR(MF, MVT::i1);
711  MachineInstr *NewCmp = BuildMI(&MBB, DL,
712  TII->get(Hexagon::C2_cmpgtui), Done)
713  .addReg(LoopCount)
714  .addImm(TC);
715  Cond.push_back(MachineOperand::CreateImm(Hexagon::J2_jumpf));
716  Cond.push_back(NewCmp->getOperand(0));
717  return {};
718  }
719 
720  return TripCount > TC;
721  }
722 
723  void setPreheader(MachineBasicBlock *NewPreheader) override {
724  NewPreheader->splice(NewPreheader->getFirstTerminator(), Loop->getParent(),
725  Loop);
726  }
727 
728  void adjustTripCount(int TripCountAdjust) override {
729  // If the loop trip count is a compile-time value, then just change the
730  // value.
731  if (Loop->getOpcode() == Hexagon::J2_loop0i ||
732  Loop->getOpcode() == Hexagon::J2_loop1i) {
733  int64_t TripCount = Loop->getOperand(1).getImm() + TripCountAdjust;
734  assert(TripCount > 0 && "Can't create an empty or negative loop!");
735  Loop->getOperand(1).setImm(TripCount);
736  return;
737  }
738 
739  // The loop trip count is a run-time value. We generate code to subtract
740  // one from the trip count, and update the loop instruction.
741  Register LoopCount = Loop->getOperand(1).getReg();
742  Register NewLoopCount = TII->createVR(MF, MVT::i32);
743  BuildMI(*Loop->getParent(), Loop, Loop->getDebugLoc(),
744  TII->get(Hexagon::A2_addi), NewLoopCount)
745  .addReg(LoopCount)
746  .addImm(TripCountAdjust);
747  Loop->getOperand(1).setReg(NewLoopCount);
748  }
749 
750  void disposed() override { Loop->eraseFromParent(); }
751 };
752 } // namespace
753 
754 std::unique_ptr<TargetInstrInfo::PipelinerLoopInfo>
756  // We really "analyze" only hardware loops right now.
758 
759  if (I != LoopBB->end() && isEndLoopN(I->getOpcode())) {
761  MachineInstr *LoopInst = findLoopInstr(
762  LoopBB, I->getOpcode(), I->getOperand(0).getMBB(), VisitedBBs);
763  if (LoopInst)
764  return std::make_unique<HexagonPipelinerLoopInfo>(LoopInst, &*I);
765  }
766  return nullptr;
767 }
768 
770  unsigned NumCycles, unsigned ExtraPredCycles,
771  BranchProbability Probability) const {
772  return nonDbgBBSize(&MBB) <= 3;
773 }
774 
776  unsigned NumTCycles, unsigned ExtraTCycles, MachineBasicBlock &FMBB,
777  unsigned NumFCycles, unsigned ExtraFCycles, BranchProbability Probability)
778  const {
779  return nonDbgBBSize(&TMBB) <= 3 && nonDbgBBSize(&FMBB) <= 3;
780 }
781 
783  unsigned NumInstrs, BranchProbability Probability) const {
784  return NumInstrs <= 4;
785 }
786 
789  const DebugLoc &DL, unsigned DestReg,
790  unsigned SrcReg, bool KillSrc) const {
791  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
792  unsigned KillFlag = getKillRegState(KillSrc);
793 
794  if (Hexagon::IntRegsRegClass.contains(SrcReg, DestReg)) {
795  BuildMI(MBB, I, DL, get(Hexagon::A2_tfr), DestReg)
796  .addReg(SrcReg, KillFlag);
797  return;
798  }
799  if (Hexagon::DoubleRegsRegClass.contains(SrcReg, DestReg)) {
800  BuildMI(MBB, I, DL, get(Hexagon::A2_tfrp), DestReg)
801  .addReg(SrcReg, KillFlag);
802  return;
803  }
804  if (Hexagon::PredRegsRegClass.contains(SrcReg, DestReg)) {
805  // Map Pd = Ps to Pd = or(Ps, Ps).
806  BuildMI(MBB, I, DL, get(Hexagon::C2_or), DestReg)
807  .addReg(SrcReg).addReg(SrcReg, KillFlag);
808  return;
809  }
810  if (Hexagon::CtrRegsRegClass.contains(DestReg) &&
811  Hexagon::IntRegsRegClass.contains(SrcReg)) {
812  BuildMI(MBB, I, DL, get(Hexagon::A2_tfrrcr), DestReg)
813  .addReg(SrcReg, KillFlag);
814  return;
815  }
816  if (Hexagon::IntRegsRegClass.contains(DestReg) &&
817  Hexagon::CtrRegsRegClass.contains(SrcReg)) {
818  BuildMI(MBB, I, DL, get(Hexagon::A2_tfrcrr), DestReg)
819  .addReg(SrcReg, KillFlag);
820  return;
821  }
822  if (Hexagon::ModRegsRegClass.contains(DestReg) &&
823  Hexagon::IntRegsRegClass.contains(SrcReg)) {
824  BuildMI(MBB, I, DL, get(Hexagon::A2_tfrrcr), DestReg)
825  .addReg(SrcReg, KillFlag);
826  return;
827  }
828  if (Hexagon::PredRegsRegClass.contains(SrcReg) &&
829  Hexagon::IntRegsRegClass.contains(DestReg)) {
830  BuildMI(MBB, I, DL, get(Hexagon::C2_tfrpr), DestReg)
831  .addReg(SrcReg, KillFlag);
832  return;
833  }
834  if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
835  Hexagon::PredRegsRegClass.contains(DestReg)) {
836  BuildMI(MBB, I, DL, get(Hexagon::C2_tfrrp), DestReg)
837  .addReg(SrcReg, KillFlag);
838  return;
839  }
840  if (Hexagon::PredRegsRegClass.contains(SrcReg) &&
841  Hexagon::IntRegsRegClass.contains(DestReg)) {
842  BuildMI(MBB, I, DL, get(Hexagon::C2_tfrpr), DestReg)
843  .addReg(SrcReg, KillFlag);
844  return;
845  }
846  if (Hexagon::HvxVRRegClass.contains(SrcReg, DestReg)) {
847  BuildMI(MBB, I, DL, get(Hexagon::V6_vassign), DestReg).
848  addReg(SrcReg, KillFlag);
849  return;
850  }
851  if (Hexagon::HvxWRRegClass.contains(SrcReg, DestReg)) {
852  Register LoSrc = HRI.getSubReg(SrcReg, Hexagon::vsub_lo);
853  Register HiSrc = HRI.getSubReg(SrcReg, Hexagon::vsub_hi);
854  BuildMI(MBB, I, DL, get(Hexagon::V6_vcombine), DestReg)
855  .addReg(HiSrc, KillFlag)
856  .addReg(LoSrc, KillFlag);
857  return;
858  }
859  if (Hexagon::HvxQRRegClass.contains(SrcReg, DestReg)) {
860  BuildMI(MBB, I, DL, get(Hexagon::V6_pred_and), DestReg)
861  .addReg(SrcReg)
862  .addReg(SrcReg, KillFlag);
863  return;
864  }
865  if (Hexagon::HvxQRRegClass.contains(SrcReg) &&
866  Hexagon::HvxVRRegClass.contains(DestReg)) {
867  llvm_unreachable("Unimplemented pred to vec");
868  return;
869  }
870  if (Hexagon::HvxQRRegClass.contains(DestReg) &&
871  Hexagon::HvxVRRegClass.contains(SrcReg)) {
872  llvm_unreachable("Unimplemented vec to pred");
873  return;
874  }
875 
876 #ifndef NDEBUG
877  // Show the invalid registers to ease debugging.
878  dbgs() << "Invalid registers for copy in " << printMBBReference(MBB) << ": "
879  << printReg(DestReg, &HRI) << " = " << printReg(SrcReg, &HRI) << '\n';
880 #endif
881  llvm_unreachable("Unimplemented");
882 }
883 
885  MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI,
886  const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const {
887  DebugLoc DL = MBB.findDebugLoc(I);
888  MachineFunction &MF = *MBB.getParent();
889  MachineFrameInfo &MFI = MF.getFrameInfo();
890  unsigned SlotAlign = MFI.getObjectAlignment(FI);
891  unsigned RegAlign = TRI->getSpillAlignment(*RC);
892  unsigned KillFlag = getKillRegState(isKill);
893  bool HasAlloca = MFI.hasVarSizedObjects();
894  const HexagonFrameLowering &HFI = *Subtarget.getFrameLowering();
895 
898  MFI.getObjectSize(FI), SlotAlign);
899 
900  if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {
901  BuildMI(MBB, I, DL, get(Hexagon::S2_storeri_io))
902  .addFrameIndex(FI).addImm(0)
903  .addReg(SrcReg, KillFlag).addMemOperand(MMO);
904  } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {
905  BuildMI(MBB, I, DL, get(Hexagon::S2_storerd_io))
906  .addFrameIndex(FI).addImm(0)
907  .addReg(SrcReg, KillFlag).addMemOperand(MMO);
908  } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {
909  BuildMI(MBB, I, DL, get(Hexagon::STriw_pred))
910  .addFrameIndex(FI).addImm(0)
911  .addReg(SrcReg, KillFlag).addMemOperand(MMO);
912  } else if (Hexagon::ModRegsRegClass.hasSubClassEq(RC)) {
913  BuildMI(MBB, I, DL, get(Hexagon::STriw_ctr))
914  .addFrameIndex(FI).addImm(0)
915  .addReg(SrcReg, KillFlag).addMemOperand(MMO);
916  } else if (Hexagon::HvxQRRegClass.hasSubClassEq(RC)) {
917  BuildMI(MBB, I, DL, get(Hexagon::PS_vstorerq_ai))
918  .addFrameIndex(FI).addImm(0)
919  .addReg(SrcReg, KillFlag).addMemOperand(MMO);
920  } else if (Hexagon::HvxVRRegClass.hasSubClassEq(RC)) {
921  // If there are variable-sized objects, spills will not be aligned.
922  if (HasAlloca)
923  SlotAlign = HFI.getStackAlignment();
924  unsigned Opc = SlotAlign < RegAlign ? Hexagon::V6_vS32Ub_ai
925  : Hexagon::V6_vS32b_ai;
928  MFI.getObjectSize(FI), SlotAlign);
929  BuildMI(MBB, I, DL, get(Opc))
930  .addFrameIndex(FI).addImm(0)
931  .addReg(SrcReg, KillFlag).addMemOperand(MMOA);
932  } else if (Hexagon::HvxWRRegClass.hasSubClassEq(RC)) {
933  // If there are variable-sized objects, spills will not be aligned.
934  if (HasAlloca)
935  SlotAlign = HFI.getStackAlignment();
936  unsigned Opc = SlotAlign < RegAlign ? Hexagon::PS_vstorerwu_ai
937  : Hexagon::PS_vstorerw_ai;
940  MFI.getObjectSize(FI), SlotAlign);
941  BuildMI(MBB, I, DL, get(Opc))
942  .addFrameIndex(FI).addImm(0)
943  .addReg(SrcReg, KillFlag).addMemOperand(MMOA);
944  } else {
945  llvm_unreachable("Unimplemented");
946  }
947 }
948 
950  MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg,
951  int FI, const TargetRegisterClass *RC,
952  const TargetRegisterInfo *TRI) const {
953  DebugLoc DL = MBB.findDebugLoc(I);
954  MachineFunction &MF = *MBB.getParent();
955  MachineFrameInfo &MFI = MF.getFrameInfo();
956  unsigned SlotAlign = MFI.getObjectAlignment(FI);
957  unsigned RegAlign = TRI->getSpillAlignment(*RC);
958  bool HasAlloca = MFI.hasVarSizedObjects();
959  const HexagonFrameLowering &HFI = *Subtarget.getFrameLowering();
960 
963  MFI.getObjectSize(FI), SlotAlign);
964 
965  if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {
966  BuildMI(MBB, I, DL, get(Hexagon::L2_loadri_io), DestReg)
967  .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
968  } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {
969  BuildMI(MBB, I, DL, get(Hexagon::L2_loadrd_io), DestReg)
970  .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
971  } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {
972  BuildMI(MBB, I, DL, get(Hexagon::LDriw_pred), DestReg)
973  .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
974  } else if (Hexagon::ModRegsRegClass.hasSubClassEq(RC)) {
975  BuildMI(MBB, I, DL, get(Hexagon::LDriw_ctr), DestReg)
976  .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
977  } else if (Hexagon::HvxQRRegClass.hasSubClassEq(RC)) {
978  BuildMI(MBB, I, DL, get(Hexagon::PS_vloadrq_ai), DestReg)
979  .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
980  } else if (Hexagon::HvxVRRegClass.hasSubClassEq(RC)) {
981  // If there are variable-sized objects, spills will not be aligned.
982  if (HasAlloca)
983  SlotAlign = HFI.getStackAlignment();
984  unsigned Opc = SlotAlign < RegAlign ? Hexagon::V6_vL32Ub_ai
985  : Hexagon::V6_vL32b_ai;
988  MFI.getObjectSize(FI), SlotAlign);
989  BuildMI(MBB, I, DL, get(Opc), DestReg)
990  .addFrameIndex(FI).addImm(0).addMemOperand(MMOA);
991  } else if (Hexagon::HvxWRRegClass.hasSubClassEq(RC)) {
992  // If there are variable-sized objects, spills will not be aligned.
993  if (HasAlloca)
994  SlotAlign = HFI.getStackAlignment();
995  unsigned Opc = SlotAlign < RegAlign ? Hexagon::PS_vloadrwu_ai
996  : Hexagon::PS_vloadrw_ai;
999  MFI.getObjectSize(FI), SlotAlign);
1000  BuildMI(MBB, I, DL, get(Opc), DestReg)
1001  .addFrameIndex(FI).addImm(0).addMemOperand(MMOA);
1002  } else {
1003  llvm_unreachable("Can't store this register to stack slot");
1004  }
1005 }
1006 
1007 static void getLiveRegsAt(LivePhysRegs &Regs, const MachineInstr &MI) {
1008  const MachineBasicBlock &B = *MI.getParent();
1009  Regs.addLiveOuts(B);
1010  auto E = ++MachineBasicBlock::const_iterator(MI.getIterator()).getReverse();
1011  for (auto I = B.rbegin(); I != E; ++I)
1012  Regs.stepBackward(*I);
1013 }
1014 
1015 /// expandPostRAPseudo - This function is called for all pseudo instructions
1016 /// that remain after register allocation. Many pseudo instructions are
1017 /// created to help register allocation. This is the place to convert them
1018 /// into real instructions. The target can edit MI in place, or it can insert
1019 /// new instructions and erase MI. The function should return true if
1020 /// anything was changed.
1022  MachineBasicBlock &MBB = *MI.getParent();
1023  MachineFunction &MF = *MBB.getParent();
1025  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
1026  DebugLoc DL = MI.getDebugLoc();
1027  unsigned Opc = MI.getOpcode();
1028 
1029  auto RealCirc = [&](unsigned Opc, bool HasImm, unsigned MxOp) {
1030  Register Mx = MI.getOperand(MxOp).getReg();
1031  unsigned CSx = (Mx == Hexagon::M0 ? Hexagon::CS0 : Hexagon::CS1);
1032  BuildMI(MBB, MI, DL, get(Hexagon::A2_tfrrcr), CSx)
1033  .add(MI.getOperand((HasImm ? 5 : 4)));
1034  auto MIB = BuildMI(MBB, MI, DL, get(Opc)).add(MI.getOperand(0))
1035  .add(MI.getOperand(1)).add(MI.getOperand(2)).add(MI.getOperand(3));
1036  if (HasImm)
1037  MIB.add(MI.getOperand(4));
1038  MIB.addReg(CSx, RegState::Implicit);
1039  MBB.erase(MI);
1040  return true;
1041  };
1042 
1043  switch (Opc) {
1044  case TargetOpcode::COPY: {
1045  MachineOperand &MD = MI.getOperand(0);
1046  MachineOperand &MS = MI.getOperand(1);
1048  if (MD.getReg() != MS.getReg() && !MS.isUndef()) {
1049  copyPhysReg(MBB, MI, DL, MD.getReg(), MS.getReg(), MS.isKill());
1050  std::prev(MBBI)->copyImplicitOps(*MBB.getParent(), MI);
1051  }
1052  MBB.erase(MBBI);
1053  return true;
1054  }
1055  case Hexagon::PS_aligna:
1056  BuildMI(MBB, MI, DL, get(Hexagon::A2_andir), MI.getOperand(0).getReg())
1057  .addReg(HRI.getFrameRegister())
1058  .addImm(-MI.getOperand(1).getImm());
1059  MBB.erase(MI);
1060  return true;
1061  case Hexagon::V6_vassignp: {
1062  Register SrcReg = MI.getOperand(1).getReg();
1063  Register DstReg = MI.getOperand(0).getReg();
1064  unsigned Kill = getKillRegState(MI.getOperand(1).isKill());
1065  BuildMI(MBB, MI, DL, get(Hexagon::V6_vcombine), DstReg)
1066  .addReg(HRI.getSubReg(SrcReg, Hexagon::vsub_hi), Kill)
1067  .addReg(HRI.getSubReg(SrcReg, Hexagon::vsub_lo), Kill);
1068  MBB.erase(MI);
1069  return true;
1070  }
1071  case Hexagon::V6_lo: {
1072  Register SrcReg = MI.getOperand(1).getReg();
1073  Register DstReg = MI.getOperand(0).getReg();
1074  Register SrcSubLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo);
1075  copyPhysReg(MBB, MI, DL, DstReg, SrcSubLo, MI.getOperand(1).isKill());
1076  MBB.erase(MI);
1077  MRI.clearKillFlags(SrcSubLo);
1078  return true;
1079  }
1080  case Hexagon::V6_hi: {
1081  Register SrcReg = MI.getOperand(1).getReg();
1082  Register DstReg = MI.getOperand(0).getReg();
1083  Register SrcSubHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi);
1084  copyPhysReg(MBB, MI, DL, DstReg, SrcSubHi, MI.getOperand(1).isKill());
1085  MBB.erase(MI);
1086  MRI.clearKillFlags(SrcSubHi);
1087  return true;
1088  }
1089  case Hexagon::PS_vstorerw_ai:
1090  case Hexagon::PS_vstorerwu_ai: {
1091  bool Aligned = Opc == Hexagon::PS_vstorerw_ai;
1092  Register SrcReg = MI.getOperand(2).getReg();
1093  Register SrcSubHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi);
1094  Register SrcSubLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo);
1095  unsigned NewOpc = Aligned ? Hexagon::V6_vS32b_ai : Hexagon::V6_vS32Ub_ai;
1096  unsigned Offset = HRI.getSpillSize(Hexagon::HvxVRRegClass);
1097 
1098  MachineInstr *MI1New = BuildMI(MBB, MI, DL, get(NewOpc))
1099  .add(MI.getOperand(0))
1100  .addImm(MI.getOperand(1).getImm())
1101  .addReg(SrcSubLo)
1102  .cloneMemRefs(MI);
1103  MI1New->getOperand(0).setIsKill(false);
1104  BuildMI(MBB, MI, DL, get(NewOpc))
1105  .add(MI.getOperand(0))
1106  // The Vectors are indexed in multiples of vector size.
1107  .addImm(MI.getOperand(1).getImm() + Offset)
1108  .addReg(SrcSubHi)
1109  .cloneMemRefs(MI);
1110  MBB.erase(MI);
1111  return true;
1112  }
1113  case Hexagon::PS_vloadrw_ai:
1114  case Hexagon::PS_vloadrwu_ai: {
1115  bool Aligned = Opc == Hexagon::PS_vloadrw_ai;
1116  Register DstReg = MI.getOperand(0).getReg();
1117  unsigned NewOpc = Aligned ? Hexagon::V6_vL32b_ai : Hexagon::V6_vL32Ub_ai;
1118  unsigned Offset = HRI.getSpillSize(Hexagon::HvxVRRegClass);
1119 
1120  MachineInstr *MI1New = BuildMI(MBB, MI, DL, get(NewOpc),
1121  HRI.getSubReg(DstReg, Hexagon::vsub_lo))
1122  .add(MI.getOperand(1))
1123  .addImm(MI.getOperand(2).getImm())
1124  .cloneMemRefs(MI);
1125  MI1New->getOperand(1).setIsKill(false);
1126  BuildMI(MBB, MI, DL, get(NewOpc), HRI.getSubReg(DstReg, Hexagon::vsub_hi))
1127  .add(MI.getOperand(1))
1128  // The Vectors are indexed in multiples of vector size.
1129  .addImm(MI.getOperand(2).getImm() + Offset)
1130  .cloneMemRefs(MI);
1131  MBB.erase(MI);
1132  return true;
1133  }
1134  case Hexagon::PS_true: {
1135  Register Reg = MI.getOperand(0).getReg();
1136  BuildMI(MBB, MI, DL, get(Hexagon::C2_orn), Reg)
1137  .addReg(Reg, RegState::Undef)
1138  .addReg(Reg, RegState::Undef);
1139  MBB.erase(MI);
1140  return true;
1141  }
1142  case Hexagon::PS_false: {
1143  Register Reg = MI.getOperand(0).getReg();
1144  BuildMI(MBB, MI, DL, get(Hexagon::C2_andn), Reg)
1145  .addReg(Reg, RegState::Undef)
1146  .addReg(Reg, RegState::Undef);
1147  MBB.erase(MI);
1148  return true;
1149  }
1150  case Hexagon::PS_qtrue: {
1151  BuildMI(MBB, MI, DL, get(Hexagon::V6_veqw), MI.getOperand(0).getReg())
1152  .addReg(Hexagon::V0, RegState::Undef)
1153  .addReg(Hexagon::V0, RegState::Undef);
1154  MBB.erase(MI);
1155  return true;
1156  }
1157  case Hexagon::PS_qfalse: {
1158  BuildMI(MBB, MI, DL, get(Hexagon::V6_vgtw), MI.getOperand(0).getReg())
1159  .addReg(Hexagon::V0, RegState::Undef)
1160  .addReg(Hexagon::V0, RegState::Undef);
1161  MBB.erase(MI);
1162  return true;
1163  }
1164  case Hexagon::PS_vdd0: {
1165  Register Vd = MI.getOperand(0).getReg();
1166  BuildMI(MBB, MI, DL, get(Hexagon::V6_vsubw_dv), Vd)
1167  .addReg(Vd, RegState::Undef)
1168  .addReg(Vd, RegState::Undef);
1169  MBB.erase(MI);
1170  return true;
1171  }
1172  case Hexagon::PS_vmulw: {
1173  // Expand a 64-bit vector multiply into 2 32-bit scalar multiplies.
1174  Register DstReg = MI.getOperand(0).getReg();
1175  Register Src1Reg = MI.getOperand(1).getReg();
1176  Register Src2Reg = MI.getOperand(2).getReg();
1177  Register Src1SubHi = HRI.getSubReg(Src1Reg, Hexagon::isub_hi);
1178  Register Src1SubLo = HRI.getSubReg(Src1Reg, Hexagon::isub_lo);
1179  Register Src2SubHi = HRI.getSubReg(Src2Reg, Hexagon::isub_hi);
1180  Register Src2SubLo = HRI.getSubReg(Src2Reg, Hexagon::isub_lo);
1181  BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_mpyi),
1182  HRI.getSubReg(DstReg, Hexagon::isub_hi))
1183  .addReg(Src1SubHi)
1184  .addReg(Src2SubHi);
1185  BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_mpyi),
1186  HRI.getSubReg(DstReg, Hexagon::isub_lo))
1187  .addReg(Src1SubLo)
1188  .addReg(Src2SubLo);
1189  MBB.erase(MI);
1190  MRI.clearKillFlags(Src1SubHi);
1191  MRI.clearKillFlags(Src1SubLo);
1192  MRI.clearKillFlags(Src2SubHi);
1193  MRI.clearKillFlags(Src2SubLo);
1194  return true;
1195  }
1196  case Hexagon::PS_vmulw_acc: {
1197  // Expand 64-bit vector multiply with addition into 2 scalar multiplies.
1198  Register DstReg = MI.getOperand(0).getReg();
1199  Register Src1Reg = MI.getOperand(1).getReg();
1200  Register Src2Reg = MI.getOperand(2).getReg();
1201  Register Src3Reg = MI.getOperand(3).getReg();
1202  Register Src1SubHi = HRI.getSubReg(Src1Reg, Hexagon::isub_hi);
1203  Register Src1SubLo = HRI.getSubReg(Src1Reg, Hexagon::isub_lo);
1204  Register Src2SubHi = HRI.getSubReg(Src2Reg, Hexagon::isub_hi);
1205  Register Src2SubLo = HRI.getSubReg(Src2Reg, Hexagon::isub_lo);
1206  Register Src3SubHi = HRI.getSubReg(Src3Reg, Hexagon::isub_hi);
1207  Register Src3SubLo = HRI.getSubReg(Src3Reg, Hexagon::isub_lo);
1208  BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_maci),
1209  HRI.getSubReg(DstReg, Hexagon::isub_hi))
1210  .addReg(Src1SubHi)
1211  .addReg(Src2SubHi)
1212  .addReg(Src3SubHi);
1213  BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_maci),
1214  HRI.getSubReg(DstReg, Hexagon::isub_lo))
1215  .addReg(Src1SubLo)
1216  .addReg(Src2SubLo)
1217  .addReg(Src3SubLo);
1218  MBB.erase(MI);
1219  MRI.clearKillFlags(Src1SubHi);
1220  MRI.clearKillFlags(Src1SubLo);
1221  MRI.clearKillFlags(Src2SubHi);
1222  MRI.clearKillFlags(Src2SubLo);
1223  MRI.clearKillFlags(Src3SubHi);
1224  MRI.clearKillFlags(Src3SubLo);
1225  return true;
1226  }
1227  case Hexagon::PS_pselect: {
1228  const MachineOperand &Op0 = MI.getOperand(0);
1229  const MachineOperand &Op1 = MI.getOperand(1);
1230  const MachineOperand &Op2 = MI.getOperand(2);
1231  const MachineOperand &Op3 = MI.getOperand(3);
1232  Register Rd = Op0.getReg();
1233  Register Pu = Op1.getReg();
1234  Register Rs = Op2.getReg();
1235  Register Rt = Op3.getReg();
1236  DebugLoc DL = MI.getDebugLoc();
1237  unsigned K1 = getKillRegState(Op1.isKill());
1238  unsigned K2 = getKillRegState(Op2.isKill());
1239  unsigned K3 = getKillRegState(Op3.isKill());
1240  if (Rd != Rs)
1241  BuildMI(MBB, MI, DL, get(Hexagon::A2_tfrpt), Rd)
1242  .addReg(Pu, (Rd == Rt) ? K1 : 0)
1243  .addReg(Rs, K2);
1244  if (Rd != Rt)
1245  BuildMI(MBB, MI, DL, get(Hexagon::A2_tfrpf), Rd)
1246  .addReg(Pu, K1)
1247  .addReg(Rt, K3);
1248  MBB.erase(MI);
1249  return true;
1250  }
1251  case Hexagon::PS_vselect: {
1252  const MachineOperand &Op0 = MI.getOperand(0);
1253  const MachineOperand &Op1 = MI.getOperand(1);
1254  const MachineOperand &Op2 = MI.getOperand(2);
1255  const MachineOperand &Op3 = MI.getOperand(3);
1256  LivePhysRegs LiveAtMI(HRI);
1257  getLiveRegsAt(LiveAtMI, MI);
1258  bool IsDestLive = !LiveAtMI.available(MRI, Op0.getReg());
1259  Register PReg = Op1.getReg();
1260  assert(Op1.getSubReg() == 0);
1261  unsigned PState = getRegState(Op1);
1262 
1263  if (Op0.getReg() != Op2.getReg()) {
1264  unsigned S = Op0.getReg() != Op3.getReg() ? PState & ~RegState::Kill
1265  : PState;
1266  auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vcmov))
1267  .add(Op0)
1268  .addReg(PReg, S)
1269  .add(Op2);
1270  if (IsDestLive)
1271  T.addReg(Op0.getReg(), RegState::Implicit);
1272  IsDestLive = true;
1273  }
1274  if (Op0.getReg() != Op3.getReg()) {
1275  auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vncmov))
1276  .add(Op0)
1277  .addReg(PReg, PState)
1278  .add(Op3);
1279  if (IsDestLive)
1280  T.addReg(Op0.getReg(), RegState::Implicit);
1281  }
1282  MBB.erase(MI);
1283  return true;
1284  }
1285  case Hexagon::PS_wselect: {
1286  MachineOperand &Op0 = MI.getOperand(0);
1287  MachineOperand &Op1 = MI.getOperand(1);
1288  MachineOperand &Op2 = MI.getOperand(2);
1289  MachineOperand &Op3 = MI.getOperand(3);
1290  LivePhysRegs LiveAtMI(HRI);
1291  getLiveRegsAt(LiveAtMI, MI);
1292  bool IsDestLive = !LiveAtMI.available(MRI, Op0.getReg());
1293  Register PReg = Op1.getReg();
1294  assert(Op1.getSubReg() == 0);
1295  unsigned PState = getRegState(Op1);
1296 
1297  if (Op0.getReg() != Op2.getReg()) {
1298  unsigned S = Op0.getReg() != Op3.getReg() ? PState & ~RegState::Kill
1299  : PState;
1300  Register SrcLo = HRI.getSubReg(Op2.getReg(), Hexagon::vsub_lo);
1301  Register SrcHi = HRI.getSubReg(Op2.getReg(), Hexagon::vsub_hi);
1302  auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vccombine))
1303  .add(Op0)
1304  .addReg(PReg, S)
1305  .addReg(SrcHi)
1306  .addReg(SrcLo);
1307  if (IsDestLive)
1308  T.addReg(Op0.getReg(), RegState::Implicit);
1309  IsDestLive = true;
1310  }
1311  if (Op0.getReg() != Op3.getReg()) {
1312  Register SrcLo = HRI.getSubReg(Op3.getReg(), Hexagon::vsub_lo);
1313  Register SrcHi = HRI.getSubReg(Op3.getReg(), Hexagon::vsub_hi);
1314  auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vnccombine))
1315  .add(Op0)
1316  .addReg(PReg, PState)
1317  .addReg(SrcHi)
1318  .addReg(SrcLo);
1319  if (IsDestLive)
1320  T.addReg(Op0.getReg(), RegState::Implicit);
1321  }
1322  MBB.erase(MI);
1323  return true;
1324  }
1325 
1326  case Hexagon::PS_crash: {
1327  // Generate a misaligned load that is guaranteed to cause a crash.
1328  class CrashPseudoSourceValue : public PseudoSourceValue {
1329  public:
1330  CrashPseudoSourceValue(const TargetInstrInfo &TII)
1331  : PseudoSourceValue(TargetCustom, TII) {}
1332 
1333  bool isConstant(const MachineFrameInfo *) const override {
1334  return false;
1335  }
1336  bool isAliased(const MachineFrameInfo *) const override {
1337  return false;
1338  }
1339  bool mayAlias(const MachineFrameInfo *) const override {
1340  return false;
1341  }
1342  void printCustom(raw_ostream &OS) const override {
1343  OS << "MisalignedCrash";
1344  }
1345  };
1346 
1347  static const CrashPseudoSourceValue CrashPSV(*this);
1349  MachinePointerInfo(&CrashPSV),
1351  BuildMI(MBB, MI, DL, get(Hexagon::PS_loadrdabs), Hexagon::D13)
1352  .addImm(0xBADC0FEE) // Misaligned load.
1353  .addMemOperand(MMO);
1354  MBB.erase(MI);
1355  return true;
1356  }
1357 
1358  case Hexagon::PS_tailcall_i:
1359  MI.setDesc(get(Hexagon::J2_jump));
1360  return true;
1361  case Hexagon::PS_tailcall_r:
1362  case Hexagon::PS_jmpret:
1363  MI.setDesc(get(Hexagon::J2_jumpr));
1364  return true;
1365  case Hexagon::PS_jmprett:
1366  MI.setDesc(get(Hexagon::J2_jumprt));
1367  return true;
1368  case Hexagon::PS_jmpretf:
1369  MI.setDesc(get(Hexagon::J2_jumprf));
1370  return true;
1371  case Hexagon::PS_jmprettnewpt:
1372  MI.setDesc(get(Hexagon::J2_jumprtnewpt));
1373  return true;
1374  case Hexagon::PS_jmpretfnewpt:
1375  MI.setDesc(get(Hexagon::J2_jumprfnewpt));
1376  return true;
1377  case Hexagon::PS_jmprettnew:
1378  MI.setDesc(get(Hexagon::J2_jumprtnew));
1379  return true;
1380  case Hexagon::PS_jmpretfnew:
1381  MI.setDesc(get(Hexagon::J2_jumprfnew));
1382  return true;
1383 
1384  case Hexagon::PS_loadrub_pci:
1385  return RealCirc(Hexagon::L2_loadrub_pci, /*HasImm*/true, /*MxOp*/4);
1386  case Hexagon::PS_loadrb_pci:
1387  return RealCirc(Hexagon::L2_loadrb_pci, /*HasImm*/true, /*MxOp*/4);
1388  case Hexagon::PS_loadruh_pci:
1389  return RealCirc(Hexagon::L2_loadruh_pci, /*HasImm*/true, /*MxOp*/4);
1390  case Hexagon::PS_loadrh_pci:
1391  return RealCirc(Hexagon::L2_loadrh_pci, /*HasImm*/true, /*MxOp*/4);
1392  case Hexagon::PS_loadri_pci:
1393  return RealCirc(Hexagon::L2_loadri_pci, /*HasImm*/true, /*MxOp*/4);
1394  case Hexagon::PS_loadrd_pci:
1395  return RealCirc(Hexagon::L2_loadrd_pci, /*HasImm*/true, /*MxOp*/4);
1396  case Hexagon::PS_loadrub_pcr:
1397  return RealCirc(Hexagon::L2_loadrub_pcr, /*HasImm*/false, /*MxOp*/3);
1398  case Hexagon::PS_loadrb_pcr:
1399  return RealCirc(Hexagon::L2_loadrb_pcr, /*HasImm*/false, /*MxOp*/3);
1400  case Hexagon::PS_loadruh_pcr:
1401  return RealCirc(Hexagon::L2_loadruh_pcr, /*HasImm*/false, /*MxOp*/3);
1402  case Hexagon::PS_loadrh_pcr:
1403  return RealCirc(Hexagon::L2_loadrh_pcr, /*HasImm*/false, /*MxOp*/3);
1404  case Hexagon::PS_loadri_pcr:
1405  return RealCirc(Hexagon::L2_loadri_pcr, /*HasImm*/false, /*MxOp*/3);
1406  case Hexagon::PS_loadrd_pcr:
1407  return RealCirc(Hexagon::L2_loadrd_pcr, /*HasImm*/false, /*MxOp*/3);
1408  case Hexagon::PS_storerb_pci:
1409  return RealCirc(Hexagon::S2_storerb_pci, /*HasImm*/true, /*MxOp*/3);
1410  case Hexagon::PS_storerh_pci:
1411  return RealCirc(Hexagon::S2_storerh_pci, /*HasImm*/true, /*MxOp*/3);
1412  case Hexagon::PS_storerf_pci:
1413  return RealCirc(Hexagon::S2_storerf_pci, /*HasImm*/true, /*MxOp*/3);
1414  case Hexagon::PS_storeri_pci:
1415  return RealCirc(Hexagon::S2_storeri_pci, /*HasImm*/true, /*MxOp*/3);
1416  case Hexagon::PS_storerd_pci:
1417  return RealCirc(Hexagon::S2_storerd_pci, /*HasImm*/true, /*MxOp*/3);
1418  case Hexagon::PS_storerb_pcr:
1419  return RealCirc(Hexagon::S2_storerb_pcr, /*HasImm*/false, /*MxOp*/2);
1420  case Hexagon::PS_storerh_pcr:
1421  return RealCirc(Hexagon::S2_storerh_pcr, /*HasImm*/false, /*MxOp*/2);
1422  case Hexagon::PS_storerf_pcr:
1423  return RealCirc(Hexagon::S2_storerf_pcr, /*HasImm*/false, /*MxOp*/2);
1424  case Hexagon::PS_storeri_pcr:
1425  return RealCirc(Hexagon::S2_storeri_pcr, /*HasImm*/false, /*MxOp*/2);
1426  case Hexagon::PS_storerd_pcr:
1427  return RealCirc(Hexagon::S2_storerd_pcr, /*HasImm*/false, /*MxOp*/2);
1428  }
1429 
1430  return false;
1431 }
1432 
1435  MachineBasicBlock &MBB = *MI.getParent();
1436  const DebugLoc &DL = MI.getDebugLoc();
1437  unsigned Opc = MI.getOpcode();
1439 
1440  switch (Opc) {
1441  case Hexagon::V6_vgathermh_pseudo:
1442  First = BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermh))
1443  .add(MI.getOperand(1))
1444  .add(MI.getOperand(2))
1445  .add(MI.getOperand(3));
1446  BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1447  .add(MI.getOperand(0))
1448  .addImm(0)
1449  .addReg(Hexagon::VTMP);
1450  MBB.erase(MI);
1451  return First.getInstrIterator();
1452 
1453  case Hexagon::V6_vgathermw_pseudo:
1454  First = BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermw))
1455  .add(MI.getOperand(1))
1456  .add(MI.getOperand(2))
1457  .add(MI.getOperand(3));
1458  BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1459  .add(MI.getOperand(0))
1460  .addImm(0)
1461  .addReg(Hexagon::VTMP);
1462  MBB.erase(MI);
1463  return First.getInstrIterator();
1464 
1465  case Hexagon::V6_vgathermhw_pseudo:
1466  First = BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermhw))
1467  .add(MI.getOperand(1))
1468  .add(MI.getOperand(2))
1469  .add(MI.getOperand(3));
1470  BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1471  .add(MI.getOperand(0))
1472  .addImm(0)
1473  .addReg(Hexagon::VTMP);
1474  MBB.erase(MI);
1475  return First.getInstrIterator();
1476 
1477  case Hexagon::V6_vgathermhq_pseudo:
1478  First = BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermhq))
1479  .add(MI.getOperand(1))
1480  .add(MI.getOperand(2))
1481  .add(MI.getOperand(3))
1482  .add(MI.getOperand(4));
1483  BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1484  .add(MI.getOperand(0))
1485  .addImm(0)
1486  .addReg(Hexagon::VTMP);
1487  MBB.erase(MI);
1488  return First.getInstrIterator();
1489 
1490  case Hexagon::V6_vgathermwq_pseudo:
1491  First = BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermwq))
1492  .add(MI.getOperand(1))
1493  .add(MI.getOperand(2))
1494  .add(MI.getOperand(3))
1495  .add(MI.getOperand(4));
1496  BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1497  .add(MI.getOperand(0))
1498  .addImm(0)
1499  .addReg(Hexagon::VTMP);
1500  MBB.erase(MI);
1501  return First.getInstrIterator();
1502 
1503  case Hexagon::V6_vgathermhwq_pseudo:
1504  First = BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermhwq))
1505  .add(MI.getOperand(1))
1506  .add(MI.getOperand(2))
1507  .add(MI.getOperand(3))
1508  .add(MI.getOperand(4));
1509  BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1510  .add(MI.getOperand(0))
1511  .addImm(0)
1512  .addReg(Hexagon::VTMP);
1513  MBB.erase(MI);
1514  return First.getInstrIterator();
1515  }
1516 
1517  return MI.getIterator();
1518 }
1519 
1520 // We indicate that we want to reverse the branch by
1521 // inserting the reversed branching opcode.
1523  SmallVectorImpl<MachineOperand> &Cond) const {
1524  if (Cond.empty())
1525  return true;
1526  assert(Cond[0].isImm() && "First entry in the cond vector not imm-val");
1527  unsigned opcode = Cond[0].getImm();
1528  //unsigned temp;
1529  assert(get(opcode).isBranch() && "Should be a branching condition.");
1530  if (isEndLoopN(opcode))
1531  return true;
1532  unsigned NewOpcode = getInvertedPredicatedOpcode(opcode);
1533  Cond[0].setImm(NewOpcode);
1534  return false;
1535 }
1536 
1539  DebugLoc DL;
1540  BuildMI(MBB, MI, DL, get(Hexagon::A2_nop));
1541 }
1542 
1544  return getAddrMode(MI) == HexagonII::PostInc;
1545 }
1546 
1547 // Returns true if an instruction is predicated irrespective of the predicate
1548 // sense. For example, all of the following will return true.
1549 // if (p0) R1 = add(R2, R3)
1550 // if (!p0) R1 = add(R2, R3)
1551 // if (p0.new) R1 = add(R2, R3)
1552 // if (!p0.new) R1 = add(R2, R3)
1553 // Note: New-value stores are not included here as in the current
1554 // implementation, we don't need to check their predicate sense.
1556  const uint64_t F = MI.getDesc().TSFlags;
1558 }
1559 
1561  MachineInstr &MI, ArrayRef<MachineOperand> Cond) const {
1562  if (Cond.empty() || isNewValueJump(Cond[0].getImm()) ||
1563  isEndLoopN(Cond[0].getImm())) {
1564  LLVM_DEBUG(dbgs() << "\nCannot predicate:"; MI.dump(););
1565  return false;
1566  }
1567  int Opc = MI.getOpcode();
1568  assert (isPredicable(MI) && "Expected predicable instruction");
1569  bool invertJump = predOpcodeHasNot(Cond);
1570 
1571  // We have to predicate MI "in place", i.e. after this function returns,
1572  // MI will need to be transformed into a predicated form. To avoid com-
1573  // plicated manipulations with the operands (handling tied operands,
1574  // etc.), build a new temporary instruction, then overwrite MI with it.
1575 
1576  MachineBasicBlock &B = *MI.getParent();
1577  DebugLoc DL = MI.getDebugLoc();
1578  unsigned PredOpc = getCondOpcode(Opc, invertJump);
1579  MachineInstrBuilder T = BuildMI(B, MI, DL, get(PredOpc));
1580  unsigned NOp = 0, NumOps = MI.getNumOperands();
1581  while (NOp < NumOps) {
1582  MachineOperand &Op = MI.getOperand(NOp);
1583  if (!Op.isReg() || !Op.isDef() || Op.isImplicit())
1584  break;
1585  T.add(Op);
1586  NOp++;
1587  }
1588 
1589  unsigned PredReg, PredRegPos, PredRegFlags;
1590  bool GotPredReg = getPredReg(Cond, PredReg, PredRegPos, PredRegFlags);
1591  (void)GotPredReg;
1592  assert(GotPredReg);
1593  T.addReg(PredReg, PredRegFlags);
1594  while (NOp < NumOps)
1595  T.add(MI.getOperand(NOp++));
1596 
1597  MI.setDesc(get(PredOpc));
1598  while (unsigned n = MI.getNumOperands())
1599  MI.RemoveOperand(n-1);
1600  for (unsigned i = 0, n = T->getNumOperands(); i < n; ++i)
1601  MI.addOperand(T->getOperand(i));
1602 
1604  B.erase(TI);
1605 
1607  MRI.clearKillFlags(PredReg);
1608  return true;
1609 }
1610 
1612  ArrayRef<MachineOperand> Pred2) const {
1613  // TODO: Fix this
1614  return false;
1615 }
1616 
1618  std::vector<MachineOperand> &Pred) const {
1619  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
1620 
1621  for (unsigned oper = 0; oper < MI.getNumOperands(); ++oper) {
1622  MachineOperand MO = MI.getOperand(oper);
1623  if (MO.isReg()) {
1624  if (!MO.isDef())
1625  continue;
1626  const TargetRegisterClass* RC = HRI.getMinimalPhysRegClass(MO.getReg());
1627  if (RC == &Hexagon::PredRegsRegClass) {
1628  Pred.push_back(MO);
1629  return true;
1630  }
1631  continue;
1632  } else if (MO.isRegMask()) {
1633  for (unsigned PR : Hexagon::PredRegsRegClass) {
1634  if (!MI.modifiesRegister(PR, &HRI))
1635  continue;
1636  Pred.push_back(MO);
1637  return true;
1638  }
1639  }
1640  }
1641  return false;
1642 }
1643 
1645  if (!MI.getDesc().isPredicable())
1646  return false;
1647 
1648  if (MI.isCall() || isTailCall(MI)) {
1649  if (!Subtarget.usePredicatedCalls())
1650  return false;
1651  }
1652 
1653  // HVX loads are not predicable on v60, but are on v62.
1654  if (!Subtarget.hasV62Ops()) {
1655  switch (MI.getOpcode()) {
1656  case Hexagon::V6_vL32b_ai:
1657  case Hexagon::V6_vL32b_pi:
1658  case Hexagon::V6_vL32b_ppu:
1659  case Hexagon::V6_vL32b_cur_ai:
1660  case Hexagon::V6_vL32b_cur_pi:
1661  case Hexagon::V6_vL32b_cur_ppu:
1662  case Hexagon::V6_vL32b_nt_ai:
1663  case Hexagon::V6_vL32b_nt_pi:
1664  case Hexagon::V6_vL32b_nt_ppu:
1665  case Hexagon::V6_vL32b_tmp_ai:
1666  case Hexagon::V6_vL32b_tmp_pi:
1667  case Hexagon::V6_vL32b_tmp_ppu:
1668  case Hexagon::V6_vL32b_nt_cur_ai:
1669  case Hexagon::V6_vL32b_nt_cur_pi:
1670  case Hexagon::V6_vL32b_nt_cur_ppu:
1671  case Hexagon::V6_vL32b_nt_tmp_ai:
1672  case Hexagon::V6_vL32b_nt_tmp_pi:
1673  case Hexagon::V6_vL32b_nt_tmp_ppu:
1674  return false;
1675  }
1676  }
1677  return true;
1678 }
1679 
1681  const MachineBasicBlock *MBB,
1682  const MachineFunction &MF) const {
1683  // Debug info is never a scheduling boundary. It's necessary to be explicit
1684  // due to the special treatment of IT instructions below, otherwise a
1685  // dbg_value followed by an IT will result in the IT instruction being
1686  // considered a scheduling hazard, which is wrong. It should be the actual
1687  // instruction preceding the dbg_value instruction(s), just like it is
1688  // when debug info is not present.
1689  if (MI.isDebugInstr())
1690  return false;
1691 
1692  // Throwing call is a boundary.
1693  if (MI.isCall()) {
1694  // Don't mess around with no return calls.
1695  if (doesNotReturn(MI))
1696  return true;
1697  // If any of the block's successors is a landing pad, this could be a
1698  // throwing call.
1699  for (auto I : MBB->successors())
1700  if (I->isEHPad())
1701  return true;
1702  }
1703 
1704  // Terminators and labels can't be scheduled around.
1705  if (MI.getDesc().isTerminator() || MI.isPosition())
1706  return true;
1707 
1708  if (MI.isInlineAsm() && !ScheduleInlineAsm)
1709  return true;
1710 
1711  return false;
1712 }
1713 
1714 /// Measure the specified inline asm to determine an approximation of its
1715 /// length.
1716 /// Comments (which run till the next SeparatorString or newline) do not
1717 /// count as an instruction.
1718 /// Any other non-whitespace text is considered an instruction, with
1719 /// multiple instructions separated by SeparatorString or newlines.
1720 /// Variable-length instructions are not handled here; this function
1721 /// may be overloaded in the target code to do that.
1722 /// Hexagon counts the number of ##'s and adjust for that many
1723 /// constant exenders.
1724 unsigned HexagonInstrInfo::getInlineAsmLength(const char *Str,
1725  const MCAsmInfo &MAI,
1726  const TargetSubtargetInfo *STI) const {
1727  StringRef AStr(Str);
1728  // Count the number of instructions in the asm.
1729  bool atInsnStart = true;
1730  unsigned Length = 0;
1731  const unsigned MaxInstLength = MAI.getMaxInstLength(STI);
1732  for (; *Str; ++Str) {
1733  if (*Str == '\n' || strncmp(Str, MAI.getSeparatorString(),
1734  strlen(MAI.getSeparatorString())) == 0)
1735  atInsnStart = true;
1736  if (atInsnStart && !std::isspace(static_cast<unsigned char>(*Str))) {
1737  Length += MaxInstLength;
1738  atInsnStart = false;
1739  }
1740  if (atInsnStart && strncmp(Str, MAI.getCommentString().data(),
1741  MAI.getCommentString().size()) == 0)
1742  atInsnStart = false;
1743  }
1744 
1745  // Add to size number of constant extenders seen * 4.
1746  StringRef Occ("##");
1747  Length += AStr.count(Occ)*4;
1748  return Length;
1749 }
1750 
1753  const InstrItineraryData *II, const ScheduleDAG *DAG) const {
1754  if (UseDFAHazardRec)
1755  return new HexagonHazardRecognizer(II, this, Subtarget);
1757 }
1758 
1759 /// For a comparison instruction, return the source registers in
1760 /// \p SrcReg and \p SrcReg2 if having two register operands, and the value it
1761 /// compares against in CmpValue. Return true if the comparison instruction
1762 /// can be analyzed.
1763 bool HexagonInstrInfo::analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
1764  unsigned &SrcReg2, int &Mask,
1765  int &Value) const {
1766  unsigned Opc = MI.getOpcode();
1767 
1768  // Set mask and the first source register.
1769  switch (Opc) {
1770  case Hexagon::C2_cmpeq:
1771  case Hexagon::C2_cmpeqp:
1772  case Hexagon::C2_cmpgt:
1773  case Hexagon::C2_cmpgtp:
1774  case Hexagon::C2_cmpgtu:
1775  case Hexagon::C2_cmpgtup:
1776  case Hexagon::C4_cmpneq:
1777  case Hexagon::C4_cmplte:
1778  case Hexagon::C4_cmplteu:
1779  case Hexagon::C2_cmpeqi:
1780  case Hexagon::C2_cmpgti:
1781  case Hexagon::C2_cmpgtui:
1782  case Hexagon::C4_cmpneqi:
1783  case Hexagon::C4_cmplteui:
1784  case Hexagon::C4_cmpltei:
1785  SrcReg = MI.getOperand(1).getReg();
1786  Mask = ~0;
1787  break;
1788  case Hexagon::A4_cmpbeq:
1789  case Hexagon::A4_cmpbgt:
1790  case Hexagon::A4_cmpbgtu:
1791  case Hexagon::A4_cmpbeqi:
1792  case Hexagon::A4_cmpbgti:
1793  case Hexagon::A4_cmpbgtui:
1794  SrcReg = MI.getOperand(1).getReg();
1795  Mask = 0xFF;
1796  break;
1797  case Hexagon::A4_cmpheq:
1798  case Hexagon::A4_cmphgt:
1799  case Hexagon::A4_cmphgtu:
1800  case Hexagon::A4_cmpheqi:
1801  case Hexagon::A4_cmphgti:
1802  case Hexagon::A4_cmphgtui:
1803  SrcReg = MI.getOperand(1).getReg();
1804  Mask = 0xFFFF;
1805  break;
1806  }
1807 
1808  // Set the value/second source register.
1809  switch (Opc) {
1810  case Hexagon::C2_cmpeq:
1811  case Hexagon::C2_cmpeqp:
1812  case Hexagon::C2_cmpgt:
1813  case Hexagon::C2_cmpgtp:
1814  case Hexagon::C2_cmpgtu:
1815  case Hexagon::C2_cmpgtup:
1816  case Hexagon::A4_cmpbeq:
1817  case Hexagon::A4_cmpbgt:
1818  case Hexagon::A4_cmpbgtu:
1819  case Hexagon::A4_cmpheq:
1820  case Hexagon::A4_cmphgt:
1821  case Hexagon::A4_cmphgtu:
1822  case Hexagon::C4_cmpneq:
1823  case Hexagon::C4_cmplte:
1824  case Hexagon::C4_cmplteu:
1825  SrcReg2 = MI.getOperand(2).getReg();
1826  return true;
1827 
1828  case Hexagon::C2_cmpeqi:
1829  case Hexagon::C2_cmpgtui:
1830  case Hexagon::C2_cmpgti:
1831  case Hexagon::C4_cmpneqi:
1832  case Hexagon::C4_cmplteui:
1833  case Hexagon::C4_cmpltei:
1834  case Hexagon::A4_cmpbeqi:
1835  case Hexagon::A4_cmpbgti:
1836  case Hexagon::A4_cmpbgtui:
1837  case Hexagon::A4_cmpheqi:
1838  case Hexagon::A4_cmphgti:
1839  case Hexagon::A4_cmphgtui: {
1840  SrcReg2 = 0;
1841  const MachineOperand &Op2 = MI.getOperand(2);
1842  if (!Op2.isImm())
1843  return false;
1844  Value = MI.getOperand(2).getImm();
1845  return true;
1846  }
1847  }
1848 
1849  return false;
1850 }
1851 
1853  const MachineInstr &MI,
1854  unsigned *PredCost) const {
1855  return getInstrTimingClassLatency(ItinData, MI);
1856 }
1857 
1859  const TargetSubtargetInfo &STI) const {
1860  const InstrItineraryData *II = STI.getInstrItineraryData();
1861  return static_cast<const HexagonSubtarget&>(STI).createDFAPacketizer(II);
1862 }
1863 
1864 // Inspired by this pair:
1865 // %r13 = L2_loadri_io %r29, 136; mem:LD4[FixedStack0]
1866 // S2_storeri_io %r29, 132, killed %r1; flags: mem:ST4[FixedStack1]
1867 // Currently AA considers the addresses in these instructions to be aliasing.
1869  const MachineInstr &MIa, const MachineInstr &MIb) const {
1870  if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects() ||
1872  return false;
1873 
1874  // Instructions that are pure loads, not loads and stores like memops are not
1875  // dependent.
1876  if (MIa.mayLoad() && !isMemOp(MIa) && MIb.mayLoad() && !isMemOp(MIb))
1877  return true;
1878 
1879  // Get the base register in MIa.
1880  unsigned BasePosA, OffsetPosA;
1881  if (!getBaseAndOffsetPosition(MIa, BasePosA, OffsetPosA))
1882  return false;
1883  const MachineOperand &BaseA = MIa.getOperand(BasePosA);
1884  Register BaseRegA = BaseA.getReg();
1885  unsigned BaseSubA = BaseA.getSubReg();
1886 
1887  // Get the base register in MIb.
1888  unsigned BasePosB, OffsetPosB;
1889  if (!getBaseAndOffsetPosition(MIb, BasePosB, OffsetPosB))
1890  return false;
1891  const MachineOperand &BaseB = MIb.getOperand(BasePosB);
1892  Register BaseRegB = BaseB.getReg();
1893  unsigned BaseSubB = BaseB.getSubReg();
1894 
1895  if (BaseRegA != BaseRegB || BaseSubA != BaseSubB)
1896  return false;
1897 
1898  // Get the access sizes.
1899  unsigned SizeA = getMemAccessSize(MIa);
1900  unsigned SizeB = getMemAccessSize(MIb);
1901 
1902  // Get the offsets. Handle immediates only for now.
1903  const MachineOperand &OffA = MIa.getOperand(OffsetPosA);
1904  const MachineOperand &OffB = MIb.getOperand(OffsetPosB);
1905  if (!MIa.getOperand(OffsetPosA).isImm() ||
1906  !MIb.getOperand(OffsetPosB).isImm())
1907  return false;
1908  int OffsetA = isPostIncrement(MIa) ? 0 : OffA.getImm();
1909  int OffsetB = isPostIncrement(MIb) ? 0 : OffB.getImm();
1910 
1911  // This is a mem access with the same base register and known offsets from it.
1912  // Reason about it.
1913  if (OffsetA > OffsetB) {
1914  uint64_t OffDiff = (uint64_t)((int64_t)OffsetA - (int64_t)OffsetB);
1915  return SizeB <= OffDiff;
1916  }
1917  if (OffsetA < OffsetB) {
1918  uint64_t OffDiff = (uint64_t)((int64_t)OffsetB - (int64_t)OffsetA);
1919  return SizeA <= OffDiff;
1920  }
1921 
1922  return false;
1923 }
1924 
1925 /// If the instruction is an increment of a constant value, return the amount.
1927  int &Value) const {
1928  if (isPostIncrement(MI)) {
1929  unsigned BasePos = 0, OffsetPos = 0;
1930  if (!getBaseAndOffsetPosition(MI, BasePos, OffsetPos))
1931  return false;
1932  const MachineOperand &OffsetOp = MI.getOperand(OffsetPos);
1933  if (OffsetOp.isImm()) {
1934  Value = OffsetOp.getImm();
1935  return true;
1936  }
1937  } else if (MI.getOpcode() == Hexagon::A2_addi) {
1938  const MachineOperand &AddOp = MI.getOperand(2);
1939  if (AddOp.isImm()) {
1940  Value = AddOp.getImm();
1941  return true;
1942  }
1943  }
1944 
1945  return false;
1946 }
1947 
1948 std::pair<unsigned, unsigned>
1950  return std::make_pair(TF & ~HexagonII::MO_Bitmasks,
1951  TF & HexagonII::MO_Bitmasks);
1952 }
1953 
1956  using namespace HexagonII;
1957 
1958  static const std::pair<unsigned, const char*> Flags[] = {
1959  {MO_PCREL, "hexagon-pcrel"},
1960  {MO_GOT, "hexagon-got"},
1961  {MO_LO16, "hexagon-lo16"},
1962  {MO_HI16, "hexagon-hi16"},
1963  {MO_GPREL, "hexagon-gprel"},
1964  {MO_GDGOT, "hexagon-gdgot"},
1965  {MO_GDPLT, "hexagon-gdplt"},
1966  {MO_IE, "hexagon-ie"},
1967  {MO_IEGOT, "hexagon-iegot"},
1968  {MO_TPREL, "hexagon-tprel"}
1969  };
1970  return makeArrayRef(Flags);
1971 }
1972 
1975  using namespace HexagonII;
1976 
1977  static const std::pair<unsigned, const char*> Flags[] = {
1978  {HMOTF_ConstExtended, "hexagon-ext"}
1979  };
1980  return makeArrayRef(Flags);
1981 }
1982 
1985  const TargetRegisterClass *TRC;
1986  if (VT == MVT::i1) {
1987  TRC = &Hexagon::PredRegsRegClass;
1988  } else if (VT == MVT::i32 || VT == MVT::f32) {
1989  TRC = &Hexagon::IntRegsRegClass;
1990  } else if (VT == MVT::i64 || VT == MVT::f64) {
1991  TRC = &Hexagon::DoubleRegsRegClass;
1992  } else {
1993  llvm_unreachable("Cannot handle this register class");
1994  }
1995 
1996  Register NewReg = MRI.createVirtualRegister(TRC);
1997  return NewReg;
1998 }
1999 
2001  return (getAddrMode(MI) == HexagonII::AbsoluteSet);
2002 }
2003 
2005  const uint64_t F = MI.getDesc().TSFlags;
2007 }
2008 
2010  return getAddrMode(MI) == HexagonII::BaseImmOffset;
2011 }
2012 
2014  return !isTC1(MI) && !isTC2Early(MI) && !MI.getDesc().mayLoad() &&
2015  !MI.getDesc().mayStore() &&
2016  MI.getDesc().getOpcode() != Hexagon::S2_allocframe &&
2017  MI.getDesc().getOpcode() != Hexagon::L2_deallocframe &&
2018  !isMemOp(MI) && !MI.isBranch() && !MI.isReturn() && !MI.isCall();
2019 }
2020 
2021 // Return true if the instruction is a compund branch instruction.
2023  return getType(MI) == HexagonII::TypeCJ && MI.isBranch();
2024 }
2025 
2026 // TODO: In order to have isExtendable for fpimm/f32Ext, we need to handle
2027 // isFPImm and later getFPImm as well.
2029  const uint64_t F = MI.getDesc().TSFlags;
2031  if (isExtended) // Instruction must be extended.
2032  return true;
2033 
2034  unsigned isExtendable =
2036  if (!isExtendable)
2037  return false;
2038 
2039  if (MI.isCall())
2040  return false;
2041 
2042  short ExtOpNum = getCExtOpNum(MI);
2043  const MachineOperand &MO = MI.getOperand(ExtOpNum);
2044  // Use MO operand flags to determine if MO
2045  // has the HMOTF_ConstExtended flag set.
2047  return true;
2048  // If this is a Machine BB address we are talking about, and it is
2049  // not marked as extended, say so.
2050  if (MO.isMBB())
2051  return false;
2052 
2053  // We could be using an instruction with an extendable immediate and shoehorn
2054  // a global address into it. If it is a global address it will be constant
2055  // extended. We do this for COMBINE.
2056  if (MO.isGlobal() || MO.isSymbol() || MO.isBlockAddress() ||
2057  MO.isJTI() || MO.isCPI() || MO.isFPImm())
2058  return true;
2059 
2060  // If the extendable operand is not 'Immediate' type, the instruction should
2061  // have 'isExtended' flag set.
2062  assert(MO.isImm() && "Extendable operand must be Immediate type");
2063 
2064  int MinValue = getMinValue(MI);
2065  int MaxValue = getMaxValue(MI);
2066  int ImmValue = MO.getImm();
2067 
2068  return (ImmValue < MinValue || ImmValue > MaxValue);
2069 }
2070 
2072  switch (MI.getOpcode()) {
2073  case Hexagon::L4_return:
2074  case Hexagon::L4_return_t:
2075  case Hexagon::L4_return_f:
2076  case Hexagon::L4_return_tnew_pnt:
2077  case Hexagon::L4_return_fnew_pnt:
2078  case Hexagon::L4_return_tnew_pt:
2079  case Hexagon::L4_return_fnew_pt:
2080  return true;
2081  }
2082  return false;
2083 }
2084 
2085 // Return true when ConsMI uses a register defined by ProdMI.
2087  const MachineInstr &ConsMI) const {
2088  if (!ProdMI.getDesc().getNumDefs())
2089  return false;
2090  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
2091 
2096 
2097  parseOperands(ProdMI, DefsA, UsesA);
2098  parseOperands(ConsMI, DefsB, UsesB);
2099 
2100  for (auto &RegA : DefsA)
2101  for (auto &RegB : UsesB) {
2102  // True data dependency.
2103  if (RegA == RegB)
2104  return true;
2105 
2106  if (Register::isPhysicalRegister(RegA))
2107  for (MCSubRegIterator SubRegs(RegA, &HRI); SubRegs.isValid(); ++SubRegs)
2108  if (RegB == *SubRegs)
2109  return true;
2110 
2111  if (Register::isPhysicalRegister(RegB))
2112  for (MCSubRegIterator SubRegs(RegB, &HRI); SubRegs.isValid(); ++SubRegs)
2113  if (RegA == *SubRegs)
2114  return true;
2115  }
2116 
2117  return false;
2118 }
2119 
2120 // Returns true if the instruction is alread a .cur.
2122  switch (MI.getOpcode()) {
2123  case Hexagon::V6_vL32b_cur_pi:
2124  case Hexagon::V6_vL32b_cur_ai:
2125  return true;
2126  }
2127  return false;
2128 }
2129 
2130 // Returns true, if any one of the operands is a dot new
2131 // insn, whether it is predicated dot new or register dot new.
2133  if (isNewValueInst(MI) || (isPredicated(MI) && isPredicatedNew(MI)))
2134  return true;
2135 
2136  return false;
2137 }
2138 
2139 /// Symmetrical. See if these two instructions are fit for duplex pair.
2141  const MachineInstr &MIb) const {
2144  return (isDuplexPairMatch(MIaG, MIbG) || isDuplexPairMatch(MIbG, MIaG));
2145 }
2146 
2148  if (MI.mayLoad() || MI.mayStore() || MI.isCompare())
2149  return true;
2150 
2151  // Multiply
2152  unsigned SchedClass = MI.getDesc().getSchedClass();
2153  return is_TC4x(SchedClass) || is_TC3x(SchedClass);
2154 }
2155 
2156 bool HexagonInstrInfo::isEndLoopN(unsigned Opcode) const {
2157  return (Opcode == Hexagon::ENDLOOP0 ||
2158  Opcode == Hexagon::ENDLOOP1);
2159 }
2160 
2161 bool HexagonInstrInfo::isExpr(unsigned OpType) const {
2162  switch(OpType) {
2169  return true;
2170  default:
2171  return false;
2172  }
2173 }
2174 
2176  const MCInstrDesc &MID = MI.getDesc();
2177  const uint64_t F = MID.TSFlags;
2179  return true;
2180 
2181  // TODO: This is largely obsolete now. Will need to be removed
2182  // in consecutive patches.
2183  switch (MI.getOpcode()) {
2184  // PS_fi and PS_fia remain special cases.
2185  case Hexagon::PS_fi:
2186  case Hexagon::PS_fia:
2187  return true;
2188  default:
2189  return false;
2190  }
2191  return false;
2192 }
2193 
2194 // This returns true in two cases:
2195 // - The OP code itself indicates that this is an extended instruction.
2196 // - One of MOs has been marked with HMOTF_ConstExtended flag.
2198  // First check if this is permanently extended op code.
2199  const uint64_t F = MI.getDesc().TSFlags;
2201  return true;
2202  // Use MO operand flags to determine if one of MI's operands
2203  // has HMOTF_ConstExtended flag set.
2204  for (const MachineOperand &MO : MI.operands())
2205  if (MO.getTargetFlags() & HexagonII::HMOTF_ConstExtended)
2206  return true;
2207  return false;
2208 }
2209 
2211  unsigned Opcode = MI.getOpcode();
2212  const uint64_t F = get(Opcode).TSFlags;
2213  return (F >> HexagonII::FPPos) & HexagonII::FPMask;
2214 }
2215 
2216 // No V60 HVX VMEM with A_INDIRECT.
2218  const MachineInstr &J) const {
2219  if (!isHVXVec(I))
2220  return false;
2221  if (!I.mayLoad() && !I.mayStore())
2222  return false;
2223  return J.isIndirectBranch() || isIndirectCall(J) || isIndirectL4Return(J);
2224 }
2225 
2227  switch (MI.getOpcode()) {
2228  case Hexagon::J2_callr:
2229  case Hexagon::J2_callrf:
2230  case Hexagon::J2_callrt:
2231  case Hexagon::PS_call_nr:
2232  return true;
2233  }
2234  return false;
2235 }
2236 
2238  switch (MI.getOpcode()) {
2239  case Hexagon::L4_return:
2240  case Hexagon::L4_return_t:
2241  case Hexagon::L4_return_f:
2242  case Hexagon::L4_return_fnew_pnt:
2243  case Hexagon::L4_return_fnew_pt:
2244  case Hexagon::L4_return_tnew_pnt:
2245  case Hexagon::L4_return_tnew_pt:
2246  return true;
2247  }
2248  return false;
2249 }
2250 
2252  switch (MI.getOpcode()) {
2253  case Hexagon::J2_jumpr:
2254  case Hexagon::J2_jumprt:
2255  case Hexagon::J2_jumprf:
2256  case Hexagon::J2_jumprtnewpt:
2257  case Hexagon::J2_jumprfnewpt:
2258  case Hexagon::J2_jumprtnew:
2259  case Hexagon::J2_jumprfnew:
2260  return true;
2261  }
2262  return false;
2263 }
2264 
2265 // Return true if a given MI can accommodate given offset.
2266 // Use abs estimate as oppose to the exact number.
2267 // TODO: This will need to be changed to use MC level
2268 // definition of instruction extendable field size.
2270  unsigned offset) const {
2271  // This selection of jump instructions matches to that what
2272  // analyzeBranch can parse, plus NVJ.
2273  if (isNewValueJump(MI)) // r9:2
2274  return isInt<11>(offset);
2275 
2276  switch (MI.getOpcode()) {
2277  // Still missing Jump to address condition on register value.
2278  default:
2279  return false;
2280  case Hexagon::J2_jump: // bits<24> dst; // r22:2
2281  case Hexagon::J2_call:
2282  case Hexagon::PS_call_nr:
2283  return isInt<24>(offset);
2284  case Hexagon::J2_jumpt: //bits<17> dst; // r15:2
2285  case Hexagon::J2_jumpf:
2286  case Hexagon::J2_jumptnew:
2287  case Hexagon::J2_jumptnewpt:
2288  case Hexagon::J2_jumpfnew:
2289  case Hexagon::J2_jumpfnewpt:
2290  case Hexagon::J2_callt:
2291  case Hexagon::J2_callf:
2292  return isInt<17>(offset);
2293  case Hexagon::J2_loop0i:
2294  case Hexagon::J2_loop0iext:
2295  case Hexagon::J2_loop0r:
2296  case Hexagon::J2_loop0rext:
2297  case Hexagon::J2_loop1i:
2298  case Hexagon::J2_loop1iext:
2299  case Hexagon::J2_loop1r:
2300  case Hexagon::J2_loop1rext:
2301  return isInt<9>(offset);
2302  // TODO: Add all the compound branches here. Can we do this in Relation model?
2303  case Hexagon::J4_cmpeqi_tp0_jump_nt:
2304  case Hexagon::J4_cmpeqi_tp1_jump_nt:
2305  case Hexagon::J4_cmpeqn1_tp0_jump_nt:
2306  case Hexagon::J4_cmpeqn1_tp1_jump_nt:
2307  return isInt<11>(offset);
2308  }
2309 }
2310 
2312  const MachineInstr &ESMI) const {
2313  bool isLate = isLateResultInstr(LRMI);
2314  bool isEarly = isEarlySourceInstr(ESMI);
2315 
2316  LLVM_DEBUG(dbgs() << "V60" << (isLate ? "-LR " : " -- "));
2317  LLVM_DEBUG(LRMI.dump());
2318  LLVM_DEBUG(dbgs() << "V60" << (isEarly ? "-ES " : " -- "));
2319  LLVM_DEBUG(ESMI.dump());
2320 
2321  if (isLate && isEarly) {
2322  LLVM_DEBUG(dbgs() << "++Is Late Result feeding Early Source\n");
2323  return true;
2324  }
2325 
2326  return false;
2327 }
2328 
2330  switch (MI.getOpcode()) {
2331  case TargetOpcode::EXTRACT_SUBREG:
2332  case TargetOpcode::INSERT_SUBREG:
2333  case TargetOpcode::SUBREG_TO_REG:
2334  case TargetOpcode::REG_SEQUENCE:
2335  case TargetOpcode::IMPLICIT_DEF:
2336  case TargetOpcode::COPY:
2338  case TargetOpcode::PHI:
2339  return false;
2340  default:
2341  break;
2342  }
2343 
2344  unsigned SchedClass = MI.getDesc().getSchedClass();
2345  return !is_TC1(SchedClass);
2346 }
2347 
2349  // Instructions with iclass A_CVI_VX and attribute A_CVI_LATE uses a multiply
2350  // resource, but all operands can be received late like an ALU instruction.
2351  return getType(MI) == HexagonII::TypeCVI_VX_LATE;
2352 }
2353 
2355  unsigned Opcode = MI.getOpcode();
2356  return Opcode == Hexagon::J2_loop0i ||
2357  Opcode == Hexagon::J2_loop0r ||
2358  Opcode == Hexagon::J2_loop0iext ||
2359  Opcode == Hexagon::J2_loop0rext ||
2360  Opcode == Hexagon::J2_loop1i ||
2361  Opcode == Hexagon::J2_loop1r ||
2362  Opcode == Hexagon::J2_loop1iext ||
2363  Opcode == Hexagon::J2_loop1rext;
2364 }
2365 
2367  switch (MI.getOpcode()) {
2368  default: return false;
2369  case Hexagon::L4_iadd_memopw_io:
2370  case Hexagon::L4_isub_memopw_io:
2371  case Hexagon::L4_add_memopw_io:
2372  case Hexagon::L4_sub_memopw_io:
2373  case Hexagon::L4_and_memopw_io:
2374  case Hexagon::L4_or_memopw_io:
2375  case Hexagon::L4_iadd_memoph_io:
2376  case Hexagon::L4_isub_memoph_io:
2377  case Hexagon::L4_add_memoph_io:
2378  case Hexagon::L4_sub_memoph_io:
2379  case Hexagon::L4_and_memoph_io:
2380  case Hexagon::L4_or_memoph_io:
2381  case Hexagon::L4_iadd_memopb_io:
2382  case Hexagon::L4_isub_memopb_io:
2383  case Hexagon::L4_add_memopb_io:
2384  case Hexagon::L4_sub_memopb_io:
2385  case Hexagon::L4_and_memopb_io:
2386  case Hexagon::L4_or_memopb_io:
2387  case Hexagon::L4_ior_memopb_io:
2388  case Hexagon::L4_ior_memoph_io:
2389  case Hexagon::L4_ior_memopw_io:
2390  case Hexagon::L4_iand_memopb_io:
2391  case Hexagon::L4_iand_memoph_io:
2392  case Hexagon::L4_iand_memopw_io:
2393  return true;
2394  }
2395  return false;
2396 }
2397 
2399  const uint64_t F = MI.getDesc().TSFlags;
2401 }
2402 
2403 bool HexagonInstrInfo::isNewValue(unsigned Opcode) const {
2404  const uint64_t F = get(Opcode).TSFlags;
2406 }
2407 
2409  return isNewValueJump(MI) || isNewValueStore(MI);
2410 }
2411 
2413  return isNewValue(MI) && MI.isBranch();
2414 }
2415 
2416 bool HexagonInstrInfo::isNewValueJump(unsigned Opcode) const {
2417  return isNewValue(Opcode) && get(Opcode).isBranch() && isPredicated(Opcode);
2418 }
2419 
2421  const uint64_t F = MI.getDesc().TSFlags;
2423 }
2424 
2425 bool HexagonInstrInfo::isNewValueStore(unsigned Opcode) const {
2426  const uint64_t F = get(Opcode).TSFlags;
2428 }
2429 
2430 // Returns true if a particular operand is extendable for an instruction.
2432  unsigned OperandNum) const {
2433  const uint64_t F = MI.getDesc().TSFlags;
2435  == OperandNum;
2436 }
2437 
2439  const uint64_t F = MI.getDesc().TSFlags;
2440  assert(isPredicated(MI));
2442 }
2443 
2444 bool HexagonInstrInfo::isPredicatedNew(unsigned Opcode) const {
2445  const uint64_t F = get(Opcode).TSFlags;
2446  assert(isPredicated(Opcode));
2448 }
2449 
2451  const uint64_t F = MI.getDesc().TSFlags;
2452  return !((F >> HexagonII::PredicatedFalsePos) &
2454 }
2455 
2456 bool HexagonInstrInfo::isPredicatedTrue(unsigned Opcode) const {
2457  const uint64_t F = get(Opcode).TSFlags;
2458  // Make sure that the instruction is predicated.
2460  return !((F >> HexagonII::PredicatedFalsePos) &
2462 }
2463 
2464 bool HexagonInstrInfo::isPredicated(unsigned Opcode) const {
2465  const uint64_t F = get(Opcode).TSFlags;
2467 }
2468 
2469 bool HexagonInstrInfo::isPredicateLate(unsigned Opcode) const {
2470  const uint64_t F = get(Opcode).TSFlags;
2472 }
2473 
2474 bool HexagonInstrInfo::isPredictedTaken(unsigned Opcode) const {
2475  const uint64_t F = get(Opcode).TSFlags;
2476  assert(get(Opcode).isBranch() &&
2477  (isPredicatedNew(Opcode) || isNewValue(Opcode)));
2478  return (F >> HexagonII::TakenPos) & HexagonII::TakenMask;
2479 }
2480 
2482  return MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4 ||
2483  MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_EXT ||
2484  MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_PIC ||
2485  MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_EXT_PIC;
2486 }
2487 
2489  switch (MI.getOpcode()) {
2490  // Byte
2491  case Hexagon::L2_loadrb_io:
2492  case Hexagon::L4_loadrb_ur:
2493  case Hexagon::L4_loadrb_ap:
2494  case Hexagon::L2_loadrb_pr:
2495  case Hexagon::L2_loadrb_pbr:
2496  case Hexagon::L2_loadrb_pi:
2497  case Hexagon::L2_loadrb_pci:
2498  case Hexagon::L2_loadrb_pcr:
2499  case Hexagon::L2_loadbsw2_io:
2500  case Hexagon::L4_loadbsw2_ur:
2501  case Hexagon::L4_loadbsw2_ap:
2502  case Hexagon::L2_loadbsw2_pr:
2503  case Hexagon::L2_loadbsw2_pbr:
2504  case Hexagon::L2_loadbsw2_pi:
2505  case Hexagon::L2_loadbsw2_pci:
2506  case Hexagon::L2_loadbsw2_pcr:
2507  case Hexagon::L2_loadbsw4_io:
2508  case Hexagon::L4_loadbsw4_ur:
2509  case Hexagon::L4_loadbsw4_ap:
2510  case Hexagon::L2_loadbsw4_pr:
2511  case Hexagon::L2_loadbsw4_pbr:
2512  case Hexagon::L2_loadbsw4_pi:
2513  case Hexagon::L2_loadbsw4_pci:
2514  case Hexagon::L2_loadbsw4_pcr:
2515  case Hexagon::L4_loadrb_rr:
2516  case Hexagon::L2_ploadrbt_io:
2517  case Hexagon::L2_ploadrbt_pi:
2518  case Hexagon::L2_ploadrbf_io:
2519  case Hexagon::L2_ploadrbf_pi:
2520  case Hexagon::L2_ploadrbtnew_io:
2521  case Hexagon::L2_ploadrbfnew_io:
2522  case Hexagon::L4_ploadrbt_rr:
2523  case Hexagon::L4_ploadrbf_rr:
2524  case Hexagon::L4_ploadrbtnew_rr:
2525  case Hexagon::L4_ploadrbfnew_rr:
2526  case Hexagon::L2_ploadrbtnew_pi:
2527  case Hexagon::L2_ploadrbfnew_pi:
2528  case Hexagon::L4_ploadrbt_abs:
2529  case Hexagon::L4_ploadrbf_abs:
2530  case Hexagon::L4_ploadrbtnew_abs:
2531  case Hexagon::L4_ploadrbfnew_abs:
2532  case Hexagon::L2_loadrbgp:
2533  // Half
2534  case Hexagon::L2_loadrh_io:
2535  case Hexagon::L4_loadrh_ur:
2536  case Hexagon::L4_loadrh_ap:
2537  case Hexagon::L2_loadrh_pr:
2538  case Hexagon::L2_loadrh_pbr:
2539  case Hexagon::L2_loadrh_pi:
2540  case Hexagon::L2_loadrh_pci:
2541  case Hexagon::L2_loadrh_pcr:
2542  case Hexagon::L4_loadrh_rr:
2543  case Hexagon::L2_ploadrht_io:
2544  case Hexagon::L2_ploadrht_pi:
2545  case Hexagon::L2_ploadrhf_io:
2546  case Hexagon::L2_ploadrhf_pi:
2547  case Hexagon::L2_ploadrhtnew_io:
2548  case Hexagon::L2_ploadrhfnew_io:
2549  case Hexagon::L4_ploadrht_rr:
2550  case Hexagon::L4_ploadrhf_rr:
2551  case Hexagon::L4_ploadrhtnew_rr:
2552  case Hexagon::L4_ploadrhfnew_rr:
2553  case Hexagon::L2_ploadrhtnew_pi:
2554  case Hexagon::L2_ploadrhfnew_pi:
2555  case Hexagon::L4_ploadrht_abs:
2556  case Hexagon::L4_ploadrhf_abs:
2557  case Hexagon::L4_ploadrhtnew_abs:
2558  case Hexagon::L4_ploadrhfnew_abs:
2559  case Hexagon::L2_loadrhgp:
2560  return true;
2561  default:
2562  return false;
2563  }
2564 }
2565 
2567  const uint64_t F = MI.getDesc().TSFlags;
2568  return (F >> HexagonII::SoloPos) & HexagonII::SoloMask;
2569 }
2570 
2572  switch (MI.getOpcode()) {
2573  case Hexagon::STriw_pred:
2574  case Hexagon::LDriw_pred:
2575  return true;
2576  default:
2577  return false;
2578  }
2579 }
2580 
2582  if (!MI.isBranch())
2583  return false;
2584 
2585  for (auto &Op : MI.operands())
2586  if (Op.isGlobal() || Op.isSymbol())
2587  return true;
2588  return false;
2589 }
2590 
2591 // Returns true when SU has a timing class TC1.
2593  unsigned SchedClass = MI.getDesc().getSchedClass();
2594  return is_TC1(SchedClass);
2595 }
2596 
2598  unsigned SchedClass = MI.getDesc().getSchedClass();
2599  return is_TC2(SchedClass);
2600 }
2601 
2603  unsigned SchedClass = MI.getDesc().getSchedClass();
2604  return is_TC2early(SchedClass);
2605 }
2606 
2608  unsigned SchedClass = MI.getDesc().getSchedClass();
2609  return is_TC4x(SchedClass);
2610 }
2611 
2612 // Schedule this ASAP.
2614  const MachineInstr &MI2) const {
2615  if (mayBeCurLoad(MI1)) {
2616  // if (result of SU is used in Next) return true;
2617  Register DstReg = MI1.getOperand(0).getReg();
2618  int N = MI2.getNumOperands();
2619  for (int I = 0; I < N; I++)
2620  if (MI2.getOperand(I).isReg() && DstReg == MI2.getOperand(I).getReg())
2621  return true;
2622  }
2623  if (mayBeNewStore(MI2))
2624  if (MI2.getOpcode() == Hexagon::V6_vS32b_pi)
2625  if (MI1.getOperand(0).isReg() && MI2.getOperand(3).isReg() &&
2626  MI1.getOperand(0).getReg() == MI2.getOperand(3).getReg())
2627  return true;
2628  return false;
2629 }
2630 
2632  const uint64_t V = getType(MI);
2634 }
2635 
2636 // Check if the Offset is a valid auto-inc imm by Load/Store Type.
2638  int Size = VT.getSizeInBits() / 8;
2639  if (Offset % Size != 0)
2640  return false;
2641  int Count = Offset / Size;
2642 
2643  switch (VT.getSimpleVT().SimpleTy) {
2644  // For scalars the auto-inc is s4
2645  case MVT::i8:
2646  case MVT::i16:
2647  case MVT::i32:
2648  case MVT::i64:
2649  case MVT::f32:
2650  case MVT::f64:
2651  case MVT::v2i16:
2652  case MVT::v2i32:
2653  case MVT::v4i8:
2654  case MVT::v4i16:
2655  case MVT::v8i8:
2656  return isInt<4>(Count);
2657  // For HVX vectors the auto-inc is s3
2658  case MVT::v64i8:
2659  case MVT::v32i16:
2660  case MVT::v16i32:
2661  case MVT::v8i64:
2662  case MVT::v128i8:
2663  case MVT::v64i16:
2664  case MVT::v32i32:
2665  case MVT::v16i64:
2666  return isInt<3>(Count);
2667  default:
2668  break;
2669  }
2670 
2671  llvm_unreachable("Not an valid type!");
2672 }
2673 
2674 bool HexagonInstrInfo::isValidOffset(unsigned Opcode, int Offset,
2675  const TargetRegisterInfo *TRI, bool Extend) const {
2676  // This function is to check whether the "Offset" is in the correct range of
2677  // the given "Opcode". If "Offset" is not in the correct range, "A2_addi" is
2678  // inserted to calculate the final address. Due to this reason, the function
2679  // assumes that the "Offset" has correct alignment.
2680  // We used to assert if the offset was not properly aligned, however,
2681  // there are cases where a misaligned pointer recast can cause this
2682  // problem, and we need to allow for it. The front end warns of such
2683  // misaligns with respect to load size.
2684  switch (Opcode) {
2685  case Hexagon::PS_vstorerq_ai:
2686  case Hexagon::PS_vstorerw_ai:
2687  case Hexagon::PS_vstorerw_nt_ai:
2688  case Hexagon::PS_vloadrq_ai:
2689  case Hexagon::PS_vloadrw_ai:
2690  case Hexagon::PS_vloadrw_nt_ai:
2691  case Hexagon::V6_vL32b_ai:
2692  case Hexagon::V6_vS32b_ai:
2693  case Hexagon::V6_vL32b_nt_ai:
2694  case Hexagon::V6_vS32b_nt_ai:
2695  case Hexagon::V6_vL32Ub_ai:
2696  case Hexagon::V6_vS32Ub_ai: {
2697  unsigned VectorSize = TRI->getSpillSize(Hexagon::HvxVRRegClass);
2698  assert(isPowerOf2_32(VectorSize));
2699  if (Offset & (VectorSize-1))
2700  return false;
2701  return isInt<4>(Offset >> Log2_32(VectorSize));
2702  }
2703 
2704  case Hexagon::J2_loop0i:
2705  case Hexagon::J2_loop1i:
2706  return isUInt<10>(Offset);
2707 
2708  case Hexagon::S4_storeirb_io:
2709  case Hexagon::S4_storeirbt_io:
2710  case Hexagon::S4_storeirbf_io:
2711  return isUInt<6>(Offset);
2712 
2713  case Hexagon::S4_storeirh_io:
2714  case Hexagon::S4_storeirht_io:
2715  case Hexagon::S4_storeirhf_io:
2716  return isShiftedUInt<6,1>(Offset);
2717 
2718  case Hexagon::S4_storeiri_io:
2719  case Hexagon::S4_storeirit_io:
2720  case Hexagon::S4_storeirif_io:
2721  return isShiftedUInt<6,2>(Offset);
2722  }
2723 
2724  if (Extend)
2725  return true;
2726 
2727  switch (Opcode) {
2728  case Hexagon::L2_loadri_io:
2729  case Hexagon::S2_storeri_io:
2730  return (Offset >= Hexagon_MEMW_OFFSET_MIN) &&
2731  (Offset <= Hexagon_MEMW_OFFSET_MAX);
2732 
2733  case Hexagon::L2_loadrd_io:
2734  case Hexagon::S2_storerd_io:
2735  return (Offset >= Hexagon_MEMD_OFFSET_MIN) &&
2736  (Offset <= Hexagon_MEMD_OFFSET_MAX);
2737 
2738  case Hexagon::L2_loadrh_io:
2739  case Hexagon::L2_loadruh_io:
2740  case Hexagon::S2_storerh_io:
2741  case Hexagon::S2_storerf_io:
2742  return (Offset >= Hexagon_MEMH_OFFSET_MIN) &&
2743  (Offset <= Hexagon_MEMH_OFFSET_MAX);
2744 
2745  case Hexagon::L2_loadrb_io:
2746  case Hexagon::L2_loadrub_io:
2747  case Hexagon::S2_storerb_io:
2748  return (Offset >= Hexagon_MEMB_OFFSET_MIN) &&
2749  (Offset <= Hexagon_MEMB_OFFSET_MAX);
2750 
2751  case Hexagon::A2_addi:
2752  return (Offset >= Hexagon_ADDI_OFFSET_MIN) &&
2753  (Offset <= Hexagon_ADDI_OFFSET_MAX);
2754 
2755  case Hexagon::L4_iadd_memopw_io:
2756  case Hexagon::L4_isub_memopw_io:
2757  case Hexagon::L4_add_memopw_io:
2758  case Hexagon::L4_sub_memopw_io:
2759  case Hexagon::L4_and_memopw_io:
2760  case Hexagon::L4_or_memopw_io:
2761  return (0 <= Offset && Offset <= 255);
2762 
2763  case Hexagon::L4_iadd_memoph_io:
2764  case Hexagon::L4_isub_memoph_io:
2765  case Hexagon::L4_add_memoph_io:
2766  case Hexagon::L4_sub_memoph_io:
2767  case Hexagon::L4_and_memoph_io:
2768  case Hexagon::L4_or_memoph_io:
2769  return (0 <= Offset && Offset <= 127);
2770 
2771  case Hexagon::L4_iadd_memopb_io:
2772  case Hexagon::L4_isub_memopb_io:
2773  case Hexagon::L4_add_memopb_io:
2774  case Hexagon::L4_sub_memopb_io:
2775  case Hexagon::L4_and_memopb_io:
2776  case Hexagon::L4_or_memopb_io:
2777  return (0 <= Offset && Offset <= 63);
2778 
2779  // LDriw_xxx and STriw_xxx are pseudo operations, so it has to take offset of
2780  // any size. Later pass knows how to handle it.
2781  case Hexagon::STriw_pred:
2782  case Hexagon::LDriw_pred:
2783  case Hexagon::STriw_ctr:
2784  case Hexagon::LDriw_ctr:
2785  return true;
2786 
2787  case Hexagon::PS_fi:
2788  case Hexagon::PS_fia:
2789  case Hexagon::INLINEASM:
2790  return true;
2791 
2792  case Hexagon::L2_ploadrbt_io:
2793  case Hexagon::L2_ploadrbf_io:
2794  case Hexagon::L2_ploadrubt_io:
2795  case Hexagon::L2_ploadrubf_io:
2796  case Hexagon::S2_pstorerbt_io:
2797  case Hexagon::S2_pstorerbf_io:
2798  return isUInt<6>(Offset);
2799 
2800  case Hexagon::L2_ploadrht_io:
2801  case Hexagon::L2_ploadrhf_io:
2802  case Hexagon::L2_ploadruht_io:
2803  case Hexagon::L2_ploadruhf_io:
2804  case Hexagon::S2_pstorerht_io:
2805  case Hexagon::S2_pstorerhf_io:
2806  return isShiftedUInt<6,1>(Offset);
2807 
2808  case Hexagon::L2_ploadrit_io:
2809  case Hexagon::L2_ploadrif_io:
2810  case Hexagon::S2_pstorerit_io:
2811  case Hexagon::S2_pstorerif_io:
2812  return isShiftedUInt<6,2>(Offset);
2813 
2814  case Hexagon::L2_ploadrdt_io:
2815  case Hexagon::L2_ploadrdf_io:
2816  case Hexagon::S2_pstorerdt_io:
2817  case Hexagon::S2_pstorerdf_io:
2818  return isShiftedUInt<6,3>(Offset);
2819  } // switch
2820 
2821  llvm_unreachable("No offset range is defined for this opcode. "
2822  "Please define it in the above switch statement!");
2823 }
2824 
2826  return isHVXVec(MI) && isAccumulator(MI);
2827 }
2828 
2830  const uint64_t F = get(MI.getOpcode()).TSFlags;
2831  const uint64_t V = ((F >> HexagonII::TypePos) & HexagonII::TypeMask);
2832  return
2833  V == HexagonII::TypeCVI_VA ||
2835 }
2836 
2838  const MachineInstr &ConsMI) const {
2839  if (EnableACCForwarding && isVecAcc(ProdMI) && isVecAcc(ConsMI))
2840  return true;
2841 
2842  if (EnableALUForwarding && (isVecALU(ConsMI) || isLateSourceInstr(ConsMI)))
2843  return true;
2844 
2845  if (mayBeNewStore(ConsMI))
2846  return true;
2847 
2848  return false;
2849 }
2850 
2852  switch (MI.getOpcode()) {
2853  // Byte
2854  case Hexagon::L2_loadrub_io:
2855  case Hexagon::L4_loadrub_ur:
2856  case Hexagon::L4_loadrub_ap:
2857  case Hexagon::L2_loadrub_pr:
2858  case Hexagon::L2_loadrub_pbr:
2859  case Hexagon::L2_loadrub_pi:
2860  case Hexagon::L2_loadrub_pci:
2861  case Hexagon::L2_loadrub_pcr:
2862  case Hexagon::L2_loadbzw2_io:
2863  case Hexagon::L4_loadbzw2_ur:
2864  case Hexagon::L4_loadbzw2_ap:
2865  case Hexagon::L2_loadbzw2_pr:
2866  case Hexagon::L2_loadbzw2_pbr:
2867  case Hexagon::L2_loadbzw2_pi:
2868  case Hexagon::L2_loadbzw2_pci:
2869  case Hexagon::L2_loadbzw2_pcr:
2870  case Hexagon::L2_loadbzw4_io:
2871  case Hexagon::L4_loadbzw4_ur:
2872  case Hexagon::L4_loadbzw4_ap:
2873  case Hexagon::L2_loadbzw4_pr:
2874  case Hexagon::L2_loadbzw4_pbr:
2875  case Hexagon::L2_loadbzw4_pi:
2876  case Hexagon::L2_loadbzw4_pci:
2877  case Hexagon::L2_loadbzw4_pcr:
2878  case Hexagon::L4_loadrub_rr:
2879  case Hexagon::L2_ploadrubt_io:
2880  case Hexagon::L2_ploadrubt_pi:
2881  case Hexagon::L2_ploadrubf_io:
2882  case Hexagon::L2_ploadrubf_pi:
2883  case Hexagon::L2_ploadrubtnew_io:
2884  case Hexagon::L2_ploadrubfnew_io:
2885  case Hexagon::L4_ploadrubt_rr:
2886  case Hexagon::L4_ploadrubf_rr:
2887  case Hexagon::L4_ploadrubtnew_rr:
2888  case Hexagon::L4_ploadrubfnew_rr:
2889  case Hexagon::L2_ploadrubtnew_pi:
2890  case Hexagon::L2_ploadrubfnew_pi:
2891  case Hexagon::L4_ploadrubt_abs:
2892  case Hexagon::L4_ploadrubf_abs:
2893  case Hexagon::L4_ploadrubtnew_abs:
2894  case Hexagon::L4_ploadrubfnew_abs:
2895  case Hexagon::L2_loadrubgp:
2896  // Half
2897  case Hexagon::L2_loadruh_io:
2898  case Hexagon::L4_loadruh_ur:
2899  case Hexagon::L4_loadruh_ap:
2900  case Hexagon::L2_loadruh_pr:
2901  case Hexagon::L2_loadruh_pbr:
2902  case Hexagon::L2_loadruh_pi:
2903  case Hexagon::L2_loadruh_pci:
2904  case Hexagon::L2_loadruh_pcr:
2905  case Hexagon::L4_loadruh_rr:
2906  case Hexagon::L2_ploadruht_io:
2907  case Hexagon::L2_ploadruht_pi:
2908  case Hexagon::L2_ploadruhf_io:
2909  case Hexagon::L2_ploadruhf_pi:
2910  case Hexagon::L2_ploadruhtnew_io:
2911  case Hexagon::L2_ploadruhfnew_io:
2912  case Hexagon::L4_ploadruht_rr:
2913  case Hexagon::L4_ploadruhf_rr:
2914  case Hexagon::L4_ploadruhtnew_rr:
2915  case Hexagon::L4_ploadruhfnew_rr:
2916  case Hexagon::L2_ploadruhtnew_pi:
2917  case Hexagon::L2_ploadruhfnew_pi:
2918  case Hexagon::L4_ploadruht_abs:
2919  case Hexagon::L4_ploadruhf_abs:
2920  case Hexagon::L4_ploadruhtnew_abs:
2921  case Hexagon::L4_ploadruhfnew_abs:
2922  case Hexagon::L2_loadruhgp:
2923  return true;
2924  default:
2925  return false;
2926  }
2927 }
2928 
2929 // Add latency to instruction.
2931  const MachineInstr &MI2) const {
2932  if (isHVXVec(MI1) && isHVXVec(MI2))
2933  if (!isVecUsableNextPacket(MI1, MI2))
2934  return true;
2935  return false;
2936 }
2937 
2938 /// Get the base register and byte offset of a load/store instr.
2940  const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset,
2941  const TargetRegisterInfo *TRI) const {
2942  unsigned AccessSize = 0;
2943  BaseOp = getBaseAndOffset(LdSt, Offset, AccessSize);
2944  assert((!BaseOp || BaseOp->isReg()) &&
2945  "getMemOperandWithOffset only supports base "
2946  "operands of type register.");
2947  return BaseOp != nullptr;
2948 }
2949 
2950 /// Can these instructions execute at the same time in a bundle.
2952  const MachineInstr &Second) const {
2953  if (Second.mayStore() && First.getOpcode() == Hexagon::S2_allocframe) {
2954  const MachineOperand &Op = Second.getOperand(0);
2955  if (Op.isReg() && Op.isUse() && Op.getReg() == Hexagon::R29)
2956  return true;
2957  }
2958  if (DisableNVSchedule)
2959  return false;
2960  if (mayBeNewStore(Second)) {
2961  // Make sure the definition of the first instruction is the value being
2962  // stored.
2963  const MachineOperand &Stored =
2964  Second.getOperand(Second.getNumOperands() - 1);
2965  if (!Stored.isReg())
2966  return false;
2967  for (unsigned i = 0, e = First.getNumOperands(); i < e; ++i) {
2968  const MachineOperand &Op = First.getOperand(i);
2969  if (Op.isReg() && Op.isDef() && Op.getReg() == Stored.getReg())
2970  return true;
2971  }
2972  }
2973  return false;
2974 }
2975 
2977  unsigned Opc = CallMI.getOpcode();
2978  return Opc == Hexagon::PS_call_nr || Opc == Hexagon::PS_callr_nr;
2979 }
2980 
2982  for (auto &I : *B)
2983  if (I.isEHLabel())
2984  return true;
2985  return false;
2986 }
2987 
2988 // Returns true if an instruction can be converted into a non-extended
2989 // equivalent instruction.
2991  short NonExtOpcode;
2992  // Check if the instruction has a register form that uses register in place
2993  // of the extended operand, if so return that as the non-extended form.
2994  if (Hexagon::getRegForm(MI.getOpcode()) >= 0)
2995  return true;
2996 
2997  if (MI.getDesc().mayLoad() || MI.getDesc().mayStore()) {
2998  // Check addressing mode and retrieve non-ext equivalent instruction.
2999 
3000  switch (getAddrMode(MI)) {
3001  case HexagonII::Absolute:
3002  // Load/store with absolute addressing mode can be converted into
3003  // base+offset mode.
3004  NonExtOpcode = Hexagon::changeAddrMode_abs_io(MI.getOpcode());
3005  break;
3007  // Load/store with base+offset addressing mode can be converted into
3008  // base+register offset addressing mode. However left shift operand should
3009  // be set to 0.
3010  NonExtOpcode = Hexagon::changeAddrMode_io_rr(MI.getOpcode());
3011  break;
3013  NonExtOpcode = Hexagon::changeAddrMode_ur_rr(MI.getOpcode());
3014  break;
3015  default:
3016  return false;
3017  }
3018  if (NonExtOpcode < 0)
3019  return false;
3020  return true;
3021  }
3022  return false;
3023 }
3024 
3026  return Hexagon::getRealHWInstr(MI.getOpcode(),
3027  Hexagon::InstrType_Pseudo) >= 0;
3028 }
3029 
3031  const {
3033  while (I != E) {
3034  if (I->isBarrier())
3035  return true;
3036  ++I;
3037  }
3038  return false;
3039 }
3040 
3041 // Returns true, if a LD insn can be promoted to a cur load.
3043  const uint64_t F = MI.getDesc().TSFlags;
3045  Subtarget.hasV60Ops();
3046 }
3047 
3048 // Returns true, if a ST insn can be promoted to a new-value store.
3050  if (MI.mayStore() && !Subtarget.useNewValueStores())
3051  return false;
3052 
3053  const uint64_t F = MI.getDesc().TSFlags;
3055 }
3056 
3058  const MachineInstr &ConsMI) const {
3059  // There is no stall when ProdMI is not a V60 vector.
3060  if (!isHVXVec(ProdMI))
3061  return false;
3062 
3063  // There is no stall when ProdMI and ConsMI are not dependent.
3064  if (!isDependent(ProdMI, ConsMI))
3065  return false;
3066 
3067  // When Forward Scheduling is enabled, there is no stall if ProdMI and ConsMI
3068  // are scheduled in consecutive packets.
3069  if (isVecUsableNextPacket(ProdMI, ConsMI))
3070  return false;
3071 
3072  return true;
3073 }
3074 
3077  // There is no stall when I is not a V60 vector.
3078  if (!isHVXVec(MI))
3079  return false;
3080 
3082  MachineBasicBlock::const_instr_iterator MIE = MII->getParent()->instr_end();
3083 
3084  if (!MII->isBundle())
3085  return producesStall(*MII, MI);
3086 
3087  for (++MII; MII != MIE && MII->isInsideBundle(); ++MII) {
3088  const MachineInstr &J = *MII;
3089  if (producesStall(J, MI))
3090  return true;
3091  }
3092  return false;
3093 }
3094 
3096  unsigned PredReg) const {
3097  for (const MachineOperand &MO : MI.operands()) {
3098  // Predicate register must be explicitly defined.
3099  if (MO.isRegMask() && MO.clobbersPhysReg(PredReg))
3100  return false;
3101  if (MO.isReg() && MO.isDef() && MO.isImplicit() && (MO.getReg() == PredReg))
3102  return false;
3103  }
3104 
3105  // Instruction that produce late predicate cannot be used as sources of
3106  // dot-new.
3107  switch (MI.getOpcode()) {
3108  case Hexagon::A4_addp_c:
3109  case Hexagon::A4_subp_c:
3110  case Hexagon::A4_tlbmatch:
3111  case Hexagon::A5_ACS:
3112  case Hexagon::F2_sfinvsqrta:
3113  case Hexagon::F2_sfrecipa:
3114  case Hexagon::J2_endloop0:
3115  case Hexagon::J2_endloop01:
3116  case Hexagon::J2_ploop1si:
3117  case Hexagon::J2_ploop1sr:
3118  case Hexagon::J2_ploop2si:
3119  case Hexagon::J2_ploop2sr:
3120  case Hexagon::J2_ploop3si:
3121  case Hexagon::J2_ploop3sr:
3122  case Hexagon::S2_cabacdecbin:
3123  case Hexagon::S2_storew_locked:
3124  case Hexagon::S4_stored_locked:
3125  return false;
3126  }
3127  return true;
3128 }
3129 
3130 bool HexagonInstrInfo::PredOpcodeHasJMP_c(unsigned Opcode) const {
3131  return Opcode == Hexagon::J2_jumpt ||
3132  Opcode == Hexagon::J2_jumptpt ||
3133  Opcode == Hexagon::J2_jumpf ||
3134  Opcode == Hexagon::J2_jumpfpt ||
3135  Opcode == Hexagon::J2_jumptnew ||
3136  Opcode == Hexagon::J2_jumpfnew ||
3137  Opcode == Hexagon::J2_jumptnewpt ||
3138  Opcode == Hexagon::J2_jumpfnewpt;
3139 }
3140 
3142  if (Cond.empty() || !isPredicated(Cond[0].getImm()))
3143  return false;
3144  return !isPredicatedTrue(Cond[0].getImm());
3145 }
3146 
3148  const uint64_t F = MI.getDesc().TSFlags;
3150 }
3151 
3152 // Returns the base register in a memory access (load/store). The offset is
3153 // returned in Offset and the access size is returned in AccessSize.
3154 // If the base operand has a subregister or the offset field does not contain
3155 // an immediate value, return nullptr.
3157  int64_t &Offset,
3158  unsigned &AccessSize) const {
3159  // Return if it is not a base+offset type instruction or a MemOp.
3162  !isMemOp(MI) && !isPostIncrement(MI))
3163  return nullptr;
3164 
3165  AccessSize = getMemAccessSize(MI);
3166 
3167  unsigned BasePos = 0, OffsetPos = 0;
3168  if (!getBaseAndOffsetPosition(MI, BasePos, OffsetPos))
3169  return nullptr;
3170 
3171  // Post increment updates its EA after the mem access,
3172  // so we need to treat its offset as zero.
3173  if (isPostIncrement(MI)) {
3174  Offset = 0;
3175  } else {
3176  const MachineOperand &OffsetOp = MI.getOperand(OffsetPos);
3177  if (!OffsetOp.isImm())
3178  return nullptr;
3179  Offset = OffsetOp.getImm();
3180  }
3181 
3182  const MachineOperand &BaseOp = MI.getOperand(BasePos);
3183  if (BaseOp.getSubReg() != 0)
3184  return nullptr;
3185  return &const_cast<MachineOperand&>(BaseOp);
3186 }
3187 
3188 /// Return the position of the base and offset operands for this instruction.
3190  unsigned &BasePos, unsigned &OffsetPos) const {
3191  if (!isAddrModeWithOffset(MI) && !isPostIncrement(MI))
3192  return false;
3193 
3194  // Deal with memops first.
3195  if (isMemOp(MI)) {
3196  BasePos = 0;
3197  OffsetPos = 1;
3198  } else if (MI.mayStore()) {
3199  BasePos = 0;
3200  OffsetPos = 1;
3201  } else if (MI.mayLoad()) {
3202  BasePos = 1;
3203  OffsetPos = 2;
3204  } else
3205  return false;
3206 
3207  if (isPredicated(MI)) {
3208  BasePos++;
3209  OffsetPos++;
3210  }
3211  if (isPostIncrement(MI)) {
3212  BasePos++;
3213  OffsetPos++;
3214  }
3215 
3216  if (!MI.getOperand(BasePos).isReg() || !MI.getOperand(OffsetPos).isImm())
3217  return false;
3218 
3219  return true;
3220 }
3221 
3222 // Inserts branching instructions in reverse order of their occurrence.
3223 // e.g. jump_t t1 (i1)
3224 // jump t2 (i2)
3225 // Jumpers = {i2, i1}
3227  MachineBasicBlock& MBB) const {
3229  // If the block has no terminators, it just falls into the block after it.
3231  if (I == MBB.instr_begin())
3232  return Jumpers;
3233 
3234  // A basic block may looks like this:
3235  //
3236  // [ insn
3237  // EH_LABEL
3238  // insn
3239  // insn
3240  // insn
3241  // EH_LABEL
3242  // insn ]
3243  //
3244  // It has two succs but does not have a terminator
3245  // Don't know how to handle it.
3246  do {
3247  --I;
3248  if (I->isEHLabel())
3249  return Jumpers;
3250  } while (I != MBB.instr_begin());
3251 
3252  I = MBB.instr_end();
3253  --I;
3254 
3255  while (I->isDebugInstr()) {
3256  if (I == MBB.instr_begin())
3257  return Jumpers;
3258  --I;
3259  }
3260  if (!isUnpredicatedTerminator(*I))
3261  return Jumpers;
3262 
3263  // Get the last instruction in the block.
3264  MachineInstr *LastInst = &*I;
3265  Jumpers.push_back(LastInst);
3266  MachineInstr *SecondLastInst = nullptr;
3267  // Find one more terminator if present.
3268  do {
3269  if (&*I != LastInst && !I->isBundle() && isUnpredicatedTerminator(*I)) {
3270  if (!SecondLastInst) {
3271  SecondLastInst = &*I;
3272  Jumpers.push_back(SecondLastInst);
3273  } else // This is a third branch.
3274  return Jumpers;
3275  }
3276  if (I == MBB.instr_begin())
3277  break;
3278  --I;
3279  } while (true);
3280  return Jumpers;
3281 }
3282 
3283 // Returns Operand Index for the constant extended instruction.
3285  const uint64_t F = MI.getDesc().TSFlags;
3287 }
3288 
3289 // See if instruction could potentially be a duplex candidate.
3290 // If so, return its group. Zero otherwise.
3292  const MachineInstr &MI) const {
3293  unsigned DstReg, SrcReg, Src1Reg, Src2Reg;
3294 
3295  switch (MI.getOpcode()) {
3296  default:
3297  return HexagonII::HCG_None;
3298  //
3299  // Compound pairs.
3300  // "p0=cmp.eq(Rs16,Rt16); if (p0.new) jump:nt #r9:2"
3301  // "Rd16=#U6 ; jump #r9:2"
3302  // "Rd16=Rs16 ; jump #r9:2"
3303  //
3304  case Hexagon::C2_cmpeq:
3305  case Hexagon::C2_cmpgt:
3306  case Hexagon::C2_cmpgtu:
3307  DstReg = MI.getOperand(0).getReg();
3308  Src1Reg = MI.getOperand(1).getReg();
3309  Src2Reg = MI.getOperand(2).getReg();
3310  if (Hexagon::PredRegsRegClass.contains(DstReg) &&
3311  (Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
3312  isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg))
3313  return HexagonII::HCG_A;
3314  break;
3315  case Hexagon::C2_cmpeqi:
3316  case Hexagon::C2_cmpgti:
3317  case Hexagon::C2_cmpgtui:
3318  // P0 = cmp.eq(Rs,#u2)
3319  DstReg = MI.getOperand(0).getReg();
3320  SrcReg = MI.getOperand(1).getReg();
3321  if (Hexagon::PredRegsRegClass.contains(DstReg) &&
3322  (Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
3323  isIntRegForSubInst(SrcReg) && MI.getOperand(2).isImm() &&
3324  ((isUInt<5>(MI.getOperand(2).getImm())) ||
3325  (MI.getOperand(2).getImm() == -1)))
3326  return HexagonII::HCG_A;
3327  break;
3328  case Hexagon::A2_tfr:
3329  // Rd = Rs
3330  DstReg = MI.getOperand(0).getReg();
3331  SrcReg = MI.getOperand(1).getReg();
3332  if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg))
3333  return HexagonII::HCG_A;
3334  break;
3335  case Hexagon::A2_tfrsi:
3336  // Rd = #u6
3337  // Do not test for #u6 size since the const is getting extended
3338  // regardless and compound could be formed.
3339  DstReg = MI.getOperand(0).getReg();
3340  if (isIntRegForSubInst(DstReg))
3341  return HexagonII::HCG_A;
3342  break;
3343  case Hexagon::S2_tstbit_i:
3344  DstReg = MI.getOperand(0).getReg();
3345  Src1Reg = MI.getOperand(1).getReg();
3346  if (Hexagon::PredRegsRegClass.contains(DstReg) &&
3347  (Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
3348  MI.getOperand(2).isImm() &&
3349  isIntRegForSubInst(Src1Reg) && (MI.getOperand(2).getImm() == 0))
3350  return HexagonII::HCG_A;
3351  break;
3352  // The fact that .new form is used pretty much guarantees
3353  // that predicate register will match. Nevertheless,
3354  // there could be some false positives without additional
3355  // checking.
3356  case Hexagon::J2_jumptnew:
3357  case Hexagon::J2_jumpfnew:
3358  case Hexagon::J2_jumptnewpt:
3359  case Hexagon::J2_jumpfnewpt:
3360  Src1Reg = MI.getOperand(0).getReg();
3361  if (Hexagon::PredRegsRegClass.contains(Src1Reg) &&
3362  (Hexagon::P0 == Src1Reg || Hexagon::P1 == Src1Reg))
3363  return HexagonII::HCG_B;
3364  break;
3365  // Transfer and jump:
3366  // Rd=#U6 ; jump #r9:2
3367  // Rd=Rs ; jump #r9:2
3368  // Do not test for jump range here.
3369  case Hexagon::J2_jump:
3370  case Hexagon::RESTORE_DEALLOC_RET_JMP_V4:
3371  case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC:
3372  return HexagonII::HCG_C;
3373  }
3374 
3375  return HexagonII::HCG_None;
3376 }
3377 
3378 // Returns -1 when there is no opcode found.
3380  const MachineInstr &GB) const {
3383  if ((GA.getOpcode() != Hexagon::C2_cmpeqi) ||
3384  (GB.getOpcode() != Hexagon::J2_jumptnew))
3385  return -1u;
3386  Register DestReg = GA.getOperand(0).getReg();
3387  if (!GB.readsRegister(DestReg))
3388  return -1u;
3389  if (DestReg != Hexagon::P0 && DestReg != Hexagon::P1)
3390  return -1u;
3391  // The value compared against must be either u5 or -1.
3392  const MachineOperand &CmpOp = GA.getOperand(2);
3393  if (!CmpOp.isImm())
3394  return -1u;
3395  int V = CmpOp.getImm();
3396  if (V == -1)
3397  return DestReg == Hexagon::P0 ? Hexagon::J4_cmpeqn1_tp0_jump_nt
3398  : Hexagon::J4_cmpeqn1_tp1_jump_nt;
3399  if (!isUInt<5>(V))
3400  return -1u;
3401  return DestReg == Hexagon::P0 ? Hexagon::J4_cmpeqi_tp0_jump_nt
3402  : Hexagon::J4_cmpeqi_tp1_jump_nt;
3403 }
3404 
3405 int HexagonInstrInfo::getCondOpcode(int Opc, bool invertPredicate) const {
3406  enum Hexagon::PredSense inPredSense;
3407  inPredSense = invertPredicate ? Hexagon::PredSense_false :
3408  Hexagon::PredSense_true;
3409  int CondOpcode = Hexagon::getPredOpcode(Opc, inPredSense);
3410  if (CondOpcode >= 0) // Valid Conditional opcode/instruction
3411  return CondOpcode;
3412 
3413  llvm_unreachable("Unexpected predicable instruction");
3414 }
3415 
3416 // Return the cur value instruction for a given store.
3418  switch (MI.getOpcode()) {
3419  default: llvm_unreachable("Unknown .cur type");
3420  case Hexagon::V6_vL32b_pi:
3421  return Hexagon::V6_vL32b_cur_pi;
3422  case Hexagon::V6_vL32b_ai:
3423  return Hexagon::V6_vL32b_cur_ai;
3424  case Hexagon::V6_vL32b_nt_pi:
3425  return Hexagon::V6_vL32b_nt_cur_pi;
3426  case Hexagon::V6_vL32b_nt_ai:
3427  return Hexagon::V6_vL32b_nt_cur_ai;
3428  }
3429  return 0;
3430 }
3431 
3432 // Return the regular version of the .cur instruction.
3434  switch (MI.getOpcode()) {
3435  default: llvm_unreachable("Unknown .cur type");
3436  case Hexagon::V6_vL32b_cur_pi:
3437  return Hexagon::V6_vL32b_pi;
3438  case Hexagon::V6_vL32b_cur_ai:
3439  return Hexagon::V6_vL32b_ai;
3440  case Hexagon::V6_vL32b_nt_cur_pi:
3441  return Hexagon::V6_vL32b_nt_pi;
3442  case Hexagon::V6_vL32b_nt_cur_ai:
3443  return Hexagon::V6_vL32b_nt_ai;
3444  }
3445  return 0;
3446 }
3447 
3448 // The diagram below shows the steps involved in the conversion of a predicated
3449 // store instruction to its .new predicated new-value form.
3450 //
3451 // Note: It doesn't include conditional new-value stores as they can't be
3452 // converted to .new predicate.
3453 //
3454 // p.new NV store [ if(p0.new)memw(R0+#0)=R2.new ]
3455 // ^ ^
3456 // / \ (not OK. it will cause new-value store to be
3457 // / X conditional on p0.new while R2 producer is
3458 // / \ on p0)
3459 // / \.
3460 // p.new store p.old NV store
3461 // [if(p0.new)memw(R0+#0)=R2] [if(p0)memw(R0+#0)=R2.new]
3462 // ^ ^
3463 // \ /
3464 // \ /
3465 // \ /
3466 // p.old store
3467 // [if (p0)memw(R0+#0)=R2]
3468 //
3469 // The following set of instructions further explains the scenario where
3470 // conditional new-value store becomes invalid when promoted to .new predicate
3471 // form.
3472 //
3473 // { 1) if (p0) r0 = add(r1, r2)
3474 // 2) p0 = cmp.eq(r3, #0) }
3475 //
3476 // 3) if (p0) memb(r1+#0) = r0 --> this instruction can't be grouped with
3477 // the first two instructions because in instr 1, r0 is conditional on old value
3478 // of p0 but its use in instr 3 is conditional on p0 modified by instr 2 which
3479 // is not valid for new-value stores.
3480 // Predicated new value stores (i.e. if (p0) memw(..)=r0.new) are excluded
3481 // from the "Conditional Store" list. Because a predicated new value store
3482 // would NOT be promoted to a double dot new store. See diagram below:
3483 // This function returns yes for those stores that are predicated but not
3484 // yet promoted to predicate dot new instructions.
3485 //
3486 // +---------------------+
3487 // /-----| if (p0) memw(..)=r0 |---------\~
3488 // || +---------------------+ ||
3489 // promote || /\ /\ || promote
3490 // || /||\ /||\ ||
3491 // \||/ demote || \||/
3492 // \/ || || \/
3493 // +-------------------------+ || +-------------------------+
3494 // | if (p0.new) memw(..)=r0 | || | if (p0) memw(..)=r0.new |
3495 // +-------------------------+ || +-------------------------+
3496 // || || ||
3497 // || demote \||/
3498 // promote || \/ NOT possible
3499 // || || /\~
3500 // \||/ || /||\~
3501 // \/ || ||
3502 // +-----------------------------+
3503 // | if (p0.new) memw(..)=r0.new |
3504 // +-----------------------------+
3505 // Double Dot New Store
3506 //
3507 // Returns the most basic instruction for the .new predicated instructions and
3508 // new-value stores.
3509 // For example, all of the following instructions will be converted back to the
3510 // same instruction:
3511 // 1) if (p0.new) memw(R0+#0) = R1.new --->
3512 // 2) if (p0) memw(R0+#0)= R1.new -------> if (p0) memw(R0+#0) = R1
3513 // 3) if (p0.new) memw(R0+#0) = R1 --->
3514 //
3515 // To understand the translation of instruction 1 to its original form, consider
3516 // a packet with 3 instructions.
3517 // { p0 = cmp.eq(R0,R1)
3518 // if (p0.new) R2 = add(R3, R4)
3519 // R5 = add (R3, R1)
3520 // }
3521 // if (p0) memw(R5+#0) = R2 <--- trying to include it in the previous packet
3522 //
3523 // This instruction can be part of the previous packet only if both p0 and R2
3524 // are promoted to .new values. This promotion happens in steps, first
3525 // predicate register is promoted to .new and in the next iteration R2 is
3526 // promoted. Therefore, in case of dependence check failure (due to R5) during
3527 // next iteration, it should be converted back to its most basic form.
3528 
3529 // Return the new value instruction for a given store.
3531  int NVOpcode = Hexagon::getNewValueOpcode(MI.getOpcode());
3532  if (NVOpcode >= 0) // Valid new-value store instruction.
3533  return NVOpcode;
3534 
3535  switch (MI.getOpcode()) {
3536  default:
3537  report_fatal_error(std::string("Unknown .new type: ") +
3538  std::to_string(MI.getOpcode()));
3539  case Hexagon::S4_storerb_ur:
3540  return Hexagon::S4_storerbnew_ur;
3541 
3542  case Hexagon::S2_storerb_pci:
3543  return Hexagon::S2_storerb_pci;
3544 
3545  case Hexagon::S2_storeri_pci:
3546  return Hexagon::S2_storeri_pci;
3547 
3548  case Hexagon::S2_storerh_pci:
3549  return Hexagon::S2_storerh_pci;
3550 
3551  case Hexagon::S2_storerd_pci:
3552  return Hexagon::S2_storerd_pci;
3553 
3554  case Hexagon::S2_storerf_pci:
3555  return Hexagon::S2_storerf_pci;
3556 
3557  case Hexagon::V6_vS32b_ai:
3558  return Hexagon::V6_vS32b_new_ai;
3559 
3560  case Hexagon::V6_vS32b_pi:
3561  return Hexagon::V6_vS32b_new_pi;
3562  }
3563  return 0;
3564 }
3565 
3566 // Returns the opcode to use when converting MI, which is a conditional jump,
3567 // into a conditional instruction which uses the .new value of the predicate.
3568 // We also use branch probabilities to add a hint to the jump.
3569 // If MBPI is null, all edges will be treated as equally likely for the
3570 // purposes of establishing a predication hint.
3572  const MachineBranchProbabilityInfo *MBPI) const {
3573  // We assume that block can have at most two successors.
3574  const MachineBasicBlock *Src = MI.getParent();
3575  const MachineOperand &BrTarget = MI.getOperand(1);
3576  bool Taken = false;
3577  const BranchProbability OneHalf(1, 2);
3578 
3579  auto getEdgeProbability = [MBPI] (const MachineBasicBlock *Src,
3580  const MachineBasicBlock *Dst) {
3581  if (MBPI)
3582  return MBPI->getEdgeProbability(Src, Dst);
3583  return BranchProbability(1, Src->succ_size());
3584  };
3585 
3586  if (BrTarget.isMBB()) {
3587  const MachineBasicBlock *Dst = BrTarget.getMBB();
3588  Taken = getEdgeProbability(Src, Dst) >= OneHalf;
3589  } else {
3590  // The branch target is not a basic block (most likely a function).
3591  // Since BPI only gives probabilities for targets that are basic blocks,
3592  // try to identify another target of this branch (potentially a fall-
3593  // -through) and check the probability of that target.
3594  //
3595  // The only handled branch combinations are:
3596  // - one conditional branch,
3597  // - one conditional branch followed by one unconditional branch.
3598  // Otherwise, assume not-taken.
3600  const MachineBasicBlock &B = *MI.getParent();
3601  bool SawCond = false, Bad = false;
3602  for (const MachineInstr &I : B) {
3603  if (!I.isBranch())
3604  continue;
3605  if (I.isConditionalBranch()) {
3606  SawCond = true;
3607  if (&I != &MI) {
3608  Bad = true;
3609  break;
3610  }
3611  }
3612  if (I.isUnconditionalBranch() && !SawCond) {
3613  Bad = true;
3614  break;
3615  }
3616  }
3617  if (!Bad) {
3619  MachineBasicBlock::const_instr_iterator NextIt = std::next(It);
3620  if (NextIt == B.instr_end()) {
3621  // If this branch is the last, look for the fall-through block.
3622  for (const MachineBasicBlock *SB : B.successors()) {
3623  if (!B.isLayoutSuccessor(SB))
3624  continue;
3625  Taken = getEdgeProbability(Src, SB) < OneHalf;
3626  break;
3627  }
3628  } else {
3629  assert(NextIt->isUnconditionalBranch());
3630  // Find the first MBB operand and assume it's the target.
3631  const MachineBasicBlock *BT = nullptr;
3632  for (const MachineOperand &Op : NextIt->operands()) {
3633  if (!Op.isMBB())
3634  continue;
3635  BT = Op.getMBB();
3636  break;
3637  }
3638  Taken = BT && getEdgeProbability(Src, BT) < OneHalf;
3639  }
3640  } // if (!Bad)
3641  }
3642 
3643  // The Taken flag should be set to something reasonable by this point.
3644 
3645  switch (MI.getOpcode()) {
3646  case Hexagon::J2_jumpt:
3647  return Taken ? Hexagon::J2_jumptnewpt : Hexagon::J2_jumptnew;
3648  case Hexagon::J2_jumpf:
3649  return Taken ? Hexagon::J2_jumpfnewpt : Hexagon::J2_jumpfnew;
3650 
3651  default:
3652  llvm_unreachable("Unexpected jump instruction.");
3653  }
3654 }
3655 
3656 // Return .new predicate version for an instruction.
3658  const MachineBranchProbabilityInfo *MBPI) const {
3659  switch (MI.getOpcode()) {
3660  // Condtional Jumps
3661  case Hexagon::J2_jumpt:
3662  case Hexagon::J2_jumpf:
3663  return getDotNewPredJumpOp(MI, MBPI);
3664  }
3665 
3666  int NewOpcode = Hexagon::getPredNewOpcode(MI.getOpcode());
3667  if (NewOpcode >= 0)
3668  return NewOpcode;
3669  return 0;
3670 }
3671 
3673  int NewOp = MI.getOpcode();
3674  if (isPredicated(NewOp) && isPredicatedNew(NewOp)) { // Get predicate old form
3675  NewOp = Hexagon::getPredOldOpcode(NewOp);
3676  // All Hexagon architectures have prediction bits on dot-new branches,
3677  // but only Hexagon V60+ has prediction bits on dot-old ones. Make sure
3678  // to pick the right opcode when converting back to dot-old.
3679  if (!Subtarget.getFeatureBits()[Hexagon::ArchV60]) {
3680  switch (NewOp) {
3681  case Hexagon::J2_jumptpt:
3682  NewOp = Hexagon::J2_jumpt;
3683  break;
3684  case Hexagon::J2_jumpfpt:
3685  NewOp = Hexagon::J2_jumpf;
3686  break;
3687  case Hexagon::J2_jumprtpt:
3688  NewOp = Hexagon::J2_jumprt;
3689  break;
3690  case Hexagon::J2_jumprfpt:
3691  NewOp = Hexagon::J2_jumprf;
3692  break;
3693  }
3694  }
3695  assert(NewOp >= 0 &&
3696  "Couldn't change predicate new instruction to its old form.");
3697  }
3698 
3699  if (isNewValueStore(NewOp)) { // Convert into non-new-value format
3700  NewOp = Hexagon::getNonNVStore(NewOp);
3701  assert(NewOp >= 0 && "Couldn't change new-value store to its old form.");
3702  }
3703 
3704  if (Subtarget.hasV60Ops())
3705  return NewOp;
3706 
3707  // Subtargets prior to V60 didn't support 'taken' forms of predicated jumps.
3708  switch (NewOp) {
3709  case Hexagon::J2_jumpfpt:
3710  return Hexagon::J2_jumpf;
3711  case Hexagon::J2_jumptpt:
3712  return Hexagon::J2_jumpt;
3713  case Hexagon::J2_jumprfpt:
3714  return Hexagon::J2_jumprf;
3715  case Hexagon::J2_jumprtpt:
3716  return Hexagon::J2_jumprt;
3717  }
3718  return NewOp;
3719 }
3720 
3721 // See if instruction could potentially be a duplex candidate.
3722 // If so, return its group. Zero otherwise.
3724  const MachineInstr &MI) const {
3725  unsigned DstReg, SrcReg, Src1Reg, Src2Reg;
3726  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
3727 
3728  switch (MI.getOpcode()) {
3729  default:
3730  return HexagonII::HSIG_None;
3731  //
3732  // Group L1:
3733  //
3734  // Rd = memw(Rs+#u4:2)
3735  // Rd = memub(Rs+#u4:0)
3736  case Hexagon::L2_loadri_io:
3737  DstReg = MI.getOperand(0).getReg();
3738  SrcReg = MI.getOperand(1).getReg();
3739  // Special case this one from Group L2.
3740  // Rd = memw(r29+#u5:2)
3741  if (isIntRegForSubInst(DstReg)) {
3742  if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
3743  HRI.getStackRegister() == SrcReg &&
3744  MI.getOperand(2).isImm() &&
3745  isShiftedUInt<5,2>(MI.getOperand(2).getImm()))
3746  return HexagonII::HSIG_L2;
3747  // Rd = memw(Rs+#u4:2)
3748  if (isIntRegForSubInst(SrcReg) &&
3749  (MI.getOperand(2).isImm() &&
3750  isShiftedUInt<4,2>(MI.getOperand(2).getImm())))
3751  return HexagonII::HSIG_L1;
3752  }
3753  break;
3754  case Hexagon::L2_loadrub_io:
3755  // Rd = memub(Rs+#u4:0)
3756  DstReg = MI.getOperand(0).getReg();
3757  SrcReg = MI.getOperand(1).getReg();
3758  if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg) &&
3759  MI.getOperand(2).isImm() && isUInt<4>(MI.getOperand(2).getImm()))
3760  return HexagonII::HSIG_L1;
3761  break;
3762  //
3763  // Group L2:
3764  //
3765  // Rd = memh/memuh(Rs+#u3:1)
3766  // Rd = memb(Rs+#u3:0)
3767  // Rd = memw(r29+#u5:2) - Handled above.
3768  // Rdd = memd(r29+#u5:3)
3769  // deallocframe
3770  // [if ([!]p0[.new])] dealloc_return
3771  // [if ([!]p0[.new])] jumpr r31
3772  case Hexagon::L2_loadrh_io:
3773  case Hexagon::L2_loadruh_io:
3774  // Rd = memh/memuh(Rs+#u3:1)
3775  DstReg = MI.getOperand(0).getReg();
3776  SrcReg = MI.getOperand(1).getReg();
3777  if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg) &&
3778  MI.getOperand(2).isImm() &&
3779  isShiftedUInt<3,1>(MI.getOperand(2).getImm()))
3780  return HexagonII::HSIG_L2;
3781  break;
3782  case Hexagon::L2_loadrb_io:
3783  // Rd = memb(Rs+#u3:0)
3784  DstReg = MI.getOperand(0).getReg();
3785  SrcReg = MI.getOperand(1).getReg();
3786  if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg) &&
3787  MI.getOperand(2).isImm() &&
3788  isUInt<3>(MI.getOperand(2).getImm()))
3789  return HexagonII::HSIG_L2;
3790  break;
3791  case Hexagon::L2_loadrd_io:
3792  // Rdd = memd(r29+#u5:3)
3793  DstReg = MI.getOperand(0).getReg();
3794  SrcReg = MI.getOperand(1).getReg();
3795  if (isDblRegForSubInst(DstReg, HRI) &&
3796  Hexagon::IntRegsRegClass.contains(SrcReg) &&
3797  HRI.getStackRegister() == SrcReg &&
3798  MI.getOperand(2).isImm() &&
3799  isShiftedUInt<5,3>(MI.getOperand(2).getImm()))
3800  return HexagonII::HSIG_L2;
3801  break;
3802  // dealloc_return is not documented in Hexagon Manual, but marked
3803  // with A_SUBINSN attribute in iset_v4classic.py.
3804  case Hexagon::RESTORE_DEALLOC_RET_JMP_V4:
3805  case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC:
3806  case Hexagon::L4_return:
3807  case Hexagon::L2_deallocframe:
3808  return HexagonII::HSIG_L2;
3809  case Hexagon::EH_RETURN_JMPR:
3810  case Hexagon::PS_jmpret:
3811  case Hexagon::SL2_jumpr31:
3812  // jumpr r31
3813  // Actual form JMPR implicit-def %pc, implicit %r31, implicit internal %r0
3814  DstReg = MI.getOperand(0).getReg();
3815  if (Hexagon::IntRegsRegClass.contains(DstReg) && (Hexagon::R31 == DstReg))
3816  return HexagonII::HSIG_L2;
3817  break;
3818  case Hexagon::PS_jmprett:
3819  case Hexagon::PS_jmpretf:
3820  case Hexagon::PS_jmprettnewpt:
3821  case Hexagon::PS_jmpretfnewpt:
3822  case Hexagon::PS_jmprettnew:
3823  case Hexagon::PS_jmpretfnew:
3824  case Hexagon::SL2_jumpr31_t:
3825  case Hexagon::SL2_jumpr31_f:
3826  case Hexagon::SL2_jumpr31_tnew:
3827  DstReg = MI.getOperand(1).getReg();
3828  SrcReg = MI.getOperand(0).getReg();
3829  // [if ([!]p0[.new])] jumpr r31
3830  if ((Hexagon::PredRegsRegClass.contains(SrcReg) &&
3831  (Hexagon::P0 == SrcReg)) &&
3832  (Hexagon::IntRegsRegClass.contains(DstReg) && (Hexagon::R31 == DstReg)))
3833  return HexagonII::HSIG_L2;
3834  break;
3835  case Hexagon::L4_return_t:
3836  case Hexagon::L4_return_f:
3837  case Hexagon::L4_return_tnew_pnt:
3838  case Hexagon::L4_return_fnew_pnt:
3839  case Hexagon::L4_return_tnew_pt:
3840  case Hexagon::L4_return_fnew_pt:
3841  // [if ([!]p0[.new])] dealloc_return
3842  SrcReg = MI.getOperand(0).getReg();
3843  if (Hexagon::PredRegsRegClass.contains(SrcReg) && (Hexagon::P0 == SrcReg))
3844  return HexagonII::HSIG_L2;
3845  break;
3846  //
3847  // Group S1:
3848  //
3849  // memw(Rs+#u4:2) = Rt
3850  // memb(Rs+#u4:0) = Rt
3851  case Hexagon::S2_storeri_io:
3852  // Special case this one from Group S2.
3853  // memw(r29+#u5:2) = Rt
3854  Src1Reg = MI.getOperand(0).getReg();
3855  Src2Reg = MI.getOperand(2).getReg();
3856  if (Hexagon::IntRegsRegClass.contains(Src1Reg) &&
3857  isIntRegForSubInst(Src2Reg) &&
3858  HRI.getStackRegister() == Src1Reg && MI.getOperand(1).isImm() &&
3859  isShiftedUInt<5,2>(MI.getOperand(1).getImm()))
3860  return HexagonII::HSIG_S2;
3861  // memw(Rs+#u4:2) = Rt
3862  if (isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg) &&
3863  MI.getOperand(1).isImm() &&
3864  isShiftedUInt<4,2>(MI.getOperand(1).getImm()))
3865  return HexagonII::HSIG_S1;
3866  break;
3867  case Hexagon::S2_storerb_io:
3868  // memb(Rs+#u4:0) = Rt
3869  Src1Reg = MI.getOperand(0).getReg();
3870  Src2Reg = MI.getOperand(2).getReg();
3871  if (isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg) &&
3872  MI.getOperand(1).isImm() && isUInt<4>(MI.getOperand(1).getImm()))
3873  return HexagonII::HSIG_S1;
3874  break;
3875  //
3876  // Group S2:
3877  //
3878  // memh(Rs+#u3:1) = Rt
3879  // memw(r29+#u5:2) = Rt
3880  // memd(r29+#s6:3) = Rtt
3881  // memw(Rs+#u4:2) = #U1
3882  // memb(Rs+#u4) = #U1
3883  // allocframe(#u5:3)
3884  case Hexagon::S2_storerh_io:
3885  // memh(Rs+#u3:1) = Rt
3886  Src1Reg = MI.getOperand(0).getReg();
3887  Src2Reg = MI.getOperand(2).getReg();
3888  if (isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg) &&
3889  MI.getOperand(1).isImm() &&
3890  isShiftedUInt<3,1>(MI.getOperand(1).getImm()))
3891  return HexagonII::HSIG_S1;
3892  break;
3893  case Hexagon::S2_storerd_io:
3894  // memd(r29+#s6:3) = Rtt
3895  Src1Reg = MI.getOperand(0).getReg();
3896  Src2Reg = MI.getOperand(2).getReg();
3897  if (isDblRegForSubInst(Src2Reg, HRI) &&
3898  Hexagon::IntRegsRegClass.contains(Src1Reg) &&
3899  HRI.getStackRegister() == Src1Reg && MI.getOperand(1).isImm() &&
3900  isShiftedInt<6,3>(MI.getOperand(1).getImm()))
3901  return HexagonII::HSIG_S2;
3902  break;
3903  case Hexagon::S4_storeiri_io:
3904  // memw(Rs+#u4:2) = #U1
3905  Src1Reg = MI.getOperand(0).getReg();
3906  if (isIntRegForSubInst(Src1Reg) && MI.getOperand(1).isImm() &&
3907  isShiftedUInt<4,2>(MI.getOperand(1).getImm()) &&
3908  MI.getOperand(2).isImm() && isUInt<1>(MI.getOperand(2).getImm()))
3909  return HexagonII::HSIG_S2;
3910  break;
3911  case Hexagon::S4_storeirb_io:
3912  // memb(Rs+#u4) = #U1
3913  Src1Reg = MI.getOperand(0).getReg();
3914  if (isIntRegForSubInst(Src1Reg) &&
3915  MI.getOperand(1).isImm() && isUInt<4>(MI.getOperand(1).getImm()) &&
3916  MI.getOperand(2).isImm() && isUInt<1>(MI.getOperand(2).getImm()))
3917  return HexagonII::HSIG_S2;
3918  break;
3919  case Hexagon::S2_allocframe:
3920  if (MI.getOperand(2).isImm() &&
3921  isShiftedUInt<5,3>(MI.getOperand(2).getImm()))
3922  return HexagonII::HSIG_S1;
3923  break;
3924  //
3925  // Group A:
3926  //
3927  // Rx = add(Rx,#s7)
3928  // Rd = Rs
3929  // Rd = #u6
3930  // Rd = #-1
3931  // if ([!]P0[.new]) Rd = #0
3932  // Rd = add(r29,#u6:2)
3933  // Rx = add(Rx,Rs)
3934  // P0 = cmp.eq(Rs,#u2)
3935  // Rdd = combine(#0,Rs)
3936  // Rdd = combine(Rs,#0)
3937  // Rdd = combine(#u2,#U2)
3938  // Rd = add(Rs,#1)
3939  // Rd = add(Rs,#-1)
3940  // Rd = sxth/sxtb/zxtb/zxth(Rs)
3941  // Rd = and(Rs,#1)
3942  case Hexagon::A2_addi:
3943  DstReg = MI.getOperand(0).getReg();
3944  SrcReg = MI.getOperand(1).getReg();
3945  if (isIntRegForSubInst(DstReg)) {
3946  // Rd = add(r29,#u6:2)
3947  if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
3948  HRI.getStackRegister() == SrcReg && MI.getOperand(2).isImm() &&
3949  isShiftedUInt<6,2>(MI.getOperand(2).getImm()))
3950  return HexagonII::HSIG_A;
3951  // Rx = add(Rx,#s7)
3952  if ((DstReg == SrcReg) && MI.getOperand(2).isImm() &&
3953  isInt<7>(MI.getOperand(2).getImm()))
3954  return HexagonII::HSIG_A;
3955  // Rd = add(Rs,#1)
3956  // Rd = add(Rs,#-1)
3957  if (isIntRegForSubInst(SrcReg) && MI.getOperand(2).isImm() &&
3958  ((MI.getOperand(2).getImm() == 1) ||
3959  (MI.getOperand(2).getImm() == -1)))
3960  return HexagonII::HSIG_A;
3961  }
3962  break;
3963  case Hexagon::A2_add:
3964  // Rx = add(Rx,Rs)
3965  DstReg = MI.getOperand(0).getReg();
3966  Src1Reg = MI.getOperand(1).getReg();
3967  Src2Reg = MI.getOperand(2).getReg();
3968  if (isIntRegForSubInst(DstReg) && (DstReg == Src1Reg) &&
3969  isIntRegForSubInst(Src2Reg))
3970  return HexagonII::HSIG_A;
3971  break;
3972  case Hexagon::A2_andir:
3973  // Same as zxtb.
3974  // Rd16=and(Rs16,#255)
3975  // Rd16=and(Rs16,#1)
3976  DstReg = MI.getOperand(0).getReg();
3977  SrcReg = MI.getOperand(1).getReg();
3978  if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg) &&
3979  MI.getOperand(2).isImm() &&
3980  ((MI.getOperand(2).getImm() == 1) ||
3981  (MI.getOperand(2).getImm() == 255)))
3982  return HexagonII::HSIG_A;
3983  break;
3984  case Hexagon::A2_tfr:
3985  // Rd = Rs
3986  DstReg = MI.getOperand(0).getReg();
3987  SrcReg = MI.getOperand(1).getReg();
3988  if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg))
3989  return HexagonII::HSIG_A;
3990  break;
3991  case Hexagon::A2_tfrsi:
3992  // Rd = #u6
3993  // Do not test for #u6 size since the const is getting extended
3994  // regardless and compound could be formed.
3995  // Rd = #-1
3996  DstReg = MI.getOperand(0).getReg();
3997  if (isIntRegForSubInst(DstReg))
3998  return HexagonII::HSIG_A;
3999  break;
4000  case Hexagon::C2_cmoveit:
4001  case Hexagon::C2_cmovenewit:
4002  case Hexagon::C2_cmoveif:
4003  case Hexagon::C2_cmovenewif:
4004  // if ([!]P0[.new]) Rd = #0
4005  // Actual form:
4006  // %r16 = C2_cmovenewit internal %p0, 0, implicit undef %r16;
4007  DstReg = MI.getOperand(0).getReg();
4008  SrcReg = MI.getOperand(1).getReg();
4009  if (isIntRegForSubInst(DstReg) &&
4010  Hexagon::PredRegsRegClass.contains(SrcReg) && Hexagon::P0 == SrcReg &&
4011  MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0)
4012  return HexagonII::HSIG_A;
4013  break;
4014  case Hexagon::C2_cmpeqi:
4015  // P0 = cmp.eq(Rs,#u2)
4016  DstReg = MI.getOperand(0).getReg();
4017  SrcReg = MI.getOperand(1).getReg();
4018  if (Hexagon::PredRegsRegClass.contains(DstReg) &&
4019  Hexagon::P0 == DstReg && isIntRegForSubInst(SrcReg) &&
4020  MI.getOperand(2).isImm() && isUInt<2>(MI.getOperand(2).getImm()))
4021  return HexagonII::HSIG_A;
4022  break;
4023  case Hexagon::A2_combineii:
4024  case Hexagon::A4_combineii:
4025  // Rdd = combine(#u2,#U2)
4026  DstReg = MI.getOperand(0).getReg();
4027  if (isDblRegForSubInst(DstReg, HRI) &&
4028  ((MI.getOperand(1).isImm() && isUInt<2>(MI.getOperand(1).getImm())) ||
4029  (MI.getOperand(1).isGlobal() &&
4030  isUInt<2>(MI.getOperand(1).getOffset()))) &&
4031  ((MI.getOperand(2).isImm() && isUInt<2>(MI.getOperand(2).getImm())) ||
4032  (MI.getOperand(2).isGlobal() &&
4033  isUInt<2>(MI.getOperand(2).getOffset()))))
4034  return HexagonII::HSIG_A;
4035  break;
4036  case Hexagon::A4_combineri:
4037  // Rdd = combine(Rs,#0)
4038  DstReg = MI.getOperand(0).getReg();
4039  SrcReg = MI.getOperand(1).getReg();
4040  if (isDblRegForSubInst(DstReg, HRI) && isIntRegForSubInst(SrcReg) &&
4041  ((MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0) ||
4042  (MI.getOperand(2).isGlobal() && MI.getOperand(2).getOffset() == 0)))
4043  return HexagonII::HSIG_A;
4044  break;
4045  case Hexagon::A4_combineir:
4046  // Rdd = combine(#0,Rs)
4047  DstReg = MI.getOperand(0).getReg();
4048  SrcReg = MI.getOperand(2).getReg();
4049  if (isDblRegForSubInst(DstReg, HRI) && isIntRegForSubInst(SrcReg) &&
4050  ((MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == 0) ||
4051  (MI.getOperand(1).isGlobal() && MI.getOperand(1).getOffset() == 0)))
4052  return HexagonII::HSIG_A;
4053  break;
4054  case Hexagon::A2_sxtb:
4055  case Hexagon::A2_sxth:
4056  case Hexagon::A2_zxtb:
4057  case Hexagon::A2_zxth:
4058  // Rd = sxth/sxtb/zxtb/zxth(Rs)
4059  DstReg = MI.getOperand(0).getReg();
4060  SrcReg = MI.getOperand(1).getReg();
4061  if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg))
4062  return HexagonII::HSIG_A;
4063  break;
4064  }
4065 
4066  return HexagonII::HSIG_None;
4067 }
4068 
4070  return Hexagon::getRealHWInstr(MI.getOpcode(), Hexagon::InstrType_Real);
4071 }
4072 
4074  const InstrItineraryData *ItinData, const MachineInstr &MI) const {
4075  // Default to one cycle for no itinerary. However, an "empty" itinerary may
4076  // still have a MinLatency property, which getStageLatency checks.
4077  if (!ItinData)
4078  return getInstrLatency(ItinData, MI);
4079 
4080  if (MI.isTransient())
4081  return 0;
4082  return ItinData->getStageLatency(MI.getDesc().getSchedClass());
4083 }
4084 
4085 /// getOperandLatency - Compute and return the use operand latency of a given
4086 /// pair of def and use.
4087 /// In most cases, the static scheduling itinerary was enough to determine the
4088 /// operand latency. But it may not be possible for instructions with variable
4089 /// number of defs / uses.
4090 ///
4091 /// This is a raw interface to the itinerary that may be directly overriden by
4092 /// a target. Use computeOperandLatency to get the best estimate of latency.
4094  const MachineInstr &DefMI,
4095  unsigned DefIdx,
4096  const MachineInstr &UseMI,
4097  unsigned UseIdx) const {
4098  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
4099 
4100  // Get DefIdx and UseIdx for super registers.
4101  const MachineOperand &DefMO = DefMI.getOperand(DefIdx);
4102 
4103  if (DefMO.isReg() && Register::isPhysicalRegister(DefMO.getReg())) {
4104  if (DefMO.isImplicit()) {
4105  for (MCSuperRegIterator SR(DefMO.getReg(), &HRI); SR.isValid(); ++SR) {
4106  int Idx = DefMI.findRegisterDefOperandIdx(*SR, false, false, &HRI);
4107  if (Idx != -1) {
4108  DefIdx = Idx;
4109  break;
4110  }
4111  }
4112  }
4113 
4114  const MachineOperand &UseMO = UseMI.getOperand(UseIdx);
4115  if (UseMO.isImplicit()) {
4116  for (MCSuperRegIterator SR(UseMO.getReg(), &HRI); SR.isValid(); ++SR) {
4117  int Idx = UseMI.findRegisterUseOperandIdx(*SR, false, &HRI);
4118  if (Idx != -1) {
4119  UseIdx = Idx;
4120  break;
4121  }
4122  }
4123  }
4124  }
4125 
4126  int Latency = TargetInstrInfo::getOperandLatency(ItinData, DefMI, DefIdx,
4127  UseMI, UseIdx);
4128  if (!Latency)
4129  // We should never have 0 cycle latency between two instructions unless
4130  // they can be packetized together. However, this decision can't be made
4131  // here.
4132  Latency = 1;
4133  return Latency;
4134 }
4135 
4136 // inverts the predication logic.
4137 // p -> NotP
4138 // NotP -> P
4140  SmallVectorImpl<MachineOperand> &Cond) const {
4141  if (Cond.empty())
4142  return false;
4143  unsigned Opc = getInvertedPredicatedOpcode(Cond[0].getImm());
4144  Cond[0].setImm(Opc);
4145  return true;
4146 }
4147 
4148 unsigned HexagonInstrInfo::getInvertedPredicatedOpcode(const int Opc) const {
4149  int InvPredOpcode;
4150  InvPredOpcode = isPredicatedTrue(Opc) ? Hexagon::getFalsePredOpcode(Opc)
4151  : Hexagon::getTruePredOpcode(Opc);
4152  if (InvPredOpcode >= 0) // Valid instruction with the inverted predicate.
4153  return InvPredOpcode;
4154 
4155  llvm_unreachable("Unexpected predicated instruction");
4156 }
4157 
4158 // Returns the max value that doesn't need to be extended.
4160  const uint64_t F = MI.getDesc().TSFlags;
4161  unsigned isSigned = (F >> HexagonII::ExtentSignedPos)
4163  unsigned bits = (F >> HexagonII::ExtentBitsPos)
4165 
4166  if (isSigned) // if value is signed
4167  return ~(-1U << (bits - 1));
4168  else
4169  return ~(-1U << bits);
4170 }
4171 
4172 
4174  switch (MI.getOpcode()) {
4175  case Hexagon::L2_loadrbgp:
4176  case Hexagon::L2_loadrdgp:
4177  case Hexagon::L2_loadrhgp:
4178  case Hexagon::L2_loadrigp:
4179  case Hexagon::L2_loadrubgp:
4180  case Hexagon::L2_loadruhgp:
4181  case Hexagon::S2_storerbgp:
4182  case Hexagon::S2_storerbnewgp:
4183  case Hexagon::S2_storerhgp:
4184  case Hexagon::S2_storerhnewgp:
4185  case Hexagon::S2_storerigp:
4186  case Hexagon::S2_storerinewgp:
4187  case Hexagon::S2_storerdgp:
4188  case Hexagon::S2_storerfgp:
4189  return true;
4190  }
4191  const uint64_t F = MI.getDesc().TSFlags;
4192  unsigned addrMode =
4194  // Disallow any base+offset instruction. The assembler does not yet reorder
4195  // based up any zero offset instruction.
4196  return (addrMode == HexagonII::BaseRegOffset ||
4197  addrMode == HexagonII::BaseImmOffset ||
4198  addrMode == HexagonII::BaseLongOffset);
4199 }
4200 
4202  using namespace HexagonII;
4203 
4204  const uint64_t F = MI.getDesc().TSFlags;
4205  unsigned S = (F >> MemAccessSizePos) & MemAccesSizeMask;
4207  if (Size != 0)
4208  return Size;
4209 
4210  // Handle vector access sizes.
4211  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
4212  switch (S) {
4214  return HRI.getSpillSize(Hexagon::HvxVRRegClass);
4215  default:
4216  llvm_unreachable("Unexpected instruction");
4217  }
4218 }
4219 
4220 // Returns the min value that doesn't need to be extended.
4222  const uint64_t F = MI.getDesc().TSFlags;
4223  unsigned isSigned = (F >> HexagonII::ExtentSignedPos)
4225  unsigned bits = (F >> HexagonII::ExtentBitsPos)
4227 
4228  if (isSigned) // if value is signed
4229  return -1U << (bits - 1);
4230  else
4231  return 0;
4232 }
4233 
4234 // Returns opcode of the non-extended equivalent instruction.
4236  // Check if the instruction has a register form that uses register in place
4237  // of the extended operand, if so return that as the non-extended form.
4238  short NonExtOpcode = Hexagon::getRegForm(MI.getOpcode());
4239  if (NonExtOpcode >= 0)
4240  return NonExtOpcode;
4241 
4242  if (MI.getDesc().mayLoad() || MI.getDesc().mayStore()) {
4243  // Check addressing mode and retrieve non-ext equivalent instruction.
4244  switch (getAddrMode(MI)) {
4245  case HexagonII::Absolute:
4246  return Hexagon::changeAddrMode_abs_io(MI.getOpcode());
4248  return Hexagon::changeAddrMode_io_rr(MI.getOpcode());
4250  return Hexagon::changeAddrMode_ur_rr(MI.getOpcode());
4251 
4252  default:
4253  return -1;
4254  }
4255  }
4256  return -1;
4257 }
4258 
4260  unsigned &PredReg, unsigned &PredRegPos, unsigned &PredRegFlags) const {
4261  if (Cond.empty())
4262  return false;
4263  assert(Cond.size() == 2);
4264  if (isNewValueJump(Cond[0].getImm()) || Cond[1].isMBB()) {
4265  LLVM_DEBUG(dbgs() << "No predregs for new-value jumps/endloop");
4266  return false;
4267  }
4268  PredReg = Cond[1].getReg();
4269  PredRegPos = 1;
4270  // See IfConversion.cpp why we add RegState::Implicit | RegState::Undef
4271  PredRegFlags = 0;
4272  if (Cond[1].isImplicit())
4273  PredRegFlags = RegState::Implicit;
4274  if (Cond[1].isUndef())
4275  PredRegFlags |= RegState::Undef;
4276  return true;
4277 }
4278 
4280  return Hexagon::getRealHWInstr(MI.getOpcode(), Hexagon::InstrType_Pseudo);
4281 }
4282 
4284  return Hexagon::getRegForm(MI.getOpcode());
4285 }
4286 
4287 // Return the number of bytes required to encode the instruction.
4288 // Hexagon instructions are fixed length, 4 bytes, unless they
4289 // use a constant extender, which requires another 4 bytes.
4290 // For debug instructions and prolog labels, return 0.
4292  if (MI.isDebugInstr() || MI.isPosition())
4293  return 0;
4294 
4295  unsigned Size = MI.getDesc().getSize();
4296  if (!Size)
4297  // Assume the default insn size in case it cannot be determined
4298  // for whatever reason.
4299  Size = HEXAGON_INSTR_SIZE;
4300 
4301  if (isConstExtended(MI) || isExtended(MI))
4302  Size += HEXAGON_INSTR_SIZE;
4303 
4304  // Try and compute number of instructions in asm.
4306  const MachineBasicBlock &MBB = *MI.getParent();
4307  const MachineFunction *MF = MBB.getParent();
4308  const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
4309 
4310  // Count the number of register definitions to find the asm string.
4311  unsigned NumDefs = 0;
4312  for (; MI.getOperand(NumDefs).isReg() && MI.getOperand(NumDefs).isDef();
4313  ++NumDefs)
4314  assert(NumDefs != MI.getNumOperands()-2 && "No asm string?");
4315 
4316  assert(MI.getOperand(NumDefs).isSymbol() && "No asm string?");
4317  // Disassemble the AsmStr and approximate number of instructions.
4318  const char *AsmStr = MI.getOperand(NumDefs).getSymbolName();
4319  Size = getInlineAsmLength(AsmStr, *MAI);
4320  }
4321 
4322  return Size;
4323 }
4324 
4326  const uint64_t F = MI.getDesc().TSFlags;
4327  return (F >> HexagonII::TypePos) & HexagonII::TypeMask;
4328 }
4329 
4331  const InstrItineraryData &II = *Subtarget.getInstrItineraryData();
4332  const InstrStage &IS = *II.beginStage(MI.getDesc().getSchedClass());
4333 
4334  return IS.getUnits();
4335 }
4336 
4337 // Calculate size of the basic block without debug instructions.
4339  return nonDbgMICount(BB->instr_begin(), BB->instr_end());
4340 }
4341 
4343  MachineBasicBlock::const_iterator BundleHead) const {
4344  assert(BundleHead->isBundle() && "Not a bundle header");
4345  auto MII = BundleHead.getInstrIterator();
4346  // Skip the bundle header.
4347  return nonDbgMICount(++MII, getBundleEnd(BundleHead.getInstrIterator()));
4348 }
4349 
4350 /// immediateExtend - Changes the instruction in place to one using an immediate
4351 /// extender.
4353  assert((isExtendable(MI)||isConstExtended(MI)) &&
4354  "Instruction must be extendable");
4355  // Find which operand is extendable.
4356  short ExtOpNum = getCExtOpNum(MI);
4357  MachineOperand &MO = MI.getOperand(ExtOpNum);
4358  // This needs to be something we understand.
4359  assert((MO.isMBB() || MO.isImm()) &&
4360  "Branch with unknown extendable field type");
4361  // Mark given operand as extended.
4363 }
4364 
4366  MachineInstr &MI, MachineBasicBlock *NewTarget) const {
4367  LLVM_DEBUG(dbgs() << "\n[invertAndChangeJumpTarget] to "
4368  << printMBBReference(*NewTarget);
4369  MI.dump(););
4370  assert(MI.isBranch());
4371  unsigned NewOpcode = getInvertedPredicatedOpcode(MI.getOpcode());
4372  int TargetPos = MI.getNumOperands() - 1;
4373  // In general branch target is the last operand,
4374  // but some implicit defs added at the end might change it.
4375  while ((TargetPos > -1) && !MI.getOperand(TargetPos).isMBB())
4376  --TargetPos;
4377  assert((TargetPos >= 0) && MI.getOperand(TargetPos).isMBB());
4378  MI.getOperand(TargetPos).setMBB(NewTarget);
4380  NewOpcode = reversePrediction(NewOpcode);
4381  }
4382  MI.setDesc(get(NewOpcode));
4383  return true;
4384 }
4385 
4387  /* +++ The code below is used to generate complete set of Hexagon Insn +++ */
4389  MachineBasicBlock &B = *A;
4391  DebugLoc DL = I->getDebugLoc();
4392  MachineInstr *NewMI;
4393 
4394  for (unsigned insn = TargetOpcode::GENERIC_OP_END+1;
4395  insn < Hexagon::INSTRUCTION_LIST_END; ++insn) {
4396  NewMI = BuildMI(B, I, DL, get(insn));
4397  LLVM_DEBUG(dbgs() << "\n"
4398  << getName(NewMI->getOpcode())
4399  << " Class: " << NewMI->getDesc().getSchedClass());
4400  NewMI->eraseFromParent();
4401  }
4402  /* --- The code above is used to generate complete set of Hexagon Insn --- */
4403 }
4404 
4405 // inverts the predication logic.
4406 // p -> NotP
4407 // NotP -> P
4409  LLVM_DEBUG(dbgs() << "\nTrying to reverse pred. sense of:"; MI.dump());
4411  return true;
4412 }
4413 
4414 // Reverse the branch prediction.
4415 unsigned HexagonInstrInfo::reversePrediction(unsigned Opcode) const {
4416  int PredRevOpcode = -1;
4417  if (isPredictedTaken(Opcode))
4418  PredRevOpcode = Hexagon::notTakenBranchPrediction(Opcode);
4419  else
4420  PredRevOpcode = Hexagon::takenBranchPrediction(Opcode);
4421  assert(PredRevOpcode > 0);
4422  return PredRevOpcode;
4423 }
4424 
4425 // TODO: Add more rigorous validation.
4427  const {
4428  return Cond.empty() || (Cond[0].isImm() && (Cond.size() != 1));
4429 }
4430 
4431 void HexagonInstrInfo::
4433  assert(MIB->isBundle());
4434  MachineOperand &Operand = MIB->getOperand(0);
4435  if (Operand.isImm())
4436  Operand.setImm(Operand.getImm() | memShufDisabledMask);
4437  else
4438  MIB->addOperand(MachineOperand::CreateImm(memShufDisabledMask));
4439 }
4440 
4442  assert(MIB.isBundle());
4443  const MachineOperand &Operand = MIB.getOperand(0);
4444  return (Operand.isImm() && (Operand.getImm() & memShufDisabledMask) != 0);
4445 }
4446 
4447 // Addressing mode relations.
4449  return Opc >= 0 ? Hexagon::changeAddrMode_abs_io(Opc) : Opc;
4450 }
4451 
4453  return Opc >= 0 ? Hexagon::changeAddrMode_io_abs(Opc) : Opc;
4454 }
4455 
4457  return Opc >= 0 ? Hexagon::changeAddrMode_io_pi(Opc) : Opc;
4458 }
4459 
4461  return Opc >= 0 ? Hexagon::changeAddrMode_io_rr(Opc) : Opc;
4462 }
4463 
4465  return Opc >= 0 ? Hexagon::changeAddrMode_pi_io(Opc) : Opc;
4466 }
4467 
4469  return Opc >= 0 ? Hexagon::changeAddrMode_rr_io(Opc) : Opc;
4470 }
4471 
4473  return Opc >= 0 ? Hexagon::changeAddrMode_rr_ur(Opc) : Opc;
4474 }
4475 
4477  return Opc >= 0 ? Hexagon::changeAddrMode_ur_rr(Opc) : Opc;
4478 }
static bool isReg(const MCInst &MI, unsigned OpNo)
unsigned getTargetFlags() const
bool isRegMask() const
isRegMask - Tests if this is a MO_RegisterMask operand.
short getNonExtOpcode(const MachineInstr &MI) const
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
Return an array that contains the direct target flag values and their names.
bool isVecALU(const MachineInstr &MI) const
const MachineInstrBuilder & add(const MachineOperand &MO) const
bool DefinesPredicate(MachineInstr &MI, std::vector< MachineOperand > &Pred) const override
If the specified instruction defines any predicate or condition code register(s) used for predication...
short changeAddrMode_rr_io(short Opc) const
static bool isConstant(const MachineInstr &MI)
instr_iterator instr_begin()
const int Hexagon_MEMH_OFFSET_MAX
bool is_TC2early(unsigned SchedClass)
bool isCall(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:656
unsigned nonDbgBBSize(const MachineBasicBlock *BB) const
getInstrTimingClassLatency - Compute the instruction latency of a given instruction using Timing Clas...
instr_iterator instr_end()
MachineBasicBlock * getMBB() const
const int Hexagon_ADDI_OFFSET_MAX
Object returned by analyzeLoopForPipelining.
unsigned getRegState(const MachineOperand &RegOp)
Get all register state flags from machine operand RegOp.
const int Hexagon_MEMH_OFFSET_MIN
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:139
This class represents lattice values for constants.
Definition: AllocatorList.h:23
const InstrStage * beginStage(unsigned ItinClassIndx) const
Return the first stage of the itinerary.
static void parseOperands(const MachineInstr &MI, SmallVector< unsigned, 4 > &Defs, SmallVector< unsigned, 8 > &Uses)
Gather register def/uses from MI.
static bool mayAlias(MachineInstr &MIa, MachineInstr &MIb, AliasAnalysis *AA)
static cl::opt< bool > UseDFAHazardRec("dfa-hazard-rec", cl::init(true), cl::Hidden, cl::ZeroOrMore, cl::desc("Use the DFA based hazard recognizer."))
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Store the specified register of the given register class to the specified stack frame index...
void setBundleNoShuf(MachineBasicBlock::instr_iterator MIB) const
short getEquivalentHWInstr(const MachineInstr &MI) const
DFAPacketizer * CreateTargetScheduleState(const TargetSubtargetInfo &STI) const override
Create machine specific model for scheduling.
void push_back(const T &Elt)
Definition: SmallVector.h:211
bool isAbsoluteSet(const MachineInstr &MI) const
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:384
bool isJumpR(const MachineInstr &MI) const
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:63
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
bool SubsumesPredicate(ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const override
Returns true if the first specified predicate subsumes the second, e.g.
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:179
unsigned getUnits() const
Returns the choice of FUs.
bool isConstExtended(const MachineInstr &MI) const
bool getInvertedPredSense(SmallVectorImpl< MachineOperand > &Cond) const
Address of indexed Jump Table for switch.
unsigned Reg
int findRegisterDefOperandIdx(Register Reg, bool isDead=false, bool Overlap=false, const TargetRegisterInfo *TRI=nullptr) const
Returns the operand index that is a def of the specified register or -1 if it is not found...
unsigned nonDbgBundleSize(MachineBasicBlock::const_iterator BundleHead) const
unsigned getSubReg() const
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:252
bool isInlineAsm() const
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
Reverses the branch condition of the specified condition list, returning false on success and true if...
int getMaxValue(const MachineInstr &MI) const
ArrayRef< std::pair< unsigned, const char * > > getSerializableBitmaskMachineOperandTargetFlags() const override
Return an array that contains the bitmask target flag values and their names.
const int Hexagon_ADDI_OFFSET_MIN
bool reversePredSense(MachineInstr &MI) const
int getDotNewPredOp(const MachineInstr &MI, const MachineBranchProbabilityInfo *MBPI) const
bool isTransient() const
Return true if this is a transient instruction that is either very likely to be eliminated during reg...
demanded bits
MachineBasicBlock reference.
#define HEXAGON_INSTR_SIZE
bool isExpr(unsigned OpType) const
bool isTailCall(const MachineInstr &MI) const override
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:33
F(f)
bool isCPI() const
isCPI - Tests if this is a MO_ConstantPoolIndex operand.
bool producesStall(const MachineInstr &ProdMI, const MachineInstr &ConsMI) const
MachineInstrBundleIterator< const MachineInstr > const_iterator
unsigned getMemAccessSize(const MachineInstr &MI) const
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
const int Hexagon_MEMD_OFFSET_MAX
unsigned getSize(const MachineInstr &MI) const
int getDotCurOp(const MachineInstr &MI) const
bool mayLoad() const
Return true if this instruction could possibly read memory.
Definition: MCInstrDesc.h:418
bool isLateResultInstr(const MachineInstr &MI) const
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:476
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
bool is_TC1(unsigned SchedClass)
void immediateExtend(MachineInstr &MI) const
immediateExtend - Changes the instruction in place to one using an immediate extender.
int getDotNewPredJumpOp(const MachineInstr &MI, const MachineBranchProbabilityInfo *MBPI) const
short changeAddrMode_ur_rr(short Opc) const
bool hasLoadFromStackSlot(const MachineInstr &MI, SmallVectorImpl< const MachineMemOperand *> &Accesses) const override
Check if the instruction or the bundle of instructions has load from stack slots. ...
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
unsigned getSpillSize(const TargetRegisterClass &RC) const
Return the size in bytes of the stack slot allocated to hold a spilled copy of a register from class ...
return AArch64::GPR64RegClass contains(Reg)
iterator_range< succ_iterator > successors()
bool isToBeScheduledASAP(const MachineInstr &MI1, const MachineInstr &MI2) const
void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
Insert a noop into the instruction stream at the specified point.
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
Analyze the branching code at the end of MBB, returning true if it cannot be understood (e...
bool isHVXVec(const MachineInstr &MI) const
static cl::opt< bool > BranchRelaxAsmLarge("branch-relax-asm-large", cl::init(true), cl::Hidden, cl::ZeroOrMore, cl::desc("branch relax asm"))
bool isComplex(const MachineInstr &MI) const
unsigned getSpillAlignment(const TargetRegisterClass &RC) const
Return the minimum required alignment in bytes for a spill slot for a register of this class...
static cl::opt< bool > DisableNVSchedule("disable-hexagon-nv-schedule", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("Disable schedule adjustment for new value stores."))
A description of a memory reference used in the backend.
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Load the specified register of the given register class from the specified stack frame index...
unsigned getInvertedPredicatedOpcode(const int Opc) const
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
MCSuperRegIterator enumerates all super-registers of Reg.
ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, const ScheduleDAG *DAG) const override
Allocate and return a hazard recognizer to use for this target when scheduling the machine instructio...
const HexagonInstrInfo * TII
Register getFrameRegister(const MachineFunction &MF) const override
Printable printMBBReference(const MachineBasicBlock &MBB)
Prints a machine basic block reference.
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
Definition: ArrayRef.h:450
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:413
LLVM_NODISCARD size_t count(char C) const
Return the number of occurrences of C in the string.
Definition: StringRef.h:471
unsigned getCompoundOpcode(const MachineInstr &GA, const MachineInstr &GB) const
bool isPredicatedNew(const MachineInstr &MI) const
bool canExecuteInBundle(const MachineInstr &First, const MachineInstr &Second) const
Can these instructions execute at the same time in a bundle.
bool predOpcodeHasNot(ArrayRef< MachineOperand > Cond) const
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
bool isVecUsableNextPacket(const MachineInstr &ProdMI, const MachineInstr &ConsMI) const
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
Name of external global symbol.
static StringRef getName(Value *V)
SimpleValueType SimpleTy
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
bool isDotNewInst(const MachineInstr &MI) const
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:410
bool isDeallocRet(const MachineInstr &MI) const
bool isExtended(const MachineInstr &MI) const
bool hasStoreToStackSlot(const MachineInstr &MI, SmallVectorImpl< const MachineMemOperand *> &Accesses) const override
Check if the instruction or the bundle of instructions has store to stack slots.
const char * getSymbolName() const
bool is_TC2(unsigned SchedClass)
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, unsigned base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
INLINEASM - Represents an inline asm block.
Definition: ISDOpcodes.h:703
bool isSolo(const MachineInstr &MI) const
bool isLateInstrFeedsEarlyInstr(const MachineInstr &LRMI, const MachineInstr &ESMI) const
MachineBasicBlock::instr_iterator expandVGatherPseudo(MachineInstr &MI) const
bool expandPostRAPseudo(MachineInstr &MI) const override
This function is called for all pseudo instructions that remain after register allocation.
bool PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Cond) const override
Convert the instruction into a predicated instruction.
bool predCanBeUsedAsDotNew(const MachineInstr &MI, unsigned PredReg) const
MachineInstr * findLoopInstr(MachineBasicBlock *BB, unsigned EndLoopOp, MachineBasicBlock *TargetBB, SmallPtrSet< MachineBasicBlock *, 8 > &Visited) const
Find the hardware loop instruction used to set-up the specified loop.
SmallVector< MachineInstr *, 2 > getBranchingInstrs(MachineBasicBlock &MBB) const
bool doesNotReturn(const MachineInstr &CallMI) const
unsigned getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:291
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:407
bool isIndirectBranch(QueryType Type=AnyInBundle) const
Return true if this is an indirect branch, such as a branch through a register.
Definition: MachineInstr.h:686
bool isEndLoopN(unsigned Opcode) const
bool isBundle() const
bool isCompoundBranchInstr(const MachineInstr &MI) const
void clearKillFlags(unsigned Reg) const
clearKillFlags - Iterate over all the uses of the given register and clear the kill flag from the Mac...
MO_GOT - This flag indicates that a symbol operand represents the address of the GOT entry for the sy...
short changeAddrMode_io_rr(short Opc) const
bool isPredictedTaken(unsigned Opcode) const
int getMinValue(const MachineInstr &MI) const
bool getBundleNoShuf(const MachineInstr &MIB) const
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
LLVM_NODISCARD size_t size() const
size - Get the string size.
Definition: StringRef.h:144
bool isFPImm() const
isFPImm - Tests if this is a MO_FPImmediate operand.
Itinerary data supplied by a subtarget to be used by a target.
short changeAddrMode_io_pi(short Opc) const
void setReg(Register Reg)
Change the register this operand corresponds to.
bool isTC1(const MachineInstr &MI) const
unsigned getUndefRegState(bool B)
unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const override
Compute the instruction latency of a given instruction.
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
unsigned getStageLatency(unsigned ItinClassIndx) const
Return the total stage latency of the given class.
short changeAddrMode_rr_ur(short Opc) const
reverse_iterator rbegin()
bool isBranch(QueryType Type=AnyInBundle) const
Returns true if this is a conditional, unconditional, or indirect branch.
Definition: MachineInstr.h:680
bool getPredReg(ArrayRef< MachineOperand > Cond, unsigned &PredReg, unsigned &PredRegPos, unsigned &PredRegFlags) const
BasicBlockListType::iterator iterator
unsigned getKillRegState(bool B)
virtual const InstrItineraryData * getInstrItineraryData() const
getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget...
unsigned getCExtOpNum(const MachineInstr &MI) const
const int Hexagon_MEMD_OFFSET_MIN
MachineOperand * getBaseAndOffset(const MachineInstr &MI, int64_t &Offset, unsigned &AccessSize) const
TargetInstrInfo - Interface to description of machine instruction set.
bool isReturn(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:646
bool is_TC3x(unsigned SchedClass)
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
static cl::opt< bool > EnableBranchPrediction("hexagon-enable-branch-prediction", cl::Hidden, cl::init(true), cl::desc("Enable branch prediction"))
bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const override
Return true if it&#39;s profitable for if-converter to duplicate instructions of specified accumulated in...
The memory access is volatile.
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
unsigned getSchedClass() const
Return the scheduling class for this instruction.
Definition: MCInstrDesc.h:601
unsigned getObjectAlignment(int ObjectIdx) const
Return the alignment of the specified stack object.
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
Definition: MachineInstr.h:843
Address of a global value.
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:432
const int Hexagon_MEMW_OFFSET_MAX
Constants for Hexagon instructions.
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
unsigned const MachineRegisterInfo * MRI
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
Definition: MathExtras.h:465
Machine Value Type.
static cl::opt< bool > EnableALUForwarding("enable-alu-forwarding", cl::Hidden, cl::init(true), cl::desc("Enable vec alu forwarding"))
HazardRecognizer - This determines whether or not an instruction can be issued this cycle...
bool getIncrementValue(const MachineInstr &MI, int &Value) const override
If the instruction is an increment of a constant value, return the amount.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.