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16 #ifndef LLVM_LIB_TARGET_AARCH64_UTILS_AARCH64BASEINFO_H
17 #define LLVM_LIB_TARGET_AARCH64_UTILS_AARCH64BASEINFO_H
31 case AArch64::X0:
return AArch64::W0;
32 case AArch64::X1:
return AArch64::W1;
33 case AArch64::X2:
return AArch64::W2;
34 case AArch64::X3:
return AArch64::W3;
35 case AArch64::X4:
return AArch64::W4;
36 case AArch64::X5:
return AArch64::W5;
37 case AArch64::X6:
return AArch64::W6;
38 case AArch64::X7:
return AArch64::W7;
39 case AArch64::X8:
return AArch64::W8;
40 case AArch64::X9:
return AArch64::W9;
41 case AArch64::X10:
return AArch64::W10;
42 case AArch64::X11:
return AArch64::W11;
43 case AArch64::X12:
return AArch64::W12;
44 case AArch64::X13:
return AArch64::W13;
45 case AArch64::X14:
return AArch64::W14;
46 case AArch64::X15:
return AArch64::W15;
47 case AArch64::X16:
return AArch64::W16;
48 case AArch64::X17:
return AArch64::W17;
49 case AArch64::X18:
return AArch64::W18;
50 case AArch64::X19:
return AArch64::W19;
51 case AArch64::X20:
return AArch64::W20;
52 case AArch64::X21:
return AArch64::W21;
53 case AArch64::X22:
return AArch64::W22;
54 case AArch64::X23:
return AArch64::W23;
55 case AArch64::X24:
return AArch64::W24;
56 case AArch64::X25:
return AArch64::W25;
57 case AArch64::X26:
return AArch64::W26;
58 case AArch64::X27:
return AArch64::W27;
59 case AArch64::X28:
return AArch64::W28;
60 case AArch64::FP:
return AArch64::W29;
61 case AArch64::LR:
return AArch64::W30;
62 case AArch64::SP:
return AArch64::WSP;
63 case AArch64::XZR:
return AArch64::WZR;
71 case AArch64::W0:
return AArch64::X0;
72 case AArch64::W1:
return AArch64::X1;
73 case AArch64::W2:
return AArch64::X2;
74 case AArch64::W3:
return AArch64::X3;
75 case AArch64::W4:
return AArch64::X4;
76 case AArch64::W5:
return AArch64::X5;
77 case AArch64::W6:
return AArch64::X6;
78 case AArch64::W7:
return AArch64::X7;
79 case AArch64::W8:
return AArch64::X8;
80 case AArch64::W9:
return AArch64::X9;
81 case AArch64::W10:
return AArch64::X10;
82 case AArch64::W11:
return AArch64::X11;
83 case AArch64::W12:
return AArch64::X12;
84 case AArch64::W13:
return AArch64::X13;
85 case AArch64::W14:
return AArch64::X14;
86 case AArch64::W15:
return AArch64::X15;
87 case AArch64::W16:
return AArch64::X16;
88 case AArch64::W17:
return AArch64::X17;
89 case AArch64::W18:
return AArch64::X18;
90 case AArch64::W19:
return AArch64::X19;
91 case AArch64::W20:
return AArch64::X20;
92 case AArch64::W21:
return AArch64::X21;
93 case AArch64::W22:
return AArch64::X22;
94 case AArch64::W23:
return AArch64::X23;
95 case AArch64::W24:
return AArch64::X24;
96 case AArch64::W25:
return AArch64::X25;
97 case AArch64::W26:
return AArch64::X26;
98 case AArch64::W27:
return AArch64::X27;
99 case AArch64::W28:
return AArch64::X28;
100 case AArch64::W29:
return AArch64::FP;
101 case AArch64::W30:
return AArch64::LR;
102 case AArch64::WSP:
return AArch64::SP;
103 case AArch64::WZR:
return AArch64::XZR;
111 case AArch64::X0_X1_X2_X3_X4_X5_X6_X7:
return AArch64::X0;
112 case AArch64::X2_X3_X4_X5_X6_X7_X8_X9:
return AArch64::X2;
113 case AArch64::X4_X5_X6_X7_X8_X9_X10_X11:
return AArch64::X4;
114 case AArch64::X6_X7_X8_X9_X10_X11_X12_X13:
return AArch64::X6;
115 case AArch64::X8_X9_X10_X11_X12_X13_X14_X15:
return AArch64::X8;
116 case AArch64::X10_X11_X12_X13_X14_X15_X16_X17:
return AArch64::X10;
117 case AArch64::X12_X13_X14_X15_X16_X17_X18_X19:
return AArch64::X12;
118 case AArch64::X14_X15_X16_X17_X18_X19_X20_X21:
return AArch64::X14;
119 case AArch64::X16_X17_X18_X19_X20_X21_X22_X23:
return AArch64::X16;
120 case AArch64::X18_X19_X20_X21_X22_X23_X24_X25:
return AArch64::X18;
121 case AArch64::X20_X21_X22_X23_X24_X25_X26_X27:
return AArch64::X20;
122 case AArch64::X22_X23_X24_X25_X26_X27_X28_FP:
return AArch64::X22;
130 case AArch64::D0:
return AArch64::B0;
131 case AArch64::D1:
return AArch64::B1;
132 case AArch64::D2:
return AArch64::B2;
133 case AArch64::D3:
return AArch64::B3;
134 case AArch64::D4:
return AArch64::B4;
135 case AArch64::D5:
return AArch64::B5;
136 case AArch64::D6:
return AArch64::B6;
137 case AArch64::D7:
return AArch64::B7;
138 case AArch64::D8:
return AArch64::B8;
139 case AArch64::D9:
return AArch64::B9;
140 case AArch64::D10:
return AArch64::B10;
141 case AArch64::D11:
return AArch64::B11;
142 case AArch64::D12:
return AArch64::B12;
143 case AArch64::D13:
return AArch64::B13;
144 case AArch64::D14:
return AArch64::B14;
145 case AArch64::D15:
return AArch64::B15;
146 case AArch64::D16:
return AArch64::B16;
147 case AArch64::D17:
return AArch64::B17;
148 case AArch64::D18:
return AArch64::B18;
149 case AArch64::D19:
return AArch64::B19;
150 case AArch64::D20:
return AArch64::B20;
151 case AArch64::D21:
return AArch64::B21;
152 case AArch64::D22:
return AArch64::B22;
153 case AArch64::D23:
return AArch64::B23;
154 case AArch64::D24:
return AArch64::B24;
155 case AArch64::D25:
return AArch64::B25;
156 case AArch64::D26:
return AArch64::B26;
157 case AArch64::D27:
return AArch64::B27;
158 case AArch64::D28:
return AArch64::B28;
159 case AArch64::D29:
return AArch64::B29;
160 case AArch64::D30:
return AArch64::B30;
161 case AArch64::D31:
return AArch64::B31;
170 case AArch64::B0:
return AArch64::D0;
171 case AArch64::B1:
return AArch64::D1;
172 case AArch64::B2:
return AArch64::D2;
173 case AArch64::B3:
return AArch64::D3;
174 case AArch64::B4:
return AArch64::D4;
175 case AArch64::B5:
return AArch64::D5;
176 case AArch64::B6:
return AArch64::D6;
177 case AArch64::B7:
return AArch64::D7;
178 case AArch64::B8:
return AArch64::D8;
179 case AArch64::B9:
return AArch64::D9;
180 case AArch64::B10:
return AArch64::D10;
181 case AArch64::B11:
return AArch64::D11;
182 case AArch64::B12:
return AArch64::D12;
183 case AArch64::B13:
return AArch64::D13;
184 case AArch64::B14:
return AArch64::D14;
185 case AArch64::B15:
return AArch64::D15;
186 case AArch64::B16:
return AArch64::D16;
187 case AArch64::B17:
return AArch64::D17;
188 case AArch64::B18:
return AArch64::D18;
189 case AArch64::B19:
return AArch64::D19;
190 case AArch64::B20:
return AArch64::D20;
191 case AArch64::B21:
return AArch64::D21;
192 case AArch64::B22:
return AArch64::D22;
193 case AArch64::B23:
return AArch64::D23;
194 case AArch64::B24:
return AArch64::D24;
195 case AArch64::B25:
return AArch64::D25;
196 case AArch64::B26:
return AArch64::D26;
197 case AArch64::B27:
return AArch64::D27;
198 case AArch64::B28:
return AArch64::D28;
199 case AArch64::B29:
return AArch64::D29;
200 case AArch64::B30:
return AArch64::D30;
201 case AArch64::B31:
return AArch64::D31;
209 case AArch64::LDADDAB:
case AArch64::LDADDAH:
210 case AArch64::LDADDAW:
case AArch64::LDADDAX:
211 case AArch64::LDADDALB:
case AArch64::LDADDALH:
212 case AArch64::LDADDALW:
case AArch64::LDADDALX:
213 case AArch64::LDCLRAB:
case AArch64::LDCLRAH:
214 case AArch64::LDCLRAW:
case AArch64::LDCLRAX:
215 case AArch64::LDCLRALB:
case AArch64::LDCLRALH:
216 case AArch64::LDCLRALW:
case AArch64::LDCLRALX:
217 case AArch64::LDEORAB:
case AArch64::LDEORAH:
218 case AArch64::LDEORAW:
case AArch64::LDEORAX:
219 case AArch64::LDEORALB:
case AArch64::LDEORALH:
220 case AArch64::LDEORALW:
case AArch64::LDEORALX:
221 case AArch64::LDSETAB:
case AArch64::LDSETAH:
222 case AArch64::LDSETAW:
case AArch64::LDSETAX:
223 case AArch64::LDSETALB:
case AArch64::LDSETALH:
224 case AArch64::LDSETALW:
case AArch64::LDSETALX:
225 case AArch64::LDSMAXAB:
case AArch64::LDSMAXAH:
226 case AArch64::LDSMAXAW:
case AArch64::LDSMAXAX:
227 case AArch64::LDSMAXALB:
case AArch64::LDSMAXALH:
228 case AArch64::LDSMAXALW:
case AArch64::LDSMAXALX:
229 case AArch64::LDSMINAB:
case AArch64::LDSMINAH:
230 case AArch64::LDSMINAW:
case AArch64::LDSMINAX:
231 case AArch64::LDSMINALB:
case AArch64::LDSMINALH:
232 case AArch64::LDSMINALW:
case AArch64::LDSMINALX:
233 case AArch64::LDUMAXAB:
case AArch64::LDUMAXAH:
234 case AArch64::LDUMAXAW:
case AArch64::LDUMAXAX:
235 case AArch64::LDUMAXALB:
case AArch64::LDUMAXALH:
236 case AArch64::LDUMAXALW:
case AArch64::LDUMAXALX:
237 case AArch64::LDUMINAB:
case AArch64::LDUMINAH:
238 case AArch64::LDUMINAW:
case AArch64::LDUMINAX:
239 case AArch64::LDUMINALB:
case AArch64::LDUMINALH:
240 case AArch64::LDUMINALW:
case AArch64::LDUMINALX:
241 case AArch64::SWPAB:
case AArch64::SWPAH:
242 case AArch64::SWPAW:
case AArch64::SWPAX:
243 case AArch64::SWPALB:
case AArch64::SWPALH:
244 case AArch64::SWPALW:
case AArch64::SWPALX:
250 namespace AArch64CC {
284 case EQ:
return "eq";
285 case NE:
return "ne";
286 case HS:
return "hs";
287 case LO:
return "lo";
288 case MI:
return "mi";
289 case PL:
return "pl";
290 case VS:
return "vs";
291 case VC:
return "vc";
292 case HI:
return "hi";
293 case LS:
return "ls";
294 case GE:
return "ge";
295 case LT:
return "lt";
296 case GT:
return "gt";
297 case LE:
return "le";
298 case AL:
return "al";
299 case NV:
return "nv";
306 return static_cast<CondCode>(
static_cast<unsigned>(Code) ^ 0x1);
315 enum {
N = 8, Z = 4,
C = 2, V = 1 };
368 namespace AArch64SVCR {
372 #define GET_SVCR_DECL
373 #include "AArch64GenSystemOperands.inc"
381 #include "AArch64GenSystemOperands.inc"
384 namespace AArch64DB {
389 #include "AArch64GenSystemOperands.inc"
392 namespace AArch64DBnXS {
396 #define GET_DBNXS_DECL
397 #include "AArch64GenSystemOperands.inc"
400 namespace AArch64DC {
405 #include "AArch64GenSystemOperands.inc"
408 namespace AArch64IC {
413 #include "AArch64GenSystemOperands.inc"
416 namespace AArch64ISB {
421 #include "AArch64GenSystemOperands.inc"
424 namespace AArch64TSB {
429 #include "AArch64GenSystemOperands.inc"
432 namespace AArch64PRFM {
436 #define GET_PRFM_DECL
437 #include "AArch64GenSystemOperands.inc"
440 namespace AArch64SVEPRFM {
444 #define GET_SVEPRFM_DECL
445 #include "AArch64GenSystemOperands.inc"
448 namespace AArch64SVEPredPattern {
453 #define GET_SVEPREDPAT_DECL
454 #include "AArch64GenSystemOperands.inc"
463 case AArch64SVEPredPattern::vl1:
464 case AArch64SVEPredPattern::vl2:
465 case AArch64SVEPredPattern::vl3:
466 case AArch64SVEPredPattern::vl4:
467 case AArch64SVEPredPattern::vl5:
468 case AArch64SVEPredPattern::vl6:
469 case AArch64SVEPredPattern::vl7:
470 case AArch64SVEPredPattern::vl8:
472 case AArch64SVEPredPattern::vl16:
474 case AArch64SVEPredPattern::vl32:
476 case AArch64SVEPredPattern::vl64:
478 case AArch64SVEPredPattern::vl128:
480 case AArch64SVEPredPattern::vl256:
486 inline Optional<unsigned>
488 switch (MinNumElts) {
501 return AArch64SVEPredPattern::vl16;
503 return AArch64SVEPredPattern::vl32;
505 return AArch64SVEPredPattern::vl64;
507 return AArch64SVEPredPattern::vl128;
509 return AArch64SVEPredPattern::vl256;
513 namespace AArch64ExactFPImm {
519 #define GET_EXACTFPIMM_DECL
520 #include "AArch64GenSystemOperands.inc"
523 namespace AArch64PState {
527 #define GET_PSTATE_DECL
528 #include "AArch64GenSystemOperands.inc"
531 namespace AArch64PSBHint {
536 #include "AArch64GenSystemOperands.inc"
539 namespace AArch64BTIHint {
544 #include "AArch64GenSystemOperands.inc"
547 namespace AArch64SE {
568 namespace AArch64Layout {
590 inline static const char *
627 namespace AArch64SysReg {
641 #define GET_SYSREG_DECL
642 #include "AArch64GenSystemOperands.inc"
651 namespace AArch64TLBI {
655 #define GET_TLBITable_DECL
656 #include "AArch64GenSystemOperands.inc"
659 namespace AArch64PRCTX {
663 #define GET_PRCTX_DECL
664 #include "AArch64GenSystemOperands.inc"
667 namespace AArch64II {
StringSwitch & Case(StringLiteral S, T Value)
@ MO_G3
MO_G3 - A symbol operand with this flag (granule 3) represents the high 16-bits of a 64-bit address,...
This is an optimization pass for GlobalISel generic memory operations.
@ MO_HI12
MO_HI12 - This flag indicates that a symbol operand represents the bits 13-24 of a 64-bit address,...
static unsigned getNZCVToSatisfyCondCode(CondCode Code)
Given a condition code, return NZCV flags that would satisfy that condition.
@ MO_G1
MO_G1 - A symbol operand with this flag (granule 1) represents the bits 16-31 of a 64-bit address,...
FeatureBitset FeaturesRequired
LLVM_NODISCARD R Default(T Value)
const SysReg * lookupSysRegByName(StringRef)
constexpr SysAlias(const char *N, uint16_t E)
Reg
All possible values of the reg field in the ModR/M byte.
constexpr SysAliasReg(const char *N, uint16_t E, bool R)
@ MO_PREL
MO_PREL - Indicates that the bits of the symbol operand represented by MO_G0 etc are PC relative.
constexpr SysAliasImm(const char *N, uint16_t E, uint16_t I)
Container class for subtarget features.
FeatureBitset getRequiredFeatures() const
@ MO_TLS
MO_TLS - Indicates that the operand being accessed is some kind of thread-local symbol.
@ MO_G0
MO_G0 - A symbol operand with this flag (granule 0) represents the bits 0-15 of a 64-bit address,...
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
(vector float) vec_cmpeq(*A, *B) C
static const char * getCondCodeName(CondCode Code)
constexpr SysAliasImm(const char *N, uint16_t E, uint16_t I, FeatureBitset F)
@ MO_S
MO_S - Indicates that the bits of the symbol operand represented by MO_G0 etc are signed.
@ MO_DLLIMPORT
MO_DLLIMPORT - On a symbol operand, this represents that the reference to the symbol is for an import...
static constexpr unsigned SVEBitsPerBlock
@ MO_NC
MO_NC - Indicates whether the linker is expected to check the symbol reference for overflow.
@ MO_PAGEOFF
MO_PAGEOFF - A symbol operand with this flag represents the offset of that symbol within a 4K page.
uint32_t parseGenericRegister(StringRef Name)
static const char * AArch64VectorLayoutToString(AArch64Layout::VectorLayout Layout)
static unsigned getBRegFromDReg(unsigned Reg)
TOF
Target Operand Flag enum.
static bool atomicBarrierDroppedOnZero(unsigned Opcode)
StringRef - Represent a constant reference to a string, i.e.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
static unsigned getXRegFromXRegTuple(unsigned RegTuple)
static unsigned getXRegFromWReg(unsigned Reg)
const SysReg * lookupSysRegByEncoding(uint16_t)
std::string genericRegisterString(uint32_t Bits)
static AArch64Layout::VectorLayout AArch64StringToVectorLayout(StringRef LayoutStr)
Optional< unsigned > getSVEPredPatternFromNumElements(unsigned MinNumElts)
Return specific VL predicate pattern based on the number of elements.
constexpr SysAlias(const char *N, uint16_t E, FeatureBitset F)
static CondCode getInvertedCondCode(CondCode Code)
constexpr SysAliasReg(const char *N, uint16_t E, bool R, FeatureBitset F)
unsigned getNumElementsFromSVEPredPattern(unsigned Pattern)
Return the number of active elements for VL1 to VL256 predicate pattern, zero for all other patterns.
static unsigned getWRegFromXReg(unsigned Reg)
bool haveFeatures(FeatureBitset ActiveFeatures) const
static unsigned getDRegFromBReg(unsigned Reg)
FeatureBitset FeaturesRequired
A switch()-like statement whose cases are string literals.
@ MO_G2
MO_G2 - A symbol operand with this flag (granule 2) represents the bits 32-47 of a 64-bit address,...
@ MO_COFFSTUB
MO_COFFSTUB - On a symbol operand "FOO", this indicates that the reference is actually to the "....
static constexpr unsigned SVEMaxBitsPerVector
@ MO_TAGGED
MO_TAGGED - With MO_PAGE, indicates that the page includes a memory tag in bits 56-63.
@ MO_GOT
MO_GOT - This flag indicates that a symbol operand represents the address of the GOT entry for the sy...
@ MO_PAGE
MO_PAGE - A symbol operand with this flag represents the pc-relative offset of the 4K page containing...
bool haveFeatures(FeatureBitset ActiveFeatures) const