LLVM  13.0.0git
AArch64BaseInfo.h
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1 //===-- AArch64BaseInfo.h - Top level definitions for AArch64 ---*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains small standalone helper functions and enum definitions for
10 // the AArch64 target useful for the compiler back-end and the MC libraries.
11 // As such, it deliberately does not include references to LLVM core
12 // code gen types, passes, etc..
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #ifndef LLVM_LIB_TARGET_AARCH64_UTILS_AARCH64BASEINFO_H
17 #define LLVM_LIB_TARGET_AARCH64_UTILS_AARCH64BASEINFO_H
18 
19 // FIXME: Is it easiest to fix this layering violation by moving the .inc
20 // #includes from AArch64MCTargetDesc.h to here?
21 #include "MCTargetDesc/AArch64MCTargetDesc.h" // For AArch64::X0 and friends.
22 #include "llvm/ADT/STLExtras.h"
23 #include "llvm/ADT/StringSwitch.h"
26 
27 namespace llvm {
28 
29 inline static unsigned getWRegFromXReg(unsigned Reg) {
30  switch (Reg) {
31  case AArch64::X0: return AArch64::W0;
32  case AArch64::X1: return AArch64::W1;
33  case AArch64::X2: return AArch64::W2;
34  case AArch64::X3: return AArch64::W3;
35  case AArch64::X4: return AArch64::W4;
36  case AArch64::X5: return AArch64::W5;
37  case AArch64::X6: return AArch64::W6;
38  case AArch64::X7: return AArch64::W7;
39  case AArch64::X8: return AArch64::W8;
40  case AArch64::X9: return AArch64::W9;
41  case AArch64::X10: return AArch64::W10;
42  case AArch64::X11: return AArch64::W11;
43  case AArch64::X12: return AArch64::W12;
44  case AArch64::X13: return AArch64::W13;
45  case AArch64::X14: return AArch64::W14;
46  case AArch64::X15: return AArch64::W15;
47  case AArch64::X16: return AArch64::W16;
48  case AArch64::X17: return AArch64::W17;
49  case AArch64::X18: return AArch64::W18;
50  case AArch64::X19: return AArch64::W19;
51  case AArch64::X20: return AArch64::W20;
52  case AArch64::X21: return AArch64::W21;
53  case AArch64::X22: return AArch64::W22;
54  case AArch64::X23: return AArch64::W23;
55  case AArch64::X24: return AArch64::W24;
56  case AArch64::X25: return AArch64::W25;
57  case AArch64::X26: return AArch64::W26;
58  case AArch64::X27: return AArch64::W27;
59  case AArch64::X28: return AArch64::W28;
60  case AArch64::FP: return AArch64::W29;
61  case AArch64::LR: return AArch64::W30;
62  case AArch64::SP: return AArch64::WSP;
63  case AArch64::XZR: return AArch64::WZR;
64  }
65  // For anything else, return it unchanged.
66  return Reg;
67 }
68 
69 inline static unsigned getXRegFromWReg(unsigned Reg) {
70  switch (Reg) {
71  case AArch64::W0: return AArch64::X0;
72  case AArch64::W1: return AArch64::X1;
73  case AArch64::W2: return AArch64::X2;
74  case AArch64::W3: return AArch64::X3;
75  case AArch64::W4: return AArch64::X4;
76  case AArch64::W5: return AArch64::X5;
77  case AArch64::W6: return AArch64::X6;
78  case AArch64::W7: return AArch64::X7;
79  case AArch64::W8: return AArch64::X8;
80  case AArch64::W9: return AArch64::X9;
81  case AArch64::W10: return AArch64::X10;
82  case AArch64::W11: return AArch64::X11;
83  case AArch64::W12: return AArch64::X12;
84  case AArch64::W13: return AArch64::X13;
85  case AArch64::W14: return AArch64::X14;
86  case AArch64::W15: return AArch64::X15;
87  case AArch64::W16: return AArch64::X16;
88  case AArch64::W17: return AArch64::X17;
89  case AArch64::W18: return AArch64::X18;
90  case AArch64::W19: return AArch64::X19;
91  case AArch64::W20: return AArch64::X20;
92  case AArch64::W21: return AArch64::X21;
93  case AArch64::W22: return AArch64::X22;
94  case AArch64::W23: return AArch64::X23;
95  case AArch64::W24: return AArch64::X24;
96  case AArch64::W25: return AArch64::X25;
97  case AArch64::W26: return AArch64::X26;
98  case AArch64::W27: return AArch64::X27;
99  case AArch64::W28: return AArch64::X28;
100  case AArch64::W29: return AArch64::FP;
101  case AArch64::W30: return AArch64::LR;
102  case AArch64::WSP: return AArch64::SP;
103  case AArch64::WZR: return AArch64::XZR;
104  }
105  // For anything else, return it unchanged.
106  return Reg;
107 }
108 
109 static inline unsigned getBRegFromDReg(unsigned Reg) {
110  switch (Reg) {
111  case AArch64::D0: return AArch64::B0;
112  case AArch64::D1: return AArch64::B1;
113  case AArch64::D2: return AArch64::B2;
114  case AArch64::D3: return AArch64::B3;
115  case AArch64::D4: return AArch64::B4;
116  case AArch64::D5: return AArch64::B5;
117  case AArch64::D6: return AArch64::B6;
118  case AArch64::D7: return AArch64::B7;
119  case AArch64::D8: return AArch64::B8;
120  case AArch64::D9: return AArch64::B9;
121  case AArch64::D10: return AArch64::B10;
122  case AArch64::D11: return AArch64::B11;
123  case AArch64::D12: return AArch64::B12;
124  case AArch64::D13: return AArch64::B13;
125  case AArch64::D14: return AArch64::B14;
126  case AArch64::D15: return AArch64::B15;
127  case AArch64::D16: return AArch64::B16;
128  case AArch64::D17: return AArch64::B17;
129  case AArch64::D18: return AArch64::B18;
130  case AArch64::D19: return AArch64::B19;
131  case AArch64::D20: return AArch64::B20;
132  case AArch64::D21: return AArch64::B21;
133  case AArch64::D22: return AArch64::B22;
134  case AArch64::D23: return AArch64::B23;
135  case AArch64::D24: return AArch64::B24;
136  case AArch64::D25: return AArch64::B25;
137  case AArch64::D26: return AArch64::B26;
138  case AArch64::D27: return AArch64::B27;
139  case AArch64::D28: return AArch64::B28;
140  case AArch64::D29: return AArch64::B29;
141  case AArch64::D30: return AArch64::B30;
142  case AArch64::D31: return AArch64::B31;
143  }
144  // For anything else, return it unchanged.
145  return Reg;
146 }
147 
148 
149 static inline unsigned getDRegFromBReg(unsigned Reg) {
150  switch (Reg) {
151  case AArch64::B0: return AArch64::D0;
152  case AArch64::B1: return AArch64::D1;
153  case AArch64::B2: return AArch64::D2;
154  case AArch64::B3: return AArch64::D3;
155  case AArch64::B4: return AArch64::D4;
156  case AArch64::B5: return AArch64::D5;
157  case AArch64::B6: return AArch64::D6;
158  case AArch64::B7: return AArch64::D7;
159  case AArch64::B8: return AArch64::D8;
160  case AArch64::B9: return AArch64::D9;
161  case AArch64::B10: return AArch64::D10;
162  case AArch64::B11: return AArch64::D11;
163  case AArch64::B12: return AArch64::D12;
164  case AArch64::B13: return AArch64::D13;
165  case AArch64::B14: return AArch64::D14;
166  case AArch64::B15: return AArch64::D15;
167  case AArch64::B16: return AArch64::D16;
168  case AArch64::B17: return AArch64::D17;
169  case AArch64::B18: return AArch64::D18;
170  case AArch64::B19: return AArch64::D19;
171  case AArch64::B20: return AArch64::D20;
172  case AArch64::B21: return AArch64::D21;
173  case AArch64::B22: return AArch64::D22;
174  case AArch64::B23: return AArch64::D23;
175  case AArch64::B24: return AArch64::D24;
176  case AArch64::B25: return AArch64::D25;
177  case AArch64::B26: return AArch64::D26;
178  case AArch64::B27: return AArch64::D27;
179  case AArch64::B28: return AArch64::D28;
180  case AArch64::B29: return AArch64::D29;
181  case AArch64::B30: return AArch64::D30;
182  case AArch64::B31: return AArch64::D31;
183  }
184  // For anything else, return it unchanged.
185  return Reg;
186 }
187 
188 static inline bool atomicBarrierDroppedOnZero(unsigned Opcode) {
189  switch (Opcode) {
190  case AArch64::LDADDAB: case AArch64::LDADDAH:
191  case AArch64::LDADDAW: case AArch64::LDADDAX:
192  case AArch64::LDADDALB: case AArch64::LDADDALH:
193  case AArch64::LDADDALW: case AArch64::LDADDALX:
194  case AArch64::LDCLRAB: case AArch64::LDCLRAH:
195  case AArch64::LDCLRAW: case AArch64::LDCLRAX:
196  case AArch64::LDCLRALB: case AArch64::LDCLRALH:
197  case AArch64::LDCLRALW: case AArch64::LDCLRALX:
198  case AArch64::LDEORAB: case AArch64::LDEORAH:
199  case AArch64::LDEORAW: case AArch64::LDEORAX:
200  case AArch64::LDEORALB: case AArch64::LDEORALH:
201  case AArch64::LDEORALW: case AArch64::LDEORALX:
202  case AArch64::LDSETAB: case AArch64::LDSETAH:
203  case AArch64::LDSETAW: case AArch64::LDSETAX:
204  case AArch64::LDSETALB: case AArch64::LDSETALH:
205  case AArch64::LDSETALW: case AArch64::LDSETALX:
206  case AArch64::LDSMAXAB: case AArch64::LDSMAXAH:
207  case AArch64::LDSMAXAW: case AArch64::LDSMAXAX:
208  case AArch64::LDSMAXALB: case AArch64::LDSMAXALH:
209  case AArch64::LDSMAXALW: case AArch64::LDSMAXALX:
210  case AArch64::LDSMINAB: case AArch64::LDSMINAH:
211  case AArch64::LDSMINAW: case AArch64::LDSMINAX:
212  case AArch64::LDSMINALB: case AArch64::LDSMINALH:
213  case AArch64::LDSMINALW: case AArch64::LDSMINALX:
214  case AArch64::LDUMAXAB: case AArch64::LDUMAXAH:
215  case AArch64::LDUMAXAW: case AArch64::LDUMAXAX:
216  case AArch64::LDUMAXALB: case AArch64::LDUMAXALH:
217  case AArch64::LDUMAXALW: case AArch64::LDUMAXALX:
218  case AArch64::LDUMINAB: case AArch64::LDUMINAH:
219  case AArch64::LDUMINAW: case AArch64::LDUMINAX:
220  case AArch64::LDUMINALB: case AArch64::LDUMINALH:
221  case AArch64::LDUMINALW: case AArch64::LDUMINALX:
222  case AArch64::SWPAB: case AArch64::SWPAH:
223  case AArch64::SWPAW: case AArch64::SWPAX:
224  case AArch64::SWPALB: case AArch64::SWPALH:
225  case AArch64::SWPALW: case AArch64::SWPALX:
226  return true;
227  }
228  return false;
229 }
230 
231 namespace AArch64CC {
232 
233 // The CondCodes constants map directly to the 4-bit encoding of the condition
234 // field for predicated instructions.
235 enum CondCode { // Meaning (integer) Meaning (floating-point)
236  EQ = 0x0, // Equal Equal
237  NE = 0x1, // Not equal Not equal, or unordered
238  HS = 0x2, // Unsigned higher or same >, ==, or unordered
239  LO = 0x3, // Unsigned lower Less than
240  MI = 0x4, // Minus, negative Less than
241  PL = 0x5, // Plus, positive or zero >, ==, or unordered
242  VS = 0x6, // Overflow Unordered
243  VC = 0x7, // No overflow Not unordered
244  HI = 0x8, // Unsigned higher Greater than, or unordered
245  LS = 0x9, // Unsigned lower or same Less than or equal
246  GE = 0xa, // Greater than or equal Greater than or equal
247  LT = 0xb, // Less than Less than, or unordered
248  GT = 0xc, // Greater than Greater than
249  LE = 0xd, // Less than or equal <, ==, or unordered
250  AL = 0xe, // Always (unconditional) Always (unconditional)
251  NV = 0xf, // Always (unconditional) Always (unconditional)
252  // Note the NV exists purely to disassemble 0b1111. Execution is "always".
254 
255  // Common aliases used for SVE.
256  ANY_ACTIVE = NE, // (!Z)
257  FIRST_ACTIVE = MI, // ( N)
258  LAST_ACTIVE = LO, // (!C)
259  NONE_ACTIVE = EQ // ( Z)
260 };
261 
262 inline static const char *getCondCodeName(CondCode Code) {
263  switch (Code) {
264  default: llvm_unreachable("Unknown condition code");
265  case EQ: return "eq";
266  case NE: return "ne";
267  case HS: return "hs";
268  case LO: return "lo";
269  case MI: return "mi";
270  case PL: return "pl";
271  case VS: return "vs";
272  case VC: return "vc";
273  case HI: return "hi";
274  case LS: return "ls";
275  case GE: return "ge";
276  case LT: return "lt";
277  case GT: return "gt";
278  case LE: return "le";
279  case AL: return "al";
280  case NV: return "nv";
281  }
282 }
283 
284 inline static CondCode getInvertedCondCode(CondCode Code) {
285  // To reverse a condition it's necessary to only invert the low bit:
286 
287  return static_cast<CondCode>(static_cast<unsigned>(Code) ^ 0x1);
288 }
289 
290 /// Given a condition code, return NZCV flags that would satisfy that condition.
291 /// The flag bits are in the format expected by the ccmp instructions.
292 /// Note that many different flag settings can satisfy a given condition code,
293 /// this function just returns one of them.
294 inline static unsigned getNZCVToSatisfyCondCode(CondCode Code) {
295  // NZCV flags encoded as expected by ccmp instructions, ARMv8 ISA 5.5.7.
296  enum { N = 8, Z = 4, C = 2, V = 1 };
297  switch (Code) {
298  default: llvm_unreachable("Unknown condition code");
299  case EQ: return Z; // Z == 1
300  case NE: return 0; // Z == 0
301  case HS: return C; // C == 1
302  case LO: return 0; // C == 0
303  case MI: return N; // N == 1
304  case PL: return 0; // N == 0
305  case VS: return V; // V == 1
306  case VC: return 0; // V == 0
307  case HI: return C; // C == 1 && Z == 0
308  case LS: return 0; // C == 0 || Z == 1
309  case GE: return 0; // N == V
310  case LT: return N; // N != V
311  case GT: return 0; // Z == 0 && N == V
312  case LE: return Z; // Z == 1 || N != V
313  }
314 }
315 } // end namespace AArch64CC
316 
317 struct SysAlias {
318  const char *Name;
321 
322  constexpr SysAlias(const char *N, uint16_t E) : Name(N), Encoding(E) {}
323  constexpr SysAlias(const char *N, uint16_t E, FeatureBitset F)
324  : Name(N), Encoding(E), FeaturesRequired(F) {}
325 
326  bool haveFeatures(FeatureBitset ActiveFeatures) const {
327  return (FeaturesRequired & ActiveFeatures) == FeaturesRequired;
328  }
329 
331 };
332 
334  bool NeedsReg;
335  constexpr SysAliasReg(const char *N, uint16_t E, bool R)
336  : SysAlias(N, E), NeedsReg(R) {}
337  constexpr SysAliasReg(const char *N, uint16_t E, bool R, FeatureBitset F)
338  : SysAlias(N, E, F), NeedsReg(R) {}
339 };
340 
343  constexpr SysAliasImm(const char *N, uint16_t E, uint16_t I)
344  : SysAlias(N, E), ImmValue(I) {}
345  constexpr SysAliasImm(const char *N, uint16_t E, uint16_t I, FeatureBitset F)
346  : SysAlias(N, E, F), ImmValue(I) {}
347 };
348 
349 namespace AArch64AT{
350  struct AT : SysAlias {
351  using SysAlias::SysAlias;
352  };
353  #define GET_AT_DECL
354  #include "AArch64GenSystemOperands.inc"
355 }
356 
357 namespace AArch64DB {
358  struct DB : SysAlias {
359  using SysAlias::SysAlias;
360  };
361  #define GET_DB_DECL
362  #include "AArch64GenSystemOperands.inc"
363 }
364 
365 namespace AArch64DBnXS {
366  struct DBnXS : SysAliasImm {
368  };
369  #define GET_DBNXS_DECL
370  #include "AArch64GenSystemOperands.inc"
371 }
372 
373 namespace AArch64DC {
374  struct DC : SysAlias {
375  using SysAlias::SysAlias;
376  };
377  #define GET_DC_DECL
378  #include "AArch64GenSystemOperands.inc"
379 }
380 
381 namespace AArch64IC {
382  struct IC : SysAliasReg {
384  };
385  #define GET_IC_DECL
386  #include "AArch64GenSystemOperands.inc"
387 }
388 
389 namespace AArch64ISB {
390  struct ISB : SysAlias {
391  using SysAlias::SysAlias;
392  };
393  #define GET_ISB_DECL
394  #include "AArch64GenSystemOperands.inc"
395 }
396 
397 namespace AArch64TSB {
398  struct TSB : SysAlias {
399  using SysAlias::SysAlias;
400  };
401  #define GET_TSB_DECL
402  #include "AArch64GenSystemOperands.inc"
403 }
404 
405 namespace AArch64PRFM {
406  struct PRFM : SysAlias {
407  using SysAlias::SysAlias;
408  };
409  #define GET_PRFM_DECL
410  #include "AArch64GenSystemOperands.inc"
411 }
412 
413 namespace AArch64SVEPRFM {
414  struct SVEPRFM : SysAlias {
415  using SysAlias::SysAlias;
416  };
417 #define GET_SVEPRFM_DECL
418 #include "AArch64GenSystemOperands.inc"
419 }
420 
421 namespace AArch64SVEPredPattern {
422  struct SVEPREDPAT {
423  const char *Name;
425  };
426 #define GET_SVEPREDPAT_DECL
427 #include "AArch64GenSystemOperands.inc"
428 }
429 
430 namespace AArch64ExactFPImm {
431  struct ExactFPImm {
432  const char *Name;
433  int Enum;
434  const char *Repr;
435  };
436 #define GET_EXACTFPIMM_DECL
437 #include "AArch64GenSystemOperands.inc"
438 }
439 
440 namespace AArch64PState {
441  struct PState : SysAlias{
442  using SysAlias::SysAlias;
443  };
444  #define GET_PSTATE_DECL
445  #include "AArch64GenSystemOperands.inc"
446 }
447 
448 namespace AArch64PSBHint {
449  struct PSB : SysAlias {
450  using SysAlias::SysAlias;
451  };
452  #define GET_PSB_DECL
453  #include "AArch64GenSystemOperands.inc"
454 }
455 
456 namespace AArch64BTIHint {
457  struct BTI : SysAlias {
458  using SysAlias::SysAlias;
459  };
460  #define GET_BTI_DECL
461  #include "AArch64GenSystemOperands.inc"
462 }
463 
464 namespace AArch64SE {
466  Invalid = -1,
472 
477 
482  };
483 }
484 
485 namespace AArch64Layout {
487  Invalid = -1,
492 
497 
498  // Bare layout for the 128-bit vector
499  // (only show ".b", ".h", ".s", ".d" without vector number)
504  };
505 }
506 
507 inline static const char *
509  switch (Layout) {
510  case AArch64Layout::VL_8B: return ".8b";
511  case AArch64Layout::VL_4H: return ".4h";
512  case AArch64Layout::VL_2S: return ".2s";
513  case AArch64Layout::VL_1D: return ".1d";
514  case AArch64Layout::VL_16B: return ".16b";
515  case AArch64Layout::VL_8H: return ".8h";
516  case AArch64Layout::VL_4S: return ".4s";
517  case AArch64Layout::VL_2D: return ".2d";
518  case AArch64Layout::VL_B: return ".b";
519  case AArch64Layout::VL_H: return ".h";
520  case AArch64Layout::VL_S: return ".s";
521  case AArch64Layout::VL_D: return ".d";
522  default: llvm_unreachable("Unknown Vector Layout");
523  }
524 }
525 
526 inline static AArch64Layout::VectorLayout
529  .Case(".8b", AArch64Layout::VL_8B)
530  .Case(".4h", AArch64Layout::VL_4H)
531  .Case(".2s", AArch64Layout::VL_2S)
532  .Case(".1d", AArch64Layout::VL_1D)
533  .Case(".16b", AArch64Layout::VL_16B)
534  .Case(".8h", AArch64Layout::VL_8H)
535  .Case(".4s", AArch64Layout::VL_4S)
536  .Case(".2d", AArch64Layout::VL_2D)
537  .Case(".b", AArch64Layout::VL_B)
538  .Case(".h", AArch64Layout::VL_H)
539  .Case(".s", AArch64Layout::VL_S)
540  .Case(".d", AArch64Layout::VL_D)
542 }
543 
544 namespace AArch64SysReg {
545  struct SysReg {
546  const char *Name;
547  unsigned Encoding;
548  bool Readable;
549  bool Writeable;
551 
552  bool haveFeatures(FeatureBitset ActiveFeatures) const {
553  return (FeaturesRequired & ActiveFeatures) == FeaturesRequired;
554  }
555  };
556 
557  #define GET_SYSREG_DECL
558  #include "AArch64GenSystemOperands.inc"
559 
560  const SysReg *lookupSysRegByName(StringRef);
561  const SysReg *lookupSysRegByEncoding(uint16_t);
562 
564  std::string genericRegisterString(uint32_t Bits);
565 }
566 
567 namespace AArch64TLBI {
568  struct TLBI : SysAliasReg {
570  };
571  #define GET_TLBITable_DECL
572  #include "AArch64GenSystemOperands.inc"
573 }
574 
575 namespace AArch64PRCTX {
576  struct PRCTX : SysAliasReg {
578  };
579  #define GET_PRCTX_DECL
580  #include "AArch64GenSystemOperands.inc"
581 }
582 
583 namespace AArch64II {
584  /// Target Operand Flag enum.
585  enum TOF {
586  //===------------------------------------------------------------------===//
587  // AArch64 Specific MachineOperand flags.
588 
590 
591  MO_FRAGMENT = 0x7,
592 
593  /// MO_PAGE - A symbol operand with this flag represents the pc-relative
594  /// offset of the 4K page containing the symbol. This is used with the
595  /// ADRP instruction.
596  MO_PAGE = 1,
597 
598  /// MO_PAGEOFF - A symbol operand with this flag represents the offset of
599  /// that symbol within a 4K page. This offset is added to the page address
600  /// to produce the complete address.
602 
603  /// MO_G3 - A symbol operand with this flag (granule 3) represents the high
604  /// 16-bits of a 64-bit address, used in a MOVZ or MOVK instruction
605  MO_G3 = 3,
606 
607  /// MO_G2 - A symbol operand with this flag (granule 2) represents the bits
608  /// 32-47 of a 64-bit address, used in a MOVZ or MOVK instruction
609  MO_G2 = 4,
610 
611  /// MO_G1 - A symbol operand with this flag (granule 1) represents the bits
612  /// 16-31 of a 64-bit address, used in a MOVZ or MOVK instruction
613  MO_G1 = 5,
614 
615  /// MO_G0 - A symbol operand with this flag (granule 0) represents the bits
616  /// 0-15 of a 64-bit address, used in a MOVZ or MOVK instruction
617  MO_G0 = 6,
618 
619  /// MO_HI12 - This flag indicates that a symbol operand represents the bits
620  /// 13-24 of a 64-bit address, used in a arithmetic immediate-shifted-left-
621  /// by-12-bits instruction.
622  MO_HI12 = 7,
623 
624  /// MO_COFFSTUB - On a symbol operand "FOO", this indicates that the
625  /// reference is actually to the ".refptr.FOO" symbol. This is used for
626  /// stub symbols on windows.
627  MO_COFFSTUB = 0x8,
628 
629  /// MO_GOT - This flag indicates that a symbol operand represents the
630  /// address of the GOT entry for the symbol, rather than the address of
631  /// the symbol itself.
632  MO_GOT = 0x10,
633 
634  /// MO_NC - Indicates whether the linker is expected to check the symbol
635  /// reference for overflow. For example in an ADRP/ADD pair of relocations
636  /// the ADRP usually does check, but not the ADD.
637  MO_NC = 0x20,
638 
639  /// MO_TLS - Indicates that the operand being accessed is some kind of
640  /// thread-local symbol. On Darwin, only one type of thread-local access
641  /// exists (pre linker-relaxation), but on ELF the TLSModel used for the
642  /// referee will affect interpretation.
643  MO_TLS = 0x40,
644 
645  /// MO_DLLIMPORT - On a symbol operand, this represents that the reference
646  /// to the symbol is for an import stub. This is used for DLL import
647  /// storage class indication on Windows.
648  MO_DLLIMPORT = 0x80,
649 
650  /// MO_S - Indicates that the bits of the symbol operand represented by
651  /// MO_G0 etc are signed.
652  MO_S = 0x100,
653 
654  /// MO_PREL - Indicates that the bits of the symbol operand represented by
655  /// MO_G0 etc are PC relative.
656  MO_PREL = 0x200,
657 
658  /// MO_TAGGED - With MO_PAGE, indicates that the page includes a memory tag
659  /// in bits 56-63.
660  /// On a FrameIndex operand, indicates that the underlying memory is tagged
661  /// with an unknown tag value (MTE); this needs to be lowered either to an
662  /// SP-relative load or store instruction (which do not check tags), or to
663  /// an LDG instruction to obtain the tag value.
664  MO_TAGGED = 0x400,
665  };
666 } // end namespace AArch64II
667 
668 namespace AArch64 {
669 // The number of bits in a SVE register is architecturally defined
670 // to be a multiple of this value. If <M x t> has this number of bits,
671 // a <n x M x t> vector can be stored in a SVE register without any
672 // redundant bits. If <M x t> has this number of bits divided by P,
673 // a <n x M x t> vector is stored in a SVE register by placing index i
674 // in index i*P of a <n x (M*P) x t> vector. The other elements of the
675 // <n x (M*P) x t> vector (such as index 1) are undefined.
676 static constexpr unsigned SVEBitsPerBlock = 128;
677 static constexpr unsigned SVEMaxBitsPerVector = 2048;
678 const unsigned NeonBitsPerVector = 128;
679 } // end namespace AArch64
680 } // end namespace llvm
681 
682 #endif
llvm::StringSwitch::Case
StringSwitch & Case(StringLiteral S, T Value)
Definition: StringSwitch.h:67
llvm::SysAliasImm
Definition: AArch64BaseInfo.h:341
llvm::AArch64II::MO_G3
@ MO_G3
MO_G3 - A symbol operand with this flag (granule 3) represents the high 16-bits of a 64-bit address,...
Definition: AArch64BaseInfo.h:605
llvm::AArch64SE::UXTW
@ UXTW
Definition: AArch64BaseInfo.h:475
llvm::AArch64Layout::VL_2S
@ VL_2S
Definition: AArch64BaseInfo.h:490
llvm::AArch64CC::Invalid
@ Invalid
Definition: AArch64BaseInfo.h:253
llvm::AArch64CC::LO
@ LO
Definition: AArch64BaseInfo.h:239
llvm::AArch64CC::HI
@ HI
Definition: AArch64BaseInfo.h:244
llvm
Definition: AllocatorList.h:23
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::AArch64CC::AL
@ AL
Definition: AArch64BaseInfo.h:250
llvm::AArch64CC::NE
@ NE
Definition: AArch64BaseInfo.h:237
llvm::AArch64II::MO_HI12
@ MO_HI12
MO_HI12 - This flag indicates that a symbol operand represents the bits 13-24 of a 64-bit address,...
Definition: AArch64BaseInfo.h:622
llvm::AArch64CC::getNZCVToSatisfyCondCode
static unsigned getNZCVToSatisfyCondCode(CondCode Code)
Given a condition code, return NZCV flags that would satisfy that condition.
Definition: AArch64BaseInfo.h:294
llvm::AArch64II::MO_G1
@ MO_G1
MO_G1 - A symbol operand with this flag (granule 1) represents the bits 16-31 of a 64-bit address,...
Definition: AArch64BaseInfo.h:613
llvm::AArch64CC::MI
@ MI
Definition: AArch64BaseInfo.h:240
llvm::AArch64SysReg::SysReg::FeaturesRequired
FeatureBitset FeaturesRequired
Definition: AArch64BaseInfo.h:550
llvm::StringSwitch::Default
LLVM_NODISCARD R Default(T Value)
Definition: StringSwitch.h:181
llvm::AArch64CC::NONE_ACTIVE
@ NONE_ACTIVE
Definition: AArch64BaseInfo.h:259
llvm::AArch64SysReg::lookupSysRegByName
const SysReg * lookupSysRegByName(StringRef)
llvm::SysAlias
Definition: AArch64BaseInfo.h:317
llvm::AArch64TLBI::TLBI
Definition: AArch64BaseInfo.h:568
llvm::SysAlias::SysAlias
constexpr SysAlias(const char *N, uint16_t E)
Definition: AArch64BaseInfo.h:322
llvm::AArch64CC::FIRST_ACTIVE
@ FIRST_ACTIVE
Definition: AArch64BaseInfo.h:257
ErrorHandling.h
llvm::SysAliasReg::SysAliasReg
constexpr SysAliasReg(const char *N, uint16_t E, bool R)
Definition: AArch64BaseInfo.h:335
llvm::AArch64SysReg::SysReg::Name
const char * Name
Definition: AArch64BaseInfo.h:546
llvm::AArch64Layout::Invalid
@ Invalid
Definition: AArch64BaseInfo.h:487
llvm::AArch64ExactFPImm::ExactFPImm::Repr
const char * Repr
Definition: AArch64BaseInfo.h:434
llvm::AArch64II::MO_PREL
@ MO_PREL
MO_PREL - Indicates that the bits of the symbol operand represented by MO_G0 etc are PC relative.
Definition: AArch64BaseInfo.h:656
llvm::AArch64CC::ANY_ACTIVE
@ ANY_ACTIVE
Definition: AArch64BaseInfo.h:256
llvm::SysAliasReg
Definition: AArch64BaseInfo.h:333
llvm::AArch64Layout::VL_B
@ VL_B
Definition: AArch64BaseInfo.h:500
llvm::tgtok::Bits
@ Bits
Definition: TGLexer.h:50
llvm::AArch64PRCTX::PRCTX
Definition: AArch64BaseInfo.h:576
llvm::SysAliasImm::SysAliasImm
constexpr SysAliasImm(const char *N, uint16_t E, uint16_t I)
Definition: AArch64BaseInfo.h:343
llvm::FeatureBitset
Container class for subtarget features.
Definition: SubtargetFeature.h:40
llvm::AArch64SysReg::SysReg
Definition: AArch64BaseInfo.h:545
STLExtras.h
llvm::AArch64Layout::VL_16B
@ VL_16B
Definition: AArch64BaseInfo.h:493
llvm::SysAlias::getRequiredFeatures
FeatureBitset getRequiredFeatures() const
Definition: AArch64BaseInfo.h:330
llvm::AArch64SE::UXTH
@ UXTH
Definition: AArch64BaseInfo.h:474
llvm::AArch64ISB::ISB
Definition: AArch64BaseInfo.h:390
llvm::AArch64SE::UXTX
@ UXTX
Definition: AArch64BaseInfo.h:476
F
#define F(x, y, z)
Definition: MD5.cpp:56
llvm::AArch64II::MO_TLS
@ MO_TLS
MO_TLS - Indicates that the operand being accessed is some kind of thread-local symbol.
Definition: AArch64BaseInfo.h:643
llvm::AArch64CC::LT
@ LT
Definition: AArch64BaseInfo.h:247
llvm::AArch64SE::SXTB
@ SXTB
Definition: AArch64BaseInfo.h:478
llvm::AArch64SysReg::SysReg::Writeable
bool Writeable
Definition: AArch64BaseInfo.h:549
llvm::AArch64SVEPredPattern::SVEPREDPAT
Definition: AArch64BaseInfo.h:422
llvm::AArch64SVEPredPattern::SVEPREDPAT::Encoding
uint16_t Encoding
Definition: AArch64BaseInfo.h:424
llvm::AArch64II::MO_G0
@ MO_G0
MO_G0 - A symbol operand with this flag (granule 0) represents the bits 0-15 of a 64-bit address,...
Definition: AArch64BaseInfo.h:617
SubtargetFeature.h
llvm::AArch64Layout::VectorLayout
VectorLayout
Definition: AArch64BaseInfo.h:486
llvm::AArch64CC::VC
@ VC
Definition: AArch64BaseInfo.h:243
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::AArch64Layout::VL_S
@ VL_S
Definition: AArch64BaseInfo.h:502
llvm::AArch64Layout::VL_8B
@ VL_8B
Definition: AArch64BaseInfo.h:488
llvm::AArch64Layout::VL_4S
@ VL_4S
Definition: AArch64BaseInfo.h:495
llvm::AArch64CC::HS
@ HS
Definition: AArch64BaseInfo.h:238
llvm::AArch64IC::IC
Definition: AArch64BaseInfo.h:382
llvm::AArch64DC::DC
Definition: AArch64BaseInfo.h:374
llvm::AArch64Layout::VL_8H
@ VL_8H
Definition: AArch64BaseInfo.h:494
llvm::AArch64CC::LE
@ LE
Definition: AArch64BaseInfo.h:249
llvm::AArch64ExactFPImm::ExactFPImm
Definition: AArch64BaseInfo.h:431
llvm::AArch64CC::PL
@ PL
Definition: AArch64BaseInfo.h:241
llvm::AArch64CC::getCondCodeName
static const char * getCondCodeName(CondCode Code)
Definition: AArch64BaseInfo.h:262
llvm::SysAliasImm::SysAliasImm
constexpr SysAliasImm(const char *N, uint16_t E, uint16_t I, FeatureBitset F)
Definition: AArch64BaseInfo.h:345
llvm::AArch64Layout::VL_1D
@ VL_1D
Definition: AArch64BaseInfo.h:491
llvm::AArch64BTIHint::BTI
Definition: AArch64BaseInfo.h:457
llvm::AArch64Layout::VL_H
@ VL_H
Definition: AArch64BaseInfo.h:501
llvm::AArch64II::MO_S
@ MO_S
MO_S - Indicates that the bits of the symbol operand represented by MO_G0 etc are signed.
Definition: AArch64BaseInfo.h:652
llvm::AArch64AT::AT
Definition: AArch64BaseInfo.h:350
llvm::AArch64II::MO_DLLIMPORT
@ MO_DLLIMPORT
MO_DLLIMPORT - On a symbol operand, this represents that the reference to the symbol is for an import...
Definition: AArch64BaseInfo.h:648
llvm::AArch64Layout::VL_2D
@ VL_2D
Definition: AArch64BaseInfo.h:496
llvm::AArch64::SVEBitsPerBlock
static constexpr unsigned SVEBitsPerBlock
Definition: AArch64BaseInfo.h:676
llvm::AArch64PState::PState
Definition: AArch64BaseInfo.h:441
llvm::AArch64PSBHint::PSB
Definition: AArch64BaseInfo.h:449
llvm::AArch64II::MO_NC
@ MO_NC
MO_NC - Indicates whether the linker is expected to check the symbol reference for overflow.
Definition: AArch64BaseInfo.h:637
llvm::AArch64II::MO_PAGEOFF
@ MO_PAGEOFF
MO_PAGEOFF - A symbol operand with this flag represents the offset of that symbol within a 4K page.
Definition: AArch64BaseInfo.h:601
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::SysAlias::Name
const char * Name
Definition: AArch64BaseInfo.h:318
llvm::AArch64II::MO_NO_FLAG
@ MO_NO_FLAG
Definition: AArch64BaseInfo.h:589
llvm::AArch64Layout::VL_D
@ VL_D
Definition: AArch64BaseInfo.h:503
llvm::SysAliasImm::ImmValue
uint16_t ImmValue
Definition: AArch64BaseInfo.h:342
llvm::AArch64SysReg::parseGenericRegister
uint32_t parseGenericRegister(StringRef Name)
Definition: AArch64BaseInfo.cpp:133
llvm::AArch64SE::LSL
@ LSL
Definition: AArch64BaseInfo.h:467
llvm::AArch64SysReg::SysReg::Encoding
unsigned Encoding
Definition: AArch64BaseInfo.h:547
llvm::AArch64SE::UXTB
@ UXTB
Definition: AArch64BaseInfo.h:473
llvm::AArch64CC::LAST_ACTIVE
@ LAST_ACTIVE
Definition: AArch64BaseInfo.h:258
llvm::AArch64VectorLayoutToString
static const char * AArch64VectorLayoutToString(AArch64Layout::VectorLayout Layout)
Definition: AArch64BaseInfo.h:508
llvm::AArch64PRFM::PRFM
Definition: AArch64BaseInfo.h:406
llvm::getBRegFromDReg
static unsigned getBRegFromDReg(unsigned Reg)
Definition: AArch64BaseInfo.h:109
llvm::AArch64II::TOF
TOF
Target Operand Flag enum.
Definition: AArch64BaseInfo.h:585
llvm::AArch64II::MO_FRAGMENT
@ MO_FRAGMENT
Definition: AArch64BaseInfo.h:591
llvm::AArch64SE::ROR
@ ROR
Definition: AArch64BaseInfo.h:471
llvm::AArch64CC::GE
@ GE
Definition: AArch64BaseInfo.h:246
llvm::atomicBarrierDroppedOnZero
static bool atomicBarrierDroppedOnZero(unsigned Opcode)
Definition: AArch64BaseInfo.h:188
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
llvm::AArch64SE::ShiftExtSpecifiers
ShiftExtSpecifiers
Definition: AArch64BaseInfo.h:465
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:136
uint32_t
llvm::AArch64SysReg::SysReg::Readable
bool Readable
Definition: AArch64BaseInfo.h:548
llvm::AArch64SE::SXTH
@ SXTH
Definition: AArch64BaseInfo.h:479
llvm::AArch64CC::EQ
@ EQ
Definition: AArch64BaseInfo.h:236
llvm::AArch64ExactFPImm::ExactFPImm::Enum
int Enum
Definition: AArch64BaseInfo.h:433
llvm::getXRegFromWReg
static unsigned getXRegFromWReg(unsigned Reg)
Definition: AArch64BaseInfo.h:69
llvm::AArch64DBnXS::DBnXS
Definition: AArch64BaseInfo.h:366
llvm::AArch64SVEPRFM::SVEPRFM
Definition: AArch64BaseInfo.h:414
llvm::AArch64SysReg::lookupSysRegByEncoding
const SysReg * lookupSysRegByEncoding(uint16_t)
llvm::GraphProgram::Name
Name
Definition: GraphWriter.h:52
llvm::AArch64CC::VS
@ VS
Definition: AArch64BaseInfo.h:242
uint16_t
llvm::SysAliasReg::NeedsReg
bool NeedsReg
Definition: AArch64BaseInfo.h:334
llvm::AArch64TSB::TSB
Definition: AArch64BaseInfo.h:398
llvm::AArch64SysReg::genericRegisterString
std::string genericRegisterString(uint32_t Bits)
Definition: AArch64BaseInfo.cpp:154
llvm::AArch64SE::SXTX
@ SXTX
Definition: AArch64BaseInfo.h:481
llvm::AArch64SE::ASR
@ ASR
Definition: AArch64BaseInfo.h:470
llvm::AArch64CC::LS
@ LS
Definition: AArch64BaseInfo.h:245
llvm::AArch64StringToVectorLayout
static AArch64Layout::VectorLayout AArch64StringToVectorLayout(StringRef LayoutStr)
Definition: AArch64BaseInfo.h:527
llvm::SysAlias::SysAlias
constexpr SysAlias(const char *N, uint16_t E, FeatureBitset F)
Definition: AArch64BaseInfo.h:323
AArch64MCTargetDesc.h
StringSwitch.h
llvm::AArch64CC::getInvertedCondCode
static CondCode getInvertedCondCode(CondCode Code)
Definition: AArch64BaseInfo.h:284
llvm::AArch64SE::MSL
@ MSL
Definition: AArch64BaseInfo.h:468
llvm::AArch64::NeonBitsPerVector
const unsigned NeonBitsPerVector
Definition: AArch64BaseInfo.h:678
llvm::AArch64CC::GT
@ GT
Definition: AArch64BaseInfo.h:248
llvm::SysAliasReg::SysAliasReg
constexpr SysAliasReg(const char *N, uint16_t E, bool R, FeatureBitset F)
Definition: AArch64BaseInfo.h:337
llvm::AArch64DB::DB
Definition: AArch64BaseInfo.h:358
llvm::AArch64CC::NV
@ NV
Definition: AArch64BaseInfo.h:251
llvm::getWRegFromXReg
static unsigned getWRegFromXReg(unsigned Reg)
Definition: AArch64BaseInfo.h:29
llvm::AArch64Layout::VL_4H
@ VL_4H
Definition: AArch64BaseInfo.h:489
N
#define N
llvm::AArch64SE::LSR
@ LSR
Definition: AArch64BaseInfo.h:469
llvm::SysAlias::Encoding
uint16_t Encoding
Definition: AArch64BaseInfo.h:319
llvm::SysAlias::haveFeatures
bool haveFeatures(FeatureBitset ActiveFeatures) const
Definition: AArch64BaseInfo.h:326
llvm::AArch64SE::SXTW
@ SXTW
Definition: AArch64BaseInfo.h:480
llvm::getDRegFromBReg
static unsigned getDRegFromBReg(unsigned Reg)
Definition: AArch64BaseInfo.h:149
llvm::SysAlias::FeaturesRequired
FeatureBitset FeaturesRequired
Definition: AArch64BaseInfo.h:320
llvm::AArch64CC::CondCode
CondCode
Definition: AArch64BaseInfo.h:235
llvm::StringSwitch
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:42
llvm::AArch64II::MO_G2
@ MO_G2
MO_G2 - A symbol operand with this flag (granule 2) represents the bits 32-47 of a 64-bit address,...
Definition: AArch64BaseInfo.h:609
llvm::AArch64II::MO_COFFSTUB
@ MO_COFFSTUB
MO_COFFSTUB - On a symbol operand "FOO", this indicates that the reference is actually to the "....
Definition: AArch64BaseInfo.h:627
llvm::AArch64::SVEMaxBitsPerVector
static constexpr unsigned SVEMaxBitsPerVector
Definition: AArch64BaseInfo.h:677
llvm::AArch64II::MO_TAGGED
@ MO_TAGGED
MO_TAGGED - With MO_PAGE, indicates that the page includes a memory tag in bits 56-63.
Definition: AArch64BaseInfo.h:664
llvm::AArch64SE::Invalid
@ Invalid
Definition: AArch64BaseInfo.h:466
llvm::AArch64SVEPredPattern::SVEPREDPAT::Name
const char * Name
Definition: AArch64BaseInfo.h:423
llvm::AArch64II::MO_GOT
@ MO_GOT
MO_GOT - This flag indicates that a symbol operand represents the address of the GOT entry for the sy...
Definition: AArch64BaseInfo.h:632
llvm::AArch64ExactFPImm::ExactFPImm::Name
const char * Name
Definition: AArch64BaseInfo.h:432
llvm::AArch64II::MO_PAGE
@ MO_PAGE
MO_PAGE - A symbol operand with this flag represents the pc-relative offset of the 4K page containing...
Definition: AArch64BaseInfo.h:596
llvm::AArch64SysReg::SysReg::haveFeatures
bool haveFeatures(FeatureBitset ActiveFeatures) const
Definition: AArch64BaseInfo.h:552