LLVM  14.0.0git
AArch64BaseInfo.h
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1 //===-- AArch64BaseInfo.h - Top level definitions for AArch64 ---*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains small standalone helper functions and enum definitions for
10 // the AArch64 target useful for the compiler back-end and the MC libraries.
11 // As such, it deliberately does not include references to LLVM core
12 // code gen types, passes, etc..
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #ifndef LLVM_LIB_TARGET_AARCH64_UTILS_AARCH64BASEINFO_H
17 #define LLVM_LIB_TARGET_AARCH64_UTILS_AARCH64BASEINFO_H
18 
19 // FIXME: Is it easiest to fix this layering violation by moving the .inc
20 // #includes from AArch64MCTargetDesc.h to here?
21 #include "MCTargetDesc/AArch64MCTargetDesc.h" // For AArch64::X0 and friends.
22 #include "llvm/ADT/STLExtras.h"
23 #include "llvm/ADT/StringSwitch.h"
26 
27 namespace llvm {
28 
29 inline static unsigned getWRegFromXReg(unsigned Reg) {
30  switch (Reg) {
31  case AArch64::X0: return AArch64::W0;
32  case AArch64::X1: return AArch64::W1;
33  case AArch64::X2: return AArch64::W2;
34  case AArch64::X3: return AArch64::W3;
35  case AArch64::X4: return AArch64::W4;
36  case AArch64::X5: return AArch64::W5;
37  case AArch64::X6: return AArch64::W6;
38  case AArch64::X7: return AArch64::W7;
39  case AArch64::X8: return AArch64::W8;
40  case AArch64::X9: return AArch64::W9;
41  case AArch64::X10: return AArch64::W10;
42  case AArch64::X11: return AArch64::W11;
43  case AArch64::X12: return AArch64::W12;
44  case AArch64::X13: return AArch64::W13;
45  case AArch64::X14: return AArch64::W14;
46  case AArch64::X15: return AArch64::W15;
47  case AArch64::X16: return AArch64::W16;
48  case AArch64::X17: return AArch64::W17;
49  case AArch64::X18: return AArch64::W18;
50  case AArch64::X19: return AArch64::W19;
51  case AArch64::X20: return AArch64::W20;
52  case AArch64::X21: return AArch64::W21;
53  case AArch64::X22: return AArch64::W22;
54  case AArch64::X23: return AArch64::W23;
55  case AArch64::X24: return AArch64::W24;
56  case AArch64::X25: return AArch64::W25;
57  case AArch64::X26: return AArch64::W26;
58  case AArch64::X27: return AArch64::W27;
59  case AArch64::X28: return AArch64::W28;
60  case AArch64::FP: return AArch64::W29;
61  case AArch64::LR: return AArch64::W30;
62  case AArch64::SP: return AArch64::WSP;
63  case AArch64::XZR: return AArch64::WZR;
64  }
65  // For anything else, return it unchanged.
66  return Reg;
67 }
68 
69 inline static unsigned getXRegFromWReg(unsigned Reg) {
70  switch (Reg) {
71  case AArch64::W0: return AArch64::X0;
72  case AArch64::W1: return AArch64::X1;
73  case AArch64::W2: return AArch64::X2;
74  case AArch64::W3: return AArch64::X3;
75  case AArch64::W4: return AArch64::X4;
76  case AArch64::W5: return AArch64::X5;
77  case AArch64::W6: return AArch64::X6;
78  case AArch64::W7: return AArch64::X7;
79  case AArch64::W8: return AArch64::X8;
80  case AArch64::W9: return AArch64::X9;
81  case AArch64::W10: return AArch64::X10;
82  case AArch64::W11: return AArch64::X11;
83  case AArch64::W12: return AArch64::X12;
84  case AArch64::W13: return AArch64::X13;
85  case AArch64::W14: return AArch64::X14;
86  case AArch64::W15: return AArch64::X15;
87  case AArch64::W16: return AArch64::X16;
88  case AArch64::W17: return AArch64::X17;
89  case AArch64::W18: return AArch64::X18;
90  case AArch64::W19: return AArch64::X19;
91  case AArch64::W20: return AArch64::X20;
92  case AArch64::W21: return AArch64::X21;
93  case AArch64::W22: return AArch64::X22;
94  case AArch64::W23: return AArch64::X23;
95  case AArch64::W24: return AArch64::X24;
96  case AArch64::W25: return AArch64::X25;
97  case AArch64::W26: return AArch64::X26;
98  case AArch64::W27: return AArch64::X27;
99  case AArch64::W28: return AArch64::X28;
100  case AArch64::W29: return AArch64::FP;
101  case AArch64::W30: return AArch64::LR;
102  case AArch64::WSP: return AArch64::SP;
103  case AArch64::WZR: return AArch64::XZR;
104  }
105  // For anything else, return it unchanged.
106  return Reg;
107 }
108 
109 inline static unsigned getXRegFromXRegTuple(unsigned RegTuple) {
110  switch (RegTuple) {
111  case AArch64::X0_X1_X2_X3_X4_X5_X6_X7: return AArch64::X0;
112  case AArch64::X2_X3_X4_X5_X6_X7_X8_X9: return AArch64::X2;
113  case AArch64::X4_X5_X6_X7_X8_X9_X10_X11: return AArch64::X4;
114  case AArch64::X6_X7_X8_X9_X10_X11_X12_X13: return AArch64::X6;
115  case AArch64::X8_X9_X10_X11_X12_X13_X14_X15: return AArch64::X8;
116  case AArch64::X10_X11_X12_X13_X14_X15_X16_X17: return AArch64::X10;
117  case AArch64::X12_X13_X14_X15_X16_X17_X18_X19: return AArch64::X12;
118  case AArch64::X14_X15_X16_X17_X18_X19_X20_X21: return AArch64::X14;
119  case AArch64::X16_X17_X18_X19_X20_X21_X22_X23: return AArch64::X16;
120  case AArch64::X18_X19_X20_X21_X22_X23_X24_X25: return AArch64::X18;
121  case AArch64::X20_X21_X22_X23_X24_X25_X26_X27: return AArch64::X20;
122  case AArch64::X22_X23_X24_X25_X26_X27_X28_FP: return AArch64::X22;
123  }
124  // For anything else, return it unchanged.
125  return RegTuple;
126 }
127 
128 static inline unsigned getBRegFromDReg(unsigned Reg) {
129  switch (Reg) {
130  case AArch64::D0: return AArch64::B0;
131  case AArch64::D1: return AArch64::B1;
132  case AArch64::D2: return AArch64::B2;
133  case AArch64::D3: return AArch64::B3;
134  case AArch64::D4: return AArch64::B4;
135  case AArch64::D5: return AArch64::B5;
136  case AArch64::D6: return AArch64::B6;
137  case AArch64::D7: return AArch64::B7;
138  case AArch64::D8: return AArch64::B8;
139  case AArch64::D9: return AArch64::B9;
140  case AArch64::D10: return AArch64::B10;
141  case AArch64::D11: return AArch64::B11;
142  case AArch64::D12: return AArch64::B12;
143  case AArch64::D13: return AArch64::B13;
144  case AArch64::D14: return AArch64::B14;
145  case AArch64::D15: return AArch64::B15;
146  case AArch64::D16: return AArch64::B16;
147  case AArch64::D17: return AArch64::B17;
148  case AArch64::D18: return AArch64::B18;
149  case AArch64::D19: return AArch64::B19;
150  case AArch64::D20: return AArch64::B20;
151  case AArch64::D21: return AArch64::B21;
152  case AArch64::D22: return AArch64::B22;
153  case AArch64::D23: return AArch64::B23;
154  case AArch64::D24: return AArch64::B24;
155  case AArch64::D25: return AArch64::B25;
156  case AArch64::D26: return AArch64::B26;
157  case AArch64::D27: return AArch64::B27;
158  case AArch64::D28: return AArch64::B28;
159  case AArch64::D29: return AArch64::B29;
160  case AArch64::D30: return AArch64::B30;
161  case AArch64::D31: return AArch64::B31;
162  }
163  // For anything else, return it unchanged.
164  return Reg;
165 }
166 
167 
168 static inline unsigned getDRegFromBReg(unsigned Reg) {
169  switch (Reg) {
170  case AArch64::B0: return AArch64::D0;
171  case AArch64::B1: return AArch64::D1;
172  case AArch64::B2: return AArch64::D2;
173  case AArch64::B3: return AArch64::D3;
174  case AArch64::B4: return AArch64::D4;
175  case AArch64::B5: return AArch64::D5;
176  case AArch64::B6: return AArch64::D6;
177  case AArch64::B7: return AArch64::D7;
178  case AArch64::B8: return AArch64::D8;
179  case AArch64::B9: return AArch64::D9;
180  case AArch64::B10: return AArch64::D10;
181  case AArch64::B11: return AArch64::D11;
182  case AArch64::B12: return AArch64::D12;
183  case AArch64::B13: return AArch64::D13;
184  case AArch64::B14: return AArch64::D14;
185  case AArch64::B15: return AArch64::D15;
186  case AArch64::B16: return AArch64::D16;
187  case AArch64::B17: return AArch64::D17;
188  case AArch64::B18: return AArch64::D18;
189  case AArch64::B19: return AArch64::D19;
190  case AArch64::B20: return AArch64::D20;
191  case AArch64::B21: return AArch64::D21;
192  case AArch64::B22: return AArch64::D22;
193  case AArch64::B23: return AArch64::D23;
194  case AArch64::B24: return AArch64::D24;
195  case AArch64::B25: return AArch64::D25;
196  case AArch64::B26: return AArch64::D26;
197  case AArch64::B27: return AArch64::D27;
198  case AArch64::B28: return AArch64::D28;
199  case AArch64::B29: return AArch64::D29;
200  case AArch64::B30: return AArch64::D30;
201  case AArch64::B31: return AArch64::D31;
202  }
203  // For anything else, return it unchanged.
204  return Reg;
205 }
206 
207 static inline bool atomicBarrierDroppedOnZero(unsigned Opcode) {
208  switch (Opcode) {
209  case AArch64::LDADDAB: case AArch64::LDADDAH:
210  case AArch64::LDADDAW: case AArch64::LDADDAX:
211  case AArch64::LDADDALB: case AArch64::LDADDALH:
212  case AArch64::LDADDALW: case AArch64::LDADDALX:
213  case AArch64::LDCLRAB: case AArch64::LDCLRAH:
214  case AArch64::LDCLRAW: case AArch64::LDCLRAX:
215  case AArch64::LDCLRALB: case AArch64::LDCLRALH:
216  case AArch64::LDCLRALW: case AArch64::LDCLRALX:
217  case AArch64::LDEORAB: case AArch64::LDEORAH:
218  case AArch64::LDEORAW: case AArch64::LDEORAX:
219  case AArch64::LDEORALB: case AArch64::LDEORALH:
220  case AArch64::LDEORALW: case AArch64::LDEORALX:
221  case AArch64::LDSETAB: case AArch64::LDSETAH:
222  case AArch64::LDSETAW: case AArch64::LDSETAX:
223  case AArch64::LDSETALB: case AArch64::LDSETALH:
224  case AArch64::LDSETALW: case AArch64::LDSETALX:
225  case AArch64::LDSMAXAB: case AArch64::LDSMAXAH:
226  case AArch64::LDSMAXAW: case AArch64::LDSMAXAX:
227  case AArch64::LDSMAXALB: case AArch64::LDSMAXALH:
228  case AArch64::LDSMAXALW: case AArch64::LDSMAXALX:
229  case AArch64::LDSMINAB: case AArch64::LDSMINAH:
230  case AArch64::LDSMINAW: case AArch64::LDSMINAX:
231  case AArch64::LDSMINALB: case AArch64::LDSMINALH:
232  case AArch64::LDSMINALW: case AArch64::LDSMINALX:
233  case AArch64::LDUMAXAB: case AArch64::LDUMAXAH:
234  case AArch64::LDUMAXAW: case AArch64::LDUMAXAX:
235  case AArch64::LDUMAXALB: case AArch64::LDUMAXALH:
236  case AArch64::LDUMAXALW: case AArch64::LDUMAXALX:
237  case AArch64::LDUMINAB: case AArch64::LDUMINAH:
238  case AArch64::LDUMINAW: case AArch64::LDUMINAX:
239  case AArch64::LDUMINALB: case AArch64::LDUMINALH:
240  case AArch64::LDUMINALW: case AArch64::LDUMINALX:
241  case AArch64::SWPAB: case AArch64::SWPAH:
242  case AArch64::SWPAW: case AArch64::SWPAX:
243  case AArch64::SWPALB: case AArch64::SWPALH:
244  case AArch64::SWPALW: case AArch64::SWPALX:
245  return true;
246  }
247  return false;
248 }
249 
250 namespace AArch64CC {
251 
252 // The CondCodes constants map directly to the 4-bit encoding of the condition
253 // field for predicated instructions.
254 enum CondCode { // Meaning (integer) Meaning (floating-point)
255  EQ = 0x0, // Equal Equal
256  NE = 0x1, // Not equal Not equal, or unordered
257  HS = 0x2, // Unsigned higher or same >, ==, or unordered
258  LO = 0x3, // Unsigned lower Less than
259  MI = 0x4, // Minus, negative Less than
260  PL = 0x5, // Plus, positive or zero >, ==, or unordered
261  VS = 0x6, // Overflow Unordered
262  VC = 0x7, // No overflow Not unordered
263  HI = 0x8, // Unsigned higher Greater than, or unordered
264  LS = 0x9, // Unsigned lower or same Less than or equal
265  GE = 0xa, // Greater than or equal Greater than or equal
266  LT = 0xb, // Less than Less than, or unordered
267  GT = 0xc, // Greater than Greater than
268  LE = 0xd, // Less than or equal <, ==, or unordered
269  AL = 0xe, // Always (unconditional) Always (unconditional)
270  NV = 0xf, // Always (unconditional) Always (unconditional)
271  // Note the NV exists purely to disassemble 0b1111. Execution is "always".
273 
274  // Common aliases used for SVE.
275  ANY_ACTIVE = NE, // (!Z)
276  FIRST_ACTIVE = MI, // ( N)
277  LAST_ACTIVE = LO, // (!C)
278  NONE_ACTIVE = EQ // ( Z)
279 };
280 
281 inline static const char *getCondCodeName(CondCode Code) {
282  switch (Code) {
283  default: llvm_unreachable("Unknown condition code");
284  case EQ: return "eq";
285  case NE: return "ne";
286  case HS: return "hs";
287  case LO: return "lo";
288  case MI: return "mi";
289  case PL: return "pl";
290  case VS: return "vs";
291  case VC: return "vc";
292  case HI: return "hi";
293  case LS: return "ls";
294  case GE: return "ge";
295  case LT: return "lt";
296  case GT: return "gt";
297  case LE: return "le";
298  case AL: return "al";
299  case NV: return "nv";
300  }
301 }
302 
303 inline static CondCode getInvertedCondCode(CondCode Code) {
304  // To reverse a condition it's necessary to only invert the low bit:
305 
306  return static_cast<CondCode>(static_cast<unsigned>(Code) ^ 0x1);
307 }
308 
309 /// Given a condition code, return NZCV flags that would satisfy that condition.
310 /// The flag bits are in the format expected by the ccmp instructions.
311 /// Note that many different flag settings can satisfy a given condition code,
312 /// this function just returns one of them.
313 inline static unsigned getNZCVToSatisfyCondCode(CondCode Code) {
314  // NZCV flags encoded as expected by ccmp instructions, ARMv8 ISA 5.5.7.
315  enum { N = 8, Z = 4, C = 2, V = 1 };
316  switch (Code) {
317  default: llvm_unreachable("Unknown condition code");
318  case EQ: return Z; // Z == 1
319  case NE: return 0; // Z == 0
320  case HS: return C; // C == 1
321  case LO: return 0; // C == 0
322  case MI: return N; // N == 1
323  case PL: return 0; // N == 0
324  case VS: return V; // V == 1
325  case VC: return 0; // V == 0
326  case HI: return C; // C == 1 && Z == 0
327  case LS: return 0; // C == 0 || Z == 1
328  case GE: return 0; // N == V
329  case LT: return N; // N != V
330  case GT: return 0; // Z == 0 && N == V
331  case LE: return Z; // Z == 1 || N != V
332  }
333 }
334 } // end namespace AArch64CC
335 
336 struct SysAlias {
337  const char *Name;
340 
341  constexpr SysAlias(const char *N, uint16_t E) : Name(N), Encoding(E) {}
342  constexpr SysAlias(const char *N, uint16_t E, FeatureBitset F)
343  : Name(N), Encoding(E), FeaturesRequired(F) {}
344 
345  bool haveFeatures(FeatureBitset ActiveFeatures) const {
346  return (FeaturesRequired & ActiveFeatures) == FeaturesRequired;
347  }
348 
350 };
351 
353  bool NeedsReg;
354  constexpr SysAliasReg(const char *N, uint16_t E, bool R)
355  : SysAlias(N, E), NeedsReg(R) {}
356  constexpr SysAliasReg(const char *N, uint16_t E, bool R, FeatureBitset F)
357  : SysAlias(N, E, F), NeedsReg(R) {}
358 };
359 
362  constexpr SysAliasImm(const char *N, uint16_t E, uint16_t I)
363  : SysAlias(N, E), ImmValue(I) {}
364  constexpr SysAliasImm(const char *N, uint16_t E, uint16_t I, FeatureBitset F)
365  : SysAlias(N, E, F), ImmValue(I) {}
366 };
367 
368 namespace AArch64SVCR {
369  struct SVCR : SysAlias{
370  using SysAlias::SysAlias;
371  };
372  #define GET_SVCR_DECL
373  #include "AArch64GenSystemOperands.inc"
374 }
375 
376 namespace AArch64AT{
377  struct AT : SysAlias {
378  using SysAlias::SysAlias;
379  };
380  #define GET_AT_DECL
381  #include "AArch64GenSystemOperands.inc"
382 }
383 
384 namespace AArch64DB {
385  struct DB : SysAlias {
386  using SysAlias::SysAlias;
387  };
388  #define GET_DB_DECL
389  #include "AArch64GenSystemOperands.inc"
390 }
391 
392 namespace AArch64DBnXS {
393  struct DBnXS : SysAliasImm {
395  };
396  #define GET_DBNXS_DECL
397  #include "AArch64GenSystemOperands.inc"
398 }
399 
400 namespace AArch64DC {
401  struct DC : SysAlias {
402  using SysAlias::SysAlias;
403  };
404  #define GET_DC_DECL
405  #include "AArch64GenSystemOperands.inc"
406 }
407 
408 namespace AArch64IC {
409  struct IC : SysAliasReg {
411  };
412  #define GET_IC_DECL
413  #include "AArch64GenSystemOperands.inc"
414 }
415 
416 namespace AArch64ISB {
417  struct ISB : SysAlias {
418  using SysAlias::SysAlias;
419  };
420  #define GET_ISB_DECL
421  #include "AArch64GenSystemOperands.inc"
422 }
423 
424 namespace AArch64TSB {
425  struct TSB : SysAlias {
426  using SysAlias::SysAlias;
427  };
428  #define GET_TSB_DECL
429  #include "AArch64GenSystemOperands.inc"
430 }
431 
432 namespace AArch64PRFM {
433  struct PRFM : SysAlias {
434  using SysAlias::SysAlias;
435  };
436  #define GET_PRFM_DECL
437  #include "AArch64GenSystemOperands.inc"
438 }
439 
440 namespace AArch64SVEPRFM {
441  struct SVEPRFM : SysAlias {
442  using SysAlias::SysAlias;
443  };
444 #define GET_SVEPRFM_DECL
445 #include "AArch64GenSystemOperands.inc"
446 }
447 
448 namespace AArch64SVEPredPattern {
449  struct SVEPREDPAT {
450  const char *Name;
452  };
453 #define GET_SVEPREDPAT_DECL
454 #include "AArch64GenSystemOperands.inc"
455 }
456 
457 /// Return the number of active elements for VL1 to VL256 predicate pattern,
458 /// zero for all other patterns.
459 inline unsigned getNumElementsFromSVEPredPattern(unsigned Pattern) {
460  switch (Pattern) {
461  default:
462  return 0;
463  case AArch64SVEPredPattern::vl1:
464  case AArch64SVEPredPattern::vl2:
465  case AArch64SVEPredPattern::vl3:
466  case AArch64SVEPredPattern::vl4:
467  case AArch64SVEPredPattern::vl5:
468  case AArch64SVEPredPattern::vl6:
469  case AArch64SVEPredPattern::vl7:
470  case AArch64SVEPredPattern::vl8:
471  return Pattern;
472  case AArch64SVEPredPattern::vl16:
473  return 16;
474  case AArch64SVEPredPattern::vl32:
475  return 32;
476  case AArch64SVEPredPattern::vl64:
477  return 64;
478  case AArch64SVEPredPattern::vl128:
479  return 128;
480  case AArch64SVEPredPattern::vl256:
481  return 256;
482  }
483 }
484 
485 /// Return specific VL predicate pattern based on the number of elements.
486 inline unsigned getSVEPredPatternFromNumElements(unsigned MinNumElts) {
487  switch (MinNumElts) {
488  default:
489  llvm_unreachable("unexpected element count for SVE predicate");
490  case 1:
491  return AArch64SVEPredPattern::vl1;
492  case 2:
493  return AArch64SVEPredPattern::vl2;
494  case 4:
495  return AArch64SVEPredPattern::vl4;
496  case 8:
497  return AArch64SVEPredPattern::vl8;
498  case 16:
499  return AArch64SVEPredPattern::vl16;
500  case 32:
501  return AArch64SVEPredPattern::vl32;
502  case 64:
503  return AArch64SVEPredPattern::vl64;
504  case 128:
505  return AArch64SVEPredPattern::vl128;
506  case 256:
507  return AArch64SVEPredPattern::vl256;
508  }
509 }
510 
511 namespace AArch64ExactFPImm {
512  struct ExactFPImm {
513  const char *Name;
514  int Enum;
515  const char *Repr;
516  };
517 #define GET_EXACTFPIMM_DECL
518 #include "AArch64GenSystemOperands.inc"
519 }
520 
521 namespace AArch64PState {
522  struct PState : SysAlias{
523  using SysAlias::SysAlias;
524  };
525  #define GET_PSTATE_DECL
526  #include "AArch64GenSystemOperands.inc"
527 }
528 
529 namespace AArch64PSBHint {
530  struct PSB : SysAlias {
531  using SysAlias::SysAlias;
532  };
533  #define GET_PSB_DECL
534  #include "AArch64GenSystemOperands.inc"
535 }
536 
537 namespace AArch64BTIHint {
538  struct BTI : SysAlias {
539  using SysAlias::SysAlias;
540  };
541  #define GET_BTI_DECL
542  #include "AArch64GenSystemOperands.inc"
543 }
544 
545 namespace AArch64SE {
547  Invalid = -1,
553 
558 
563  };
564 }
565 
566 namespace AArch64Layout {
568  Invalid = -1,
573 
578 
579  // Bare layout for the 128-bit vector
580  // (only show ".b", ".h", ".s", ".d" without vector number)
585  };
586 }
587 
588 inline static const char *
590  switch (Layout) {
591  case AArch64Layout::VL_8B: return ".8b";
592  case AArch64Layout::VL_4H: return ".4h";
593  case AArch64Layout::VL_2S: return ".2s";
594  case AArch64Layout::VL_1D: return ".1d";
595  case AArch64Layout::VL_16B: return ".16b";
596  case AArch64Layout::VL_8H: return ".8h";
597  case AArch64Layout::VL_4S: return ".4s";
598  case AArch64Layout::VL_2D: return ".2d";
599  case AArch64Layout::VL_B: return ".b";
600  case AArch64Layout::VL_H: return ".h";
601  case AArch64Layout::VL_S: return ".s";
602  case AArch64Layout::VL_D: return ".d";
603  default: llvm_unreachable("Unknown Vector Layout");
604  }
605 }
606 
607 inline static AArch64Layout::VectorLayout
610  .Case(".8b", AArch64Layout::VL_8B)
611  .Case(".4h", AArch64Layout::VL_4H)
612  .Case(".2s", AArch64Layout::VL_2S)
613  .Case(".1d", AArch64Layout::VL_1D)
614  .Case(".16b", AArch64Layout::VL_16B)
615  .Case(".8h", AArch64Layout::VL_8H)
616  .Case(".4s", AArch64Layout::VL_4S)
617  .Case(".2d", AArch64Layout::VL_2D)
618  .Case(".b", AArch64Layout::VL_B)
619  .Case(".h", AArch64Layout::VL_H)
620  .Case(".s", AArch64Layout::VL_S)
621  .Case(".d", AArch64Layout::VL_D)
623 }
624 
625 namespace AArch64SysReg {
626  struct SysReg {
627  const char *Name;
628  unsigned Encoding;
629  bool Readable;
630  bool Writeable;
632 
633  bool haveFeatures(FeatureBitset ActiveFeatures) const {
634  return (FeaturesRequired & ActiveFeatures) == FeaturesRequired;
635  }
636  };
637 
638  #define GET_SYSREG_DECL
639  #include "AArch64GenSystemOperands.inc"
640 
641  const SysReg *lookupSysRegByName(StringRef);
642  const SysReg *lookupSysRegByEncoding(uint16_t);
643 
645  std::string genericRegisterString(uint32_t Bits);
646 }
647 
648 namespace AArch64TLBI {
649  struct TLBI : SysAliasReg {
651  };
652  #define GET_TLBITable_DECL
653  #include "AArch64GenSystemOperands.inc"
654 }
655 
656 namespace AArch64PRCTX {
657  struct PRCTX : SysAliasReg {
659  };
660  #define GET_PRCTX_DECL
661  #include "AArch64GenSystemOperands.inc"
662 }
663 
664 namespace AArch64II {
665  /// Target Operand Flag enum.
666  enum TOF {
667  //===------------------------------------------------------------------===//
668  // AArch64 Specific MachineOperand flags.
669 
671 
672  MO_FRAGMENT = 0x7,
673 
674  /// MO_PAGE - A symbol operand with this flag represents the pc-relative
675  /// offset of the 4K page containing the symbol. This is used with the
676  /// ADRP instruction.
677  MO_PAGE = 1,
678 
679  /// MO_PAGEOFF - A symbol operand with this flag represents the offset of
680  /// that symbol within a 4K page. This offset is added to the page address
681  /// to produce the complete address.
683 
684  /// MO_G3 - A symbol operand with this flag (granule 3) represents the high
685  /// 16-bits of a 64-bit address, used in a MOVZ or MOVK instruction
686  MO_G3 = 3,
687 
688  /// MO_G2 - A symbol operand with this flag (granule 2) represents the bits
689  /// 32-47 of a 64-bit address, used in a MOVZ or MOVK instruction
690  MO_G2 = 4,
691 
692  /// MO_G1 - A symbol operand with this flag (granule 1) represents the bits
693  /// 16-31 of a 64-bit address, used in a MOVZ or MOVK instruction
694  MO_G1 = 5,
695 
696  /// MO_G0 - A symbol operand with this flag (granule 0) represents the bits
697  /// 0-15 of a 64-bit address, used in a MOVZ or MOVK instruction
698  MO_G0 = 6,
699 
700  /// MO_HI12 - This flag indicates that a symbol operand represents the bits
701  /// 13-24 of a 64-bit address, used in a arithmetic immediate-shifted-left-
702  /// by-12-bits instruction.
703  MO_HI12 = 7,
704 
705  /// MO_COFFSTUB - On a symbol operand "FOO", this indicates that the
706  /// reference is actually to the ".refptr.FOO" symbol. This is used for
707  /// stub symbols on windows.
708  MO_COFFSTUB = 0x8,
709 
710  /// MO_GOT - This flag indicates that a symbol operand represents the
711  /// address of the GOT entry for the symbol, rather than the address of
712  /// the symbol itself.
713  MO_GOT = 0x10,
714 
715  /// MO_NC - Indicates whether the linker is expected to check the symbol
716  /// reference for overflow. For example in an ADRP/ADD pair of relocations
717  /// the ADRP usually does check, but not the ADD.
718  MO_NC = 0x20,
719 
720  /// MO_TLS - Indicates that the operand being accessed is some kind of
721  /// thread-local symbol. On Darwin, only one type of thread-local access
722  /// exists (pre linker-relaxation), but on ELF the TLSModel used for the
723  /// referee will affect interpretation.
724  MO_TLS = 0x40,
725 
726  /// MO_DLLIMPORT - On a symbol operand, this represents that the reference
727  /// to the symbol is for an import stub. This is used for DLL import
728  /// storage class indication on Windows.
729  MO_DLLIMPORT = 0x80,
730 
731  /// MO_S - Indicates that the bits of the symbol operand represented by
732  /// MO_G0 etc are signed.
733  MO_S = 0x100,
734 
735  /// MO_PREL - Indicates that the bits of the symbol operand represented by
736  /// MO_G0 etc are PC relative.
737  MO_PREL = 0x200,
738 
739  /// MO_TAGGED - With MO_PAGE, indicates that the page includes a memory tag
740  /// in bits 56-63.
741  /// On a FrameIndex operand, indicates that the underlying memory is tagged
742  /// with an unknown tag value (MTE); this needs to be lowered either to an
743  /// SP-relative load or store instruction (which do not check tags), or to
744  /// an LDG instruction to obtain the tag value.
745  MO_TAGGED = 0x400,
746  };
747 } // end namespace AArch64II
748 
749 namespace AArch64 {
750 // The number of bits in a SVE register is architecturally defined
751 // to be a multiple of this value. If <M x t> has this number of bits,
752 // a <n x M x t> vector can be stored in a SVE register without any
753 // redundant bits. If <M x t> has this number of bits divided by P,
754 // a <n x M x t> vector is stored in a SVE register by placing index i
755 // in index i*P of a <n x (M*P) x t> vector. The other elements of the
756 // <n x (M*P) x t> vector (such as index 1) are undefined.
757 static constexpr unsigned SVEBitsPerBlock = 128;
758 static constexpr unsigned SVEMaxBitsPerVector = 2048;
759 const unsigned NeonBitsPerVector = 128;
760 } // end namespace AArch64
761 } // end namespace llvm
762 
763 #endif
llvm::StringSwitch::Case
StringSwitch & Case(StringLiteral S, T Value)
Definition: StringSwitch.h:67
llvm::SysAliasImm
Definition: AArch64BaseInfo.h:360
llvm::AArch64II::MO_G3
@ MO_G3
MO_G3 - A symbol operand with this flag (granule 3) represents the high 16-bits of a 64-bit address,...
Definition: AArch64BaseInfo.h:686
llvm::AArch64SE::UXTW
@ UXTW
Definition: AArch64BaseInfo.h:556
llvm::AArch64Layout::VL_2S
@ VL_2S
Definition: AArch64BaseInfo.h:571
llvm::AArch64CC::Invalid
@ Invalid
Definition: AArch64BaseInfo.h:272
llvm::AArch64CC::LO
@ LO
Definition: AArch64BaseInfo.h:258
llvm::AArch64CC::HI
@ HI
Definition: AArch64BaseInfo.h:263
llvm
This file implements support for optimizing divisions by a constant.
Definition: AllocatorList.h:23
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::AArch64CC::AL
@ AL
Definition: AArch64BaseInfo.h:269
llvm::AArch64CC::NE
@ NE
Definition: AArch64BaseInfo.h:256
llvm::AArch64II::MO_HI12
@ MO_HI12
MO_HI12 - This flag indicates that a symbol operand represents the bits 13-24 of a 64-bit address,...
Definition: AArch64BaseInfo.h:703
llvm::AArch64CC::getNZCVToSatisfyCondCode
static unsigned getNZCVToSatisfyCondCode(CondCode Code)
Given a condition code, return NZCV flags that would satisfy that condition.
Definition: AArch64BaseInfo.h:313
llvm::AArch64II::MO_G1
@ MO_G1
MO_G1 - A symbol operand with this flag (granule 1) represents the bits 16-31 of a 64-bit address,...
Definition: AArch64BaseInfo.h:694
llvm::AArch64CC::MI
@ MI
Definition: AArch64BaseInfo.h:259
llvm::AArch64SysReg::SysReg::FeaturesRequired
FeatureBitset FeaturesRequired
Definition: AArch64BaseInfo.h:631
llvm::StringSwitch::Default
LLVM_NODISCARD R Default(T Value)
Definition: StringSwitch.h:181
llvm::AArch64CC::NONE_ACTIVE
@ NONE_ACTIVE
Definition: AArch64BaseInfo.h:278
llvm::AArch64SysReg::lookupSysRegByName
const SysReg * lookupSysRegByName(StringRef)
llvm::SysAlias
Definition: AArch64BaseInfo.h:336
llvm::AArch64TLBI::TLBI
Definition: AArch64BaseInfo.h:649
llvm::SysAlias::SysAlias
constexpr SysAlias(const char *N, uint16_t E)
Definition: AArch64BaseInfo.h:341
llvm::AArch64CC::FIRST_ACTIVE
@ FIRST_ACTIVE
Definition: AArch64BaseInfo.h:276
ErrorHandling.h
llvm::SysAliasReg::SysAliasReg
constexpr SysAliasReg(const char *N, uint16_t E, bool R)
Definition: AArch64BaseInfo.h:354
llvm::AArch64SysReg::SysReg::Name
const char * Name
Definition: AArch64BaseInfo.h:627
llvm::AArch64Layout::Invalid
@ Invalid
Definition: AArch64BaseInfo.h:568
llvm::AArch64ExactFPImm::ExactFPImm::Repr
const char * Repr
Definition: AArch64BaseInfo.h:515
llvm::AArch64II::MO_PREL
@ MO_PREL
MO_PREL - Indicates that the bits of the symbol operand represented by MO_G0 etc are PC relative.
Definition: AArch64BaseInfo.h:737
llvm::AArch64CC::ANY_ACTIVE
@ ANY_ACTIVE
Definition: AArch64BaseInfo.h:275
llvm::SysAliasReg
Definition: AArch64BaseInfo.h:352
llvm::AArch64Layout::VL_B
@ VL_B
Definition: AArch64BaseInfo.h:581
llvm::tgtok::Bits
@ Bits
Definition: TGLexer.h:50
llvm::AArch64PRCTX::PRCTX
Definition: AArch64BaseInfo.h:657
llvm::SysAliasImm::SysAliasImm
constexpr SysAliasImm(const char *N, uint16_t E, uint16_t I)
Definition: AArch64BaseInfo.h:362
llvm::FeatureBitset
Container class for subtarget features.
Definition: SubtargetFeature.h:40
llvm::AArch64SysReg::SysReg
Definition: AArch64BaseInfo.h:626
STLExtras.h
llvm::AArch64Layout::VL_16B
@ VL_16B
Definition: AArch64BaseInfo.h:574
llvm::SysAlias::getRequiredFeatures
FeatureBitset getRequiredFeatures() const
Definition: AArch64BaseInfo.h:349
llvm::AArch64SE::UXTH
@ UXTH
Definition: AArch64BaseInfo.h:555
llvm::AArch64ISB::ISB
Definition: AArch64BaseInfo.h:417
llvm::AArch64SE::UXTX
@ UXTX
Definition: AArch64BaseInfo.h:557
F
#define F(x, y, z)
Definition: MD5.cpp:56
llvm::AArch64II::MO_TLS
@ MO_TLS
MO_TLS - Indicates that the operand being accessed is some kind of thread-local symbol.
Definition: AArch64BaseInfo.h:724
llvm::AArch64CC::LT
@ LT
Definition: AArch64BaseInfo.h:266
llvm::AArch64SE::SXTB
@ SXTB
Definition: AArch64BaseInfo.h:559
llvm::AArch64SysReg::SysReg::Writeable
bool Writeable
Definition: AArch64BaseInfo.h:630
llvm::AArch64SVEPredPattern::SVEPREDPAT
Definition: AArch64BaseInfo.h:449
llvm::AArch64SVEPredPattern::SVEPREDPAT::Encoding
uint16_t Encoding
Definition: AArch64BaseInfo.h:451
llvm::AArch64II::MO_G0
@ MO_G0
MO_G0 - A symbol operand with this flag (granule 0) represents the bits 0-15 of a 64-bit address,...
Definition: AArch64BaseInfo.h:698
SubtargetFeature.h
llvm::AArch64Layout::VectorLayout
VectorLayout
Definition: AArch64BaseInfo.h:567
llvm::AArch64CC::VC
@ VC
Definition: AArch64BaseInfo.h:262
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::AArch64Layout::VL_S
@ VL_S
Definition: AArch64BaseInfo.h:583
llvm::AArch64Layout::VL_8B
@ VL_8B
Definition: AArch64BaseInfo.h:569
llvm::AArch64Layout::VL_4S
@ VL_4S
Definition: AArch64BaseInfo.h:576
llvm::AArch64CC::HS
@ HS
Definition: AArch64BaseInfo.h:257
llvm::AArch64IC::IC
Definition: AArch64BaseInfo.h:409
llvm::AArch64DC::DC
Definition: AArch64BaseInfo.h:401
llvm::AArch64Layout::VL_8H
@ VL_8H
Definition: AArch64BaseInfo.h:575
llvm::AArch64CC::LE
@ LE
Definition: AArch64BaseInfo.h:268
llvm::AArch64ExactFPImm::ExactFPImm
Definition: AArch64BaseInfo.h:512
llvm::AArch64CC::PL
@ PL
Definition: AArch64BaseInfo.h:260
llvm::AArch64CC::getCondCodeName
static const char * getCondCodeName(CondCode Code)
Definition: AArch64BaseInfo.h:281
llvm::SysAliasImm::SysAliasImm
constexpr SysAliasImm(const char *N, uint16_t E, uint16_t I, FeatureBitset F)
Definition: AArch64BaseInfo.h:364
llvm::AArch64Layout::VL_1D
@ VL_1D
Definition: AArch64BaseInfo.h:572
llvm::AArch64BTIHint::BTI
Definition: AArch64BaseInfo.h:538
llvm::AArch64Layout::VL_H
@ VL_H
Definition: AArch64BaseInfo.h:582
llvm::AArch64II::MO_S
@ MO_S
MO_S - Indicates that the bits of the symbol operand represented by MO_G0 etc are signed.
Definition: AArch64BaseInfo.h:733
llvm::getSVEPredPatternFromNumElements
unsigned getSVEPredPatternFromNumElements(unsigned MinNumElts)
Return specific VL predicate pattern based on the number of elements.
Definition: AArch64BaseInfo.h:486
llvm::AArch64AT::AT
Definition: AArch64BaseInfo.h:377
llvm::AArch64II::MO_DLLIMPORT
@ MO_DLLIMPORT
MO_DLLIMPORT - On a symbol operand, this represents that the reference to the symbol is for an import...
Definition: AArch64BaseInfo.h:729
llvm::AArch64Layout::VL_2D
@ VL_2D
Definition: AArch64BaseInfo.h:577
llvm::AArch64::SVEBitsPerBlock
static constexpr unsigned SVEBitsPerBlock
Definition: AArch64BaseInfo.h:757
llvm::AArch64PState::PState
Definition: AArch64BaseInfo.h:522
llvm::AArch64PSBHint::PSB
Definition: AArch64BaseInfo.h:530
llvm::AArch64II::MO_NC
@ MO_NC
MO_NC - Indicates whether the linker is expected to check the symbol reference for overflow.
Definition: AArch64BaseInfo.h:718
llvm::AArch64II::MO_PAGEOFF
@ MO_PAGEOFF
MO_PAGEOFF - A symbol operand with this flag represents the offset of that symbol within a 4K page.
Definition: AArch64BaseInfo.h:682
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::SysAlias::Name
const char * Name
Definition: AArch64BaseInfo.h:337
llvm::AArch64II::MO_NO_FLAG
@ MO_NO_FLAG
Definition: AArch64BaseInfo.h:670
llvm::AArch64Layout::VL_D
@ VL_D
Definition: AArch64BaseInfo.h:584
llvm::SysAliasImm::ImmValue
uint16_t ImmValue
Definition: AArch64BaseInfo.h:361
llvm::AArch64SysReg::parseGenericRegister
uint32_t parseGenericRegister(StringRef Name)
Definition: AArch64BaseInfo.cpp:133
llvm::AArch64SE::LSL
@ LSL
Definition: AArch64BaseInfo.h:548
llvm::AArch64SysReg::SysReg::Encoding
unsigned Encoding
Definition: AArch64BaseInfo.h:628
llvm::AArch64SE::UXTB
@ UXTB
Definition: AArch64BaseInfo.h:554
llvm::AArch64CC::LAST_ACTIVE
@ LAST_ACTIVE
Definition: AArch64BaseInfo.h:277
llvm::AArch64VectorLayoutToString
static const char * AArch64VectorLayoutToString(AArch64Layout::VectorLayout Layout)
Definition: AArch64BaseInfo.h:589
llvm::AArch64PRFM::PRFM
Definition: AArch64BaseInfo.h:433
llvm::getBRegFromDReg
static unsigned getBRegFromDReg(unsigned Reg)
Definition: AArch64BaseInfo.h:128
llvm::AArch64II::TOF
TOF
Target Operand Flag enum.
Definition: AArch64BaseInfo.h:666
llvm::AArch64SVCR::SVCR
Definition: AArch64BaseInfo.h:369
llvm::AArch64II::MO_FRAGMENT
@ MO_FRAGMENT
Definition: AArch64BaseInfo.h:672
llvm::AArch64SE::ROR
@ ROR
Definition: AArch64BaseInfo.h:552
llvm::AArch64CC::GE
@ GE
Definition: AArch64BaseInfo.h:265
llvm::atomicBarrierDroppedOnZero
static bool atomicBarrierDroppedOnZero(unsigned Opcode)
Definition: AArch64BaseInfo.h:207
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::AArch64SE::ShiftExtSpecifiers
ShiftExtSpecifiers
Definition: AArch64BaseInfo.h:546
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:134
uint32_t
llvm::AArch64SysReg::SysReg::Readable
bool Readable
Definition: AArch64BaseInfo.h:629
llvm::AArch64SE::SXTH
@ SXTH
Definition: AArch64BaseInfo.h:560
llvm::AArch64CC::EQ
@ EQ
Definition: AArch64BaseInfo.h:255
llvm::AArch64ExactFPImm::ExactFPImm::Enum
int Enum
Definition: AArch64BaseInfo.h:514
llvm::getXRegFromXRegTuple
static unsigned getXRegFromXRegTuple(unsigned RegTuple)
Definition: AArch64BaseInfo.h:109
llvm::getXRegFromWReg
static unsigned getXRegFromWReg(unsigned Reg)
Definition: AArch64BaseInfo.h:69
llvm::AArch64DBnXS::DBnXS
Definition: AArch64BaseInfo.h:393
llvm::AArch64SVEPRFM::SVEPRFM
Definition: AArch64BaseInfo.h:441
llvm::AArch64SysReg::lookupSysRegByEncoding
const SysReg * lookupSysRegByEncoding(uint16_t)
llvm::GraphProgram::Name
Name
Definition: GraphWriter.h:52
llvm::AArch64CC::VS
@ VS
Definition: AArch64BaseInfo.h:261
uint16_t
llvm::SysAliasReg::NeedsReg
bool NeedsReg
Definition: AArch64BaseInfo.h:353
llvm::AArch64TSB::TSB
Definition: AArch64BaseInfo.h:425
llvm::AArch64SysReg::genericRegisterString
std::string genericRegisterString(uint32_t Bits)
Definition: AArch64BaseInfo.cpp:154
llvm::AArch64SE::SXTX
@ SXTX
Definition: AArch64BaseInfo.h:562
llvm::AArch64SE::ASR
@ ASR
Definition: AArch64BaseInfo.h:551
llvm::AArch64CC::LS
@ LS
Definition: AArch64BaseInfo.h:264
llvm::AArch64StringToVectorLayout
static AArch64Layout::VectorLayout AArch64StringToVectorLayout(StringRef LayoutStr)
Definition: AArch64BaseInfo.h:608
llvm::SysAlias::SysAlias
constexpr SysAlias(const char *N, uint16_t E, FeatureBitset F)
Definition: AArch64BaseInfo.h:342
AArch64MCTargetDesc.h
StringSwitch.h
llvm::AArch64CC::getInvertedCondCode
static CondCode getInvertedCondCode(CondCode Code)
Definition: AArch64BaseInfo.h:303
llvm::AArch64SE::MSL
@ MSL
Definition: AArch64BaseInfo.h:549
llvm::AArch64::NeonBitsPerVector
const unsigned NeonBitsPerVector
Definition: AArch64BaseInfo.h:759
llvm::AArch64CC::GT
@ GT
Definition: AArch64BaseInfo.h:267
llvm::SysAliasReg::SysAliasReg
constexpr SysAliasReg(const char *N, uint16_t E, bool R, FeatureBitset F)
Definition: AArch64BaseInfo.h:356
llvm::AArch64DB::DB
Definition: AArch64BaseInfo.h:385
llvm::AArch64CC::NV
@ NV
Definition: AArch64BaseInfo.h:270
llvm::getNumElementsFromSVEPredPattern
unsigned getNumElementsFromSVEPredPattern(unsigned Pattern)
Return the number of active elements for VL1 to VL256 predicate pattern, zero for all other patterns.
Definition: AArch64BaseInfo.h:459
llvm::getWRegFromXReg
static unsigned getWRegFromXReg(unsigned Reg)
Definition: AArch64BaseInfo.h:29
llvm::Pattern
Definition: FileCheckImpl.h:614
llvm::AArch64Layout::VL_4H
@ VL_4H
Definition: AArch64BaseInfo.h:570
N
#define N
llvm::AArch64SE::LSR
@ LSR
Definition: AArch64BaseInfo.h:550
llvm::SysAlias::Encoding
uint16_t Encoding
Definition: AArch64BaseInfo.h:338
llvm::SysAlias::haveFeatures
bool haveFeatures(FeatureBitset ActiveFeatures) const
Definition: AArch64BaseInfo.h:345
llvm::AArch64SE::SXTW
@ SXTW
Definition: AArch64BaseInfo.h:561
llvm::getDRegFromBReg
static unsigned getDRegFromBReg(unsigned Reg)
Definition: AArch64BaseInfo.h:168
llvm::SysAlias::FeaturesRequired
FeatureBitset FeaturesRequired
Definition: AArch64BaseInfo.h:339
llvm::AArch64CC::CondCode
CondCode
Definition: AArch64BaseInfo.h:254
llvm::StringSwitch
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:42
llvm::AArch64II::MO_G2
@ MO_G2
MO_G2 - A symbol operand with this flag (granule 2) represents the bits 32-47 of a 64-bit address,...
Definition: AArch64BaseInfo.h:690
llvm::AArch64II::MO_COFFSTUB
@ MO_COFFSTUB
MO_COFFSTUB - On a symbol operand "FOO", this indicates that the reference is actually to the "....
Definition: AArch64BaseInfo.h:708
llvm::AArch64::SVEMaxBitsPerVector
static constexpr unsigned SVEMaxBitsPerVector
Definition: AArch64BaseInfo.h:758
llvm::AArch64II::MO_TAGGED
@ MO_TAGGED
MO_TAGGED - With MO_PAGE, indicates that the page includes a memory tag in bits 56-63.
Definition: AArch64BaseInfo.h:745
llvm::AArch64SE::Invalid
@ Invalid
Definition: AArch64BaseInfo.h:547
llvm::AArch64SVEPredPattern::SVEPREDPAT::Name
const char * Name
Definition: AArch64BaseInfo.h:450
llvm::AArch64II::MO_GOT
@ MO_GOT
MO_GOT - This flag indicates that a symbol operand represents the address of the GOT entry for the sy...
Definition: AArch64BaseInfo.h:713
llvm::AArch64ExactFPImm::ExactFPImm::Name
const char * Name
Definition: AArch64BaseInfo.h:513
llvm::AArch64II::MO_PAGE
@ MO_PAGE
MO_PAGE - A symbol operand with this flag represents the pc-relative offset of the 4K page containing...
Definition: AArch64BaseInfo.h:677
llvm::AArch64SysReg::SysReg::haveFeatures
bool haveFeatures(FeatureBitset ActiveFeatures) const
Definition: AArch64BaseInfo.h:633