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LLVM 18.0.0git
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#include "AArch64.h"#include "AArch64RegisterInfo.h"#include "llvm/CodeGen/TargetInstrInfo.h"#include "llvm/Support/TypeSize.h"#include <optional>#include "AArch64GenInstrInfo.inc"Go to the source code of this file.
Classes | |
| class | llvm::AArch64InstrInfo |
| struct | llvm::UsedNZCV |
Namespaces | |
| namespace | llvm |
| This is an optimization pass for GlobalISel generic memory operations. | |
| namespace | llvm::AArch64 |
Macros | |
| #define | GET_INSTRINFO_HEADER |
| #define | FALKOR_STRIDED_ACCESS_MD "falkor.strided.access" |
| #define | GET_INSTRINFO_HELPER_DECLS |
| #define | TSFLAG_ELEMENT_SIZE_TYPE(X) (X) |
| #define | TSFLAG_DESTRUCTIVE_INST_TYPE(X) ((X) << 3) |
| #define | TSFLAG_FALSE_LANE_TYPE(X) ((X) << 7) |
| #define | TSFLAG_INSTR_FLAGS(X) ((X) << 9) |
| #define | TSFLAG_SME_MATRIX_TYPE(X) ((X) << 11) |
Enumerations | |
| enum | llvm::AArch64FrameOffsetStatus { llvm::AArch64FrameOffsetCannotUpdate = 0x0 , llvm::AArch64FrameOffsetIsLegal = 0x1 , llvm::AArch64FrameOffsetCanUpdate = 0x2 } |
| Use to report the frame offset status in isAArch64FrameOffsetLegal. More... | |
| enum | llvm::AArch64::ElementSizeType { llvm::AArch64::ElementSizeMask = TSFLAG_ELEMENT_SIZE_TYPE(0x7) , llvm::AArch64::ElementSizeNone = TSFLAG_ELEMENT_SIZE_TYPE(0x0) , llvm::AArch64::ElementSizeB = TSFLAG_ELEMENT_SIZE_TYPE(0x1) , llvm::AArch64::ElementSizeH = TSFLAG_ELEMENT_SIZE_TYPE(0x2) , llvm::AArch64::ElementSizeS = TSFLAG_ELEMENT_SIZE_TYPE(0x3) , llvm::AArch64::ElementSizeD = TSFLAG_ELEMENT_SIZE_TYPE(0x4) } |
| enum | llvm::AArch64::DestructiveInstType { llvm::AArch64::DestructiveInstTypeMask = TSFLAG_DESTRUCTIVE_INST_TYPE(0xf) , llvm::AArch64::NotDestructive = TSFLAG_DESTRUCTIVE_INST_TYPE(0x0) , llvm::AArch64::DestructiveOther = TSFLAG_DESTRUCTIVE_INST_TYPE(0x1) , llvm::AArch64::DestructiveUnary = TSFLAG_DESTRUCTIVE_INST_TYPE(0x2) , llvm::AArch64::DestructiveBinaryImm = TSFLAG_DESTRUCTIVE_INST_TYPE(0x3) , llvm::AArch64::DestructiveBinaryShImmUnpred = TSFLAG_DESTRUCTIVE_INST_TYPE(0x4) , llvm::AArch64::DestructiveBinary = TSFLAG_DESTRUCTIVE_INST_TYPE(0x5) , llvm::AArch64::DestructiveBinaryComm = TSFLAG_DESTRUCTIVE_INST_TYPE(0x6) , llvm::AArch64::DestructiveBinaryCommWithRev = TSFLAG_DESTRUCTIVE_INST_TYPE(0x7) , llvm::AArch64::DestructiveTernaryCommWithRev = TSFLAG_DESTRUCTIVE_INST_TYPE(0x8) , llvm::AArch64::DestructiveUnaryPassthru = TSFLAG_DESTRUCTIVE_INST_TYPE(0x9) } |
| enum | llvm::AArch64::FalseLaneType { llvm::AArch64::FalseLanesMask = TSFLAG_FALSE_LANE_TYPE(0x3) , llvm::AArch64::FalseLanesZero = TSFLAG_FALSE_LANE_TYPE(0x1) , llvm::AArch64::FalseLanesUndef = TSFLAG_FALSE_LANE_TYPE(0x2) } |
| enum | llvm::AArch64::SMEMatrixType { llvm::AArch64::SMEMatrixTypeMask = TSFLAG_SME_MATRIX_TYPE(0x7) , llvm::AArch64::SMEMatrixNone = TSFLAG_SME_MATRIX_TYPE(0x0) , llvm::AArch64::SMEMatrixTileB = TSFLAG_SME_MATRIX_TYPE(0x1) , llvm::AArch64::SMEMatrixTileH = TSFLAG_SME_MATRIX_TYPE(0x2) , llvm::AArch64::SMEMatrixTileS = TSFLAG_SME_MATRIX_TYPE(0x3) , llvm::AArch64::SMEMatrixTileD = TSFLAG_SME_MATRIX_TYPE(0x4) , llvm::AArch64::SMEMatrixTileQ = TSFLAG_SME_MATRIX_TYPE(0x5) , llvm::AArch64::SMEMatrixArray = TSFLAG_SME_MATRIX_TYPE(0x6) } |
Functions | |
| std::optional< UsedNZCV > | llvm::examineCFlagsUse (MachineInstr &MI, MachineInstr &CmpInstr, const TargetRegisterInfo &TRI, SmallVectorImpl< MachineInstr * > *CCUseInstrs=nullptr) |
| bool | llvm::isNZCVTouchedInInstructionRange (const MachineInstr &DefMI, const MachineInstr &UseMI, const TargetRegisterInfo *TRI) |
Return true if there is an instruction /after/ DefMI and before UseMI which either reads or clobbers NZCV. | |
| MCCFIInstruction | llvm::createDefCFA (const TargetRegisterInfo &TRI, unsigned FrameReg, unsigned Reg, const StackOffset &Offset, bool LastAdjustmentWasScalable=true) |
| MCCFIInstruction | llvm::createCFAOffset (const TargetRegisterInfo &MRI, unsigned Reg, const StackOffset &OffsetFromDefCFA) |
| void | llvm::emitFrameOffset (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, StackOffset Offset, const TargetInstrInfo *TII, MachineInstr::MIFlag=MachineInstr::NoFlags, bool SetNZCV=false, bool NeedsWinCFI=false, bool *HasWinCFI=nullptr, bool EmitCFAOffset=false, StackOffset InitialOffset={}, unsigned FrameReg=AArch64::SP) |
| emitFrameOffset - Emit instructions as needed to set DestReg to SrcReg plus Offset. | |
| bool | llvm::rewriteAArch64FrameIndex (MachineInstr &MI, unsigned FrameRegIdx, unsigned FrameReg, StackOffset &Offset, const AArch64InstrInfo *TII) |
| rewriteAArch64FrameIndex - Rewrite MI to access 'Offset' bytes from the FP. | |
| int | llvm::isAArch64FrameOffsetLegal (const MachineInstr &MI, StackOffset &Offset, bool *OutUseUnscaledOp=nullptr, unsigned *OutUnscaledOp=nullptr, int64_t *EmittableOffset=nullptr) |
Check if the Offset is a valid frame offset for MI. | |
| static bool | llvm::isUncondBranchOpcode (int Opc) |
| static bool | llvm::isCondBranchOpcode (int Opc) |
| static bool | llvm::isIndirectBranchOpcode (int Opc) |
| static bool | llvm::isPTrueOpcode (unsigned Opc) |
| unsigned | llvm::getBLRCallOpcode (const MachineFunction &MF) |
| Return opcode to be used for indirect calls. | |
| static unsigned | llvm::getXPACOpcodeForKey (AArch64PACKey::ID K) |
| Return XPAC opcode to be used for a ptrauth strip using the given key. | |
| static unsigned | llvm::getAUTOpcodeForKey (AArch64PACKey::ID K, bool Zero) |
| Return AUT opcode to be used for a ptrauth auth using the given key, or its AUT*Z variant that doesn't take a discriminator operand, using zero instead. | |
| static unsigned | llvm::getPACOpcodeForKey (AArch64PACKey::ID K, bool Zero) |
| Return PAC opcode to be used for a ptrauth sign using the given key, or its PAC*Z variant that doesn't take a discriminator operand, using zero instead. | |
| int | llvm::AArch64::getSVEPseudoMap (uint16_t Opcode) |
| int | llvm::AArch64::getSVERevInstr (uint16_t Opcode) |
| int | llvm::AArch64::getSVENonRevInstr (uint16_t Opcode) |
| int | llvm::AArch64::getSMEPseudoMap (uint16_t Opcode) |
Variables | |
| static const MachineMemOperand::Flags | llvm::MOSuppressPair |
| static const MachineMemOperand::Flags | llvm::MOStridedAccess |
| static const uint64_t | llvm::AArch64::InstrFlagIsWhile = TSFLAG_INSTR_FLAGS(0x1) |
| static const uint64_t | llvm::AArch64::InstrFlagIsPTestLike = TSFLAG_INSTR_FLAGS(0x2) |
| #define FALKOR_STRIDED_ACCESS_MD "falkor.strided.access" |
Definition at line 34 of file AArch64InstrInfo.h.
| #define GET_INSTRINFO_HEADER |
Definition at line 22 of file AArch64InstrInfo.h.
| #define GET_INSTRINFO_HELPER_DECLS |
Definition at line 385 of file AArch64InstrInfo.h.
Definition at line 590 of file AArch64InstrInfo.h.
Definition at line 589 of file AArch64InstrInfo.h.
Definition at line 591 of file AArch64InstrInfo.h.
Definition at line 592 of file AArch64InstrInfo.h.
Definition at line 593 of file AArch64InstrInfo.h.
1.9.6