LLVM  14.0.0git
AArch64InstrInfo.h
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1 //===- AArch64InstrInfo.h - AArch64 Instruction Information -----*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the AArch64 implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64INSTRINFO_H
14 #define LLVM_LIB_TARGET_AARCH64_AARCH64INSTRINFO_H
15 
16 #include "AArch64.h"
17 #include "AArch64RegisterInfo.h"
18 #include "llvm/ADT/Optional.h"
21 #include "llvm/Support/TypeSize.h"
22 
23 #define GET_INSTRINFO_HEADER
24 #include "AArch64GenInstrInfo.inc"
25 
26 namespace llvm {
27 
28 class AArch64Subtarget;
29 class AArch64TargetMachine;
30 
35 
36 #define FALKOR_STRIDED_ACCESS_MD "falkor.strided.access"
37 
38 class AArch64InstrInfo final : public AArch64GenInstrInfo {
39  const AArch64RegisterInfo RI;
40  const AArch64Subtarget &Subtarget;
41 
42 public:
43  explicit AArch64InstrInfo(const AArch64Subtarget &STI);
44 
45  /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
46  /// such, whenever a client has an instance of instruction info, it should
47  /// always be able to get register info as well (through this method).
48  const AArch64RegisterInfo &getRegisterInfo() const { return RI; }
49 
50  unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
51 
52  bool isAsCheapAsAMove(const MachineInstr &MI) const override;
53 
54  bool isCoalescableExtInstr(const MachineInstr &MI, Register &SrcReg,
55  Register &DstReg, unsigned &SubIdx) const override;
56 
57  bool
59  const MachineInstr &MIb) const override;
60 
61  unsigned isLoadFromStackSlot(const MachineInstr &MI,
62  int &FrameIndex) const override;
63  unsigned isStoreToStackSlot(const MachineInstr &MI,
64  int &FrameIndex) const override;
65 
66  /// Does this instruction set its full destination register to zero?
67  static bool isGPRZero(const MachineInstr &MI);
68 
69  /// Does this instruction rename a GPR without modifying bits?
70  static bool isGPRCopy(const MachineInstr &MI);
71 
72  /// Does this instruction rename an FPR without modifying bits?
73  static bool isFPRCopy(const MachineInstr &MI);
74 
75  /// Return true if pairing the given load or store is hinted to be
76  /// unprofitable.
77  static bool isLdStPairSuppressed(const MachineInstr &MI);
78 
79  /// Return true if the given load or store is a strided memory access.
80  static bool isStridedAccess(const MachineInstr &MI);
81 
82  /// Return true if it has an unscaled load/store offset.
83  static bool hasUnscaledLdStOffset(unsigned Opc);
85  return hasUnscaledLdStOffset(MI.getOpcode());
86  }
87 
88  /// Returns the unscaled load/store for the scaled load/store opcode,
89  /// if there is a corresponding unscaled variant available.
90  static Optional<unsigned> getUnscaledLdSt(unsigned Opc);
91 
92  /// Scaling factor for (scaled or unscaled) load or store.
93  static int getMemScale(unsigned Opc);
94  static int getMemScale(const MachineInstr &MI) {
95  return getMemScale(MI.getOpcode());
96  }
97 
98  /// Returns whether the instruction is a pre-indexed load.
99  static bool isPreLd(const MachineInstr &MI);
100 
101  /// Returns whether the instruction is a pre-indexed store.
102  static bool isPreSt(const MachineInstr &MI);
103 
104  /// Returns whether the instruction is a pre-indexed load/store.
105  static bool isPreLdSt(const MachineInstr &MI);
106 
107  /// Returns the index for the immediate for a given instruction.
108  static unsigned getLoadStoreImmIdx(unsigned Opc);
109 
110  /// Return true if pairing the given load or store may be paired with another.
111  static bool isPairableLdStInst(const MachineInstr &MI);
112 
113  /// Return the opcode that set flags when possible. The caller is
114  /// responsible for ensuring the opc has a flag setting equivalent.
115  static unsigned convertToFlagSettingOpc(unsigned Opc, bool &Is64Bit);
116 
117  /// Return true if this is a load/store that can be potentially paired/merged.
118  bool isCandidateToMergeOrPair(const MachineInstr &MI) const;
119 
120  /// Hint that pairing the given load or store is unprofitable.
121  static void suppressLdStPair(MachineInstr &MI);
122 
125  const TargetRegisterInfo *TRI) const override;
126 
129  int64_t &Offset, bool &OffsetIsScalable, unsigned &Width,
130  const TargetRegisterInfo *TRI) const override;
131 
132  /// If \p OffsetIsScalable is set to 'true', the offset is scaled by `vscale`.
133  /// This is true for some SVE instructions like ldr/str that have a
134  /// 'reg + imm' addressing mode where the immediate is an index to the
135  /// scalable vector located at 'reg + imm * vscale x #bytes'.
137  const MachineOperand *&BaseOp,
138  int64_t &Offset, bool &OffsetIsScalable,
139  unsigned &Width,
140  const TargetRegisterInfo *TRI) const;
141 
142  /// Return the immediate offset of the base register in a load/store \p LdSt.
144 
145  /// Returns true if opcode \p Opc is a memory operation. If it is, set
146  /// \p Scale, \p Width, \p MinOffset, and \p MaxOffset accordingly.
147  ///
148  /// For unscaled instructions, \p Scale is set to 1.
149  static bool getMemOpInfo(unsigned Opcode, TypeSize &Scale, unsigned &Width,
150  int64_t &MinOffset, int64_t &MaxOffset);
151 
154  unsigned NumLoads, unsigned NumBytes) const override;
155 
157  const DebugLoc &DL, MCRegister DestReg,
158  MCRegister SrcReg, bool KillSrc, unsigned Opcode,
159  llvm::ArrayRef<unsigned> Indices) const;
161  DebugLoc DL, unsigned DestReg, unsigned SrcReg,
162  bool KillSrc, unsigned Opcode, unsigned ZeroReg,
163  llvm::ArrayRef<unsigned> Indices) const;
165  const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
166  bool KillSrc) const override;
167 
170  bool isKill, int FrameIndex,
171  const TargetRegisterClass *RC,
172  const TargetRegisterInfo *TRI) const override;
173 
176  int FrameIndex, const TargetRegisterClass *RC,
177  const TargetRegisterInfo *TRI) const override;
178 
179  // This tells target independent code that it is okay to pass instructions
180  // with subreg operands to foldMemoryOperandImpl.
181  bool isSubregFoldable() const override { return true; }
182 
184  MachineInstr *
186  ArrayRef<unsigned> Ops,
188  LiveIntervals *LIS = nullptr,
189  VirtRegMap *VRM = nullptr) const override;
190 
191  /// \returns true if a branch from an instruction with opcode \p BranchOpc
192  /// bytes is capable of jumping to a position \p BrOffset bytes away.
193  bool isBranchOffsetInRange(unsigned BranchOpc,
194  int64_t BrOffset) const override;
195 
196  MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override;
197 
199  MachineBasicBlock *&FBB,
201  bool AllowModify = false) const override;
203  MachineBranchPredicate &MBP,
204  bool AllowModify) const override;
206  int *BytesRemoved = nullptr) const override;
209  const DebugLoc &DL,
210  int *BytesAdded = nullptr) const override;
211  bool
214  Register, Register, Register, int &, int &,
215  int &) const override;
217  const DebugLoc &DL, Register DstReg,
219  Register FalseReg) const override;
220  MCInst getNop() const override;
221 
223  const MachineBasicBlock *MBB,
224  const MachineFunction &MF) const override;
225 
226  /// analyzeCompare - For a comparison instruction, return the source registers
227  /// in SrcReg and SrcReg2, and the value it compares against in CmpValue.
228  /// Return true if the comparison instruction can be analyzed.
229  bool analyzeCompare(const MachineInstr &MI, Register &SrcReg,
230  Register &SrcReg2, int64_t &CmpMask,
231  int64_t &CmpValue) const override;
232  /// optimizeCompareInstr - Convert the instruction supplying the argument to
233  /// the comparison into one that sets the zero bit in the flags register.
234  bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
235  Register SrcReg2, int64_t CmpMask, int64_t CmpValue,
236  const MachineRegisterInfo *MRI) const override;
237  bool optimizeCondBranch(MachineInstr &MI) const override;
238 
239  /// Return true when a code sequence can improve throughput. It
240  /// should be called only for instructions in loops.
241  /// \param Pattern - combiner pattern
243  /// Return true when there is potentially a faster code sequence
244  /// for an instruction chain ending in ``Root``. All potential patterns are
245  /// listed in the ``Patterns`` array.
246  bool
249  bool DoRegPressureReduce) const override;
250  /// Return true when Inst is associative and commutative so that it can be
251  /// reassociated.
252  bool isAssociativeAndCommutative(const MachineInstr &Inst) const override;
253  /// When getMachineCombinerPatterns() finds patterns, this function generates
254  /// the instructions that could replace the original code sequence
259  DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const override;
260  /// AArch64 supports MachineCombiner.
261  bool useMachineCombiner() const override;
262 
263  bool expandPostRAPseudo(MachineInstr &MI) const override;
264 
265  std::pair<unsigned, unsigned>
266  decomposeMachineOperandsTargetFlags(unsigned TF) const override;
273 
275  bool OutlineFromLinkOnceODRs) const override;
277  std::vector<outliner::Candidate> &RepeatedSequenceLocs) const override;
279  getOutliningType(MachineBasicBlock::iterator &MIT, unsigned Flags) const override;
281  unsigned &Flags) const override;
283  const outliner::OutlinedFunction &OF) const override;
287  const outliner::Candidate &C) const override;
288  bool shouldOutlineFromFunctionByDefault(MachineFunction &MF) const override;
289  /// Returns the vector element size (B, H, S or D) of an SVE opcode.
290  uint64_t getElementSizeForOpcode(unsigned Opc) const;
291  /// Returns true if the opcode is for an SVE instruction that sets the
292  /// condition codes as if it's results had been fed to a PTEST instruction
293  /// along with the same general predicate.
294  bool isPTestLikeOpcode(unsigned Opc) const;
295  /// Returns true if the opcode is for an SVE WHILE## instruction.
296  bool isWhileOpcode(unsigned Opc) const;
297  /// Returns true if the instruction has a shift by immediate that can be
298  /// executed in one cycle less.
299  static bool isFalkorShiftExtFast(const MachineInstr &MI);
300  /// Return true if the instructions is a SEH instruciton used for unwinding
301  /// on Windows.
302  static bool isSEHInstruction(const MachineInstr &MI);
303 
305  Register Reg) const override;
306 
308  Register Reg) const override;
309 
310  unsigned int getTailDuplicateSize(CodeGenOpt::Level OptLevel) const override;
311 
313  MachineRegisterInfo &MRI) const override;
314 
316  int64_t &NumBytes,
317  int64_t &NumPredicateVectors,
318  int64_t &NumDataVectors);
320  int64_t &ByteSized,
321  int64_t &VGSized);
322 #define GET_INSTRINFO_HELPER_DECLS
323 #include "AArch64GenInstrInfo.inc"
324 
325 protected:
326  /// If the specific machine instruction is an instruction that moves/copies
327  /// value from one register to another register return destination and source
328  /// registers as machine operands.
329  Optional<DestSourcePair>
330  isCopyInstrImpl(const MachineInstr &MI) const override;
331 
332 private:
333  unsigned getInstBundleLength(const MachineInstr &MI) const;
334 
335  /// Sets the offsets on outlined instructions in \p MBB which use SP
336  /// so that they will be valid post-outlining.
337  ///
338  /// \param MBB A \p MachineBasicBlock in an outlined function.
339  void fixupPostOutline(MachineBasicBlock &MBB) const;
340 
341  void instantiateCondBranch(MachineBasicBlock &MBB, const DebugLoc &DL,
342  MachineBasicBlock *TBB,
343  ArrayRef<MachineOperand> Cond) const;
344  bool substituteCmpToZero(MachineInstr &CmpInstr, unsigned SrcReg,
345  const MachineRegisterInfo &MRI) const;
346  bool removeCmpToZeroOrOne(MachineInstr &CmpInstr, unsigned SrcReg,
347  int CmpValue, const MachineRegisterInfo &MRI) const;
348 
349  /// Returns an unused general-purpose register which can be used for
350  /// constructing an outlined call if one exists. Returns 0 otherwise.
351  unsigned findRegisterToSaveLRTo(const outliner::Candidate &C) const;
352 
353  /// Remove a ptest of a predicate-generating operation that already sets, or
354  /// can be made to set, the condition codes in an identical manner
355  bool optimizePTestInstr(MachineInstr *PTest, unsigned MaskReg,
356  unsigned PredReg,
357  const MachineRegisterInfo *MRI) const;
358 };
359 
360 /// Return true if there is an instruction /after/ \p DefMI and before \p UseMI
361 /// which either reads or clobbers NZCV.
362 bool isNZCVTouchedInInstructionRange(const MachineInstr &DefMI,
363  const MachineInstr &UseMI,
364  const TargetRegisterInfo *TRI);
365 
366 /// emitFrameOffset - Emit instructions as needed to set DestReg to SrcReg
367 /// plus Offset. This is intended to be used from within the prolog/epilog
368 /// insertion (PEI) pass, where a virtual scratch register may be allocated
369 /// if necessary, to be replaced by the scavenger at the end of PEI.
370 void emitFrameOffset(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
371  const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
372  StackOffset Offset, const TargetInstrInfo *TII,
374  bool SetNZCV = false, bool NeedsWinCFI = false,
375  bool *HasWinCFI = nullptr);
376 
377 /// rewriteAArch64FrameIndex - Rewrite MI to access 'Offset' bytes from the
378 /// FP. Return false if the offset could not be handled directly in MI, and
379 /// return the left-over portion by reference.
380 bool rewriteAArch64FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
381  unsigned FrameReg, StackOffset &Offset,
382  const AArch64InstrInfo *TII);
383 
384 /// Use to report the frame offset status in isAArch64FrameOffsetLegal.
386  AArch64FrameOffsetCannotUpdate = 0x0, ///< Offset cannot apply.
387  AArch64FrameOffsetIsLegal = 0x1, ///< Offset is legal.
388  AArch64FrameOffsetCanUpdate = 0x2 ///< Offset can apply, at least partly.
389 };
390 
391 /// Check if the @p Offset is a valid frame offset for @p MI.
392 /// The returned value reports the validity of the frame offset for @p MI.
393 /// It uses the values defined by AArch64FrameOffsetStatus for that.
394 /// If result == AArch64FrameOffsetCannotUpdate, @p MI cannot be updated to
395 /// use an offset.eq
396 /// If result & AArch64FrameOffsetIsLegal, @p Offset can completely be
397 /// rewritten in @p MI.
398 /// If result & AArch64FrameOffsetCanUpdate, @p Offset contains the
399 /// amount that is off the limit of the legal offset.
400 /// If set, @p OutUseUnscaledOp will contain the whether @p MI should be
401 /// turned into an unscaled operator, which opcode is in @p OutUnscaledOp.
402 /// If set, @p EmittableOffset contains the amount that can be set in @p MI
403 /// (possibly with @p OutUnscaledOp if OutUseUnscaledOp is true) and that
404 /// is a legal offset.
405 int isAArch64FrameOffsetLegal(const MachineInstr &MI, StackOffset &Offset,
406  bool *OutUseUnscaledOp = nullptr,
407  unsigned *OutUnscaledOp = nullptr,
408  int64_t *EmittableOffset = nullptr);
409 
410 static inline bool isUncondBranchOpcode(int Opc) { return Opc == AArch64::B; }
411 
412 static inline bool isCondBranchOpcode(int Opc) {
413  switch (Opc) {
414  case AArch64::Bcc:
415  case AArch64::CBZW:
416  case AArch64::CBZX:
417  case AArch64::CBNZW:
418  case AArch64::CBNZX:
419  case AArch64::TBZW:
420  case AArch64::TBZX:
421  case AArch64::TBNZW:
422  case AArch64::TBNZX:
423  return true;
424  default:
425  return false;
426  }
427 }
428 
429 static inline bool isIndirectBranchOpcode(int Opc) {
430  switch (Opc) {
431  case AArch64::BR:
432  case AArch64::BRAA:
433  case AArch64::BRAB:
434  case AArch64::BRAAZ:
435  case AArch64::BRABZ:
436  return true;
437  }
438  return false;
439 }
440 
441 static inline bool isPTrueOpcode(unsigned Opc) {
442  switch (Opc) {
443  case AArch64::PTRUE_B:
444  case AArch64::PTRUE_H:
445  case AArch64::PTRUE_S:
446  case AArch64::PTRUE_D:
447  return true;
448  default:
449  return false;
450  }
451 }
452 
453 /// Return opcode to be used for indirect calls.
454 unsigned getBLRCallOpcode(const MachineFunction &MF);
455 
456 // struct TSFlags {
457 #define TSFLAG_ELEMENT_SIZE_TYPE(X) (X) // 3-bits
458 #define TSFLAG_DESTRUCTIVE_INST_TYPE(X) ((X) << 3) // 4-bits
459 #define TSFLAG_FALSE_LANE_TYPE(X) ((X) << 7) // 2-bits
460 #define TSFLAG_INSTR_FLAGS(X) ((X) << 9) // 2-bits
461 // }
462 
463 namespace AArch64 {
464 
472 };
473 
486 };
487 
492 };
493 
494 // NOTE: This is a bit field.
497 
498 #undef TSFLAG_ELEMENT_SIZE_TYPE
499 #undef TSFLAG_DESTRUCTIVE_INST_TYPE
500 #undef TSFLAG_FALSE_LANE_TYPE
501 #undef TSFLAG_INSTR_FLAGS
502 
503 int getSVEPseudoMap(uint16_t Opcode);
504 int getSVERevInstr(uint16_t Opcode);
505 int getSVENonRevInstr(uint16_t Opcode);
506 }
507 
508 } // end namespace llvm
509 
510 #endif
llvm::AArch64InstrInfo::getTailDuplicateSize
unsigned int getTailDuplicateSize(CodeGenOpt::Level OptLevel) const override
Definition: AArch64InstrInfo.cpp:7553
llvm::AArch64::DestructiveInstType
DestructiveInstType
Definition: AArch64InstrInfo.h:474
llvm::AArch64InstrInfo::describeLoadedValue
Optional< ParamLoadedValue > describeLoadedValue(const MachineInstr &MI, Register Reg) const override
Definition: AArch64InstrInfo.cpp:7493
llvm::AArch64::ElementSizeNone
@ ElementSizeNone
Definition: AArch64InstrInfo.h:467
AArch64RegisterInfo.h
llvm::AArch64InstrInfo::suppressLdStPair
static void suppressLdStPair(MachineInstr &MI)
Hint that pairing the given load or store is unprofitable.
Definition: AArch64InstrInfo.cpp:2162
llvm::AArch64InstrInfo::isThroughputPattern
bool isThroughputPattern(MachineCombinerPattern Pattern) const override
Return true when a code sequence can improve throughput.
Definition: AArch64InstrInfo.cpp:4866
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:103
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
AArch64.h
UseMI
MachineInstrBuilder & UseMI
Definition: AArch64ExpandPseudoInsts.cpp:102
llvm::AArch64InstrInfo::copyPhysReg
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
Definition: AArch64InstrInfo.cpp:3267
Optional.h
TSFLAG_DESTRUCTIVE_INST_TYPE
#define TSFLAG_DESTRUCTIVE_INST_TYPE(X)
Definition: AArch64InstrInfo.h:458
llvm::AArch64InstrInfo::expandPostRAPseudo
bool expandPostRAPseudo(MachineInstr &MI) const override
Definition: AArch64InstrInfo.cpp:1864
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
llvm::AArch64InstrInfo::getInstSizeInBytes
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
GetInstSize - Return the number of bytes of code the specified instruction may be.
Definition: AArch64InstrInfo.cpp:77
llvm::AArch64::FalseLanesZero
@ FalseLanesZero
Definition: AArch64InstrInfo.h:490
llvm::AArch64InstrInfo::getAddrModeFromMemoryOp
Optional< ExtAddrMode > getAddrModeFromMemoryOp(const MachineInstr &MemI, const TargetRegisterInfo *TRI) const override
Definition: AArch64InstrInfo.cpp:2534
llvm::AArch64::ElementSizeS
@ ElementSizeS
Definition: AArch64InstrInfo.h:470
llvm::AArch64FrameOffsetCanUpdate
@ AArch64FrameOffsetCanUpdate
Offset can apply, at least partly.
Definition: AArch64InstrInfo.h:388
llvm::AArch64InstrInfo::getMemOperandWithOffsetWidth
bool getMemOperandWithOffsetWidth(const MachineInstr &MI, const MachineOperand *&BaseOp, int64_t &Offset, bool &OffsetIsScalable, unsigned &Width, const TargetRegisterInfo *TRI) const
If OffsetIsScalable is set to 'true', the offset is scaled by vscale.
Definition: AArch64InstrInfo.cpp:2551
TypeSize.h
llvm::AArch64::InstrFlagIsPTestLike
static const uint64_t InstrFlagIsPTestLike
Definition: AArch64InstrInfo.h:496
llvm::AArch64InstrInfo::getMemOperandsWithOffsetWidth
bool getMemOperandsWithOffsetWidth(const MachineInstr &MI, SmallVectorImpl< const MachineOperand * > &BaseOps, int64_t &Offset, bool &OffsetIsScalable, unsigned &Width, const TargetRegisterInfo *TRI) const override
Definition: AArch64InstrInfo.cpp:2518
llvm::VirtRegMap
Definition: VirtRegMap.h:33
llvm::getBLRCallOpcode
unsigned getBLRCallOpcode(const MachineFunction &MF)
Return opcode to be used for indirect calls.
Definition: AArch64InstrInfo.cpp:7557
llvm::AArch64InstrInfo::isPreLdSt
static bool isPreLdSt(const MachineInstr &MI)
Returns whether the instruction is a pre-indexed load/store.
Definition: AArch64InstrInfo.cpp:3061
llvm::AArch64InstrInfo::getMemScale
static int getMemScale(const MachineInstr &MI)
Definition: AArch64InstrInfo.h:94
llvm::AArch64InstrInfo::getSerializableDirectMachineOperandTargetFlags
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
Definition: AArch64InstrInfo.cpp:6218
llvm::MachineMemOperand::MOTargetFlag2
@ MOTargetFlag2
Definition: MachineMemOperand.h:152
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:233
llvm::outliner::InstrType
InstrType
Represents how an instruction should be mapped by the outliner.
Definition: MachineOutliner.h:34
llvm::AArch64InstrInfo::getElementSizeForOpcode
uint64_t getElementSizeForOpcode(unsigned Opc) const
Returns the vector element size (B, H, S or D) of an SVE opcode.
Definition: AArch64InstrInfo.cpp:7540
TargetInstrInfo.h
llvm::AArch64InstrInfo::areMemAccessesTriviallyDisjoint
bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb) const override
Definition: AArch64InstrInfo.cpp:1053
llvm::isCondBranchOpcode
static bool isCondBranchOpcode(int Opc)
Definition: AArch64InstrInfo.h:412
llvm::rewriteAArch64FrameIndex
bool rewriteAArch64FrameIndex(MachineInstr &MI, unsigned FrameRegIdx, unsigned FrameReg, StackOffset &Offset, const AArch64InstrInfo *TII)
rewriteAArch64FrameIndex - Rewrite MI to access 'Offset' bytes from the FP.
Definition: AArch64InstrInfo.cpp:4358
llvm::AArch64::ElementSizeB
@ ElementSizeB
Definition: AArch64InstrInfo.h:468
llvm::AArch64::DestructiveTernaryCommWithRev
@ DestructiveTernaryCommWithRev
Definition: AArch64InstrInfo.h:484
llvm::Optional< unsigned >
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
llvm::isUncondBranchOpcode
static bool isUncondBranchOpcode(int Opc)
Definition: AArch64InstrInfo.h:410
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
llvm::outliner::OutlinedFunction
The information necessary to create an outlined function for some class of candidate.
Definition: MachineOutliner.h:164
llvm::AArch64InstrInfo::copyGPRRegTuple
void copyGPRRegTuple(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc, unsigned Opcode, unsigned ZeroReg, llvm::ArrayRef< unsigned > Indices) const
Definition: AArch64InstrInfo.cpp:3242
llvm::AArch64::DestructiveOther
@ DestructiveOther
Definition: AArch64InstrInfo.h:477
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
llvm::AArch64InstrInfo::buildOutlinedFrame
void buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF, const outliner::OutlinedFunction &OF) const override
Definition: AArch64InstrInfo.cpp:7181
llvm::AArch64FrameOffsetCannotUpdate
@ AArch64FrameOffsetCannotUpdate
Offset cannot apply.
Definition: AArch64InstrInfo.h:386
llvm::AArch64InstrInfo::isPairableLdStInst
static bool isPairableLdStInst(const MachineInstr &MI)
Return true if pairing the given load or store may be paired with another.
Definition: AArch64InstrInfo.cpp:2317
llvm::AArch64::getSVERevInstr
int getSVERevInstr(uint16_t Opcode)
AArch64GenInstrInfo
x3
In x86 we generate this spiffy xmm0 xmm0 ret in x86 we generate this which could be xmm1 movss xmm1 xmm0 ret In sse4 we could use insertps to make both better Here s another testcase that could use x3
Definition: README-SSE.txt:547
llvm::MachineMemOperand::MOTargetFlag1
@ MOTargetFlag1
Definition: MachineMemOperand.h:151
llvm::AArch64InstrInfo::getLoadStoreImmIdx
static unsigned getLoadStoreImmIdx(unsigned Opc)
Returns the index for the immediate for a given instruction.
Definition: AArch64InstrInfo.cpp:2240
llvm::AArch64::FalseLaneType
FalseLaneType
Definition: AArch64InstrInfo.h:488
llvm::AArch64InstrInfo::isWhileOpcode
bool isWhileOpcode(unsigned Opc) const
Returns true if the opcode is for an SVE WHILE## instruction.
Definition: AArch64InstrInfo.cpp:7548
llvm::MOStridedAccess
static const MachineMemOperand::Flags MOStridedAccess
Definition: AArch64InstrInfo.h:33
llvm::AArch64InstrInfo
Definition: AArch64InstrInfo.h:38
llvm::AArch64InstrInfo::isSchedulingBoundary
bool isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override
Definition: AArch64InstrInfo.cpp:1091
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::AArch64InstrInfo::isGPRZero
static bool isGPRZero(const MachineInstr &MI)
Does this instruction set its full destination register to zero?
Definition: AArch64InstrInfo.cpp:2034
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::AArch64::InstrFlagIsWhile
static const uint64_t InstrFlagIsWhile
Definition: AArch64InstrInfo.h:495
llvm::AArch64InstrInfo::shouldOutlineFromFunctionByDefault
bool shouldOutlineFromFunctionByDefault(MachineFunction &MF) const override
Definition: AArch64InstrInfo.cpp:7393
llvm::AArch64InstrInfo::getMachineCombinerPatterns
bool getMachineCombinerPatterns(MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &Patterns, bool DoRegPressureReduce) const override
Return true when there is potentially a faster code sequence for an instruction chain ending in Root.
Definition: AArch64InstrInfo.cpp:4975
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:129
llvm::AArch64InstrInfo::insertBranch
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
Definition: AArch64InstrInfo.cpp:503
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
llvm::AArch64InstrInfo::isStridedAccess
static bool isStridedAccess(const MachineInstr &MI)
Return true if the given load or store is a strided memory access.
Definition: AArch64InstrInfo.cpp:2169
llvm::AArch64::DestructiveUnaryPassthru
@ DestructiveUnaryPassthru
Definition: AArch64InstrInfo.h:485
MachineCombinerPattern.h
llvm::AArch64InstrInfo::copyPhysRegTuple
void copyPhysRegTuple(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc, unsigned Opcode, llvm::ArrayRef< unsigned > Indices) const
Definition: AArch64InstrInfo.cpp:3215
llvm::AArch64InstrInfo::isFPRCopy
static bool isFPRCopy(const MachineInstr &MI)
Does this instruction rename an FPR without modifying bits?
Definition: AArch64InstrInfo.cpp:2088
llvm::AArch64InstrInfo::useMachineCombiner
bool useMachineCombiner() const override
AArch64 supports MachineCombiner.
Definition: AArch64InstrInfo.cpp:4398
llvm::emitFrameOffset
void emitFrameOffset(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, StackOffset Offset, const TargetInstrInfo *TII, MachineInstr::MIFlag=MachineInstr::NoFlags, bool SetNZCV=false, bool NeedsWinCFI=false, bool *HasWinCFI=nullptr)
emitFrameOffset - Emit instructions as needed to set DestReg to SrcReg plus Offset.
Definition: AArch64InstrInfo.cpp:4041
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::AArch64InstrInfo::getBranchDestBlock
MachineBasicBlock * getBranchDestBlock(const MachineInstr &MI) const override
Definition: AArch64InstrInfo.cpp:221
llvm::AArch64::ElementSizeType
ElementSizeType
Definition: AArch64InstrInfo.h:465
llvm::AArch64InstrInfo::isCoalescableExtInstr
bool isCoalescableExtInstr(const MachineInstr &MI, Register &SrcReg, Register &DstReg, unsigned &SubIdx) const override
Definition: AArch64InstrInfo.cpp:1033
llvm::AArch64FrameOffsetIsLegal
@ AArch64FrameOffsetIsLegal
Offset is legal.
Definition: AArch64InstrInfo.h:387
llvm::AArch64::NotDestructive
@ NotDestructive
Definition: AArch64InstrInfo.h:476
llvm::isAArch64FrameOffsetLegal
int isAArch64FrameOffsetLegal(const MachineInstr &MI, StackOffset &Offset, bool *OutUseUnscaledOp=nullptr, unsigned *OutUnscaledOp=nullptr, int64_t *EmittableOffset=nullptr)
Check if the Offset is a valid frame offset for MI.
Definition: AArch64InstrInfo.cpp:4261
llvm::isIndirectBranchOpcode
static bool isIndirectBranchOpcode(int Opc)
Definition: AArch64InstrInfo.h:429
x2
gcc mainline compiles it x2(%rip)
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
uint64_t
llvm::AArch64InstrInfo::isPreLd
static bool isPreLd(const MachineInstr &MI)
Returns whether the instruction is a pre-indexed load.
Definition: AArch64InstrInfo.cpp:3035
llvm::MOSuppressPair
static const MachineMemOperand::Flags MOSuppressPair
Definition: AArch64InstrInfo.h:31
TSFLAG_INSTR_FLAGS
#define TSFLAG_INSTR_FLAGS(X)
Definition: AArch64InstrInfo.h:460
llvm::outliner::Candidate
An individual sequence of instructions to be replaced with a call to an outlined function.
Definition: MachineOutliner.h:38
llvm::DenseMap< unsigned, unsigned >
llvm::AArch64InstrInfo::removeBranch
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
Definition: AArch64InstrInfo.cpp:451
TSFLAG_ELEMENT_SIZE_TYPE
#define TSFLAG_ELEMENT_SIZE_TYPE(X)
Definition: AArch64InstrInfo.h:457
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::AArch64InstrInfo::getOutliningType
outliner::InstrType getOutliningType(MachineBasicBlock::iterator &MIT, unsigned Flags) const override
Definition: AArch64InstrInfo.cpp:6936
llvm::AArch64InstrInfo::isFunctionSafeToOutlineFrom
bool isFunctionSafeToOutlineFrom(MachineFunction &MF, bool OutlineFromLinkOnceODRs) const override
Definition: AArch64InstrInfo.cpp:6839
llvm::AArch64InstrInfo::genAlternativeCodeSequence
void genAlternativeCodeSequence(MachineInstr &Root, MachineCombinerPattern Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, DenseMap< unsigned, unsigned > &InstrIdxForVirtReg) const override
When getMachineCombinerPatterns() finds patterns, this function generates the instructions that could...
Definition: AArch64InstrInfo.cpp:5199
llvm::AArch64InstrInfo::isLoadFromStackSlot
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
Definition: AArch64InstrInfo.cpp:2107
llvm::AArch64InstrInfo::getNop
MCInst getNop() const override
Definition: AArch64InstrInfo.cpp:4393
llvm::AArch64InstrInfo::isMBBSafeToOutlineFrom
bool isMBBSafeToOutlineFrom(MachineBasicBlock &MBB, unsigned &Flags) const override
Definition: AArch64InstrInfo.cpp:6869
llvm::MachineMemOperand::Flags
Flags
Flags values. These may be or'd together.
Definition: MachineMemOperand.h:131
llvm::isNZCVTouchedInInstructionRange
bool isNZCVTouchedInInstructionRange(const MachineInstr &DefMI, const MachineInstr &UseMI, const TargetRegisterInfo *TRI)
Return true if there is an instruction /after/ DefMI and before UseMI which either reads or clobbers ...
Definition: AArch64InstrInfo.cpp:3887
llvm::MachineInstr::NoFlags
@ NoFlags
Definition: MachineInstr.h:81
llvm::AArch64InstrInfo::getOutliningCandidateInfo
outliner::OutlinedFunction getOutliningCandidateInfo(std::vector< outliner::Candidate > &RepeatedSequenceLocs) const override
Definition: AArch64InstrInfo.cpp:6397
llvm::AArch64InstrInfo::getSerializableBitmaskMachineOperandTargetFlags
ArrayRef< std::pair< unsigned, const char * > > getSerializableBitmaskMachineOperandTargetFlags() const override
Definition: AArch64InstrInfo.cpp:6230
llvm::AArch64InstrInfo::getMemOpBaseRegImmOfsOffsetOperand
MachineOperand & getMemOpBaseRegImmOfsOffsetOperand(MachineInstr &LdSt) const
Return the immediate offset of the base register in a load/store LdSt.
Definition: AArch64InstrInfo.cpp:2600
llvm::AArch64InstrInfo::AArch64InstrInfo
AArch64InstrInfo(const AArch64Subtarget &STI)
Definition: AArch64InstrInfo.cpp:70
llvm::AArch64InstrInfo::isAddImmediate
Optional< RegImmPair > isAddImmediate(const MachineInstr &MI, Register Reg) const override
Definition: AArch64InstrInfo.cpp:7418
llvm::AArch64InstrInfo::getUnscaledLdSt
static Optional< unsigned > getUnscaledLdSt(unsigned Opc)
Returns the unscaled load/store for the scaled load/store opcode, if there is a corresponding unscale...
Definition: AArch64InstrInfo.cpp:2210
llvm::Module
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:67
llvm::MachineInstr::MIFlag
MIFlag
Definition: MachineInstr.h:80
llvm::MachineFunction
Definition: MachineFunction.h:230
llvm::MachineBasicBlock::iterator
MachineInstrBundleIterator< MachineInstr > iterator
Definition: MachineBasicBlock.h:233
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::AArch64InstrInfo::shouldClusterMemOps
bool shouldClusterMemOps(ArrayRef< const MachineOperand * > BaseOps1, ArrayRef< const MachineOperand * > BaseOps2, unsigned NumLoads, unsigned NumBytes) const override
Detect opportunities for ldp/stp formation.
Definition: AArch64InstrInfo.cpp:3128
llvm::AArch64InstrInfo::isGPRCopy
static bool isGPRCopy(const MachineInstr &MI)
Does this instruction rename a GPR without modifying bits?
Definition: AArch64InstrInfo.cpp:2058
Cond
SmallVector< MachineOperand, 4 > Cond
Definition: BasicBlockSections.cpp:179
llvm::AArch64InstrInfo::isPTestLikeOpcode
bool isPTestLikeOpcode(unsigned Opc) const
Returns true if the opcode is for an SVE instruction that sets the condition codes as if it's results...
Definition: AArch64InstrInfo.cpp:7544
MBBI
MachineBasicBlock MachineBasicBlock::iterator MBBI
Definition: AArch64SLSHardening.cpp:75
llvm::AArch64::FalseLanesMask
@ FalseLanesMask
Definition: AArch64InstrInfo.h:489
llvm::AArch64InstrInfo::isCopyInstrImpl
Optional< DestSourcePair > isCopyInstrImpl(const MachineInstr &MI) const override
If the specific machine instruction is an instruction that moves/copies value from one register to an...
Definition: AArch64InstrInfo.cpp:7399
llvm::AArch64InstrInfo::decomposeMachineOperandsTargetFlags
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
Definition: AArch64InstrInfo.cpp:6212
llvm::StackOffset
StackOffset is a class to represent an offset with 2 dimensions, named fixed and scalable,...
Definition: TypeSize.h:134
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::AArch64RegisterInfo
Definition: AArch64RegisterInfo.h:26
llvm::CodeGenOpt::Level
Level
Definition: CodeGen.h:52
llvm::AArch64InstrInfo::canInsertSelect
bool canInsertSelect(const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, Register, Register, Register, int &, int &, int &) const override
Definition: AArch64InstrInfo.cpp:611
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::AArch64InstrInfo::loadRegFromStackSlot
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Definition: AArch64InstrInfo.cpp:3758
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::AArch64InstrInfo::getSerializableMachineMemOperandTargetFlags
ArrayRef< std::pair< MachineMemOperand::Flags, const char * > > getSerializableMachineMemOperandTargetFlags() const override
Definition: AArch64InstrInfo.cpp:6246
llvm::AArch64::DestructiveUnary
@ DestructiveUnary
Definition: AArch64InstrInfo.h:478
llvm::ISD::FrameIndex
@ FrameIndex
Definition: ISDOpcodes.h:80
llvm::AArch64InstrInfo::decomposeStackOffsetForFrameOffsets
static void decomposeStackOffsetForFrameOffsets(const StackOffset &Offset, int64_t &NumBytes, int64_t &NumPredicateVectors, int64_t &NumDataVectors)
Returns the offset in parts to which this frame offset can be decomposed for the purpose of describin...
Definition: AArch64InstrInfo.cpp:3917
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::AArch64::ElementSizeD
@ ElementSizeD
Definition: AArch64InstrInfo.h:471
llvm::AArch64InstrInfo::hasUnscaledLdStOffset
static bool hasUnscaledLdStOffset(unsigned Opc)
Return true if it has an unscaled load/store offset.
Definition: AArch64InstrInfo.cpp:2175
llvm::AArch64InstrInfo::getRegisterInfo
const AArch64RegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
Definition: AArch64InstrInfo.h:48
llvm::AArch64::DestructiveBinaryShImmUnpred
@ DestructiveBinaryShImmUnpred
Definition: AArch64InstrInfo.h:480
uint16_t
llvm::AArch64InstrInfo::convertToFlagSettingOpc
static unsigned convertToFlagSettingOpc(unsigned Opc, bool &Is64Bit)
Return the opcode that set flags when possible.
Definition: AArch64InstrInfo.cpp:2359
llvm::ISD::BR
@ BR
Control flow instructions. These all have token chains.
Definition: ISDOpcodes.h:937
llvm::AArch64InstrInfo::storeRegToStackSlot
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Definition: AArch64InstrInfo.cpp:3604
llvm::AArch64::ElementSizeMask
@ ElementSizeMask
Definition: AArch64InstrInfo.h:466
llvm::TypeSize
Definition: TypeSize.h:417
llvm::AArch64InstrInfo::getMemOpInfo
static bool getMemOpInfo(unsigned Opcode, TypeSize &Scale, unsigned &Width, int64_t &MinOffset, int64_t &MaxOffset)
Returns true if opcode Opc is a memory operation.
Definition: AArch64InstrInfo.cpp:2607
llvm::AArch64::DestructiveInstTypeMask
@ DestructiveInstTypeMask
Definition: AArch64InstrInfo.h:475
llvm::AArch64InstrInfo::isLdStPairSuppressed
static bool isLdStPairSuppressed(const MachineInstr &MI)
Return true if pairing the given load or store is hinted to be unprofitable.
Definition: AArch64InstrInfo.cpp:2155
llvm::AArch64InstrInfo::decomposeStackOffsetForDwarfOffsets
static void decomposeStackOffsetForDwarfOffsets(const StackOffset &Offset, int64_t &ByteSized, int64_t &VGSized)
Definition: AArch64InstrInfo.cpp:3898
llvm::AArch64InstrInfo::analyzeBranchPredicate
bool analyzeBranchPredicate(MachineBasicBlock &MBB, MachineBranchPredicate &MBP, bool AllowModify) const override
Definition: AArch64InstrInfo.cpp:360
llvm::LiveIntervals
Definition: LiveIntervals.h:54
llvm::AArch64InstrInfo::insertSelect
void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, Register DstReg, ArrayRef< MachineOperand > Cond, Register TrueReg, Register FalseReg) const override
Definition: AArch64InstrInfo.cpp:660
llvm::AArch64InstrInfo::optimizeCompareInstr
bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int64_t CmpMask, int64_t CmpValue, const MachineRegisterInfo *MRI) const override
optimizeCompareInstr - Convert the instruction supplying the argument to the comparison into one that...
Definition: AArch64InstrInfo.cpp:1429
llvm::AArch64InstrInfo::isBranchOffsetInRange
bool isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const override
Definition: AArch64InstrInfo.cpp:212
llvm::AMDGPU::Hwreg::Width
Width
Definition: SIDefines.h:410
llvm::AArch64::DestructiveBinaryComm
@ DestructiveBinaryComm
Definition: AArch64InstrInfo.h:482
TSFLAG_FALSE_LANE_TYPE
#define TSFLAG_FALSE_LANE_TYPE(X)
Definition: AArch64InstrInfo.h:459
llvm::AArch64FrameOffsetStatus
AArch64FrameOffsetStatus
Use to report the frame offset status in isAArch64FrameOffsetLegal.
Definition: AArch64InstrInfo.h:385
llvm::AArch64::DestructiveBinary
@ DestructiveBinary
Definition: AArch64InstrInfo.h:481
llvm::Pattern
Definition: FileCheckImpl.h:614
llvm::TargetInstrInfo::foldMemoryOperandImpl
virtual MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const
Target-dependent implementation for foldMemoryOperand.
Definition: TargetInstrInfo.h:1207
llvm::AArch64InstrInfo::foldMemoryOperandImpl
MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const override
Definition: AArch64InstrInfo.cpp:4083
DefMI
MachineInstrBuilder MachineInstrBuilder & DefMI
Definition: AArch64ExpandPseudoInsts.cpp:103
llvm::AArch64::getSVEPseudoMap
int getSVEPseudoMap(uint16_t Opcode)
llvm::AArch64InstrInfo::isExtendLikelyToBeFolded
bool isExtendLikelyToBeFolded(MachineInstr &ExtMI, MachineRegisterInfo &MRI) const override
Definition: AArch64InstrInfo.cpp:7520
llvm::AArch64InstrInfo::hasUnscaledLdStOffset
static bool hasUnscaledLdStOffset(MachineInstr &MI)
Definition: AArch64InstrInfo.h:84
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
llvm::AArch64InstrInfo::reverseBranchCondition
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
Definition: AArch64InstrInfo.cpp:410
llvm::AArch64::DestructiveBinaryImm
@ DestructiveBinaryImm
Definition: AArch64InstrInfo.h:479
llvm::AArch64InstrInfo::insertOutlinedCall
MachineBasicBlock::iterator insertOutlinedCall(Module &M, MachineBasicBlock &MBB, MachineBasicBlock::iterator &It, MachineFunction &MF, const outliner::Candidate &C) const override
Definition: AArch64InstrInfo.cpp:7317
llvm::AArch64::DestructiveBinaryCommWithRev
@ DestructiveBinaryCommWithRev
Definition: AArch64InstrInfo.h:483
llvm::AArch64InstrInfo::getMemScale
static int getMemScale(unsigned Opc)
Scaling factor for (scaled or unscaled) load or store.
Definition: AArch64InstrInfo.cpp:2963
llvm::AArch64InstrInfo::optimizeCondBranch
bool optimizeCondBranch(MachineInstr &MI) const override
Replace csincr-branch sequence by simple conditional branch.
Definition: AArch64InstrInfo.cpp:6074
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::AArch64InstrInfo::analyzeCompare
bool analyzeCompare(const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int64_t &CmpMask, int64_t &CmpValue) const override
analyzeCompare - For a comparison instruction, return the source registers in SrcReg and SrcReg2,...
Definition: AArch64InstrInfo.cpp:1114
llvm::AArch64InstrInfo::isFalkorShiftExtFast
static bool isFalkorShiftExtFast(const MachineInstr &MI)
Returns true if the instruction has a shift by immediate that can be executed in one cycle less.
Definition: AArch64InstrInfo.cpp:885
llvm::isPTrueOpcode
static bool isPTrueOpcode(unsigned Opc)
Definition: AArch64InstrInfo.h:441
llvm::AArch64Subtarget
Definition: AArch64Subtarget.h:38
llvm::AArch64InstrInfo::isCandidateToMergeOrPair
bool isCandidateToMergeOrPair(const MachineInstr &MI) const
Return true if this is a load/store that can be potentially paired/merged.
Definition: AArch64InstrInfo.cpp:2449
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::AArch64::FalseLanesUndef
@ FalseLanesUndef
Definition: AArch64InstrInfo.h:491
llvm::AArch64::getSVENonRevInstr
int getSVENonRevInstr(uint16_t Opcode)
llvm::AArch64InstrInfo::isPreSt
static bool isPreSt(const MachineInstr &MI)
Returns whether the instruction is a pre-indexed store.
Definition: AArch64InstrInfo.cpp:3048
llvm::AArch64InstrInfo::isAssociativeAndCommutative
bool isAssociativeAndCommutative(const MachineInstr &Inst) const override
Return true when Inst is associative and commutative so that it can be reassociated.
Definition: AArch64InstrInfo.cpp:4554
llvm::AArch64InstrInfo::isSubregFoldable
bool isSubregFoldable() const override
Definition: AArch64InstrInfo.h:181
llvm::AArch64InstrInfo::isAsCheapAsAMove
bool isAsCheapAsAMove(const MachineInstr &MI) const override
Definition: AArch64InstrInfo.cpp:806
llvm::AArch64InstrInfo::isSEHInstruction
static bool isSEHInstruction(const MachineInstr &MI)
Return true if the instructions is a SEH instruciton used for unwinding on Windows.
Definition: AArch64InstrInfo.cpp:1007
llvm::AArch64InstrInfo::isStoreToStackSlot
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
Definition: AArch64InstrInfo.cpp:2130
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:23
llvm::MachineCombinerPattern
MachineCombinerPattern
These are instruction patterns matched by the machine combiner pass.
Definition: MachineCombinerPattern.h:20
llvm::AArch64InstrInfo::analyzeBranch
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override
Definition: AArch64InstrInfo.cpp:242
llvm::AArch64::ElementSizeH
@ ElementSizeH
Definition: AArch64InstrInfo.h:469