LLVM 17.0.0git
AArch64InstrInfo.h
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1//===- AArch64InstrInfo.h - AArch64 Instruction Information -----*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the AArch64 implementation of the TargetInstrInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_AARCH64_AARCH64INSTRINFO_H
14#define LLVM_LIB_TARGET_AARCH64_AARCH64INSTRINFO_H
15
16#include "AArch64.h"
17#include "AArch64RegisterInfo.h"
20#include <optional>
21
22#define GET_INSTRINFO_HEADER
23#include "AArch64GenInstrInfo.inc"
24
25namespace llvm {
26
27class AArch64Subtarget;
28
33
34#define FALKOR_STRIDED_ACCESS_MD "falkor.strided.access"
35
37 const AArch64RegisterInfo RI;
38 const AArch64Subtarget &Subtarget;
39
40public:
41 explicit AArch64InstrInfo(const AArch64Subtarget &STI);
42
43 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
44 /// such, whenever a client has an instance of instruction info, it should
45 /// always be able to get register info as well (through this method).
46 const AArch64RegisterInfo &getRegisterInfo() const { return RI; }
47
48 unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
49
50 bool isAsCheapAsAMove(const MachineInstr &MI) const override;
51
52 bool isCoalescableExtInstr(const MachineInstr &MI, Register &SrcReg,
53 Register &DstReg, unsigned &SubIdx) const override;
54
55 bool
57 const MachineInstr &MIb) const override;
58
59 unsigned isLoadFromStackSlot(const MachineInstr &MI,
60 int &FrameIndex) const override;
61 unsigned isStoreToStackSlot(const MachineInstr &MI,
62 int &FrameIndex) const override;
63
64 /// Does this instruction set its full destination register to zero?
65 static bool isGPRZero(const MachineInstr &MI);
66
67 /// Does this instruction rename a GPR without modifying bits?
68 static bool isGPRCopy(const MachineInstr &MI);
69
70 /// Does this instruction rename an FPR without modifying bits?
71 static bool isFPRCopy(const MachineInstr &MI);
72
73 /// Return true if pairing the given load or store is hinted to be
74 /// unprofitable.
75 static bool isLdStPairSuppressed(const MachineInstr &MI);
76
77 /// Return true if the given load or store is a strided memory access.
78 static bool isStridedAccess(const MachineInstr &MI);
79
80 /// Return true if it has an unscaled load/store offset.
81 static bool hasUnscaledLdStOffset(unsigned Opc);
83 return hasUnscaledLdStOffset(MI.getOpcode());
84 }
85
86 /// Returns the unscaled load/store for the scaled load/store opcode,
87 /// if there is a corresponding unscaled variant available.
88 static std::optional<unsigned> getUnscaledLdSt(unsigned Opc);
89
90 /// Scaling factor for (scaled or unscaled) load or store.
91 static int getMemScale(unsigned Opc);
92 static int getMemScale(const MachineInstr &MI) {
93 return getMemScale(MI.getOpcode());
94 }
95
96 /// Returns whether the instruction is a pre-indexed load.
97 static bool isPreLd(const MachineInstr &MI);
98
99 /// Returns whether the instruction is a pre-indexed store.
100 static bool isPreSt(const MachineInstr &MI);
101
102 /// Returns whether the instruction is a pre-indexed load/store.
103 static bool isPreLdSt(const MachineInstr &MI);
104
105 /// Returns whether the instruction is a paired load/store.
106 static bool isPairedLdSt(const MachineInstr &MI);
107
108 /// Returns the base register operator of a load/store.
109 static const MachineOperand &getLdStBaseOp(const MachineInstr &MI);
110
111 /// Returns the the immediate offset operator of a load/store.
112 static const MachineOperand &getLdStOffsetOp(const MachineInstr &MI);
113
114 /// Returns whether the instruction is FP or NEON.
115 static bool isFpOrNEON(const MachineInstr &MI);
116
117 /// Returns whether the instruction is in Q form (128 bit operands)
118 static bool isQForm(const MachineInstr &MI);
119
120 /// Returns the index for the immediate for a given instruction.
121 static unsigned getLoadStoreImmIdx(unsigned Opc);
122
123 /// Return true if pairing the given load or store may be paired with another.
124 static bool isPairableLdStInst(const MachineInstr &MI);
125
126 /// Return the opcode that set flags when possible. The caller is
127 /// responsible for ensuring the opc has a flag setting equivalent.
128 static unsigned convertToFlagSettingOpc(unsigned Opc);
129
130 /// Return true if this is a load/store that can be potentially paired/merged.
131 bool isCandidateToMergeOrPair(const MachineInstr &MI) const;
132
133 /// Hint that pairing the given load or store is unprofitable.
134 static void suppressLdStPair(MachineInstr &MI);
135
136 std::optional<ExtAddrMode>
138 const TargetRegisterInfo *TRI) const override;
139
142 int64_t &Offset, bool &OffsetIsScalable, unsigned &Width,
143 const TargetRegisterInfo *TRI) const override;
144
145 /// If \p OffsetIsScalable is set to 'true', the offset is scaled by `vscale`.
146 /// This is true for some SVE instructions like ldr/str that have a
147 /// 'reg + imm' addressing mode where the immediate is an index to the
148 /// scalable vector located at 'reg + imm * vscale x #bytes'.
150 const MachineOperand *&BaseOp,
151 int64_t &Offset, bool &OffsetIsScalable,
152 unsigned &Width,
153 const TargetRegisterInfo *TRI) const;
154
155 /// Return the immediate offset of the base register in a load/store \p LdSt.
157
158 /// Returns true if opcode \p Opc is a memory operation. If it is, set
159 /// \p Scale, \p Width, \p MinOffset, and \p MaxOffset accordingly.
160 ///
161 /// For unscaled instructions, \p Scale is set to 1.
162 static bool getMemOpInfo(unsigned Opcode, TypeSize &Scale, unsigned &Width,
163 int64_t &MinOffset, int64_t &MaxOffset);
164
167 unsigned NumLoads, unsigned NumBytes) const override;
168
170 const DebugLoc &DL, MCRegister DestReg,
171 MCRegister SrcReg, bool KillSrc, unsigned Opcode,
172 llvm::ArrayRef<unsigned> Indices) const;
174 DebugLoc DL, unsigned DestReg, unsigned SrcReg,
175 bool KillSrc, unsigned Opcode, unsigned ZeroReg,
176 llvm::ArrayRef<unsigned> Indices) const;
178 const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
179 bool KillSrc) const override;
180
183 bool isKill, int FrameIndex,
184 const TargetRegisterClass *RC,
185 const TargetRegisterInfo *TRI,
186 Register VReg) const override;
187
190 int FrameIndex, const TargetRegisterClass *RC,
191 const TargetRegisterInfo *TRI,
192 Register VReg) const override;
193
194 // This tells target independent code that it is okay to pass instructions
195 // with subreg operands to foldMemoryOperandImpl.
196 bool isSubregFoldable() const override { return true; }
197
202 MachineBasicBlock::iterator InsertPt, int FrameIndex,
203 LiveIntervals *LIS = nullptr,
204 VirtRegMap *VRM = nullptr) const override;
205
206 /// \returns true if a branch from an instruction with opcode \p BranchOpc
207 /// bytes is capable of jumping to a position \p BrOffset bytes away.
208 bool isBranchOffsetInRange(unsigned BranchOpc,
209 int64_t BrOffset) const override;
210
211 MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override;
212
214 MachineBasicBlock *&FBB,
216 bool AllowModify = false) const override;
218 MachineBranchPredicate &MBP,
219 bool AllowModify) const override;
221 int *BytesRemoved = nullptr) const override;
224 const DebugLoc &DL,
225 int *BytesAdded = nullptr) const override;
226 bool
229 Register, Register, Register, int &, int &,
230 int &) const override;
232 const DebugLoc &DL, Register DstReg,
234 Register FalseReg) const override;
235 MCInst getNop() const override;
236
238 const MachineBasicBlock *MBB,
239 const MachineFunction &MF) const override;
240
241 /// analyzeCompare - For a comparison instruction, return the source registers
242 /// in SrcReg and SrcReg2, and the value it compares against in CmpValue.
243 /// Return true if the comparison instruction can be analyzed.
244 bool analyzeCompare(const MachineInstr &MI, Register &SrcReg,
245 Register &SrcReg2, int64_t &CmpMask,
246 int64_t &CmpValue) const override;
247 /// optimizeCompareInstr - Convert the instruction supplying the argument to
248 /// the comparison into one that sets the zero bit in the flags register.
249 bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
250 Register SrcReg2, int64_t CmpMask, int64_t CmpValue,
251 const MachineRegisterInfo *MRI) const override;
252 bool optimizeCondBranch(MachineInstr &MI) const override;
253
254 /// Return true when a code sequence can improve throughput. It
255 /// should be called only for instructions in loops.
256 /// \param Pattern - combiner pattern
258 /// Return true when there is potentially a faster code sequence
259 /// for an instruction chain ending in ``Root``. All potential patterns are
260 /// listed in the ``Patterns`` array.
261 bool
264 bool DoRegPressureReduce) const override;
265 /// Return true when Inst is associative and commutative so that it can be
266 /// reassociated. If Invert is true, then the inverse of Inst operation must
267 /// be checked.
269 bool Invert) const override;
270 /// When getMachineCombinerPatterns() finds patterns, this function generates
271 /// the instructions that could replace the original code sequence
276 DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const override;
277 /// AArch64 supports MachineCombiner.
278 bool useMachineCombiner() const override;
279
280 bool expandPostRAPseudo(MachineInstr &MI) const override;
281
282 std::pair<unsigned, unsigned>
283 decomposeMachineOperandsTargetFlags(unsigned TF) const override;
290
292 bool OutlineFromLinkOnceODRs) const override;
293 std::optional<outliner::OutlinedFunction> getOutliningCandidateInfo(
294 std::vector<outliner::Candidate> &RepeatedSequenceLocs) const override;
296 getOutliningTypeImpl(MachineBasicBlock::iterator &MIT, unsigned Flags) const override;
298 std::pair<MachineBasicBlock::iterator, MachineBasicBlock::iterator>>
299 getOutlinableRanges(MachineBasicBlock &MBB, unsigned &Flags) const override;
301 const outliner::OutlinedFunction &OF) const override;
305 outliner::Candidate &C) const override;
307 /// Returns the vector element size (B, H, S or D) of an SVE opcode.
308 uint64_t getElementSizeForOpcode(unsigned Opc) const;
309 /// Returns true if the opcode is for an SVE instruction that sets the
310 /// condition codes as if it's results had been fed to a PTEST instruction
311 /// along with the same general predicate.
312 bool isPTestLikeOpcode(unsigned Opc) const;
313 /// Returns true if the opcode is for an SVE WHILE## instruction.
314 bool isWhileOpcode(unsigned Opc) const;
315 /// Returns true if the instruction has a shift by immediate that can be
316 /// executed in one cycle less.
317 static bool isFalkorShiftExtFast(const MachineInstr &MI);
318 /// Return true if the instructions is a SEH instruciton used for unwinding
319 /// on Windows.
320 static bool isSEHInstruction(const MachineInstr &MI);
321
322 std::optional<RegImmPair> isAddImmediate(const MachineInstr &MI,
323 Register Reg) const override;
324
325 std::optional<ParamLoadedValue>
326 describeLoadedValue(const MachineInstr &MI, Register Reg) const override;
327
328 unsigned int getTailDuplicateSize(CodeGenOpt::Level OptLevel) const override;
329
331 MachineRegisterInfo &MRI) const override;
332
334 int64_t &NumBytes,
335 int64_t &NumPredicateVectors,
336 int64_t &NumDataVectors);
338 int64_t &ByteSized,
339 int64_t &VGSized);
340#define GET_INSTRINFO_HELPER_DECLS
341#include "AArch64GenInstrInfo.inc"
342
343protected:
344 /// If the specific machine instruction is an instruction that moves/copies
345 /// value from one register to another register return destination and source
346 /// registers as machine operands.
347 std::optional<DestSourcePair>
348 isCopyInstrImpl(const MachineInstr &MI) const override;
349
350private:
351 unsigned getInstBundleLength(const MachineInstr &MI) const;
352
353 /// Sets the offsets on outlined instructions in \p MBB which use SP
354 /// so that they will be valid post-outlining.
355 ///
356 /// \param MBB A \p MachineBasicBlock in an outlined function.
357 void fixupPostOutline(MachineBasicBlock &MBB) const;
358
359 void instantiateCondBranch(MachineBasicBlock &MBB, const DebugLoc &DL,
360 MachineBasicBlock *TBB,
361 ArrayRef<MachineOperand> Cond) const;
362 bool substituteCmpToZero(MachineInstr &CmpInstr, unsigned SrcReg,
363 const MachineRegisterInfo &MRI) const;
364 bool removeCmpToZeroOrOne(MachineInstr &CmpInstr, unsigned SrcReg,
365 int CmpValue, const MachineRegisterInfo &MRI) const;
366
367 /// Returns an unused general-purpose register which can be used for
368 /// constructing an outlined call if one exists. Returns 0 otherwise.
369 Register findRegisterToSaveLRTo(outliner::Candidate &C) const;
370
371 /// Remove a ptest of a predicate-generating operation that already sets, or
372 /// can be made to set, the condition codes in an identical manner
373 bool optimizePTestInstr(MachineInstr *PTest, unsigned MaskReg,
374 unsigned PredReg,
375 const MachineRegisterInfo *MRI) const;
376};
377
378struct UsedNZCV {
379 bool N = false;
380 bool Z = false;
381 bool C = false;
382 bool V = false;
383
384 UsedNZCV() = default;
385
386 UsedNZCV &operator|=(const UsedNZCV &UsedFlags) {
387 this->N |= UsedFlags.N;
388 this->Z |= UsedFlags.Z;
389 this->C |= UsedFlags.C;
390 this->V |= UsedFlags.V;
391 return *this;
392 }
393};
394
395/// \returns Conditions flags used after \p CmpInstr in its MachineBB if NZCV
396/// flags are not alive in successors of the same \p CmpInstr and \p MI parent.
397/// \returns std::nullopt otherwise.
398///
399/// Collect instructions using that flags in \p CCUseInstrs if provided.
400std::optional<UsedNZCV>
401examineCFlagsUse(MachineInstr &MI, MachineInstr &CmpInstr,
402 const TargetRegisterInfo &TRI,
403 SmallVectorImpl<MachineInstr *> *CCUseInstrs = nullptr);
404
405/// Return true if there is an instruction /after/ \p DefMI and before \p UseMI
406/// which either reads or clobbers NZCV.
407bool isNZCVTouchedInInstructionRange(const MachineInstr &DefMI,
408 const MachineInstr &UseMI,
409 const TargetRegisterInfo *TRI);
410
411MCCFIInstruction createDefCFA(const TargetRegisterInfo &TRI, unsigned FrameReg,
412 unsigned Reg, const StackOffset &Offset,
413 bool LastAdjustmentWasScalable = true);
414MCCFIInstruction createCFAOffset(const TargetRegisterInfo &MRI, unsigned Reg,
415 const StackOffset &OffsetFromDefCFA);
416
417/// emitFrameOffset - Emit instructions as needed to set DestReg to SrcReg
418/// plus Offset. This is intended to be used from within the prolog/epilog
419/// insertion (PEI) pass, where a virtual scratch register may be allocated
420/// if necessary, to be replaced by the scavenger at the end of PEI.
421void emitFrameOffset(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
422 const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
423 StackOffset Offset, const TargetInstrInfo *TII,
425 bool SetNZCV = false, bool NeedsWinCFI = false,
426 bool *HasWinCFI = nullptr, bool EmitCFAOffset = false,
427 StackOffset InitialOffset = {},
428 unsigned FrameReg = AArch64::SP);
429
430/// rewriteAArch64FrameIndex - Rewrite MI to access 'Offset' bytes from the
431/// FP. Return false if the offset could not be handled directly in MI, and
432/// return the left-over portion by reference.
433bool rewriteAArch64FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
434 unsigned FrameReg, StackOffset &Offset,
435 const AArch64InstrInfo *TII);
436
437/// Use to report the frame offset status in isAArch64FrameOffsetLegal.
439 AArch64FrameOffsetCannotUpdate = 0x0, ///< Offset cannot apply.
440 AArch64FrameOffsetIsLegal = 0x1, ///< Offset is legal.
441 AArch64FrameOffsetCanUpdate = 0x2 ///< Offset can apply, at least partly.
443
444/// Check if the @p Offset is a valid frame offset for @p MI.
445/// The returned value reports the validity of the frame offset for @p MI.
446/// It uses the values defined by AArch64FrameOffsetStatus for that.
447/// If result == AArch64FrameOffsetCannotUpdate, @p MI cannot be updated to
448/// use an offset.eq
449/// If result & AArch64FrameOffsetIsLegal, @p Offset can completely be
450/// rewritten in @p MI.
451/// If result & AArch64FrameOffsetCanUpdate, @p Offset contains the
452/// amount that is off the limit of the legal offset.
453/// If set, @p OutUseUnscaledOp will contain the whether @p MI should be
454/// turned into an unscaled operator, which opcode is in @p OutUnscaledOp.
455/// If set, @p EmittableOffset contains the amount that can be set in @p MI
456/// (possibly with @p OutUnscaledOp if OutUseUnscaledOp is true) and that
457/// is a legal offset.
458int isAArch64FrameOffsetLegal(const MachineInstr &MI, StackOffset &Offset,
459 bool *OutUseUnscaledOp = nullptr,
460 unsigned *OutUnscaledOp = nullptr,
461 int64_t *EmittableOffset = nullptr);
462
463static inline bool isUncondBranchOpcode(int Opc) { return Opc == AArch64::B; }
464
465static inline bool isCondBranchOpcode(int Opc) {
466 switch (Opc) {
467 case AArch64::Bcc:
468 case AArch64::CBZW:
469 case AArch64::CBZX:
470 case AArch64::CBNZW:
471 case AArch64::CBNZX:
472 case AArch64::TBZW:
473 case AArch64::TBZX:
474 case AArch64::TBNZW:
475 case AArch64::TBNZX:
476 return true;
477 default:
478 return false;
479 }
480}
481
482static inline bool isIndirectBranchOpcode(int Opc) {
483 switch (Opc) {
484 case AArch64::BR:
485 case AArch64::BRAA:
486 case AArch64::BRAB:
487 case AArch64::BRAAZ:
488 case AArch64::BRABZ:
489 return true;
490 }
491 return false;
492}
493
494static inline bool isPTrueOpcode(unsigned Opc) {
495 switch (Opc) {
496 case AArch64::PTRUE_B:
497 case AArch64::PTRUE_H:
498 case AArch64::PTRUE_S:
499 case AArch64::PTRUE_D:
500 return true;
501 default:
502 return false;
503 }
504}
505
506/// Return opcode to be used for indirect calls.
507unsigned getBLRCallOpcode(const MachineFunction &MF);
508
509/// Return XPAC opcode to be used for a ptrauth strip using the given key.
510static inline unsigned getXPACOpcodeForKey(AArch64PACKey::ID K) {
511 using namespace AArch64PACKey;
512 switch (K) {
513 case IA: case IB: return AArch64::XPACI;
514 case DA: case DB: return AArch64::XPACD;
515 }
516 llvm_unreachable("Unhandled AArch64PACKey::ID enum");
517}
518
519/// Return AUT opcode to be used for a ptrauth auth using the given key, or its
520/// AUT*Z variant that doesn't take a discriminator operand, using zero instead.
521static inline unsigned getAUTOpcodeForKey(AArch64PACKey::ID K, bool Zero) {
522 using namespace AArch64PACKey;
523 switch (K) {
524 case IA: return Zero ? AArch64::AUTIZA : AArch64::AUTIA;
525 case IB: return Zero ? AArch64::AUTIZB : AArch64::AUTIB;
526 case DA: return Zero ? AArch64::AUTDZA : AArch64::AUTDA;
527 case DB: return Zero ? AArch64::AUTDZB : AArch64::AUTDB;
528 }
529}
530
531/// Return PAC opcode to be used for a ptrauth sign using the given key, or its
532/// PAC*Z variant that doesn't take a discriminator operand, using zero instead.
533static inline unsigned getPACOpcodeForKey(AArch64PACKey::ID K, bool Zero) {
534 using namespace AArch64PACKey;
535 switch (K) {
536 case IA: return Zero ? AArch64::PACIZA : AArch64::PACIA;
537 case IB: return Zero ? AArch64::PACIZB : AArch64::PACIB;
538 case DA: return Zero ? AArch64::PACDZA : AArch64::PACDA;
539 case DB: return Zero ? AArch64::PACDZB : AArch64::PACDB;
540 }
541}
542
543// struct TSFlags {
544#define TSFLAG_ELEMENT_SIZE_TYPE(X) (X) // 3-bits
545#define TSFLAG_DESTRUCTIVE_INST_TYPE(X) ((X) << 3) // 4-bits
546#define TSFLAG_FALSE_LANE_TYPE(X) ((X) << 7) // 2-bits
547#define TSFLAG_INSTR_FLAGS(X) ((X) << 9) // 2-bits
548#define TSFLAG_SME_MATRIX_TYPE(X) ((X) << 11) // 3-bits
549// }
550
551namespace AArch64 {
552
560};
561
574};
575
580};
581
582// NOTE: This is a bit field.
585
595};
596
597#undef TSFLAG_ELEMENT_SIZE_TYPE
598#undef TSFLAG_DESTRUCTIVE_INST_TYPE
599#undef TSFLAG_FALSE_LANE_TYPE
600#undef TSFLAG_INSTR_FLAGS
601#undef TSFLAG_SME_MATRIX_TYPE
602
606
608}
609
610} // end namespace llvm
611
612#endif
unsigned const MachineRegisterInfo * MRI
MachineInstrBuilder & UseMI
MachineInstrBuilder MachineInstrBuilder & DefMI
#define TSFLAG_DESTRUCTIVE_INST_TYPE(X)
#define TSFLAG_SME_MATRIX_TYPE(X)
#define TSFLAG_FALSE_LANE_TYPE(X)
#define TSFLAG_INSTR_FLAGS(X)
#define TSFLAG_ELEMENT_SIZE_TYPE(X)
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MachineBasicBlock MachineBasicBlock::iterator MBBI
SmallVector< MachineOperand, 4 > Cond
const HexagonInstrInfo * TII
IRTranslator LLVM IR MI
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
unsigned Reg
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
@ Flags
Definition: TextStubV5.cpp:93
void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, Register DstReg, ArrayRef< MachineOperand > Cond, Register TrueReg, Register FalseReg) const override
static bool isQForm(const MachineInstr &MI)
Returns whether the instruction is in Q form (128 bit operands)
static void decomposeStackOffsetForFrameOffsets(const StackOffset &Offset, int64_t &NumBytes, int64_t &NumPredicateVectors, int64_t &NumDataVectors)
Returns the offset in parts to which this frame offset can be decomposed for the purpose of describin...
static bool isFPRCopy(const MachineInstr &MI)
Does this instruction rename an FPR without modifying bits?
bool isThroughputPattern(MachineCombinerPattern Pattern) const override
Return true when a code sequence can improve throughput.
std::optional< DestSourcePair > isCopyInstrImpl(const MachineInstr &MI) const override
If the specific machine instruction is an instruction that moves/copies value from one register to an...
static int getMemScale(const MachineInstr &MI)
MachineBasicBlock * getBranchDestBlock(const MachineInstr &MI) const override
std::optional< RegImmPair > isAddImmediate(const MachineInstr &MI, Register Reg) const override
bool isSubregFoldable() const override
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
GetInstSize - Return the number of bytes of code the specified instruction may be.
bool shouldClusterMemOps(ArrayRef< const MachineOperand * > BaseOps1, ArrayRef< const MachineOperand * > BaseOps2, unsigned NumLoads, unsigned NumBytes) const override
Detect opportunities for ldp/stp formation.
bool getMemOperandWithOffsetWidth(const MachineInstr &MI, const MachineOperand *&BaseOp, int64_t &Offset, bool &OffsetIsScalable, unsigned &Width, const TargetRegisterInfo *TRI) const
If OffsetIsScalable is set to 'true', the offset is scaled by vscale.
uint64_t getElementSizeForOpcode(unsigned Opc) const
Returns the vector element size (B, H, S or D) of an SVE opcode.
outliner::InstrType getOutliningTypeImpl(MachineBasicBlock::iterator &MIT, unsigned Flags) const override
bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb) const override
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
static bool isGPRCopy(const MachineInstr &MI)
Does this instruction rename a GPR without modifying bits?
static unsigned convertToFlagSettingOpc(unsigned Opc)
Return the opcode that set flags when possible.
bool isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const override
bool canInsertSelect(const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, Register, Register, Register, int &, int &, int &) const override
static const MachineOperand & getLdStOffsetOp(const MachineInstr &MI)
Returns the the immediate offset operator of a load/store.
bool isCoalescableExtInstr(const MachineInstr &MI, Register &SrcReg, Register &DstReg, unsigned &SubIdx) const override
bool isWhileOpcode(unsigned Opc) const
Returns true if the opcode is for an SVE WHILE## instruction.
static std::optional< unsigned > getUnscaledLdSt(unsigned Opc)
Returns the unscaled load/store for the scaled load/store opcode, if there is a corresponding unscale...
static bool hasUnscaledLdStOffset(unsigned Opc)
Return true if it has an unscaled load/store offset.
static bool hasUnscaledLdStOffset(MachineInstr &MI)
static bool isPreLdSt(const MachineInstr &MI)
Returns whether the instruction is a pre-indexed load/store.
MachineBasicBlock::iterator insertOutlinedCall(Module &M, MachineBasicBlock &MBB, MachineBasicBlock::iterator &It, MachineFunction &MF, outliner::Candidate &C) const override
std::optional< ExtAddrMode > getAddrModeFromMemoryOp(const MachineInstr &MemI, const TargetRegisterInfo *TRI) const override
bool analyzeBranchPredicate(MachineBasicBlock &MBB, MachineBranchPredicate &MBP, bool AllowModify) const override
static bool isSEHInstruction(const MachineInstr &MI)
Return true if the instructions is a SEH instruciton used for unwinding on Windows.
SmallVector< std::pair< MachineBasicBlock::iterator, MachineBasicBlock::iterator > > getOutlinableRanges(MachineBasicBlock &MBB, unsigned &Flags) const override
static bool isPairableLdStInst(const MachineInstr &MI)
Return true if pairing the given load or store may be paired with another.
const AArch64RegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
static bool isPreSt(const MachineInstr &MI)
Returns whether the instruction is a pre-indexed store.
MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const override
static bool isPairedLdSt(const MachineInstr &MI)
Returns whether the instruction is a paired load/store.
bool useMachineCombiner() const override
AArch64 supports MachineCombiner.
ArrayRef< std::pair< MachineMemOperand::Flags, const char * > > getSerializableMachineMemOperandTargetFlags() const override
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
bool isExtendLikelyToBeFolded(MachineInstr &ExtMI, MachineRegisterInfo &MRI) const override
static bool isFalkorShiftExtFast(const MachineInstr &MI)
Returns true if the instruction has a shift by immediate that can be executed in one cycle less.
std::optional< ParamLoadedValue > describeLoadedValue(const MachineInstr &MI, Register Reg) const override
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
static bool isStridedAccess(const MachineInstr &MI)
Return true if the given load or store is a strided memory access.
void genAlternativeCodeSequence(MachineInstr &Root, MachineCombinerPattern Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, DenseMap< unsigned, unsigned > &InstrIdxForVirtReg) const override
When getMachineCombinerPatterns() finds patterns, this function generates the instructions that could...
bool expandPostRAPseudo(MachineInstr &MI) const override
bool isFunctionSafeToOutlineFrom(MachineFunction &MF, bool OutlineFromLinkOnceODRs) const override
bool getMemOperandsWithOffsetWidth(const MachineInstr &MI, SmallVectorImpl< const MachineOperand * > &BaseOps, int64_t &Offset, bool &OffsetIsScalable, unsigned &Width, const TargetRegisterInfo *TRI) const override
static bool isFpOrNEON(const MachineInstr &MI)
Returns whether the instruction is FP or NEON.
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
bool shouldOutlineFromFunctionByDefault(MachineFunction &MF) const override
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
void copyGPRRegTuple(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc, unsigned Opcode, unsigned ZeroReg, llvm::ArrayRef< unsigned > Indices) const
void buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF, const outliner::OutlinedFunction &OF) const override
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
MachineOperand & getMemOpBaseRegImmOfsOffsetOperand(MachineInstr &LdSt) const
Return the immediate offset of the base register in a load/store LdSt.
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override
static bool isLdStPairSuppressed(const MachineInstr &MI)
Return true if pairing the given load or store is hinted to be unprofitable.
static bool getMemOpInfo(unsigned Opcode, TypeSize &Scale, unsigned &Width, int64_t &MinOffset, int64_t &MaxOffset)
Returns true if opcode Opc is a memory operation.
bool isAssociativeAndCommutative(const MachineInstr &Inst, bool Invert) const override
Return true when Inst is associative and commutative so that it can be reassociated.
bool isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int64_t CmpMask, int64_t CmpValue, const MachineRegisterInfo *MRI) const override
optimizeCompareInstr - Convert the instruction supplying the argument to the comparison into one that...
std::optional< outliner::OutlinedFunction > getOutliningCandidateInfo(std::vector< outliner::Candidate > &RepeatedSequenceLocs) const override
bool getMachineCombinerPatterns(MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &Patterns, bool DoRegPressureReduce) const override
Return true when there is potentially a faster code sequence for an instruction chain ending in Root.
static unsigned getLoadStoreImmIdx(unsigned Opc)
Returns the index for the immediate for a given instruction.
static bool isGPRZero(const MachineInstr &MI)
Does this instruction set its full destination register to zero?
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
bool analyzeCompare(const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int64_t &CmpMask, int64_t &CmpValue) const override
analyzeCompare - For a comparison instruction, return the source registers in SrcReg and SrcReg2,...
bool isAsCheapAsAMove(const MachineInstr &MI) const override
static void suppressLdStPair(MachineInstr &MI)
Hint that pairing the given load or store is unprofitable.
static bool isPreLd(const MachineInstr &MI)
Returns whether the instruction is a pre-indexed load.
ArrayRef< std::pair< unsigned, const char * > > getSerializableBitmaskMachineOperandTargetFlags() const override
void copyPhysRegTuple(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc, unsigned Opcode, llvm::ArrayRef< unsigned > Indices) const
unsigned int getTailDuplicateSize(CodeGenOpt::Level OptLevel) const override
bool optimizeCondBranch(MachineInstr &MI) const override
Replace csincr-branch sequence by simple conditional branch.
static int getMemScale(unsigned Opc)
Scaling factor for (scaled or unscaled) load or store.
bool isCandidateToMergeOrPair(const MachineInstr &MI) const
Return true if this is a load/store that can be potentially paired/merged.
MCInst getNop() const override
static const MachineOperand & getLdStBaseOp(const MachineInstr &MI)
Returns the base register operator of a load/store.
bool isPTestLikeOpcode(unsigned Opc) const
Returns true if the opcode is for an SVE instruction that sets the condition codes as if it's results...
static void decomposeStackOffsetForDwarfOffsets(const StackOffset &Offset, int64_t &ByteSized, int64_t &VGSized)
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
A debug info location.
Definition: DebugLoc.h:33
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24
MachineInstrBundleIterator< MachineInstr > iterator
Representation of each machine instruction.
Definition: MachineInstr.h:68
Flags
Flags values. These may be or'd together.
MachineOperand class - Representation of each machine instruction operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:577
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1200
StackOffset holds a fixed and a scalable offset in bytes.
Definition: TypeSize.h:36
virtual MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const
Target-dependent implementation for foldMemoryOperand.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
int getSVERevInstr(uint16_t Opcode)
int getSMEPseudoMap(uint16_t Opcode)
static const uint64_t InstrFlagIsWhile
static const uint64_t InstrFlagIsPTestLike
int getSVEPseudoMap(uint16_t Opcode)
int getSVENonRevInstr(uint16_t Opcode)
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
Level
Code generation optimization level.
Definition: CodeGen.h:57
InstrType
Represents how an instruction should be mapped by the outliner.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:440
static bool isCondBranchOpcode(int Opc)
MCCFIInstruction createDefCFA(const TargetRegisterInfo &TRI, unsigned FrameReg, unsigned Reg, const StackOffset &Offset, bool LastAdjustmentWasScalable=true)
static bool isPTrueOpcode(unsigned Opc)
int isAArch64FrameOffsetLegal(const MachineInstr &MI, StackOffset &Offset, bool *OutUseUnscaledOp=nullptr, unsigned *OutUnscaledOp=nullptr, int64_t *EmittableOffset=nullptr)
Check if the Offset is a valid frame offset for MI.
static bool isIndirectBranchOpcode(int Opc)
static unsigned getXPACOpcodeForKey(AArch64PACKey::ID K)
Return XPAC opcode to be used for a ptrauth strip using the given key.
MCCFIInstruction createCFAOffset(const TargetRegisterInfo &MRI, unsigned Reg, const StackOffset &OffsetFromDefCFA)
unsigned getBLRCallOpcode(const MachineFunction &MF)
Return opcode to be used for indirect calls.
AArch64FrameOffsetStatus
Use to report the frame offset status in isAArch64FrameOffsetLegal.
@ AArch64FrameOffsetIsLegal
Offset is legal.
@ AArch64FrameOffsetCanUpdate
Offset can apply, at least partly.
@ AArch64FrameOffsetCannotUpdate
Offset cannot apply.
void emitFrameOffset(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, StackOffset Offset, const TargetInstrInfo *TII, MachineInstr::MIFlag=MachineInstr::NoFlags, bool SetNZCV=false, bool NeedsWinCFI=false, bool *HasWinCFI=nullptr, bool EmitCFAOffset=false, StackOffset InitialOffset={}, unsigned FrameReg=AArch64::SP)
emitFrameOffset - Emit instructions as needed to set DestReg to SrcReg plus Offset.
MachineCombinerPattern
These are instruction patterns matched by the machine combiner pass.
std::optional< UsedNZCV > examineCFlagsUse(MachineInstr &MI, MachineInstr &CmpInstr, const TargetRegisterInfo &TRI, SmallVectorImpl< MachineInstr * > *CCUseInstrs=nullptr)
static bool isUncondBranchOpcode(int Opc)
static unsigned getPACOpcodeForKey(AArch64PACKey::ID K, bool Zero)
Return PAC opcode to be used for a ptrauth sign using the given key, or its PAC*Z variant that doesn'...
bool rewriteAArch64FrameIndex(MachineInstr &MI, unsigned FrameRegIdx, unsigned FrameReg, StackOffset &Offset, const AArch64InstrInfo *TII)
rewriteAArch64FrameIndex - Rewrite MI to access 'Offset' bytes from the FP.
static const MachineMemOperand::Flags MOSuppressPair
bool isNZCVTouchedInInstructionRange(const MachineInstr &DefMI, const MachineInstr &UseMI, const TargetRegisterInfo *TRI)
Return true if there is an instruction /after/ DefMI and before UseMI which either reads or clobbers ...
static const MachineMemOperand::Flags MOStridedAccess
static unsigned getAUTOpcodeForKey(AArch64PACKey::ID K, bool Zero)
Return AUT opcode to be used for a ptrauth auth using the given key, or its AUT*Z variant that doesn'...
UsedNZCV & operator|=(const UsedNZCV &UsedFlags)
UsedNZCV()=default
An individual sequence of instructions to be replaced with a call to an outlined function.
The information necessary to create an outlined function for some class of candidate.