LLVM  14.0.0git
AArch64InstrInfo.h
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1 //===- AArch64InstrInfo.h - AArch64 Instruction Information -----*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the AArch64 implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64INSTRINFO_H
14 #define LLVM_LIB_TARGET_AARCH64_AARCH64INSTRINFO_H
15 
16 #include "AArch64.h"
17 #include "AArch64RegisterInfo.h"
18 #include "llvm/ADT/Optional.h"
21 #include "llvm/Support/TypeSize.h"
22 
23 #define GET_INSTRINFO_HEADER
24 #include "AArch64GenInstrInfo.inc"
25 
26 namespace llvm {
27 
28 class AArch64Subtarget;
29 
34 
35 #define FALKOR_STRIDED_ACCESS_MD "falkor.strided.access"
36 
37 class AArch64InstrInfo final : public AArch64GenInstrInfo {
38  const AArch64RegisterInfo RI;
39  const AArch64Subtarget &Subtarget;
40 
41 public:
42  explicit AArch64InstrInfo(const AArch64Subtarget &STI);
43 
44  /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
45  /// such, whenever a client has an instance of instruction info, it should
46  /// always be able to get register info as well (through this method).
47  const AArch64RegisterInfo &getRegisterInfo() const { return RI; }
48 
49  unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
50 
51  bool isAsCheapAsAMove(const MachineInstr &MI) const override;
52 
53  bool isCoalescableExtInstr(const MachineInstr &MI, Register &SrcReg,
54  Register &DstReg, unsigned &SubIdx) const override;
55 
56  bool
58  const MachineInstr &MIb) const override;
59 
60  unsigned isLoadFromStackSlot(const MachineInstr &MI,
61  int &FrameIndex) const override;
62  unsigned isStoreToStackSlot(const MachineInstr &MI,
63  int &FrameIndex) const override;
64 
65  /// Does this instruction set its full destination register to zero?
66  static bool isGPRZero(const MachineInstr &MI);
67 
68  /// Does this instruction rename a GPR without modifying bits?
69  static bool isGPRCopy(const MachineInstr &MI);
70 
71  /// Does this instruction rename an FPR without modifying bits?
72  static bool isFPRCopy(const MachineInstr &MI);
73 
74  /// Return true if pairing the given load or store is hinted to be
75  /// unprofitable.
76  static bool isLdStPairSuppressed(const MachineInstr &MI);
77 
78  /// Return true if the given load or store is a strided memory access.
79  static bool isStridedAccess(const MachineInstr &MI);
80 
81  /// Return true if it has an unscaled load/store offset.
82  static bool hasUnscaledLdStOffset(unsigned Opc);
84  return hasUnscaledLdStOffset(MI.getOpcode());
85  }
86 
87  /// Returns the unscaled load/store for the scaled load/store opcode,
88  /// if there is a corresponding unscaled variant available.
89  static Optional<unsigned> getUnscaledLdSt(unsigned Opc);
90 
91  /// Scaling factor for (scaled or unscaled) load or store.
92  static int getMemScale(unsigned Opc);
93  static int getMemScale(const MachineInstr &MI) {
94  return getMemScale(MI.getOpcode());
95  }
96 
97  /// Returns whether the instruction is a pre-indexed load.
98  static bool isPreLd(const MachineInstr &MI);
99 
100  /// Returns whether the instruction is a pre-indexed store.
101  static bool isPreSt(const MachineInstr &MI);
102 
103  /// Returns whether the instruction is a pre-indexed load/store.
104  static bool isPreLdSt(const MachineInstr &MI);
105 
106  /// Returns the index for the immediate for a given instruction.
107  static unsigned getLoadStoreImmIdx(unsigned Opc);
108 
109  /// Return true if pairing the given load or store may be paired with another.
110  static bool isPairableLdStInst(const MachineInstr &MI);
111 
112  /// Return the opcode that set flags when possible. The caller is
113  /// responsible for ensuring the opc has a flag setting equivalent.
114  static unsigned convertToFlagSettingOpc(unsigned Opc, bool &Is64Bit);
115 
116  /// Return true if this is a load/store that can be potentially paired/merged.
117  bool isCandidateToMergeOrPair(const MachineInstr &MI) const;
118 
119  /// Hint that pairing the given load or store is unprofitable.
120  static void suppressLdStPair(MachineInstr &MI);
121 
124  const TargetRegisterInfo *TRI) const override;
125 
128  int64_t &Offset, bool &OffsetIsScalable, unsigned &Width,
129  const TargetRegisterInfo *TRI) const override;
130 
131  /// If \p OffsetIsScalable is set to 'true', the offset is scaled by `vscale`.
132  /// This is true for some SVE instructions like ldr/str that have a
133  /// 'reg + imm' addressing mode where the immediate is an index to the
134  /// scalable vector located at 'reg + imm * vscale x #bytes'.
136  const MachineOperand *&BaseOp,
137  int64_t &Offset, bool &OffsetIsScalable,
138  unsigned &Width,
139  const TargetRegisterInfo *TRI) const;
140 
141  /// Return the immediate offset of the base register in a load/store \p LdSt.
143 
144  /// Returns true if opcode \p Opc is a memory operation. If it is, set
145  /// \p Scale, \p Width, \p MinOffset, and \p MaxOffset accordingly.
146  ///
147  /// For unscaled instructions, \p Scale is set to 1.
148  static bool getMemOpInfo(unsigned Opcode, TypeSize &Scale, unsigned &Width,
149  int64_t &MinOffset, int64_t &MaxOffset);
150 
153  unsigned NumLoads, unsigned NumBytes) const override;
154 
156  const DebugLoc &DL, MCRegister DestReg,
157  MCRegister SrcReg, bool KillSrc, unsigned Opcode,
158  llvm::ArrayRef<unsigned> Indices) const;
160  DebugLoc DL, unsigned DestReg, unsigned SrcReg,
161  bool KillSrc, unsigned Opcode, unsigned ZeroReg,
162  llvm::ArrayRef<unsigned> Indices) const;
164  const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
165  bool KillSrc) const override;
166 
169  bool isKill, int FrameIndex,
170  const TargetRegisterClass *RC,
171  const TargetRegisterInfo *TRI) const override;
172 
175  int FrameIndex, const TargetRegisterClass *RC,
176  const TargetRegisterInfo *TRI) const override;
177 
178  // This tells target independent code that it is okay to pass instructions
179  // with subreg operands to foldMemoryOperandImpl.
180  bool isSubregFoldable() const override { return true; }
181 
183  MachineInstr *
185  ArrayRef<unsigned> Ops,
187  LiveIntervals *LIS = nullptr,
188  VirtRegMap *VRM = nullptr) const override;
189 
190  /// \returns true if a branch from an instruction with opcode \p BranchOpc
191  /// bytes is capable of jumping to a position \p BrOffset bytes away.
192  bool isBranchOffsetInRange(unsigned BranchOpc,
193  int64_t BrOffset) const override;
194 
195  MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override;
196 
198  MachineBasicBlock *&FBB,
200  bool AllowModify = false) const override;
202  MachineBranchPredicate &MBP,
203  bool AllowModify) const override;
205  int *BytesRemoved = nullptr) const override;
208  const DebugLoc &DL,
209  int *BytesAdded = nullptr) const override;
210  bool
213  Register, Register, Register, int &, int &,
214  int &) const override;
216  const DebugLoc &DL, Register DstReg,
218  Register FalseReg) const override;
219  MCInst getNop() const override;
220 
222  const MachineBasicBlock *MBB,
223  const MachineFunction &MF) const override;
224 
225  /// analyzeCompare - For a comparison instruction, return the source registers
226  /// in SrcReg and SrcReg2, and the value it compares against in CmpValue.
227  /// Return true if the comparison instruction can be analyzed.
228  bool analyzeCompare(const MachineInstr &MI, Register &SrcReg,
229  Register &SrcReg2, int64_t &CmpMask,
230  int64_t &CmpValue) const override;
231  /// optimizeCompareInstr - Convert the instruction supplying the argument to
232  /// the comparison into one that sets the zero bit in the flags register.
233  bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
234  Register SrcReg2, int64_t CmpMask, int64_t CmpValue,
235  const MachineRegisterInfo *MRI) const override;
236  bool optimizeCondBranch(MachineInstr &MI) const override;
237 
238  /// Return true when a code sequence can improve throughput. It
239  /// should be called only for instructions in loops.
240  /// \param Pattern - combiner pattern
242  /// Return true when there is potentially a faster code sequence
243  /// for an instruction chain ending in ``Root``. All potential patterns are
244  /// listed in the ``Patterns`` array.
245  bool
248  bool DoRegPressureReduce) const override;
249  /// Return true when Inst is associative and commutative so that it can be
250  /// reassociated.
251  bool isAssociativeAndCommutative(const MachineInstr &Inst) const override;
252  /// When getMachineCombinerPatterns() finds patterns, this function generates
253  /// the instructions that could replace the original code sequence
258  DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const override;
259  /// AArch64 supports MachineCombiner.
260  bool useMachineCombiner() const override;
261 
262  bool expandPostRAPseudo(MachineInstr &MI) const override;
263 
264  std::pair<unsigned, unsigned>
265  decomposeMachineOperandsTargetFlags(unsigned TF) const override;
272 
274  bool OutlineFromLinkOnceODRs) const override;
276  std::vector<outliner::Candidate> &RepeatedSequenceLocs) const override;
278  getOutliningType(MachineBasicBlock::iterator &MIT, unsigned Flags) const override;
280  unsigned &Flags) const override;
282  const outliner::OutlinedFunction &OF) const override;
286  const outliner::Candidate &C) const override;
287  bool shouldOutlineFromFunctionByDefault(MachineFunction &MF) const override;
288  /// Returns the vector element size (B, H, S or D) of an SVE opcode.
289  uint64_t getElementSizeForOpcode(unsigned Opc) const;
290  /// Returns true if the opcode is for an SVE instruction that sets the
291  /// condition codes as if it's results had been fed to a PTEST instruction
292  /// along with the same general predicate.
293  bool isPTestLikeOpcode(unsigned Opc) const;
294  /// Returns true if the opcode is for an SVE WHILE## instruction.
295  bool isWhileOpcode(unsigned Opc) const;
296  /// Returns true if the instruction has a shift by immediate that can be
297  /// executed in one cycle less.
298  static bool isFalkorShiftExtFast(const MachineInstr &MI);
299  /// Return true if the instructions is a SEH instruciton used for unwinding
300  /// on Windows.
301  static bool isSEHInstruction(const MachineInstr &MI);
302 
304  Register Reg) const override;
305 
307  Register Reg) const override;
308 
309  unsigned int getTailDuplicateSize(CodeGenOpt::Level OptLevel) const override;
310 
312  MachineRegisterInfo &MRI) const override;
313 
315  int64_t &NumBytes,
316  int64_t &NumPredicateVectors,
317  int64_t &NumDataVectors);
319  int64_t &ByteSized,
320  int64_t &VGSized);
321 #define GET_INSTRINFO_HELPER_DECLS
322 #include "AArch64GenInstrInfo.inc"
323 
324 protected:
325  /// If the specific machine instruction is an instruction that moves/copies
326  /// value from one register to another register return destination and source
327  /// registers as machine operands.
328  Optional<DestSourcePair>
329  isCopyInstrImpl(const MachineInstr &MI) const override;
330 
331 private:
332  unsigned getInstBundleLength(const MachineInstr &MI) const;
333 
334  /// Sets the offsets on outlined instructions in \p MBB which use SP
335  /// so that they will be valid post-outlining.
336  ///
337  /// \param MBB A \p MachineBasicBlock in an outlined function.
338  void fixupPostOutline(MachineBasicBlock &MBB) const;
339 
340  void instantiateCondBranch(MachineBasicBlock &MBB, const DebugLoc &DL,
341  MachineBasicBlock *TBB,
342  ArrayRef<MachineOperand> Cond) const;
343  bool substituteCmpToZero(MachineInstr &CmpInstr, unsigned SrcReg,
344  const MachineRegisterInfo &MRI) const;
345  bool removeCmpToZeroOrOne(MachineInstr &CmpInstr, unsigned SrcReg,
346  int CmpValue, const MachineRegisterInfo &MRI) const;
347 
348  /// Returns an unused general-purpose register which can be used for
349  /// constructing an outlined call if one exists. Returns 0 otherwise.
350  unsigned findRegisterToSaveLRTo(const outliner::Candidate &C) const;
351 
352  /// Remove a ptest of a predicate-generating operation that already sets, or
353  /// can be made to set, the condition codes in an identical manner
354  bool optimizePTestInstr(MachineInstr *PTest, unsigned MaskReg,
355  unsigned PredReg,
356  const MachineRegisterInfo *MRI) const;
357 };
358 
359 /// Return true if there is an instruction /after/ \p DefMI and before \p UseMI
360 /// which either reads or clobbers NZCV.
361 bool isNZCVTouchedInInstructionRange(const MachineInstr &DefMI,
362  const MachineInstr &UseMI,
363  const TargetRegisterInfo *TRI);
364 
365 /// emitFrameOffset - Emit instructions as needed to set DestReg to SrcReg
366 /// plus Offset. This is intended to be used from within the prolog/epilog
367 /// insertion (PEI) pass, where a virtual scratch register may be allocated
368 /// if necessary, to be replaced by the scavenger at the end of PEI.
369 void emitFrameOffset(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
370  const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
371  StackOffset Offset, const TargetInstrInfo *TII,
373  bool SetNZCV = false, bool NeedsWinCFI = false,
374  bool *HasWinCFI = nullptr);
375 
376 /// rewriteAArch64FrameIndex - Rewrite MI to access 'Offset' bytes from the
377 /// FP. Return false if the offset could not be handled directly in MI, and
378 /// return the left-over portion by reference.
379 bool rewriteAArch64FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
380  unsigned FrameReg, StackOffset &Offset,
381  const AArch64InstrInfo *TII);
382 
383 /// Use to report the frame offset status in isAArch64FrameOffsetLegal.
385  AArch64FrameOffsetCannotUpdate = 0x0, ///< Offset cannot apply.
386  AArch64FrameOffsetIsLegal = 0x1, ///< Offset is legal.
387  AArch64FrameOffsetCanUpdate = 0x2 ///< Offset can apply, at least partly.
388 };
389 
390 /// Check if the @p Offset is a valid frame offset for @p MI.
391 /// The returned value reports the validity of the frame offset for @p MI.
392 /// It uses the values defined by AArch64FrameOffsetStatus for that.
393 /// If result == AArch64FrameOffsetCannotUpdate, @p MI cannot be updated to
394 /// use an offset.eq
395 /// If result & AArch64FrameOffsetIsLegal, @p Offset can completely be
396 /// rewritten in @p MI.
397 /// If result & AArch64FrameOffsetCanUpdate, @p Offset contains the
398 /// amount that is off the limit of the legal offset.
399 /// If set, @p OutUseUnscaledOp will contain the whether @p MI should be
400 /// turned into an unscaled operator, which opcode is in @p OutUnscaledOp.
401 /// If set, @p EmittableOffset contains the amount that can be set in @p MI
402 /// (possibly with @p OutUnscaledOp if OutUseUnscaledOp is true) and that
403 /// is a legal offset.
404 int isAArch64FrameOffsetLegal(const MachineInstr &MI, StackOffset &Offset,
405  bool *OutUseUnscaledOp = nullptr,
406  unsigned *OutUnscaledOp = nullptr,
407  int64_t *EmittableOffset = nullptr);
408 
409 static inline bool isUncondBranchOpcode(int Opc) { return Opc == AArch64::B; }
410 
411 static inline bool isCondBranchOpcode(int Opc) {
412  switch (Opc) {
413  case AArch64::Bcc:
414  case AArch64::CBZW:
415  case AArch64::CBZX:
416  case AArch64::CBNZW:
417  case AArch64::CBNZX:
418  case AArch64::TBZW:
419  case AArch64::TBZX:
420  case AArch64::TBNZW:
421  case AArch64::TBNZX:
422  return true;
423  default:
424  return false;
425  }
426 }
427 
428 static inline bool isIndirectBranchOpcode(int Opc) {
429  switch (Opc) {
430  case AArch64::BR:
431  case AArch64::BRAA:
432  case AArch64::BRAB:
433  case AArch64::BRAAZ:
434  case AArch64::BRABZ:
435  return true;
436  }
437  return false;
438 }
439 
440 static inline bool isPTrueOpcode(unsigned Opc) {
441  switch (Opc) {
442  case AArch64::PTRUE_B:
443  case AArch64::PTRUE_H:
444  case AArch64::PTRUE_S:
445  case AArch64::PTRUE_D:
446  return true;
447  default:
448  return false;
449  }
450 }
451 
452 /// Return opcode to be used for indirect calls.
453 unsigned getBLRCallOpcode(const MachineFunction &MF);
454 
455 // struct TSFlags {
456 #define TSFLAG_ELEMENT_SIZE_TYPE(X) (X) // 3-bits
457 #define TSFLAG_DESTRUCTIVE_INST_TYPE(X) ((X) << 3) // 4-bits
458 #define TSFLAG_FALSE_LANE_TYPE(X) ((X) << 7) // 2-bits
459 #define TSFLAG_INSTR_FLAGS(X) ((X) << 9) // 2-bits
460 // }
461 
462 namespace AArch64 {
463 
471 };
472 
485 };
486 
491 };
492 
493 // NOTE: This is a bit field.
496 
497 #undef TSFLAG_ELEMENT_SIZE_TYPE
498 #undef TSFLAG_DESTRUCTIVE_INST_TYPE
499 #undef TSFLAG_FALSE_LANE_TYPE
500 #undef TSFLAG_INSTR_FLAGS
501 
502 int getSVEPseudoMap(uint16_t Opcode);
503 int getSVERevInstr(uint16_t Opcode);
504 int getSVENonRevInstr(uint16_t Opcode);
505 }
506 
507 } // end namespace llvm
508 
509 #endif
llvm::AArch64InstrInfo::getTailDuplicateSize
unsigned int getTailDuplicateSize(CodeGenOpt::Level OptLevel) const override
Definition: AArch64InstrInfo.cpp:7743
llvm::AArch64::DestructiveInstType
DestructiveInstType
Definition: AArch64InstrInfo.h:473
llvm::AArch64InstrInfo::describeLoadedValue
Optional< ParamLoadedValue > describeLoadedValue(const MachineInstr &MI, Register Reg) const override
Definition: AArch64InstrInfo.cpp:7683
llvm::AArch64::ElementSizeNone
@ ElementSizeNone
Definition: AArch64InstrInfo.h:466
AArch64RegisterInfo.h
llvm::AArch64InstrInfo::suppressLdStPair
static void suppressLdStPair(MachineInstr &MI)
Hint that pairing the given load or store is unprofitable.
Definition: AArch64InstrInfo.cpp:2162
llvm::AArch64InstrInfo::isThroughputPattern
bool isThroughputPattern(MachineCombinerPattern Pattern) const override
Return true when a code sequence can improve throughput.
Definition: AArch64InstrInfo.cpp:4973
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:105
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AllocatorList.h:23
Reg
unsigned Reg
Definition: MachineSink.cpp:1563
AArch64.h
UseMI
MachineInstrBuilder & UseMI
Definition: AArch64ExpandPseudoInsts.cpp:102
llvm::AArch64InstrInfo::copyPhysReg
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
Definition: AArch64InstrInfo.cpp:3321
Optional.h
TSFLAG_DESTRUCTIVE_INST_TYPE
#define TSFLAG_DESTRUCTIVE_INST_TYPE(X)
Definition: AArch64InstrInfo.h:457
llvm::AArch64InstrInfo::expandPostRAPseudo
bool expandPostRAPseudo(MachineInstr &MI) const override
Definition: AArch64InstrInfo.cpp:1864
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
llvm::AArch64InstrInfo::getInstSizeInBytes
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
GetInstSize - Return the number of bytes of code the specified instruction may be.
Definition: AArch64InstrInfo.cpp:77
llvm::AArch64::FalseLanesZero
@ FalseLanesZero
Definition: AArch64InstrInfo.h:489
llvm::AArch64InstrInfo::getAddrModeFromMemoryOp
Optional< ExtAddrMode > getAddrModeFromMemoryOp(const MachineInstr &MemI, const TargetRegisterInfo *TRI) const override
Definition: AArch64InstrInfo.cpp:2563
llvm::AArch64::ElementSizeS
@ ElementSizeS
Definition: AArch64InstrInfo.h:469
llvm::AArch64FrameOffsetCanUpdate
@ AArch64FrameOffsetCanUpdate
Offset can apply, at least partly.
Definition: AArch64InstrInfo.h:387
llvm::AArch64InstrInfo::getMemOperandWithOffsetWidth
bool getMemOperandWithOffsetWidth(const MachineInstr &MI, const MachineOperand *&BaseOp, int64_t &Offset, bool &OffsetIsScalable, unsigned &Width, const TargetRegisterInfo *TRI) const
If OffsetIsScalable is set to 'true', the offset is scaled by vscale.
Definition: AArch64InstrInfo.cpp:2581
TypeSize.h
llvm::AArch64::InstrFlagIsPTestLike
static const uint64_t InstrFlagIsPTestLike
Definition: AArch64InstrInfo.h:495
llvm::AArch64InstrInfo::getMemOperandsWithOffsetWidth
bool getMemOperandsWithOffsetWidth(const MachineInstr &MI, SmallVectorImpl< const MachineOperand * > &BaseOps, int64_t &Offset, bool &OffsetIsScalable, unsigned &Width, const TargetRegisterInfo *TRI) const override
Definition: AArch64InstrInfo.cpp:2547
llvm::VirtRegMap
Definition: VirtRegMap.h:33
llvm::getBLRCallOpcode
unsigned getBLRCallOpcode(const MachineFunction &MF)
Return opcode to be used for indirect calls.
Definition: AArch64InstrInfo.cpp:7747
llvm::AArch64InstrInfo::isPreLdSt
static bool isPreLdSt(const MachineInstr &MI)
Returns whether the instruction is a pre-indexed load/store.
Definition: AArch64InstrInfo.cpp:3115
llvm::AArch64InstrInfo::getMemScale
static int getMemScale(const MachineInstr &MI)
Definition: AArch64InstrInfo.h:93
llvm::AArch64InstrInfo::getSerializableDirectMachineOperandTargetFlags
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
Definition: AArch64InstrInfo.cpp:6411
llvm::MachineMemOperand::MOTargetFlag2
@ MOTargetFlag2
Definition: MachineMemOperand.h:152
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:233
llvm::outliner::InstrType
InstrType
Represents how an instruction should be mapped by the outliner.
Definition: MachineOutliner.h:34
llvm::AArch64InstrInfo::getElementSizeForOpcode
uint64_t getElementSizeForOpcode(unsigned Opc) const
Returns the vector element size (B, H, S or D) of an SVE opcode.
Definition: AArch64InstrInfo.cpp:7730
TargetInstrInfo.h
llvm::AArch64InstrInfo::areMemAccessesTriviallyDisjoint
bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb) const override
Definition: AArch64InstrInfo.cpp:1053
llvm::isCondBranchOpcode
static bool isCondBranchOpcode(int Opc)
Definition: AArch64InstrInfo.h:411
llvm::rewriteAArch64FrameIndex
bool rewriteAArch64FrameIndex(MachineInstr &MI, unsigned FrameRegIdx, unsigned FrameReg, StackOffset &Offset, const AArch64InstrInfo *TII)
rewriteAArch64FrameIndex - Rewrite MI to access 'Offset' bytes from the FP.
Definition: AArch64InstrInfo.cpp:4416
llvm::AArch64::ElementSizeB
@ ElementSizeB
Definition: AArch64InstrInfo.h:467
llvm::AArch64::DestructiveTernaryCommWithRev
@ DestructiveTernaryCommWithRev
Definition: AArch64InstrInfo.h:483
llvm::Optional< unsigned >
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:80
llvm::isUncondBranchOpcode
static bool isUncondBranchOpcode(int Opc)
Definition: AArch64InstrInfo.h:409
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
llvm::outliner::OutlinedFunction
The information necessary to create an outlined function for some class of candidate.
Definition: MachineOutliner.h:164
llvm::AArch64InstrInfo::copyGPRRegTuple
void copyGPRRegTuple(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc, unsigned Opcode, unsigned ZeroReg, llvm::ArrayRef< unsigned > Indices) const
Definition: AArch64InstrInfo.cpp:3296
llvm::AArch64::DestructiveOther
@ DestructiveOther
Definition: AArch64InstrInfo.h:476
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1564
llvm::AArch64InstrInfo::buildOutlinedFrame
void buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF, const outliner::OutlinedFunction &OF) const override
Definition: AArch64InstrInfo.cpp:7371
llvm::AArch64FrameOffsetCannotUpdate
@ AArch64FrameOffsetCannotUpdate
Offset cannot apply.
Definition: AArch64InstrInfo.h:385
llvm::AArch64InstrInfo::isPairableLdStInst
static bool isPairableLdStInst(const MachineInstr &MI)
Return true if pairing the given load or store may be paired with another.
Definition: AArch64InstrInfo.cpp:2346
llvm::AArch64::getSVERevInstr
int getSVERevInstr(uint16_t Opcode)
AArch64GenInstrInfo
x3
In x86 we generate this spiffy xmm0 xmm0 ret in x86 we generate this which could be xmm1 movss xmm1 xmm0 ret In sse4 we could use insertps to make both better Here s another testcase that could use x3
Definition: README-SSE.txt:547
llvm::MachineMemOperand::MOTargetFlag1
@ MOTargetFlag1
Definition: MachineMemOperand.h:151
llvm::AArch64InstrInfo::getLoadStoreImmIdx
static unsigned getLoadStoreImmIdx(unsigned Opc)
Returns the index for the immediate for a given instruction.
Definition: AArch64InstrInfo.cpp:2240
llvm::AArch64::FalseLaneType
FalseLaneType
Definition: AArch64InstrInfo.h:487
llvm::AArch64InstrInfo::isWhileOpcode
bool isWhileOpcode(unsigned Opc) const
Returns true if the opcode is for an SVE WHILE## instruction.
Definition: AArch64InstrInfo.cpp:7738
llvm::MOStridedAccess
static const MachineMemOperand::Flags MOStridedAccess
Definition: AArch64InstrInfo.h:32
llvm::AArch64InstrInfo
Definition: AArch64InstrInfo.h:37
llvm::AArch64InstrInfo::isSchedulingBoundary
bool isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override
Definition: AArch64InstrInfo.cpp:1091
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::AArch64InstrInfo::isGPRZero
static bool isGPRZero(const MachineInstr &MI)
Does this instruction set its full destination register to zero?
Definition: AArch64InstrInfo.cpp:2034
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::AArch64::InstrFlagIsWhile
static const uint64_t InstrFlagIsWhile
Definition: AArch64InstrInfo.h:494
llvm::AArch64InstrInfo::shouldOutlineFromFunctionByDefault
bool shouldOutlineFromFunctionByDefault(MachineFunction &MF) const override
Definition: AArch64InstrInfo.cpp:7583
llvm::AArch64InstrInfo::getMachineCombinerPatterns
bool getMachineCombinerPatterns(MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &Patterns, bool DoRegPressureReduce) const override
Return true when there is potentially a faster code sequence for an instruction chain ending in Root.
Definition: AArch64InstrInfo.cpp:5092
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:127
llvm::AArch64InstrInfo::insertBranch
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
Definition: AArch64InstrInfo.cpp:503
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
llvm::AArch64InstrInfo::isStridedAccess
static bool isStridedAccess(const MachineInstr &MI)
Return true if the given load or store is a strided memory access.
Definition: AArch64InstrInfo.cpp:2169
llvm::AArch64::DestructiveUnaryPassthru
@ DestructiveUnaryPassthru
Definition: AArch64InstrInfo.h:484
MachineCombinerPattern.h
llvm::AArch64InstrInfo::copyPhysRegTuple
void copyPhysRegTuple(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc, unsigned Opcode, llvm::ArrayRef< unsigned > Indices) const
Definition: AArch64InstrInfo.cpp:3269
llvm::AArch64InstrInfo::isFPRCopy
static bool isFPRCopy(const MachineInstr &MI)
Does this instruction rename an FPR without modifying bits?
Definition: AArch64InstrInfo.cpp:2088
llvm::AArch64InstrInfo::useMachineCombiner
bool useMachineCombiner() const override
AArch64 supports MachineCombiner.
Definition: AArch64InstrInfo.cpp:4456
llvm::emitFrameOffset
void emitFrameOffset(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, StackOffset Offset, const TargetInstrInfo *TII, MachineInstr::MIFlag=MachineInstr::NoFlags, bool SetNZCV=false, bool NeedsWinCFI=false, bool *HasWinCFI=nullptr)
emitFrameOffset - Emit instructions as needed to set DestReg to SrcReg plus Offset.
Definition: AArch64InstrInfo.cpp:4095
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::AArch64InstrInfo::getBranchDestBlock
MachineBasicBlock * getBranchDestBlock(const MachineInstr &MI) const override
Definition: AArch64InstrInfo.cpp:221
llvm::AArch64::ElementSizeType
ElementSizeType
Definition: AArch64InstrInfo.h:464
llvm::AArch64InstrInfo::isCoalescableExtInstr
bool isCoalescableExtInstr(const MachineInstr &MI, Register &SrcReg, Register &DstReg, unsigned &SubIdx) const override
Definition: AArch64InstrInfo.cpp:1033
llvm::AArch64FrameOffsetIsLegal
@ AArch64FrameOffsetIsLegal
Offset is legal.
Definition: AArch64InstrInfo.h:386
llvm::AArch64::NotDestructive
@ NotDestructive
Definition: AArch64InstrInfo.h:475
llvm::isAArch64FrameOffsetLegal
int isAArch64FrameOffsetLegal(const MachineInstr &MI, StackOffset &Offset, bool *OutUseUnscaledOp=nullptr, unsigned *OutUnscaledOp=nullptr, int64_t *EmittableOffset=nullptr)
Check if the Offset is a valid frame offset for MI.
Definition: AArch64InstrInfo.cpp:4315
llvm::isIndirectBranchOpcode
static bool isIndirectBranchOpcode(int Opc)
Definition: AArch64InstrInfo.h:428
x2
gcc mainline compiles it x2(%rip)
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
uint64_t
llvm::AArch64InstrInfo::isPreLd
static bool isPreLd(const MachineInstr &MI)
Returns whether the instruction is a pre-indexed load.
Definition: AArch64InstrInfo.cpp:3089
llvm::MOSuppressPair
static const MachineMemOperand::Flags MOSuppressPair
Definition: AArch64InstrInfo.h:30
TSFLAG_INSTR_FLAGS
#define TSFLAG_INSTR_FLAGS(X)
Definition: AArch64InstrInfo.h:459
llvm::outliner::Candidate
An individual sequence of instructions to be replaced with a call to an outlined function.
Definition: MachineOutliner.h:38
llvm::DenseMap< unsigned, unsigned >
llvm::AArch64InstrInfo::removeBranch
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
Definition: AArch64InstrInfo.cpp:451
TSFLAG_ELEMENT_SIZE_TYPE
#define TSFLAG_ELEMENT_SIZE_TYPE(X)
Definition: AArch64InstrInfo.h:456
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::AArch64InstrInfo::getOutliningType
outliner::InstrType getOutliningType(MachineBasicBlock::iterator &MIT, unsigned Flags) const override
Definition: AArch64InstrInfo.cpp:7126
llvm::AArch64InstrInfo::isFunctionSafeToOutlineFrom
bool isFunctionSafeToOutlineFrom(MachineFunction &MF, bool OutlineFromLinkOnceODRs) const override
Definition: AArch64InstrInfo.cpp:7027
llvm::AArch64InstrInfo::genAlternativeCodeSequence
void genAlternativeCodeSequence(MachineInstr &Root, MachineCombinerPattern Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, DenseMap< unsigned, unsigned > &InstrIdxForVirtReg) const override
When getMachineCombinerPatterns() finds patterns, this function generates the instructions that could...
Definition: AArch64InstrInfo.cpp:5354
llvm::AArch64InstrInfo::isLoadFromStackSlot
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
Definition: AArch64InstrInfo.cpp:2107
llvm::AArch64InstrInfo::getNop
MCInst getNop() const override
Definition: AArch64InstrInfo.cpp:4451
llvm::AArch64InstrInfo::isMBBSafeToOutlineFrom
bool isMBBSafeToOutlineFrom(MachineBasicBlock &MBB, unsigned &Flags) const override
Definition: AArch64InstrInfo.cpp:7057
llvm::MachineMemOperand::Flags
Flags
Flags values. These may be or'd together.
Definition: MachineMemOperand.h:131
llvm::isNZCVTouchedInInstructionRange
bool isNZCVTouchedInInstructionRange(const MachineInstr &DefMI, const MachineInstr &UseMI, const TargetRegisterInfo *TRI)
Return true if there is an instruction /after/ DefMI and before UseMI which either reads or clobbers ...
Definition: AArch64InstrInfo.cpp:3941
llvm::MachineInstr::NoFlags
@ NoFlags
Definition: MachineInstr.h:81
llvm::AArch64InstrInfo::getOutliningCandidateInfo
outliner::OutlinedFunction getOutliningCandidateInfo(std::vector< outliner::Candidate > &RepeatedSequenceLocs) const override
Definition: AArch64InstrInfo.cpp:6590
llvm::AArch64InstrInfo::getSerializableBitmaskMachineOperandTargetFlags
ArrayRef< std::pair< unsigned, const char * > > getSerializableBitmaskMachineOperandTargetFlags() const override
Definition: AArch64InstrInfo.cpp:6423
llvm::AArch64InstrInfo::getMemOpBaseRegImmOfsOffsetOperand
MachineOperand & getMemOpBaseRegImmOfsOffsetOperand(MachineInstr &LdSt) const
Return the immediate offset of the base register in a load/store LdSt.
Definition: AArch64InstrInfo.cpp:2630
llvm::AArch64InstrInfo::AArch64InstrInfo
AArch64InstrInfo(const AArch64Subtarget &STI)
Definition: AArch64InstrInfo.cpp:70
llvm::AArch64InstrInfo::isAddImmediate
Optional< RegImmPair > isAddImmediate(const MachineInstr &MI, Register Reg) const override
Definition: AArch64InstrInfo.cpp:7608
llvm::AArch64InstrInfo::getUnscaledLdSt
static Optional< unsigned > getUnscaledLdSt(unsigned Opc)
Returns the unscaled load/store for the scaled load/store opcode, if there is a corresponding unscale...
Definition: AArch64InstrInfo.cpp:2210
llvm::Module
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
llvm::MachineInstr::MIFlag
MIFlag
Definition: MachineInstr.h:80
llvm::MachineFunction
Definition: MachineFunction.h:241
llvm::MachineBasicBlock::iterator
MachineInstrBundleIterator< MachineInstr > iterator
Definition: MachineBasicBlock.h:237
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::AArch64InstrInfo::shouldClusterMemOps
bool shouldClusterMemOps(ArrayRef< const MachineOperand * > BaseOps1, ArrayRef< const MachineOperand * > BaseOps2, unsigned NumLoads, unsigned NumBytes) const override
Detect opportunities for ldp/stp formation.
Definition: AArch64InstrInfo.cpp:3182
llvm::AArch64InstrInfo::isGPRCopy
static bool isGPRCopy(const MachineInstr &MI)
Does this instruction rename a GPR without modifying bits?
Definition: AArch64InstrInfo.cpp:2058
Cond
SmallVector< MachineOperand, 4 > Cond
Definition: BasicBlockSections.cpp:179
llvm::AArch64InstrInfo::isPTestLikeOpcode
bool isPTestLikeOpcode(unsigned Opc) const
Returns true if the opcode is for an SVE instruction that sets the condition codes as if it's results...
Definition: AArch64InstrInfo.cpp:7734
MBBI
MachineBasicBlock MachineBasicBlock::iterator MBBI
Definition: AArch64SLSHardening.cpp:75
llvm::AArch64::FalseLanesMask
@ FalseLanesMask
Definition: AArch64InstrInfo.h:488
llvm::AArch64InstrInfo::isCopyInstrImpl
Optional< DestSourcePair > isCopyInstrImpl(const MachineInstr &MI) const override
If the specific machine instruction is an instruction that moves/copies value from one register to an...
Definition: AArch64InstrInfo.cpp:7589
llvm::AArch64InstrInfo::decomposeMachineOperandsTargetFlags
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
Definition: AArch64InstrInfo.cpp:6405
llvm::StackOffset
StackOffset is a class to represent an offset with 2 dimensions, named fixed and scalable,...
Definition: TypeSize.h:134
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::AArch64RegisterInfo
Definition: AArch64RegisterInfo.h:26
llvm::CodeGenOpt::Level
Level
Definition: CodeGen.h:52
llvm::AArch64InstrInfo::canInsertSelect
bool canInsertSelect(const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, Register, Register, Register, int &, int &, int &) const override
Definition: AArch64InstrInfo.cpp:611
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::AArch64InstrInfo::loadRegFromStackSlot
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Definition: AArch64InstrInfo.cpp:3812
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::AArch64InstrInfo::getSerializableMachineMemOperandTargetFlags
ArrayRef< std::pair< MachineMemOperand::Flags, const char * > > getSerializableMachineMemOperandTargetFlags() const override
Definition: AArch64InstrInfo.cpp:6439
llvm::AArch64::DestructiveUnary
@ DestructiveUnary
Definition: AArch64InstrInfo.h:477
llvm::ISD::FrameIndex
@ FrameIndex
Definition: ISDOpcodes.h:80
llvm::AArch64InstrInfo::decomposeStackOffsetForFrameOffsets
static void decomposeStackOffsetForFrameOffsets(const StackOffset &Offset, int64_t &NumBytes, int64_t &NumPredicateVectors, int64_t &NumDataVectors)
Returns the offset in parts to which this frame offset can be decomposed for the purpose of describin...
Definition: AArch64InstrInfo.cpp:3971
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::AArch64::ElementSizeD
@ ElementSizeD
Definition: AArch64InstrInfo.h:470
llvm::AArch64InstrInfo::hasUnscaledLdStOffset
static bool hasUnscaledLdStOffset(unsigned Opc)
Return true if it has an unscaled load/store offset.
Definition: AArch64InstrInfo.cpp:2175
llvm::AArch64InstrInfo::getRegisterInfo
const AArch64RegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
Definition: AArch64InstrInfo.h:47
llvm::AArch64::DestructiveBinaryShImmUnpred
@ DestructiveBinaryShImmUnpred
Definition: AArch64InstrInfo.h:479
uint16_t
llvm::AArch64InstrInfo::convertToFlagSettingOpc
static unsigned convertToFlagSettingOpc(unsigned Opc, bool &Is64Bit)
Return the opcode that set flags when possible.
Definition: AArch64InstrInfo.cpp:2388
llvm::ISD::BR
@ BR
Control flow instructions. These all have token chains.
Definition: ISDOpcodes.h:941
llvm::AArch64InstrInfo::storeRegToStackSlot
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Definition: AArch64InstrInfo.cpp:3658
llvm::AArch64::ElementSizeMask
@ ElementSizeMask
Definition: AArch64InstrInfo.h:465
llvm::TypeSize
Definition: TypeSize.h:416
llvm::AArch64InstrInfo::getMemOpInfo
static bool getMemOpInfo(unsigned Opcode, TypeSize &Scale, unsigned &Width, int64_t &MinOffset, int64_t &MaxOffset)
Returns true if opcode Opc is a memory operation.
Definition: AArch64InstrInfo.cpp:2637
llvm::AArch64::DestructiveInstTypeMask
@ DestructiveInstTypeMask
Definition: AArch64InstrInfo.h:474
llvm::AArch64InstrInfo::isLdStPairSuppressed
static bool isLdStPairSuppressed(const MachineInstr &MI)
Return true if pairing the given load or store is hinted to be unprofitable.
Definition: AArch64InstrInfo.cpp:2155
llvm::AArch64InstrInfo::decomposeStackOffsetForDwarfOffsets
static void decomposeStackOffsetForDwarfOffsets(const StackOffset &Offset, int64_t &ByteSized, int64_t &VGSized)
Definition: AArch64InstrInfo.cpp:3952
llvm::AArch64InstrInfo::analyzeBranchPredicate
bool analyzeBranchPredicate(MachineBasicBlock &MBB, MachineBranchPredicate &MBP, bool AllowModify) const override
Definition: AArch64InstrInfo.cpp:360
llvm::LiveIntervals
Definition: LiveIntervals.h:54
llvm::AArch64InstrInfo::insertSelect
void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, Register DstReg, ArrayRef< MachineOperand > Cond, Register TrueReg, Register FalseReg) const override
Definition: AArch64InstrInfo.cpp:660
llvm::AArch64InstrInfo::optimizeCompareInstr
bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int64_t CmpMask, int64_t CmpValue, const MachineRegisterInfo *MRI) const override
optimizeCompareInstr - Convert the instruction supplying the argument to the comparison into one that...
Definition: AArch64InstrInfo.cpp:1429
llvm::AArch64InstrInfo::isBranchOffsetInRange
bool isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const override
Definition: AArch64InstrInfo.cpp:212
llvm::AMDGPU::Hwreg::Width
Width
Definition: SIDefines.h:416
llvm::AArch64::DestructiveBinaryComm
@ DestructiveBinaryComm
Definition: AArch64InstrInfo.h:481
TSFLAG_FALSE_LANE_TYPE
#define TSFLAG_FALSE_LANE_TYPE(X)
Definition: AArch64InstrInfo.h:458
llvm::AArch64FrameOffsetStatus
AArch64FrameOffsetStatus
Use to report the frame offset status in isAArch64FrameOffsetLegal.
Definition: AArch64InstrInfo.h:384
llvm::AArch64::DestructiveBinary
@ DestructiveBinary
Definition: AArch64InstrInfo.h:480
llvm::Pattern
Definition: FileCheckImpl.h:614
llvm::TargetInstrInfo::foldMemoryOperandImpl
virtual MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const
Target-dependent implementation for foldMemoryOperand.
Definition: TargetInstrInfo.h:1207
llvm::AArch64InstrInfo::foldMemoryOperandImpl
MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const override
Definition: AArch64InstrInfo.cpp:4137
DefMI
MachineInstrBuilder MachineInstrBuilder & DefMI
Definition: AArch64ExpandPseudoInsts.cpp:103
llvm::AArch64::getSVEPseudoMap
int getSVEPseudoMap(uint16_t Opcode)
llvm::AArch64InstrInfo::isExtendLikelyToBeFolded
bool isExtendLikelyToBeFolded(MachineInstr &ExtMI, MachineRegisterInfo &MRI) const override
Definition: AArch64InstrInfo.cpp:7710
llvm::AArch64InstrInfo::hasUnscaledLdStOffset
static bool hasUnscaledLdStOffset(MachineInstr &MI)
Definition: AArch64InstrInfo.h:83
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
llvm::AArch64InstrInfo::reverseBranchCondition
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
Definition: AArch64InstrInfo.cpp:410
llvm::AArch64::DestructiveBinaryImm
@ DestructiveBinaryImm
Definition: AArch64InstrInfo.h:478
llvm::AArch64InstrInfo::insertOutlinedCall
MachineBasicBlock::iterator insertOutlinedCall(Module &M, MachineBasicBlock &MBB, MachineBasicBlock::iterator &It, MachineFunction &MF, const outliner::Candidate &C) const override
Definition: AArch64InstrInfo.cpp:7507
llvm::AArch64::DestructiveBinaryCommWithRev
@ DestructiveBinaryCommWithRev
Definition: AArch64InstrInfo.h:482
llvm::AArch64InstrInfo::getMemScale
static int getMemScale(unsigned Opc)
Scaling factor for (scaled or unscaled) load or store.
Definition: AArch64InstrInfo.cpp:3017
llvm::AArch64InstrInfo::optimizeCondBranch
bool optimizeCondBranch(MachineInstr &MI) const override
Replace csincr-branch sequence by simple conditional branch.
Definition: AArch64InstrInfo.cpp:6267
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::AArch64InstrInfo::analyzeCompare
bool analyzeCompare(const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int64_t &CmpMask, int64_t &CmpValue) const override
analyzeCompare - For a comparison instruction, return the source registers in SrcReg and SrcReg2,...
Definition: AArch64InstrInfo.cpp:1114
llvm::AArch64InstrInfo::isFalkorShiftExtFast
static bool isFalkorShiftExtFast(const MachineInstr &MI)
Returns true if the instruction has a shift by immediate that can be executed in one cycle less.
Definition: AArch64InstrInfo.cpp:885
llvm::isPTrueOpcode
static bool isPTrueOpcode(unsigned Opc)
Definition: AArch64InstrInfo.h:440
llvm::AArch64Subtarget
Definition: AArch64Subtarget.h:38
llvm::AArch64InstrInfo::isCandidateToMergeOrPair
bool isCandidateToMergeOrPair(const MachineInstr &MI) const
Return true if this is a load/store that can be potentially paired/merged.
Definition: AArch64InstrInfo.cpp:2478
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::AArch64::FalseLanesUndef
@ FalseLanesUndef
Definition: AArch64InstrInfo.h:490
llvm::AArch64::getSVENonRevInstr
int getSVENonRevInstr(uint16_t Opcode)
llvm::AArch64InstrInfo::isPreSt
static bool isPreSt(const MachineInstr &MI)
Returns whether the instruction is a pre-indexed store.
Definition: AArch64InstrInfo.cpp:3102
llvm::AArch64InstrInfo::isAssociativeAndCommutative
bool isAssociativeAndCommutative(const MachineInstr &Inst) const override
Return true when Inst is associative and commutative so that it can be reassociated.
Definition: AArch64InstrInfo.cpp:4612
llvm::AArch64InstrInfo::isSubregFoldable
bool isSubregFoldable() const override
Definition: AArch64InstrInfo.h:180
llvm::AArch64InstrInfo::isAsCheapAsAMove
bool isAsCheapAsAMove(const MachineInstr &MI) const override
Definition: AArch64InstrInfo.cpp:806
llvm::AArch64InstrInfo::isSEHInstruction
static bool isSEHInstruction(const MachineInstr &MI)
Return true if the instructions is a SEH instruciton used for unwinding on Windows.
Definition: AArch64InstrInfo.cpp:1007
llvm::AArch64InstrInfo::isStoreToStackSlot
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
Definition: AArch64InstrInfo.cpp:2130
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24
llvm::MachineCombinerPattern
MachineCombinerPattern
These are instruction patterns matched by the machine combiner pass.
Definition: MachineCombinerPattern.h:20
llvm::AArch64InstrInfo::analyzeBranch
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override
Definition: AArch64InstrInfo.cpp:242
llvm::AArch64::ElementSizeH
@ ElementSizeH
Definition: AArch64InstrInfo.h:468