LLVM  13.0.0git
AArch64InstrInfo.h
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1 //===- AArch64InstrInfo.h - AArch64 Instruction Information -----*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the AArch64 implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64INSTRINFO_H
14 #define LLVM_LIB_TARGET_AARCH64_AARCH64INSTRINFO_H
15 
16 #include "AArch64.h"
17 #include "AArch64RegisterInfo.h"
18 #include "llvm/ADT/Optional.h"
21 #include "llvm/Support/TypeSize.h"
22 
23 #define GET_INSTRINFO_HEADER
24 #include "AArch64GenInstrInfo.inc"
25 
26 namespace llvm {
27 
28 class AArch64Subtarget;
29 class AArch64TargetMachine;
30 
35 
36 #define FALKOR_STRIDED_ACCESS_MD "falkor.strided.access"
37 
38 class AArch64InstrInfo final : public AArch64GenInstrInfo {
39  const AArch64RegisterInfo RI;
40  const AArch64Subtarget &Subtarget;
41 
42 public:
43  explicit AArch64InstrInfo(const AArch64Subtarget &STI);
44 
45  /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
46  /// such, whenever a client has an instance of instruction info, it should
47  /// always be able to get register info as well (through this method).
48  const AArch64RegisterInfo &getRegisterInfo() const { return RI; }
49 
50  unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
51 
52  bool isAsCheapAsAMove(const MachineInstr &MI) const override;
53 
54  bool isCoalescableExtInstr(const MachineInstr &MI, Register &SrcReg,
55  Register &DstReg, unsigned &SubIdx) const override;
56 
57  bool
59  const MachineInstr &MIb) const override;
60 
61  unsigned isLoadFromStackSlot(const MachineInstr &MI,
62  int &FrameIndex) const override;
63  unsigned isStoreToStackSlot(const MachineInstr &MI,
64  int &FrameIndex) const override;
65 
66  /// Does this instruction set its full destination register to zero?
67  static bool isGPRZero(const MachineInstr &MI);
68 
69  /// Does this instruction rename a GPR without modifying bits?
70  static bool isGPRCopy(const MachineInstr &MI);
71 
72  /// Does this instruction rename an FPR without modifying bits?
73  static bool isFPRCopy(const MachineInstr &MI);
74 
75  /// Return true if pairing the given load or store is hinted to be
76  /// unprofitable.
77  static bool isLdStPairSuppressed(const MachineInstr &MI);
78 
79  /// Return true if the given load or store is a strided memory access.
80  static bool isStridedAccess(const MachineInstr &MI);
81 
82  /// Return true if this is an unscaled load/store.
83  static bool isUnscaledLdSt(unsigned Opc);
84  static bool isUnscaledLdSt(MachineInstr &MI) {
85  return isUnscaledLdSt(MI.getOpcode());
86  }
87 
88  /// Returns the unscaled load/store for the scaled load/store opcode,
89  /// if there is a corresponding unscaled variant available.
90  static Optional<unsigned> getUnscaledLdSt(unsigned Opc);
91 
92  /// Scaling factor for (scaled or unscaled) load or store.
93  static int getMemScale(unsigned Opc);
94  static int getMemScale(const MachineInstr &MI) {
95  return getMemScale(MI.getOpcode());
96  }
97 
98 
99  /// Returns the index for the immediate for a given instruction.
100  static unsigned getLoadStoreImmIdx(unsigned Opc);
101 
102  /// Return true if pairing the given load or store may be paired with another.
103  static bool isPairableLdStInst(const MachineInstr &MI);
104 
105  /// Return the opcode that set flags when possible. The caller is
106  /// responsible for ensuring the opc has a flag setting equivalent.
107  static unsigned convertToFlagSettingOpc(unsigned Opc, bool &Is64Bit);
108 
109  /// Return true if this is a load/store that can be potentially paired/merged.
110  bool isCandidateToMergeOrPair(const MachineInstr &MI) const;
111 
112  /// Hint that pairing the given load or store is unprofitable.
113  static void suppressLdStPair(MachineInstr &MI);
114 
117  const TargetRegisterInfo *TRI) const override;
118 
121  int64_t &Offset, bool &OffsetIsScalable, unsigned &Width,
122  const TargetRegisterInfo *TRI) const override;
123 
124  /// If \p OffsetIsScalable is set to 'true', the offset is scaled by `vscale`.
125  /// This is true for some SVE instructions like ldr/str that have a
126  /// 'reg + imm' addressing mode where the immediate is an index to the
127  /// scalable vector located at 'reg + imm * vscale x #bytes'.
129  const MachineOperand *&BaseOp,
130  int64_t &Offset, bool &OffsetIsScalable,
131  unsigned &Width,
132  const TargetRegisterInfo *TRI) const;
133 
134  /// Return the immediate offset of the base register in a load/store \p LdSt.
136 
137  /// Returns true if opcode \p Opc is a memory operation. If it is, set
138  /// \p Scale, \p Width, \p MinOffset, and \p MaxOffset accordingly.
139  ///
140  /// For unscaled instructions, \p Scale is set to 1.
141  static bool getMemOpInfo(unsigned Opcode, TypeSize &Scale, unsigned &Width,
142  int64_t &MinOffset, int64_t &MaxOffset);
143 
146  unsigned NumLoads, unsigned NumBytes) const override;
147 
149  const DebugLoc &DL, MCRegister DestReg,
150  MCRegister SrcReg, bool KillSrc, unsigned Opcode,
151  llvm::ArrayRef<unsigned> Indices) const;
153  DebugLoc DL, unsigned DestReg, unsigned SrcReg,
154  bool KillSrc, unsigned Opcode, unsigned ZeroReg,
155  llvm::ArrayRef<unsigned> Indices) const;
157  const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
158  bool KillSrc) const override;
159 
162  bool isKill, int FrameIndex,
163  const TargetRegisterClass *RC,
164  const TargetRegisterInfo *TRI) const override;
165 
168  int FrameIndex, const TargetRegisterClass *RC,
169  const TargetRegisterInfo *TRI) const override;
170 
171  // This tells target independent code that it is okay to pass instructions
172  // with subreg operands to foldMemoryOperandImpl.
173  bool isSubregFoldable() const override { return true; }
174 
176  MachineInstr *
178  ArrayRef<unsigned> Ops,
180  LiveIntervals *LIS = nullptr,
181  VirtRegMap *VRM = nullptr) const override;
182 
183  /// \returns true if a branch from an instruction with opcode \p BranchOpc
184  /// bytes is capable of jumping to a position \p BrOffset bytes away.
185  bool isBranchOffsetInRange(unsigned BranchOpc,
186  int64_t BrOffset) const override;
187 
188  MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override;
189 
191  MachineBasicBlock *&FBB,
193  bool AllowModify = false) const override;
195  MachineBranchPredicate &MBP,
196  bool AllowModify) const override;
198  int *BytesRemoved = nullptr) const override;
201  const DebugLoc &DL,
202  int *BytesAdded = nullptr) const override;
203  bool
206  Register, Register, Register, int &, int &,
207  int &) const override;
209  const DebugLoc &DL, Register DstReg,
211  Register FalseReg) const override;
212  MCInst getNop() const override;
213 
215  const MachineBasicBlock *MBB,
216  const MachineFunction &MF) const override;
217 
218  /// analyzeCompare - For a comparison instruction, return the source registers
219  /// in SrcReg and SrcReg2, and the value it compares against in CmpValue.
220  /// Return true if the comparison instruction can be analyzed.
221  bool analyzeCompare(const MachineInstr &MI, Register &SrcReg,
222  Register &SrcReg2, int &CmpMask,
223  int &CmpValue) const override;
224  /// optimizeCompareInstr - Convert the instruction supplying the argument to
225  /// the comparison into one that sets the zero bit in the flags register.
226  bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
227  Register SrcReg2, int CmpMask, int CmpValue,
228  const MachineRegisterInfo *MRI) const override;
229  bool optimizeCondBranch(MachineInstr &MI) const override;
230 
231  /// Return true when a code sequence can improve throughput. It
232  /// should be called only for instructions in loops.
233  /// \param Pattern - combiner pattern
235  /// Return true when there is potentially a faster code sequence
236  /// for an instruction chain ending in ``Root``. All potential patterns are
237  /// listed in the ``Patterns`` array.
238  bool
241  bool DoRegPressureReduce) const override;
242  /// Return true when Inst is associative and commutative so that it can be
243  /// reassociated.
244  bool isAssociativeAndCommutative(const MachineInstr &Inst) const override;
245  /// When getMachineCombinerPatterns() finds patterns, this function generates
246  /// the instructions that could replace the original code sequence
251  DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const override;
252  /// AArch64 supports MachineCombiner.
253  bool useMachineCombiner() const override;
254 
255  bool expandPostRAPseudo(MachineInstr &MI) const override;
256 
257  std::pair<unsigned, unsigned>
258  decomposeMachineOperandsTargetFlags(unsigned TF) const override;
265 
267  bool OutlineFromLinkOnceODRs) const override;
269  std::vector<outliner::Candidate> &RepeatedSequenceLocs) const override;
271  getOutliningType(MachineBasicBlock::iterator &MIT, unsigned Flags) const override;
273  unsigned &Flags) const override;
275  const outliner::OutlinedFunction &OF) const override;
279  const outliner::Candidate &C) const override;
280  bool shouldOutlineFromFunctionByDefault(MachineFunction &MF) const override;
281  /// Returns the vector element size (B, H, S or D) of an SVE opcode.
282  uint64_t getElementSizeForOpcode(unsigned Opc) const;
283  /// Returns true if the opcode is for an SVE instruction that sets the
284  /// condition codes as if it's results had been fed to a PTEST instruction
285  /// along with the same general predicate.
286  bool isPTestLikeOpcode(unsigned Opc) const;
287  /// Returns true if the opcode is for an SVE WHILE## instruction.
288  bool isWhileOpcode(unsigned Opc) const;
289  /// Returns true if the instruction has a shift by immediate that can be
290  /// executed in one cycle less.
291  static bool isFalkorShiftExtFast(const MachineInstr &MI);
292  /// Return true if the instructions is a SEH instruciton used for unwinding
293  /// on Windows.
294  static bool isSEHInstruction(const MachineInstr &MI);
295 
297  Register Reg) const override;
298 
300  Register Reg) const override;
301 
302  unsigned int getTailDuplicateSize(CodeGenOpt::Level OptLevel) const override;
303 
305  MachineRegisterInfo &MRI) const override;
306 
308  int64_t &NumBytes,
309  int64_t &NumPredicateVectors,
310  int64_t &NumDataVectors);
312  int64_t &ByteSized,
313  int64_t &VGSized);
314 #define GET_INSTRINFO_HELPER_DECLS
315 #include "AArch64GenInstrInfo.inc"
316 
317 protected:
318  /// If the specific machine instruction is an instruction that moves/copies
319  /// value from one register to another register return destination and source
320  /// registers as machine operands.
321  Optional<DestSourcePair>
322  isCopyInstrImpl(const MachineInstr &MI) const override;
323 
324 private:
325  unsigned getInstBundleLength(const MachineInstr &MI) const;
326 
327  /// Sets the offsets on outlined instructions in \p MBB which use SP
328  /// so that they will be valid post-outlining.
329  ///
330  /// \param MBB A \p MachineBasicBlock in an outlined function.
331  void fixupPostOutline(MachineBasicBlock &MBB) const;
332 
333  void instantiateCondBranch(MachineBasicBlock &MBB, const DebugLoc &DL,
334  MachineBasicBlock *TBB,
335  ArrayRef<MachineOperand> Cond) const;
336  bool substituteCmpToZero(MachineInstr &CmpInstr, unsigned SrcReg,
337  const MachineRegisterInfo *MRI) const;
338 
339  /// Returns an unused general-purpose register which can be used for
340  /// constructing an outlined call if one exists. Returns 0 otherwise.
341  unsigned findRegisterToSaveLRTo(const outliner::Candidate &C) const;
342 
343  /// Remove a ptest of a predicate-generating operation that already sets, or
344  /// can be made to set, the condition codes in an identical manner
345  bool optimizePTestInstr(MachineInstr *PTest, unsigned MaskReg,
346  unsigned PredReg,
347  const MachineRegisterInfo *MRI) const;
348 };
349 
350 /// Return true if there is an instruction /after/ \p DefMI and before \p UseMI
351 /// which either reads or clobbers NZCV.
352 bool isNZCVTouchedInInstructionRange(const MachineInstr &DefMI,
353  const MachineInstr &UseMI,
354  const TargetRegisterInfo *TRI);
355 
356 /// emitFrameOffset - Emit instructions as needed to set DestReg to SrcReg
357 /// plus Offset. This is intended to be used from within the prolog/epilog
358 /// insertion (PEI) pass, where a virtual scratch register may be allocated
359 /// if necessary, to be replaced by the scavenger at the end of PEI.
360 void emitFrameOffset(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
361  const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
362  StackOffset Offset, const TargetInstrInfo *TII,
364  bool SetNZCV = false, bool NeedsWinCFI = false,
365  bool *HasWinCFI = nullptr);
366 
367 /// rewriteAArch64FrameIndex - Rewrite MI to access 'Offset' bytes from the
368 /// FP. Return false if the offset could not be handled directly in MI, and
369 /// return the left-over portion by reference.
370 bool rewriteAArch64FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
371  unsigned FrameReg, StackOffset &Offset,
372  const AArch64InstrInfo *TII);
373 
374 /// Use to report the frame offset status in isAArch64FrameOffsetLegal.
376  AArch64FrameOffsetCannotUpdate = 0x0, ///< Offset cannot apply.
377  AArch64FrameOffsetIsLegal = 0x1, ///< Offset is legal.
378  AArch64FrameOffsetCanUpdate = 0x2 ///< Offset can apply, at least partly.
379 };
380 
381 /// Check if the @p Offset is a valid frame offset for @p MI.
382 /// The returned value reports the validity of the frame offset for @p MI.
383 /// It uses the values defined by AArch64FrameOffsetStatus for that.
384 /// If result == AArch64FrameOffsetCannotUpdate, @p MI cannot be updated to
385 /// use an offset.eq
386 /// If result & AArch64FrameOffsetIsLegal, @p Offset can completely be
387 /// rewritten in @p MI.
388 /// If result & AArch64FrameOffsetCanUpdate, @p Offset contains the
389 /// amount that is off the limit of the legal offset.
390 /// If set, @p OutUseUnscaledOp will contain the whether @p MI should be
391 /// turned into an unscaled operator, which opcode is in @p OutUnscaledOp.
392 /// If set, @p EmittableOffset contains the amount that can be set in @p MI
393 /// (possibly with @p OutUnscaledOp if OutUseUnscaledOp is true) and that
394 /// is a legal offset.
395 int isAArch64FrameOffsetLegal(const MachineInstr &MI, StackOffset &Offset,
396  bool *OutUseUnscaledOp = nullptr,
397  unsigned *OutUnscaledOp = nullptr,
398  int64_t *EmittableOffset = nullptr);
399 
400 static inline bool isUncondBranchOpcode(int Opc) { return Opc == AArch64::B; }
401 
402 static inline bool isCondBranchOpcode(int Opc) {
403  switch (Opc) {
404  case AArch64::Bcc:
405  case AArch64::CBZW:
406  case AArch64::CBZX:
407  case AArch64::CBNZW:
408  case AArch64::CBNZX:
409  case AArch64::TBZW:
410  case AArch64::TBZX:
411  case AArch64::TBNZW:
412  case AArch64::TBNZX:
413  return true;
414  default:
415  return false;
416  }
417 }
418 
419 static inline bool isIndirectBranchOpcode(int Opc) {
420  switch (Opc) {
421  case AArch64::BR:
422  case AArch64::BRAA:
423  case AArch64::BRAB:
424  case AArch64::BRAAZ:
425  case AArch64::BRABZ:
426  return true;
427  }
428  return false;
429 }
430 
431 static inline bool isPTrueOpcode(unsigned Opc) {
432  switch (Opc) {
433  case AArch64::PTRUE_B:
434  case AArch64::PTRUE_H:
435  case AArch64::PTRUE_S:
436  case AArch64::PTRUE_D:
437  return true;
438  default:
439  return false;
440  }
441 }
442 
443 /// Return opcode to be used for indirect calls.
444 unsigned getBLRCallOpcode(const MachineFunction &MF);
445 
446 // struct TSFlags {
447 #define TSFLAG_ELEMENT_SIZE_TYPE(X) (X) // 3-bits
448 #define TSFLAG_DESTRUCTIVE_INST_TYPE(X) ((X) << 3) // 4-bit
449 #define TSFLAG_FALSE_LANE_TYPE(X) ((X) << 7) // 2-bits
450 #define TSFLAG_INSTR_FLAGS(X) ((X) << 9) // 2-bits
451 // }
452 
453 namespace AArch64 {
454 
462 };
463 
475 };
476 
481 };
482 
483 // NOTE: This is a bit field.
484 static const uint64_t InstrFlagIsWhile = TSFLAG_INSTR_FLAGS(0x1);
485 static const uint64_t InstrFlagIsPTestLike = TSFLAG_INSTR_FLAGS(0x2);
486 
487 #undef TSFLAG_ELEMENT_SIZE_TYPE
488 #undef TSFLAG_DESTRUCTIVE_INST_TYPE
489 #undef TSFLAG_FALSE_LANE_TYPE
490 #undef TSFLAG_INSTR_FLAGS
491 
492 int getSVEPseudoMap(uint16_t Opcode);
493 int getSVERevInstr(uint16_t Opcode);
494 int getSVENonRevInstr(uint16_t Opcode);
495 }
496 
497 } // end namespace llvm
498 
499 #endif
llvm::AArch64InstrInfo::getTailDuplicateSize
unsigned int getTailDuplicateSize(CodeGenOpt::Level OptLevel) const override
Definition: AArch64InstrInfo.cpp:7207
llvm::AArch64::DestructiveInstType
DestructiveInstType
Definition: AArch64InstrInfo.h:464
llvm::AArch64InstrInfo::describeLoadedValue
Optional< ParamLoadedValue > describeLoadedValue(const MachineInstr &MI, Register Reg) const override
Definition: AArch64InstrInfo.cpp:7147
llvm::AArch64::ElementSizeNone
@ ElementSizeNone
Definition: AArch64InstrInfo.h:457
AArch64RegisterInfo.h
llvm::AArch64InstrInfo::suppressLdStPair
static void suppressLdStPair(MachineInstr &MI)
Hint that pairing the given load or store is unprofitable.
Definition: AArch64InstrInfo.cpp:1959
llvm::AArch64InstrInfo::isThroughputPattern
bool isThroughputPattern(MachineCombinerPattern Pattern) const override
Return true when a code sequence can improve throughput.
Definition: AArch64InstrInfo.cpp:4531
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:100
llvm
Definition: AllocatorList.h:23
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
AArch64.h
UseMI
MachineInstrBuilder & UseMI
Definition: AArch64ExpandPseudoInsts.cpp:100
llvm::AArch64InstrInfo::copyPhysReg
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
Definition: AArch64InstrInfo.cpp:2897
Optional.h
TSFLAG_DESTRUCTIVE_INST_TYPE
#define TSFLAG_DESTRUCTIVE_INST_TYPE(X)
Definition: AArch64InstrInfo.h:448
llvm::AArch64InstrInfo::expandPostRAPseudo
bool expandPostRAPseudo(MachineInstr &MI) const override
Definition: AArch64InstrInfo.cpp:1721
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
llvm::AArch64InstrInfo::getInstSizeInBytes
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
GetInstSize - Return the number of bytes of code the specified instruction may be.
Definition: AArch64InstrInfo.cpp:77
llvm::AArch64::FalseLanesZero
@ FalseLanesZero
Definition: AArch64InstrInfo.h:479
llvm::AArch64InstrInfo::getAddrModeFromMemoryOp
Optional< ExtAddrMode > getAddrModeFromMemoryOp(const MachineInstr &MemI, const TargetRegisterInfo *TRI) const override
Definition: AArch64InstrInfo.cpp:2279
llvm::AArch64::ElementSizeS
@ ElementSizeS
Definition: AArch64InstrInfo.h:460
llvm::AArch64FrameOffsetCanUpdate
@ AArch64FrameOffsetCanUpdate
Offset can apply, at least partly.
Definition: AArch64InstrInfo.h:378
llvm::AArch64InstrInfo::getMemOperandWithOffsetWidth
bool getMemOperandWithOffsetWidth(const MachineInstr &MI, const MachineOperand *&BaseOp, int64_t &Offset, bool &OffsetIsScalable, unsigned &Width, const TargetRegisterInfo *TRI) const
If OffsetIsScalable is set to 'true', the offset is scaled by vscale.
Definition: AArch64InstrInfo.cpp:2296
TypeSize.h
llvm::AArch64::InstrFlagIsPTestLike
static const uint64_t InstrFlagIsPTestLike
Definition: AArch64InstrInfo.h:485
llvm::AArch64InstrInfo::getMemOperandsWithOffsetWidth
bool getMemOperandsWithOffsetWidth(const MachineInstr &MI, SmallVectorImpl< const MachineOperand * > &BaseOps, int64_t &Offset, bool &OffsetIsScalable, unsigned &Width, const TargetRegisterInfo *TRI) const override
Definition: AArch64InstrInfo.cpp:2263
llvm::VirtRegMap
Definition: VirtRegMap.h:33
llvm::getBLRCallOpcode
unsigned getBLRCallOpcode(const MachineFunction &MF)
Return opcode to be used for indirect calls.
Definition: AArch64InstrInfo.cpp:7211
llvm::AArch64InstrInfo::getMemScale
static int getMemScale(const MachineInstr &MI)
Definition: AArch64InstrInfo.h:94
llvm::AArch64InstrInfo::getSerializableDirectMachineOperandTargetFlags
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
Definition: AArch64InstrInfo.cpp:5883
llvm::MachineMemOperand::MOTargetFlag2
@ MOTargetFlag2
Definition: MachineMemOperand.h:151
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:231
llvm::outliner::InstrType
InstrType
Represents how an instruction should be mapped by the outliner.
Definition: MachineOutliner.h:34
llvm::AArch64InstrInfo::getElementSizeForOpcode
uint64_t getElementSizeForOpcode(unsigned Opc) const
Returns the vector element size (B, H, S or D) of an SVE opcode.
Definition: AArch64InstrInfo.cpp:7194
TargetInstrInfo.h
llvm::AArch64InstrInfo::areMemAccessesTriviallyDisjoint
bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb) const override
Definition: AArch64InstrInfo.cpp:1050
llvm::isCondBranchOpcode
static bool isCondBranchOpcode(int Opc)
Definition: AArch64InstrInfo.h:402
llvm::rewriteAArch64FrameIndex
bool rewriteAArch64FrameIndex(MachineInstr &MI, unsigned FrameRegIdx, unsigned FrameReg, StackOffset &Offset, const AArch64InstrInfo *TII)
rewriteAArch64FrameIndex - Rewrite MI to access 'Offset' bytes from the FP.
Definition: AArch64InstrInfo.cpp:4023
llvm::AArch64::ElementSizeB
@ ElementSizeB
Definition: AArch64InstrInfo.h:458
llvm::AArch64::DestructiveTernaryCommWithRev
@ DestructiveTernaryCommWithRev
Definition: AArch64InstrInfo.h:474
llvm::Optional< unsigned >
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
llvm::isUncondBranchOpcode
static bool isUncondBranchOpcode(int Opc)
Definition: AArch64InstrInfo.h:400
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:183
llvm::AArch64InstrInfo::isUnscaledLdSt
static bool isUnscaledLdSt(MachineInstr &MI)
Definition: AArch64InstrInfo.h:84
llvm::outliner::OutlinedFunction
The information necessary to create an outlined function for some class of candidate.
Definition: MachineOutliner.h:164
llvm::AArch64InstrInfo::copyGPRRegTuple
void copyGPRRegTuple(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc, unsigned Opcode, unsigned ZeroReg, llvm::ArrayRef< unsigned > Indices) const
Definition: AArch64InstrInfo.cpp:2872
llvm::AArch64::DestructiveOther
@ DestructiveOther
Definition: AArch64InstrInfo.h:467
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
llvm::AArch64InstrInfo::buildOutlinedFrame
void buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF, const outliner::OutlinedFunction &OF) const override
Definition: AArch64InstrInfo.cpp:6839
llvm::AArch64FrameOffsetCannotUpdate
@ AArch64FrameOffsetCannotUpdate
Offset cannot apply.
Definition: AArch64InstrInfo.h:376
llvm::AArch64InstrInfo::isPairableLdStInst
static bool isPairableLdStInst(const MachineInstr &MI)
Return true if pairing the given load or store may be paired with another.
Definition: AArch64InstrInfo.cpp:2088
llvm::AArch64::getSVERevInstr
int getSVERevInstr(uint16_t Opcode)
AArch64GenInstrInfo
x3
In x86 we generate this spiffy xmm0 xmm0 ret in x86 we generate this which could be xmm1 movss xmm1 xmm0 ret In sse4 we could use insertps to make both better Here s another testcase that could use x3
Definition: README-SSE.txt:547
llvm::MachineMemOperand::MOTargetFlag1
@ MOTargetFlag1
Definition: MachineMemOperand.h:150
llvm::AArch64InstrInfo::getLoadStoreImmIdx
static unsigned getLoadStoreImmIdx(unsigned Opc)
Returns the index for the immediate for a given instruction.
Definition: AArch64InstrInfo.cpp:2027
llvm::AArch64::FalseLaneType
FalseLaneType
Definition: AArch64InstrInfo.h:477
llvm::AArch64InstrInfo::isWhileOpcode
bool isWhileOpcode(unsigned Opc) const
Returns true if the opcode is for an SVE WHILE## instruction.
Definition: AArch64InstrInfo.cpp:7202
llvm::MOStridedAccess
static const MachineMemOperand::Flags MOStridedAccess
Definition: AArch64InstrInfo.h:33
llvm::AArch64InstrInfo
Definition: AArch64InstrInfo.h:38
llvm::AArch64InstrInfo::isSchedulingBoundary
bool isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override
Definition: AArch64InstrInfo.cpp:1088
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::AArch64InstrInfo::analyzeCompare
bool analyzeCompare(const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int &CmpMask, int &CmpValue) const override
analyzeCompare - For a comparison instruction, return the source registers in SrcReg and SrcReg2,...
Definition: AArch64InstrInfo.cpp:1111
llvm::AArch64InstrInfo::isUnscaledLdSt
static bool isUnscaledLdSt(unsigned Opc)
Return true if this is an unscaled load/store.
Definition: AArch64InstrInfo.cpp:1972
llvm::AArch64InstrInfo::isGPRZero
static bool isGPRZero(const MachineInstr &MI)
Does this instruction set its full destination register to zero?
Definition: AArch64InstrInfo.cpp:1829
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::AArch64::InstrFlagIsWhile
static const uint64_t InstrFlagIsWhile
Definition: AArch64InstrInfo.h:484
llvm::AArch64InstrInfo::shouldOutlineFromFunctionByDefault
bool shouldOutlineFromFunctionByDefault(MachineFunction &MF) const override
Definition: AArch64InstrInfo.cpp:7047
llvm::AArch64InstrInfo::getMachineCombinerPatterns
bool getMachineCombinerPatterns(MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &Patterns, bool DoRegPressureReduce) const override
Return true when there is potentially a faster code sequence for an instruction chain ending in Root.
Definition: AArch64InstrInfo.cpp:4640
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:129
llvm::AArch64InstrInfo::insertBranch
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
Definition: AArch64InstrInfo.cpp:500
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
llvm::AArch64InstrInfo::isStridedAccess
static bool isStridedAccess(const MachineInstr &MI)
Return true if the given load or store is a strided memory access.
Definition: AArch64InstrInfo.cpp:1966
MachineCombinerPattern.h
llvm::AArch64InstrInfo::copyPhysRegTuple
void copyPhysRegTuple(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc, unsigned Opcode, llvm::ArrayRef< unsigned > Indices) const
Definition: AArch64InstrInfo.cpp:2845
llvm::AArch64InstrInfo::isFPRCopy
static bool isFPRCopy(const MachineInstr &MI)
Does this instruction rename an FPR without modifying bits?
Definition: AArch64InstrInfo.cpp:1883
llvm::AArch64InstrInfo::useMachineCombiner
bool useMachineCombiner() const override
AArch64 supports MachineCombiner.
Definition: AArch64InstrInfo.cpp:4063
llvm::emitFrameOffset
void emitFrameOffset(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, StackOffset Offset, const TargetInstrInfo *TII, MachineInstr::MIFlag=MachineInstr::NoFlags, bool SetNZCV=false, bool NeedsWinCFI=false, bool *HasWinCFI=nullptr)
emitFrameOffset - Emit instructions as needed to set DestReg to SrcReg plus Offset.
Definition: AArch64InstrInfo.cpp:3706
llvm::AArch64InstrInfo::optimizeCompareInstr
bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int CmpMask, int CmpValue, const MachineRegisterInfo *MRI) const override
optimizeCompareInstr - Convert the instruction supplying the argument to the comparison into one that...
Definition: AArch64InstrInfo.cpp:1432
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::AArch64InstrInfo::getBranchDestBlock
MachineBasicBlock * getBranchDestBlock(const MachineInstr &MI) const override
Definition: AArch64InstrInfo.cpp:218
llvm::AArch64::ElementSizeType
ElementSizeType
Definition: AArch64InstrInfo.h:455
llvm::AArch64InstrInfo::isCoalescableExtInstr
bool isCoalescableExtInstr(const MachineInstr &MI, Register &SrcReg, Register &DstReg, unsigned &SubIdx) const override
Definition: AArch64InstrInfo.cpp:1030
llvm::AArch64FrameOffsetIsLegal
@ AArch64FrameOffsetIsLegal
Offset is legal.
Definition: AArch64InstrInfo.h:377
llvm::AArch64::NotDestructive
@ NotDestructive
Definition: AArch64InstrInfo.h:466
llvm::isAArch64FrameOffsetLegal
int isAArch64FrameOffsetLegal(const MachineInstr &MI, StackOffset &Offset, bool *OutUseUnscaledOp=nullptr, unsigned *OutUnscaledOp=nullptr, int64_t *EmittableOffset=nullptr)
Check if the Offset is a valid frame offset for MI.
Definition: AArch64InstrInfo.cpp:3926
llvm::isIndirectBranchOpcode
static bool isIndirectBranchOpcode(int Opc)
Definition: AArch64InstrInfo.h:419
x2
gcc mainline compiles it x2(%rip)
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::MOSuppressPair
static const MachineMemOperand::Flags MOSuppressPair
Definition: AArch64InstrInfo.h:31
TSFLAG_INSTR_FLAGS
#define TSFLAG_INSTR_FLAGS(X)
Definition: AArch64InstrInfo.h:450
llvm::outliner::Candidate
An individual sequence of instructions to be replaced with a call to an outlined function.
Definition: MachineOutliner.h:38
llvm::DenseMap< unsigned, unsigned >
llvm::AArch64InstrInfo::removeBranch
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
Definition: AArch64InstrInfo.cpp:448
TSFLAG_ELEMENT_SIZE_TYPE
#define TSFLAG_ELEMENT_SIZE_TYPE(X)
Definition: AArch64InstrInfo.h:447
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::AArch64InstrInfo::getOutliningType
outliner::InstrType getOutliningType(MachineBasicBlock::iterator &MIT, unsigned Flags) const override
Definition: AArch64InstrInfo.cpp:6601
llvm::AArch64InstrInfo::isFunctionSafeToOutlineFrom
bool isFunctionSafeToOutlineFrom(MachineFunction &MF, bool OutlineFromLinkOnceODRs) const override
Definition: AArch64InstrInfo.cpp:6504
llvm::AArch64InstrInfo::genAlternativeCodeSequence
void genAlternativeCodeSequence(MachineInstr &Root, MachineCombinerPattern Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, DenseMap< unsigned, unsigned > &InstrIdxForVirtReg) const override
When getMachineCombinerPatterns() finds patterns, this function generates the instructions that could...
Definition: AArch64InstrInfo.cpp:4864
llvm::AArch64InstrInfo::isLoadFromStackSlot
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
Definition: AArch64InstrInfo.cpp:1904
llvm::AArch64InstrInfo::getNop
MCInst getNop() const override
Definition: AArch64InstrInfo.cpp:4058
llvm::AArch64InstrInfo::isMBBSafeToOutlineFrom
bool isMBBSafeToOutlineFrom(MachineBasicBlock &MBB, unsigned &Flags) const override
Definition: AArch64InstrInfo.cpp:6534
llvm::MachineMemOperand::Flags
Flags
Flags values. These may be or'd together.
Definition: MachineMemOperand.h:130
llvm::isNZCVTouchedInInstructionRange
bool isNZCVTouchedInInstructionRange(const MachineInstr &DefMI, const MachineInstr &UseMI, const TargetRegisterInfo *TRI)
Return true if there is an instruction /after/ DefMI and before UseMI which either reads or clobbers ...
Definition: AArch64InstrInfo.cpp:3552
llvm::MachineInstr::NoFlags
@ NoFlags
Definition: MachineInstr.h:81
llvm::AArch64InstrInfo::getOutliningCandidateInfo
outliner::OutlinedFunction getOutliningCandidateInfo(std::vector< outliner::Candidate > &RepeatedSequenceLocs) const override
Definition: AArch64InstrInfo.cpp:6062
llvm::AArch64InstrInfo::getSerializableBitmaskMachineOperandTargetFlags
ArrayRef< std::pair< unsigned, const char * > > getSerializableBitmaskMachineOperandTargetFlags() const override
Definition: AArch64InstrInfo.cpp:5895
llvm::AArch64InstrInfo::getMemOpBaseRegImmOfsOffsetOperand
MachineOperand & getMemOpBaseRegImmOfsOffsetOperand(MachineInstr &LdSt) const
Return the immediate offset of the base register in a load/store LdSt.
Definition: AArch64InstrInfo.cpp:2345
llvm::AArch64InstrInfo::AArch64InstrInfo
AArch64InstrInfo(const AArch64Subtarget &STI)
Definition: AArch64InstrInfo.cpp:70
llvm::AArch64InstrInfo::isAddImmediate
Optional< RegImmPair > isAddImmediate(const MachineInstr &MI, Register Reg) const override
Definition: AArch64InstrInfo.cpp:7072
llvm::AArch64InstrInfo::getUnscaledLdSt
static Optional< unsigned > getUnscaledLdSt(unsigned Opc)
Returns the unscaled load/store for the scaled load/store opcode, if there is a corresponding unscale...
Definition: AArch64InstrInfo.cpp:1997
llvm::Module
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:67
llvm::MachineInstr::MIFlag
MIFlag
Definition: MachineInstr.h:80
llvm::MachineFunction
Definition: MachineFunction.h:227
llvm::MachineBasicBlock::iterator
MachineInstrBundleIterator< MachineInstr > iterator
Definition: MachineBasicBlock.h:233
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:33
llvm::AArch64InstrInfo::shouldClusterMemOps
bool shouldClusterMemOps(ArrayRef< const MachineOperand * > BaseOps1, ArrayRef< const MachineOperand * > BaseOps2, unsigned NumLoads, unsigned NumBytes) const override
Detect opportunities for ldp/stp formation.
Definition: AArch64InstrInfo.cpp:2758
llvm::AArch64InstrInfo::isGPRCopy
static bool isGPRCopy(const MachineInstr &MI)
Does this instruction rename a GPR without modifying bits?
Definition: AArch64InstrInfo.cpp:1853
Cond
SmallVector< MachineOperand, 4 > Cond
Definition: BasicBlockSections.cpp:167
llvm::AArch64InstrInfo::isPTestLikeOpcode
bool isPTestLikeOpcode(unsigned Opc) const
Returns true if the opcode is for an SVE instruction that sets the condition codes as if it's results...
Definition: AArch64InstrInfo.cpp:7198
MBBI
MachineBasicBlock MachineBasicBlock::iterator MBBI
Definition: AArch64SLSHardening.cpp:75
llvm::AArch64::FalseLanesMask
@ FalseLanesMask
Definition: AArch64InstrInfo.h:478
llvm::AArch64InstrInfo::isCopyInstrImpl
Optional< DestSourcePair > isCopyInstrImpl(const MachineInstr &MI) const override
If the specific machine instruction is an instruction that moves/copies value from one register to an...
Definition: AArch64InstrInfo.cpp:7053
llvm::AArch64InstrInfo::decomposeMachineOperandsTargetFlags
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
Definition: AArch64InstrInfo.cpp:5877
llvm::StackOffset
StackOffset is a class to represent an offset with 2 dimensions, named fixed and scalable,...
Definition: TypeSize.h:134
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::AArch64RegisterInfo
Definition: AArch64RegisterInfo.h:26
llvm::CodeGenOpt::Level
Level
Definition: CodeGen.h:52
llvm::AArch64InstrInfo::canInsertSelect
bool canInsertSelect(const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, Register, Register, Register, int &, int &, int &) const override
Definition: AArch64InstrInfo.cpp:608
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::AArch64InstrInfo::loadRegFromStackSlot
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Definition: AArch64InstrInfo.cpp:3423
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::AArch64InstrInfo::getSerializableMachineMemOperandTargetFlags
ArrayRef< std::pair< MachineMemOperand::Flags, const char * > > getSerializableMachineMemOperandTargetFlags() const override
Definition: AArch64InstrInfo.cpp:5911
llvm::AArch64::DestructiveUnary
@ DestructiveUnary
Definition: AArch64InstrInfo.h:468
llvm::ISD::FrameIndex
@ FrameIndex
Definition: ISDOpcodes.h:73
llvm::AArch64InstrInfo::decomposeStackOffsetForFrameOffsets
static void decomposeStackOffsetForFrameOffsets(const StackOffset &Offset, int64_t &NumBytes, int64_t &NumPredicateVectors, int64_t &NumDataVectors)
Returns the offset in parts to which this frame offset can be decomposed for the purpose of describin...
Definition: AArch64InstrInfo.cpp:3582
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::AArch64::ElementSizeD
@ ElementSizeD
Definition: AArch64InstrInfo.h:461
llvm::AArch64InstrInfo::getRegisterInfo
const AArch64RegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
Definition: AArch64InstrInfo.h:48
llvm::AArch64::DestructiveBinaryShImmUnpred
@ DestructiveBinaryShImmUnpred
Definition: AArch64InstrInfo.h:470
uint16_t
llvm::AArch64InstrInfo::convertToFlagSettingOpc
static unsigned convertToFlagSettingOpc(unsigned Opc, bool &Is64Bit)
Return the opcode that set flags when possible.
Definition: AArch64InstrInfo.cpp:2120
llvm::ISD::BR
@ BR
Control flow instructions. These all have token chains.
Definition: ISDOpcodes.h:922
llvm::AArch64InstrInfo::storeRegToStackSlot
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Definition: AArch64InstrInfo.cpp:3269
llvm::AArch64::ElementSizeMask
@ ElementSizeMask
Definition: AArch64InstrInfo.h:456
llvm::TypeSize
Definition: TypeSize.h:417
llvm::AArch64InstrInfo::getMemOpInfo
static bool getMemOpInfo(unsigned Opcode, TypeSize &Scale, unsigned &Width, int64_t &MinOffset, int64_t &MaxOffset)
Returns true if opcode Opc is a memory operation.
Definition: AArch64InstrInfo.cpp:2352
llvm::AArch64::DestructiveInstTypeMask
@ DestructiveInstTypeMask
Definition: AArch64InstrInfo.h:465
llvm::AArch64InstrInfo::isLdStPairSuppressed
static bool isLdStPairSuppressed(const MachineInstr &MI)
Return true if pairing the given load or store is hinted to be unprofitable.
Definition: AArch64InstrInfo.cpp:1952
llvm::AArch64InstrInfo::decomposeStackOffsetForDwarfOffsets
static void decomposeStackOffsetForDwarfOffsets(const StackOffset &Offset, int64_t &ByteSized, int64_t &VGSized)
Definition: AArch64InstrInfo.cpp:3563
llvm::AArch64InstrInfo::analyzeBranchPredicate
bool analyzeBranchPredicate(MachineBasicBlock &MBB, MachineBranchPredicate &MBP, bool AllowModify) const override
Definition: AArch64InstrInfo.cpp:357
llvm::LiveIntervals
Definition: LiveIntervals.h:54
llvm::AArch64InstrInfo::insertSelect
void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, Register DstReg, ArrayRef< MachineOperand > Cond, Register TrueReg, Register FalseReg) const override
Definition: AArch64InstrInfo.cpp:657
llvm::AArch64InstrInfo::isBranchOffsetInRange
bool isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const override
Definition: AArch64InstrInfo.cpp:209
llvm::AMDGPU::Hwreg::Width
Width
Definition: SIDefines.h:403
llvm::AArch64::DestructiveBinaryComm
@ DestructiveBinaryComm
Definition: AArch64InstrInfo.h:472
TSFLAG_FALSE_LANE_TYPE
#define TSFLAG_FALSE_LANE_TYPE(X)
Definition: AArch64InstrInfo.h:449
llvm::AArch64FrameOffsetStatus
AArch64FrameOffsetStatus
Use to report the frame offset status in isAArch64FrameOffsetLegal.
Definition: AArch64InstrInfo.h:375
llvm::AArch64::DestructiveBinary
@ DestructiveBinary
Definition: AArch64InstrInfo.h:471
llvm::Pattern
Definition: FileCheckImpl.h:615
llvm::TargetInstrInfo::foldMemoryOperandImpl
virtual MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const
Target-dependent implementation for foldMemoryOperand.
Definition: TargetInstrInfo.h:1194
llvm::AArch64InstrInfo::foldMemoryOperandImpl
MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const override
Definition: AArch64InstrInfo.cpp:3748
DefMI
MachineInstrBuilder MachineInstrBuilder & DefMI
Definition: AArch64ExpandPseudoInsts.cpp:101
llvm::AArch64::getSVEPseudoMap
int getSVEPseudoMap(uint16_t Opcode)
llvm::AArch64InstrInfo::isExtendLikelyToBeFolded
bool isExtendLikelyToBeFolded(MachineInstr &ExtMI, MachineRegisterInfo &MRI) const override
Definition: AArch64InstrInfo.cpp:7174
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
llvm::AArch64InstrInfo::reverseBranchCondition
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
Definition: AArch64InstrInfo.cpp:407
llvm::AArch64::DestructiveBinaryImm
@ DestructiveBinaryImm
Definition: AArch64InstrInfo.h:469
llvm::AArch64InstrInfo::insertOutlinedCall
MachineBasicBlock::iterator insertOutlinedCall(Module &M, MachineBasicBlock &MBB, MachineBasicBlock::iterator &It, MachineFunction &MF, const outliner::Candidate &C) const override
Definition: AArch64InstrInfo.cpp:6975
llvm::AArch64::DestructiveBinaryCommWithRev
@ DestructiveBinaryCommWithRev
Definition: AArch64InstrInfo.h:473
llvm::AArch64InstrInfo::getMemScale
static int getMemScale(unsigned Opc)
Scaling factor for (scaled or unscaled) load or store.
Definition: AArch64InstrInfo.cpp:2633
llvm::AArch64InstrInfo::optimizeCondBranch
bool optimizeCondBranch(MachineInstr &MI) const override
Replace csincr-branch sequence by simple conditional branch.
Definition: AArch64InstrInfo.cpp:5739
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::AArch64InstrInfo::isFalkorShiftExtFast
static bool isFalkorShiftExtFast(const MachineInstr &MI)
Returns true if the instruction has a shift by immediate that can be executed in one cycle less.
Definition: AArch64InstrInfo.cpp:882
llvm::isPTrueOpcode
static bool isPTrueOpcode(unsigned Opc)
Definition: AArch64InstrInfo.h:431
llvm::AArch64Subtarget
Definition: AArch64Subtarget.h:38
llvm::AArch64InstrInfo::isCandidateToMergeOrPair
bool isCandidateToMergeOrPair(const MachineInstr &MI) const
Return true if this is a load/store that can be potentially paired/merged.
Definition: AArch64InstrInfo.cpp:2210
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::AArch64::FalseLanesUndef
@ FalseLanesUndef
Definition: AArch64InstrInfo.h:480
llvm::AArch64::getSVENonRevInstr
int getSVENonRevInstr(uint16_t Opcode)
llvm::AArch64InstrInfo::isAssociativeAndCommutative
bool isAssociativeAndCommutative(const MachineInstr &Inst) const override
Return true when Inst is associative and commutative so that it can be reassociated.
Definition: AArch64InstrInfo.cpp:4219
llvm::AArch64InstrInfo::isSubregFoldable
bool isSubregFoldable() const override
Definition: AArch64InstrInfo.h:173
llvm::AArch64InstrInfo::isAsCheapAsAMove
bool isAsCheapAsAMove(const MachineInstr &MI) const override
Definition: AArch64InstrInfo.cpp:803
llvm::AArch64InstrInfo::isSEHInstruction
static bool isSEHInstruction(const MachineInstr &MI)
Return true if the instructions is a SEH instruciton used for unwinding on Windows.
Definition: AArch64InstrInfo.cpp:1004
llvm::AArch64InstrInfo::isStoreToStackSlot
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
Definition: AArch64InstrInfo.cpp:1927
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:22
llvm::MachineCombinerPattern
MachineCombinerPattern
These are instruction patterns matched by the machine combiner pass.
Definition: MachineCombinerPattern.h:20
llvm::AArch64InstrInfo::analyzeBranch
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override
Definition: AArch64InstrInfo.cpp:239
llvm::AArch64::ElementSizeH
@ ElementSizeH
Definition: AArch64InstrInfo.h:459