LLVM  14.0.0git
Classes | Public Member Functions | Static Public Member Functions | Static Public Attributes | Protected Member Functions | Static Protected Member Functions | List of all members
llvm::TargetInstrInfo Class Reference

TargetInstrInfo - Interface to description of machine instruction set. More...

#include "llvm/CodeGen/TargetInstrInfo.h"

Inheritance diagram for llvm::TargetInstrInfo:
Inheritance graph
[legend]
Collaboration diagram for llvm::TargetInstrInfo:
Collaboration graph
[legend]

Classes

struct  MachineBranchPredicate
 Represents a predicate at the MachineFunction level. More...
 
class  PipelinerLoopInfo
 Object returned by analyzeLoopForPipelining. More...
 
struct  RegSubRegPair
 A pair composed of a register and a sub-register index. More...
 
struct  RegSubRegPairAndIdx
 A pair composed of a pair of a register and a sub-register index, and another sub-register index. More...
 

Public Member Functions

 TargetInstrInfo (unsigned CFSetupOpcode=~0u, unsigned CFDestroyOpcode=~0u, unsigned CatchRetOpcode=~0u, unsigned ReturnOpcode=~0u)
 
 TargetInstrInfo (const TargetInstrInfo &)=delete
 
TargetInstrInfooperator= (const TargetInstrInfo &)=delete
 
virtual ~TargetInstrInfo ()
 
virtual const TargetRegisterClassgetRegClass (const MCInstrDesc &MCID, unsigned OpNum, const TargetRegisterInfo *TRI, const MachineFunction &MF) const
 Given a machine instruction descriptor, returns the register class constraint for OpNum, or NULL. More...
 
bool isTriviallyReMaterializable (const MachineInstr &MI, AAResults *AA=nullptr) const
 Return true if the instruction is trivially rematerializable, meaning it has no side effects and requires no operands that aren't always available. More...
 
virtual bool isIgnorableUse (const MachineOperand &MO) const
 Given MO is a PhysReg use return if it can be ignored for the purpose of instruction rematerialization. More...
 
unsigned getCallFrameSetupOpcode () const
 These methods return the opcode of the frame setup/destroy instructions if they exist (-1 otherwise). More...
 
unsigned getCallFrameDestroyOpcode () const
 
bool isFrameInstr (const MachineInstr &I) const
 Returns true if the argument is a frame pseudo instruction. More...
 
bool isFrameSetup (const MachineInstr &I) const
 Returns true if the argument is a frame setup pseudo instruction. More...
 
int64_t getFrameSize (const MachineInstr &I) const
 Returns size of the frame associated with the given frame instruction. More...
 
int64_t getFrameTotalSize (const MachineInstr &I) const
 Returns the total frame size, which is made up of the space set up inside the pair of frame start-stop instructions and the space that is set up prior to the pair. More...
 
unsigned getCatchReturnOpcode () const
 
unsigned getReturnOpcode () const
 
virtual int getSPAdjust (const MachineInstr &MI) const
 Returns the actual stack pointer adjustment made by an instruction as part of a call sequence. More...
 
virtual bool isCoalescableExtInstr (const MachineInstr &MI, Register &SrcReg, Register &DstReg, unsigned &SubIdx) const
 Return true if the instruction is a "coalescable" extension instruction. More...
 
virtual unsigned isLoadFromStackSlot (const MachineInstr &MI, int &FrameIndex) const
 If the specified machine instruction is a direct load from a stack slot, return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot. More...
 
virtual unsigned isLoadFromStackSlot (const MachineInstr &MI, int &FrameIndex, unsigned &MemBytes) const
 Optional extension of isLoadFromStackSlot that returns the number of bytes loaded from the stack. More...
 
virtual unsigned isLoadFromStackSlotPostFE (const MachineInstr &MI, int &FrameIndex) const
 Check for post-frame ptr elimination stack locations as well. More...
 
virtual bool hasLoadFromStackSlot (const MachineInstr &MI, SmallVectorImpl< const MachineMemOperand * > &Accesses) const
 If the specified machine instruction has a load from a stack slot, return true along with the FrameIndices of the loaded stack slot and the machine mem operands containing the reference. More...
 
virtual unsigned isStoreToStackSlot (const MachineInstr &MI, int &FrameIndex) const
 If the specified machine instruction is a direct store to a stack slot, return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot. More...
 
virtual unsigned isStoreToStackSlot (const MachineInstr &MI, int &FrameIndex, unsigned &MemBytes) const
 Optional extension of isStoreToStackSlot that returns the number of bytes stored to the stack. More...
 
virtual unsigned isStoreToStackSlotPostFE (const MachineInstr &MI, int &FrameIndex) const
 Check for post-frame ptr elimination stack locations as well. More...
 
virtual bool hasStoreToStackSlot (const MachineInstr &MI, SmallVectorImpl< const MachineMemOperand * > &Accesses) const
 If the specified machine instruction has a store to a stack slot, return true along with the FrameIndices of the loaded stack slot and the machine mem operands containing the reference. More...
 
virtual bool isStackSlotCopy (const MachineInstr &MI, int &DestFrameIndex, int &SrcFrameIndex) const
 Return true if the specified machine instruction is a copy of one stack slot to another and has no other effect. More...
 
virtual bool getStackSlotRange (const TargetRegisterClass *RC, unsigned SubIdx, unsigned &Size, unsigned &Offset, const MachineFunction &MF) const
 Compute the size in bytes and offset within a stack slot of a spilled register or subregister. More...
 
bool isUnspillableTerminator (const MachineInstr *MI) const
 Return true if the given instruction is terminator that is unspillable, according to isUnspillableTerminatorImpl. More...
 
virtual unsigned getInstSizeInBytes (const MachineInstr &MI) const
 Returns the size in bytes of the specified MachineInstr, or ~0U when this function is not implemented by a target. More...
 
virtual bool isAsCheapAsAMove (const MachineInstr &MI) const
 Return true if the instruction is as cheap as a move instruction. More...
 
virtual bool shouldSink (const MachineInstr &MI) const
 Return true if the instruction should be sunk by MachineSink. More...
 
virtual void reMaterialize (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, unsigned SubIdx, const MachineInstr &Orig, const TargetRegisterInfo &TRI) const
 Re-issue the specified 'original' instruction at the specific location targeting a new destination register. More...
 
virtual MachineInstrduplicate (MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, const MachineInstr &Orig) const
 Clones instruction or the whole instruction bundle Orig and insert into MBB before InsertBefore. More...
 
virtual MachineInstrconvertToThreeAddress (MachineInstr &MI, LiveVariables *LV, LiveIntervals *LIS) const
 This method must be implemented by targets that set the M_CONVERTIBLE_TO_3_ADDR flag. More...
 
MachineInstrcommuteInstruction (MachineInstr &MI, bool NewMI=false, unsigned OpIdx1=CommuteAnyOperandIndex, unsigned OpIdx2=CommuteAnyOperandIndex) const
 This method commutes the operands of the given machine instruction MI. More...
 
virtual bool findCommutedOpIndices (const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const
 Returns true iff the routine could find two commutable operands in the given machine instruction. More...
 
virtual bool hasCommutePreference (MachineInstr &MI, bool &Commute) const
 Returns true if the target has a preference on the operands order of the given machine instruction. More...
 
bool getRegSequenceInputs (const MachineInstr &MI, unsigned DefIdx, SmallVectorImpl< RegSubRegPairAndIdx > &InputRegs) const
 Build the equivalent inputs of a REG_SEQUENCE for the given MI and DefIdx. More...
 
bool getExtractSubregInputs (const MachineInstr &MI, unsigned DefIdx, RegSubRegPairAndIdx &InputReg) const
 Build the equivalent inputs of a EXTRACT_SUBREG for the given MI and DefIdx. More...
 
bool getInsertSubregInputs (const MachineInstr &MI, unsigned DefIdx, RegSubRegPair &BaseReg, RegSubRegPairAndIdx &InsertedReg) const
 Build the equivalent inputs of a INSERT_SUBREG for the given MI and DefIdx. More...
 
virtual bool produceSameValue (const MachineInstr &MI0, const MachineInstr &MI1, const MachineRegisterInfo *MRI=nullptr) const
 Return true if two machine instructions would produce identical values. More...
 
virtual bool isBranchOffsetInRange (unsigned BranchOpc, int64_t BrOffset) const
 
virtual MachineBasicBlockgetBranchDestBlock (const MachineInstr &MI) const
 
virtual void insertIndirectBranch (MachineBasicBlock &MBB, MachineBasicBlock &NewDestBB, MachineBasicBlock &RestoreBB, const DebugLoc &DL, int64_t BrOffset=0, RegScavenger *RS=nullptr) const
 Insert an unconditional indirect branch at the end of MBB to NewDestBB. More...
 
virtual bool analyzeBranch (MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const
 Analyze the branching code at the end of MBB, returning true if it cannot be understood (e.g. More...
 
virtual bool analyzeBranchPredicate (MachineBasicBlock &MBB, MachineBranchPredicate &MBP, bool AllowModify=false) const
 Analyze the branching code at the end of MBB and parse it into the MachineBranchPredicate structure if possible. More...
 
virtual unsigned removeBranch (MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const
 Remove the branching code at the end of the specific MBB. More...
 
virtual unsigned insertBranch (MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const
 Insert branch code into the end of the specified MachineBasicBlock. More...
 
unsigned insertUnconditionalBranch (MachineBasicBlock &MBB, MachineBasicBlock *DestBB, const DebugLoc &DL, int *BytesAdded=nullptr) const
 
virtual std::unique_ptr< PipelinerLoopInfoanalyzeLoopForPipelining (MachineBasicBlock *LoopBB) const
 Analyze loop L, which must be a single-basic-block loop, and if the conditions can be understood enough produce a PipelinerLoopInfo object. More...
 
virtual bool analyzeLoop (MachineLoop &L, MachineInstr *&IndVarInst, MachineInstr *&CmpInst) const
 Analyze the loop code, return true if it cannot be understood. More...
 
virtual unsigned reduceLoopCount (MachineBasicBlock &MBB, MachineBasicBlock &PreHeader, MachineInstr *IndVar, MachineInstr &Cmp, SmallVectorImpl< MachineOperand > &Cond, SmallVectorImpl< MachineInstr * > &PrevInsts, unsigned Iter, unsigned MaxIter) const
 Generate code to reduce the loop iteration by one and check if the loop is finished. More...
 
virtual void ReplaceTailWithBranchTo (MachineBasicBlock::iterator Tail, MachineBasicBlock *NewDest) const
 Delete the instruction OldInst and everything after it, replacing it with an unconditional branch to NewDest. More...
 
virtual bool isLegalToSplitMBBAt (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const
 Return true if it's legal to split the given basic block at the specified instruction (i.e. More...
 
virtual bool isProfitableToIfCvt (MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const
 Return true if it's profitable to predicate instructions with accumulated instruction latency of "NumCycles" of the specified basic block, where the probability of the instructions being executed is given by Probability, and Confidence is a measure of our confidence that it will be properly predicted. More...
 
virtual bool isProfitableToIfCvt (MachineBasicBlock &TMBB, unsigned NumTCycles, unsigned ExtraTCycles, MachineBasicBlock &FMBB, unsigned NumFCycles, unsigned ExtraFCycles, BranchProbability Probability) const
 Second variant of isProfitableToIfCvt. More...
 
virtual bool isProfitableToDupForIfCvt (MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const
 Return true if it's profitable for if-converter to duplicate instructions of specified accumulated instruction latencies in the specified MBB to enable if-conversion. More...
 
virtual unsigned extraSizeToPredicateInstructions (const MachineFunction &MF, unsigned NumInsts) const
 Return the increase in code size needed to predicate a contiguous run of NumInsts instructions. More...
 
virtual unsigned predictBranchSizeForIfCvt (MachineInstr &MI) const
 Return an estimate for the code size reduction (in bytes) which will be caused by removing the given branch instruction during if-conversion. More...
 
virtual bool isProfitableToUnpredicate (MachineBasicBlock &TMBB, MachineBasicBlock &FMBB) const
 Return true if it's profitable to unpredicate one side of a 'diamond', i.e. More...
 
virtual bool canInsertSelect (const MachineBasicBlock &MBB, ArrayRef< MachineOperand > Cond, Register DstReg, Register TrueReg, Register FalseReg, int &CondCycles, int &TrueCycles, int &FalseCycles) const
 Return true if it is possible to insert a select instruction that chooses between TrueReg and FalseReg based on the condition code in Cond. More...
 
virtual void insertSelect (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register DstReg, ArrayRef< MachineOperand > Cond, Register TrueReg, Register FalseReg) const
 Insert a select instruction into MBB before I that will copy TrueReg to DstReg when Cond is true, and FalseReg to DstReg when Cond is false. More...
 
virtual bool analyzeSelect (const MachineInstr &MI, SmallVectorImpl< MachineOperand > &Cond, unsigned &TrueOp, unsigned &FalseOp, bool &Optimizable) const
 Analyze the given select instruction, returning true if it cannot be understood. More...
 
virtual MachineInstroptimizeSelect (MachineInstr &MI, SmallPtrSetImpl< MachineInstr * > &NewMIs, bool PreferFalse=false) const
 Given a select instruction that was understood by analyzeSelect and returned Optimizable = true, attempt to optimize MI by merging it with one of its operands. More...
 
virtual void copyPhysReg (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const
 Emit instructions to copy a pair of physical registers. More...
 
virtual bool isPCRelRegisterOperandLegal (const MachineOperand &MO) const
 Allow targets to tell MachineVerifier whether a specific register MachineOperand can be used as part of PC-relative addressing. More...
 
Optional< DestSourcePairisCopyInstr (const MachineInstr &MI) const
 If the specific machine instruction is a instruction that moves/copies value from one register to another register return destination and source registers as machine operands. More...
 
virtual Optional< RegImmPairisAddImmediate (const MachineInstr &MI, Register Reg) const
 If the specific machine instruction is an instruction that adds an immediate value and a physical register, and stores the result in the given physical register Reg, return a pair of the source register and the offset which has been added. More...
 
virtual bool getConstValDefinedInReg (const MachineInstr &MI, const Register Reg, int64_t &ImmVal) const
 Returns true if MI is an instruction that defines Reg to have a constant value and the value is recorded in ImmVal. More...
 
virtual void storeRegToStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const
 Store the specified register of the given register class to the specified stack frame index. More...
 
virtual void loadRegFromStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const
 Load the specified register of the given register class from the specified stack frame index. More...
 
virtual bool expandPostRAPseudo (MachineInstr &MI) const
 This function is called for all pseudo instructions that remain after register allocation. More...
 
virtual bool isSubregFoldable () const
 Check whether the target can fold a load that feeds a subreg operand (or a subreg operand that feeds a store). More...
 
virtual std::pair< unsigned, unsigned > getPatchpointUnfoldableRange (const MachineInstr &MI) const
 For a patchpoint, stackmap, or statepoint intrinsic, return the range of operands which can't be folded into stack references. More...
 
MachineInstrfoldMemoryOperand (MachineInstr &MI, ArrayRef< unsigned > Ops, int FI, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const
 Attempt to fold a load or store of the specified stack slot into the specified machine instruction for the specified operand(s). More...
 
MachineInstrfoldMemoryOperand (MachineInstr &MI, ArrayRef< unsigned > Ops, MachineInstr &LoadMI, LiveIntervals *LIS=nullptr) const
 Same as the previous version except it allows folding of any load and store from / to any address, not just from a specific stack slot. More...
 
virtual bool getMachineCombinerPatterns (MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &Patterns, bool DoRegPressureReduce) const
 Return true when there is potentially a faster code sequence for an instruction chain ending in Root. More...
 
virtual bool shouldReduceRegisterPressure (MachineBasicBlock *MBB, RegisterClassInfo *RegClassInfo) const
 Return true if target supports reassociation of instructions in machine combiner pass to reduce register pressure for a given BB. More...
 
virtual void finalizeInsInstrs (MachineInstr &Root, MachineCombinerPattern &P, SmallVectorImpl< MachineInstr * > &InsInstrs) const
 Fix up the placeholder we may add in genAlternativeCodeSequence(). More...
 
virtual bool isThroughputPattern (MachineCombinerPattern Pattern) const
 Return true when a code sequence can improve throughput. More...
 
bool isReassociationCandidate (const MachineInstr &Inst, bool &Commuted) const
 Return true if the input \P Inst is part of a chain of dependent ops that are suitable for reassociation, otherwise return false. More...
 
virtual bool isAssociativeAndCommutative (const MachineInstr &Inst) const
 Return true when \P Inst is both associative and commutative. More...
 
virtual bool hasReassociableOperands (const MachineInstr &Inst, const MachineBasicBlock *MBB) const
 Return true when \P Inst has reassociable operands in the same \P MBB. More...
 
bool hasReassociableSibling (const MachineInstr &Inst, bool &Commuted) const
 Return true when \P Inst has reassociable sibling. More...
 
virtual void genAlternativeCodeSequence (MachineInstr &Root, MachineCombinerPattern Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, DenseMap< unsigned, unsigned > &InstIdxForVirtReg) const
 When getMachineCombinerPatterns() finds patterns, this function generates the instructions that could replace the original code sequence. More...
 
void reassociateOps (MachineInstr &Root, MachineInstr &Prev, MachineCombinerPattern Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, DenseMap< unsigned, unsigned > &InstrIdxForVirtReg) const
 Attempt to reassociate \P Root and \P Prev according to \P Pattern to reduce critical path length. More...
 
virtual int getExtendResourceLenLimit () const
 The limit on resource length extension we accept in MachineCombiner Pass. More...
 
virtual void setSpecialOperandAttr (MachineInstr &OldMI1, MachineInstr &OldMI2, MachineInstr &NewMI1, MachineInstr &NewMI2) const
 This is an architecture-specific helper function of reassociateOps. More...
 
virtual void setSpecialOperandAttr (MachineInstr &MI, uint16_t Flags) const
 
virtual bool useMachineCombiner () const
 Return true when a target supports MachineCombiner. More...
 
virtual bool canCopyGluedNodeDuringSchedule (SDNode *N) const
 Return true if the given SDNode can be copied during scheduling even if it has glue. More...
 
virtual unsigned getAddressSpaceForPseudoSourceKind (unsigned Kind) const
 getAddressSpaceForPseudoSourceKind - Given the kind of memory (e.g. More...
 
virtual bool unfoldMemoryOperand (MachineFunction &MF, MachineInstr &MI, unsigned Reg, bool UnfoldLoad, bool UnfoldStore, SmallVectorImpl< MachineInstr * > &NewMIs) const
 unfoldMemoryOperand - Separate a single instruction which folded a load or a store or a load and a store into two or more instruction. More...
 
virtual bool unfoldMemoryOperand (SelectionDAG &DAG, SDNode *N, SmallVectorImpl< SDNode * > &NewNodes) const
 
virtual unsigned getOpcodeAfterMemoryUnfold (unsigned Opc, bool UnfoldLoad, bool UnfoldStore, unsigned *LoadRegIndex=nullptr) const
 Returns the opcode of the would be new instruction after load / store are unfolded from an instruction of the specified opcode. More...
 
virtual bool areLoadsFromSameBasePtr (SDNode *Load1, SDNode *Load2, int64_t &Offset1, int64_t &Offset2) const
 This is used by the pre-regalloc scheduler to determine if two loads are loading from the same base address. More...
 
virtual bool shouldScheduleLoadsNear (SDNode *Load1, SDNode *Load2, int64_t Offset1, int64_t Offset2, unsigned NumLoads) const
 This is a used by the pre-regalloc scheduler to determine (in conjunction with areLoadsFromSameBasePtr) if two loads should be scheduled together. More...
 
bool getMemOperandWithOffset (const MachineInstr &MI, const MachineOperand *&BaseOp, int64_t &Offset, bool &OffsetIsScalable, const TargetRegisterInfo *TRI) const
 Get the base operand and byte offset of an instruction that reads/writes memory. More...
 
virtual bool getMemOperandsWithOffsetWidth (const MachineInstr &MI, SmallVectorImpl< const MachineOperand * > &BaseOps, int64_t &Offset, bool &OffsetIsScalable, unsigned &Width, const TargetRegisterInfo *TRI) const
 Get zero or more base operands and the byte offset of an instruction that reads/writes memory. More...
 
virtual bool getBaseAndOffsetPosition (const MachineInstr &MI, unsigned &BasePos, unsigned &OffsetPos) const
 Return true if the instruction contains a base register and offset. More...
 
virtual Optional< ExtAddrModegetAddrModeFromMemoryOp (const MachineInstr &MemI, const TargetRegisterInfo *TRI) const
 Target dependent implementation to get the values constituting the address MachineInstr that is accessing memory. More...
 
virtual bool preservesZeroValueInReg (const MachineInstr *MI, const Register NullValueReg, const TargetRegisterInfo *TRI) const
 Returns true if MI's Def is NullValueReg, and the MI does not change the Zero value. More...
 
virtual bool getIncrementValue (const MachineInstr &MI, int &Value) const
 If the instruction is an increment of a constant value, return the amount. More...
 
virtual bool shouldClusterMemOps (ArrayRef< const MachineOperand * > BaseOps1, ArrayRef< const MachineOperand * > BaseOps2, unsigned NumLoads, unsigned NumBytes) const
 Returns true if the two given memory operations should be scheduled adjacent. More...
 
virtual bool reverseBranchCondition (SmallVectorImpl< MachineOperand > &Cond) const
 Reverses the branch condition of the specified condition list, returning false on success and true if it cannot be reversed. More...
 
virtual void insertNoop (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const
 Insert a noop into the instruction stream at the specified point. More...
 
virtual void insertNoops (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned Quantity) const
 Insert noops into the instruction stream at the specified point. More...
 
virtual MCInst getNop () const
 Return the noop instruction to use for a noop. More...
 
virtual bool isPostIncrement (const MachineInstr &MI) const
 Return true for post-incremented instructions. More...
 
virtual bool isPredicated (const MachineInstr &MI) const
 Returns true if the instruction is already predicated. More...
 
virtual std::string createMIROperandComment (const MachineInstr &MI, const MachineOperand &Op, unsigned OpIdx, const TargetRegisterInfo *TRI) const
 
bool isUnpredicatedTerminator (const MachineInstr &MI) const
 Returns true if the instruction is a terminator instruction that has not been predicated. More...
 
virtual bool isUnconditionalTailCall (const MachineInstr &MI) const
 Returns true if MI is an unconditional tail call. More...
 
virtual bool canMakeTailCallConditional (SmallVectorImpl< MachineOperand > &Cond, const MachineInstr &TailCall) const
 Returns true if the tail call can be made conditional on BranchCond. More...
 
virtual void replaceBranchWithTailCall (MachineBasicBlock &MBB, SmallVectorImpl< MachineOperand > &Cond, const MachineInstr &TailCall) const
 Replace the conditional branch in MBB with a conditional tail call. More...
 
virtual bool PredicateInstruction (MachineInstr &MI, ArrayRef< MachineOperand > Pred) const
 Convert the instruction into a predicated instruction. More...
 
virtual bool SubsumesPredicate (ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const
 Returns true if the first specified predicate subsumes the second, e.g. More...
 
virtual bool ClobbersPredicate (MachineInstr &MI, std::vector< MachineOperand > &Pred, bool SkipDead) const
 If the specified instruction defines any predicate or condition code register(s) used for predication, returns true as well as the definition predicate(s) by reference. More...
 
virtual bool isPredicable (const MachineInstr &MI) const
 Return true if the specified instruction can be predicated. More...
 
virtual bool isSafeToMoveRegClassDefs (const TargetRegisterClass *RC) const
 Return true if it's safe to move a machine instruction that defines the specified register class. More...
 
virtual bool isSchedulingBoundary (const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const
 Test if the given instruction should be considered a scheduling boundary. More...
 
virtual unsigned getInlineAsmLength (const char *Str, const MCAsmInfo &MAI, const TargetSubtargetInfo *STI=nullptr) const
 Measure the specified inline asm to determine an approximation of its length. More...
 
virtual ScheduleHazardRecognizerCreateTargetHazardRecognizer (const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const
 Allocate and return a hazard recognizer to use for this target when scheduling the machine instructions before register allocation. More...
 
virtual ScheduleHazardRecognizerCreateTargetMIHazardRecognizer (const InstrItineraryData *, const ScheduleDAGMI *DAG) const
 Allocate and return a hazard recognizer to use for this target when scheduling the machine instructions before register allocation. More...
 
virtual ScheduleHazardRecognizerCreateTargetPostRAHazardRecognizer (const InstrItineraryData *, const ScheduleDAG *DAG) const
 Allocate and return a hazard recognizer to use for this target when scheduling the machine instructions after register allocation. More...
 
virtual ScheduleHazardRecognizerCreateTargetPostRAHazardRecognizer (const MachineFunction &MF) const
 Allocate and return a hazard recognizer to use for by non-scheduling passes. More...
 
bool usePreRAHazardRecognizer () const
 Provide a global flag for disabling the PreRA hazard recognizer that targets may choose to honor. More...
 
virtual bool analyzeCompare (const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int64_t &Mask, int64_t &Value) const
 For a comparison instruction, return the source registers in SrcReg and SrcReg2 if having two register operands, and the value it compares against in CmpValue. More...
 
virtual bool optimizeCompareInstr (MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int64_t Mask, int64_t Value, const MachineRegisterInfo *MRI) const
 See if the comparison instruction can be converted into something more efficient. More...
 
virtual bool optimizeCondBranch (MachineInstr &MI) const
 
virtual MachineInstroptimizeLoadInstr (MachineInstr &MI, const MachineRegisterInfo *MRI, Register &FoldAsLoadDefReg, MachineInstr *&DefMI) const
 Try to remove the load by folding it to a register operand at the use. More...
 
virtual bool FoldImmediate (MachineInstr &UseMI, MachineInstr &DefMI, Register Reg, MachineRegisterInfo *MRI) const
 'Reg' is known to be defined by a move immediate instruction, try to fold the immediate into the use instruction. More...
 
virtual unsigned getNumMicroOps (const InstrItineraryData *ItinData, const MachineInstr &MI) const
 Return the number of u-operations the given machine instruction will be decoded to on the target cpu. More...
 
bool isZeroCost (unsigned Opcode) const
 Return true for pseudo instructions that don't consume any machine resources in their current form. More...
 
virtual int getOperandLatency (const InstrItineraryData *ItinData, SDNode *DefNode, unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const
 
virtual int getOperandLatency (const InstrItineraryData *ItinData, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const
 Compute and return the use operand latency of a given pair of def and use. More...
 
virtual unsigned getInstrLatency (const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const
 Compute the instruction latency of a given instruction. More...
 
virtual unsigned getPredicationCost (const MachineInstr &MI) const
 
virtual int getInstrLatency (const InstrItineraryData *ItinData, SDNode *Node) const
 
unsigned defaultDefLatency (const MCSchedModel &SchedModel, const MachineInstr &DefMI) const
 Return the default expected latency for a def based on its opcode. More...
 
virtual bool isHighLatencyDef (int opc) const
 Return true if this opcode has high latency to its result. More...
 
virtual bool hasHighOperandLatency (const TargetSchedModel &SchedModel, const MachineRegisterInfo *MRI, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const
 Compute operand latency between a def of 'Reg' and a use in the current loop. More...
 
virtual bool hasLowDefLatency (const TargetSchedModel &SchedModel, const MachineInstr &DefMI, unsigned DefIdx) const
 Compute operand latency of a def of 'Reg'. More...
 
virtual bool verifyInstruction (const MachineInstr &MI, StringRef &ErrInfo) const
 Perform target-specific instruction verification. More...
 
virtual std::pair< uint16_t, uint16_tgetExecutionDomain (const MachineInstr &MI) const
 Return the current execution domain and bit mask of possible domains for instruction. More...
 
virtual void setExecutionDomain (MachineInstr &MI, unsigned Domain) const
 Change the opcode of MI to execute in Domain. More...
 
virtual unsigned getPartialRegUpdateClearance (const MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const
 Returns the preferred minimum clearance before an instruction with an unwanted partial register update. More...
 
virtual unsigned getUndefRegClearance (const MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const
 Return the minimum clearance before an instruction that reads an unused register. More...
 
virtual void breakPartialRegDependency (MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const
 Insert a dependency-breaking instruction before MI to eliminate an unwanted dependency on OpNum. More...
 
virtual DFAPacketizerCreateTargetScheduleState (const TargetSubtargetInfo &) const
 Create machine specific model for scheduling. More...
 
virtual bool areMemAccessesTriviallyDisjoint (const MachineInstr &MIa, const MachineInstr &MIb) const
 Sometimes, it is possible for the target to tell, even without aliasing information, that two MIs access different memory addresses. More...
 
virtual unsigned getMachineCSELookAheadLimit () const
 Return the value to use for the MachineCSE's LookAheadLimit, which is a heuristic used for CSE'ing phys reg defs. More...
 
virtual unsigned getMemOperandAACheckLimit () const
 Return the maximal number of alias checks on memory operands. More...
 
virtual ArrayRef< std::pair< int, const char * > > getSerializableTargetIndices () const
 Return an array that contains the ids of the target indices (used for the TargetIndex machine operand) and their names. More...
 
virtual std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags (unsigned) const
 Decompose the machine operand's target flags into two values - the direct target flag value and any of bit flags that are applied. More...
 
virtual ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags () const
 Return an array that contains the direct target flag values and their names. More...
 
virtual ArrayRef< std::pair< unsigned, const char * > > getSerializableBitmaskMachineOperandTargetFlags () const
 Return an array that contains the bitmask target flag values and their names. More...
 
virtual ArrayRef< std::pair< MachineMemOperand::Flags, const char * > > getSerializableMachineMemOperandTargetFlags () const
 Return an array that contains the MMO target flag values and their names. More...
 
virtual bool isTailCall (const MachineInstr &Inst) const
 Determines whether Inst is a tail call instruction. More...
 
virtual bool isBasicBlockPrologue (const MachineInstr &MI) const
 True if the instruction is bound to the top of its basic block and no other instructions shall be inserted before it. More...
 
virtual MachineInstrcreatePHIDestinationCopy (MachineBasicBlock &MBB, MachineBasicBlock::iterator InsPt, const DebugLoc &DL, Register Src, Register Dst) const
 During PHI eleimination lets target to make necessary checks and insert the copy to the PHI destination register in a target specific manner. More...
 
virtual MachineInstrcreatePHISourceCopy (MachineBasicBlock &MBB, MachineBasicBlock::iterator InsPt, const DebugLoc &DL, Register Src, unsigned SrcSubReg, Register Dst) const
 During PHI eleimination lets target to make necessary checks and insert the copy to the PHI destination register in a target specific manner. More...
 
virtual outliner::OutlinedFunction getOutliningCandidateInfo (std::vector< outliner::Candidate > &RepeatedSequenceLocs) const
 Returns a outliner::OutlinedFunction struct containing target-specific information for a set of outlining candidates. More...
 
virtual void mergeOutliningCandidateAttributes (Function &F, std::vector< outliner::Candidate > &Candidates) const
 Optional target hook to create the LLVM IR attributes for the outlined function. More...
 
virtual outliner::InstrType getOutliningType (MachineBasicBlock::iterator &MIT, unsigned Flags) const
 Returns how or if MI should be outlined. More...
 
virtual bool isMBBSafeToOutlineFrom (MachineBasicBlock &MBB, unsigned &Flags) const
 Optional target hook that returns true if MBB is safe to outline from, and returns any target-specific information in Flags. More...
 
virtual void buildOutlinedFrame (MachineBasicBlock &MBB, MachineFunction &MF, const outliner::OutlinedFunction &OF) const
 Insert a custom frame for outlined functions. More...
 
virtual MachineBasicBlock::iterator insertOutlinedCall (Module &M, MachineBasicBlock &MBB, MachineBasicBlock::iterator &It, MachineFunction &MF, const outliner::Candidate &C) const
 Insert a call to an outlined function into the program. More...
 
virtual bool isFunctionSafeToOutlineFrom (MachineFunction &MF, bool OutlineFromLinkOnceODRs) const
 Return true if the function can safely be outlined from. More...
 
virtual bool shouldOutlineFromFunctionByDefault (MachineFunction &MF) const
 Return true if the function should be outlined from by default. More...
 
virtual Optional< ParamLoadedValuedescribeLoadedValue (const MachineInstr &MI, Register Reg) const
 Produce the expression describing the MI loading a value into the physical register Reg. More...
 
virtual bool isExtendLikelyToBeFolded (MachineInstr &ExtMI, MachineRegisterInfo &MRI) const
 Given the generic extension instruction ExtMI, returns true if this extension is a likely candidate for being folded into an another instruction. More...
 
virtual const MIRFormattergetMIRFormatter () const
 Return MIR formatter to format/parse MIR operands. More...
 
virtual unsigned getTailDuplicateSize (CodeGenOpt::Level OptLevel) const
 Returns the target-specific default value for tail duplication. More...
 
virtual const MachineOperandgetCalleeOperand (const MachineInstr &MI) const
 Returns the callee operand from the given MI. More...
 
- Public Member Functions inherited from llvm::MCInstrInfo
void InitMCInstrInfo (const MCInstrDesc *D, const unsigned *NI, const char *ND, const uint8_t *DF, const ComplexDeprecationPredicate *CDI, unsigned NO)
 Initialize MCInstrInfo, called by TableGen auto-generated routines. More...
 
unsigned getNumOpcodes () const
 
const MCInstrDescget (unsigned Opcode) const
 Return the machine instruction descriptor that corresponds to the specified instruction opcode. More...
 
StringRef getName (unsigned Opcode) const
 Returns the name for the instructions with the given opcode. More...
 
bool getDeprecatedInfo (MCInst &MI, const MCSubtargetInfo &STI, std::string &Info) const
 Returns true if a certain instruction is deprecated and if so returns the reason in Info. More...
 

Static Public Member Functions

static bool isGenericOpcode (unsigned Opc)
 

Static Public Attributes

static const unsigned CommuteAnyOperandIndex = ~0U
 

Protected Member Functions

virtual bool isReallyTriviallyReMaterializable (const MachineInstr &MI, AAResults *AA) const
 For instructions with opcodes for which the M_REMATERIALIZABLE flag is set, this hook lets the target specify whether the instruction is actually trivially rematerializable, taking into consideration its operands. More...
 
virtual MachineInstrcommuteInstructionImpl (MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const
 This method commutes the operands of the given machine instruction MI. More...
 
virtual Optional< DestSourcePairisCopyInstrImpl (const MachineInstr &MI) const
 Target-dependent implementation for IsCopyInstr. More...
 
virtual bool isUnspillableTerminatorImpl (const MachineInstr *MI) const
 Return true if the given terminator MI is not expected to spill. More...
 
virtual MachineInstrfoldMemoryOperandImpl (MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const
 Target-dependent implementation for foldMemoryOperand. More...
 
virtual MachineInstrfoldMemoryOperandImpl (MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI, LiveIntervals *LIS=nullptr) const
 Target-dependent implementation for foldMemoryOperand. More...
 
virtual bool getRegSequenceLikeInputs (const MachineInstr &MI, unsigned DefIdx, SmallVectorImpl< RegSubRegPairAndIdx > &InputRegs) const
 Target-dependent implementation of getRegSequenceInputs. More...
 
virtual bool getExtractSubregLikeInputs (const MachineInstr &MI, unsigned DefIdx, RegSubRegPairAndIdx &InputReg) const
 Target-dependent implementation of getExtractSubregInputs. More...
 
virtual bool getInsertSubregLikeInputs (const MachineInstr &MI, unsigned DefIdx, RegSubRegPair &BaseReg, RegSubRegPairAndIdx &InsertedReg) const
 Target-dependent implementation of getInsertSubregInputs. More...
 

Static Protected Member Functions

static bool fixCommutedOpIndices (unsigned &ResultIdx1, unsigned &ResultIdx2, unsigned CommutableOpIdx1, unsigned CommutableOpIdx2)
 Assigns the (CommutableOpIdx1, CommutableOpIdx2) pair of commutable operand indices to (ResultIdx1, ResultIdx2). More...
 

Additional Inherited Members

- Public Types inherited from llvm::MCInstrInfo
using ComplexDeprecationPredicate = bool(*)(MCInst &, const MCSubtargetInfo &, std::string &)
 

Detailed Description

TargetInstrInfo - Interface to description of machine instruction set.

Definition at line 97 of file TargetInstrInfo.h.

Constructor & Destructor Documentation

◆ TargetInstrInfo() [1/2]

llvm::TargetInstrInfo::TargetInstrInfo ( unsigned  CFSetupOpcode = ~0u,
unsigned  CFDestroyOpcode = ~0u,
unsigned  CatchRetOpcode = ~0u,
unsigned  ReturnOpcode = ~0u 
)
inline

Definition at line 99 of file TargetInstrInfo.h.

◆ TargetInstrInfo() [2/2]

llvm::TargetInstrInfo::TargetInstrInfo ( const TargetInstrInfo )
delete

◆ ~TargetInstrInfo()

TargetInstrInfo::~TargetInstrInfo ( )
virtual

Definition at line 43 of file TargetInstrInfo.cpp.

Member Function Documentation

◆ analyzeBranch()

virtual bool llvm::TargetInstrInfo::analyzeBranch ( MachineBasicBlock MBB,
MachineBasicBlock *&  TBB,
MachineBasicBlock *&  FBB,
SmallVectorImpl< MachineOperand > &  Cond,
bool  AllowModify = false 
) const
inlinevirtual

Analyze the branching code at the end of MBB, returning true if it cannot be understood (e.g.

it's a switch dispatch or isn't implemented for a target). Upon success, this returns false and returns with the following information in various cases:

  1. If this block ends with no branches (it just falls through to its succ) just return false, leaving TBB/FBB null.
  2. If this block ends with only an unconditional branch, it sets TBB to be the destination block.
  3. If this block ends with a conditional branch and it falls through to a successor block, it sets TBB to be the branch destination block and a list of operands that evaluate the condition. These operands can be passed to other TargetInstrInfo methods to create new branches.
  4. If this block ends with a conditional branch followed by an unconditional branch, it returns the 'true' destination in TBB, the 'false' destination in FBB, and a list of operands that evaluate the condition. These operands can be passed to other TargetInstrInfo methods to create new branches.

Note that removeBranch and insertBranch must be implemented to support cases where this method returns success.

If AllowModify is true, then this routine is allowed to modify the basic block (e.g. delete instructions after the unconditional branch).

The CFG information in MBB.Predecessors and MBB.Successors must be valid before calling this function.

Definition at line 627 of file TargetInstrInfo.h.

Referenced by llvm::TailDuplicator::canTailDuplicate(), llvm::PeelingModuloScheduleExpander::CreateLCSSAExitingBlock(), and llvm::TailDuplicator::shouldTailDuplicate().

◆ analyzeBranchPredicate()

virtual bool llvm::TargetInstrInfo::analyzeBranchPredicate ( MachineBasicBlock MBB,
MachineBranchPredicate MBP,
bool  AllowModify = false 
) const
inlinevirtual

Analyze the branching code at the end of MBB and parse it into the MachineBranchPredicate structure if possible.

Returns false on success and true on failure.

If AllowModify is true, then this routine is allowed to modify the basic block (e.g. delete instructions after the unconditional branch).

Definition at line 669 of file TargetInstrInfo.h.

◆ analyzeCompare()

virtual bool llvm::TargetInstrInfo::analyzeCompare ( const MachineInstr MI,
Register SrcReg,
Register SrcReg2,
int64_t &  Mask,
int64_t &  Value 
) const
inlinevirtual

For a comparison instruction, return the source registers in SrcReg and SrcReg2 if having two register operands, and the value it compares against in CmpValue.

Return true if the comparison instruction can be analyzed.

Definition at line 1541 of file TargetInstrInfo.h.

◆ analyzeLoop()

virtual bool llvm::TargetInstrInfo::analyzeLoop ( MachineLoop L,
MachineInstr *&  IndVarInst,
MachineInstr *&  CmpInst 
) const
inlinevirtual

Analyze the loop code, return true if it cannot be understood.

Upon success, this function returns false and returns information about the induction variable and compare instruction used at the end.

Definition at line 761 of file TargetInstrInfo.h.

◆ analyzeLoopForPipelining()

virtual std::unique_ptr<PipelinerLoopInfo> llvm::TargetInstrInfo::analyzeLoopForPipelining ( MachineBasicBlock LoopBB) const
inlinevirtual

Analyze loop L, which must be a single-basic-block loop, and if the conditions can be understood enough produce a PipelinerLoopInfo object.

Definition at line 754 of file TargetInstrInfo.h.

Referenced by llvm::PeelingModuloScheduleExpander::expand().

◆ analyzeSelect()

virtual bool llvm::TargetInstrInfo::analyzeSelect ( const MachineInstr MI,
SmallVectorImpl< MachineOperand > &  Cond,
unsigned &  TrueOp,
unsigned &  FalseOp,
bool &  Optimizable 
) const
inlinevirtual

Analyze the given select instruction, returning true if it cannot be understood.

It is assumed that MI->isSelect() is true.

When successful, return the controlling condition and the operands that determine the true and false result values.

Result = SELECT Cond, TrueOp, FalseOp

Some targets can optimize select instructions, for example by predicating the instruction defining one of the operands. Such targets should set Optimizable.

Parameters
MISelect instruction to analyze.
CondCondition controlling the select.
TrueOpOperand number of the value selected when Cond is true.
FalseOpOperand number of the value selected when Cond is false.
OptimizableReturned as true if MI is optimizable.
Returns
False on success.

Definition at line 924 of file TargetInstrInfo.h.

References assert(), and MI.

◆ areLoadsFromSameBasePtr()

virtual bool llvm::TargetInstrInfo::areLoadsFromSameBasePtr ( SDNode Load1,
SDNode Load2,
int64_t &  Offset1,
int64_t &  Offset2 
) const
inlinevirtual

This is used by the pre-regalloc scheduler to determine if two loads are loading from the same base address.

It should only return true if the base pointers are the same and the only differences between the two addresses are the offset. It also returns the offsets by reference.

Definition at line 1311 of file TargetInstrInfo.h.

◆ areMemAccessesTriviallyDisjoint()

virtual bool llvm::TargetInstrInfo::areMemAccessesTriviallyDisjoint ( const MachineInstr MIa,
const MachineInstr MIb 
) const
inlinevirtual

Sometimes, it is possible for the target to tell, even without aliasing information, that two MIs access different memory addresses.

This function returns true if two MIs access different memory addresses and false otherwise.

Assumes any physical registers used to compute addresses have the same value for both instructions. (This is the most useful assumption for post-RA scheduling.)

See also MachineInstr::mayAlias, which is implemented on top of this function.

Definition at line 1793 of file TargetInstrInfo.h.

References assert(), and llvm::MachineInstr::mayLoadOrStore().

◆ breakPartialRegDependency()

virtual void llvm::TargetInstrInfo::breakPartialRegDependency ( MachineInstr MI,
unsigned  OpNum,
const TargetRegisterInfo TRI 
) const
inlinevirtual

Insert a dependency-breaking instruction before MI to eliminate an unwanted dependency on OpNum.

If it wasn't possible to avoid a def in the last N instructions before MI (see getPartialRegUpdateClearance), this hook will be called to break the unwanted dependency.

On x86, an xorps instruction can be used as a dependency breaker:

addps xmm1, xmm0 movaps xmm0, (rax) xorps xmm0, xmm0 cvtsi2ss rbx, xmm0

An <imp-kill> operand should be added to MI if an instruction was inserted. This ties the instructions together in the post-ra scheduler.

Definition at line 1772 of file TargetInstrInfo.h.

◆ buildOutlinedFrame()

virtual void llvm::TargetInstrInfo::buildOutlinedFrame ( MachineBasicBlock MBB,
MachineFunction MF,
const outliner::OutlinedFunction OF 
) const
inlinevirtual

Insert a custom frame for outlined functions.

Definition at line 1937 of file TargetInstrInfo.h.

References llvm_unreachable.

◆ canCopyGluedNodeDuringSchedule()

virtual bool llvm::TargetInstrInfo::canCopyGluedNodeDuringSchedule ( SDNode N) const
inlinevirtual

Return true if the given SDNode can be copied during scheduling even if it has glue.

Definition at line 1200 of file TargetInstrInfo.h.

◆ canInsertSelect()

virtual bool llvm::TargetInstrInfo::canInsertSelect ( const MachineBasicBlock MBB,
ArrayRef< MachineOperand Cond,
Register  DstReg,
Register  TrueReg,
Register  FalseReg,
int CondCycles,
int TrueCycles,
int FalseCycles 
) const
inlinevirtual

Return true if it is possible to insert a select instruction that chooses between TrueReg and FalseReg based on the condition code in Cond.

When successful, also return the latency in cycles from TrueReg, FalseReg, and Cond to the destination register. In most cases, a select instruction will be 1 cycle, so CondCycles = TrueCycles = FalseCycles = 1

Some x86 implementations have 2-cycle cmov instructions.

Parameters
MBBBlock where select instruction would be inserted.
CondCondition returned by analyzeBranch.
DstRegVirtual dest register that the result should write to.
TrueRegVirtual register to select when Cond is true.
FalseRegVirtual register to select when Cond is false.
CondCyclesLatency from Cond+Branch to select output.
TrueCyclesLatency from TrueReg to select output.
FalseCyclesLatency from FalseReg to select output.

Definition at line 876 of file TargetInstrInfo.h.

◆ canMakeTailCallConditional()

virtual bool llvm::TargetInstrInfo::canMakeTailCallConditional ( SmallVectorImpl< MachineOperand > &  Cond,
const MachineInstr TailCall 
) const
inlinevirtual

Returns true if the tail call can be made conditional on BranchCond.

Definition at line 1446 of file TargetInstrInfo.h.

◆ ClobbersPredicate()

virtual bool llvm::TargetInstrInfo::ClobbersPredicate ( MachineInstr MI,
std::vector< MachineOperand > &  Pred,
bool  SkipDead 
) const
inlinevirtual

If the specified instruction defines any predicate or condition code register(s) used for predication, returns true as well as the definition predicate(s) by reference.

SkipDead should be set to false at any point that dead predicate instructions should be considered as being defined. A dead predicate instruction is one that is guaranteed to be removed after a call to PredicateInstruction.

Definition at line 1477 of file TargetInstrInfo.h.

◆ commuteInstruction()

MachineInstr * TargetInstrInfo::commuteInstruction ( MachineInstr MI,
bool  NewMI = false,
unsigned  OpIdx1 = CommuteAnyOperandIndex,
unsigned  OpIdx2 = CommuteAnyOperandIndex 
) const

This method commutes the operands of the given machine instruction MI.

The operands to be commuted are specified by their indices OpIdx1 and OpIdx2. OpIdx1 and OpIdx2 arguments may be set to a special value 'CommuteAnyOperandIndex', which means that the method is free to choose any arbitrarily chosen commutable operand. If both arguments are set to 'CommuteAnyOperandIndex' then the method looks for 2 different commutable operands; then commutes them if such operands could be found.

If NewMI is false, MI is modified in place and returned; otherwise, a new machine instruction is created and returned.

Do not call this method for a non-commutable instruction or for non-commuable operands. Even though the instruction is commutable, the method may still fail to commute the operands, null pointer is returned in such cases.

Definition at line 250 of file TargetInstrInfo.cpp.

References assert(), CommuteAnyOperandIndex, commuteInstructionImpl(), findCommutedOpIndices(), and MI.

◆ commuteInstructionImpl()

MachineInstr * TargetInstrInfo::commuteInstructionImpl ( MachineInstr MI,
bool  NewMI,
unsigned  OpIdx1,
unsigned  OpIdx2 
) const
protectedvirtual

This method commutes the operands of the given machine instruction MI.

The operands to be commuted are specified by their indices OpIdx1 and OpIdx2.

If a target has any instructions that are commutable but require converting to different instructions or making non-trivial changes to commute them, this method can be overloaded to do that. The default implementation simply swaps the commutable operands.

If NewMI is false, MI is modified in place and returned; otherwise, a new machine instruction is created and returned.

Do not call this method for a non-commutable instruction. Even though the instruction is commutable, the method may still fail to commute the operands, null pointer is returned in such cases.

Definition at line 167 of file TargetInstrInfo.cpp.

References assert(), llvm::MachineFunction::CloneMachineInstr(), findCommutedOpIndices(), llvm::MCInstrDesc::getNumDefs(), llvm::MachineInstr::getOperand(), llvm::Register::isPhysicalRegister(), MI, llvm::MachineOperand::setIsInternalRead(), llvm::MachineOperand::setIsKill(), llvm::MachineOperand::setIsRenamable(), llvm::MachineOperand::setIsUndef(), llvm::MachineOperand::setReg(), llvm::MachineOperand::setSubReg(), and llvm::MCOI::TIED_TO.

Referenced by commuteInstruction(), llvm::WebAssemblyInstrInfo::commuteInstructionImpl(), llvm::ARMBaseInstrInfo::commuteInstructionImpl(), llvm::SIInstrInfo::commuteInstructionImpl(), llvm::RISCVInstrInfo::commuteInstructionImpl(), llvm::SystemZInstrInfo::commuteInstructionImpl(), llvm::PPCInstrInfo::commuteInstructionImpl(), and llvm::X86InstrInfo::commuteInstructionImpl().

◆ convertToThreeAddress()

virtual MachineInstr* llvm::TargetInstrInfo::convertToThreeAddress ( MachineInstr MI,
LiveVariables LV,
LiveIntervals LIS 
) const
inlinevirtual

This method must be implemented by targets that set the M_CONVERTIBLE_TO_3_ADDR flag.

When this flag is set, the target may be able to convert a two-address instruction into one or more true three-address instructions on demand. This allows the X86 target (for example) to convert ADD and SHL instructions into LEA instructions if they would require register copies due to two-addressness.

This method returns a null pointer if the transformation cannot be performed, otherwise it returns the last new instruction.

If LIS is not nullptr, the LiveIntervals info should be updated for replacing MI with new instructions, even though this function does not remove MI.

Definition at line 417 of file TargetInstrInfo.h.

◆ copyPhysReg()

virtual void llvm::TargetInstrInfo::copyPhysReg ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  MI,
const DebugLoc DL,
MCRegister  DestReg,
MCRegister  SrcReg,
bool  KillSrc 
) const
inlinevirtual

Emit instructions to copy a pair of physical registers.

This function should support copies within any legal register class as well as any cross-class copies created during instruction selection.

The source and destination registers may overlap, which may require a careful implementation when multiple copy instructions are required for large registers. See for example the ARM target.

Definition at line 962 of file TargetInstrInfo.h.

References llvm_unreachable.

◆ createMIROperandComment()

std::string TargetInstrInfo::createMIROperandComment ( const MachineInstr MI,
const MachineOperand Op,
unsigned  OpIdx,
const TargetRegisterInfo TRI 
) const
virtual

◆ createPHIDestinationCopy()

virtual MachineInstr* llvm::TargetInstrInfo::createPHIDestinationCopy ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  InsPt,
const DebugLoc DL,
Register  Src,
Register  Dst 
) const
inlinevirtual

During PHI eleimination lets target to make necessary checks and insert the copy to the PHI destination register in a target specific manner.

Definition at line 1889 of file TargetInstrInfo.h.

References llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), DL, llvm::MCInstrInfo::get(), and MBB.

Referenced by llvm::SIInstrInfo::createPHIDestinationCopy().

◆ createPHISourceCopy()

virtual MachineInstr* llvm::TargetInstrInfo::createPHISourceCopy ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  InsPt,
const DebugLoc DL,
Register  Src,
unsigned  SrcSubReg,
Register  Dst 
) const
inlinevirtual

During PHI eleimination lets target to make necessary checks and insert the copy to the PHI destination register in a target specific manner.

Definition at line 1899 of file TargetInstrInfo.h.

References llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), DL, llvm::MCInstrInfo::get(), and MBB.

Referenced by llvm::SIInstrInfo::createPHISourceCopy().

◆ CreateTargetHazardRecognizer()

ScheduleHazardRecognizer * TargetInstrInfo::CreateTargetHazardRecognizer ( const TargetSubtargetInfo STI,
const ScheduleDAG DAG 
) const
virtual

Allocate and return a hazard recognizer to use for this target when scheduling the machine instructions before register allocation.

Definition at line 1050 of file TargetInstrInfo.cpp.

Referenced by llvm::ARMBaseInstrInfo::CreateTargetHazardRecognizer(), and llvm::PPCInstrInfo::CreateTargetHazardRecognizer().

◆ CreateTargetMIHazardRecognizer()

ScheduleHazardRecognizer * TargetInstrInfo::CreateTargetMIHazardRecognizer ( const InstrItineraryData II,
const ScheduleDAGMI DAG 
) const
virtual

Allocate and return a hazard recognizer to use for this target when scheduling the machine instructions before register allocation.

Definition at line 1057 of file TargetInstrInfo.cpp.

Referenced by llvm::ARMBaseInstrInfo::CreateTargetMIHazardRecognizer(), llvm::SIInstrInfo::CreateTargetMIHazardRecognizer(), llvm::GenericScheduler::initialize(), and llvm::PostGenericScheduler::initialize().

◆ CreateTargetPostRAHazardRecognizer() [1/2]

ScheduleHazardRecognizer * TargetInstrInfo::CreateTargetPostRAHazardRecognizer ( const InstrItineraryData II,
const ScheduleDAG DAG 
) const
virtual

Allocate and return a hazard recognizer to use for this target when scheduling the machine instructions after register allocation.

Definition at line 1064 of file TargetInstrInfo.cpp.

Referenced by llvm::ARMBaseInstrInfo::CreateTargetPostRAHazardRecognizer(), and llvm::HexagonInstrInfo::CreateTargetPostRAHazardRecognizer().

◆ CreateTargetPostRAHazardRecognizer() [2/2]

virtual ScheduleHazardRecognizer* llvm::TargetInstrInfo::CreateTargetPostRAHazardRecognizer ( const MachineFunction MF) const
inlinevirtual

Allocate and return a hazard recognizer to use for by non-scheduling passes.

Definition at line 1529 of file TargetInstrInfo.h.

◆ CreateTargetScheduleState()

virtual DFAPacketizer* llvm::TargetInstrInfo::CreateTargetScheduleState ( const TargetSubtargetInfo ) const
inlinevirtual

◆ decomposeMachineOperandsTargetFlags()

virtual std::pair<unsigned, unsigned> llvm::TargetInstrInfo::decomposeMachineOperandsTargetFlags ( unsigned  ) const
inlinevirtual

Decompose the machine operand's target flags into two values - the direct target flag value and any of bit flags that are applied.

Definition at line 1838 of file TargetInstrInfo.h.

◆ defaultDefLatency()

unsigned TargetInstrInfo::defaultDefLatency ( const MCSchedModel SchedModel,
const MachineInstr DefMI 
) const

Return the default expected latency for a def based on its opcode.

Return the default expected latency for a def based on it's opcode.

Definition at line 1135 of file TargetInstrInfo.cpp.

References DefMI, llvm::MCSchedModel::HighLatency, isHighLatencyDef(), and llvm::MCSchedModel::LoadLatency.

Referenced by llvm::TargetSchedModel::computeInstrLatency(), and llvm::TargetSchedModel::computeOperandLatency().

◆ describeLoadedValue()

Optional< ParamLoadedValue > TargetInstrInfo::describeLoadedValue ( const MachineInstr MI,
Register  Reg 
) const
virtual

◆ duplicate()

MachineInstr & TargetInstrInfo::duplicate ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  InsertBefore,
const MachineInstr Orig 
) const
virtual

Clones instruction or the whole instruction bundle Orig and insert into MBB before InsertBefore.

The target may update operands that are required to be unique.

Orig must not return true for MachineInstr::isNotDuplicable().

Definition at line 435 of file TargetInstrInfo.cpp.

References assert(), llvm::MachineFunction::CloneMachineInstrBundle(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::isNotDuplicable(), and MBB.

Referenced by llvm::ARMBaseInstrInfo::duplicate().

◆ expandPostRAPseudo()

virtual bool llvm::TargetInstrInfo::expandPostRAPseudo ( MachineInstr MI) const
inlinevirtual

This function is called for all pseudo instructions that remain after register allocation.

Many pseudo instructions are created to help register allocation. This is the place to convert them into real instructions. The target can edit MI in place, or it can insert new instructions and erase MI. The function should return true if anything was changed.

Definition at line 1066 of file TargetInstrInfo.h.

Referenced by llvm::SIInstrInfo::expandPostRAPseudo().

◆ extraSizeToPredicateInstructions()

virtual unsigned llvm::TargetInstrInfo::extraSizeToPredicateInstructions ( const MachineFunction MF,
unsigned  NumInsts 
) const
inlinevirtual

Return the increase in code size needed to predicate a contiguous run of NumInsts instructions.

Definition at line 831 of file TargetInstrInfo.h.

◆ finalizeInsInstrs()

virtual void llvm::TargetInstrInfo::finalizeInsInstrs ( MachineInstr Root,
MachineCombinerPattern P,
SmallVectorImpl< MachineInstr * > &  InsInstrs 
) const
inlinevirtual

Fix up the placeholder we may add in genAlternativeCodeSequence().

Definition at line 1133 of file TargetInstrInfo.h.

◆ findCommutedOpIndices()

bool TargetInstrInfo::findCommutedOpIndices ( const MachineInstr MI,
unsigned &  SrcOpIdx1,
unsigned &  SrcOpIdx2 
) const
virtual

Returns true iff the routine could find two commutable operands in the given machine instruction.

The 'SrcOpIdx1' and 'SrcOpIdx2' are INPUT and OUTPUT arguments. If any of the INPUT values is set to the special value 'CommuteAnyOperandIndex' then the method arbitrarily picks a commutable operand, then returns its index in the corresponding argument. If both of INPUT values are set to 'CommuteAnyOperandIndex' then method looks for 2 commutable operands. If INPUT values refer to some operands of MI, then the method simply returns true if the corresponding operands are commutable and returns false otherwise.

For example, calling this method this way: unsigned Op1 = 1, Op2 = CommuteAnyOperandIndex; findCommutedOpIndices(MI, Op1, Op2); can be interpreted as a query asking to find an operand that would be commutable with the operand#1.

Definition at line 296 of file TargetInstrInfo.cpp.

References assert(), fixCommutedOpIndices(), llvm::MCInstrDesc::getNumDefs(), llvm::MCInstrDesc::isCommutable(), and MI.

Referenced by commuteInstruction(), commuteInstructionImpl(), llvm::RISCVInstrInfo::findCommutedOpIndices(), llvm::MipsInstrInfo::findCommutedOpIndices(), llvm::X86InstrInfo::findCommutedOpIndices(), and llvm::PPCInstrInfo::findCommutedOpIndices().

◆ fixCommutedOpIndices()

bool TargetInstrInfo::fixCommutedOpIndices ( unsigned &  ResultIdx1,
unsigned &  ResultIdx2,
unsigned  CommutableOpIdx1,
unsigned  CommutableOpIdx2 
)
staticprotected

Assigns the (CommutableOpIdx1, CommutableOpIdx2) pair of commutable operand indices to (ResultIdx1, ResultIdx2).

One or both input values of the pair: (ResultIdx1, ResultIdx2) may be predefined to some indices or be undefined (designated by the special value 'CommuteAnyOperandIndex'). The predefined result indices cannot be re-defined. The function returns true iff after the result pair redefinition the fixed result pair is equal to or equivalent to the source pair of indices: (CommutableOpIdx1, CommutableOpIdx2). It is assumed here that the pairs (x,y) and (y,x) are equivalent.

Definition at line 265 of file TargetInstrInfo.cpp.

References CommuteAnyOperandIndex.

Referenced by findCommutedOpIndices().

◆ FoldImmediate()

virtual bool llvm::TargetInstrInfo::FoldImmediate ( MachineInstr UseMI,
MachineInstr DefMI,
Register  Reg,
MachineRegisterInfo MRI 
) const
inlinevirtual

'Reg' is known to be defined by a move immediate instruction, try to fold the immediate into the use instruction.

If MRI->hasOneNonDBGUse(Reg) is true, and this function returns true, then the caller may assume that DefMI has been erased from its parent block. The caller may assume that it will not be erased by this function otherwise.

Definition at line 1578 of file TargetInstrInfo.h.

◆ foldMemoryOperand() [1/2]

MachineInstr * TargetInstrInfo::foldMemoryOperand ( MachineInstr MI,
ArrayRef< unsigned >  Ops,
int  FI,
LiveIntervals LIS = nullptr,
VirtRegMap VRM = nullptr 
) const

Attempt to fold a load or store of the specified stack slot into the specified machine instruction for the specified operand(s).

If this is possible, a new instruction is returned with the specified operand folded, otherwise NULL is returned. The new instruction is inserted before MI, and the client is responsible for removing the old instruction. If VRM is passed, the assigned physregs can be inspected by target to decide on using an opcode (note that those assignments can still change).

Definition at line 560 of file TargetInstrInfo.cpp.

References llvm::MachineInstr::addMemOperand(), assert(), canFoldCopy(), llvm::MachineInstr::cloneInstrSymbols(), foldMemoryOperandImpl(), foldPatchpoint(), llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineFrameInfo::getObjectAlign(), llvm::MachineFrameInfo::getObjectOffset(), llvm::MachineFrameInfo::getObjectSize(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::TargetSubtargetInfo::getRegisterInfo(), llvm::MCRegisterInfo::getSubRegIdxSize(), llvm::MachineFunction::getSubtarget(), llvm::MachineBasicBlock::insert(), llvm::MachineOperand::isKill(), loadRegFromStackSlot(), llvm::max(), llvm::MachineInstr::mayLoad(), llvm::MachineInstr::mayStore(), MBB, MI, llvm::MachineMemOperand::MOLoad, llvm::MachineMemOperand::MONone, llvm::MachineMemOperand::MOStore, llvm::MachineInstr::setMemRefs(), storeRegToStackSlot(), SubReg, and TRI.

◆ foldMemoryOperand() [2/2]

MachineInstr * TargetInstrInfo::foldMemoryOperand ( MachineInstr MI,
ArrayRef< unsigned >  Ops,
MachineInstr LoadMI,
LiveIntervals LIS = nullptr 
) const

◆ foldMemoryOperandImpl() [1/2]

virtual MachineInstr* llvm::TargetInstrInfo::foldMemoryOperandImpl ( MachineFunction MF,
MachineInstr MI,
ArrayRef< unsigned >  Ops,
MachineBasicBlock::iterator  InsertPt,
int  FrameIndex,
LiveIntervals LIS = nullptr,
VirtRegMap VRM = nullptr 
) const
inlineprotectedvirtual

Target-dependent implementation for foldMemoryOperand.

Target-independent code in foldMemoryOperand will take care of adding a MachineMemOperand to the newly created instruction. The instruction and any auxiliary instructions necessary will be inserted at InsertPt.

Definition at line 1209 of file TargetInstrInfo.h.

Referenced by foldMemoryOperand().

◆ foldMemoryOperandImpl() [2/2]

virtual MachineInstr* llvm::TargetInstrInfo::foldMemoryOperandImpl ( MachineFunction MF,
MachineInstr MI,
ArrayRef< unsigned >  Ops,
MachineBasicBlock::iterator  InsertPt,
MachineInstr LoadMI,
LiveIntervals LIS = nullptr 
) const
inlineprotectedvirtual

Target-dependent implementation for foldMemoryOperand.

Target-independent code in foldMemoryOperand will take care of adding a MachineMemOperand to the newly created instruction. The instruction and any auxiliary instructions necessary will be inserted at InsertPt.

Definition at line 1222 of file TargetInstrInfo.h.

◆ genAlternativeCodeSequence()

void TargetInstrInfo::genAlternativeCodeSequence ( MachineInstr Root,
MachineCombinerPattern  Pattern,
SmallVectorImpl< MachineInstr * > &  InsInstrs,
SmallVectorImpl< MachineInstr * > &  DelInstrs,
DenseMap< unsigned, unsigned > &  InstIdxForVirtReg 
) const
virtual

When getMachineCombinerPatterns() finds patterns, this function generates the instructions that could replace the original code sequence.

The client has to decide whether the actual replacement is beneficial or not.

Parameters
Root- Instruction that could be combined with one of its operands
Pattern- Combination pattern for Root
InsInstrs- Vector of new instructions that implement P
DelInstrs- Old instructions, including Root, that could be replaced by InsInstr
InstIdxForVirtReg- map of virtual register to instruction in InsInstr that defines it

Definition at line 891 of file TargetInstrInfo.cpp.

References assert(), llvm::MachineInstr::getMF(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::MachineRegisterInfo::getUniqueVRegDef(), MRI, llvm::REASSOC_AX_BY, llvm::REASSOC_AX_YB, llvm::REASSOC_XA_BY, llvm::REASSOC_XA_YB, and reassociateOps().

Referenced by llvm::AArch64InstrInfo::genAlternativeCodeSequence(), and llvm::PPCInstrInfo::genAlternativeCodeSequence().

◆ getAddressSpaceForPseudoSourceKind()

virtual unsigned llvm::TargetInstrInfo::getAddressSpaceForPseudoSourceKind ( unsigned  Kind) const
inlinevirtual

getAddressSpaceForPseudoSourceKind - Given the kind of memory (e.g.

stack) the target returns the corresponding address space.

Definition at line 1276 of file TargetInstrInfo.h.

◆ getAddrModeFromMemoryOp()

virtual Optional<ExtAddrMode> llvm::TargetInstrInfo::getAddrModeFromMemoryOp ( const MachineInstr MemI,
const TargetRegisterInfo TRI 
) const
inlinevirtual

Target dependent implementation to get the values constituting the address MachineInstr that is accessing memory.

These values are returned as a struct ExtAddrMode which contains all relevant information to make up the address.

Definition at line 1367 of file TargetInstrInfo.h.

References llvm::None.

◆ getBaseAndOffsetPosition()

virtual bool llvm::TargetInstrInfo::getBaseAndOffsetPosition ( const MachineInstr MI,
unsigned &  BasePos,
unsigned &  OffsetPos 
) const
inlinevirtual

Return true if the instruction contains a base register and offset.

If true, the function also sets the operand position in the instruction for the base register and offset.

Definition at line 1356 of file TargetInstrInfo.h.

Referenced by llvm::SwingSchedulerDAG::applyInstrChange(), and llvm::SwingSchedulerDAG::fixupRegisterOverlaps().

◆ getBranchDestBlock()

virtual MachineBasicBlock* llvm::TargetInstrInfo::getBranchDestBlock ( const MachineInstr MI) const
inlinevirtual
Returns
The block that branch instruction MI jumps to.

Definition at line 584 of file TargetInstrInfo.h.

References llvm_unreachable.

◆ getCalleeOperand()

virtual const MachineOperand& llvm::TargetInstrInfo::getCalleeOperand ( const MachineInstr MI) const
inlinevirtual

Returns the callee operand from the given MI.

Definition at line 1999 of file TargetInstrInfo.h.

References MI.

◆ getCallFrameDestroyOpcode()

unsigned llvm::TargetInstrInfo::getCallFrameDestroyOpcode ( ) const
inline

◆ getCallFrameSetupOpcode()

unsigned llvm::TargetInstrInfo::getCallFrameSetupOpcode ( ) const
inline

These methods return the opcode of the frame setup/destroy instructions if they exist (-1 otherwise).

Some targets use pseudo instructions in order to abstract away the difference between operating with a frame pointer and operating without, through the use of these two instructions.

Definition at line 198 of file TargetInstrInfo.h.

Referenced by getSPAdjust(), isFrameInstr(), and isFrameSetup().

◆ getCatchReturnOpcode()

unsigned llvm::TargetInstrInfo::getCatchReturnOpcode ( ) const
inline

Definition at line 238 of file TargetInstrInfo.h.

◆ getConstValDefinedInReg()

virtual bool llvm::TargetInstrInfo::getConstValDefinedInReg ( const MachineInstr MI,
const Register  Reg,
int64_t &  ImmVal 
) const
inlinevirtual

Returns true if MI is an instruction that defines Reg to have a constant value and the value is recorded in ImmVal.

The ImmVal is a result that should be interpreted as modulo size of Reg.

Definition at line 1029 of file TargetInstrInfo.h.

◆ getExecutionDomain()

virtual std::pair<uint16_t, uint16_t> llvm::TargetInstrInfo::getExecutionDomain ( const MachineInstr MI) const
inlinevirtual

Return the current execution domain and bit mask of possible domains for instruction.

Some micro-architectures have multiple execution domains, and multiple opcodes that perform the same operation in different domains. For example, the x86 architecture provides the por, orps, and orpd instructions that all do the same thing. There is a latency penalty if a register is written in one domain and read in another.

This function returns a pair (domain, mask) containing the execution domain of MI, and a bit mask of possible domains. The setExecutionDomain function can be used to change the opcode to one of the domains in the bit mask. Instructions whose execution domain can't be changed should return a 0 mask.

The execution domain numbers don't have any special meaning except domain 0 is used for instructions that are not associated with any interesting execution domain.

Definition at line 1679 of file TargetInstrInfo.h.

◆ getExtendResourceLenLimit()

virtual int llvm::TargetInstrInfo::getExtendResourceLenLimit ( ) const
inlinevirtual

The limit on resource length extension we accept in MachineCombiner Pass.

Definition at line 1185 of file TargetInstrInfo.h.

◆ getExtractSubregInputs()

bool TargetInstrInfo::getExtractSubregInputs ( const MachineInstr MI,
unsigned  DefIdx,
RegSubRegPairAndIdx InputReg 
) const

Build the equivalent inputs of a EXTRACT_SUBREG for the given MI and DefIdx.

[out] InputReg of the equivalent EXTRACT_SUBREG. E.g., EXTRACT_SUBREG %1:sub1, sub0, sub1 would produce:

  • %1:sub1, sub0
Returns
true if it is possible to build such an input sequence with the pair MI, DefIdx and the operand has no undef flag set. False otherwise.
Precondition
MI.isExtractSubreg() or MI.isExtractSubregLike().
Note
The generic implementation does not provide any support for MI.isExtractSubregLike(). In other words, one has to override getExtractSubregLikeInputs for target specific instructions.

Definition at line 1293 of file TargetInstrInfo.cpp.

References assert(), getExtractSubregLikeInputs(), llvm::MachineOperand::getImm(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), llvm::MachineOperand::isImm(), llvm::MachineOperand::isUndef(), MI, llvm::TargetInstrInfo::RegSubRegPair::Reg, llvm::TargetInstrInfo::RegSubRegPairAndIdx::SubIdx, and llvm::TargetInstrInfo::RegSubRegPair::SubReg.

◆ getExtractSubregLikeInputs()

virtual bool llvm::TargetInstrInfo::getExtractSubregLikeInputs ( const MachineInstr MI,
unsigned  DefIdx,
RegSubRegPairAndIdx InputReg 
) const
inlineprotectedvirtual

Target-dependent implementation of getExtractSubregInputs.

Returns
true if it is possible to build the equivalent EXTRACT_SUBREG inputs with the pair MI, DefIdx. False otherwise.
Precondition
MI.isExtractSubregLike().
See also
TargetInstrInfo::getExtractSubregInputs.

Definition at line 1251 of file TargetInstrInfo.h.

Referenced by getExtractSubregInputs().

◆ getFrameSize()

int64_t llvm::TargetInstrInfo::getFrameSize ( const MachineInstr I) const
inline

Returns size of the frame associated with the given frame instruction.

For frame setup instruction this is frame that is set up space set up after the instruction. For frame destroy instruction this is the frame freed by the caller. Note, in some cases a call frame (or a part of it) may be prepared prior to the frame setup instruction. It occurs in the calls that involve inalloca arguments. This function reports only the size of the frame part that is set up between the frame setup and destroy pseudo instructions.

Definition at line 220 of file TargetInstrInfo.h.

References assert(), I, and isFrameInstr().

Referenced by getFrameTotalSize(), and getSPAdjust().

◆ getFrameTotalSize()

int64_t llvm::TargetInstrInfo::getFrameTotalSize ( const MachineInstr I) const
inline

Returns the total frame size, which is made up of the space set up inside the pair of frame start-stop instructions and the space that is set up prior to the pair.

Definition at line 229 of file TargetInstrInfo.h.

References assert(), getFrameSize(), I, and isFrameSetup().

◆ getIncrementValue()

virtual bool llvm::TargetInstrInfo::getIncrementValue ( const MachineInstr MI,
int Value 
) const
inlinevirtual

If the instruction is an increment of a constant value, return the amount.

Definition at line 1384 of file TargetInstrInfo.h.

Referenced by llvm::SwingSchedulerDAG::isLoopCarriedDep().

◆ getInlineAsmLength()

unsigned TargetInstrInfo::getInlineAsmLength ( const char *  Str,
const MCAsmInfo MAI,
const TargetSubtargetInfo STI = nullptr 
) const
virtual

Measure the specified inline asm to determine an approximation of its length.

Comments (which run till the next SeparatorString or newline) do not count as an instruction. Any other non-whitespace text is considered an instruction, with multiple instructions separated by SeparatorString or newlines. Variable-length instructions are not handled here; this function may be overloaded in the target code to do that. We implement a special case of the .space directive which takes only a single integer argument in base 10 that is the size in bytes. This is a restricted form of the GAS directive in that we only interpret simple–i.e. not a logical or arithmetic expression–size values without the optional fill value. This is primarily used for creating arbitrary sized inline asm blocks for testing purposes.

Definition at line 100 of file TargetInstrInfo.cpp.

References llvm::MCAsmInfo::getMaxInstLength(), llvm::MCAsmInfo::getSeparatorString(), and isAsmComment().

◆ getInsertSubregInputs()

bool TargetInstrInfo::getInsertSubregInputs ( const MachineInstr MI,
unsigned  DefIdx,
RegSubRegPair BaseReg,
RegSubRegPairAndIdx InsertedReg 
) const

Build the equivalent inputs of a INSERT_SUBREG for the given MI and DefIdx.

[out] BaseReg and [out] InsertedReg contain the equivalent inputs of INSERT_SUBREG. E.g., INSERT_SUBREG %0:sub0, %1:sub1, sub3 would produce:

  • BaseReg: %0:sub0
  • InsertedReg: %1:sub1, sub3
Returns
true if it is possible to build such an input sequence with the pair MI, DefIdx and the operand has no undef flag set. False otherwise.
Precondition
MI.isInsertSubreg() or MI.isInsertSubregLike().
Note
The generic implementation does not provide any support for MI.isInsertSubregLike(). In other words, one has to override getInsertSubregLikeInputs for target specific instructions.

Definition at line 1318 of file TargetInstrInfo.cpp.

References assert(), llvm::MachineOperand::getImm(), getInsertSubregLikeInputs(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), llvm::MachineOperand::isImm(), llvm::MachineOperand::isUndef(), MI, llvm::TargetInstrInfo::RegSubRegPair::Reg, llvm::TargetInstrInfo::RegSubRegPairAndIdx::SubIdx, and llvm::TargetInstrInfo::RegSubRegPair::SubReg.

◆ getInsertSubregLikeInputs()

virtual bool llvm::TargetInstrInfo::getInsertSubregLikeInputs ( const MachineInstr MI,
unsigned  DefIdx,
RegSubRegPair BaseReg,
RegSubRegPairAndIdx InsertedReg 
) const
inlineprotectedvirtual

Target-dependent implementation of getInsertSubregInputs.

Returns
true if it is possible to build the equivalent INSERT_SUBREG inputs with the pair MI, DefIdx. False otherwise.
Precondition
MI.isInsertSubregLike().
See also
TargetInstrInfo::getInsertSubregInputs.

Definition at line 1266 of file TargetInstrInfo.h.

Referenced by getInsertSubregInputs().

◆ getInstrLatency() [1/2]

unsigned TargetInstrInfo::getInstrLatency ( const InstrItineraryData ItinData,
const MachineInstr MI,
unsigned *  PredCost = nullptr 
) const
virtual

Compute the instruction latency of a given instruction.

If the instruction has higher cost when predicated, it's returned via PredCost.

Definition at line 1150 of file TargetInstrInfo.cpp.

References llvm::InstrItineraryData::getStageLatency(), and MI.

Referenced by llvm::TargetSchedModel::computeInstrLatency(), llvm::ScheduleDAGSDNodes::computeLatency(), and llvm::TargetSchedModel::computeOperandLatency().

◆ getInstrLatency() [2/2]

int TargetInstrInfo::getInstrLatency ( const InstrItineraryData ItinData,
SDNode Node 
) const
virtual

◆ getInstSizeInBytes()

virtual unsigned llvm::TargetInstrInfo::getInstSizeInBytes ( const MachineInstr MI) const
inlinevirtual

Returns the size in bytes of the specified MachineInstr, or ~0U when this function is not implemented by a target.

Definition at line 366 of file TargetInstrInfo.h.

Referenced by predictBranchSizeForIfCvt().

◆ getMachineCombinerPatterns()

bool TargetInstrInfo::getMachineCombinerPatterns ( MachineInstr Root,
SmallVectorImpl< MachineCombinerPattern > &  Patterns,
bool  DoRegPressureReduce 
) const
virtual

Return true when there is potentially a faster code sequence for an instruction chain ending in Root.

All potential patterns are returned in the Pattern vector. Pattern should be sorted in priority order since the pattern evaluator stops checking as soon as it finds a faster sequence.

Parameters
Root- Instruction that could be combined with one of its operands
Patterns- Vector of possible combination patterns

Definition at line 777 of file TargetInstrInfo.cpp.

References isReassociationCandidate(), llvm::REASSOC_AX_BY, llvm::REASSOC_AX_YB, llvm::REASSOC_XA_BY, and llvm::REASSOC_XA_YB.

Referenced by llvm::AArch64InstrInfo::getMachineCombinerPatterns(), and llvm::PPCInstrInfo::getMachineCombinerPatterns().

◆ getMachineCSELookAheadLimit()

virtual unsigned llvm::TargetInstrInfo::getMachineCSELookAheadLimit ( ) const
inlinevirtual

Return the value to use for the MachineCSE's LookAheadLimit, which is a heuristic used for CSE'ing phys reg defs.

Definition at line 1804 of file TargetInstrInfo.h.

◆ getMemOperandAACheckLimit()

virtual unsigned llvm::TargetInstrInfo::getMemOperandAACheckLimit ( ) const
inlinevirtual

Return the maximal number of alias checks on memory operands.

For instructions with more than one memory operands, the alias check on a single MachineInstr pair has quadratic overhead and results in unacceptable performance in the worst case. The limit here is to clamp that maximal checks performed. Usually, that's the product of memory operand numbers from that pair of MachineInstr to be checked. For instance, with two MachineInstrs with 4 and 5 memory operands correspondingly, a total of 20 checks are required. With this limit set to 16, their alias check is skipped. We choose to limit the product instead of the individual instruction as targets may have special MachineInstrs with a considerably high number of memory operands, such as ldm in ARM. Setting this limit per MachineInstr would result in either too high overhead or too rigid restriction.

Definition at line 1823 of file TargetInstrInfo.h.

◆ getMemOperandsWithOffsetWidth()

virtual bool llvm::TargetInstrInfo::getMemOperandsWithOffsetWidth ( const MachineInstr MI,
SmallVectorImpl< const MachineOperand * > &  BaseOps,
int64_t &  Offset,
bool &  OffsetIsScalable,
unsigned &  Width,
const TargetRegisterInfo TRI 
) const
inlinevirtual

Get zero or more base operands and the byte offset of an instruction that reads/writes memory.

Note that there may be zero base operands if the instruction accesses a constant address. It returns false if MI does not read/write memory. It returns false if base operands and offset could not be determined. It is not guaranteed to always recognize base operands and offsets in all cases.

Definition at line 1346 of file TargetInstrInfo.h.

Referenced by getMemOperandWithOffset().

◆ getMemOperandWithOffset()

bool TargetInstrInfo::getMemOperandWithOffset ( const MachineInstr MI,
const MachineOperand *&  BaseOp,
int64_t &  Offset,
bool &  OffsetIsScalable,
const TargetRegisterInfo TRI 
) const

Get the base operand and byte offset of an instruction that reads/writes memory.

This is a convenience function for callers that are only prepared to handle a single base operand.

Definition at line 1070 of file TargetInstrInfo.cpp.

References getMemOperandsWithOffsetWidth(), MI, Offset, and TRI.

Referenced by llvm::SwingSchedulerDAG::isLoopCarriedDep().

◆ getMIRFormatter()

virtual const MIRFormatter* llvm::TargetInstrInfo::getMIRFormatter ( ) const
inlinevirtual

Return MIR formatter to format/parse MIR operands.

Target can override this virtual function and return target specific MIR formatter.

Definition at line 1985 of file TargetInstrInfo.h.

◆ getNop()

MCInst TargetInstrInfo::getNop ( ) const
virtual

Return the noop instruction to use for a noop.

Definition at line 475 of file TargetInstrInfo.cpp.

References llvm_unreachable.

Referenced by llvm::AsmPrinter::emitFunctionBody(), and llvm::AsmPrinter::emitNops().

◆ getNumMicroOps()

unsigned TargetInstrInfo::getNumMicroOps ( const InstrItineraryData ItinData,
const MachineInstr MI 
) const
virtual

Return the number of u-operations the given machine instruction will be decoded to on the target cpu.

The itinerary's IssueWidth is the number of microops that can be dispatched each cycle. An instruction with zero microops takes no dispatch resources.

Definition at line 1119 of file TargetInstrInfo.cpp.

References llvm::InstrItineraryData::isEmpty(), llvm::InstrItineraryData::Itineraries, MI, and llvm::InstrItinerary::NumMicroOps.

Referenced by llvm::TargetSchedModel::getNumMicroOps().

◆ getOpcodeAfterMemoryUnfold()

virtual unsigned llvm::TargetInstrInfo::getOpcodeAfterMemoryUnfold ( unsigned  Opc,
bool  UnfoldLoad,
bool  UnfoldStore,
unsigned *  LoadRegIndex = nullptr 
) const
inlinevirtual

Returns the opcode of the would be new instruction after load / store are unfolded from an instruction of the specified opcode.

It returns zero if the specified unfolding is not possible. If LoadRegIndex is non-null, it is filled in with the operand index of the operand which will hold the register holding the loaded value.

Definition at line 1302 of file TargetInstrInfo.h.

◆ getOperandLatency() [1/2]

int TargetInstrInfo::getOperandLatency ( const InstrItineraryData ItinData,
const MachineInstr DefMI,
unsigned  DefIdx,
const MachineInstr UseMI,
unsigned  UseIdx 
) const
virtual

Compute and return the use operand latency of a given pair of def and use.

Both DefMI and UseMI must be valid.

In most cases, the static scheduling itinerary was enough to determine the operand latency. But it may not be possible for instructions with variable number of defs / uses.

This is a raw interface to the itinerary that may be directly overridden by a target. Use computeOperandLatency to get the best estimate of latency.

By default, call directly to the itinerary. This may be overriden by the target.

Definition at line 1256 of file TargetInstrInfo.cpp.

References DefMI, llvm::InstrItineraryData::getOperandLatency(), and UseMI.

◆ getOperandLatency() [2/2]

int TargetInstrInfo::getOperandLatency ( const InstrItineraryData ItinData,
SDNode DefNode,
unsigned  DefIdx,
SDNode UseNode,
unsigned  UseIdx 
) const
virtual

◆ getOutliningCandidateInfo()

virtual outliner::OutlinedFunction llvm::TargetInstrInfo::getOutliningCandidateInfo ( std::vector< outliner::Candidate > &  RepeatedSequenceLocs) const
inlinevirtual

Returns a outliner::OutlinedFunction struct containing target-specific information for a set of outlining candidates.

Definition at line 1910 of file TargetInstrInfo.h.

References llvm_unreachable.

◆ getOutliningType()

virtual outliner::InstrType llvm::TargetInstrInfo::getOutliningType ( MachineBasicBlock::iterator MIT,
unsigned  Flags 
) const
inlinevirtual

Returns how or if MI should be outlined.

Definition at line 1924 of file TargetInstrInfo.h.

References llvm_unreachable.

◆ getPartialRegUpdateClearance()

virtual unsigned llvm::TargetInstrInfo::getPartialRegUpdateClearance ( const MachineInstr MI,
unsigned  OpNum,
const TargetRegisterInfo TRI 
) const
inlinevirtual

Returns the preferred minimum clearance before an instruction with an unwanted partial register update.

Some instructions only write part of a register, and implicitly need to read the other parts of the register. This may cause unwanted stalls preventing otherwise unrelated instructions from executing in parallel in an out-of-order CPU.

For example, the x86 instruction cvtsi2ss writes its result to bits [31:0] of the destination xmm register. Bits [127:32] are unaffected, so the instruction needs to wait for the old value of the register to become available:

addps xmm1, xmm0 movaps xmm0, (rax) cvtsi2ss rbx, xmm0

In the code above, the cvtsi2ss instruction needs to wait for the addps instruction before it can issue, even though the high bits of xmm0 probably aren't needed.

This hook returns the preferred clearance before MI, measured in instructions. Other defs of MI's operand OpNum are avoided in the last N instructions before MI. It should only return a positive value for unwanted dependencies. If the old bits of the defined register have useful values, or if MI is determined to otherwise read the dependency, the hook should return 0.

The unwanted dependency may be handled by:

  1. Allocating the same register for an MI def and use. That makes the unwanted dependency identical to a required dependency.
  2. Allocating a register for the def that has no defs in the previous N instructions.
  3. Calling breakPartialRegDependency() with the same arguments. This allows the target to insert a dependency breaking instruction.

Definition at line 1729 of file TargetInstrInfo.h.

◆ getPatchpointUnfoldableRange()

std::pair< unsigned, unsigned > TargetInstrInfo::getPatchpointUnfoldableRange ( const MachineInstr MI) const
virtual

For a patchpoint, stackmap, or statepoint intrinsic, return the range of operands which can't be folded into stack references.

Operands outside of the range are most likely foldable but it is not guaranteed. These instructions are unique in that stack references for some operands have the same execution cost (e.g. none) as the unfolded register forms. The ranged return is guaranteed to include all operands which can't be folded at zero cost.

Definition at line 478 of file TargetInstrInfo.cpp.

References llvm_unreachable, and MI.

◆ getPredicationCost()

unsigned TargetInstrInfo::getPredicationCost ( const MachineInstr MI) const
virtual

Definition at line 1146 of file TargetInstrInfo.cpp.

◆ getRegClass()

const TargetRegisterClass * TargetInstrInfo::getRegClass ( const MCInstrDesc MCID,
unsigned  OpNum,
const TargetRegisterInfo TRI,
const MachineFunction MF 
) const
virtual

◆ getRegSequenceInputs()

bool TargetInstrInfo::getRegSequenceInputs ( const MachineInstr MI,
unsigned  DefIdx,
SmallVectorImpl< RegSubRegPairAndIdx > &  InputRegs 
) const

Build the equivalent inputs of a REG_SEQUENCE for the given MI and DefIdx.

[out] InputRegs of the equivalent REG_SEQUENCE. Each element of the list is modeled as <Reg:SubReg, SubIdx>. Operands with the undef flag are not added to this list. E.g., REG_SEQUENCE %1:sub1, sub0, %2, sub1 would produce two elements:

  • %1:sub1, sub0
  • %2<:0>, sub1
Returns
true if it is possible to build such an input sequence with the pair MI, DefIdx. False otherwise.
Precondition
MI.isRegSequence() or MI.isRegSequenceLike().
Note
The generic implementation does not provide any support for MI.isRegSequenceLike(). In other words, one has to override getRegSequenceLikeInputs for target specific instructions.

Definition at line 1266 of file TargetInstrInfo.cpp.

References assert(), llvm::MachineOperand::getImm(), llvm::MachineOperand::getReg(), getRegSequenceLikeInputs(), llvm::MachineOperand::getSubReg(), llvm::MachineOperand::isImm(), llvm::MachineOperand::isUndef(), and MI.

◆ getRegSequenceLikeInputs()

virtual bool llvm::TargetInstrInfo::getRegSequenceLikeInputs ( const MachineInstr MI,
unsigned  DefIdx,
SmallVectorImpl< RegSubRegPairAndIdx > &  InputRegs 
) const
inlineprotectedvirtual

Target-dependent implementation of getRegSequenceInputs.

Returns
true if it is possible to build the equivalent REG_SEQUENCE inputs with the pair MI, DefIdx. False otherwise.
Precondition
MI.isRegSequenceLike().
See also
TargetInstrInfo::getRegSequenceInputs.

Definition at line 1237 of file TargetInstrInfo.h.

Referenced by getRegSequenceInputs().

◆ getReturnOpcode()

unsigned llvm::TargetInstrInfo::getReturnOpcode ( ) const
inline

Definition at line 239 of file TargetInstrInfo.h.

◆ getSerializableBitmaskMachineOperandTargetFlags()

virtual ArrayRef<std::pair<unsigned, const char *> > llvm::TargetInstrInfo::getSerializableBitmaskMachineOperandTargetFlags ( ) const
inlinevirtual

Return an array that contains the bitmask target flag values and their names.

MIR Serialization is able to serialize only the target flags that are defined by this method.

Definition at line 1858 of file TargetInstrInfo.h.

References llvm::None.

◆ getSerializableDirectMachineOperandTargetFlags()

virtual ArrayRef<std::pair<unsigned, const char *> > llvm::TargetInstrInfo::getSerializableDirectMachineOperandTargetFlags ( ) const
inlinevirtual

Return an array that contains the direct target flag values and their names.

MIR Serialization is able to serialize only the target flags that are defined by this method.

Definition at line 1848 of file TargetInstrInfo.h.

References llvm::None.

◆ getSerializableMachineMemOperandTargetFlags()

virtual ArrayRef<std::pair<MachineMemOperand::Flags, const char *> > llvm::TargetInstrInfo::getSerializableMachineMemOperandTargetFlags ( ) const
inlinevirtual

Return an array that contains the MMO target flag values and their names.

MIR Serialization is able to serialize only the MMO target flags that are defined by this method.

Definition at line 1868 of file TargetInstrInfo.h.

References llvm::None.

◆ getSerializableTargetIndices()

virtual ArrayRef<std::pair<int, const char *> > llvm::TargetInstrInfo::getSerializableTargetIndices ( ) const
inlinevirtual

Return an array that contains the ids of the target indices (used for the TargetIndex machine operand) and their names.

MIR Serialization is able to serialize only the target indices that are defined by this method.

Definition at line 1831 of file TargetInstrInfo.h.

References llvm::None.

◆ getSPAdjust()

int TargetInstrInfo::getSPAdjust ( const MachineInstr MI) const
virtual

Returns the actual stack pointer adjustment made by an instruction as part of a call sequence.

By default, only call frame setup/destroy instructions adjust the stack, but targets may want to override this to enable more fine-grained adjustment, or adjust by a different value.

Definition at line 997 of file TargetInstrInfo.cpp.

References llvm::TargetFrameLowering::alignSPAdjust(), getCallFrameDestroyOpcode(), getCallFrameSetupOpcode(), llvm::TargetSubtargetInfo::getFrameLowering(), getFrameSize(), llvm::TargetFrameLowering::getStackGrowthDirection(), llvm::MachineFunction::getSubtarget(), isFrameInstr(), MI, and llvm::TargetFrameLowering::StackGrowsDown.

◆ getStackSlotRange()

bool TargetInstrInfo::getStackSlotRange ( const TargetRegisterClass RC,
unsigned  SubIdx,
unsigned &  Size,
unsigned &  Offset,
const MachineFunction MF 
) const
virtual

Compute the size in bytes and offset within a stack slot of a spilled register or subregister.

Parameters
[out]Sizein bytes of the spilled value.
[out]Offsetin bytes within the stack slot.
Returns
true if both Size and Offset are successfully computed.

Not all subregisters have computable spill slots. For example, subregisters registers may not be byte-sized, and a pair of discontiguous subregisters has no single offset.

Targets with nontrivial bigendian implementations may need to override this, particularly to support spilled vector registers.

Definition at line 389 of file TargetInstrInfo.cpp.

References assert(), llvm::MachineFunction::getDataLayout(), llvm::TargetSubtargetInfo::getRegisterInfo(), llvm::TargetRegisterInfo::getSpillSize(), llvm::MCRegisterInfo::getSubRegIdxOffset(), llvm::MCRegisterInfo::getSubRegIdxSize(), llvm::MachineFunction::getSubtarget(), llvm::DataLayout::isLittleEndian(), Offset, llvm::Check::Size, and TRI.

◆ getTailDuplicateSize()

virtual unsigned llvm::TargetInstrInfo::getTailDuplicateSize ( CodeGenOpt::Level  OptLevel) const
inlinevirtual

Returns the target-specific default value for tail duplication.

This value will be used if the tail-dup-placement-threshold argument is not provided.

Definition at line 1994 of file TargetInstrInfo.h.

References llvm::CodeGenOpt::Aggressive.

◆ getUndefRegClearance()

virtual unsigned llvm::TargetInstrInfo::getUndefRegClearance ( const MachineInstr MI,
unsigned  OpNum,
const TargetRegisterInfo TRI 
) const
inlinevirtual

Return the minimum clearance before an instruction that reads an unused register.

For example, AVX instructions may copy part of a register operand into the unused high bits of the destination register.

vcvtsi2sdq rax, undef xmm0, xmm14

In the code above, vcvtsi2sdq copies xmm0[127:64] into xmm14 creating a false dependence on any previous write to xmm0.

This hook works similarly to getPartialRegUpdateClearance, except that it does not take an operand index. Instead sets OpNum to the index of the unused register.

Definition at line 1749 of file TargetInstrInfo.h.

◆ hasCommutePreference()

virtual bool llvm::TargetInstrInfo::hasCommutePreference ( MachineInstr MI,
bool &  Commute 
) const
inlinevirtual

Returns true if the target has a preference on the operands order of the given machine instruction.

And specify if Commute is required to get the desired operands order.

Definition at line 474 of file TargetInstrInfo.h.

◆ hasHighOperandLatency()

virtual bool llvm::TargetInstrInfo::hasHighOperandLatency ( const TargetSchedModel SchedModel,
const MachineRegisterInfo MRI,
const MachineInstr DefMI,
unsigned  DefIdx,
const MachineInstr UseMI,
unsigned  UseIdx 
) const
inlinevirtual

Compute operand latency between a def of 'Reg' and a use in the current loop.

Return true if the target considered it 'high'. This is used by optimization passes such as machine LICM to determine whether it makes sense to hoist an instruction out even in a high register pressure situation.

Definition at line 1639 of file TargetInstrInfo.h.

◆ hasLoadFromStackSlot()

bool TargetInstrInfo::hasLoadFromStackSlot ( const MachineInstr MI,
SmallVectorImpl< const MachineMemOperand * > &  Accesses 
) const
virtual

If the specified machine instruction has a load from a stack slot, return true along with the FrameIndices of the loaded stack slot and the machine mem operands containing the reference.

If not, return false. Unlike isLoadFromStackSlot, this returns true for any instructions that loads from the stack. This is just a hint, as some cases may be missed.

Definition at line 361 of file TargetInstrInfo.cpp.

References MI.

Referenced by llvm::HexagonInstrInfo::hasLoadFromStackSlot().

◆ hasLowDefLatency()

bool TargetInstrInfo::hasLowDefLatency ( const TargetSchedModel SchedModel,
const MachineInstr DefMI,
unsigned  DefIdx 
) const
virtual

Compute operand latency of a def of 'Reg'.

Return true if the target considered it 'low'.

Definition at line 1161 of file TargetInstrInfo.cpp.

References DefMI, llvm::TargetSchedModel::getInstrItineraries(), llvm::InstrItineraryData::getOperandCycle(), and llvm::InstrItineraryData::isEmpty().

◆ hasReassociableOperands()

bool TargetInstrInfo::hasReassociableOperands ( const MachineInstr Inst,
const MachineBasicBlock MBB 
) const
virtual

◆ hasReassociableSibling()

bool TargetInstrInfo::hasReassociableSibling ( const MachineInstr Inst,
bool &  Commuted 
) const

◆ hasStoreToStackSlot()

bool TargetInstrInfo::hasStoreToStackSlot ( const MachineInstr MI,
SmallVectorImpl< const MachineMemOperand * > &  Accesses 
) const
virtual

If the specified machine instruction has a store to a stack slot, return true along with the FrameIndices of the loaded stack slot and the machine mem operands containing the reference.

If not, return false. Unlike isStoreToStackSlot, this returns true for any instructions that stores to the stack. This is just a hint, as some cases may be missed.

Definition at line 375 of file TargetInstrInfo.cpp.

References MI.

Referenced by llvm::HexagonInstrInfo::hasStoreToStackSlot().

◆ insertBranch()

virtual unsigned llvm::TargetInstrInfo::insertBranch ( MachineBasicBlock MBB,
MachineBasicBlock TBB,
MachineBasicBlock FBB,
ArrayRef< MachineOperand Cond,
const DebugLoc DL,
int BytesAdded = nullptr 
) const
inlinevirtual

Insert branch code into the end of the specified MachineBasicBlock.

The operands to this method are the same as those returned by analyzeBranch. This is only invoked in cases where analyzeBranch returns success. It returns the number of instructions inserted. If BytesAdded is non-null, report the change in code size from the added instructions.

It is also invoked by tail merging to add unconditional branches in cases where analyzeBranch doesn't apply because there was no original branch to analyze. At least this much must be implemented, else tail merging needs to be disabled.

The CFG information in MBB.Predecessors and MBB.Successors must be valid before calling this function.

Definition at line 698 of file TargetInstrInfo.h.

References llvm_unreachable.

Referenced by llvm::PeelingModuloScheduleExpander::CreateLCSSAExitingBlock(), llvm::PeelingModuloScheduleExpander::fixupBranches(), insertUnconditionalBranch(), and ReplaceTailWithBranchTo().

◆ insertIndirectBranch()

virtual void llvm::TargetInstrInfo::insertIndirectBranch ( MachineBasicBlock MBB,
MachineBasicBlock NewDestBB,
MachineBasicBlock RestoreBB,
const DebugLoc DL,
int64_t  BrOffset = 0,
RegScavenger RS = nullptr 
) const
inlinevirtual

Insert an unconditional indirect branch at the end of MBB to NewDestBB.

Optionally, insert the clobbered register restoring in RestoreBB. BrOffset indicates the offset of NewDestBB relative to the offset of the position to insert the new branch.

Definition at line 592 of file TargetInstrInfo.h.

References llvm_unreachable.

◆ insertNoop()

void TargetInstrInfo::insertNoop ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  MI 
) const
virtual

Insert a noop into the instruction stream at the specified point.

insertNoop - Insert a noop into the instruction stream at the specified point.

Definition at line 67 of file TargetInstrInfo.cpp.

References llvm_unreachable.

Referenced by insertNoops().

◆ insertNoops()

void TargetInstrInfo::insertNoops ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  MI,
unsigned  Quantity 
) const
virtual

Insert noops into the instruction stream at the specified point.

insertNoops - Insert noops into the instruction stream at the specified point.

Definition at line 74 of file TargetInstrInfo.cpp.

References i, insertNoop(), MBB, and MI.

◆ insertOutlinedCall()

virtual MachineBasicBlock::iterator llvm::TargetInstrInfo::insertOutlinedCall ( Module M,
MachineBasicBlock MBB,
MachineBasicBlock::iterator It,
MachineFunction MF,
const outliner::Candidate C 
) const
inlinevirtual

Insert a call to an outlined function into the program.

Returns an iterator to the spot where we inserted the call. This must be implemented by the target.

Definition at line 1947 of file TargetInstrInfo.h.

References llvm_unreachable.

◆ insertSelect()

virtual void llvm::TargetInstrInfo::insertSelect ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  I,
const DebugLoc DL,
Register  DstReg,
ArrayRef< MachineOperand Cond,
Register  TrueReg,
Register  FalseReg 
) const
inlinevirtual

Insert a select instruction into MBB before I that will copy TrueReg to DstReg when Cond is true, and FalseReg to DstReg when Cond is false.

This function can only be called after canInsertSelect() returned true. The condition in Cond comes from analyzeBranch, and it can be assumed that the same flags or registers required by Cond are available at the insertion point.

Parameters
MBBBlock where select instruction should be inserted.
IInsertion point.
DLSource location for debugging.
DstRegVirtual register to be defined by select instruction.
CondCondition as computed by analyzeBranch.
TrueRegVirtual register to copy when Cond is true.
FalseRegVirtual register to copy when Cons is false.

Definition at line 899 of file TargetInstrInfo.h.

References llvm_unreachable.

◆ insertUnconditionalBranch()

unsigned llvm::TargetInstrInfo::insertUnconditionalBranch ( MachineBasicBlock MBB,
MachineBasicBlock DestBB,
const DebugLoc DL,
int BytesAdded = nullptr 
) const
inline

◆ isAddImmediate()

virtual Optional<RegImmPair> llvm::TargetInstrInfo::isAddImmediate ( const MachineInstr MI,
Register  Reg 
) const
inlinevirtual

If the specific machine instruction is an instruction that adds an immediate value and a physical register, and stores the result in the given physical register Reg, return a pair of the source register and the offset which has been added.

Definition at line 1021 of file TargetInstrInfo.h.

References llvm::None.

Referenced by describeLoadedValue().

◆ isAsCheapAsAMove()

virtual bool llvm::TargetInstrInfo::isAsCheapAsAMove ( const MachineInstr MI) const
inlinevirtual

Return true if the instruction is as cheap as a move instruction.

Targets for different archs need to override this, and different micro-architectures can also be finely tuned inside.

Definition at line 374 of file TargetInstrInfo.h.

References MI.

Referenced by llvm::LiveRangeEdit::canRematerializeAt().

◆ isAssociativeAndCommutative()

virtual bool llvm::TargetInstrInfo::isAssociativeAndCommutative ( const MachineInstr Inst) const
inlinevirtual

Return true when \P Inst is both associative and commutative.

Definition at line 1149 of file TargetInstrInfo.h.

Referenced by hasReassociableSibling(), and isReassociationCandidate().

◆ isBasicBlockPrologue()

virtual bool llvm::TargetInstrInfo::isBasicBlockPrologue ( const MachineInstr MI) const
inlinevirtual

True if the instruction is bound to the top of its basic block and no other instructions shall be inserted before it.

This can be implemented to prevent register allocator to insert spills before such instructions.

Definition at line 1882 of file TargetInstrInfo.h.

◆ isBranchOffsetInRange()

virtual bool llvm::TargetInstrInfo::isBranchOffsetInRange ( unsigned  BranchOpc,
int64_t  BrOffset 
) const
inlinevirtual
Returns
true if a branch from an instruction with opcode BranchOpc bytes is capable of jumping to a position BrOffset bytes away.

Definition at line 578 of file TargetInstrInfo.h.

References llvm_unreachable.

◆ isCoalescableExtInstr()

virtual bool llvm::TargetInstrInfo::isCoalescableExtInstr ( const MachineInstr MI,
Register SrcReg,
Register DstReg,
unsigned &  SubIdx 
) const
inlinevirtual

Return true if the instruction is a "coalescable" extension instruction.

That is, it's like a copy where it's legal for the source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns true, then it's expected the pre-extension value is available as a subreg of the result register. This also returns the sub-register index in SubIdx.

Definition at line 252 of file TargetInstrInfo.h.

◆ isCopyInstr()

Optional<DestSourcePair> llvm::TargetInstrInfo::isCopyInstr ( const MachineInstr MI) const
inline

If the specific machine instruction is a instruction that moves/copies value from one register to another register return destination and source registers as machine operands.

For COPY-instruction the method naturally returns destination and source registers as machine operands, for all other instructions the method calls target-dependent implementation.

Definition at line 1010 of file TargetInstrInfo.h.

References isCopyInstrImpl(), and MI.

Referenced by describeLoadedValue().

◆ isCopyInstrImpl()

virtual Optional<DestSourcePair> llvm::TargetInstrInfo::isCopyInstrImpl ( const MachineInstr MI) const
inlineprotectedvirtual

Target-dependent implementation for IsCopyInstr.

If the specific machine instruction is a instruction that moves/copies value from one register to another register return destination and source registers as machine operands.

Definition at line 988 of file TargetInstrInfo.h.

References llvm::None.

Referenced by isCopyInstr().

◆ isExtendLikelyToBeFolded()

virtual bool llvm::TargetInstrInfo::isExtendLikelyToBeFolded ( MachineInstr ExtMI,
MachineRegisterInfo MRI 
) const
inlinevirtual

Given the generic extension instruction ExtMI, returns true if this extension is a likely candidate for being folded into an another instruction.

Definition at line 1978 of file TargetInstrInfo.h.

Referenced by llvm::CombinerHelper::matchExtendThroughPhis().

◆ isFrameInstr()

bool llvm::TargetInstrInfo::isFrameInstr ( const MachineInstr I) const
inline

Returns true if the argument is a frame pseudo instruction.

Definition at line 202 of file TargetInstrInfo.h.

References getCallFrameDestroyOpcode(), getCallFrameSetupOpcode(), and I.

Referenced by getFrameSize(), and getSPAdjust().

◆ isFrameSetup()

bool llvm::TargetInstrInfo::isFrameSetup ( const MachineInstr I) const
inline

Returns true if the argument is a frame setup pseudo instruction.

Definition at line 208 of file TargetInstrInfo.h.

References getCallFrameSetupOpcode(), and I.

Referenced by getFrameTotalSize().

◆ isFunctionSafeToOutlineFrom()

virtual bool llvm::TargetInstrInfo::isFunctionSafeToOutlineFrom ( MachineFunction MF,
bool  OutlineFromLinkOnceODRs 
) const
inlinevirtual

Return true if the function can safely be outlined from.

A function MF is considered safe for outlining if an outlined function produced from instructions in F will produce a program which produces the same output for any set of given inputs.

Definition at line 1958 of file TargetInstrInfo.h.

References llvm_unreachable.

◆ isGenericOpcode()

static bool llvm::TargetInstrInfo::isGenericOpcode ( unsigned  Opc)
inlinestatic

Definition at line 108 of file TargetInstrInfo.h.

◆ isHighLatencyDef()

virtual bool llvm::TargetInstrInfo::isHighLatencyDef ( int  opc) const
inlinevirtual

Return true if this opcode has high latency to its result.

Definition at line 1632 of file TargetInstrInfo.h.

Referenced by llvm::ScheduleDAGSDNodes::computeLatency(), and defaultDefLatency().

◆ isIgnorableUse()

virtual bool llvm::TargetInstrInfo::isIgnorableUse ( const MachineOperand MO) const
inlinevirtual

Given MO is a PhysReg use return if it can be ignored for the purpose of instruction rematerialization.

Definition at line 134 of file TargetInstrInfo.h.

Referenced by llvm::LiveRangeEdit::allUsesAvailableAt().

◆ isLegalToSplitMBBAt()

virtual bool llvm::TargetInstrInfo::isLegalToSplitMBBAt ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  MBBI 
) const
inlinevirtual

Return true if it's legal to split the given basic block at the specified instruction (i.e.

instruction would be the start of a new basic block).

Definition at line 787 of file TargetInstrInfo.h.

◆ isLoadFromStackSlot() [1/2]

virtual unsigned llvm::TargetInstrInfo::isLoadFromStackSlot ( const MachineInstr MI,
int FrameIndex 
) const
inlinevirtual

If the specified machine instruction is a direct load from a stack slot, return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot.

If not, return 0. This predicate must return 0 if the instruction has any side effects other than loading from the stack slot.

Definition at line 262 of file TargetInstrInfo.h.

Referenced by foldMemoryOperand(), and isLoadFromStackSlot().

◆ isLoadFromStackSlot() [2/2]

virtual unsigned llvm::TargetInstrInfo::isLoadFromStackSlot ( const MachineInstr MI,
int FrameIndex,
unsigned &  MemBytes 
) const
inlinevirtual

Optional extension of isLoadFromStackSlot that returns the number of bytes loaded from the stack.

This must be implemented if a backend supports partial stack slot spills/loads to further disambiguate what the load does.

Definition at line 271 of file TargetInstrInfo.h.

References llvm::ISD::FrameIndex, isLoadFromStackSlot(), and MI.

◆ isLoadFromStackSlotPostFE()

virtual unsigned llvm::TargetInstrInfo::isLoadFromStackSlotPostFE ( const MachineInstr MI,
int FrameIndex 
) const
inlinevirtual

Check for post-frame ptr elimination stack locations as well.

This uses a heuristic so it isn't reliable for correctness.

Definition at line 280 of file TargetInstrInfo.h.

◆ isMBBSafeToOutlineFrom()

virtual bool llvm::TargetInstrInfo::isMBBSafeToOutlineFrom ( MachineBasicBlock MBB,
unsigned &  Flags 
) const
inlinevirtual

Optional target hook that returns true if MBB is safe to outline from, and returns any target-specific information in Flags.

Definition at line 1931 of file TargetInstrInfo.h.

◆ isPCRelRegisterOperandLegal()

virtual bool llvm::TargetInstrInfo::isPCRelRegisterOperandLegal ( const MachineOperand MO) const
inlinevirtual

Allow targets to tell MachineVerifier whether a specific register MachineOperand can be used as part of PC-relative addressing.

PC-relative addressing modes in many CISC architectures contain (non-PC) registers as offsets or scaling values, which inherently tags the corresponding MachineOperand with OPERAND_PCREL.

Parameters
MOThe MachineOperand in question. MO.isReg() should always be true.
Returns
Whether this operand is allowed to be used PC-relatively.

Definition at line 978 of file TargetInstrInfo.h.

◆ isPostIncrement()

virtual bool llvm::TargetInstrInfo::isPostIncrement ( const MachineInstr MI) const
inlinevirtual

Return true for post-incremented instructions.

Definition at line 1426 of file TargetInstrInfo.h.

◆ isPredicable()

virtual bool llvm::TargetInstrInfo::isPredicable ( const MachineInstr MI) const
inlinevirtual

Return true if the specified instruction can be predicated.

By default, this returns true for every instruction with a PredicateOperand.

Definition at line 1486 of file TargetInstrInfo.h.

References MI.

Referenced by llvm::R600InstrInfo::isPredicable().

◆ isPredicated()

virtual bool llvm::TargetInstrInfo::isPredicated ( const MachineInstr MI) const
inlinevirtual

Returns true if the instruction is already predicated.

Definition at line 1429 of file TargetInstrInfo.h.

Referenced by llvm::TargetSchedModel::computeOutputLatency(), llvm::rdf::TargetOperandInfo::isPreserving(), and isUnpredicatedTerminator().

◆ isProfitableToDupForIfCvt()

virtual bool llvm::TargetInstrInfo::isProfitableToDupForIfCvt ( MachineBasicBlock MBB,
unsigned  NumCycles,
BranchProbability  Probability 
) const
inlinevirtual

Return true if it's profitable for if-converter to duplicate instructions of specified accumulated instruction latencies in the specified MBB to enable if-conversion.

The probability of the instructions being executed is given by Probability, and Confidence is a measure of our confidence that it will be properly predicted.

Definition at line 823 of file TargetInstrInfo.h.

◆ isProfitableToIfCvt() [1/2]

virtual bool llvm::TargetInstrInfo::isProfitableToIfCvt ( MachineBasicBlock MBB,
unsigned  NumCycles,
unsigned  ExtraPredCycles,
BranchProbability  Probability 
) const
inlinevirtual

Return true if it's profitable to predicate instructions with accumulated instruction latency of "NumCycles" of the specified basic block, where the probability of the instructions being executed is given by Probability, and Confidence is a measure of our confidence that it will be properly predicted.

Definition at line 797 of file TargetInstrInfo.h.

◆ isProfitableToIfCvt() [2/2]

virtual bool llvm::TargetInstrInfo::isProfitableToIfCvt ( MachineBasicBlock TMBB,
unsigned  NumTCycles,
unsigned  ExtraTCycles,
MachineBasicBlock FMBB,
unsigned  NumFCycles,
unsigned  ExtraFCycles,
BranchProbability  Probability 
) const
inlinevirtual

Second variant of isProfitableToIfCvt.

This one checks for the case where two basic blocks from true and false path of a if-then-else (diamond) are predicated on mutually exclusive predicates, where the probability of the true path being taken is given by Probability, and Confidence is a measure of our confidence that it will be properly predicted.

Definition at line 809 of file TargetInstrInfo.h.

◆ isProfitableToUnpredicate()

virtual bool llvm::TargetInstrInfo::isProfitableToUnpredicate ( MachineBasicBlock TMBB,
MachineBasicBlock FMBB 
) const
inlinevirtual

Return true if it's profitable to unpredicate one side of a 'diamond', i.e.

two sides of if-else predicated on mutually exclusive predicates. e.g. subeq r0, r1, #1 addne r0, r1, #1 => sub r0, r1, #1 addne r0, r1, #1

This may be profitable is conditional instructions are always executed.

Definition at line 853 of file TargetInstrInfo.h.

◆ isReallyTriviallyReMaterializable()

virtual bool llvm::TargetInstrInfo::isReallyTriviallyReMaterializable ( const MachineInstr MI,
AAResults AA 
) const
inlineprotectedvirtual

For instructions with opcodes for which the M_REMATERIALIZABLE flag is set, this hook lets the target specify whether the instruction is actually trivially rematerializable, taking into consideration its operands.

This predicate must return false if the instruction has any side effects other than producing a value, or if it requres any address registers that are not always available. Requirements must be check as stated in isTriviallyReMaterializable() .

Definition at line 146 of file TargetInstrInfo.h.

Referenced by isTriviallyReMaterializable().

◆ isReassociationCandidate()

bool TargetInstrInfo::isReassociationCandidate ( const MachineInstr Inst,
bool &  Commuted 
) const

Return true if the input \P Inst is part of a chain of dependent ops that are suitable for reassociation, otherwise return false.

If the instruction's operands must be commuted to have a previous instruction of the same type define the first source operand, \P Commuted will be set to true.

Definition at line 749 of file TargetInstrInfo.cpp.

References llvm::MachineInstr::getParent(), hasReassociableOperands(), hasReassociableSibling(), and isAssociativeAndCommutative().

Referenced by getMachineCombinerPatterns().

◆ isSafeToMoveRegClassDefs()

virtual bool llvm::TargetInstrInfo::isSafeToMoveRegClassDefs ( const TargetRegisterClass RC) const
inlinevirtual

Return true if it's safe to move a machine instruction that defines the specified register class.

Definition at line 1492 of file TargetInstrInfo.h.

◆ isSchedulingBoundary()

bool TargetInstrInfo::isSchedulingBoundary ( const MachineInstr MI,
const MachineBasicBlock MBB,
const MachineFunction MF 
) const
virtual

Test if the given instruction should be considered a scheduling boundary.

isSchedulingBoundary - Test if the given instruction should be considered a scheduling boundary.

This primarily includes labels and terminators.

Definition at line 1021 of file TargetInstrInfo.cpp.

References llvm::TargetSubtargetInfo::getRegisterInfo(), llvm::TargetLoweringBase::getStackPointerRegisterToSaveRestore(), llvm::MachineFunction::getSubtarget(), llvm::TargetSubtargetInfo::getTargetLowering(), llvm::ISD::INLINEASM_BR, MI, and TRI.

Referenced by llvm::AArch64InstrInfo::isSchedulingBoundary(), llvm::X86InstrInfo::isSchedulingBoundary(), and llvm::PPCInstrInfo::isSchedulingBoundary().

◆ isStackSlotCopy()

virtual bool llvm::TargetInstrInfo::isStackSlotCopy ( const MachineInstr MI,
int DestFrameIndex,
int SrcFrameIndex 
) const
inlinevirtual

Return true if the specified machine instruction is a copy of one stack slot to another and has no other effect.

Provide the identity of the two frame indices.

Definition at line 336 of file TargetInstrInfo.h.

◆ isStoreToStackSlot() [1/2]

virtual unsigned llvm::TargetInstrInfo::isStoreToStackSlot ( const MachineInstr MI,
int FrameIndex 
) const
inlinevirtual

If the specified machine instruction is a direct store to a stack slot, return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot.

If not, return 0. This predicate must return 0 if the instruction has any side effects other than storing to the stack slot.

Definition at line 300 of file TargetInstrInfo.h.

Referenced by isStoreToStackSlot().

◆ isStoreToStackSlot() [2/2]

virtual unsigned llvm::TargetInstrInfo::isStoreToStackSlot ( const MachineInstr MI,
int FrameIndex,
unsigned &  MemBytes 
) const
inlinevirtual

Optional extension of isStoreToStackSlot that returns the number of bytes stored to the stack.

This must be implemented if a backend supports partial stack slot spills/loads to further disambiguate what the store does.

Definition at line 309 of file TargetInstrInfo.h.

References llvm::ISD::FrameIndex, isStoreToStackSlot(), and MI.

◆ isStoreToStackSlotPostFE()

virtual unsigned llvm::TargetInstrInfo::isStoreToStackSlotPostFE ( const MachineInstr MI,
int FrameIndex 
) const
inlinevirtual

Check for post-frame ptr elimination stack locations as well.

This uses a heuristic, so it isn't reliable for correctness.

Definition at line 318 of file TargetInstrInfo.h.

◆ isSubregFoldable()

virtual bool llvm::TargetInstrInfo::isSubregFoldable ( ) const
inlinevirtual

Check whether the target can fold a load that feeds a subreg operand (or a subreg operand that feeds a store).

For example, X86 may want to return true if it can fold movl (esp), eax subb, al, ... Into: subb (esp), ...

Ideally, we'd like the target implementation of foldMemoryOperand() to reject subregs - but since this behavior used to be enforced in the target-independent code, moving this responsibility to the targets has the potential of causing nasty silent breakage in out-of-tree targets.

Definition at line 1080 of file TargetInstrInfo.h.

◆ isTailCall()

virtual bool llvm::TargetInstrInfo::isTailCall ( const MachineInstr Inst) const
inlinevirtual

Determines whether Inst is a tail call instruction.

Override this method on targets that do not properly set MCID::Return and MCID::Call on tail call instructions."

Definition at line 1875 of file TargetInstrInfo.h.

References llvm::MachineInstr::isCall(), and llvm::MachineInstr::isReturn().

◆ isThroughputPattern()

bool TargetInstrInfo::isThroughputPattern ( MachineCombinerPattern  Pattern) const
virtual

Return true when a code sequence can improve throughput.

Return true when a code sequence can improve loop throughput.

It should be called only for instructions in loops.

Parameters
Pattern- combiner pattern

Definition at line 801 of file TargetInstrInfo.cpp.

◆ isTriviallyReMaterializable()

bool llvm::TargetInstrInfo::isTriviallyReMaterializable ( const MachineInstr MI,
AAResults AA = nullptr 
) const
inline

Return true if the instruction is trivially rematerializable, meaning it has no side effects and requires no operands that aren't always available.

This means the only allowed uses are constants and unallocatable physical registers so that the instructions result is independent of the place in the function.

Definition at line 124 of file TargetInstrInfo.h.

References isReallyTriviallyReMaterializable(), and MI.

Referenced by llvm::calculateRegAllocScore(), and llvm::LiveRangeEdit::checkRematerializable().

◆ isUnconditionalTailCall()

virtual bool llvm::TargetInstrInfo::isUnconditionalTailCall ( const MachineInstr MI) const
inlinevirtual

Returns true if MI is an unconditional tail call.

Definition at line 1441 of file TargetInstrInfo.h.

◆ isUnpredicatedTerminator()

bool TargetInstrInfo::isUnpredicatedTerminator ( const MachineInstr MI) const

Returns true if the instruction is a terminator instruction that has not been predicated.

Definition at line 320 of file TargetInstrInfo.cpp.

References isPredicated(), and MI.

◆ isUnspillableTerminator()

bool llvm::TargetInstrInfo::isUnspillableTerminator ( const MachineInstr MI) const
inline

Return true if the given instruction is terminator that is unspillable, according to isUnspillableTerminatorImpl.

Definition at line 360 of file TargetInstrInfo.h.

References isUnspillableTerminatorImpl(), and MI.

◆ isUnspillableTerminatorImpl()

virtual bool llvm::TargetInstrInfo::isUnspillableTerminatorImpl ( const MachineInstr MI) const
inlineprotectedvirtual

Return true if the given terminator MI is not expected to spill.

This sets the live interval as not spillable and adjusts phi node lowering to not introduce copies after the terminator. Use with care, these are currently used for hardware loop intrinsics in very controlled situations, created prior to registry allocation in loops that only have single phi users for the terminators value. They may run out of registers if not used carefully.

Definition at line 999 of file TargetInstrInfo.h.

Referenced by isUnspillableTerminator().

◆ isZeroCost()

bool llvm::TargetInstrInfo::isZeroCost ( unsigned  Opcode) const
inline

Return true for pseudo instructions that don't consume any machine resources in their current form.

These are common cases that the scheduler should consider free, rather than conservatively handling them as instructions with no itinerary.

Definition at line 1594 of file TargetInstrInfo.h.

Referenced by llvm::ScoreboardHazardRecognizer::EmitInstruction().

◆ loadRegFromStackSlot()

virtual void llvm::TargetInstrInfo::loadRegFromStackSlot ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  MI,
Register  DestReg,
int  FrameIndex,
const TargetRegisterClass RC,
const TargetRegisterInfo TRI 
) const
inlinevirtual

Load the specified register of the given register class from the specified stack frame index.

The load instruction is to be added to the given machine basic block before the specified machine instruction.

Definition at line 1051 of file TargetInstrInfo.h.

References llvm_unreachable.

Referenced by foldMemoryOperand().

◆ mergeOutliningCandidateAttributes()

void TargetInstrInfo::mergeOutliningCandidateAttributes ( Function F,
std::vector< outliner::Candidate > &  Candidates 
) const
virtual

Optional target hook to create the LLVM IR attributes for the outlined function.

If overridden, the overriding function must call the default implementation.

Definition at line 1404 of file TargetInstrInfo.cpp.

References llvm::all_of(), F, llvm::outliner::Candidate::front(), llvm::Function::getFnAttribute(), getFunction(), llvm::MachineFunction::getFunction(), llvm::outliner::Candidate::getMF(), and llvm::Function::hasFnAttribute().

◆ operator=()

TargetInstrInfo& llvm::TargetInstrInfo::operator= ( const TargetInstrInfo )
delete

◆ optimizeCompareInstr()

virtual bool llvm::TargetInstrInfo::optimizeCompareInstr ( MachineInstr CmpInstr,
Register  SrcReg,
Register  SrcReg2,
int64_t  Mask,
int64_t  Value,
const MachineRegisterInfo MRI 
) const
inlinevirtual

See if the comparison instruction can be converted into something more efficient.

E.g., on ARM most instructions can set the flags register, obviating the need for a separate CMP.

Definition at line 1550 of file TargetInstrInfo.h.

◆ optimizeCondBranch()

virtual bool llvm::TargetInstrInfo::optimizeCondBranch ( MachineInstr MI) const
inlinevirtual

Definition at line 1556 of file TargetInstrInfo.h.

◆ optimizeLoadInstr()

virtual MachineInstr* llvm::TargetInstrInfo::optimizeLoadInstr ( MachineInstr MI,
const MachineRegisterInfo MRI,
Register FoldAsLoadDefReg,
MachineInstr *&  DefMI 
) const
inlinevirtual

Try to remove the load by folding it to a register operand at the use.

We fold the load instructions if and only if the def and use are in the same BB. We only look at one load and see whether it can be folded into MI. FoldAsLoadDefReg is the virtual register defined by the load we are trying to fold. DefMI returns the machine instruction that defines FoldAsLoadDefReg, and the function returns the machine instruction generated due to folding.

Definition at line 1565 of file TargetInstrInfo.h.

◆ optimizeSelect()

virtual MachineInstr* llvm::TargetInstrInfo::optimizeSelect ( MachineInstr MI,
SmallPtrSetImpl< MachineInstr * > &  NewMIs,
bool  PreferFalse = false 
) const
inlinevirtual

Given a select instruction that was understood by analyzeSelect and returned Optimizable = true, attempt to optimize MI by merging it with one of its operands.

Returns NULL on failure.

When successful, returns the new select instruction. The client is responsible for deleting MI.

If both sides of the select can be optimized, PreferFalse is used to pick a side.

Parameters
MIOptimizable select instruction.
NewMIsSet that record all MIs in the basic block up to MI. Has to be updated with any newly created MI or deleted ones.
PreferFalseTry to optimize FalseOp instead of TrueOp.
Returns
Optimized instruction or NULL.

Definition at line 947 of file TargetInstrInfo.h.

References llvm_unreachable.

◆ PredicateInstruction()

bool TargetInstrInfo::PredicateInstruction ( MachineInstr MI,
ArrayRef< MachineOperand Pred 
) const
virtual

◆ predictBranchSizeForIfCvt()

virtual unsigned llvm::TargetInstrInfo::predictBranchSizeForIfCvt ( MachineInstr MI) const
inlinevirtual

Return an estimate for the code size reduction (in bytes) which will be caused by removing the given branch instruction during if-conversion.

Definition at line 838 of file TargetInstrInfo.h.

References getInstSizeInBytes(), and MI.

◆ preservesZeroValueInReg()

virtual bool llvm::TargetInstrInfo::preservesZeroValueInReg ( const MachineInstr MI,
const Register  NullValueReg,
const TargetRegisterInfo TRI 
) const
inlinevirtual

Returns true if MI's Def is NullValueReg, and the MI does not change the Zero value.

i.e. cases such as rax = shr rax, X where NullValueReg = rax. Note that if the NullValueReg is non-zero, this function can return true even if becomes zero. Specifically cases such as NullValueReg = shl NullValueReg, 63.

Definition at line 1377 of file TargetInstrInfo.h.

◆ produceSameValue()

bool TargetInstrInfo::produceSameValue ( const MachineInstr MI0,
const MachineInstr MI1,
const MachineRegisterInfo MRI = nullptr 
) const
virtual

Return true if two machine instructions would produce identical values.

By default, this is only true when the two instructions are deemed identical except for defs. If this function is called when the IR is still in SSA form, the caller can pass the MachineRegisterInfo for aggressive checks.

Definition at line 429 of file TargetInstrInfo.cpp.

References llvm::MachineInstr::IgnoreVRegDefs, and llvm::MachineInstr::isIdenticalTo().

Referenced by llvm::CombinerHelper::matchEqualDefs().

◆ reassociateOps()

void TargetInstrInfo::reassociateOps ( MachineInstr Root,
MachineInstr Prev,
MachineCombinerPattern  Pattern,
SmallVectorImpl< MachineInstr * > &  InsInstrs,
SmallVectorImpl< MachineInstr * > &  DelInstrs,
DenseMap< unsigned, unsigned > &  InstrIdxForVirtReg 
) const

◆ reduceLoopCount()

virtual unsigned llvm::TargetInstrInfo::reduceLoopCount ( MachineBasicBlock MBB,
MachineBasicBlock PreHeader,
MachineInstr IndVar,
MachineInstr Cmp,
SmallVectorImpl< MachineOperand > &  Cond,
SmallVectorImpl< MachineInstr * > &  PrevInsts,
unsigned  Iter,
unsigned  MaxIter 
) const
inlinevirtual

Generate code to reduce the loop iteration by one and check if the loop is finished.

Return the value/register of the new loop count. We need this function when peeling off one or more iterations of a loop. This function assumes the nth iteration is peeled first.

Definition at line 770 of file TargetInstrInfo.h.

References llvm_unreachable.

◆ reMaterialize()

void TargetInstrInfo::reMaterialize ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  MI,
Register  DestReg,
unsigned  SubIdx,
const MachineInstr Orig,
const TargetRegisterInfo TRI 
) const
virtual

Re-issue the specified 'original' instruction at the specific location targeting a new destination register.

The register in Orig->getOperand(0).getReg() will be substituted by DestReg:SubIdx. Any existing subreg index is preserved or composed with SubIdx.

Definition at line 419 of file TargetInstrInfo.cpp.

References llvm::MachineFunction::CloneMachineInstr(), llvm::MachineBasicBlock::getParent(), I, llvm::MachineBasicBlock::insert(), MBB, MI, and TRI.

Referenced by llvm::LiveRangeEdit::rematerializeAt().

◆ removeBranch()

virtual unsigned llvm::TargetInstrInfo::removeBranch ( MachineBasicBlock MBB,
int BytesRemoved = nullptr 
) const
inlinevirtual

Remove the branching code at the end of the specific MBB.

This is only invoked in cases where analyzeBranch returns success. It returns the number of instructions that were removed. If BytesRemoved is non-null, report the change in code size from the removed instructions.

Definition at line 680 of file TargetInstrInfo.h.

References llvm_unreachable.

Referenced by llvm::PeelingModuloScheduleExpander::CreateLCSSAExitingBlock(), and llvm::PeelingModuloScheduleExpander::fixupBranches().

◆ replaceBranchWithTailCall()

virtual void llvm::TargetInstrInfo::replaceBranchWithTailCall ( MachineBasicBlock MBB,
SmallVectorImpl< MachineOperand > &  Cond,
const MachineInstr TailCall 
) const
inlinevirtual

Replace the conditional branch in MBB with a conditional tail call.

Definition at line 1452 of file TargetInstrInfo.h.

References llvm_unreachable.

◆ ReplaceTailWithBranchTo()

void TargetInstrInfo::ReplaceTailWithBranchTo ( MachineBasicBlock::iterator  Tail,
MachineBasicBlock NewDest 
) const
virtual

Delete the instruction OldInst and everything after it, replacing it with an unconditional branch to NewDest.

ReplaceTailWithBranchTo - Delete the instruction OldInst and everything after it, replacing it with an unconditional branch to NewDest.

This is used by the tail merging pass.

Definition at line 141 of file TargetInstrInfo.cpp.

References llvm::MachineBasicBlock::addSuccessor(), DL, llvm::MachineBasicBlock::end(), llvm::MachineBasicBlock::erase(), llvm::MachineFunction::eraseCallSiteInfo(), llvm::MachineBasicBlock::getParent(), insertBranch(), MBB, MI, llvm::MachineBasicBlock::removeSuccessor(), llvm::MachineBasicBlock::succ_begin(), llvm::MachineBasicBlock::succ_empty(), and llvm::CallingConv::Tail.

Referenced by llvm::Thumb2InstrInfo::ReplaceTailWithBranchTo().

◆ reverseBranchCondition()

virtual bool llvm::TargetInstrInfo::reverseBranchCondition ( SmallVectorImpl< MachineOperand > &  Cond) const
inlinevirtual

Reverses the branch condition of the specified condition list, returning false on success and true if it cannot be reversed.

Definition at line 1409 of file TargetInstrInfo.h.

◆ setExecutionDomain()

virtual void llvm::TargetInstrInfo::setExecutionDomain ( MachineInstr MI,
unsigned  Domain 
) const
inlinevirtual

Change the opcode of MI to execute in Domain.

The bit (1 << Domain) must be set in the mask returned from getExecutionDomain(MI).

Definition at line 1687 of file TargetInstrInfo.h.

◆ setSpecialOperandAttr() [1/2]

virtual void llvm::TargetInstrInfo::setSpecialOperandAttr ( MachineInstr MI,
uint16_t  Flags 
) const
inlinevirtual

Definition at line 1193 of file TargetInstrInfo.h.

◆ setSpecialOperandAttr() [2/2]

virtual void llvm::TargetInstrInfo::setSpecialOperandAttr ( MachineInstr OldMI1,
MachineInstr OldMI2,
MachineInstr NewMI1,
MachineInstr NewMI2 
) const
inlinevirtual

This is an architecture-specific helper function of reassociateOps.

Set special operand attributes for new instructions after reassociation.

Definition at line 1189 of file TargetInstrInfo.h.

Referenced by reassociateOps().

◆ shouldClusterMemOps()

virtual bool llvm::TargetInstrInfo::shouldClusterMemOps ( ArrayRef< const MachineOperand * >  BaseOps1,
ArrayRef< const MachineOperand * >  BaseOps2,
unsigned  NumLoads,
unsigned  NumBytes 
) const
inlinevirtual

Returns true if the two given memory operations should be scheduled adjacent.

Note that you have to add: DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI)); or DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI)); to TargetPassConfig::createMachineScheduler() to have an effect.

BaseOps1 and BaseOps2 are memory operands of two memory operations. NumLoads is the number of loads that will be in the cluster if this hook returns true. NumBytes is the number of bytes that will be loaded from all the clustered loads if this hook returns true.

Definition at line 1400 of file TargetInstrInfo.h.

References llvm_unreachable.

◆ shouldOutlineFromFunctionByDefault()

virtual bool llvm::TargetInstrInfo::shouldOutlineFromFunctionByDefault ( MachineFunction MF) const
inlinevirtual

Return true if the function should be outlined from by default.

Definition at line 1965 of file TargetInstrInfo.h.

◆ shouldReduceRegisterPressure()

virtual bool llvm::TargetInstrInfo::shouldReduceRegisterPressure ( MachineBasicBlock MBB,
RegisterClassInfo RegClassInfo 
) const
inlinevirtual

Return true if target supports reassociation of instructions in machine combiner pass to reduce register pressure for a given BB.

Definition at line 1126 of file TargetInstrInfo.h.

◆ shouldScheduleLoadsNear()

virtual bool llvm::TargetInstrInfo::shouldScheduleLoadsNear ( SDNode Load1,
SDNode Load2,
int64_t  Offset1,
int64_t  Offset2,
unsigned  NumLoads 
) const
inlinevirtual

This is a used by the pre-regalloc scheduler to determine (in conjunction with areLoadsFromSameBasePtr) if two loads should be scheduled together.

On some targets if two loads are loading from addresses in the same cache line, it's better if they are scheduled together. This function takes two integers that represent the load offsets from the common base address. It returns true if it decides it's desirable to schedule the two loads together. "NumLoads" is the number of loads that have already been scheduled after Load1.

Definition at line 1325 of file TargetInstrInfo.h.

◆ shouldSink()

virtual bool llvm::TargetInstrInfo::shouldSink ( const MachineInstr MI) const
inlinevirtual

Return true if the instruction should be sunk by MachineSink.

MachineSink determines on its own whether the instruction is safe to sink; this gives the target a hook to override the default behavior with regards to which instructions should be sunk.

Definition at line 383 of file TargetInstrInfo.h.

◆ storeRegToStackSlot()

virtual void llvm::TargetInstrInfo::storeRegToStackSlot ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  MI,
Register  SrcReg,
bool  isKill,
int  FrameIndex,
const TargetRegisterClass RC,
const TargetRegisterInfo TRI 
) const
inlinevirtual

Store the specified register of the given register class to the specified stack frame index.

The store instruction is to be added to the given machine basic block before the specified machine instruction. If isKill is true, the register operand is the last use and must be marked kill.

Definition at line 1039 of file TargetInstrInfo.h.

References llvm_unreachable.

Referenced by foldMemoryOperand().

◆ SubsumesPredicate()

virtual bool llvm::TargetInstrInfo::SubsumesPredicate ( ArrayRef< MachineOperand Pred1,
ArrayRef< MachineOperand Pred2 
) const
inlinevirtual

Returns true if the first specified predicate subsumes the second, e.g.

GE subsumes GT.

Definition at line 1465 of file TargetInstrInfo.h.

◆ unfoldMemoryOperand() [1/2]

virtual bool llvm::TargetInstrInfo::unfoldMemoryOperand ( MachineFunction MF,
MachineInstr MI,
unsigned  Reg,
bool  UnfoldLoad,
bool  UnfoldStore,
SmallVectorImpl< MachineInstr * > &  NewMIs 
) const
inlinevirtual

unfoldMemoryOperand - Separate a single instruction which folded a load or a store or a load and a store into two or more instruction.

If this is possible, returns true as well as the new instructions by reference.

Definition at line 1284 of file TargetInstrInfo.h.

◆ unfoldMemoryOperand() [2/2]

virtual bool llvm::TargetInstrInfo::unfoldMemoryOperand ( SelectionDAG DAG,
SDNode N,
SmallVectorImpl< SDNode * > &  NewNodes 
) const
inlinevirtual

Definition at line 1290 of file TargetInstrInfo.h.

◆ useMachineCombiner()

virtual bool llvm::TargetInstrInfo::useMachineCombiner ( ) const
inlinevirtual

Return true when a target supports MachineCombiner.

Definition at line 1196 of file TargetInstrInfo.h.

◆ usePreRAHazardRecognizer()

bool TargetInstrInfo::usePreRAHazardRecognizer ( ) const

Provide a global flag for disabling the PreRA hazard recognizer that targets may choose to honor.

Definition at line 1044 of file TargetInstrInfo.cpp.

References DisableHazardRecognizer.

◆ verifyInstruction()

virtual bool llvm::TargetInstrInfo::verifyInstruction ( const MachineInstr MI,
StringRef ErrInfo 
) const
inlinevirtual

Perform target-specific instruction verification.

Definition at line 1654 of file TargetInstrInfo.h.

Member Data Documentation

◆ CommuteAnyOperandIndex

const unsigned llvm::TargetInstrInfo::CommuteAnyOperandIndex = ~0U
static

The documentation for this class was generated from the following files: