LLVM  14.0.0git
TargetInstrInfo.h
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1 //===- llvm/CodeGen/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file describes the target machine instruction set to the code generator.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_CODEGEN_TARGETINSTRINFO_H
14 #define LLVM_CODEGEN_TARGETINSTRINFO_H
15 
16 #include "llvm/ADT/ArrayRef.h"
17 #include "llvm/ADT/DenseMap.h"
18 #include "llvm/ADT/DenseMapInfo.h"
19 #include "llvm/ADT/None.h"
30 #include "llvm/MC/MCInstrInfo.h"
33 #include <cassert>
34 #include <cstddef>
35 #include <cstdint>
36 #include <utility>
37 #include <vector>
38 
39 namespace llvm {
40 
41 class AAResults;
42 class DFAPacketizer;
43 class InstrItineraryData;
44 class LiveIntervals;
45 class LiveVariables;
46 class MachineLoop;
47 class MachineMemOperand;
48 class MachineRegisterInfo;
49 class MCAsmInfo;
50 class MCInst;
51 struct MCSchedModel;
52 class Module;
53 class ScheduleDAG;
54 class ScheduleDAGMI;
55 class ScheduleHazardRecognizer;
56 class SDNode;
57 class SelectionDAG;
58 class RegScavenger;
59 class TargetRegisterClass;
60 class TargetRegisterInfo;
61 class TargetSchedModel;
62 class TargetSubtargetInfo;
63 
64 template <class T> class SmallVectorImpl;
65 
66 using ParamLoadedValue = std::pair<MachineOperand, DIExpression*>;
67 
71 
72  DestSourcePair(const MachineOperand &Dest, const MachineOperand &Src)
73  : Destination(&Dest), Source(&Src) {}
74 };
75 
76 /// Used to describe a register and immediate addition.
77 struct RegImmPair {
79  int64_t Imm;
80 
81  RegImmPair(Register Reg, int64_t Imm) : Reg(Reg), Imm(Imm) {}
82 };
83 
84 /// Used to describe addressing mode similar to ExtAddrMode in CodeGenPrepare.
85 /// It holds the register values, the scale value and the displacement.
86 struct ExtAddrMode {
89  int64_t Scale;
90  int64_t Displacement;
91 };
92 
93 //---------------------------------------------------------------------------
94 ///
95 /// TargetInstrInfo - Interface to description of machine instruction set
96 ///
97 class TargetInstrInfo : public MCInstrInfo {
98 public:
99  TargetInstrInfo(unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u,
100  unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u)
101  : CallFrameSetupOpcode(CFSetupOpcode),
102  CallFrameDestroyOpcode(CFDestroyOpcode), CatchRetOpcode(CatchRetOpcode),
103  ReturnOpcode(ReturnOpcode) {}
104  TargetInstrInfo(const TargetInstrInfo &) = delete;
105  TargetInstrInfo &operator=(const TargetInstrInfo &) = delete;
106  virtual ~TargetInstrInfo();
107 
108  static bool isGenericOpcode(unsigned Opc) {
109  return Opc <= TargetOpcode::GENERIC_OP_END;
110  }
111 
112  /// Given a machine instruction descriptor, returns the register
113  /// class constraint for OpNum, or NULL.
114  virtual
115  const TargetRegisterClass *getRegClass(const MCInstrDesc &MCID, unsigned OpNum,
116  const TargetRegisterInfo *TRI,
117  const MachineFunction &MF) const;
118 
119  /// Return true if the instruction is trivially rematerializable, meaning it
120  /// has no side effects and requires no operands that aren't always available.
121  /// This means the only allowed uses are constants and unallocatable physical
122  /// registers so that the instructions result is independent of the place
123  /// in the function.
125  AAResults *AA = nullptr) const {
126  return MI.getOpcode() == TargetOpcode::IMPLICIT_DEF ||
127  (MI.getDesc().isRematerializable() &&
129  isReallyTriviallyReMaterializableGeneric(MI, AA)));
130  }
131 
132  /// Given \p MO is a PhysReg use return if it can be ignored for the purpose
133  /// of instruction rematerialization.
134  virtual bool isIgnorableUse(const MachineOperand &MO) const {
135  return false;
136  }
137 
138 protected:
139  /// For instructions with opcodes for which the M_REMATERIALIZABLE flag is
140  /// set, this hook lets the target specify whether the instruction is actually
141  /// trivially rematerializable, taking into consideration its operands. This
142  /// predicate must return false if the instruction has any side effects other
143  /// than producing a value, or if it requres any address registers that are
144  /// not always available.
145  /// Requirements must be check as stated in isTriviallyReMaterializable() .
147  AAResults *AA) const {
148  return false;
149  }
150 
151  /// This method commutes the operands of the given machine instruction MI.
152  /// The operands to be commuted are specified by their indices OpIdx1 and
153  /// OpIdx2.
154  ///
155  /// If a target has any instructions that are commutable but require
156  /// converting to different instructions or making non-trivial changes
157  /// to commute them, this method can be overloaded to do that.
158  /// The default implementation simply swaps the commutable operands.
159  ///
160  /// If NewMI is false, MI is modified in place and returned; otherwise, a
161  /// new machine instruction is created and returned.
162  ///
163  /// Do not call this method for a non-commutable instruction.
164  /// Even though the instruction is commutable, the method may still
165  /// fail to commute the operands, null pointer is returned in such cases.
166  virtual MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
167  unsigned OpIdx1,
168  unsigned OpIdx2) const;
169 
170  /// Assigns the (CommutableOpIdx1, CommutableOpIdx2) pair of commutable
171  /// operand indices to (ResultIdx1, ResultIdx2).
172  /// One or both input values of the pair: (ResultIdx1, ResultIdx2) may be
173  /// predefined to some indices or be undefined (designated by the special
174  /// value 'CommuteAnyOperandIndex').
175  /// The predefined result indices cannot be re-defined.
176  /// The function returns true iff after the result pair redefinition
177  /// the fixed result pair is equal to or equivalent to the source pair of
178  /// indices: (CommutableOpIdx1, CommutableOpIdx2). It is assumed here that
179  /// the pairs (x,y) and (y,x) are equivalent.
180  static bool fixCommutedOpIndices(unsigned &ResultIdx1, unsigned &ResultIdx2,
181  unsigned CommutableOpIdx1,
182  unsigned CommutableOpIdx2);
183 
184 private:
185  /// For instructions with opcodes for which the M_REMATERIALIZABLE flag is
186  /// set and the target hook isReallyTriviallyReMaterializable returns false,
187  /// this function does target-independent tests to determine if the
188  /// instruction is really trivially rematerializable.
189  bool isReallyTriviallyReMaterializableGeneric(const MachineInstr &MI,
190  AAResults *AA) const;
191 
192 public:
193  /// These methods return the opcode of the frame setup/destroy instructions
194  /// if they exist (-1 otherwise). Some targets use pseudo instructions in
195  /// order to abstract away the difference between operating with a frame
196  /// pointer and operating without, through the use of these two instructions.
197  ///
198  unsigned getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; }
199  unsigned getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; }
200 
201  /// Returns true if the argument is a frame pseudo instruction.
202  bool isFrameInstr(const MachineInstr &I) const {
203  return I.getOpcode() == getCallFrameSetupOpcode() ||
204  I.getOpcode() == getCallFrameDestroyOpcode();
205  }
206 
207  /// Returns true if the argument is a frame setup pseudo instruction.
208  bool isFrameSetup(const MachineInstr &I) const {
209  return I.getOpcode() == getCallFrameSetupOpcode();
210  }
211 
212  /// Returns size of the frame associated with the given frame instruction.
213  /// For frame setup instruction this is frame that is set up space set up
214  /// after the instruction. For frame destroy instruction this is the frame
215  /// freed by the caller.
216  /// Note, in some cases a call frame (or a part of it) may be prepared prior
217  /// to the frame setup instruction. It occurs in the calls that involve
218  /// inalloca arguments. This function reports only the size of the frame part
219  /// that is set up between the frame setup and destroy pseudo instructions.
220  int64_t getFrameSize(const MachineInstr &I) const {
221  assert(isFrameInstr(I) && "Not a frame instruction");
222  assert(I.getOperand(0).getImm() >= 0);
223  return I.getOperand(0).getImm();
224  }
225 
226  /// Returns the total frame size, which is made up of the space set up inside
227  /// the pair of frame start-stop instructions and the space that is set up
228  /// prior to the pair.
229  int64_t getFrameTotalSize(const MachineInstr &I) const {
230  if (isFrameSetup(I)) {
231  assert(I.getOperand(1).getImm() >= 0 &&
232  "Frame size must not be negative");
233  return getFrameSize(I) + I.getOperand(1).getImm();
234  }
235  return getFrameSize(I);
236  }
237 
238  unsigned getCatchReturnOpcode() const { return CatchRetOpcode; }
239  unsigned getReturnOpcode() const { return ReturnOpcode; }
240 
241  /// Returns the actual stack pointer adjustment made by an instruction
242  /// as part of a call sequence. By default, only call frame setup/destroy
243  /// instructions adjust the stack, but targets may want to override this
244  /// to enable more fine-grained adjustment, or adjust by a different value.
245  virtual int getSPAdjust(const MachineInstr &MI) const;
246 
247  /// Return true if the instruction is a "coalescable" extension instruction.
248  /// That is, it's like a copy where it's legal for the source to overlap the
249  /// destination. e.g. X86::MOVSX64rr32. If this returns true, then it's
250  /// expected the pre-extension value is available as a subreg of the result
251  /// register. This also returns the sub-register index in SubIdx.
252  virtual bool isCoalescableExtInstr(const MachineInstr &MI, Register &SrcReg,
253  Register &DstReg, unsigned &SubIdx) const {
254  return false;
255  }
256 
257  /// If the specified machine instruction is a direct
258  /// load from a stack slot, return the virtual or physical register number of
259  /// the destination along with the FrameIndex of the loaded stack slot. If
260  /// not, return 0. This predicate must return 0 if the instruction has
261  /// any side effects other than loading from the stack slot.
262  virtual unsigned isLoadFromStackSlot(const MachineInstr &MI,
263  int &FrameIndex) const {
264  return 0;
265  }
266 
267  /// Optional extension of isLoadFromStackSlot that returns the number of
268  /// bytes loaded from the stack. This must be implemented if a backend
269  /// supports partial stack slot spills/loads to further disambiguate
270  /// what the load does.
271  virtual unsigned isLoadFromStackSlot(const MachineInstr &MI,
272  int &FrameIndex,
273  unsigned &MemBytes) const {
274  MemBytes = 0;
276  }
277 
278  /// Check for post-frame ptr elimination stack locations as well.
279  /// This uses a heuristic so it isn't reliable for correctness.
280  virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI,
281  int &FrameIndex) const {
282  return 0;
283  }
284 
285  /// If the specified machine instruction has a load from a stack slot,
286  /// return true along with the FrameIndices of the loaded stack slot and the
287  /// machine mem operands containing the reference.
288  /// If not, return false. Unlike isLoadFromStackSlot, this returns true for
289  /// any instructions that loads from the stack. This is just a hint, as some
290  /// cases may be missed.
291  virtual bool hasLoadFromStackSlot(
292  const MachineInstr &MI,
294 
295  /// If the specified machine instruction is a direct
296  /// store to a stack slot, return the virtual or physical register number of
297  /// the source reg along with the FrameIndex of the loaded stack slot. If
298  /// not, return 0. This predicate must return 0 if the instruction has
299  /// any side effects other than storing to the stack slot.
300  virtual unsigned isStoreToStackSlot(const MachineInstr &MI,
301  int &FrameIndex) const {
302  return 0;
303  }
304 
305  /// Optional extension of isStoreToStackSlot that returns the number of
306  /// bytes stored to the stack. This must be implemented if a backend
307  /// supports partial stack slot spills/loads to further disambiguate
308  /// what the store does.
309  virtual unsigned isStoreToStackSlot(const MachineInstr &MI,
310  int &FrameIndex,
311  unsigned &MemBytes) const {
312  MemBytes = 0;
314  }
315 
316  /// Check for post-frame ptr elimination stack locations as well.
317  /// This uses a heuristic, so it isn't reliable for correctness.
318  virtual unsigned isStoreToStackSlotPostFE(const MachineInstr &MI,
319  int &FrameIndex) const {
320  return 0;
321  }
322 
323  /// If the specified machine instruction has a store to a stack slot,
324  /// return true along with the FrameIndices of the loaded stack slot and the
325  /// machine mem operands containing the reference.
326  /// If not, return false. Unlike isStoreToStackSlot,
327  /// this returns true for any instructions that stores to the
328  /// stack. This is just a hint, as some cases may be missed.
329  virtual bool hasStoreToStackSlot(
330  const MachineInstr &MI,
332 
333  /// Return true if the specified machine instruction
334  /// is a copy of one stack slot to another and has no other effect.
335  /// Provide the identity of the two frame indices.
336  virtual bool isStackSlotCopy(const MachineInstr &MI, int &DestFrameIndex,
337  int &SrcFrameIndex) const {
338  return false;
339  }
340 
341  /// Compute the size in bytes and offset within a stack slot of a spilled
342  /// register or subregister.
343  ///
344  /// \param [out] Size in bytes of the spilled value.
345  /// \param [out] Offset in bytes within the stack slot.
346  /// \returns true if both Size and Offset are successfully computed.
347  ///
348  /// Not all subregisters have computable spill slots. For example,
349  /// subregisters registers may not be byte-sized, and a pair of discontiguous
350  /// subregisters has no single offset.
351  ///
352  /// Targets with nontrivial bigendian implementations may need to override
353  /// this, particularly to support spilled vector registers.
354  virtual bool getStackSlotRange(const TargetRegisterClass *RC, unsigned SubIdx,
355  unsigned &Size, unsigned &Offset,
356  const MachineFunction &MF) const;
357 
358  /// Return true if the given instruction is terminator that is unspillable,
359  /// according to isUnspillableTerminatorImpl.
361  return MI->isTerminator() && isUnspillableTerminatorImpl(MI);
362  }
363 
364  /// Returns the size in bytes of the specified MachineInstr, or ~0U
365  /// when this function is not implemented by a target.
366  virtual unsigned getInstSizeInBytes(const MachineInstr &MI) const {
367  return ~0U;
368  }
369 
370  /// Return true if the instruction is as cheap as a move instruction.
371  ///
372  /// Targets for different archs need to override this, and different
373  /// micro-architectures can also be finely tuned inside.
374  virtual bool isAsCheapAsAMove(const MachineInstr &MI) const {
375  return MI.isAsCheapAsAMove();
376  }
377 
378  /// Return true if the instruction should be sunk by MachineSink.
379  ///
380  /// MachineSink determines on its own whether the instruction is safe to sink;
381  /// this gives the target a hook to override the default behavior with regards
382  /// to which instructions should be sunk.
383  virtual bool shouldSink(const MachineInstr &MI) const { return true; }
384 
385  /// Re-issue the specified 'original' instruction at the
386  /// specific location targeting a new destination register.
387  /// The register in Orig->getOperand(0).getReg() will be substituted by
388  /// DestReg:SubIdx. Any existing subreg index is preserved or composed with
389  /// SubIdx.
390  virtual void reMaterialize(MachineBasicBlock &MBB,
392  unsigned SubIdx, const MachineInstr &Orig,
393  const TargetRegisterInfo &TRI) const;
394 
395  /// Clones instruction or the whole instruction bundle \p Orig and
396  /// insert into \p MBB before \p InsertBefore. The target may update operands
397  /// that are required to be unique.
398  ///
399  /// \p Orig must not return true for MachineInstr::isNotDuplicable().
401  MachineBasicBlock::iterator InsertBefore,
402  const MachineInstr &Orig) const;
403 
404  /// This method must be implemented by targets that
405  /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
406  /// may be able to convert a two-address instruction into one or more true
407  /// three-address instructions on demand. This allows the X86 target (for
408  /// example) to convert ADD and SHL instructions into LEA instructions if they
409  /// would require register copies due to two-addressness.
410  ///
411  /// This method returns a null pointer if the transformation cannot be
412  /// performed, otherwise it returns the last new instruction.
413  ///
415  LiveVariables *LV) const {
416  return nullptr;
417  }
418 
419  // This constant can be used as an input value of operand index passed to
420  // the method findCommutedOpIndices() to tell the method that the
421  // corresponding operand index is not pre-defined and that the method
422  // can pick any commutable operand.
423  static const unsigned CommuteAnyOperandIndex = ~0U;
424 
425  /// This method commutes the operands of the given machine instruction MI.
426  ///
427  /// The operands to be commuted are specified by their indices OpIdx1 and
428  /// OpIdx2. OpIdx1 and OpIdx2 arguments may be set to a special value
429  /// 'CommuteAnyOperandIndex', which means that the method is free to choose
430  /// any arbitrarily chosen commutable operand. If both arguments are set to
431  /// 'CommuteAnyOperandIndex' then the method looks for 2 different commutable
432  /// operands; then commutes them if such operands could be found.
433  ///
434  /// If NewMI is false, MI is modified in place and returned; otherwise, a
435  /// new machine instruction is created and returned.
436  ///
437  /// Do not call this method for a non-commutable instruction or
438  /// for non-commuable operands.
439  /// Even though the instruction is commutable, the method may still
440  /// fail to commute the operands, null pointer is returned in such cases.
441  MachineInstr *
442  commuteInstruction(MachineInstr &MI, bool NewMI = false,
443  unsigned OpIdx1 = CommuteAnyOperandIndex,
444  unsigned OpIdx2 = CommuteAnyOperandIndex) const;
445 
446  /// Returns true iff the routine could find two commutable operands in the
447  /// given machine instruction.
448  /// The 'SrcOpIdx1' and 'SrcOpIdx2' are INPUT and OUTPUT arguments.
449  /// If any of the INPUT values is set to the special value
450  /// 'CommuteAnyOperandIndex' then the method arbitrarily picks a commutable
451  /// operand, then returns its index in the corresponding argument.
452  /// If both of INPUT values are set to 'CommuteAnyOperandIndex' then method
453  /// looks for 2 commutable operands.
454  /// If INPUT values refer to some operands of MI, then the method simply
455  /// returns true if the corresponding operands are commutable and returns
456  /// false otherwise.
457  ///
458  /// For example, calling this method this way:
459  /// unsigned Op1 = 1, Op2 = CommuteAnyOperandIndex;
460  /// findCommutedOpIndices(MI, Op1, Op2);
461  /// can be interpreted as a query asking to find an operand that would be
462  /// commutable with the operand#1.
463  virtual bool findCommutedOpIndices(const MachineInstr &MI,
464  unsigned &SrcOpIdx1,
465  unsigned &SrcOpIdx2) const;
466 
467  /// Returns true if the target has a preference on the operands order of
468  /// the given machine instruction. And specify if \p Commute is required to
469  /// get the desired operands order.
470  virtual bool hasCommutePreference(MachineInstr &MI, bool &Commute) const {
471  return false;
472  }
473 
474  /// A pair composed of a register and a sub-register index.
475  /// Used to give some type checking when modeling Reg:SubReg.
476  struct RegSubRegPair {
478  unsigned SubReg;
479 
481  : Reg(Reg), SubReg(SubReg) {}
482 
483  bool operator==(const RegSubRegPair& P) const {
484  return Reg == P.Reg && SubReg == P.SubReg;
485  }
486  bool operator!=(const RegSubRegPair& P) const {
487  return !(*this == P);
488  }
489  };
490 
491  /// A pair composed of a pair of a register and a sub-register index,
492  /// and another sub-register index.
493  /// Used to give some type checking when modeling Reg:SubReg1, SubReg2.
495  unsigned SubIdx;
496 
498  unsigned SubIdx = 0)
500  };
501 
502  /// Build the equivalent inputs of a REG_SEQUENCE for the given \p MI
503  /// and \p DefIdx.
504  /// \p [out] InputRegs of the equivalent REG_SEQUENCE. Each element of
505  /// the list is modeled as <Reg:SubReg, SubIdx>. Operands with the undef
506  /// flag are not added to this list.
507  /// E.g., REG_SEQUENCE %1:sub1, sub0, %2, sub1 would produce
508  /// two elements:
509  /// - %1:sub1, sub0
510  /// - %2<:0>, sub1
511  ///
512  /// \returns true if it is possible to build such an input sequence
513  /// with the pair \p MI, \p DefIdx. False otherwise.
514  ///
515  /// \pre MI.isRegSequence() or MI.isRegSequenceLike().
516  ///
517  /// \note The generic implementation does not provide any support for
518  /// MI.isRegSequenceLike(). In other words, one has to override
519  /// getRegSequenceLikeInputs for target specific instructions.
520  bool
521  getRegSequenceInputs(const MachineInstr &MI, unsigned DefIdx,
522  SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const;
523 
524  /// Build the equivalent inputs of a EXTRACT_SUBREG for the given \p MI
525  /// and \p DefIdx.
526  /// \p [out] InputReg of the equivalent EXTRACT_SUBREG.
527  /// E.g., EXTRACT_SUBREG %1:sub1, sub0, sub1 would produce:
528  /// - %1:sub1, sub0
529  ///
530  /// \returns true if it is possible to build such an input sequence
531  /// with the pair \p MI, \p DefIdx and the operand has no undef flag set.
532  /// False otherwise.
533  ///
534  /// \pre MI.isExtractSubreg() or MI.isExtractSubregLike().
535  ///
536  /// \note The generic implementation does not provide any support for
537  /// MI.isExtractSubregLike(). In other words, one has to override
538  /// getExtractSubregLikeInputs for target specific instructions.
539  bool getExtractSubregInputs(const MachineInstr &MI, unsigned DefIdx,
540  RegSubRegPairAndIdx &InputReg) const;
541 
542  /// Build the equivalent inputs of a INSERT_SUBREG for the given \p MI
543  /// and \p DefIdx.
544  /// \p [out] BaseReg and \p [out] InsertedReg contain
545  /// the equivalent inputs of INSERT_SUBREG.
546  /// E.g., INSERT_SUBREG %0:sub0, %1:sub1, sub3 would produce:
547  /// - BaseReg: %0:sub0
548  /// - InsertedReg: %1:sub1, sub3
549  ///
550  /// \returns true if it is possible to build such an input sequence
551  /// with the pair \p MI, \p DefIdx and the operand has no undef flag set.
552  /// False otherwise.
553  ///
554  /// \pre MI.isInsertSubreg() or MI.isInsertSubregLike().
555  ///
556  /// \note The generic implementation does not provide any support for
557  /// MI.isInsertSubregLike(). In other words, one has to override
558  /// getInsertSubregLikeInputs for target specific instructions.
559  bool getInsertSubregInputs(const MachineInstr &MI, unsigned DefIdx,
560  RegSubRegPair &BaseReg,
561  RegSubRegPairAndIdx &InsertedReg) const;
562 
563  /// Return true if two machine instructions would produce identical values.
564  /// By default, this is only true when the two instructions
565  /// are deemed identical except for defs. If this function is called when the
566  /// IR is still in SSA form, the caller can pass the MachineRegisterInfo for
567  /// aggressive checks.
568  virtual bool produceSameValue(const MachineInstr &MI0,
569  const MachineInstr &MI1,
570  const MachineRegisterInfo *MRI = nullptr) const;
571 
572  /// \returns true if a branch from an instruction with opcode \p BranchOpc
573  /// bytes is capable of jumping to a position \p BrOffset bytes away.
574  virtual bool isBranchOffsetInRange(unsigned BranchOpc,
575  int64_t BrOffset) const {
576  llvm_unreachable("target did not implement");
577  }
578 
579  /// \returns The block that branch instruction \p MI jumps to.
581  llvm_unreachable("target did not implement");
582  }
583 
584  /// Insert an unconditional indirect branch at the end of \p MBB to \p
585  /// NewDestBB. \p BrOffset indicates the offset of \p NewDestBB relative to
586  /// the offset of the position to insert the new branch.
587  ///
588  /// \returns The number of bytes added to the block.
590  MachineBasicBlock &NewDestBB,
591  const DebugLoc &DL,
592  int64_t BrOffset = 0,
593  RegScavenger *RS = nullptr) const {
594  llvm_unreachable("target did not implement");
595  }
596 
597  /// Analyze the branching code at the end of MBB, returning
598  /// true if it cannot be understood (e.g. it's a switch dispatch or isn't
599  /// implemented for a target). Upon success, this returns false and returns
600  /// with the following information in various cases:
601  ///
602  /// 1. If this block ends with no branches (it just falls through to its succ)
603  /// just return false, leaving TBB/FBB null.
604  /// 2. If this block ends with only an unconditional branch, it sets TBB to be
605  /// the destination block.
606  /// 3. If this block ends with a conditional branch and it falls through to a
607  /// successor block, it sets TBB to be the branch destination block and a
608  /// list of operands that evaluate the condition. These operands can be
609  /// passed to other TargetInstrInfo methods to create new branches.
610  /// 4. If this block ends with a conditional branch followed by an
611  /// unconditional branch, it returns the 'true' destination in TBB, the
612  /// 'false' destination in FBB, and a list of operands that evaluate the
613  /// condition. These operands can be passed to other TargetInstrInfo
614  /// methods to create new branches.
615  ///
616  /// Note that removeBranch and insertBranch must be implemented to support
617  /// cases where this method returns success.
618  ///
619  /// If AllowModify is true, then this routine is allowed to modify the basic
620  /// block (e.g. delete instructions after the unconditional branch).
621  ///
622  /// The CFG information in MBB.Predecessors and MBB.Successors must be valid
623  /// before calling this function.
625  MachineBasicBlock *&FBB,
627  bool AllowModify = false) const {
628  return true;
629  }
630 
631  /// Represents a predicate at the MachineFunction level. The control flow a
632  /// MachineBranchPredicate represents is:
633  ///
634  /// Reg = LHS `Predicate` RHS == ConditionDef
635  /// if Reg then goto TrueDest else goto FalseDest
636  ///
639  PRED_EQ, // True if two values are equal
640  PRED_NE, // True if two values are not equal
641  PRED_INVALID // Sentinel value
642  };
643 
650 
651  /// SingleUseCondition is true if ConditionDef is dead except for the
652  /// branch(es) at the end of the basic block.
653  ///
654  bool SingleUseCondition = false;
655 
656  explicit MachineBranchPredicate() = default;
657  };
658 
659  /// Analyze the branching code at the end of MBB and parse it into the
660  /// MachineBranchPredicate structure if possible. Returns false on success
661  /// and true on failure.
662  ///
663  /// If AllowModify is true, then this routine is allowed to modify the basic
664  /// block (e.g. delete instructions after the unconditional branch).
665  ///
668  bool AllowModify = false) const {
669  return true;
670  }
671 
672  /// Remove the branching code at the end of the specific MBB.
673  /// This is only invoked in cases where analyzeBranch returns success. It
674  /// returns the number of instructions that were removed.
675  /// If \p BytesRemoved is non-null, report the change in code size from the
676  /// removed instructions.
677  virtual unsigned removeBranch(MachineBasicBlock &MBB,
678  int *BytesRemoved = nullptr) const {
679  llvm_unreachable("Target didn't implement TargetInstrInfo::removeBranch!");
680  }
681 
682  /// Insert branch code into the end of the specified MachineBasicBlock. The
683  /// operands to this method are the same as those returned by analyzeBranch.
684  /// This is only invoked in cases where analyzeBranch returns success. It
685  /// returns the number of instructions inserted. If \p BytesAdded is non-null,
686  /// report the change in code size from the added instructions.
687  ///
688  /// It is also invoked by tail merging to add unconditional branches in
689  /// cases where analyzeBranch doesn't apply because there was no original
690  /// branch to analyze. At least this much must be implemented, else tail
691  /// merging needs to be disabled.
692  ///
693  /// The CFG information in MBB.Predecessors and MBB.Successors must be valid
694  /// before calling this function.
696  MachineBasicBlock *FBB,
698  const DebugLoc &DL,
699  int *BytesAdded = nullptr) const {
700  llvm_unreachable("Target didn't implement TargetInstrInfo::insertBranch!");
701  }
702 
704  MachineBasicBlock *DestBB,
705  const DebugLoc &DL,
706  int *BytesAdded = nullptr) const {
707  return insertBranch(MBB, DestBB, nullptr, ArrayRef<MachineOperand>(), DL,
708  BytesAdded);
709  }
710 
711  /// Object returned by analyzeLoopForPipelining. Allows software pipelining
712  /// implementations to query attributes of the loop being pipelined and to
713  /// apply target-specific updates to the loop once pipelining is complete.
715  public:
716  virtual ~PipelinerLoopInfo();
717  /// Return true if the given instruction should not be pipelined and should
718  /// be ignored. An example could be a loop comparison, or induction variable
719  /// update with no users being pipelined.
720  virtual bool shouldIgnoreForPipelining(const MachineInstr *MI) const = 0;
721 
722  /// Create a condition to determine if the trip count of the loop is greater
723  /// than TC.
724  ///
725  /// If the trip count is statically known to be greater than TC, return
726  /// true. If the trip count is statically known to be not greater than TC,
727  /// return false. Otherwise return nullopt and fill out Cond with the test
728  /// condition.
729  virtual Optional<bool>
732 
733  /// Modify the loop such that the trip count is
734  /// OriginalTC + TripCountAdjust.
735  virtual void adjustTripCount(int TripCountAdjust) = 0;
736 
737  /// Called when the loop's preheader has been modified to NewPreheader.
738  virtual void setPreheader(MachineBasicBlock *NewPreheader) = 0;
739 
740  /// Called when the loop is being removed. Any instructions in the preheader
741  /// should be removed.
742  ///
743  /// Once this function is called, no other functions on this object are
744  /// valid; the loop has been removed.
745  virtual void disposed() = 0;
746  };
747 
748  /// Analyze loop L, which must be a single-basic-block loop, and if the
749  /// conditions can be understood enough produce a PipelinerLoopInfo object.
750  virtual std::unique_ptr<PipelinerLoopInfo>
752  return nullptr;
753  }
754 
755  /// Analyze the loop code, return true if it cannot be understood. Upon
756  /// success, this function returns false and returns information about the
757  /// induction variable and compare instruction used at the end.
758  virtual bool analyzeLoop(MachineLoop &L, MachineInstr *&IndVarInst,
759  MachineInstr *&CmpInst) const {
760  return true;
761  }
762 
763  /// Generate code to reduce the loop iteration by one and check if the loop
764  /// is finished. Return the value/register of the new loop count. We need
765  /// this function when peeling off one or more iterations of a loop. This
766  /// function assumes the nth iteration is peeled first.
768  MachineBasicBlock &PreHeader,
769  MachineInstr *IndVar, MachineInstr &Cmp,
772  unsigned Iter, unsigned MaxIter) const {
773  llvm_unreachable("Target didn't implement ReduceLoopCount");
774  }
775 
776  /// Delete the instruction OldInst and everything after it, replacing it with
777  /// an unconditional branch to NewDest. This is used by the tail merging pass.
779  MachineBasicBlock *NewDest) const;
780 
781  /// Return true if it's legal to split the given basic
782  /// block at the specified instruction (i.e. instruction would be the start
783  /// of a new basic block).
786  return true;
787  }
788 
789  /// Return true if it's profitable to predicate
790  /// instructions with accumulated instruction latency of "NumCycles"
791  /// of the specified basic block, where the probability of the instructions
792  /// being executed is given by Probability, and Confidence is a measure
793  /// of our confidence that it will be properly predicted.
794  virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
795  unsigned ExtraPredCycles,
796  BranchProbability Probability) const {
797  return false;
798  }
799 
800  /// Second variant of isProfitableToIfCvt. This one
801  /// checks for the case where two basic blocks from true and false path
802  /// of a if-then-else (diamond) are predicated on mutually exclusive
803  /// predicates, where the probability of the true path being taken is given
804  /// by Probability, and Confidence is a measure of our confidence that it
805  /// will be properly predicted.
806  virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumTCycles,
807  unsigned ExtraTCycles,
808  MachineBasicBlock &FMBB, unsigned NumFCycles,
809  unsigned ExtraFCycles,
810  BranchProbability Probability) const {
811  return false;
812  }
813 
814  /// Return true if it's profitable for if-converter to duplicate instructions
815  /// of specified accumulated instruction latencies in the specified MBB to
816  /// enable if-conversion.
817  /// The probability of the instructions being executed is given by
818  /// Probability, and Confidence is a measure of our confidence that it
819  /// will be properly predicted.
821  unsigned NumCycles,
822  BranchProbability Probability) const {
823  return false;
824  }
825 
826  /// Return the increase in code size needed to predicate a contiguous run of
827  /// NumInsts instructions.
829  unsigned NumInsts) const {
830  return 0;
831  }
832 
833  /// Return an estimate for the code size reduction (in bytes) which will be
834  /// caused by removing the given branch instruction during if-conversion.
835  virtual unsigned predictBranchSizeForIfCvt(MachineInstr &MI) const {
836  return getInstSizeInBytes(MI);
837  }
838 
839  /// Return true if it's profitable to unpredicate
840  /// one side of a 'diamond', i.e. two sides of if-else predicated on mutually
841  /// exclusive predicates.
842  /// e.g.
843  /// subeq r0, r1, #1
844  /// addne r0, r1, #1
845  /// =>
846  /// sub r0, r1, #1
847  /// addne r0, r1, #1
848  ///
849  /// This may be profitable is conditional instructions are always executed.
851  MachineBasicBlock &FMBB) const {
852  return false;
853  }
854 
855  /// Return true if it is possible to insert a select
856  /// instruction that chooses between TrueReg and FalseReg based on the
857  /// condition code in Cond.
858  ///
859  /// When successful, also return the latency in cycles from TrueReg,
860  /// FalseReg, and Cond to the destination register. In most cases, a select
861  /// instruction will be 1 cycle, so CondCycles = TrueCycles = FalseCycles = 1
862  ///
863  /// Some x86 implementations have 2-cycle cmov instructions.
864  ///
865  /// @param MBB Block where select instruction would be inserted.
866  /// @param Cond Condition returned by analyzeBranch.
867  /// @param DstReg Virtual dest register that the result should write to.
868  /// @param TrueReg Virtual register to select when Cond is true.
869  /// @param FalseReg Virtual register to select when Cond is false.
870  /// @param CondCycles Latency from Cond+Branch to select output.
871  /// @param TrueCycles Latency from TrueReg to select output.
872  /// @param FalseCycles Latency from FalseReg to select output.
873  virtual bool canInsertSelect(const MachineBasicBlock &MBB,
875  Register TrueReg, Register FalseReg,
876  int &CondCycles, int &TrueCycles,
877  int &FalseCycles) const {
878  return false;
879  }
880 
881  /// Insert a select instruction into MBB before I that will copy TrueReg to
882  /// DstReg when Cond is true, and FalseReg to DstReg when Cond is false.
883  ///
884  /// This function can only be called after canInsertSelect() returned true.
885  /// The condition in Cond comes from analyzeBranch, and it can be assumed
886  /// that the same flags or registers required by Cond are available at the
887  /// insertion point.
888  ///
889  /// @param MBB Block where select instruction should be inserted.
890  /// @param I Insertion point.
891  /// @param DL Source location for debugging.
892  /// @param DstReg Virtual register to be defined by select instruction.
893  /// @param Cond Condition as computed by analyzeBranch.
894  /// @param TrueReg Virtual register to copy when Cond is true.
895  /// @param FalseReg Virtual register to copy when Cons is false.
899  Register TrueReg, Register FalseReg) const {
900  llvm_unreachable("Target didn't implement TargetInstrInfo::insertSelect!");
901  }
902 
903  /// Analyze the given select instruction, returning true if
904  /// it cannot be understood. It is assumed that MI->isSelect() is true.
905  ///
906  /// When successful, return the controlling condition and the operands that
907  /// determine the true and false result values.
908  ///
909  /// Result = SELECT Cond, TrueOp, FalseOp
910  ///
911  /// Some targets can optimize select instructions, for example by predicating
912  /// the instruction defining one of the operands. Such targets should set
913  /// Optimizable.
914  ///
915  /// @param MI Select instruction to analyze.
916  /// @param Cond Condition controlling the select.
917  /// @param TrueOp Operand number of the value selected when Cond is true.
918  /// @param FalseOp Operand number of the value selected when Cond is false.
919  /// @param Optimizable Returned as true if MI is optimizable.
920  /// @returns False on success.
921  virtual bool analyzeSelect(const MachineInstr &MI,
923  unsigned &TrueOp, unsigned &FalseOp,
924  bool &Optimizable) const {
925  assert(MI.getDesc().isSelect() && "MI must be a select instruction");
926  return true;
927  }
928 
929  /// Given a select instruction that was understood by
930  /// analyzeSelect and returned Optimizable = true, attempt to optimize MI by
931  /// merging it with one of its operands. Returns NULL on failure.
932  ///
933  /// When successful, returns the new select instruction. The client is
934  /// responsible for deleting MI.
935  ///
936  /// If both sides of the select can be optimized, PreferFalse is used to pick
937  /// a side.
938  ///
939  /// @param MI Optimizable select instruction.
940  /// @param NewMIs Set that record all MIs in the basic block up to \p
941  /// MI. Has to be updated with any newly created MI or deleted ones.
942  /// @param PreferFalse Try to optimize FalseOp instead of TrueOp.
943  /// @returns Optimized instruction or NULL.
946  bool PreferFalse = false) const {
947  // This function must be implemented if Optimizable is ever set.
948  llvm_unreachable("Target must implement TargetInstrInfo::optimizeSelect!");
949  }
950 
951  /// Emit instructions to copy a pair of physical registers.
952  ///
953  /// This function should support copies within any legal register class as
954  /// well as any cross-class copies created during instruction selection.
955  ///
956  /// The source and destination registers may overlap, which may require a
957  /// careful implementation when multiple copy instructions are required for
958  /// large registers. See for example the ARM target.
961  MCRegister DestReg, MCRegister SrcReg,
962  bool KillSrc) const {
963  llvm_unreachable("Target didn't implement TargetInstrInfo::copyPhysReg!");
964  }
965 
966  /// Allow targets to tell MachineVerifier whether a specific register
967  /// MachineOperand can be used as part of PC-relative addressing.
968  /// PC-relative addressing modes in many CISC architectures contain
969  /// (non-PC) registers as offsets or scaling values, which inherently
970  /// tags the corresponding MachineOperand with OPERAND_PCREL.
971  ///
972  /// @param MO The MachineOperand in question. MO.isReg() should always
973  /// be true.
974  /// @return Whether this operand is allowed to be used PC-relatively.
975  virtual bool isPCRelRegisterOperandLegal(const MachineOperand &MO) const {
976  return false;
977  }
978 
979 protected:
980  /// Target-dependent implementation for IsCopyInstr.
981  /// If the specific machine instruction is a instruction that moves/copies
982  /// value from one register to another register return destination and source
983  /// registers as machine operands.
986  return None;
987  }
988 
989  /// Return true if the given terminator MI is not expected to spill. This
990  /// sets the live interval as not spillable and adjusts phi node lowering to
991  /// not introduce copies after the terminator. Use with care, these are
992  /// currently used for hardware loop intrinsics in very controlled situations,
993  /// created prior to registry allocation in loops that only have single phi
994  /// users for the terminators value. They may run out of registers if not used
995  /// carefully.
996  virtual bool isUnspillableTerminatorImpl(const MachineInstr *MI) const {
997  return false;
998  }
999 
1000 public:
1001  /// If the specific machine instruction is a instruction that moves/copies
1002  /// value from one register to another register return destination and source
1003  /// registers as machine operands.
1004  /// For COPY-instruction the method naturally returns destination and source
1005  /// registers as machine operands, for all other instructions the method calls
1006  /// target-dependent implementation.
1008  if (MI.isCopy()) {
1009  return DestSourcePair{MI.getOperand(0), MI.getOperand(1)};
1010  }
1011  return isCopyInstrImpl(MI);
1012  }
1013 
1014  /// If the specific machine instruction is an instruction that adds an
1015  /// immediate value and a physical register, and stores the result in
1016  /// the given physical register \c Reg, return a pair of the source
1017  /// register and the offset which has been added.
1019  Register Reg) const {
1020  return None;
1021  }
1022 
1023  /// Returns true if MI is an instruction that defines Reg to have a constant
1024  /// value and the value is recorded in ImmVal. The ImmVal is a result that
1025  /// should be interpreted as modulo size of Reg.
1027  const Register Reg,
1028  int64_t &ImmVal) const {
1029  return false;
1030  }
1031 
1032  /// Store the specified register of the given register class to the specified
1033  /// stack frame index. The store instruction is to be added to the given
1034  /// machine basic block before the specified machine instruction. If isKill
1035  /// is true, the register operand is the last use and must be marked kill.
1038  Register SrcReg, bool isKill, int FrameIndex,
1039  const TargetRegisterClass *RC,
1040  const TargetRegisterInfo *TRI) const {
1041  llvm_unreachable("Target didn't implement "
1042  "TargetInstrInfo::storeRegToStackSlot!");
1043  }
1044 
1045  /// Load the specified register of the given register class from the specified
1046  /// stack frame index. The load instruction is to be added to the given
1047  /// machine basic block before the specified machine instruction.
1050  Register DestReg, int FrameIndex,
1051  const TargetRegisterClass *RC,
1052  const TargetRegisterInfo *TRI) const {
1053  llvm_unreachable("Target didn't implement "
1054  "TargetInstrInfo::loadRegFromStackSlot!");
1055  }
1056 
1057  /// This function is called for all pseudo instructions
1058  /// that remain after register allocation. Many pseudo instructions are
1059  /// created to help register allocation. This is the place to convert them
1060  /// into real instructions. The target can edit MI in place, or it can insert
1061  /// new instructions and erase MI. The function should return true if
1062  /// anything was changed.
1063  virtual bool expandPostRAPseudo(MachineInstr &MI) const { return false; }
1064 
1065  /// Check whether the target can fold a load that feeds a subreg operand
1066  /// (or a subreg operand that feeds a store).
1067  /// For example, X86 may want to return true if it can fold
1068  /// movl (%esp), %eax
1069  /// subb, %al, ...
1070  /// Into:
1071  /// subb (%esp), ...
1072  ///
1073  /// Ideally, we'd like the target implementation of foldMemoryOperand() to
1074  /// reject subregs - but since this behavior used to be enforced in the
1075  /// target-independent code, moving this responsibility to the targets
1076  /// has the potential of causing nasty silent breakage in out-of-tree targets.
1077  virtual bool isSubregFoldable() const { return false; }
1078 
1079  /// For a patchpoint, stackmap, or statepoint intrinsic, return the range of
1080  /// operands which can't be folded into stack references. Operands outside
1081  /// of the range are most likely foldable but it is not guaranteed.
1082  /// These instructions are unique in that stack references for some operands
1083  /// have the same execution cost (e.g. none) as the unfolded register forms.
1084  /// The ranged return is guaranteed to include all operands which can't be
1085  /// folded at zero cost.
1086  virtual std::pair<unsigned, unsigned>
1088 
1089  /// Attempt to fold a load or store of the specified stack
1090  /// slot into the specified machine instruction for the specified operand(s).
1091  /// If this is possible, a new instruction is returned with the specified
1092  /// operand folded, otherwise NULL is returned.
1093  /// The new instruction is inserted before MI, and the client is responsible
1094  /// for removing the old instruction.
1095  /// If VRM is passed, the assigned physregs can be inspected by target to
1096  /// decide on using an opcode (note that those assignments can still change).
1098  int FI,
1099  LiveIntervals *LIS = nullptr,
1100  VirtRegMap *VRM = nullptr) const;
1101 
1102  /// Same as the previous version except it allows folding of any load and
1103  /// store from / to any address, not just from a specific stack slot.
1105  MachineInstr &LoadMI,
1106  LiveIntervals *LIS = nullptr) const;
1107 
1108  /// Return true when there is potentially a faster code sequence
1109  /// for an instruction chain ending in \p Root. All potential patterns are
1110  /// returned in the \p Pattern vector. Pattern should be sorted in priority
1111  /// order since the pattern evaluator stops checking as soon as it finds a
1112  /// faster sequence.
1113  /// \param Root - Instruction that could be combined with one of its operands
1114  /// \param Patterns - Vector of possible combination patterns
1115  virtual bool
1118  bool DoRegPressureReduce) const;
1119 
1120  /// Return true if target supports reassociation of instructions in machine
1121  /// combiner pass to reduce register pressure for a given BB.
1122  virtual bool
1124  RegisterClassInfo *RegClassInfo) const {
1125  return false;
1126  }
1127 
1128  /// Fix up the placeholder we may add in genAlternativeCodeSequence().
1129  virtual void
1131  SmallVectorImpl<MachineInstr *> &InsInstrs) const {}
1132 
1133  /// Return true when a code sequence can improve throughput. It
1134  /// should be called only for instructions in loops.
1135  /// \param Pattern - combiner pattern
1137 
1138  /// Return true if the input \P Inst is part of a chain of dependent ops
1139  /// that are suitable for reassociation, otherwise return false.
1140  /// If the instruction's operands must be commuted to have a previous
1141  /// instruction of the same type define the first source operand, \P Commuted
1142  /// will be set to true.
1143  bool isReassociationCandidate(const MachineInstr &Inst, bool &Commuted) const;
1144 
1145  /// Return true when \P Inst is both associative and commutative.
1146  virtual bool isAssociativeAndCommutative(const MachineInstr &Inst) const {
1147  return false;
1148  }
1149 
1150  /// Return true when \P Inst has reassociable operands in the same \P MBB.
1151  virtual bool hasReassociableOperands(const MachineInstr &Inst,
1152  const MachineBasicBlock *MBB) const;
1153 
1154  /// Return true when \P Inst has reassociable sibling.
1155  bool hasReassociableSibling(const MachineInstr &Inst, bool &Commuted) const;
1156 
1157  /// When getMachineCombinerPatterns() finds patterns, this function generates
1158  /// the instructions that could replace the original code sequence. The client
1159  /// has to decide whether the actual replacement is beneficial or not.
1160  /// \param Root - Instruction that could be combined with one of its operands
1161  /// \param Pattern - Combination pattern for Root
1162  /// \param InsInstrs - Vector of new instructions that implement P
1163  /// \param DelInstrs - Old instructions, including Root, that could be
1164  /// replaced by InsInstr
1165  /// \param InstIdxForVirtReg - map of virtual register to instruction in
1166  /// InsInstr that defines it
1167  virtual void genAlternativeCodeSequence(
1171  DenseMap<unsigned, unsigned> &InstIdxForVirtReg) const;
1172 
1173  /// Attempt to reassociate \P Root and \P Prev according to \P Pattern to
1174  /// reduce critical path length.
1175  void reassociateOps(MachineInstr &Root, MachineInstr &Prev,
1179  DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const;
1180 
1181  /// The limit on resource length extension we accept in MachineCombiner Pass.
1182  virtual int getExtendResourceLenLimit() const { return 0; }
1183 
1184  /// This is an architecture-specific helper function of reassociateOps.
1185  /// Set special operand attributes for new instructions after reassociation.
1186  virtual void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2,
1187  MachineInstr &NewMI1,
1188  MachineInstr &NewMI2) const {}
1189 
1190  virtual void setSpecialOperandAttr(MachineInstr &MI, uint16_t Flags) const {}
1191 
1192  /// Return true when a target supports MachineCombiner.
1193  virtual bool useMachineCombiner() const { return false; }
1194 
1195  /// Return true if the given SDNode can be copied during scheduling
1196  /// even if it has glue.
1197  virtual bool canCopyGluedNodeDuringSchedule(SDNode *N) const { return false; }
1198 
1199 protected:
1200  /// Target-dependent implementation for foldMemoryOperand.
1201  /// Target-independent code in foldMemoryOperand will
1202  /// take care of adding a MachineMemOperand to the newly created instruction.
1203  /// The instruction and any auxiliary instructions necessary will be inserted
1204  /// at InsertPt.
1205  virtual MachineInstr *
1207  ArrayRef<unsigned> Ops,
1209  LiveIntervals *LIS = nullptr,
1210  VirtRegMap *VRM = nullptr) const {
1211  return nullptr;
1212  }
1213 
1214  /// Target-dependent implementation for foldMemoryOperand.
1215  /// Target-independent code in foldMemoryOperand will
1216  /// take care of adding a MachineMemOperand to the newly created instruction.
1217  /// The instruction and any auxiliary instructions necessary will be inserted
1218  /// at InsertPt.
1221  MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI,
1222  LiveIntervals *LIS = nullptr) const {
1223  return nullptr;
1224  }
1225 
1226  /// Target-dependent implementation of getRegSequenceInputs.
1227  ///
1228  /// \returns true if it is possible to build the equivalent
1229  /// REG_SEQUENCE inputs with the pair \p MI, \p DefIdx. False otherwise.
1230  ///
1231  /// \pre MI.isRegSequenceLike().
1232  ///
1233  /// \see TargetInstrInfo::getRegSequenceInputs.
1235  const MachineInstr &MI, unsigned DefIdx,
1236  SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const {
1237  return false;
1238  }
1239 
1240  /// Target-dependent implementation of getExtractSubregInputs.
1241  ///
1242  /// \returns true if it is possible to build the equivalent
1243  /// EXTRACT_SUBREG inputs with the pair \p MI, \p DefIdx. False otherwise.
1244  ///
1245  /// \pre MI.isExtractSubregLike().
1246  ///
1247  /// \see TargetInstrInfo::getExtractSubregInputs.
1249  unsigned DefIdx,
1250  RegSubRegPairAndIdx &InputReg) const {
1251  return false;
1252  }
1253 
1254  /// Target-dependent implementation of getInsertSubregInputs.
1255  ///
1256  /// \returns true if it is possible to build the equivalent
1257  /// INSERT_SUBREG inputs with the pair \p MI, \p DefIdx. False otherwise.
1258  ///
1259  /// \pre MI.isInsertSubregLike().
1260  ///
1261  /// \see TargetInstrInfo::getInsertSubregInputs.
1262  virtual bool
1263  getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
1264  RegSubRegPair &BaseReg,
1265  RegSubRegPairAndIdx &InsertedReg) const {
1266  return false;
1267  }
1268 
1269 public:
1270  /// getAddressSpaceForPseudoSourceKind - Given the kind of memory
1271  /// (e.g. stack) the target returns the corresponding address space.
1272  virtual unsigned
1274  return 0;
1275  }
1276 
1277  /// unfoldMemoryOperand - Separate a single instruction which folded a load or
1278  /// a store or a load and a store into two or more instruction. If this is
1279  /// possible, returns true as well as the new instructions by reference.
1280  virtual bool
1282  bool UnfoldLoad, bool UnfoldStore,
1283  SmallVectorImpl<MachineInstr *> &NewMIs) const {
1284  return false;
1285  }
1286 
1288  SmallVectorImpl<SDNode *> &NewNodes) const {
1289  return false;
1290  }
1291 
1292  /// Returns the opcode of the would be new
1293  /// instruction after load / store are unfolded from an instruction of the
1294  /// specified opcode. It returns zero if the specified unfolding is not
1295  /// possible. If LoadRegIndex is non-null, it is filled in with the operand
1296  /// index of the operand which will hold the register holding the loaded
1297  /// value.
1298  virtual unsigned
1299  getOpcodeAfterMemoryUnfold(unsigned Opc, bool UnfoldLoad, bool UnfoldStore,
1300  unsigned *LoadRegIndex = nullptr) const {
1301  return 0;
1302  }
1303 
1304  /// This is used by the pre-regalloc scheduler to determine if two loads are
1305  /// loading from the same base address. It should only return true if the base
1306  /// pointers are the same and the only differences between the two addresses
1307  /// are the offset. It also returns the offsets by reference.
1308  virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
1309  int64_t &Offset1,
1310  int64_t &Offset2) const {
1311  return false;
1312  }
1313 
1314  /// This is a used by the pre-regalloc scheduler to determine (in conjunction
1315  /// with areLoadsFromSameBasePtr) if two loads should be scheduled together.
1316  /// On some targets if two loads are loading from
1317  /// addresses in the same cache line, it's better if they are scheduled
1318  /// together. This function takes two integers that represent the load offsets
1319  /// from the common base address. It returns true if it decides it's desirable
1320  /// to schedule the two loads together. "NumLoads" is the number of loads that
1321  /// have already been scheduled after Load1.
1322  virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
1323  int64_t Offset1, int64_t Offset2,
1324  unsigned NumLoads) const {
1325  return false;
1326  }
1327 
1328  /// Get the base operand and byte offset of an instruction that reads/writes
1329  /// memory. This is a convenience function for callers that are only prepared
1330  /// to handle a single base operand.
1332  const MachineOperand *&BaseOp, int64_t &Offset,
1333  bool &OffsetIsScalable,
1334  const TargetRegisterInfo *TRI) const;
1335 
1336  /// Get zero or more base operands and the byte offset of an instruction that
1337  /// reads/writes memory. Note that there may be zero base operands if the
1338  /// instruction accesses a constant address.
1339  /// It returns false if MI does not read/write memory.
1340  /// It returns false if base operands and offset could not be determined.
1341  /// It is not guaranteed to always recognize base operands and offsets in all
1342  /// cases.
1345  int64_t &Offset, bool &OffsetIsScalable, unsigned &Width,
1346  const TargetRegisterInfo *TRI) const {
1347  return false;
1348  }
1349 
1350  /// Return true if the instruction contains a base register and offset. If
1351  /// true, the function also sets the operand position in the instruction
1352  /// for the base register and offset.
1354  unsigned &BasePos,
1355  unsigned &OffsetPos) const {
1356  return false;
1357  }
1358 
1359  /// Target dependent implementation to get the values constituting the address
1360  /// MachineInstr that is accessing memory. These values are returned as a
1361  /// struct ExtAddrMode which contains all relevant information to make up the
1362  /// address.
1363  virtual Optional<ExtAddrMode>
1365  const TargetRegisterInfo *TRI) const {
1366  return None;
1367  }
1368 
1369  /// Returns true if MI's Def is NullValueReg, and the MI
1370  /// does not change the Zero value. i.e. cases such as rax = shr rax, X where
1371  /// NullValueReg = rax. Note that if the NullValueReg is non-zero, this
1372  /// function can return true even if becomes zero. Specifically cases such as
1373  /// NullValueReg = shl NullValueReg, 63.
1375  const Register NullValueReg,
1376  const TargetRegisterInfo *TRI) const {
1377  return false;
1378  }
1379 
1380  /// If the instruction is an increment of a constant value, return the amount.
1381  virtual bool getIncrementValue(const MachineInstr &MI, int &Value) const {
1382  return false;
1383  }
1384 
1385  /// Returns true if the two given memory operations should be scheduled
1386  /// adjacent. Note that you have to add:
1387  /// DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
1388  /// or
1389  /// DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
1390  /// to TargetPassConfig::createMachineScheduler() to have an effect.
1391  ///
1392  /// \p BaseOps1 and \p BaseOps2 are memory operands of two memory operations.
1393  /// \p NumLoads is the number of loads that will be in the cluster if this
1394  /// hook returns true.
1395  /// \p NumBytes is the number of bytes that will be loaded from all the
1396  /// clustered loads if this hook returns true.
1399  unsigned NumLoads, unsigned NumBytes) const {
1400  llvm_unreachable("target did not implement shouldClusterMemOps()");
1401  }
1402 
1403  /// Reverses the branch condition of the specified condition list,
1404  /// returning false on success and true if it cannot be reversed.
1405  virtual bool
1407  return true;
1408  }
1409 
1410  /// Insert a noop into the instruction stream at the specified point.
1411  virtual void insertNoop(MachineBasicBlock &MBB,
1413 
1414  /// Insert noops into the instruction stream at the specified point.
1415  virtual void insertNoops(MachineBasicBlock &MBB,
1417  unsigned Quantity) const;
1418 
1419  /// Return the noop instruction to use for a noop.
1420  virtual MCInst getNop() const;
1421 
1422  /// Return true for post-incremented instructions.
1423  virtual bool isPostIncrement(const MachineInstr &MI) const { return false; }
1424 
1425  /// Returns true if the instruction is already predicated.
1426  virtual bool isPredicated(const MachineInstr &MI) const { return false; }
1427 
1428  // Returns a MIRPrinter comment for this machine operand.
1429  virtual std::string
1431  unsigned OpIdx, const TargetRegisterInfo *TRI) const;
1432 
1433  /// Returns true if the instruction is a
1434  /// terminator instruction that has not been predicated.
1435  bool isUnpredicatedTerminator(const MachineInstr &MI) const;
1436 
1437  /// Returns true if MI is an unconditional tail call.
1438  virtual bool isUnconditionalTailCall(const MachineInstr &MI) const {
1439  return false;
1440  }
1441 
1442  /// Returns true if the tail call can be made conditional on BranchCond.
1444  const MachineInstr &TailCall) const {
1445  return false;
1446  }
1447 
1448  /// Replace the conditional branch in MBB with a conditional tail call.
1451  const MachineInstr &TailCall) const {
1452  llvm_unreachable("Target didn't implement replaceBranchWithTailCall!");
1453  }
1454 
1455  /// Convert the instruction into a predicated instruction.
1456  /// It returns true if the operation was successful.
1457  virtual bool PredicateInstruction(MachineInstr &MI,
1458  ArrayRef<MachineOperand> Pred) const;
1459 
1460  /// Returns true if the first specified predicate
1461  /// subsumes the second, e.g. GE subsumes GT.
1463  ArrayRef<MachineOperand> Pred2) const {
1464  return false;
1465  }
1466 
1467  /// If the specified instruction defines any predicate
1468  /// or condition code register(s) used for predication, returns true as well
1469  /// as the definition predicate(s) by reference.
1470  /// SkipDead should be set to false at any point that dead
1471  /// predicate instructions should be considered as being defined.
1472  /// A dead predicate instruction is one that is guaranteed to be removed
1473  /// after a call to PredicateInstruction.
1475  std::vector<MachineOperand> &Pred,
1476  bool SkipDead) const {
1477  return false;
1478  }
1479 
1480  /// Return true if the specified instruction can be predicated.
1481  /// By default, this returns true for every instruction with a
1482  /// PredicateOperand.
1483  virtual bool isPredicable(const MachineInstr &MI) const {
1484  return MI.getDesc().isPredicable();
1485  }
1486 
1487  /// Return true if it's safe to move a machine
1488  /// instruction that defines the specified register class.
1489  virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
1490  return true;
1491  }
1492 
1493  /// Test if the given instruction should be considered a scheduling boundary.
1494  /// This primarily includes labels and terminators.
1495  virtual bool isSchedulingBoundary(const MachineInstr &MI,
1496  const MachineBasicBlock *MBB,
1497  const MachineFunction &MF) const;
1498 
1499  /// Measure the specified inline asm to determine an approximation of its
1500  /// length.
1501  virtual unsigned getInlineAsmLength(
1502  const char *Str, const MCAsmInfo &MAI,
1503  const TargetSubtargetInfo *STI = nullptr) const;
1504 
1505  /// Allocate and return a hazard recognizer to use for this target when
1506  /// scheduling the machine instructions before register allocation.
1507  virtual ScheduleHazardRecognizer *
1509  const ScheduleDAG *DAG) const;
1510 
1511  /// Allocate and return a hazard recognizer to use for this target when
1512  /// scheduling the machine instructions before register allocation.
1513  virtual ScheduleHazardRecognizer *
1515  const ScheduleDAGMI *DAG) const;
1516 
1517  /// Allocate and return a hazard recognizer to use for this target when
1518  /// scheduling the machine instructions after register allocation.
1519  virtual ScheduleHazardRecognizer *
1521  const ScheduleDAG *DAG) const;
1522 
1523  /// Allocate and return a hazard recognizer to use for by non-scheduling
1524  /// passes.
1525  virtual ScheduleHazardRecognizer *
1527  return nullptr;
1528  }
1529 
1530  /// Provide a global flag for disabling the PreRA hazard recognizer that
1531  /// targets may choose to honor.
1532  bool usePreRAHazardRecognizer() const;
1533 
1534  /// For a comparison instruction, return the source registers
1535  /// in SrcReg and SrcReg2 if having two register operands, and the value it
1536  /// compares against in CmpValue. Return true if the comparison instruction
1537  /// can be analyzed.
1538  virtual bool analyzeCompare(const MachineInstr &MI, Register &SrcReg,
1539  Register &SrcReg2, int64_t &Mask,
1540  int64_t &Value) const {
1541  return false;
1542  }
1543 
1544  /// See if the comparison instruction can be converted
1545  /// into something more efficient. E.g., on ARM most instructions can set the
1546  /// flags register, obviating the need for a separate CMP.
1547  virtual bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
1548  Register SrcReg2, int64_t Mask,
1549  int64_t Value,
1550  const MachineRegisterInfo *MRI) const {
1551  return false;
1552  }
1553  virtual bool optimizeCondBranch(MachineInstr &MI) const { return false; }
1554 
1555  /// Try to remove the load by folding it to a register operand at the use.
1556  /// We fold the load instructions if and only if the
1557  /// def and use are in the same BB. We only look at one load and see
1558  /// whether it can be folded into MI. FoldAsLoadDefReg is the virtual register
1559  /// defined by the load we are trying to fold. DefMI returns the machine
1560  /// instruction that defines FoldAsLoadDefReg, and the function returns
1561  /// the machine instruction generated due to folding.
1563  const MachineRegisterInfo *MRI,
1564  Register &FoldAsLoadDefReg,
1565  MachineInstr *&DefMI) const {
1566  return nullptr;
1567  }
1568 
1569  /// 'Reg' is known to be defined by a move immediate instruction,
1570  /// try to fold the immediate into the use instruction.
1571  /// If MRI->hasOneNonDBGUse(Reg) is true, and this function returns true,
1572  /// then the caller may assume that DefMI has been erased from its parent
1573  /// block. The caller may assume that it will not be erased by this
1574  /// function otherwise.
1576  Register Reg, MachineRegisterInfo *MRI) const {
1577  return false;
1578  }
1579 
1580  /// Return the number of u-operations the given machine
1581  /// instruction will be decoded to on the target cpu. The itinerary's
1582  /// IssueWidth is the number of microops that can be dispatched each
1583  /// cycle. An instruction with zero microops takes no dispatch resources.
1584  virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData,
1585  const MachineInstr &MI) const;
1586 
1587  /// Return true for pseudo instructions that don't consume any
1588  /// machine resources in their current form. These are common cases that the
1589  /// scheduler should consider free, rather than conservatively handling them
1590  /// as instructions with no itinerary.
1591  bool isZeroCost(unsigned Opcode) const {
1592  return Opcode <= TargetOpcode::COPY;
1593  }
1594 
1595  virtual int getOperandLatency(const InstrItineraryData *ItinData,
1596  SDNode *DefNode, unsigned DefIdx,
1597  SDNode *UseNode, unsigned UseIdx) const;
1598 
1599  /// Compute and return the use operand latency of a given pair of def and use.
1600  /// In most cases, the static scheduling itinerary was enough to determine the
1601  /// operand latency. But it may not be possible for instructions with variable
1602  /// number of defs / uses.
1603  ///
1604  /// This is a raw interface to the itinerary that may be directly overridden
1605  /// by a target. Use computeOperandLatency to get the best estimate of
1606  /// latency.
1607  virtual int getOperandLatency(const InstrItineraryData *ItinData,
1608  const MachineInstr &DefMI, unsigned DefIdx,
1609  const MachineInstr &UseMI,
1610  unsigned UseIdx) const;
1611 
1612  /// Compute the instruction latency of a given instruction.
1613  /// If the instruction has higher cost when predicated, it's returned via
1614  /// PredCost.
1615  virtual unsigned getInstrLatency(const InstrItineraryData *ItinData,
1616  const MachineInstr &MI,
1617  unsigned *PredCost = nullptr) const;
1618 
1619  virtual unsigned getPredicationCost(const MachineInstr &MI) const;
1620 
1621  virtual int getInstrLatency(const InstrItineraryData *ItinData,
1622  SDNode *Node) const;
1623 
1624  /// Return the default expected latency for a def based on its opcode.
1625  unsigned defaultDefLatency(const MCSchedModel &SchedModel,
1626  const MachineInstr &DefMI) const;
1627 
1628  /// Return true if this opcode has high latency to its result.
1629  virtual bool isHighLatencyDef(int opc) const { return false; }
1630 
1631  /// Compute operand latency between a def of 'Reg'
1632  /// and a use in the current loop. Return true if the target considered
1633  /// it 'high'. This is used by optimization passes such as machine LICM to
1634  /// determine whether it makes sense to hoist an instruction out even in a
1635  /// high register pressure situation.
1636  virtual bool hasHighOperandLatency(const TargetSchedModel &SchedModel,
1637  const MachineRegisterInfo *MRI,
1638  const MachineInstr &DefMI, unsigned DefIdx,
1639  const MachineInstr &UseMI,
1640  unsigned UseIdx) const {
1641  return false;
1642  }
1643 
1644  /// Compute operand latency of a def of 'Reg'. Return true
1645  /// if the target considered it 'low'.
1646  virtual bool hasLowDefLatency(const TargetSchedModel &SchedModel,
1647  const MachineInstr &DefMI,
1648  unsigned DefIdx) const;
1649 
1650  /// Perform target-specific instruction verification.
1651  virtual bool verifyInstruction(const MachineInstr &MI,
1652  StringRef &ErrInfo) const {
1653  return true;
1654  }
1655 
1656  /// Return the current execution domain and bit mask of
1657  /// possible domains for instruction.
1658  ///
1659  /// Some micro-architectures have multiple execution domains, and multiple
1660  /// opcodes that perform the same operation in different domains. For
1661  /// example, the x86 architecture provides the por, orps, and orpd
1662  /// instructions that all do the same thing. There is a latency penalty if a
1663  /// register is written in one domain and read in another.
1664  ///
1665  /// This function returns a pair (domain, mask) containing the execution
1666  /// domain of MI, and a bit mask of possible domains. The setExecutionDomain
1667  /// function can be used to change the opcode to one of the domains in the
1668  /// bit mask. Instructions whose execution domain can't be changed should
1669  /// return a 0 mask.
1670  ///
1671  /// The execution domain numbers don't have any special meaning except domain
1672  /// 0 is used for instructions that are not associated with any interesting
1673  /// execution domain.
1674  ///
1675  virtual std::pair<uint16_t, uint16_t>
1677  return std::make_pair(0, 0);
1678  }
1679 
1680  /// Change the opcode of MI to execute in Domain.
1681  ///
1682  /// The bit (1 << Domain) must be set in the mask returned from
1683  /// getExecutionDomain(MI).
1684  virtual void setExecutionDomain(MachineInstr &MI, unsigned Domain) const {}
1685 
1686  /// Returns the preferred minimum clearance
1687  /// before an instruction with an unwanted partial register update.
1688  ///
1689  /// Some instructions only write part of a register, and implicitly need to
1690  /// read the other parts of the register. This may cause unwanted stalls
1691  /// preventing otherwise unrelated instructions from executing in parallel in
1692  /// an out-of-order CPU.
1693  ///
1694  /// For example, the x86 instruction cvtsi2ss writes its result to bits
1695  /// [31:0] of the destination xmm register. Bits [127:32] are unaffected, so
1696  /// the instruction needs to wait for the old value of the register to become
1697  /// available:
1698  ///
1699  /// addps %xmm1, %xmm0
1700  /// movaps %xmm0, (%rax)
1701  /// cvtsi2ss %rbx, %xmm0
1702  ///
1703  /// In the code above, the cvtsi2ss instruction needs to wait for the addps
1704  /// instruction before it can issue, even though the high bits of %xmm0
1705  /// probably aren't needed.
1706  ///
1707  /// This hook returns the preferred clearance before MI, measured in
1708  /// instructions. Other defs of MI's operand OpNum are avoided in the last N
1709  /// instructions before MI. It should only return a positive value for
1710  /// unwanted dependencies. If the old bits of the defined register have
1711  /// useful values, or if MI is determined to otherwise read the dependency,
1712  /// the hook should return 0.
1713  ///
1714  /// The unwanted dependency may be handled by:
1715  ///
1716  /// 1. Allocating the same register for an MI def and use. That makes the
1717  /// unwanted dependency identical to a required dependency.
1718  ///
1719  /// 2. Allocating a register for the def that has no defs in the previous N
1720  /// instructions.
1721  ///
1722  /// 3. Calling breakPartialRegDependency() with the same arguments. This
1723  /// allows the target to insert a dependency breaking instruction.
1724  ///
1725  virtual unsigned
1727  const TargetRegisterInfo *TRI) const {
1728  // The default implementation returns 0 for no partial register dependency.
1729  return 0;
1730  }
1731 
1732  /// Return the minimum clearance before an instruction that reads an
1733  /// unused register.
1734  ///
1735  /// For example, AVX instructions may copy part of a register operand into
1736  /// the unused high bits of the destination register.
1737  ///
1738  /// vcvtsi2sdq %rax, undef %xmm0, %xmm14
1739  ///
1740  /// In the code above, vcvtsi2sdq copies %xmm0[127:64] into %xmm14 creating a
1741  /// false dependence on any previous write to %xmm0.
1742  ///
1743  /// This hook works similarly to getPartialRegUpdateClearance, except that it
1744  /// does not take an operand index. Instead sets \p OpNum to the index of the
1745  /// unused register.
1746  virtual unsigned getUndefRegClearance(const MachineInstr &MI, unsigned OpNum,
1747  const TargetRegisterInfo *TRI) const {
1748  // The default implementation returns 0 for no undef register dependency.
1749  return 0;
1750  }
1751 
1752  /// Insert a dependency-breaking instruction
1753  /// before MI to eliminate an unwanted dependency on OpNum.
1754  ///
1755  /// If it wasn't possible to avoid a def in the last N instructions before MI
1756  /// (see getPartialRegUpdateClearance), this hook will be called to break the
1757  /// unwanted dependency.
1758  ///
1759  /// On x86, an xorps instruction can be used as a dependency breaker:
1760  ///
1761  /// addps %xmm1, %xmm0
1762  /// movaps %xmm0, (%rax)
1763  /// xorps %xmm0, %xmm0
1764  /// cvtsi2ss %rbx, %xmm0
1765  ///
1766  /// An <imp-kill> operand should be added to MI if an instruction was
1767  /// inserted. This ties the instructions together in the post-ra scheduler.
1768  ///
1769  virtual void breakPartialRegDependency(MachineInstr &MI, unsigned OpNum,
1770  const TargetRegisterInfo *TRI) const {}
1771 
1772  /// Create machine specific model for scheduling.
1773  virtual DFAPacketizer *
1775  return nullptr;
1776  }
1777 
1778  /// Sometimes, it is possible for the target
1779  /// to tell, even without aliasing information, that two MIs access different
1780  /// memory addresses. This function returns true if two MIs access different
1781  /// memory addresses and false otherwise.
1782  ///
1783  /// Assumes any physical registers used to compute addresses have the same
1784  /// value for both instructions. (This is the most useful assumption for
1785  /// post-RA scheduling.)
1786  ///
1787  /// See also MachineInstr::mayAlias, which is implemented on top of this
1788  /// function.
1789  virtual bool
1791  const MachineInstr &MIb) const {
1792  assert(MIa.mayLoadOrStore() &&
1793  "MIa must load from or modify a memory location");
1794  assert(MIb.mayLoadOrStore() &&
1795  "MIb must load from or modify a memory location");
1796  return false;
1797  }
1798 
1799  /// Return the value to use for the MachineCSE's LookAheadLimit,
1800  /// which is a heuristic used for CSE'ing phys reg defs.
1801  virtual unsigned getMachineCSELookAheadLimit() const {
1802  // The default lookahead is small to prevent unprofitable quadratic
1803  // behavior.
1804  return 5;
1805  }
1806 
1807  /// Return the maximal number of alias checks on memory operands. For
1808  /// instructions with more than one memory operands, the alias check on a
1809  /// single MachineInstr pair has quadratic overhead and results in
1810  /// unacceptable performance in the worst case. The limit here is to clamp
1811  /// that maximal checks performed. Usually, that's the product of memory
1812  /// operand numbers from that pair of MachineInstr to be checked. For
1813  /// instance, with two MachineInstrs with 4 and 5 memory operands
1814  /// correspondingly, a total of 20 checks are required. With this limit set to
1815  /// 16, their alias check is skipped. We choose to limit the product instead
1816  /// of the individual instruction as targets may have special MachineInstrs
1817  /// with a considerably high number of memory operands, such as `ldm` in ARM.
1818  /// Setting this limit per MachineInstr would result in either too high
1819  /// overhead or too rigid restriction.
1820  virtual unsigned getMemOperandAACheckLimit() const { return 16; }
1821 
1822  /// Return an array that contains the ids of the target indices (used for the
1823  /// TargetIndex machine operand) and their names.
1824  ///
1825  /// MIR Serialization is able to serialize only the target indices that are
1826  /// defined by this method.
1829  return None;
1830  }
1831 
1832  /// Decompose the machine operand's target flags into two values - the direct
1833  /// target flag value and any of bit flags that are applied.
1834  virtual std::pair<unsigned, unsigned>
1835  decomposeMachineOperandsTargetFlags(unsigned /*TF*/) const {
1836  return std::make_pair(0u, 0u);
1837  }
1838 
1839  /// Return an array that contains the direct target flag values and their
1840  /// names.
1841  ///
1842  /// MIR Serialization is able to serialize only the target flags that are
1843  /// defined by this method.
1846  return None;
1847  }
1848 
1849  /// Return an array that contains the bitmask target flag values and their
1850  /// names.
1851  ///
1852  /// MIR Serialization is able to serialize only the target flags that are
1853  /// defined by this method.
1856  return None;
1857  }
1858 
1859  /// Return an array that contains the MMO target flag values and their
1860  /// names.
1861  ///
1862  /// MIR Serialization is able to serialize only the MMO target flags that are
1863  /// defined by this method.
1866  return None;
1867  }
1868 
1869  /// Determines whether \p Inst is a tail call instruction. Override this
1870  /// method on targets that do not properly set MCID::Return and MCID::Call on
1871  /// tail call instructions."
1872  virtual bool isTailCall(const MachineInstr &Inst) const {
1873  return Inst.isReturn() && Inst.isCall();
1874  }
1875 
1876  /// True if the instruction is bound to the top of its basic block and no
1877  /// other instructions shall be inserted before it. This can be implemented
1878  /// to prevent register allocator to insert spills before such instructions.
1879  virtual bool isBasicBlockPrologue(const MachineInstr &MI) const {
1880  return false;
1881  }
1882 
1883  /// During PHI eleimination lets target to make necessary checks and
1884  /// insert the copy to the PHI destination register in a target specific
1885  /// manner.
1888  const DebugLoc &DL, Register Src, Register Dst) const {
1889  return BuildMI(MBB, InsPt, DL, get(TargetOpcode::COPY), Dst)
1890  .addReg(Src);
1891  }
1892 
1893  /// During PHI eleimination lets target to make necessary checks and
1894  /// insert the copy to the PHI destination register in a target specific
1895  /// manner.
1898  const DebugLoc &DL, Register Src,
1899  unsigned SrcSubReg,
1900  Register Dst) const {
1901  return BuildMI(MBB, InsPt, DL, get(TargetOpcode::COPY), Dst)
1902  .addReg(Src, 0, SrcSubReg);
1903  }
1904 
1905  /// Returns a \p outliner::OutlinedFunction struct containing target-specific
1906  /// information for a set of outlining candidates.
1908  std::vector<outliner::Candidate> &RepeatedSequenceLocs) const {
1910  "Target didn't implement TargetInstrInfo::getOutliningCandidateInfo!");
1911  }
1912 
1913  /// Returns how or if \p MI should be outlined.
1914  virtual outliner::InstrType
1915  getOutliningType(MachineBasicBlock::iterator &MIT, unsigned Flags) const {
1917  "Target didn't implement TargetInstrInfo::getOutliningType!");
1918  }
1919 
1920  /// Optional target hook that returns true if \p MBB is safe to outline from,
1921  /// and returns any target-specific information in \p Flags.
1923  unsigned &Flags) const {
1924  return true;
1925  }
1926 
1927  /// Insert a custom frame for outlined functions.
1929  const outliner::OutlinedFunction &OF) const {
1931  "Target didn't implement TargetInstrInfo::buildOutlinedFrame!");
1932  }
1933 
1934  /// Insert a call to an outlined function into the program.
1935  /// Returns an iterator to the spot where we inserted the call. This must be
1936  /// implemented by the target.
1940  const outliner::Candidate &C) const {
1942  "Target didn't implement TargetInstrInfo::insertOutlinedCall!");
1943  }
1944 
1945  /// Return true if the function can safely be outlined from.
1946  /// A function \p MF is considered safe for outlining if an outlined function
1947  /// produced from instructions in F will produce a program which produces the
1948  /// same output for any set of given inputs.
1950  bool OutlineFromLinkOnceODRs) const {
1951  llvm_unreachable("Target didn't implement "
1952  "TargetInstrInfo::isFunctionSafeToOutlineFrom!");
1953  }
1954 
1955  /// Return true if the function should be outlined from by default.
1957  return false;
1958  }
1959 
1960  /// Produce the expression describing the \p MI loading a value into
1961  /// the physical register \p Reg. This hook should only be used with
1962  /// \p MIs belonging to VReg-less functions.
1964  Register Reg) const;
1965 
1966  /// Given the generic extension instruction \p ExtMI, returns true if this
1967  /// extension is a likely candidate for being folded into an another
1968  /// instruction.
1970  MachineRegisterInfo &MRI) const {
1971  return false;
1972  }
1973 
1974  /// Return MIR formatter to format/parse MIR operands. Target can override
1975  /// this virtual function and return target specific MIR formatter.
1976  virtual const MIRFormatter *getMIRFormatter() const {
1977  if (!Formatter.get())
1978  Formatter = std::make_unique<MIRFormatter>();
1979  return Formatter.get();
1980  }
1981 
1982  /// Returns the target-specific default value for tail duplication.
1983  /// This value will be used if the tail-dup-placement-threshold argument is
1984  /// not provided.
1985  virtual unsigned getTailDuplicateSize(CodeGenOpt::Level OptLevel) const {
1986  return OptLevel >= CodeGenOpt::Aggressive ? 4 : 2;
1987  }
1988 
1989  /// Returns the callee operand from the given \p MI.
1990  virtual const MachineOperand &getCalleeOperand(const MachineInstr &MI) const {
1991  return MI.getOperand(0);
1992  }
1993 
1994 private:
1995  mutable std::unique_ptr<MIRFormatter> Formatter;
1996  unsigned CallFrameSetupOpcode, CallFrameDestroyOpcode;
1997  unsigned CatchRetOpcode;
1998  unsigned ReturnOpcode;
1999 };
2000 
2001 /// Provide DenseMapInfo for TargetInstrInfo::RegSubRegPair.
2004 
2006  return TargetInstrInfo::RegSubRegPair(RegInfo::getEmptyKey(),
2007  RegInfo::getEmptyKey());
2008  }
2009 
2011  return TargetInstrInfo::RegSubRegPair(RegInfo::getTombstoneKey(),
2012  RegInfo::getTombstoneKey());
2013  }
2014 
2015  /// Reuse getHashValue implementation from
2016  /// std::pair<unsigned, unsigned>.
2017  static unsigned getHashValue(const TargetInstrInfo::RegSubRegPair &Val) {
2018  std::pair<unsigned, unsigned> PairVal = std::make_pair(Val.Reg, Val.SubReg);
2019  return DenseMapInfo<std::pair<unsigned, unsigned>>::getHashValue(PairVal);
2020  }
2021 
2022  static bool isEqual(const TargetInstrInfo::RegSubRegPair &LHS,
2023  const TargetInstrInfo::RegSubRegPair &RHS) {
2024  return RegInfo::isEqual(LHS.Reg, RHS.Reg) &&
2025  RegInfo::isEqual(LHS.SubReg, RHS.SubReg);
2026  }
2027 };
2028 
2029 } // end namespace llvm
2030 
2031 #endif // LLVM_CODEGEN_TARGETINSTRINFO_H
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
llvm::TargetInstrInfo::getConstValDefinedInReg
virtual bool getConstValDefinedInReg(const MachineInstr &MI, const Register Reg, int64_t &ImmVal) const
Returns true if MI is an instruction that defines Reg to have a constant value and the value is recor...
Definition: TargetInstrInfo.h:1026
llvm::TargetInstrInfo::hasReassociableSibling
bool hasReassociableSibling(const MachineInstr &Inst, bool &Commuted) const
Return true when \P Inst has reassociable sibling.
Definition: TargetInstrInfo.cpp:719
llvm::TargetInstrInfo::getMemOperandWithOffset
bool getMemOperandWithOffset(const MachineInstr &MI, const MachineOperand *&BaseOp, int64_t &Offset, bool &OffsetIsScalable, const TargetRegisterInfo *TRI) const
Get the base operand and byte offset of an instruction that reads/writes memory.
Definition: TargetInstrInfo.cpp:1071
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:105
MachineInstr.h
llvm
This file implements support for optimizing divisions by a constant.
Definition: AllocatorList.h:23
llvm::TargetInstrInfo::isSafeToMoveRegClassDefs
virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const
Return true if it's safe to move a machine instruction that defines the specified register class.
Definition: TargetInstrInfo.h:1489
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::TargetInstrInfo::analyzeCompare
virtual bool analyzeCompare(const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int64_t &Mask, int64_t &Value) const
For a comparison instruction, return the source registers in SrcReg and SrcReg2 if having two registe...
Definition: TargetInstrInfo.h:1538
llvm::TargetInstrInfo::insertSelect
virtual void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register DstReg, ArrayRef< MachineOperand > Cond, Register TrueReg, Register FalseReg) const
Insert a select instruction into MBB before I that will copy TrueReg to DstReg when Cond is true,...
Definition: TargetInstrInfo.h:896
UseMI
MachineInstrBuilder & UseMI
Definition: AArch64ExpandPseudoInsts.cpp:102
llvm::TargetInstrInfo::isSubregFoldable
virtual bool isSubregFoldable() const
Check whether the target can fold a load that feeds a subreg operand (or a subreg operand that feeds ...
Definition: TargetInstrInfo.h:1077
llvm::TargetInstrInfo::duplicate
virtual MachineInstr & duplicate(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, const MachineInstr &Orig) const
Clones instruction or the whole instruction bundle Orig and insert into MBB before InsertBefore.
Definition: TargetInstrInfo.cpp:435
llvm::TargetInstrInfo::areLoadsFromSameBasePtr
virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1, int64_t &Offset2) const
This is used by the pre-regalloc scheduler to determine if two loads are loading from the same base a...
Definition: TargetInstrInfo.h:1308
llvm::TargetInstrInfo::CreateTargetHazardRecognizer
virtual ScheduleHazardRecognizer * CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const
Allocate and return a hazard recognizer to use for this target when scheduling the machine instructio...
Definition: TargetInstrInfo.cpp:1051
llvm::DenseMapInfo< unsigned >
Definition: DenseMapInfo.h:117
llvm::TargetInstrInfo::replaceBranchWithTailCall
virtual void replaceBranchWithTailCall(MachineBasicBlock &MBB, SmallVectorImpl< MachineOperand > &Cond, const MachineInstr &TailCall) const
Replace the conditional branch in MBB with a conditional tail call.
Definition: TargetInstrInfo.h:1449
llvm::TargetInstrInfo::getCatchReturnOpcode
unsigned getCatchReturnOpcode() const
Definition: TargetInstrInfo.h:238
llvm::TargetInstrInfo::unfoldMemoryOperand
virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr &MI, unsigned Reg, bool UnfoldLoad, bool UnfoldStore, SmallVectorImpl< MachineInstr * > &NewMIs) const
unfoldMemoryOperand - Separate a single instruction which folded a load or a store or a load and a st...
Definition: TargetInstrInfo.h:1281
llvm::TargetInstrInfo::useMachineCombiner
virtual bool useMachineCombiner() const
Return true when a target supports MachineCombiner.
Definition: TargetInstrInfo.h:1193
llvm::TargetInstrInfo::analyzeBranchPredicate
virtual bool analyzeBranchPredicate(MachineBasicBlock &MBB, MachineBranchPredicate &MBP, bool AllowModify=false) const
Analyze the branching code at the end of MBB and parse it into the MachineBranchPredicate structure i...
Definition: TargetInstrInfo.h:666
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
llvm::TargetInstrInfo::MachineBranchPredicate
Represents a predicate at the MachineFunction level.
Definition: TargetInstrInfo.h:637
llvm::MachineInstr::mayLoadOrStore
bool mayLoadOrStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read or modify memory.
Definition: MachineInstr.h:1028
llvm::RegImmPair::Imm
int64_t Imm
Definition: TargetInstrInfo.h:79
llvm::TargetInstrInfo::getReturnOpcode
unsigned getReturnOpcode() const
Definition: TargetInstrInfo.h:239
llvm::TargetInstrInfo::isThroughputPattern
virtual bool isThroughputPattern(MachineCombinerPattern Pattern) const
Return true when a code sequence can improve throughput.
Definition: TargetInstrInfo.cpp:801
P
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
Definition: README-SSE.txt:411
llvm::MCAsmInfo
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
llvm::TargetInstrInfo::canInsertSelect
virtual bool canInsertSelect(const MachineBasicBlock &MBB, ArrayRef< MachineOperand > Cond, Register DstReg, Register TrueReg, Register FalseReg, int &CondCycles, int &TrueCycles, int &FalseCycles) const
Return true if it is possible to insert a select instruction that chooses between TrueReg and FalseRe...
Definition: TargetInstrInfo.h:873
llvm::TargetInstrInfo::getExtractSubregInputs
bool getExtractSubregInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPairAndIdx &InputReg) const
Build the equivalent inputs of a EXTRACT_SUBREG for the given MI and DefIdx.
Definition: TargetInstrInfo.cpp:1294
llvm::TargetInstrInfo::createPHIDestinationCopy
virtual MachineInstr * createPHIDestinationCopy(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsPt, const DebugLoc &DL, Register Src, Register Dst) const
During PHI eleimination lets target to make necessary checks and insert the copy to the PHI destinati...
Definition: TargetInstrInfo.h:1886
llvm::TargetInstrInfo::RegSubRegPairAndIdx
A pair composed of a pair of a register and a sub-register index, and another sub-register index.
Definition: TargetInstrInfo.h:494
llvm::TargetInstrInfo::getMachineCombinerPatterns
virtual bool getMachineCombinerPatterns(MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &Patterns, bool DoRegPressureReduce) const
Return true when there is potentially a faster code sequence for an instruction chain ending in Root.
Definition: TargetInstrInfo.cpp:777
llvm::TargetInstrInfo::isLoadFromStackSlot
virtual unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex, unsigned &MemBytes) const
Optional extension of isLoadFromStackSlot that returns the number of bytes loaded from the stack.
Definition: TargetInstrInfo.h:271
llvm::TargetInstrInfo::getUndefRegClearance
virtual unsigned getUndefRegClearance(const MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const
Return the minimum clearance before an instruction that reads an unused register.
Definition: TargetInstrInfo.h:1746
ErrorHandling.h
llvm::VirtRegMap
Definition: VirtRegMap.h:33
llvm::TargetInstrInfo::isCopyInstrImpl
virtual Optional< DestSourcePair > isCopyInstrImpl(const MachineInstr &MI) const
Target-dependent implementation for IsCopyInstr.
Definition: TargetInstrInfo.h:985
llvm::DenseMapInfo< TargetInstrInfo::RegSubRegPair >::isEqual
static bool isEqual(const TargetInstrInfo::RegSubRegPair &LHS, const TargetInstrInfo::RegSubRegPair &RHS)
Definition: TargetInstrInfo.h:2022
llvm::TargetInstrInfo::copyPhysReg
virtual void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const
Emit instructions to copy a pair of physical registers.
Definition: TargetInstrInfo.h:959
llvm::TargetInstrInfo::isGenericOpcode
static bool isGenericOpcode(unsigned Opc)
Definition: TargetInstrInfo.h:108
llvm::SDNode
Represents one node in the SelectionDAG.
Definition: SelectionDAGNodes.h:455
RegisterClassInfo.h
llvm::TargetInstrInfo::optimizeCondBranch
virtual bool optimizeCondBranch(MachineInstr &MI) const
Definition: TargetInstrInfo.h:1553
MachineBasicBlock.h
llvm::TargetInstrInfo::getAddressSpaceForPseudoSourceKind
virtual unsigned getAddressSpaceForPseudoSourceKind(unsigned Kind) const
getAddressSpaceForPseudoSourceKind - Given the kind of memory (e.g.
Definition: TargetInstrInfo.h:1273
llvm::TargetInstrInfo::MachineBranchPredicate::RHS
MachineOperand RHS
Definition: TargetInstrInfo.h:646
llvm::TargetInstrInfo::getCalleeOperand
virtual const MachineOperand & getCalleeOperand(const MachineInstr &MI) const
Returns the callee operand from the given MI.
Definition: TargetInstrInfo.h:1990
llvm::TargetInstrInfo::isUnspillableTerminator
bool isUnspillableTerminator(const MachineInstr *MI) const
Return true if the given instruction is terminator that is unspillable, according to isUnspillableTer...
Definition: TargetInstrInfo.h:360
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:233
llvm::TargetInstrInfo::insertNoops
virtual void insertNoops(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned Quantity) const
Insert noops into the instruction stream at the specified point.
Definition: TargetInstrInfo.cpp:74
llvm::TargetInstrInfo::getIncrementValue
virtual bool getIncrementValue(const MachineInstr &MI, int &Value) const
If the instruction is an increment of a constant value, return the amount.
Definition: TargetInstrInfo.h:1381
llvm::outliner::InstrType
InstrType
Represents how an instruction should be mapped by the outliner.
Definition: MachineOutliner.h:34
llvm::TargetInstrInfo::ReplaceTailWithBranchTo
virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail, MachineBasicBlock *NewDest) const
Delete the instruction OldInst and everything after it, replacing it with an unconditional branch to ...
Definition: TargetInstrInfo.cpp:141
DenseMap.h
llvm::TargetInstrInfo::MachineBranchPredicate::FalseDest
MachineBasicBlock * FalseDest
Definition: TargetInstrInfo.h:648
llvm::TargetInstrInfo::getOutliningCandidateInfo
virtual outliner::OutlinedFunction getOutliningCandidateInfo(std::vector< outliner::Candidate > &RepeatedSequenceLocs) const
Returns a outliner::OutlinedFunction struct containing target-specific information for a set of outli...
Definition: TargetInstrInfo.h:1907
llvm::TargetInstrInfo::CreateTargetScheduleState
virtual DFAPacketizer * CreateTargetScheduleState(const TargetSubtargetInfo &) const
Create machine specific model for scheduling.
Definition: TargetInstrInfo.h:1774
llvm::Optional< bool >
llvm::DestSourcePair::Destination
const MachineOperand * Destination
Definition: TargetInstrInfo.h:69
llvm::TargetInstrInfo::isCopyInstr
Optional< DestSourcePair > isCopyInstr(const MachineInstr &MI) const
If the specific machine instruction is a instruction that moves/copies value from one register to ano...
Definition: TargetInstrInfo.h:1007
llvm::TargetInstrInfo::getNop
virtual MCInst getNop() const
Return the noop instruction to use for a noop.
Definition: TargetInstrInfo.cpp:475
llvm::ExtAddrMode::ScaledReg
Register ScaledReg
Definition: TargetInstrInfo.h:88
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
llvm::TargetInstrInfo::isBranchOffsetInRange
virtual bool isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const
Definition: TargetInstrInfo.h:574
llvm::TargetInstrInfo::hasHighOperandLatency
virtual bool hasHighOperandLatency(const TargetSchedModel &SchedModel, const MachineRegisterInfo *MRI, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const
Compute operand latency between a def of 'Reg' and a use in the current loop.
Definition: TargetInstrInfo.h:1636
llvm::TargetInstrInfo::isPredicable
virtual bool isPredicable(const MachineInstr &MI) const
Return true if the specified instruction can be predicated.
Definition: TargetInstrInfo.h:1483
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
llvm::outliner::OutlinedFunction
The information necessary to create an outlined function for some class of candidate.
Definition: MachineOutliner.h:164
llvm::TargetInstrInfo::getInsertSubregInputs
bool getInsertSubregInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPair &BaseReg, RegSubRegPairAndIdx &InsertedReg) const
Build the equivalent inputs of a INSERT_SUBREG for the given MI and DefIdx.
Definition: TargetInstrInfo.cpp:1319
llvm::TargetInstrInfo::hasCommutePreference
virtual bool hasCommutePreference(MachineInstr &MI, bool &Commute) const
Returns true if the target has a preference on the operands order of the given machine instruction.
Definition: TargetInstrInfo.h:470
llvm::TargetInstrInfo::decomposeMachineOperandsTargetFlags
virtual std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned) const
Decompose the machine operand's target flags into two values - the direct target flag value and any o...
Definition: TargetInstrInfo.h:1835
llvm::TargetInstrInfo::RegSubRegPair::operator!=
bool operator!=(const RegSubRegPair &P) const
Definition: TargetInstrInfo.h:486
llvm::TargetInstrInfo::unfoldMemoryOperand
virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, SmallVectorImpl< SDNode * > &NewNodes) const
Definition: TargetInstrInfo.h:1287
llvm::TargetInstrInfo::shouldClusterMemOps
virtual bool shouldClusterMemOps(ArrayRef< const MachineOperand * > BaseOps1, ArrayRef< const MachineOperand * > BaseOps2, unsigned NumLoads, unsigned NumBytes) const
Returns true if the two given memory operations should be scheduled adjacent.
Definition: TargetInstrInfo.h:1397
llvm::BitmaskEnumDetail::Mask
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
llvm::TargetInstrInfo::foldMemoryOperandImpl
virtual MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI, LiveIntervals *LIS=nullptr) const
Target-dependent implementation for foldMemoryOperand.
Definition: TargetInstrInfo.h:1219
llvm::TargetInstrInfo::getPartialRegUpdateClearance
virtual unsigned getPartialRegUpdateClearance(const MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const
Returns the preferred minimum clearance before an instruction with an unwanted partial register updat...
Definition: TargetInstrInfo.h:1726
llvm::TargetInstrInfo::isHighLatencyDef
virtual bool isHighLatencyDef(int opc) const
Return true if this opcode has high latency to its result.
Definition: TargetInstrInfo.h:1629
llvm::TargetInstrInfo::RegSubRegPair
A pair composed of a register and a sub-register index.
Definition: TargetInstrInfo.h:476
llvm::ExtAddrMode
Used to describe addressing mode similar to ExtAddrMode in CodeGenPrepare.
Definition: TargetInstrInfo.h:86
llvm::RegImmPair::Reg
Register Reg
Definition: TargetInstrInfo.h:78
llvm::TargetInstrInfo::insertBranch
virtual unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const
Insert branch code into the end of the specified MachineBasicBlock.
Definition: TargetInstrInfo.h:695
llvm::TargetInstrInfo::getMachineCSELookAheadLimit
virtual unsigned getMachineCSELookAheadLimit() const
Return the value to use for the MachineCSE's LookAheadLimit, which is a heuristic used for CSE'ing ph...
Definition: TargetInstrInfo.h:1801
llvm::TargetInstrInfo::RegSubRegPair::operator==
bool operator==(const RegSubRegPair &P) const
Definition: TargetInstrInfo.h:483
llvm::TargetInstrInfo::isZeroCost
bool isZeroCost(unsigned Opcode) const
Return true for pseudo instructions that don't consume any machine resources in their current form.
Definition: TargetInstrInfo.h:1591
llvm::TargetInstrInfo::getFrameSize
int64_t getFrameSize(const MachineInstr &I) const
Returns size of the frame associated with the given frame instruction.
Definition: TargetInstrInfo.h:220
llvm::TargetInstrInfo::PipelinerLoopInfo
Object returned by analyzeLoopForPipelining.
Definition: TargetInstrInfo.h:714
llvm::TargetInstrInfo::getRegClass
virtual const TargetRegisterClass * getRegClass(const MCInstrDesc &MCID, unsigned OpNum, const TargetRegisterInfo *TRI, const MachineFunction &MF) const
Given a machine instruction descriptor, returns the register class constraint for OpNum,...
Definition: TargetInstrInfo.cpp:47
llvm::DenseMapInfo
Definition: APInt.h:34
llvm::TargetInstrInfo::MachineBranchPredicate::PRED_NE
@ PRED_NE
Definition: TargetInstrInfo.h:640
llvm::TargetInstrInfo::usePreRAHazardRecognizer
bool usePreRAHazardRecognizer() const
Provide a global flag for disabling the PreRA hazard recognizer that targets may choose to honor.
Definition: TargetInstrInfo.cpp:1045
llvm::CallingConv::Tail
@ Tail
Tail - This calling convention attemps to make calls as fast as possible while guaranteeing that tail...
Definition: CallingConv.h:81
llvm::TargetInstrInfo::getFrameTotalSize
int64_t getFrameTotalSize(const MachineInstr &I) const
Returns the total frame size, which is made up of the space set up inside the pair of frame start-sto...
Definition: TargetInstrInfo.h:229
llvm::MachineInstr::isCall
bool isCall(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:823
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:97
llvm::TargetInstrInfo::removeBranch
virtual unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const
Remove the branching code at the end of the specific MBB.
Definition: TargetInstrInfo.h:677
llvm::TargetInstrInfo::commuteInstructionImpl
virtual MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const
This method commutes the operands of the given machine instruction MI.
Definition: TargetInstrInfo.cpp:167
llvm::SelectionDAG
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:216
llvm::TargetInstrInfo::loadRegFromStackSlot
virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const
Load the specified register of the given register class from the specified stack frame index.
Definition: TargetInstrInfo.h:1048
llvm::AAResults
Definition: AliasAnalysis.h:508
llvm::MachineOperand::CreateImm
static MachineOperand CreateImm(int64_t Val)
Definition: MachineOperand.h:773
llvm::TargetInstrInfo::MachineBranchPredicate::ConditionDef
MachineInstr * ConditionDef
Definition: TargetInstrInfo.h:649
llvm::TargetInstrInfo::canCopyGluedNodeDuringSchedule
virtual bool canCopyGluedNodeDuringSchedule(SDNode *N) const
Return true if the given SDNode can be copied during scheduling even if it has glue.
Definition: TargetInstrInfo.h:1197
llvm::TargetInstrInfo::verifyInstruction
virtual bool verifyInstruction(const MachineInstr &MI, StringRef &ErrInfo) const
Perform target-specific instruction verification.
Definition: TargetInstrInfo.h:1651
llvm::TargetInstrInfo::getInsertSubregLikeInputs
virtual bool getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPair &BaseReg, RegSubRegPairAndIdx &InsertedReg) const
Target-dependent implementation of getInsertSubregInputs.
Definition: TargetInstrInfo.h:1263
llvm::TargetInstrInfo::PipelinerLoopInfo::adjustTripCount
virtual void adjustTripCount(int TripCountAdjust)=0
Modify the loop such that the trip count is OriginalTC + TripCountAdjust.
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::TargetInstrInfo::optimizeLoadInstr
virtual MachineInstr * optimizeLoadInstr(MachineInstr &MI, const MachineRegisterInfo *MRI, Register &FoldAsLoadDefReg, MachineInstr *&DefMI) const
Try to remove the load by folding it to a register operand at the use.
Definition: TargetInstrInfo.h:1562
llvm::TargetInstrInfo::setSpecialOperandAttr
virtual void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2, MachineInstr &NewMI1, MachineInstr &NewMI2) const
This is an architecture-specific helper function of reassociateOps.
Definition: TargetInstrInfo.h:1186
llvm::TargetInstrInfo::FoldImmediate
virtual bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg, MachineRegisterInfo *MRI) const
'Reg' is known to be defined by a move immediate instruction, try to fold the immediate into the use ...
Definition: TargetInstrInfo.h:1575
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::TargetInstrInfo::buildOutlinedFrame
virtual void buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF, const outliner::OutlinedFunction &OF) const
Insert a custom frame for outlined functions.
Definition: TargetInstrInfo.h:1928
llvm::TargetInstrInfo::getExtendResourceLenLimit
virtual int getExtendResourceLenLimit() const
The limit on resource length extension we accept in MachineCombiner Pass.
Definition: TargetInstrInfo.h:1182
MCInstrInfo.h
llvm::DFAPacketizer
Definition: DFAPacketizer.h:49
llvm::TargetInstrInfo::RegSubRegPairAndIdx::RegSubRegPairAndIdx
RegSubRegPairAndIdx(Register Reg=Register(), unsigned SubReg=0, unsigned SubIdx=0)
Definition: TargetInstrInfo.h:497
llvm::TargetInstrInfo::getRegSequenceLikeInputs
virtual bool getRegSequenceLikeInputs(const MachineInstr &MI, unsigned DefIdx, SmallVectorImpl< RegSubRegPairAndIdx > &InputRegs) const
Target-dependent implementation of getRegSequenceInputs.
Definition: TargetInstrInfo.h:1234
llvm::TargetInstrInfo::isReassociationCandidate
bool isReassociationCandidate(const MachineInstr &Inst, bool &Commuted) const
Return true if the input \P Inst is part of a chain of dependent ops that are suitable for reassociat...
Definition: TargetInstrInfo.cpp:749
llvm::TargetInstrInfo::shouldOutlineFromFunctionByDefault
virtual bool shouldOutlineFromFunctionByDefault(MachineFunction &MF) const
Return true if the function should be outlined from by default.
Definition: TargetInstrInfo.h:1956
Domain
Domain
Definition: CorrelatedValuePropagation.cpp:660
llvm::TargetInstrInfo::expandPostRAPseudo
virtual bool expandPostRAPseudo(MachineInstr &MI) const
This function is called for all pseudo instructions that remain after register allocation.
Definition: TargetInstrInfo.h:1063
llvm::TargetInstrInfo::insertNoop
virtual void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const
Insert a noop into the instruction stream at the specified point.
Definition: TargetInstrInfo.cpp:67
llvm::TargetInstrInfo::getNumMicroOps
virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData, const MachineInstr &MI) const
Return the number of u-operations the given machine instruction will be decoded to on the target cpu.
Definition: TargetInstrInfo.cpp:1120
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:195
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
llvm::TargetInstrInfo::isTailCall
virtual bool isTailCall(const MachineInstr &Inst) const
Determines whether Inst is a tail call instruction.
Definition: TargetInstrInfo.h:1872
llvm::TargetInstrInfo::MachineBranchPredicate::PRED_INVALID
@ PRED_INVALID
Definition: TargetInstrInfo.h:641
llvm::TargetInstrInfo::~TargetInstrInfo
virtual ~TargetInstrInfo()
Definition: TargetInstrInfo.cpp:43
llvm::TargetInstrInfo::analyzeSelect
virtual bool analyzeSelect(const MachineInstr &MI, SmallVectorImpl< MachineOperand > &Cond, unsigned &TrueOp, unsigned &FalseOp, bool &Optimizable) const
Analyze the given select instruction, returning true if it cannot be understood.
Definition: TargetInstrInfo.h:921
llvm::TargetInstrInfo::isProfitableToDupForIfCvt
virtual bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const
Return true if it's profitable for if-converter to duplicate instructions of specified accumulated in...
Definition: TargetInstrInfo.h:820
llvm::TargetInstrInfo::shouldScheduleLoadsNear
virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1, int64_t Offset2, unsigned NumLoads) const
This is a used by the pre-regalloc scheduler to determine (in conjunction with areLoadsFromSameBasePt...
Definition: TargetInstrInfo.h:1322
MachineCombinerPattern.h
llvm::TargetInstrInfo::isStackSlotCopy
virtual bool isStackSlotCopy(const MachineInstr &MI, int &DestFrameIndex, int &SrcFrameIndex) const
Return true if the specified machine instruction is a copy of one stack slot to another and has no ot...
Definition: TargetInstrInfo.h:336
llvm::TargetInstrInfo::reverseBranchCondition
virtual bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const
Reverses the branch condition of the specified condition list, returning false on success and true if...
Definition: TargetInstrInfo.h:1406
llvm::TargetInstrInfo::defaultDefLatency
unsigned defaultDefLatency(const MCSchedModel &SchedModel, const MachineInstr &DefMI) const
Return the default expected latency for a def based on its opcode.
Definition: TargetInstrInfo.cpp:1136
llvm::TargetInstrInfo::PipelinerLoopInfo::disposed
virtual void disposed()=0
Called when the loop is being removed.
llvm::TargetInstrInfo::shouldSink
virtual bool shouldSink(const MachineInstr &MI) const
Return true if the instruction should be sunk by MachineSink.
Definition: TargetInstrInfo.h:383
llvm::None
const NoneType None
Definition: None.h:23
llvm::lltok::Kind
Kind
Definition: LLToken.h:18
llvm::TargetInstrInfo::optimizeSelect
virtual MachineInstr * optimizeSelect(MachineInstr &MI, SmallPtrSetImpl< MachineInstr * > &NewMIs, bool PreferFalse=false) const
Given a select instruction that was understood by analyzeSelect and returned Optimizable = true,...
Definition: TargetInstrInfo.h:944
BranchProbability.h
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::TargetInstrInfo::isExtendLikelyToBeFolded
virtual bool isExtendLikelyToBeFolded(MachineInstr &ExtMI, MachineRegisterInfo &MRI) const
Given the generic extension instruction ExtMI, returns true if this extension is a likely candidate f...
Definition: TargetInstrInfo.h:1969
llvm::TargetInstrInfo::MachineBranchPredicate::PRED_EQ
@ PRED_EQ
Definition: TargetInstrInfo.h:639
llvm::TargetInstrInfo::hasReassociableOperands
virtual bool hasReassociableOperands(const MachineInstr &Inst, const MachineBasicBlock *MBB) const
Return true when \P Inst has reassociable operands in the same \P MBB.
Definition: TargetInstrInfo.cpp:700
llvm::TargetInstrInfo::isCoalescableExtInstr
virtual bool isCoalescableExtInstr(const MachineInstr &MI, Register &SrcReg, Register &DstReg, unsigned &SubIdx) const
Return true if the instruction is a "coalescable" extension instruction.
Definition: TargetInstrInfo.h:252
llvm::TargetInstrInfo::getBranchDestBlock
virtual MachineBasicBlock * getBranchDestBlock(const MachineInstr &MI) const
Definition: TargetInstrInfo.h:580
llvm::TargetInstrInfo::analyzeLoopForPipelining
virtual std::unique_ptr< PipelinerLoopInfo > analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const
Analyze loop L, which must be a single-basic-block loop, and if the conditions can be understood enou...
Definition: TargetInstrInfo.h:751
llvm::TargetInstrInfo::MachineBranchPredicate::SingleUseCondition
bool SingleUseCondition
SingleUseCondition is true if ConditionDef is dead except for the branch(es) at the end of the basic ...
Definition: TargetInstrInfo.h:654
llvm::TargetInstrInfo::RegSubRegPair::RegSubRegPair
RegSubRegPair(Register Reg=Register(), unsigned SubReg=0)
Definition: TargetInstrInfo.h:480
llvm::TargetInstrInfo::getBaseAndOffsetPosition
virtual bool getBaseAndOffsetPosition(const MachineInstr &MI, unsigned &BasePos, unsigned &OffsetPos) const
Return true if the instruction contains a base register and offset.
Definition: TargetInstrInfo.h:1353
llvm::CmpInst
This class is the base class for the comparison instructions.
Definition: InstrTypes.h:710
llvm::TargetInstrInfo::createMIROperandComment
virtual std::string createMIROperandComment(const MachineInstr &MI, const MachineOperand &Op, unsigned OpIdx, const TargetRegisterInfo *TRI) const
Definition: TargetInstrInfo.cpp:1348
llvm::TargetInstrInfo::isStoreToStackSlot
virtual unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex, unsigned &MemBytes) const
Optional extension of isStoreToStackSlot that returns the number of bytes stored to the stack.
Definition: TargetInstrInfo.h:309
llvm::TargetInstrInfo::isStoreToStackSlot
virtual unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const
If the specified machine instruction is a direct store to a stack slot, return the virtual or physica...
Definition: TargetInstrInfo.h:300
llvm::TargetInstrInfo::getOutliningType
virtual outliner::InstrType getOutliningType(MachineBasicBlock::iterator &MIT, unsigned Flags) const
Returns how or if MI should be outlined.
Definition: TargetInstrInfo.h:1915
llvm::TargetInstrInfo::isAssociativeAndCommutative
virtual bool isAssociativeAndCommutative(const MachineInstr &Inst) const
Return true when \P Inst is both associative and commutative.
Definition: TargetInstrInfo.h:1146
llvm::TargetInstrInfo::PredicateInstruction
virtual bool PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Pred) const
Convert the instruction into a predicated instruction.
Definition: TargetInstrInfo.cpp:331
llvm::TargetInstrInfo::canMakeTailCallConditional
virtual bool canMakeTailCallConditional(SmallVectorImpl< MachineOperand > &Cond, const MachineInstr &TailCall) const
Returns true if the tail call can be made conditional on BranchCond.
Definition: TargetInstrInfo.h:1443
llvm::DenseMapInfo< TargetInstrInfo::RegSubRegPair >::getHashValue
static unsigned getHashValue(const TargetInstrInfo::RegSubRegPair &Val)
Reuse getHashValue implementation from std::pair<unsigned, unsigned>.
Definition: TargetInstrInfo.h:2017
llvm::TargetInstrInfo::getStackSlotRange
virtual bool getStackSlotRange(const TargetRegisterClass *RC, unsigned SubIdx, unsigned &Size, unsigned &Offset, const MachineFunction &MF) const
Compute the size in bytes and offset within a stack slot of a spilled register or subregister.
Definition: TargetInstrInfo.cpp:389
llvm::TargetInstrInfo::getSerializableBitmaskMachineOperandTargetFlags
virtual ArrayRef< std::pair< unsigned, const char * > > getSerializableBitmaskMachineOperandTargetFlags() const
Return an array that contains the bitmask target flag values and their names.
Definition: TargetInstrInfo.h:1855
llvm::MachineLoop
Definition: MachineLoopInfo.h:45
llvm::TargetInstrInfo::RegSubRegPair::Reg
Register Reg
Definition: TargetInstrInfo.h:477
llvm::TargetSchedModel
Provide an instruction scheduling machine model to CodeGen passes.
Definition: TargetSchedule.h:30
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
VirtRegMap.h
llvm::ExtAddrMode::BaseReg
Register BaseReg
Definition: TargetInstrInfo.h:87
llvm::TargetInstrInfo::isPredicated
virtual bool isPredicated(const MachineInstr &MI) const
Returns true if the instruction is already predicated.
Definition: TargetInstrInfo.h:1426
llvm::TargetInstrInfo::getAddrModeFromMemoryOp
virtual Optional< ExtAddrMode > getAddrModeFromMemoryOp(const MachineInstr &MemI, const TargetRegisterInfo *TRI) const
Target dependent implementation to get the values constituting the address MachineInstr that is acces...
Definition: TargetInstrInfo.h:1364
llvm::TargetInstrInfo::TargetInstrInfo
TargetInstrInfo(unsigned CFSetupOpcode=~0u, unsigned CFDestroyOpcode=~0u, unsigned CatchRetOpcode=~0u, unsigned ReturnOpcode=~0u)
Definition: TargetInstrInfo.h:99
llvm::outliner::Candidate
An individual sequence of instructions to be replaced with a call to an outlined function.
Definition: MachineOutliner.h:38
llvm::TargetInstrInfo::breakPartialRegDependency
virtual void breakPartialRegDependency(MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const
Insert a dependency-breaking instruction before MI to eliminate an unwanted dependency on OpNum.
Definition: TargetInstrInfo.h:1769
llvm::TargetInstrInfo::insertOutlinedCall
virtual MachineBasicBlock::iterator insertOutlinedCall(Module &M, MachineBasicBlock &MBB, MachineBasicBlock::iterator &It, MachineFunction &MF, const outliner::Candidate &C) const
Insert a call to an outlined function into the program.
Definition: TargetInstrInfo.h:1938
llvm::DenseMap< unsigned, unsigned >
llvm::TargetInstrInfo::isMBBSafeToOutlineFrom
virtual bool isMBBSafeToOutlineFrom(MachineBasicBlock &MBB, unsigned &Flags) const
Optional target hook that returns true if MBB is safe to outline from, and returns any target-specifi...
Definition: TargetInstrInfo.h:1922
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::RegScavenger
Definition: RegisterScavenging.h:34
llvm::TargetInstrInfo::hasStoreToStackSlot
virtual bool hasStoreToStackSlot(const MachineInstr &MI, SmallVectorImpl< const MachineMemOperand * > &Accesses) const
If the specified machine instruction has a store to a stack slot, return true along with the FrameInd...
Definition: TargetInstrInfo.cpp:375
ArrayRef.h
llvm::TargetInstrInfo::isStoreToStackSlotPostFE
virtual unsigned isStoreToStackSlotPostFE(const MachineInstr &MI, int &FrameIndex) const
Check for post-frame ptr elimination stack locations as well.
Definition: TargetInstrInfo.h:318
llvm::ParamLoadedValue
std::pair< MachineOperand, DIExpression * > ParamLoadedValue
Definition: TargetInstrInfo.h:66
llvm::TargetInstrInfo::commuteInstruction
MachineInstr * commuteInstruction(MachineInstr &MI, bool NewMI=false, unsigned OpIdx1=CommuteAnyOperandIndex, unsigned OpIdx2=CommuteAnyOperandIndex) const
This method commutes the operands of the given machine instruction MI.
Definition: TargetInstrInfo.cpp:250
llvm::TargetInstrInfo::isAsCheapAsAMove
virtual bool isAsCheapAsAMove(const MachineInstr &MI) const
Return true if the instruction is as cheap as a move instruction.
Definition: TargetInstrInfo.h:374
RegSubRegPair
TargetInstrInfo::RegSubRegPair RegSubRegPair
Definition: PeepholeOptimizer.cpp:101
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::TargetInstrInfo::getInstSizeInBytes
virtual unsigned getInstSizeInBytes(const MachineInstr &MI) const
Returns the size in bytes of the specified MachineInstr, or ~0U when this function is not implemented...
Definition: TargetInstrInfo.h:366
llvm::TargetInstrInfo::insertUnconditionalBranch
unsigned insertUnconditionalBranch(MachineBasicBlock &MBB, MachineBasicBlock *DestBB, const DebugLoc &DL, int *BytesAdded=nullptr) const
Definition: TargetInstrInfo.h:703
llvm::RegisterClassInfo
Definition: RegisterClassInfo.h:30
llvm::TargetInstrInfo::describeLoadedValue
virtual Optional< ParamLoadedValue > describeLoadedValue(const MachineInstr &MI, Register Reg) const
Produce the expression describing the MI loading a value into the physical register Reg.
Definition: TargetInstrInfo.cpp:1175
llvm::TargetInstrInfo::MachineBranchPredicate::ComparePredicate
ComparePredicate
Definition: TargetInstrInfo.h:638
llvm::TargetInstrInfo::PipelinerLoopInfo::~PipelinerLoopInfo
virtual ~PipelinerLoopInfo()
Definition: TargetInstrInfo.cpp:1403
llvm::TargetInstrInfo::isLoadFromStackSlotPostFE
virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI, int &FrameIndex) const
Check for post-frame ptr elimination stack locations as well.
Definition: TargetInstrInfo.h:280
MIRFormatter.h
llvm::TargetInstrInfo::getSerializableMachineMemOperandTargetFlags
virtual ArrayRef< std::pair< MachineMemOperand::Flags, const char * > > getSerializableMachineMemOperandTargetFlags() const
Return an array that contains the MMO target flag values and their names.
Definition: TargetInstrInfo.h:1865
llvm::TargetInstrInfo::isPCRelRegisterOperandLegal
virtual bool isPCRelRegisterOperandLegal(const MachineOperand &MO) const
Allow targets to tell MachineVerifier whether a specific register MachineOperand can be used as part ...
Definition: TargetInstrInfo.h:975
llvm::TargetInstrInfo::produceSameValue
virtual bool produceSameValue(const MachineInstr &MI0, const MachineInstr &MI1, const MachineRegisterInfo *MRI=nullptr) const
Return true if two machine instructions would produce identical values.
Definition: TargetInstrInfo.cpp:429
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:97
llvm::Module
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:67
llvm::ScheduleDAGMI
ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...
Definition: MachineScheduler.h:266
llvm::TargetInstrInfo::createPHISourceCopy
virtual MachineInstr * createPHISourceCopy(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsPt, const DebugLoc &DL, Register Src, unsigned SrcSubReg, Register Dst) const
During PHI eleimination lets target to make necessary checks and insert the copy to the PHI destinati...
Definition: TargetInstrInfo.h:1896
llvm::RegImmPair
Used to describe a register and immediate addition.
Definition: TargetInstrInfo.h:77
llvm::CodeGenOpt::Aggressive
@ Aggressive
Definition: CodeGen.h:56
llvm::MachineInstr::isReturn
bool isReturn(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:813
llvm::TargetInstrInfo::getPatchpointUnfoldableRange
virtual std::pair< unsigned, unsigned > getPatchpointUnfoldableRange(const MachineInstr &MI) const
For a patchpoint, stackmap, or statepoint intrinsic, return the range of operands which can't be fold...
Definition: TargetInstrInfo.cpp:478
llvm::TargetInstrInfo::MachineBranchPredicate::Predicate
ComparePredicate Predicate
Definition: TargetInstrInfo.h:644
llvm::MachineFunction
Definition: MachineFunction.h:230
llvm::TargetInstrInfo::isLegalToSplitMBBAt
virtual bool isLegalToSplitMBBAt(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const
Return true if it's legal to split the given basic block at the specified instruction (i....
Definition: TargetInstrInfo.h:784
llvm::TargetInstrInfo::analyzeLoop
virtual bool analyzeLoop(MachineLoop &L, MachineInstr *&IndVarInst, MachineInstr *&CmpInst) const
Analyze the loop code, return true if it cannot be understood.
Definition: TargetInstrInfo.h:758
llvm::TargetInstrInfo::getSPAdjust
virtual int getSPAdjust(const MachineInstr &MI) const
Returns the actual stack pointer adjustment made by an instruction as part of a call sequence.
Definition: TargetInstrInfo.cpp:998
llvm::ScheduleDAG
Definition: ScheduleDAG.h:555
llvm::TargetInstrInfo::getPredicationCost
virtual unsigned getPredicationCost(const MachineInstr &MI) const
Definition: TargetInstrInfo.cpp:1147
llvm::TargetInstrInfo::hasLoadFromStackSlot
virtual bool hasLoadFromStackSlot(const MachineInstr &MI, SmallVectorImpl< const MachineMemOperand * > &Accesses) const
If the specified machine instruction has a load from a stack slot, return true along with the FrameIn...
Definition: TargetInstrInfo.cpp:361
llvm::TargetInstrInfo::ClobbersPredicate
virtual bool ClobbersPredicate(MachineInstr &MI, std::vector< MachineOperand > &Pred, bool SkipDead) const
If the specified instruction defines any predicate or condition code register(s) used for predication...
Definition: TargetInstrInfo.h:1474
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
None.h
llvm::TargetInstrInfo::RegSubRegPair::SubReg
unsigned SubReg
Definition: TargetInstrInfo.h:478
Cond
SmallVector< MachineOperand, 4 > Cond
Definition: BasicBlockSections.cpp:179
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
MBBI
MachineBasicBlock MachineBasicBlock::iterator MBBI
Definition: AArch64SLSHardening.cpp:75
llvm::TargetInstrInfo::getTailDuplicateSize
virtual unsigned getTailDuplicateSize(CodeGenOpt::Level OptLevel) const
Returns the target-specific default value for tail duplication.
Definition: TargetInstrInfo.h:1985
llvm::TargetInstrInfo::reMaterialize
virtual void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, unsigned SubIdx, const MachineInstr &Orig, const TargetRegisterInfo &TRI) const
Re-issue the specified 'original' instruction at the specific location targeting a new destination re...
Definition: TargetInstrInfo.cpp:419
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:134
llvm::TargetInstrInfo::storeRegToStackSlot
virtual void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const
Store the specified register of the given register class to the specified stack frame index.
Definition: TargetInstrInfo.h:1036
llvm::BranchProbability
Definition: BranchProbability.h:30
llvm::TargetInstrInfo::extraSizeToPredicateInstructions
virtual unsigned extraSizeToPredicateInstructions(const MachineFunction &MF, unsigned NumInsts) const
Return the increase in code size needed to predicate a contiguous run of NumInsts instructions.
Definition: TargetInstrInfo.h:828
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
Module
Machine Check Debug Module
Definition: MachineCheckDebugify.cpp:122
Node
Definition: ItaniumDemangle.h:235
llvm::CodeGenOpt::Level
Level
Definition: CodeGen.h:52
llvm::TargetInstrInfo::isUnpredicatedTerminator
bool isUnpredicatedTerminator(const MachineInstr &MI) const
Returns true if the instruction is a terminator instruction that has not been predicated.
Definition: TargetInstrInfo.cpp:320
llvm::MipsISD::TailCall
@ TailCall
Definition: MipsISelLowering.h:65
llvm::TargetInstrInfo::isFrameInstr
bool isFrameInstr(const MachineInstr &I) const
Returns true if the argument is a frame pseudo instruction.
Definition: TargetInstrInfo.h:202
llvm::TargetSubtargetInfo
TargetSubtargetInfo - Generic base class for all target subtargets.
Definition: TargetSubtargetInfo.h:59
llvm::DenseMapInfo< TargetInstrInfo::RegSubRegPair >::getEmptyKey
static TargetInstrInfo::RegSubRegPair getEmptyKey()
Definition: TargetInstrInfo.h:2005
llvm::TargetInstrInfo::predictBranchSizeForIfCvt
virtual unsigned predictBranchSizeForIfCvt(MachineInstr &MI) const
Return an estimate for the code size reduction (in bytes) which will be caused by removing the given ...
Definition: TargetInstrInfo.h:835
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::TargetInstrInfo::fixCommutedOpIndices
static bool fixCommutedOpIndices(unsigned &ResultIdx1, unsigned &ResultIdx2, unsigned CommutableOpIdx1, unsigned CommutableOpIdx2)
Assigns the (CommutableOpIdx1, CommutableOpIdx2) pair of commutable operand indices to (ResultIdx1,...
Definition: TargetInstrInfo.cpp:265
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::TargetInstrInfo::isTriviallyReMaterializable
bool isTriviallyReMaterializable(const MachineInstr &MI, AAResults *AA=nullptr) const
Return true if the instruction is trivially rematerializable, meaning it has no side effects and requ...
Definition: TargetInstrInfo.h:124
llvm::TargetInstrInfo::isProfitableToUnpredicate
virtual bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, MachineBasicBlock &FMBB) const
Return true if it's profitable to unpredicate one side of a 'diamond', i.e.
Definition: TargetInstrInfo.h:850
llvm::TargetInstrInfo::isSchedulingBoundary
virtual bool isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const
Test if the given instruction should be considered a scheduling boundary.
Definition: TargetInstrInfo.cpp:1022
llvm::TargetInstrInfo::isFunctionSafeToOutlineFrom
virtual bool isFunctionSafeToOutlineFrom(MachineFunction &MF, bool OutlineFromLinkOnceODRs) const
Return true if the function can safely be outlined from.
Definition: TargetInstrInfo.h:1949
llvm::ISD::FrameIndex
@ FrameIndex
Definition: ISDOpcodes.h:80
llvm::TargetInstrInfo::reduceLoopCount
virtual unsigned reduceLoopCount(MachineBasicBlock &MBB, MachineBasicBlock &PreHeader, MachineInstr *IndVar, MachineInstr &Cmp, SmallVectorImpl< MachineOperand > &Cond, SmallVectorImpl< MachineInstr * > &PrevInsts, unsigned Iter, unsigned MaxIter) const
Generate code to reduce the loop iteration by one and check if the loop is finished.
Definition: TargetInstrInfo.h:767
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::MCInstrInfo
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:25
llvm::TargetInstrInfo::getCallFrameDestroyOpcode
unsigned getCallFrameDestroyOpcode() const
Definition: TargetInstrInfo.h:199
llvm::TargetInstrInfo::getExecutionDomain
virtual std::pair< uint16_t, uint16_t > getExecutionDomain(const MachineInstr &MI) const
Return the current execution domain and bit mask of possible domains for instruction.
Definition: TargetInstrInfo.h:1676
llvm::TargetInstrInfo::isIgnorableUse
virtual bool isIgnorableUse(const MachineOperand &MO) const
Given MO is a PhysReg use return if it can be ignored for the purpose of instruction rematerializatio...
Definition: TargetInstrInfo.h:134
llvm::TargetInstrInfo::isUnconditionalTailCall
virtual bool isUnconditionalTailCall(const MachineInstr &MI) const
Returns true if MI is an unconditional tail call.
Definition: TargetInstrInfo.h:1438
llvm::TargetInstrInfo::isProfitableToIfCvt
virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const
Return true if it's profitable to predicate instructions with accumulated instruction latency of "Num...
Definition: TargetInstrInfo.h:794
llvm::TargetInstrInfo::isPostIncrement
virtual bool isPostIncrement(const MachineInstr &MI) const
Return true for post-incremented instructions.
Definition: TargetInstrInfo.h:1423
uint16_t
llvm::DestSourcePair
Definition: TargetInstrInfo.h:68
llvm::TargetInstrInfo::preservesZeroValueInReg
virtual bool preservesZeroValueInReg(const MachineInstr *MI, const Register NullValueReg, const TargetRegisterInfo *TRI) const
Returns true if MI's Def is NullValueReg, and the MI does not change the Zero value.
Definition: TargetInstrInfo.h:1374
llvm::TargetInstrInfo::operator=
TargetInstrInfo & operator=(const TargetInstrInfo &)=delete
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:324
llvm::TargetInstrInfo::getMemOperandsWithOffsetWidth
virtual bool getMemOperandsWithOffsetWidth(const MachineInstr &MI, SmallVectorImpl< const MachineOperand * > &BaseOps, int64_t &Offset, bool &OffsetIsScalable, unsigned &Width, const TargetRegisterInfo *TRI) const
Get zero or more base operands and the byte offset of an instruction that reads/writes memory.
Definition: TargetInstrInfo.h:1343
llvm::TargetInstrInfo::setSpecialOperandAttr
virtual void setSpecialOperandAttr(MachineInstr &MI, uint16_t Flags) const
Definition: TargetInstrInfo.h:1190
llvm::TargetInstrInfo::analyzeBranch
virtual bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const
Analyze the branching code at the end of MBB, returning true if it cannot be understood (e....
Definition: TargetInstrInfo.h:624
llvm::TargetInstrInfo::reassociateOps
void reassociateOps(MachineInstr &Root, MachineInstr &Prev, MachineCombinerPattern Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, DenseMap< unsigned, unsigned > &InstrIdxForVirtReg) const
Attempt to reassociate \P Root and \P Prev according to \P Pattern to reduce critical path length.
Definition: TargetInstrInfo.cpp:807
llvm::TargetInstrInfo::getRegSequenceInputs
bool getRegSequenceInputs(const MachineInstr &MI, unsigned DefIdx, SmallVectorImpl< RegSubRegPairAndIdx > &InputRegs) const
Build the equivalent inputs of a REG_SEQUENCE for the given MI and DefIdx.
Definition: TargetInstrInfo.cpp:1267
llvm::TargetInstrInfo::PipelinerLoopInfo::createTripCountGreaterCondition
virtual Optional< bool > createTripCountGreaterCondition(int TC, MachineBasicBlock &MBB, SmallVectorImpl< MachineOperand > &Cond)=0
Create a condition to determine if the trip count of the loop is greater than TC.
llvm::TargetInstrInfo::CreateTargetMIHazardRecognizer
virtual ScheduleHazardRecognizer * CreateTargetMIHazardRecognizer(const InstrItineraryData *, const ScheduleDAGMI *DAG) const
Allocate and return a hazard recognizer to use for this target when scheduling the machine instructio...
Definition: TargetInstrInfo.cpp:1058
llvm::ExtAddrMode::Displacement
int64_t Displacement
Definition: TargetInstrInfo.h:90
llvm::TargetInstrInfo::areMemAccessesTriviallyDisjoint
virtual bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb) const
Sometimes, it is possible for the target to tell, even without aliasing information,...
Definition: TargetInstrInfo.h:1790
llvm::ExtAddrMode::Scale
int64_t Scale
Definition: TargetInstrInfo.h:89
llvm::MCSchedModel
Machine model for scheduling, bundling, and heuristics.
Definition: MCSchedule.h:244
llvm::TargetInstrInfo::getInstrLatency
virtual unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const
Compute the instruction latency of a given instruction.
Definition: TargetInstrInfo.cpp:1151
llvm::LiveIntervals
Definition: LiveIntervals.h:54
isEqual
static bool isEqual(const Function &Caller, const Function &Callee)
Definition: Attributes.cpp:1856
llvm::TargetInstrInfo::isBasicBlockPrologue
virtual bool isBasicBlockPrologue(const MachineInstr &MI) const
True if the instruction is bound to the top of its basic block and no other instructions shall be ins...
Definition: TargetInstrInfo.h:1879
llvm::AMDGPU::Hwreg::Width
Width
Definition: SIDefines.h:413
llvm::TargetInstrInfo::optimizeCompareInstr
virtual bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int64_t Mask, int64_t Value, const MachineRegisterInfo *MRI) const
See if the comparison instruction can be converted into something more efficient.
Definition: TargetInstrInfo.h:1547
llvm::TargetInstrInfo::hasLowDefLatency
virtual bool hasLowDefLatency(const TargetSchedModel &SchedModel, const MachineInstr &DefMI, unsigned DefIdx) const
Compute operand latency of a def of 'Reg'.
Definition: TargetInstrInfo.cpp:1162
llvm::TargetInstrInfo::MachineBranchPredicate::LHS
MachineOperand LHS
Definition: TargetInstrInfo.h:645
llvm::TargetInstrInfo::getCallFrameSetupOpcode
unsigned getCallFrameSetupOpcode() const
These methods return the opcode of the frame setup/destroy instructions if they exist (-1 otherwise).
Definition: TargetInstrInfo.h:198
llvm::TargetInstrInfo::isUnspillableTerminatorImpl
virtual bool isUnspillableTerminatorImpl(const MachineInstr *MI) const
Return true if the given terminator MI is not expected to spill.
Definition: TargetInstrInfo.h:996
llvm::TargetInstrInfo::getMIRFormatter
virtual const MIRFormatter * getMIRFormatter() const
Return MIR formatter to format/parse MIR operands.
Definition: TargetInstrInfo.h:1976
llvm::MIRFormatter
MIRFormater - Interface to format MIR operand based on target.
Definition: MIRFormatter.h:29
llvm::TargetInstrInfo::shouldReduceRegisterPressure
virtual bool shouldReduceRegisterPressure(MachineBasicBlock *MBB, RegisterClassInfo *RegClassInfo) const
Return true if target supports reassociation of instructions in machine combiner pass to reduce regis...
Definition: TargetInstrInfo.h:1123
llvm::TargetInstrInfo::PipelinerLoopInfo::setPreheader
virtual void setPreheader(MachineBasicBlock *NewPreheader)=0
Called when the loop's preheader has been modified to NewPreheader.
llvm::Pattern
Definition: FileCheckImpl.h:614
llvm::TargetInstrInfo::foldMemoryOperandImpl
virtual MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const
Target-dependent implementation for foldMemoryOperand.
Definition: TargetInstrInfo.h:1206
llvm::DestSourcePair::Source
const MachineOperand * Source
Definition: TargetInstrInfo.h:70
llvm::TargetInstrInfo::getMemOperandAACheckLimit
virtual unsigned getMemOperandAACheckLimit() const
Return the maximal number of alias checks on memory operands.
Definition: TargetInstrInfo.h:1820
llvm::TargetInstrInfo::foldMemoryOperand
MachineInstr * foldMemoryOperand(MachineInstr &MI, ArrayRef< unsigned > Ops, int FI, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const
Attempt to fold a load or store of the specified stack slot into the specified machine instruction fo...
Definition: TargetInstrInfo.cpp:560
MachineInstrBuilder.h
llvm::TargetInstrInfo::findCommutedOpIndices
virtual bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const
Returns true iff the routine could find two commutable operands in the given machine instruction.
Definition: TargetInstrInfo.cpp:296
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:328
N
#define N
DefMI
MachineInstrBuilder MachineInstrBuilder & DefMI
Definition: AArch64ExpandPseudoInsts.cpp:103
llvm::TargetInstrInfo::genAlternativeCodeSequence
virtual void genAlternativeCodeSequence(MachineInstr &Root, MachineCombinerPattern Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, DenseMap< unsigned, unsigned > &InstIdxForVirtReg) const
When getMachineCombinerPatterns() finds patterns, this function generates the instructions that could...
Definition: TargetInstrInfo.cpp:891
llvm::TargetInstrInfo::getOperandLatency
virtual int getOperandLatency(const InstrItineraryData *ItinData, SDNode *DefNode, unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const
Definition: TargetInstrInfo.cpp:1089
llvm::DenseMapInfo< TargetInstrInfo::RegSubRegPair >::getTombstoneKey
static TargetInstrInfo::RegSubRegPair getTombstoneKey()
Definition: TargetInstrInfo.h:2010
llvm::TargetInstrInfo::isFrameSetup
bool isFrameSetup(const MachineInstr &I) const
Returns true if the argument is a frame setup pseudo instruction.
Definition: TargetInstrInfo.h:208
llvm::TargetInstrInfo::PipelinerLoopInfo::shouldIgnoreForPipelining
virtual bool shouldIgnoreForPipelining(const MachineInstr *MI) const =0
Return true if the given instruction should not be pipelined and should be ignored.
llvm::TargetInstrInfo::insertIndirectBranch
virtual unsigned insertIndirectBranch(MachineBasicBlock &MBB, MachineBasicBlock &NewDestBB, const DebugLoc &DL, int64_t BrOffset=0, RegScavenger *RS=nullptr) const
Insert an unconditional indirect branch at the end of MBB to NewDestBB.
Definition: TargetInstrInfo.h:589
llvm::TargetInstrInfo::CreateTargetPostRAHazardRecognizer
virtual ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const MachineFunction &MF) const
Allocate and return a hazard recognizer to use for by non-scheduling passes.
Definition: TargetInstrInfo.h:1526
llvm::RegImmPair::RegImmPair
RegImmPair(Register Reg, int64_t Imm)
Definition: TargetInstrInfo.h:81
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
llvm::TargetInstrInfo::CreateTargetPostRAHazardRecognizer
virtual ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const InstrItineraryData *, const ScheduleDAG *DAG) const
Allocate and return a hazard recognizer to use for this target when scheduling the machine instructio...
Definition: TargetInstrInfo.cpp:1065
llvm::TargetInstrInfo::setExecutionDomain
virtual void setExecutionDomain(MachineInstr &MI, unsigned Domain) const
Change the opcode of MI to execute in Domain.
Definition: TargetInstrInfo.h:1684
MachineOperand.h
DenseMapInfo.h
llvm::SmallPtrSetImpl
A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...
Definition: SmallPtrSet.h:343
llvm::TargetInstrInfo::MachineBranchPredicate::TrueDest
MachineBasicBlock * TrueDest
Definition: TargetInstrInfo.h:647
llvm::LiveVariables
Definition: LiveVariables.h:46
llvm::MCInstrInfo::get
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
Definition: MCInstrInfo.h:62
llvm::DestSourcePair::DestSourcePair
DestSourcePair(const MachineOperand &Dest, const MachineOperand &Src)
Definition: TargetInstrInfo.h:72
llvm::TargetInstrInfo::getSerializableDirectMachineOperandTargetFlags
virtual ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const
Return an array that contains the direct target flag values and their names.
Definition: TargetInstrInfo.h:1845
llvm::TargetInstrInfo::getOpcodeAfterMemoryUnfold
virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, bool UnfoldLoad, bool UnfoldStore, unsigned *LoadRegIndex=nullptr) const
Returns the opcode of the would be new instruction after load / store are unfolded from an instructio...
Definition: TargetInstrInfo.h:1299
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::TargetInstrInfo::CommuteAnyOperandIndex
static const unsigned CommuteAnyOperandIndex
Definition: TargetInstrInfo.h:423
llvm::TargetInstrInfo::isReallyTriviallyReMaterializable
virtual bool isReallyTriviallyReMaterializable(const MachineInstr &MI, AAResults *AA) const
For instructions with opcodes for which the M_REMATERIALIZABLE flag is set, this hook lets the target...
Definition: TargetInstrInfo.h:146
MachineFunction.h
llvm::ScheduleHazardRecognizer
HazardRecognizer - This determines whether or not an instruction can be issued this cycle,...
Definition: ScheduleHazardRecognizer.h:25
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::TargetInstrInfo::isAddImmediate
virtual Optional< RegImmPair > isAddImmediate(const MachineInstr &MI, Register Reg) const
If the specific machine instruction is an instruction that adds an immediate value and a physical reg...
Definition: TargetInstrInfo.h:1018
llvm::TargetInstrInfo::finalizeInsInstrs
virtual void finalizeInsInstrs(MachineInstr &Root, MachineCombinerPattern &P, SmallVectorImpl< MachineInstr * > &InsInstrs) const
Fix up the placeholder we may add in genAlternativeCodeSequence().
Definition: TargetInstrInfo.h:1130
llvm::TargetInstrInfo::MachineBranchPredicate::MachineBranchPredicate
MachineBranchPredicate()=default
llvm::Value
LLVM Value Representation.
Definition: Value.h:75
llvm::TargetInstrInfo::SubsumesPredicate
virtual bool SubsumesPredicate(ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const
Returns true if the first specified predicate subsumes the second, e.g.
Definition: TargetInstrInfo.h:1462
llvm::InstrItineraryData
Itinerary data supplied by a subtarget to be used by a target.
Definition: MCInstrItineraries.h:109
llvm::TargetInstrInfo::isProfitableToIfCvt
virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumTCycles, unsigned ExtraTCycles, MachineBasicBlock &FMBB, unsigned NumFCycles, unsigned ExtraFCycles, BranchProbability Probability) const
Second variant of isProfitableToIfCvt.
Definition: TargetInstrInfo.h:806
llvm::TargetInstrInfo::getExtractSubregLikeInputs
virtual bool getExtractSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPairAndIdx &InputReg) const
Target-dependent implementation of getExtractSubregInputs.
Definition: TargetInstrInfo.h:1248
llvm::TargetInstrInfo::RegSubRegPairAndIdx::SubIdx
unsigned SubIdx
Definition: TargetInstrInfo.h:495
llvm::TargetInstrInfo::getInlineAsmLength
virtual unsigned getInlineAsmLength(const char *Str, const MCAsmInfo &MAI, const TargetSubtargetInfo *STI=nullptr) const
Measure the specified inline asm to determine an approximation of its length.
Definition: TargetInstrInfo.cpp:100
llvm::TargetInstrInfo::isLoadFromStackSlot
virtual unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const
If the specified machine instruction is a direct load from a stack slot, return the virtual or physic...
Definition: TargetInstrInfo.h:262
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24
llvm::TargetInstrInfo::getSerializableTargetIndices
virtual ArrayRef< std::pair< int, const char * > > getSerializableTargetIndices() const
Return an array that contains the ids of the target indices (used for the TargetIndex machine operand...
Definition: TargetInstrInfo.h:1828
llvm::MachineCombinerPattern
MachineCombinerPattern
These are instruction patterns matched by the machine combiner pass.
Definition: MachineCombinerPattern.h:20
MachineOutliner.h
llvm::TargetInstrInfo::convertToThreeAddress
virtual MachineInstr * convertToThreeAddress(MachineInstr &MI, LiveVariables *LV) const
This method must be implemented by targets that set the M_CONVERTIBLE_TO_3_ADDR flag.
Definition: TargetInstrInfo.h:414