LLVM  16.0.0git
TargetInstrInfo.h
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1 //===- llvm/CodeGen/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file describes the target machine instruction set to the code generator.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_CODEGEN_TARGETINSTRINFO_H
14 #define LLVM_CODEGEN_TARGETINSTRINFO_H
15 
16 #include "llvm/ADT/ArrayRef.h"
17 #include "llvm/ADT/DenseMap.h"
18 #include "llvm/ADT/DenseMapInfo.h"
19 #include "llvm/ADT/None.h"
30 #include "llvm/MC/MCInstrInfo.h"
33 #include <cassert>
34 #include <cstddef>
35 #include <cstdint>
36 #include <utility>
37 #include <vector>
38 
39 namespace llvm {
40 
41 class DFAPacketizer;
42 class InstrItineraryData;
43 class LiveIntervals;
44 class LiveVariables;
45 class MachineLoop;
46 class MachineMemOperand;
47 class MachineRegisterInfo;
48 class MCAsmInfo;
49 class MCInst;
50 struct MCSchedModel;
51 class Module;
52 class ScheduleDAG;
53 class ScheduleDAGMI;
54 class ScheduleHazardRecognizer;
55 class SDNode;
56 class SelectionDAG;
57 class SMSchedule;
58 class SwingSchedulerDAG;
59 class RegScavenger;
60 class TargetRegisterClass;
61 class TargetRegisterInfo;
62 class TargetSchedModel;
63 class TargetSubtargetInfo;
64 
65 template <class T> class SmallVectorImpl;
66 
67 using ParamLoadedValue = std::pair<MachineOperand, DIExpression*>;
68 
72 
73  DestSourcePair(const MachineOperand &Dest, const MachineOperand &Src)
74  : Destination(&Dest), Source(&Src) {}
75 };
76 
77 /// Used to describe a register and immediate addition.
78 struct RegImmPair {
80  int64_t Imm;
81 
82  RegImmPair(Register Reg, int64_t Imm) : Reg(Reg), Imm(Imm) {}
83 };
84 
85 /// Used to describe addressing mode similar to ExtAddrMode in CodeGenPrepare.
86 /// It holds the register values, the scale value and the displacement.
87 struct ExtAddrMode {
90  int64_t Scale;
91  int64_t Displacement;
92 };
93 
94 //---------------------------------------------------------------------------
95 ///
96 /// TargetInstrInfo - Interface to description of machine instruction set
97 ///
98 class TargetInstrInfo : public MCInstrInfo {
99 public:
100  TargetInstrInfo(unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u,
101  unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u)
102  : CallFrameSetupOpcode(CFSetupOpcode),
103  CallFrameDestroyOpcode(CFDestroyOpcode), CatchRetOpcode(CatchRetOpcode),
104  ReturnOpcode(ReturnOpcode) {}
105  TargetInstrInfo(const TargetInstrInfo &) = delete;
106  TargetInstrInfo &operator=(const TargetInstrInfo &) = delete;
107  virtual ~TargetInstrInfo();
108 
109  static bool isGenericOpcode(unsigned Opc) {
110  return Opc <= TargetOpcode::GENERIC_OP_END;
111  }
112 
113  static bool isGenericAtomicRMWOpcode(unsigned Opc) {
114  return Opc >= TargetOpcode::GENERIC_ATOMICRMW_OP_START &&
115  Opc <= TargetOpcode::GENERIC_ATOMICRMW_OP_END;
116  }
117 
118  /// Given a machine instruction descriptor, returns the register
119  /// class constraint for OpNum, or NULL.
120  virtual
121  const TargetRegisterClass *getRegClass(const MCInstrDesc &MCID, unsigned OpNum,
122  const TargetRegisterInfo *TRI,
123  const MachineFunction &MF) const;
124 
125  /// Return true if the instruction is trivially rematerializable, meaning it
126  /// has no side effects and requires no operands that aren't always available.
127  /// This means the only allowed uses are constants and unallocatable physical
128  /// registers so that the instructions result is independent of the place
129  /// in the function.
131  return MI.getOpcode() == TargetOpcode::IMPLICIT_DEF ||
132  (MI.getDesc().isRematerializable() &&
134  isReallyTriviallyReMaterializableGeneric(MI)));
135  }
136 
137  /// Given \p MO is a PhysReg use return if it can be ignored for the purpose
138  /// of instruction rematerialization or sinking.
139  virtual bool isIgnorableUse(const MachineOperand &MO) const {
140  return false;
141  }
142 
143 protected:
144  /// For instructions with opcodes for which the M_REMATERIALIZABLE flag is
145  /// set, this hook lets the target specify whether the instruction is actually
146  /// trivially rematerializable, taking into consideration its operands. This
147  /// predicate must return false if the instruction has any side effects other
148  /// than producing a value, or if it requres any address registers that are
149  /// not always available.
150  /// Requirements must be check as stated in isTriviallyReMaterializable() .
151  virtual bool isReallyTriviallyReMaterializable(const MachineInstr &MI) const {
152  return false;
153  }
154 
155  /// This method commutes the operands of the given machine instruction MI.
156  /// The operands to be commuted are specified by their indices OpIdx1 and
157  /// OpIdx2.
158  ///
159  /// If a target has any instructions that are commutable but require
160  /// converting to different instructions or making non-trivial changes
161  /// to commute them, this method can be overloaded to do that.
162  /// The default implementation simply swaps the commutable operands.
163  ///
164  /// If NewMI is false, MI is modified in place and returned; otherwise, a
165  /// new machine instruction is created and returned.
166  ///
167  /// Do not call this method for a non-commutable instruction.
168  /// Even though the instruction is commutable, the method may still
169  /// fail to commute the operands, null pointer is returned in such cases.
170  virtual MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
171  unsigned OpIdx1,
172  unsigned OpIdx2) const;
173 
174  /// Assigns the (CommutableOpIdx1, CommutableOpIdx2) pair of commutable
175  /// operand indices to (ResultIdx1, ResultIdx2).
176  /// One or both input values of the pair: (ResultIdx1, ResultIdx2) may be
177  /// predefined to some indices or be undefined (designated by the special
178  /// value 'CommuteAnyOperandIndex').
179  /// The predefined result indices cannot be re-defined.
180  /// The function returns true iff after the result pair redefinition
181  /// the fixed result pair is equal to or equivalent to the source pair of
182  /// indices: (CommutableOpIdx1, CommutableOpIdx2). It is assumed here that
183  /// the pairs (x,y) and (y,x) are equivalent.
184  static bool fixCommutedOpIndices(unsigned &ResultIdx1, unsigned &ResultIdx2,
185  unsigned CommutableOpIdx1,
186  unsigned CommutableOpIdx2);
187 
188 private:
189  /// For instructions with opcodes for which the M_REMATERIALIZABLE flag is
190  /// set and the target hook isReallyTriviallyReMaterializable returns false,
191  /// this function does target-independent tests to determine if the
192  /// instruction is really trivially rematerializable.
193  bool isReallyTriviallyReMaterializableGeneric(const MachineInstr &MI) const;
194 
195 public:
196  /// These methods return the opcode of the frame setup/destroy instructions
197  /// if they exist (-1 otherwise). Some targets use pseudo instructions in
198  /// order to abstract away the difference between operating with a frame
199  /// pointer and operating without, through the use of these two instructions.
200  ///
201  unsigned getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; }
202  unsigned getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; }
203 
204  /// Returns true if the argument is a frame pseudo instruction.
205  bool isFrameInstr(const MachineInstr &I) const {
206  return I.getOpcode() == getCallFrameSetupOpcode() ||
207  I.getOpcode() == getCallFrameDestroyOpcode();
208  }
209 
210  /// Returns true if the argument is a frame setup pseudo instruction.
211  bool isFrameSetup(const MachineInstr &I) const {
212  return I.getOpcode() == getCallFrameSetupOpcode();
213  }
214 
215  /// Returns size of the frame associated with the given frame instruction.
216  /// For frame setup instruction this is frame that is set up space set up
217  /// after the instruction. For frame destroy instruction this is the frame
218  /// freed by the caller.
219  /// Note, in some cases a call frame (or a part of it) may be prepared prior
220  /// to the frame setup instruction. It occurs in the calls that involve
221  /// inalloca arguments. This function reports only the size of the frame part
222  /// that is set up between the frame setup and destroy pseudo instructions.
223  int64_t getFrameSize(const MachineInstr &I) const {
224  assert(isFrameInstr(I) && "Not a frame instruction");
225  assert(I.getOperand(0).getImm() >= 0);
226  return I.getOperand(0).getImm();
227  }
228 
229  /// Returns the total frame size, which is made up of the space set up inside
230  /// the pair of frame start-stop instructions and the space that is set up
231  /// prior to the pair.
232  int64_t getFrameTotalSize(const MachineInstr &I) const {
233  if (isFrameSetup(I)) {
234  assert(I.getOperand(1).getImm() >= 0 &&
235  "Frame size must not be negative");
236  return getFrameSize(I) + I.getOperand(1).getImm();
237  }
238  return getFrameSize(I);
239  }
240 
241  unsigned getCatchReturnOpcode() const { return CatchRetOpcode; }
242  unsigned getReturnOpcode() const { return ReturnOpcode; }
243 
244  /// Returns the actual stack pointer adjustment made by an instruction
245  /// as part of a call sequence. By default, only call frame setup/destroy
246  /// instructions adjust the stack, but targets may want to override this
247  /// to enable more fine-grained adjustment, or adjust by a different value.
248  virtual int getSPAdjust(const MachineInstr &MI) const;
249 
250  /// Return true if the instruction is a "coalescable" extension instruction.
251  /// That is, it's like a copy where it's legal for the source to overlap the
252  /// destination. e.g. X86::MOVSX64rr32. If this returns true, then it's
253  /// expected the pre-extension value is available as a subreg of the result
254  /// register. This also returns the sub-register index in SubIdx.
255  virtual bool isCoalescableExtInstr(const MachineInstr &MI, Register &SrcReg,
256  Register &DstReg, unsigned &SubIdx) const {
257  return false;
258  }
259 
260  /// If the specified machine instruction is a direct
261  /// load from a stack slot, return the virtual or physical register number of
262  /// the destination along with the FrameIndex of the loaded stack slot. If
263  /// not, return 0. This predicate must return 0 if the instruction has
264  /// any side effects other than loading from the stack slot.
265  virtual unsigned isLoadFromStackSlot(const MachineInstr &MI,
266  int &FrameIndex) const {
267  return 0;
268  }
269 
270  /// Optional extension of isLoadFromStackSlot that returns the number of
271  /// bytes loaded from the stack. This must be implemented if a backend
272  /// supports partial stack slot spills/loads to further disambiguate
273  /// what the load does.
274  virtual unsigned isLoadFromStackSlot(const MachineInstr &MI,
275  int &FrameIndex,
276  unsigned &MemBytes) const {
277  MemBytes = 0;
279  }
280 
281  /// Check for post-frame ptr elimination stack locations as well.
282  /// This uses a heuristic so it isn't reliable for correctness.
283  virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI,
284  int &FrameIndex) const {
285  return 0;
286  }
287 
288  /// If the specified machine instruction has a load from a stack slot,
289  /// return true along with the FrameIndices of the loaded stack slot and the
290  /// machine mem operands containing the reference.
291  /// If not, return false. Unlike isLoadFromStackSlot, this returns true for
292  /// any instructions that loads from the stack. This is just a hint, as some
293  /// cases may be missed.
294  virtual bool hasLoadFromStackSlot(
295  const MachineInstr &MI,
297 
298  /// If the specified machine instruction is a direct
299  /// store to a stack slot, return the virtual or physical register number of
300  /// the source reg along with the FrameIndex of the loaded stack slot. If
301  /// not, return 0. This predicate must return 0 if the instruction has
302  /// any side effects other than storing to the stack slot.
303  virtual unsigned isStoreToStackSlot(const MachineInstr &MI,
304  int &FrameIndex) const {
305  return 0;
306  }
307 
308  /// Optional extension of isStoreToStackSlot that returns the number of
309  /// bytes stored to the stack. This must be implemented if a backend
310  /// supports partial stack slot spills/loads to further disambiguate
311  /// what the store does.
312  virtual unsigned isStoreToStackSlot(const MachineInstr &MI,
313  int &FrameIndex,
314  unsigned &MemBytes) const {
315  MemBytes = 0;
317  }
318 
319  /// Check for post-frame ptr elimination stack locations as well.
320  /// This uses a heuristic, so it isn't reliable for correctness.
321  virtual unsigned isStoreToStackSlotPostFE(const MachineInstr &MI,
322  int &FrameIndex) const {
323  return 0;
324  }
325 
326  /// If the specified machine instruction has a store to a stack slot,
327  /// return true along with the FrameIndices of the loaded stack slot and the
328  /// machine mem operands containing the reference.
329  /// If not, return false. Unlike isStoreToStackSlot,
330  /// this returns true for any instructions that stores to the
331  /// stack. This is just a hint, as some cases may be missed.
332  virtual bool hasStoreToStackSlot(
333  const MachineInstr &MI,
335 
336  /// Return true if the specified machine instruction
337  /// is a copy of one stack slot to another and has no other effect.
338  /// Provide the identity of the two frame indices.
339  virtual bool isStackSlotCopy(const MachineInstr &MI, int &DestFrameIndex,
340  int &SrcFrameIndex) const {
341  return false;
342  }
343 
344  /// Compute the size in bytes and offset within a stack slot of a spilled
345  /// register or subregister.
346  ///
347  /// \param [out] Size in bytes of the spilled value.
348  /// \param [out] Offset in bytes within the stack slot.
349  /// \returns true if both Size and Offset are successfully computed.
350  ///
351  /// Not all subregisters have computable spill slots. For example,
352  /// subregisters registers may not be byte-sized, and a pair of discontiguous
353  /// subregisters has no single offset.
354  ///
355  /// Targets with nontrivial bigendian implementations may need to override
356  /// this, particularly to support spilled vector registers.
357  virtual bool getStackSlotRange(const TargetRegisterClass *RC, unsigned SubIdx,
358  unsigned &Size, unsigned &Offset,
359  const MachineFunction &MF) const;
360 
361  /// Return true if the given instruction is terminator that is unspillable,
362  /// according to isUnspillableTerminatorImpl.
364  return MI->isTerminator() && isUnspillableTerminatorImpl(MI);
365  }
366 
367  /// Returns the size in bytes of the specified MachineInstr, or ~0U
368  /// when this function is not implemented by a target.
369  virtual unsigned getInstSizeInBytes(const MachineInstr &MI) const {
370  return ~0U;
371  }
372 
373  /// Return true if the instruction is as cheap as a move instruction.
374  ///
375  /// Targets for different archs need to override this, and different
376  /// micro-architectures can also be finely tuned inside.
377  virtual bool isAsCheapAsAMove(const MachineInstr &MI) const {
378  return MI.isAsCheapAsAMove();
379  }
380 
381  /// Return true if the instruction should be sunk by MachineSink.
382  ///
383  /// MachineSink determines on its own whether the instruction is safe to sink;
384  /// this gives the target a hook to override the default behavior with regards
385  /// to which instructions should be sunk.
386  virtual bool shouldSink(const MachineInstr &MI) const { return true; }
387 
388  /// Return false if the instruction should not be hoisted by MachineLICM.
389  ///
390  /// MachineLICM determines on its own whether the instruction is safe to
391  /// hoist; this gives the target a hook to extend this assessment and prevent
392  /// an instruction being hoisted from a given loop for target specific
393  /// reasons.
394  virtual bool shouldHoist(const MachineInstr &MI,
395  const MachineLoop *FromLoop) const {
396  return true;
397  }
398 
399  /// Re-issue the specified 'original' instruction at the
400  /// specific location targeting a new destination register.
401  /// The register in Orig->getOperand(0).getReg() will be substituted by
402  /// DestReg:SubIdx. Any existing subreg index is preserved or composed with
403  /// SubIdx.
404  virtual void reMaterialize(MachineBasicBlock &MBB,
406  unsigned SubIdx, const MachineInstr &Orig,
407  const TargetRegisterInfo &TRI) const;
408 
409  /// Clones instruction or the whole instruction bundle \p Orig and
410  /// insert into \p MBB before \p InsertBefore. The target may update operands
411  /// that are required to be unique.
412  ///
413  /// \p Orig must not return true for MachineInstr::isNotDuplicable().
415  MachineBasicBlock::iterator InsertBefore,
416  const MachineInstr &Orig) const;
417 
418  /// This method must be implemented by targets that
419  /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
420  /// may be able to convert a two-address instruction into one or more true
421  /// three-address instructions on demand. This allows the X86 target (for
422  /// example) to convert ADD and SHL instructions into LEA instructions if they
423  /// would require register copies due to two-addressness.
424  ///
425  /// This method returns a null pointer if the transformation cannot be
426  /// performed, otherwise it returns the last new instruction.
427  ///
428  /// If \p LIS is not nullptr, the LiveIntervals info should be updated for
429  /// replacing \p MI with new instructions, even though this function does not
430  /// remove MI.
432  LiveVariables *LV,
433  LiveIntervals *LIS) const {
434  return nullptr;
435  }
436 
437  // This constant can be used as an input value of operand index passed to
438  // the method findCommutedOpIndices() to tell the method that the
439  // corresponding operand index is not pre-defined and that the method
440  // can pick any commutable operand.
441  static const unsigned CommuteAnyOperandIndex = ~0U;
442 
443  /// This method commutes the operands of the given machine instruction MI.
444  ///
445  /// The operands to be commuted are specified by their indices OpIdx1 and
446  /// OpIdx2. OpIdx1 and OpIdx2 arguments may be set to a special value
447  /// 'CommuteAnyOperandIndex', which means that the method is free to choose
448  /// any arbitrarily chosen commutable operand. If both arguments are set to
449  /// 'CommuteAnyOperandIndex' then the method looks for 2 different commutable
450  /// operands; then commutes them if such operands could be found.
451  ///
452  /// If NewMI is false, MI is modified in place and returned; otherwise, a
453  /// new machine instruction is created and returned.
454  ///
455  /// Do not call this method for a non-commutable instruction or
456  /// for non-commuable operands.
457  /// Even though the instruction is commutable, the method may still
458  /// fail to commute the operands, null pointer is returned in such cases.
459  MachineInstr *
460  commuteInstruction(MachineInstr &MI, bool NewMI = false,
461  unsigned OpIdx1 = CommuteAnyOperandIndex,
462  unsigned OpIdx2 = CommuteAnyOperandIndex) const;
463 
464  /// Returns true iff the routine could find two commutable operands in the
465  /// given machine instruction.
466  /// The 'SrcOpIdx1' and 'SrcOpIdx2' are INPUT and OUTPUT arguments.
467  /// If any of the INPUT values is set to the special value
468  /// 'CommuteAnyOperandIndex' then the method arbitrarily picks a commutable
469  /// operand, then returns its index in the corresponding argument.
470  /// If both of INPUT values are set to 'CommuteAnyOperandIndex' then method
471  /// looks for 2 commutable operands.
472  /// If INPUT values refer to some operands of MI, then the method simply
473  /// returns true if the corresponding operands are commutable and returns
474  /// false otherwise.
475  ///
476  /// For example, calling this method this way:
477  /// unsigned Op1 = 1, Op2 = CommuteAnyOperandIndex;
478  /// findCommutedOpIndices(MI, Op1, Op2);
479  /// can be interpreted as a query asking to find an operand that would be
480  /// commutable with the operand#1.
481  virtual bool findCommutedOpIndices(const MachineInstr &MI,
482  unsigned &SrcOpIdx1,
483  unsigned &SrcOpIdx2) const;
484 
485  /// Returns true if the target has a preference on the operands order of
486  /// the given machine instruction. And specify if \p Commute is required to
487  /// get the desired operands order.
488  virtual bool hasCommutePreference(MachineInstr &MI, bool &Commute) const {
489  return false;
490  }
491 
492  /// A pair composed of a register and a sub-register index.
493  /// Used to give some type checking when modeling Reg:SubReg.
494  struct RegSubRegPair {
496  unsigned SubReg;
497 
499  : Reg(Reg), SubReg(SubReg) {}
500 
501  bool operator==(const RegSubRegPair& P) const {
502  return Reg == P.Reg && SubReg == P.SubReg;
503  }
504  bool operator!=(const RegSubRegPair& P) const {
505  return !(*this == P);
506  }
507  };
508 
509  /// A pair composed of a pair of a register and a sub-register index,
510  /// and another sub-register index.
511  /// Used to give some type checking when modeling Reg:SubReg1, SubReg2.
513  unsigned SubIdx;
514 
516  unsigned SubIdx = 0)
518  };
519 
520  /// Build the equivalent inputs of a REG_SEQUENCE for the given \p MI
521  /// and \p DefIdx.
522  /// \p [out] InputRegs of the equivalent REG_SEQUENCE. Each element of
523  /// the list is modeled as <Reg:SubReg, SubIdx>. Operands with the undef
524  /// flag are not added to this list.
525  /// E.g., REG_SEQUENCE %1:sub1, sub0, %2, sub1 would produce
526  /// two elements:
527  /// - %1:sub1, sub0
528  /// - %2<:0>, sub1
529  ///
530  /// \returns true if it is possible to build such an input sequence
531  /// with the pair \p MI, \p DefIdx. False otherwise.
532  ///
533  /// \pre MI.isRegSequence() or MI.isRegSequenceLike().
534  ///
535  /// \note The generic implementation does not provide any support for
536  /// MI.isRegSequenceLike(). In other words, one has to override
537  /// getRegSequenceLikeInputs for target specific instructions.
538  bool
539  getRegSequenceInputs(const MachineInstr &MI, unsigned DefIdx,
540  SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const;
541 
542  /// Build the equivalent inputs of a EXTRACT_SUBREG for the given \p MI
543  /// and \p DefIdx.
544  /// \p [out] InputReg of the equivalent EXTRACT_SUBREG.
545  /// E.g., EXTRACT_SUBREG %1:sub1, sub0, sub1 would produce:
546  /// - %1:sub1, sub0
547  ///
548  /// \returns true if it is possible to build such an input sequence
549  /// with the pair \p MI, \p DefIdx and the operand has no undef flag set.
550  /// False otherwise.
551  ///
552  /// \pre MI.isExtractSubreg() or MI.isExtractSubregLike().
553  ///
554  /// \note The generic implementation does not provide any support for
555  /// MI.isExtractSubregLike(). In other words, one has to override
556  /// getExtractSubregLikeInputs for target specific instructions.
557  bool getExtractSubregInputs(const MachineInstr &MI, unsigned DefIdx,
558  RegSubRegPairAndIdx &InputReg) const;
559 
560  /// Build the equivalent inputs of a INSERT_SUBREG for the given \p MI
561  /// and \p DefIdx.
562  /// \p [out] BaseReg and \p [out] InsertedReg contain
563  /// the equivalent inputs of INSERT_SUBREG.
564  /// E.g., INSERT_SUBREG %0:sub0, %1:sub1, sub3 would produce:
565  /// - BaseReg: %0:sub0
566  /// - InsertedReg: %1:sub1, sub3
567  ///
568  /// \returns true if it is possible to build such an input sequence
569  /// with the pair \p MI, \p DefIdx and the operand has no undef flag set.
570  /// False otherwise.
571  ///
572  /// \pre MI.isInsertSubreg() or MI.isInsertSubregLike().
573  ///
574  /// \note The generic implementation does not provide any support for
575  /// MI.isInsertSubregLike(). In other words, one has to override
576  /// getInsertSubregLikeInputs for target specific instructions.
577  bool getInsertSubregInputs(const MachineInstr &MI, unsigned DefIdx,
578  RegSubRegPair &BaseReg,
579  RegSubRegPairAndIdx &InsertedReg) const;
580 
581  /// Return true if two machine instructions would produce identical values.
582  /// By default, this is only true when the two instructions
583  /// are deemed identical except for defs. If this function is called when the
584  /// IR is still in SSA form, the caller can pass the MachineRegisterInfo for
585  /// aggressive checks.
586  virtual bool produceSameValue(const MachineInstr &MI0,
587  const MachineInstr &MI1,
588  const MachineRegisterInfo *MRI = nullptr) const;
589 
590  /// \returns true if a branch from an instruction with opcode \p BranchOpc
591  /// bytes is capable of jumping to a position \p BrOffset bytes away.
592  virtual bool isBranchOffsetInRange(unsigned BranchOpc,
593  int64_t BrOffset) const {
594  llvm_unreachable("target did not implement");
595  }
596 
597  /// \returns The block that branch instruction \p MI jumps to.
599  llvm_unreachable("target did not implement");
600  }
601 
602  /// Insert an unconditional indirect branch at the end of \p MBB to \p
603  /// NewDestBB. Optionally, insert the clobbered register restoring in \p
604  /// RestoreBB. \p BrOffset indicates the offset of \p NewDestBB relative to
605  /// the offset of the position to insert the new branch.
607  MachineBasicBlock &NewDestBB,
608  MachineBasicBlock &RestoreBB,
609  const DebugLoc &DL, int64_t BrOffset = 0,
610  RegScavenger *RS = nullptr) const {
611  llvm_unreachable("target did not implement");
612  }
613 
614  /// Analyze the branching code at the end of MBB, returning
615  /// true if it cannot be understood (e.g. it's a switch dispatch or isn't
616  /// implemented for a target). Upon success, this returns false and returns
617  /// with the following information in various cases:
618  ///
619  /// 1. If this block ends with no branches (it just falls through to its succ)
620  /// just return false, leaving TBB/FBB null.
621  /// 2. If this block ends with only an unconditional branch, it sets TBB to be
622  /// the destination block.
623  /// 3. If this block ends with a conditional branch and it falls through to a
624  /// successor block, it sets TBB to be the branch destination block and a
625  /// list of operands that evaluate the condition. These operands can be
626  /// passed to other TargetInstrInfo methods to create new branches.
627  /// 4. If this block ends with a conditional branch followed by an
628  /// unconditional branch, it returns the 'true' destination in TBB, the
629  /// 'false' destination in FBB, and a list of operands that evaluate the
630  /// condition. These operands can be passed to other TargetInstrInfo
631  /// methods to create new branches.
632  ///
633  /// Note that removeBranch and insertBranch must be implemented to support
634  /// cases where this method returns success.
635  ///
636  /// If AllowModify is true, then this routine is allowed to modify the basic
637  /// block (e.g. delete instructions after the unconditional branch).
638  ///
639  /// The CFG information in MBB.Predecessors and MBB.Successors must be valid
640  /// before calling this function.
642  MachineBasicBlock *&FBB,
644  bool AllowModify = false) const {
645  return true;
646  }
647 
648  /// Represents a predicate at the MachineFunction level. The control flow a
649  /// MachineBranchPredicate represents is:
650  ///
651  /// Reg = LHS `Predicate` RHS == ConditionDef
652  /// if Reg then goto TrueDest else goto FalseDest
653  ///
656  PRED_EQ, // True if two values are equal
657  PRED_NE, // True if two values are not equal
658  PRED_INVALID // Sentinel value
659  };
660 
667 
668  /// SingleUseCondition is true if ConditionDef is dead except for the
669  /// branch(es) at the end of the basic block.
670  ///
671  bool SingleUseCondition = false;
672 
673  explicit MachineBranchPredicate() = default;
674  };
675 
676  /// Analyze the branching code at the end of MBB and parse it into the
677  /// MachineBranchPredicate structure if possible. Returns false on success
678  /// and true on failure.
679  ///
680  /// If AllowModify is true, then this routine is allowed to modify the basic
681  /// block (e.g. delete instructions after the unconditional branch).
682  ///
685  bool AllowModify = false) const {
686  return true;
687  }
688 
689  /// Remove the branching code at the end of the specific MBB.
690  /// This is only invoked in cases where analyzeBranch returns success. It
691  /// returns the number of instructions that were removed.
692  /// If \p BytesRemoved is non-null, report the change in code size from the
693  /// removed instructions.
694  virtual unsigned removeBranch(MachineBasicBlock &MBB,
695  int *BytesRemoved = nullptr) const {
696  llvm_unreachable("Target didn't implement TargetInstrInfo::removeBranch!");
697  }
698 
699  /// Insert branch code into the end of the specified MachineBasicBlock. The
700  /// operands to this method are the same as those returned by analyzeBranch.
701  /// This is only invoked in cases where analyzeBranch returns success. It
702  /// returns the number of instructions inserted. If \p BytesAdded is non-null,
703  /// report the change in code size from the added instructions.
704  ///
705  /// It is also invoked by tail merging to add unconditional branches in
706  /// cases where analyzeBranch doesn't apply because there was no original
707  /// branch to analyze. At least this much must be implemented, else tail
708  /// merging needs to be disabled.
709  ///
710  /// The CFG information in MBB.Predecessors and MBB.Successors must be valid
711  /// before calling this function.
713  MachineBasicBlock *FBB,
715  const DebugLoc &DL,
716  int *BytesAdded = nullptr) const {
717  llvm_unreachable("Target didn't implement TargetInstrInfo::insertBranch!");
718  }
719 
721  MachineBasicBlock *DestBB,
722  const DebugLoc &DL,
723  int *BytesAdded = nullptr) const {
724  return insertBranch(MBB, DestBB, nullptr, ArrayRef<MachineOperand>(), DL,
725  BytesAdded);
726  }
727 
728  /// Object returned by analyzeLoopForPipelining. Allows software pipelining
729  /// implementations to query attributes of the loop being pipelined and to
730  /// apply target-specific updates to the loop once pipelining is complete.
732  public:
733  virtual ~PipelinerLoopInfo();
734  /// Return true if the given instruction should not be pipelined and should
735  /// be ignored. An example could be a loop comparison, or induction variable
736  /// update with no users being pipelined.
737  virtual bool shouldIgnoreForPipelining(const MachineInstr *MI) const = 0;
738 
739  /// Return true if the proposed schedule should used. Otherwise return
740  /// false to not pipeline the loop. This function should be used to ensure
741  /// that pipelined loops meet target-specific quality heuristics.
742  virtual bool shouldUseSchedule(SwingSchedulerDAG &SSD, SMSchedule &SMS) {
743  return true;
744  }
745 
746  /// Create a condition to determine if the trip count of the loop is greater
747  /// than TC, where TC is always one more than for the previous prologue or
748  /// 0 if this is being called for the outermost prologue.
749  ///
750  /// If the trip count is statically known to be greater than TC, return
751  /// true. If the trip count is statically known to be not greater than TC,
752  /// return false. Otherwise return nullopt and fill out Cond with the test
753  /// condition.
754  ///
755  /// Note: This hook is guaranteed to be called from the innermost to the
756  /// outermost prologue of the loop being software pipelined.
757  virtual Optional<bool>
760 
761  /// Modify the loop such that the trip count is
762  /// OriginalTC + TripCountAdjust.
763  virtual void adjustTripCount(int TripCountAdjust) = 0;
764 
765  /// Called when the loop's preheader has been modified to NewPreheader.
766  virtual void setPreheader(MachineBasicBlock *NewPreheader) = 0;
767 
768  /// Called when the loop is being removed. Any instructions in the preheader
769  /// should be removed.
770  ///
771  /// Once this function is called, no other functions on this object are
772  /// valid; the loop has been removed.
773  virtual void disposed() = 0;
774  };
775 
776  /// Analyze loop L, which must be a single-basic-block loop, and if the
777  /// conditions can be understood enough produce a PipelinerLoopInfo object.
778  virtual std::unique_ptr<PipelinerLoopInfo>
780  return nullptr;
781  }
782 
783  /// Analyze the loop code, return true if it cannot be understood. Upon
784  /// success, this function returns false and returns information about the
785  /// induction variable and compare instruction used at the end.
786  virtual bool analyzeLoop(MachineLoop &L, MachineInstr *&IndVarInst,
787  MachineInstr *&CmpInst) const {
788  return true;
789  }
790 
791  /// Generate code to reduce the loop iteration by one and check if the loop
792  /// is finished. Return the value/register of the new loop count. We need
793  /// this function when peeling off one or more iterations of a loop. This
794  /// function assumes the nth iteration is peeled first.
796  MachineBasicBlock &PreHeader,
797  MachineInstr *IndVar, MachineInstr &Cmp,
800  unsigned Iter, unsigned MaxIter) const {
801  llvm_unreachable("Target didn't implement ReduceLoopCount");
802  }
803 
804  /// Delete the instruction OldInst and everything after it, replacing it with
805  /// an unconditional branch to NewDest. This is used by the tail merging pass.
807  MachineBasicBlock *NewDest) const;
808 
809  /// Return true if it's legal to split the given basic
810  /// block at the specified instruction (i.e. instruction would be the start
811  /// of a new basic block).
814  return true;
815  }
816 
817  /// Return true if it's profitable to predicate
818  /// instructions with accumulated instruction latency of "NumCycles"
819  /// of the specified basic block, where the probability of the instructions
820  /// being executed is given by Probability, and Confidence is a measure
821  /// of our confidence that it will be properly predicted.
822  virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
823  unsigned ExtraPredCycles,
824  BranchProbability Probability) const {
825  return false;
826  }
827 
828  /// Second variant of isProfitableToIfCvt. This one
829  /// checks for the case where two basic blocks from true and false path
830  /// of a if-then-else (diamond) are predicated on mutually exclusive
831  /// predicates, where the probability of the true path being taken is given
832  /// by Probability, and Confidence is a measure of our confidence that it
833  /// will be properly predicted.
834  virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumTCycles,
835  unsigned ExtraTCycles,
836  MachineBasicBlock &FMBB, unsigned NumFCycles,
837  unsigned ExtraFCycles,
838  BranchProbability Probability) const {
839  return false;
840  }
841 
842  /// Return true if it's profitable for if-converter to duplicate instructions
843  /// of specified accumulated instruction latencies in the specified MBB to
844  /// enable if-conversion.
845  /// The probability of the instructions being executed is given by
846  /// Probability, and Confidence is a measure of our confidence that it
847  /// will be properly predicted.
849  unsigned NumCycles,
850  BranchProbability Probability) const {
851  return false;
852  }
853 
854  /// Return the increase in code size needed to predicate a contiguous run of
855  /// NumInsts instructions.
857  unsigned NumInsts) const {
858  return 0;
859  }
860 
861  /// Return an estimate for the code size reduction (in bytes) which will be
862  /// caused by removing the given branch instruction during if-conversion.
863  virtual unsigned predictBranchSizeForIfCvt(MachineInstr &MI) const {
864  return getInstSizeInBytes(MI);
865  }
866 
867  /// Return true if it's profitable to unpredicate
868  /// one side of a 'diamond', i.e. two sides of if-else predicated on mutually
869  /// exclusive predicates.
870  /// e.g.
871  /// subeq r0, r1, #1
872  /// addne r0, r1, #1
873  /// =>
874  /// sub r0, r1, #1
875  /// addne r0, r1, #1
876  ///
877  /// This may be profitable is conditional instructions are always executed.
879  MachineBasicBlock &FMBB) const {
880  return false;
881  }
882 
883  /// Return true if it is possible to insert a select
884  /// instruction that chooses between TrueReg and FalseReg based on the
885  /// condition code in Cond.
886  ///
887  /// When successful, also return the latency in cycles from TrueReg,
888  /// FalseReg, and Cond to the destination register. In most cases, a select
889  /// instruction will be 1 cycle, so CondCycles = TrueCycles = FalseCycles = 1
890  ///
891  /// Some x86 implementations have 2-cycle cmov instructions.
892  ///
893  /// @param MBB Block where select instruction would be inserted.
894  /// @param Cond Condition returned by analyzeBranch.
895  /// @param DstReg Virtual dest register that the result should write to.
896  /// @param TrueReg Virtual register to select when Cond is true.
897  /// @param FalseReg Virtual register to select when Cond is false.
898  /// @param CondCycles Latency from Cond+Branch to select output.
899  /// @param TrueCycles Latency from TrueReg to select output.
900  /// @param FalseCycles Latency from FalseReg to select output.
901  virtual bool canInsertSelect(const MachineBasicBlock &MBB,
903  Register TrueReg, Register FalseReg,
904  int &CondCycles, int &TrueCycles,
905  int &FalseCycles) const {
906  return false;
907  }
908 
909  /// Insert a select instruction into MBB before I that will copy TrueReg to
910  /// DstReg when Cond is true, and FalseReg to DstReg when Cond is false.
911  ///
912  /// This function can only be called after canInsertSelect() returned true.
913  /// The condition in Cond comes from analyzeBranch, and it can be assumed
914  /// that the same flags or registers required by Cond are available at the
915  /// insertion point.
916  ///
917  /// @param MBB Block where select instruction should be inserted.
918  /// @param I Insertion point.
919  /// @param DL Source location for debugging.
920  /// @param DstReg Virtual register to be defined by select instruction.
921  /// @param Cond Condition as computed by analyzeBranch.
922  /// @param TrueReg Virtual register to copy when Cond is true.
923  /// @param FalseReg Virtual register to copy when Cons is false.
927  Register TrueReg, Register FalseReg) const {
928  llvm_unreachable("Target didn't implement TargetInstrInfo::insertSelect!");
929  }
930 
931  /// Analyze the given select instruction, returning true if
932  /// it cannot be understood. It is assumed that MI->isSelect() is true.
933  ///
934  /// When successful, return the controlling condition and the operands that
935  /// determine the true and false result values.
936  ///
937  /// Result = SELECT Cond, TrueOp, FalseOp
938  ///
939  /// Some targets can optimize select instructions, for example by predicating
940  /// the instruction defining one of the operands. Such targets should set
941  /// Optimizable.
942  ///
943  /// @param MI Select instruction to analyze.
944  /// @param Cond Condition controlling the select.
945  /// @param TrueOp Operand number of the value selected when Cond is true.
946  /// @param FalseOp Operand number of the value selected when Cond is false.
947  /// @param Optimizable Returned as true if MI is optimizable.
948  /// @returns False on success.
949  virtual bool analyzeSelect(const MachineInstr &MI,
951  unsigned &TrueOp, unsigned &FalseOp,
952  bool &Optimizable) const {
953  assert(MI.getDesc().isSelect() && "MI must be a select instruction");
954  return true;
955  }
956 
957  /// Given a select instruction that was understood by
958  /// analyzeSelect and returned Optimizable = true, attempt to optimize MI by
959  /// merging it with one of its operands. Returns NULL on failure.
960  ///
961  /// When successful, returns the new select instruction. The client is
962  /// responsible for deleting MI.
963  ///
964  /// If both sides of the select can be optimized, PreferFalse is used to pick
965  /// a side.
966  ///
967  /// @param MI Optimizable select instruction.
968  /// @param NewMIs Set that record all MIs in the basic block up to \p
969  /// MI. Has to be updated with any newly created MI or deleted ones.
970  /// @param PreferFalse Try to optimize FalseOp instead of TrueOp.
971  /// @returns Optimized instruction or NULL.
974  bool PreferFalse = false) const {
975  // This function must be implemented if Optimizable is ever set.
976  llvm_unreachable("Target must implement TargetInstrInfo::optimizeSelect!");
977  }
978 
979  /// Emit instructions to copy a pair of physical registers.
980  ///
981  /// This function should support copies within any legal register class as
982  /// well as any cross-class copies created during instruction selection.
983  ///
984  /// The source and destination registers may overlap, which may require a
985  /// careful implementation when multiple copy instructions are required for
986  /// large registers. See for example the ARM target.
989  MCRegister DestReg, MCRegister SrcReg,
990  bool KillSrc) const {
991  llvm_unreachable("Target didn't implement TargetInstrInfo::copyPhysReg!");
992  }
993 
994  /// Allow targets to tell MachineVerifier whether a specific register
995  /// MachineOperand can be used as part of PC-relative addressing.
996  /// PC-relative addressing modes in many CISC architectures contain
997  /// (non-PC) registers as offsets or scaling values, which inherently
998  /// tags the corresponding MachineOperand with OPERAND_PCREL.
999  ///
1000  /// @param MO The MachineOperand in question. MO.isReg() should always
1001  /// be true.
1002  /// @return Whether this operand is allowed to be used PC-relatively.
1003  virtual bool isPCRelRegisterOperandLegal(const MachineOperand &MO) const {
1004  return false;
1005  }
1006 
1007 protected:
1008  /// Target-dependent implementation for IsCopyInstr.
1009  /// If the specific machine instruction is a instruction that moves/copies
1010  /// value from one register to another register return destination and source
1011  /// registers as machine operands.
1012  virtual Optional<DestSourcePair>
1014  return None;
1015  }
1016 
1017  /// Return true if the given terminator MI is not expected to spill. This
1018  /// sets the live interval as not spillable and adjusts phi node lowering to
1019  /// not introduce copies after the terminator. Use with care, these are
1020  /// currently used for hardware loop intrinsics in very controlled situations,
1021  /// created prior to registry allocation in loops that only have single phi
1022  /// users for the terminators value. They may run out of registers if not used
1023  /// carefully.
1024  virtual bool isUnspillableTerminatorImpl(const MachineInstr *MI) const {
1025  return false;
1026  }
1027 
1028 public:
1029  /// If the specific machine instruction is a instruction that moves/copies
1030  /// value from one register to another register return destination and source
1031  /// registers as machine operands.
1032  /// For COPY-instruction the method naturally returns destination and source
1033  /// registers as machine operands, for all other instructions the method calls
1034  /// target-dependent implementation.
1036  if (MI.isCopy()) {
1037  return DestSourcePair{MI.getOperand(0), MI.getOperand(1)};
1038  }
1039  return isCopyInstrImpl(MI);
1040  }
1041 
1042  /// If the specific machine instruction is an instruction that adds an
1043  /// immediate value and a physical register, and stores the result in
1044  /// the given physical register \c Reg, return a pair of the source
1045  /// register and the offset which has been added.
1047  Register Reg) const {
1048  return None;
1049  }
1050 
1051  /// Returns true if MI is an instruction that defines Reg to have a constant
1052  /// value and the value is recorded in ImmVal. The ImmVal is a result that
1053  /// should be interpreted as modulo size of Reg.
1055  const Register Reg,
1056  int64_t &ImmVal) const {
1057  return false;
1058  }
1059 
1060  /// Store the specified register of the given register class to the specified
1061  /// stack frame index. The store instruction is to be added to the given
1062  /// machine basic block before the specified machine instruction. If isKill
1063  /// is true, the register operand is the last use and must be marked kill.
1066  Register SrcReg, bool isKill, int FrameIndex,
1067  const TargetRegisterClass *RC,
1068  const TargetRegisterInfo *TRI) const {
1069  llvm_unreachable("Target didn't implement "
1070  "TargetInstrInfo::storeRegToStackSlot!");
1071  }
1072 
1073  /// Load the specified register of the given register class from the specified
1074  /// stack frame index. The load instruction is to be added to the given
1075  /// machine basic block before the specified machine instruction.
1078  Register DestReg, int FrameIndex,
1079  const TargetRegisterClass *RC,
1080  const TargetRegisterInfo *TRI) const {
1081  llvm_unreachable("Target didn't implement "
1082  "TargetInstrInfo::loadRegFromStackSlot!");
1083  }
1084 
1085  /// This function is called for all pseudo instructions
1086  /// that remain after register allocation. Many pseudo instructions are
1087  /// created to help register allocation. This is the place to convert them
1088  /// into real instructions. The target can edit MI in place, or it can insert
1089  /// new instructions and erase MI. The function should return true if
1090  /// anything was changed.
1091  virtual bool expandPostRAPseudo(MachineInstr &MI) const { return false; }
1092 
1093  /// Check whether the target can fold a load that feeds a subreg operand
1094  /// (or a subreg operand that feeds a store).
1095  /// For example, X86 may want to return true if it can fold
1096  /// movl (%esp), %eax
1097  /// subb, %al, ...
1098  /// Into:
1099  /// subb (%esp), ...
1100  ///
1101  /// Ideally, we'd like the target implementation of foldMemoryOperand() to
1102  /// reject subregs - but since this behavior used to be enforced in the
1103  /// target-independent code, moving this responsibility to the targets
1104  /// has the potential of causing nasty silent breakage in out-of-tree targets.
1105  virtual bool isSubregFoldable() const { return false; }
1106 
1107  /// For a patchpoint, stackmap, or statepoint intrinsic, return the range of
1108  /// operands which can't be folded into stack references. Operands outside
1109  /// of the range are most likely foldable but it is not guaranteed.
1110  /// These instructions are unique in that stack references for some operands
1111  /// have the same execution cost (e.g. none) as the unfolded register forms.
1112  /// The ranged return is guaranteed to include all operands which can't be
1113  /// folded at zero cost.
1114  virtual std::pair<unsigned, unsigned>
1116 
1117  /// Attempt to fold a load or store of the specified stack
1118  /// slot into the specified machine instruction for the specified operand(s).
1119  /// If this is possible, a new instruction is returned with the specified
1120  /// operand folded, otherwise NULL is returned.
1121  /// The new instruction is inserted before MI, and the client is responsible
1122  /// for removing the old instruction.
1123  /// If VRM is passed, the assigned physregs can be inspected by target to
1124  /// decide on using an opcode (note that those assignments can still change).
1126  int FI,
1127  LiveIntervals *LIS = nullptr,
1128  VirtRegMap *VRM = nullptr) const;
1129 
1130  /// Same as the previous version except it allows folding of any load and
1131  /// store from / to any address, not just from a specific stack slot.
1133  MachineInstr &LoadMI,
1134  LiveIntervals *LIS = nullptr) const;
1135 
1136  /// Return true when there is potentially a faster code sequence
1137  /// for an instruction chain ending in \p Root. All potential patterns are
1138  /// returned in the \p Pattern vector. Pattern should be sorted in priority
1139  /// order since the pattern evaluator stops checking as soon as it finds a
1140  /// faster sequence.
1141  /// \param Root - Instruction that could be combined with one of its operands
1142  /// \param Patterns - Vector of possible combination patterns
1143  virtual bool
1146  bool DoRegPressureReduce) const;
1147 
1148  /// Return true if target supports reassociation of instructions in machine
1149  /// combiner pass to reduce register pressure for a given BB.
1150  virtual bool
1152  RegisterClassInfo *RegClassInfo) const {
1153  return false;
1154  }
1155 
1156  /// Fix up the placeholder we may add in genAlternativeCodeSequence().
1157  virtual void
1159  SmallVectorImpl<MachineInstr *> &InsInstrs) const {}
1160 
1161  /// Return true when a code sequence can improve throughput. It
1162  /// should be called only for instructions in loops.
1163  /// \param Pattern - combiner pattern
1165 
1166  /// Return true if the input \P Inst is part of a chain of dependent ops
1167  /// that are suitable for reassociation, otherwise return false.
1168  /// If the instruction's operands must be commuted to have a previous
1169  /// instruction of the same type define the first source operand, \P Commuted
1170  /// will be set to true.
1171  bool isReassociationCandidate(const MachineInstr &Inst, bool &Commuted) const;
1172 
1173  /// Return true when \P Inst is both associative and commutative.
1174  virtual bool isAssociativeAndCommutative(const MachineInstr &Inst) const {
1175  return false;
1176  }
1177 
1178  /// Return true when \P Inst has reassociable operands in the same \P MBB.
1179  virtual bool hasReassociableOperands(const MachineInstr &Inst,
1180  const MachineBasicBlock *MBB) const;
1181 
1182  /// Return true when \P Inst has reassociable sibling.
1183  bool hasReassociableSibling(const MachineInstr &Inst, bool &Commuted) const;
1184 
1185  /// When getMachineCombinerPatterns() finds patterns, this function generates
1186  /// the instructions that could replace the original code sequence. The client
1187  /// has to decide whether the actual replacement is beneficial or not.
1188  /// \param Root - Instruction that could be combined with one of its operands
1189  /// \param Pattern - Combination pattern for Root
1190  /// \param InsInstrs - Vector of new instructions that implement P
1191  /// \param DelInstrs - Old instructions, including Root, that could be
1192  /// replaced by InsInstr
1193  /// \param InstIdxForVirtReg - map of virtual register to instruction in
1194  /// InsInstr that defines it
1195  virtual void genAlternativeCodeSequence(
1199  DenseMap<unsigned, unsigned> &InstIdxForVirtReg) const;
1200 
1201  /// Attempt to reassociate \P Root and \P Prev according to \P Pattern to
1202  /// reduce critical path length.
1203  void reassociateOps(MachineInstr &Root, MachineInstr &Prev,
1207  DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const;
1208 
1209  /// The limit on resource length extension we accept in MachineCombiner Pass.
1210  virtual int getExtendResourceLenLimit() const { return 0; }
1211 
1212  /// This is an architecture-specific helper function of reassociateOps.
1213  /// Set special operand attributes for new instructions after reassociation.
1214  virtual void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2,
1215  MachineInstr &NewMI1,
1216  MachineInstr &NewMI2) const {}
1217 
1218  /// Return true when a target supports MachineCombiner.
1219  virtual bool useMachineCombiner() const { return false; }
1220 
1221  /// Return true if the given SDNode can be copied during scheduling
1222  /// even if it has glue.
1223  virtual bool canCopyGluedNodeDuringSchedule(SDNode *N) const { return false; }
1224 
1225 protected:
1226  /// Target-dependent implementation for foldMemoryOperand.
1227  /// Target-independent code in foldMemoryOperand will
1228  /// take care of adding a MachineMemOperand to the newly created instruction.
1229  /// The instruction and any auxiliary instructions necessary will be inserted
1230  /// at InsertPt.
1231  virtual MachineInstr *
1233  ArrayRef<unsigned> Ops,
1235  LiveIntervals *LIS = nullptr,
1236  VirtRegMap *VRM = nullptr) const {
1237  return nullptr;
1238  }
1239 
1240  /// Target-dependent implementation for foldMemoryOperand.
1241  /// Target-independent code in foldMemoryOperand will
1242  /// take care of adding a MachineMemOperand to the newly created instruction.
1243  /// The instruction and any auxiliary instructions necessary will be inserted
1244  /// at InsertPt.
1247  MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI,
1248  LiveIntervals *LIS = nullptr) const {
1249  return nullptr;
1250  }
1251 
1252  /// Target-dependent implementation of getRegSequenceInputs.
1253  ///
1254  /// \returns true if it is possible to build the equivalent
1255  /// REG_SEQUENCE inputs with the pair \p MI, \p DefIdx. False otherwise.
1256  ///
1257  /// \pre MI.isRegSequenceLike().
1258  ///
1259  /// \see TargetInstrInfo::getRegSequenceInputs.
1261  const MachineInstr &MI, unsigned DefIdx,
1262  SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const {
1263  return false;
1264  }
1265 
1266  /// Target-dependent implementation of getExtractSubregInputs.
1267  ///
1268  /// \returns true if it is possible to build the equivalent
1269  /// EXTRACT_SUBREG inputs with the pair \p MI, \p DefIdx. False otherwise.
1270  ///
1271  /// \pre MI.isExtractSubregLike().
1272  ///
1273  /// \see TargetInstrInfo::getExtractSubregInputs.
1275  unsigned DefIdx,
1276  RegSubRegPairAndIdx &InputReg) const {
1277  return false;
1278  }
1279 
1280  /// Target-dependent implementation of getInsertSubregInputs.
1281  ///
1282  /// \returns true if it is possible to build the equivalent
1283  /// INSERT_SUBREG inputs with the pair \p MI, \p DefIdx. False otherwise.
1284  ///
1285  /// \pre MI.isInsertSubregLike().
1286  ///
1287  /// \see TargetInstrInfo::getInsertSubregInputs.
1288  virtual bool
1289  getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
1290  RegSubRegPair &BaseReg,
1291  RegSubRegPairAndIdx &InsertedReg) const {
1292  return false;
1293  }
1294 
1295 public:
1296  /// unfoldMemoryOperand - Separate a single instruction which folded a load or
1297  /// a store or a load and a store into two or more instruction. If this is
1298  /// possible, returns true as well as the new instructions by reference.
1299  virtual bool
1301  bool UnfoldLoad, bool UnfoldStore,
1302  SmallVectorImpl<MachineInstr *> &NewMIs) const {
1303  return false;
1304  }
1305 
1307  SmallVectorImpl<SDNode *> &NewNodes) const {
1308  return false;
1309  }
1310 
1311  /// Returns the opcode of the would be new
1312  /// instruction after load / store are unfolded from an instruction of the
1313  /// specified opcode. It returns zero if the specified unfolding is not
1314  /// possible. If LoadRegIndex is non-null, it is filled in with the operand
1315  /// index of the operand which will hold the register holding the loaded
1316  /// value.
1317  virtual unsigned
1318  getOpcodeAfterMemoryUnfold(unsigned Opc, bool UnfoldLoad, bool UnfoldStore,
1319  unsigned *LoadRegIndex = nullptr) const {
1320  return 0;
1321  }
1322 
1323  /// This is used by the pre-regalloc scheduler to determine if two loads are
1324  /// loading from the same base address. It should only return true if the base
1325  /// pointers are the same and the only differences between the two addresses
1326  /// are the offset. It also returns the offsets by reference.
1327  virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
1328  int64_t &Offset1,
1329  int64_t &Offset2) const {
1330  return false;
1331  }
1332 
1333  /// This is a used by the pre-regalloc scheduler to determine (in conjunction
1334  /// with areLoadsFromSameBasePtr) if two loads should be scheduled together.
1335  /// On some targets if two loads are loading from
1336  /// addresses in the same cache line, it's better if they are scheduled
1337  /// together. This function takes two integers that represent the load offsets
1338  /// from the common base address. It returns true if it decides it's desirable
1339  /// to schedule the two loads together. "NumLoads" is the number of loads that
1340  /// have already been scheduled after Load1.
1341  virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
1342  int64_t Offset1, int64_t Offset2,
1343  unsigned NumLoads) const {
1344  return false;
1345  }
1346 
1347  /// Get the base operand and byte offset of an instruction that reads/writes
1348  /// memory. This is a convenience function for callers that are only prepared
1349  /// to handle a single base operand.
1351  const MachineOperand *&BaseOp, int64_t &Offset,
1352  bool &OffsetIsScalable,
1353  const TargetRegisterInfo *TRI) const;
1354 
1355  /// Get zero or more base operands and the byte offset of an instruction that
1356  /// reads/writes memory. Note that there may be zero base operands if the
1357  /// instruction accesses a constant address.
1358  /// It returns false if MI does not read/write memory.
1359  /// It returns false if base operands and offset could not be determined.
1360  /// It is not guaranteed to always recognize base operands and offsets in all
1361  /// cases.
1364  int64_t &Offset, bool &OffsetIsScalable, unsigned &Width,
1365  const TargetRegisterInfo *TRI) const {
1366  return false;
1367  }
1368 
1369  /// Return true if the instruction contains a base register and offset. If
1370  /// true, the function also sets the operand position in the instruction
1371  /// for the base register and offset.
1373  unsigned &BasePos,
1374  unsigned &OffsetPos) const {
1375  return false;
1376  }
1377 
1378  /// Target dependent implementation to get the values constituting the address
1379  /// MachineInstr that is accessing memory. These values are returned as a
1380  /// struct ExtAddrMode which contains all relevant information to make up the
1381  /// address.
1382  virtual Optional<ExtAddrMode>
1384  const TargetRegisterInfo *TRI) const {
1385  return None;
1386  }
1387 
1388  /// Returns true if MI's Def is NullValueReg, and the MI
1389  /// does not change the Zero value. i.e. cases such as rax = shr rax, X where
1390  /// NullValueReg = rax. Note that if the NullValueReg is non-zero, this
1391  /// function can return true even if becomes zero. Specifically cases such as
1392  /// NullValueReg = shl NullValueReg, 63.
1394  const Register NullValueReg,
1395  const TargetRegisterInfo *TRI) const {
1396  return false;
1397  }
1398 
1399  /// If the instruction is an increment of a constant value, return the amount.
1400  virtual bool getIncrementValue(const MachineInstr &MI, int &Value) const {
1401  return false;
1402  }
1403 
1404  /// Returns true if the two given memory operations should be scheduled
1405  /// adjacent. Note that you have to add:
1406  /// DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
1407  /// or
1408  /// DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
1409  /// to TargetPassConfig::createMachineScheduler() to have an effect.
1410  ///
1411  /// \p BaseOps1 and \p BaseOps2 are memory operands of two memory operations.
1412  /// \p NumLoads is the number of loads that will be in the cluster if this
1413  /// hook returns true.
1414  /// \p NumBytes is the number of bytes that will be loaded from all the
1415  /// clustered loads if this hook returns true.
1418  unsigned NumLoads, unsigned NumBytes) const {
1419  llvm_unreachable("target did not implement shouldClusterMemOps()");
1420  }
1421 
1422  /// Reverses the branch condition of the specified condition list,
1423  /// returning false on success and true if it cannot be reversed.
1424  virtual bool
1426  return true;
1427  }
1428 
1429  /// Insert a noop into the instruction stream at the specified point.
1430  virtual void insertNoop(MachineBasicBlock &MBB,
1432 
1433  /// Insert noops into the instruction stream at the specified point.
1434  virtual void insertNoops(MachineBasicBlock &MBB,
1436  unsigned Quantity) const;
1437 
1438  /// Return the noop instruction to use for a noop.
1439  virtual MCInst getNop() const;
1440 
1441  /// Return true for post-incremented instructions.
1442  virtual bool isPostIncrement(const MachineInstr &MI) const { return false; }
1443 
1444  /// Returns true if the instruction is already predicated.
1445  virtual bool isPredicated(const MachineInstr &MI) const { return false; }
1446 
1447  // Returns a MIRPrinter comment for this machine operand.
1448  virtual std::string
1450  unsigned OpIdx, const TargetRegisterInfo *TRI) const;
1451 
1452  /// Returns true if the instruction is a
1453  /// terminator instruction that has not been predicated.
1454  bool isUnpredicatedTerminator(const MachineInstr &MI) const;
1455 
1456  /// Returns true if MI is an unconditional tail call.
1457  virtual bool isUnconditionalTailCall(const MachineInstr &MI) const {
1458  return false;
1459  }
1460 
1461  /// Returns true if the tail call can be made conditional on BranchCond.
1463  const MachineInstr &TailCall) const {
1464  return false;
1465  }
1466 
1467  /// Replace the conditional branch in MBB with a conditional tail call.
1470  const MachineInstr &TailCall) const {
1471  llvm_unreachable("Target didn't implement replaceBranchWithTailCall!");
1472  }
1473 
1474  /// Convert the instruction into a predicated instruction.
1475  /// It returns true if the operation was successful.
1476  virtual bool PredicateInstruction(MachineInstr &MI,
1477  ArrayRef<MachineOperand> Pred) const;
1478 
1479  /// Returns true if the first specified predicate
1480  /// subsumes the second, e.g. GE subsumes GT.
1482  ArrayRef<MachineOperand> Pred2) const {
1483  return false;
1484  }
1485 
1486  /// If the specified instruction defines any predicate
1487  /// or condition code register(s) used for predication, returns true as well
1488  /// as the definition predicate(s) by reference.
1489  /// SkipDead should be set to false at any point that dead
1490  /// predicate instructions should be considered as being defined.
1491  /// A dead predicate instruction is one that is guaranteed to be removed
1492  /// after a call to PredicateInstruction.
1494  std::vector<MachineOperand> &Pred,
1495  bool SkipDead) const {
1496  return false;
1497  }
1498 
1499  /// Return true if the specified instruction can be predicated.
1500  /// By default, this returns true for every instruction with a
1501  /// PredicateOperand.
1502  virtual bool isPredicable(const MachineInstr &MI) const {
1503  return MI.getDesc().isPredicable();
1504  }
1505 
1506  /// Return true if it's safe to move a machine
1507  /// instruction that defines the specified register class.
1508  virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
1509  return true;
1510  }
1511 
1512  /// Test if the given instruction should be considered a scheduling boundary.
1513  /// This primarily includes labels and terminators.
1514  virtual bool isSchedulingBoundary(const MachineInstr &MI,
1515  const MachineBasicBlock *MBB,
1516  const MachineFunction &MF) const;
1517 
1518  /// Measure the specified inline asm to determine an approximation of its
1519  /// length.
1520  virtual unsigned getInlineAsmLength(
1521  const char *Str, const MCAsmInfo &MAI,
1522  const TargetSubtargetInfo *STI = nullptr) const;
1523 
1524  /// Allocate and return a hazard recognizer to use for this target when
1525  /// scheduling the machine instructions before register allocation.
1526  virtual ScheduleHazardRecognizer *
1528  const ScheduleDAG *DAG) const;
1529 
1530  /// Allocate and return a hazard recognizer to use for this target when
1531  /// scheduling the machine instructions before register allocation.
1532  virtual ScheduleHazardRecognizer *
1534  const ScheduleDAGMI *DAG) const;
1535 
1536  /// Allocate and return a hazard recognizer to use for this target when
1537  /// scheduling the machine instructions after register allocation.
1538  virtual ScheduleHazardRecognizer *
1540  const ScheduleDAG *DAG) const;
1541 
1542  /// Allocate and return a hazard recognizer to use for by non-scheduling
1543  /// passes.
1544  virtual ScheduleHazardRecognizer *
1546  return nullptr;
1547  }
1548 
1549  /// Provide a global flag for disabling the PreRA hazard recognizer that
1550  /// targets may choose to honor.
1551  bool usePreRAHazardRecognizer() const;
1552 
1553  /// For a comparison instruction, return the source registers
1554  /// in SrcReg and SrcReg2 if having two register operands, and the value it
1555  /// compares against in CmpValue. Return true if the comparison instruction
1556  /// can be analyzed.
1557  virtual bool analyzeCompare(const MachineInstr &MI, Register &SrcReg,
1558  Register &SrcReg2, int64_t &Mask,
1559  int64_t &Value) const {
1560  return false;
1561  }
1562 
1563  /// See if the comparison instruction can be converted
1564  /// into something more efficient. E.g., on ARM most instructions can set the
1565  /// flags register, obviating the need for a separate CMP.
1566  virtual bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
1567  Register SrcReg2, int64_t Mask,
1568  int64_t Value,
1569  const MachineRegisterInfo *MRI) const {
1570  return false;
1571  }
1572  virtual bool optimizeCondBranch(MachineInstr &MI) const { return false; }
1573 
1574  /// Try to remove the load by folding it to a register operand at the use.
1575  /// We fold the load instructions if and only if the
1576  /// def and use are in the same BB. We only look at one load and see
1577  /// whether it can be folded into MI. FoldAsLoadDefReg is the virtual register
1578  /// defined by the load we are trying to fold. DefMI returns the machine
1579  /// instruction that defines FoldAsLoadDefReg, and the function returns
1580  /// the machine instruction generated due to folding.
1582  const MachineRegisterInfo *MRI,
1583  Register &FoldAsLoadDefReg,
1584  MachineInstr *&DefMI) const {
1585  return nullptr;
1586  }
1587 
1588  /// 'Reg' is known to be defined by a move immediate instruction,
1589  /// try to fold the immediate into the use instruction.
1590  /// If MRI->hasOneNonDBGUse(Reg) is true, and this function returns true,
1591  /// then the caller may assume that DefMI has been erased from its parent
1592  /// block. The caller may assume that it will not be erased by this
1593  /// function otherwise.
1595  Register Reg, MachineRegisterInfo *MRI) const {
1596  return false;
1597  }
1598 
1599  /// Return the number of u-operations the given machine
1600  /// instruction will be decoded to on the target cpu. The itinerary's
1601  /// IssueWidth is the number of microops that can be dispatched each
1602  /// cycle. An instruction with zero microops takes no dispatch resources.
1603  virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData,
1604  const MachineInstr &MI) const;
1605 
1606  /// Return true for pseudo instructions that don't consume any
1607  /// machine resources in their current form. These are common cases that the
1608  /// scheduler should consider free, rather than conservatively handling them
1609  /// as instructions with no itinerary.
1610  bool isZeroCost(unsigned Opcode) const {
1611  return Opcode <= TargetOpcode::COPY;
1612  }
1613 
1614  virtual int getOperandLatency(const InstrItineraryData *ItinData,
1615  SDNode *DefNode, unsigned DefIdx,
1616  SDNode *UseNode, unsigned UseIdx) const;
1617 
1618  /// Compute and return the use operand latency of a given pair of def and use.
1619  /// In most cases, the static scheduling itinerary was enough to determine the
1620  /// operand latency. But it may not be possible for instructions with variable
1621  /// number of defs / uses.
1622  ///
1623  /// This is a raw interface to the itinerary that may be directly overridden
1624  /// by a target. Use computeOperandLatency to get the best estimate of
1625  /// latency.
1626  virtual int getOperandLatency(const InstrItineraryData *ItinData,
1627  const MachineInstr &DefMI, unsigned DefIdx,
1628  const MachineInstr &UseMI,
1629  unsigned UseIdx) const;
1630 
1631  /// Compute the instruction latency of a given instruction.
1632  /// If the instruction has higher cost when predicated, it's returned via
1633  /// PredCost.
1634  virtual unsigned getInstrLatency(const InstrItineraryData *ItinData,
1635  const MachineInstr &MI,
1636  unsigned *PredCost = nullptr) const;
1637 
1638  virtual unsigned getPredicationCost(const MachineInstr &MI) const;
1639 
1640  virtual int getInstrLatency(const InstrItineraryData *ItinData,
1641  SDNode *Node) const;
1642 
1643  /// Return the default expected latency for a def based on its opcode.
1644  unsigned defaultDefLatency(const MCSchedModel &SchedModel,
1645  const MachineInstr &DefMI) const;
1646 
1647  /// Return true if this opcode has high latency to its result.
1648  virtual bool isHighLatencyDef(int opc) const { return false; }
1649 
1650  /// Compute operand latency between a def of 'Reg'
1651  /// and a use in the current loop. Return true if the target considered
1652  /// it 'high'. This is used by optimization passes such as machine LICM to
1653  /// determine whether it makes sense to hoist an instruction out even in a
1654  /// high register pressure situation.
1655  virtual bool hasHighOperandLatency(const TargetSchedModel &SchedModel,
1656  const MachineRegisterInfo *MRI,
1657  const MachineInstr &DefMI, unsigned DefIdx,
1658  const MachineInstr &UseMI,
1659  unsigned UseIdx) const {
1660  return false;
1661  }
1662 
1663  /// Compute operand latency of a def of 'Reg'. Return true
1664  /// if the target considered it 'low'.
1665  virtual bool hasLowDefLatency(const TargetSchedModel &SchedModel,
1666  const MachineInstr &DefMI,
1667  unsigned DefIdx) const;
1668 
1669  /// Perform target-specific instruction verification.
1670  virtual bool verifyInstruction(const MachineInstr &MI,
1671  StringRef &ErrInfo) const {
1672  return true;
1673  }
1674 
1675  /// Return the current execution domain and bit mask of
1676  /// possible domains for instruction.
1677  ///
1678  /// Some micro-architectures have multiple execution domains, and multiple
1679  /// opcodes that perform the same operation in different domains. For
1680  /// example, the x86 architecture provides the por, orps, and orpd
1681  /// instructions that all do the same thing. There is a latency penalty if a
1682  /// register is written in one domain and read in another.
1683  ///
1684  /// This function returns a pair (domain, mask) containing the execution
1685  /// domain of MI, and a bit mask of possible domains. The setExecutionDomain
1686  /// function can be used to change the opcode to one of the domains in the
1687  /// bit mask. Instructions whose execution domain can't be changed should
1688  /// return a 0 mask.
1689  ///
1690  /// The execution domain numbers don't have any special meaning except domain
1691  /// 0 is used for instructions that are not associated with any interesting
1692  /// execution domain.
1693  ///
1694  virtual std::pair<uint16_t, uint16_t>
1696  return std::make_pair(0, 0);
1697  }
1698 
1699  /// Change the opcode of MI to execute in Domain.
1700  ///
1701  /// The bit (1 << Domain) must be set in the mask returned from
1702  /// getExecutionDomain(MI).
1703  virtual void setExecutionDomain(MachineInstr &MI, unsigned Domain) const {}
1704 
1705  /// Returns the preferred minimum clearance
1706  /// before an instruction with an unwanted partial register update.
1707  ///
1708  /// Some instructions only write part of a register, and implicitly need to
1709  /// read the other parts of the register. This may cause unwanted stalls
1710  /// preventing otherwise unrelated instructions from executing in parallel in
1711  /// an out-of-order CPU.
1712  ///
1713  /// For example, the x86 instruction cvtsi2ss writes its result to bits
1714  /// [31:0] of the destination xmm register. Bits [127:32] are unaffected, so
1715  /// the instruction needs to wait for the old value of the register to become
1716  /// available:
1717  ///
1718  /// addps %xmm1, %xmm0
1719  /// movaps %xmm0, (%rax)
1720  /// cvtsi2ss %rbx, %xmm0
1721  ///
1722  /// In the code above, the cvtsi2ss instruction needs to wait for the addps
1723  /// instruction before it can issue, even though the high bits of %xmm0
1724  /// probably aren't needed.
1725  ///
1726  /// This hook returns the preferred clearance before MI, measured in
1727  /// instructions. Other defs of MI's operand OpNum are avoided in the last N
1728  /// instructions before MI. It should only return a positive value for
1729  /// unwanted dependencies. If the old bits of the defined register have
1730  /// useful values, or if MI is determined to otherwise read the dependency,
1731  /// the hook should return 0.
1732  ///
1733  /// The unwanted dependency may be handled by:
1734  ///
1735  /// 1. Allocating the same register for an MI def and use. That makes the
1736  /// unwanted dependency identical to a required dependency.
1737  ///
1738  /// 2. Allocating a register for the def that has no defs in the previous N
1739  /// instructions.
1740  ///
1741  /// 3. Calling breakPartialRegDependency() with the same arguments. This
1742  /// allows the target to insert a dependency breaking instruction.
1743  ///
1744  virtual unsigned
1746  const TargetRegisterInfo *TRI) const {
1747  // The default implementation returns 0 for no partial register dependency.
1748  return 0;
1749  }
1750 
1751  /// Return the minimum clearance before an instruction that reads an
1752  /// unused register.
1753  ///
1754  /// For example, AVX instructions may copy part of a register operand into
1755  /// the unused high bits of the destination register.
1756  ///
1757  /// vcvtsi2sdq %rax, undef %xmm0, %xmm14
1758  ///
1759  /// In the code above, vcvtsi2sdq copies %xmm0[127:64] into %xmm14 creating a
1760  /// false dependence on any previous write to %xmm0.
1761  ///
1762  /// This hook works similarly to getPartialRegUpdateClearance, except that it
1763  /// does not take an operand index. Instead sets \p OpNum to the index of the
1764  /// unused register.
1765  virtual unsigned getUndefRegClearance(const MachineInstr &MI, unsigned OpNum,
1766  const TargetRegisterInfo *TRI) const {
1767  // The default implementation returns 0 for no undef register dependency.
1768  return 0;
1769  }
1770 
1771  /// Insert a dependency-breaking instruction
1772  /// before MI to eliminate an unwanted dependency on OpNum.
1773  ///
1774  /// If it wasn't possible to avoid a def in the last N instructions before MI
1775  /// (see getPartialRegUpdateClearance), this hook will be called to break the
1776  /// unwanted dependency.
1777  ///
1778  /// On x86, an xorps instruction can be used as a dependency breaker:
1779  ///
1780  /// addps %xmm1, %xmm0
1781  /// movaps %xmm0, (%rax)
1782  /// xorps %xmm0, %xmm0
1783  /// cvtsi2ss %rbx, %xmm0
1784  ///
1785  /// An <imp-kill> operand should be added to MI if an instruction was
1786  /// inserted. This ties the instructions together in the post-ra scheduler.
1787  ///
1788  virtual void breakPartialRegDependency(MachineInstr &MI, unsigned OpNum,
1789  const TargetRegisterInfo *TRI) const {}
1790 
1791  /// Create machine specific model for scheduling.
1792  virtual DFAPacketizer *
1794  return nullptr;
1795  }
1796 
1797  /// Sometimes, it is possible for the target
1798  /// to tell, even without aliasing information, that two MIs access different
1799  /// memory addresses. This function returns true if two MIs access different
1800  /// memory addresses and false otherwise.
1801  ///
1802  /// Assumes any physical registers used to compute addresses have the same
1803  /// value for both instructions. (This is the most useful assumption for
1804  /// post-RA scheduling.)
1805  ///
1806  /// See also MachineInstr::mayAlias, which is implemented on top of this
1807  /// function.
1808  virtual bool
1810  const MachineInstr &MIb) const {
1811  assert(MIa.mayLoadOrStore() &&
1812  "MIa must load from or modify a memory location");
1813  assert(MIb.mayLoadOrStore() &&
1814  "MIb must load from or modify a memory location");
1815  return false;
1816  }
1817 
1818  /// Return the value to use for the MachineCSE's LookAheadLimit,
1819  /// which is a heuristic used for CSE'ing phys reg defs.
1820  virtual unsigned getMachineCSELookAheadLimit() const {
1821  // The default lookahead is small to prevent unprofitable quadratic
1822  // behavior.
1823  return 5;
1824  }
1825 
1826  /// Return the maximal number of alias checks on memory operands. For
1827  /// instructions with more than one memory operands, the alias check on a
1828  /// single MachineInstr pair has quadratic overhead and results in
1829  /// unacceptable performance in the worst case. The limit here is to clamp
1830  /// that maximal checks performed. Usually, that's the product of memory
1831  /// operand numbers from that pair of MachineInstr to be checked. For
1832  /// instance, with two MachineInstrs with 4 and 5 memory operands
1833  /// correspondingly, a total of 20 checks are required. With this limit set to
1834  /// 16, their alias check is skipped. We choose to limit the product instead
1835  /// of the individual instruction as targets may have special MachineInstrs
1836  /// with a considerably high number of memory operands, such as `ldm` in ARM.
1837  /// Setting this limit per MachineInstr would result in either too high
1838  /// overhead or too rigid restriction.
1839  virtual unsigned getMemOperandAACheckLimit() const { return 16; }
1840 
1841  /// Return an array that contains the ids of the target indices (used for the
1842  /// TargetIndex machine operand) and their names.
1843  ///
1844  /// MIR Serialization is able to serialize only the target indices that are
1845  /// defined by this method.
1848  return None;
1849  }
1850 
1851  /// Decompose the machine operand's target flags into two values - the direct
1852  /// target flag value and any of bit flags that are applied.
1853  virtual std::pair<unsigned, unsigned>
1854  decomposeMachineOperandsTargetFlags(unsigned /*TF*/) const {
1855  return std::make_pair(0u, 0u);
1856  }
1857 
1858  /// Return an array that contains the direct target flag values and their
1859  /// names.
1860  ///
1861  /// MIR Serialization is able to serialize only the target flags that are
1862  /// defined by this method.
1865  return None;
1866  }
1867 
1868  /// Return an array that contains the bitmask target flag values and their
1869  /// names.
1870  ///
1871  /// MIR Serialization is able to serialize only the target flags that are
1872  /// defined by this method.
1875  return None;
1876  }
1877 
1878  /// Return an array that contains the MMO target flag values and their
1879  /// names.
1880  ///
1881  /// MIR Serialization is able to serialize only the MMO target flags that are
1882  /// defined by this method.
1885  return None;
1886  }
1887 
1888  /// Determines whether \p Inst is a tail call instruction. Override this
1889  /// method on targets that do not properly set MCID::Return and MCID::Call on
1890  /// tail call instructions."
1891  virtual bool isTailCall(const MachineInstr &Inst) const {
1892  return Inst.isReturn() && Inst.isCall();
1893  }
1894 
1895  /// True if the instruction is bound to the top of its basic block and no
1896  /// other instructions shall be inserted before it. This can be implemented
1897  /// to prevent register allocator to insert spills before such instructions.
1898  virtual bool isBasicBlockPrologue(const MachineInstr &MI) const {
1899  return false;
1900  }
1901 
1902  /// During PHI eleimination lets target to make necessary checks and
1903  /// insert the copy to the PHI destination register in a target specific
1904  /// manner.
1907  const DebugLoc &DL, Register Src, Register Dst) const {
1908  return BuildMI(MBB, InsPt, DL, get(TargetOpcode::COPY), Dst)
1909  .addReg(Src);
1910  }
1911 
1912  /// During PHI eleimination lets target to make necessary checks and
1913  /// insert the copy to the PHI destination register in a target specific
1914  /// manner.
1917  const DebugLoc &DL, Register Src,
1918  unsigned SrcSubReg,
1919  Register Dst) const {
1920  return BuildMI(MBB, InsPt, DL, get(TargetOpcode::COPY), Dst)
1921  .addReg(Src, 0, SrcSubReg);
1922  }
1923 
1924  /// Returns a \p outliner::OutlinedFunction struct containing target-specific
1925  /// information for a set of outlining candidates.
1927  std::vector<outliner::Candidate> &RepeatedSequenceLocs) const {
1929  "Target didn't implement TargetInstrInfo::getOutliningCandidateInfo!");
1930  }
1931 
1932  /// Optional target hook to create the LLVM IR attributes for the outlined
1933  /// function. If overridden, the overriding function must call the default
1934  /// implementation.
1935  virtual void mergeOutliningCandidateAttributes(
1936  Function &F, std::vector<outliner::Candidate> &Candidates) const;
1937 
1938  /// Returns how or if \p MI should be outlined.
1939  virtual outliner::InstrType
1940  getOutliningType(MachineBasicBlock::iterator &MIT, unsigned Flags) const {
1942  "Target didn't implement TargetInstrInfo::getOutliningType!");
1943  }
1944 
1945  /// Optional target hook that returns true if \p MBB is safe to outline from,
1946  /// and returns any target-specific information in \p Flags.
1948  unsigned &Flags) const;
1949 
1950  /// Insert a custom frame for outlined functions.
1952  const outliner::OutlinedFunction &OF) const {
1954  "Target didn't implement TargetInstrInfo::buildOutlinedFrame!");
1955  }
1956 
1957  /// Insert a call to an outlined function into the program.
1958  /// Returns an iterator to the spot where we inserted the call. This must be
1959  /// implemented by the target.
1963  outliner::Candidate &C) const {
1965  "Target didn't implement TargetInstrInfo::insertOutlinedCall!");
1966  }
1967 
1968  /// Return true if the function can safely be outlined from.
1969  /// A function \p MF is considered safe for outlining if an outlined function
1970  /// produced from instructions in F will produce a program which produces the
1971  /// same output for any set of given inputs.
1973  bool OutlineFromLinkOnceODRs) const {
1974  llvm_unreachable("Target didn't implement "
1975  "TargetInstrInfo::isFunctionSafeToOutlineFrom!");
1976  }
1977 
1978  /// Return true if the function should be outlined from by default.
1980  return false;
1981  }
1982 
1983  /// Produce the expression describing the \p MI loading a value into
1984  /// the physical register \p Reg. This hook should only be used with
1985  /// \p MIs belonging to VReg-less functions.
1987  Register Reg) const;
1988 
1989  /// Given the generic extension instruction \p ExtMI, returns true if this
1990  /// extension is a likely candidate for being folded into an another
1991  /// instruction.
1993  MachineRegisterInfo &MRI) const {
1994  return false;
1995  }
1996 
1997  /// Return MIR formatter to format/parse MIR operands. Target can override
1998  /// this virtual function and return target specific MIR formatter.
1999  virtual const MIRFormatter *getMIRFormatter() const {
2000  if (!Formatter.get())
2001  Formatter = std::make_unique<MIRFormatter>();
2002  return Formatter.get();
2003  }
2004 
2005  /// Returns the target-specific default value for tail duplication.
2006  /// This value will be used if the tail-dup-placement-threshold argument is
2007  /// not provided.
2008  virtual unsigned getTailDuplicateSize(CodeGenOpt::Level OptLevel) const {
2009  return OptLevel >= CodeGenOpt::Aggressive ? 4 : 2;
2010  }
2011 
2012  /// Returns the callee operand from the given \p MI.
2013  virtual const MachineOperand &getCalleeOperand(const MachineInstr &MI) const {
2014  return MI.getOperand(0);
2015  }
2016 
2017 private:
2018  mutable std::unique_ptr<MIRFormatter> Formatter;
2019  unsigned CallFrameSetupOpcode, CallFrameDestroyOpcode;
2020  unsigned CatchRetOpcode;
2021  unsigned ReturnOpcode;
2022 };
2023 
2024 /// Provide DenseMapInfo for TargetInstrInfo::RegSubRegPair.
2027 
2029  return TargetInstrInfo::RegSubRegPair(RegInfo::getEmptyKey(),
2030  RegInfo::getEmptyKey());
2031  }
2032 
2034  return TargetInstrInfo::RegSubRegPair(RegInfo::getTombstoneKey(),
2035  RegInfo::getTombstoneKey());
2036  }
2037 
2038  /// Reuse getHashValue implementation from
2039  /// std::pair<unsigned, unsigned>.
2040  static unsigned getHashValue(const TargetInstrInfo::RegSubRegPair &Val) {
2041  std::pair<unsigned, unsigned> PairVal = std::make_pair(Val.Reg, Val.SubReg);
2042  return DenseMapInfo<std::pair<unsigned, unsigned>>::getHashValue(PairVal);
2043  }
2044 
2047  return RegInfo::isEqual(LHS.Reg, RHS.Reg) &&
2048  RegInfo::isEqual(LHS.SubReg, RHS.SubReg);
2049  }
2050 };
2051 
2052 } // end namespace llvm
2053 
2054 #endif // LLVM_CODEGEN_TARGETINSTRINFO_H
llvm::TargetInstrInfo::getConstValDefinedInReg
virtual bool getConstValDefinedInReg(const MachineInstr &MI, const Register Reg, int64_t &ImmVal) const
Returns true if MI is an instruction that defines Reg to have a constant value and the value is recor...
Definition: TargetInstrInfo.h:1054
llvm::SwingSchedulerDAG
This class builds the dependence graph for the instructions in a loop, and attempts to schedule the i...
Definition: MachinePipeliner.h:113
llvm::TargetInstrInfo::hasReassociableSibling
bool hasReassociableSibling(const MachineInstr &Inst, bool &Commuted) const
Return true when \P Inst has reassociable sibling.
Definition: TargetInstrInfo.cpp:717
llvm::TargetInstrInfo::PipelinerLoopInfo::shouldUseSchedule
virtual bool shouldUseSchedule(SwingSchedulerDAG &SSD, SMSchedule &SMS)
Return true if the proposed schedule should used.
Definition: TargetInstrInfo.h:742
llvm::TargetInstrInfo::getMemOperandWithOffset
bool getMemOperandWithOffset(const MachineInstr &MI, const MachineOperand *&BaseOp, int64_t &Offset, bool &OffsetIsScalable, const TargetRegisterInfo *TRI) const
Get the base operand and byte offset of an instruction that reads/writes memory.
Definition: TargetInstrInfo.cpp:1070
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:108
MachineInstr.h
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::TargetInstrInfo::isSafeToMoveRegClassDefs
virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const
Return true if it's safe to move a machine instruction that defines the specified register class.
Definition: TargetInstrInfo.h:1508
llvm::TargetInstrInfo::insertIndirectBranch
virtual void insertIndirectBranch(MachineBasicBlock &MBB, MachineBasicBlock &NewDestBB, MachineBasicBlock &RestoreBB, const DebugLoc &DL, int64_t BrOffset=0, RegScavenger *RS=nullptr) const
Insert an unconditional indirect branch at the end of MBB to NewDestBB.
Definition: TargetInstrInfo.h:606
llvm::TargetInstrInfo::analyzeCompare
virtual bool analyzeCompare(const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int64_t &Mask, int64_t &Value) const
For a comparison instruction, return the source registers in SrcReg and SrcReg2 if having two registe...
Definition: TargetInstrInfo.h:1557
llvm::TargetInstrInfo::insertSelect
virtual void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register DstReg, ArrayRef< MachineOperand > Cond, Register TrueReg, Register FalseReg) const
Insert a select instruction into MBB before I that will copy TrueReg to DstReg when Cond is true,...
Definition: TargetInstrInfo.h:924
UseMI
MachineInstrBuilder & UseMI
Definition: AArch64ExpandPseudoInsts.cpp:105
llvm::TargetInstrInfo::isSubregFoldable
virtual bool isSubregFoldable() const
Check whether the target can fold a load that feeds a subreg operand (or a subreg operand that feeds ...
Definition: TargetInstrInfo.h:1105
llvm::TargetInstrInfo::duplicate
virtual MachineInstr & duplicate(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, const MachineInstr &Orig) const
Clones instruction or the whole instruction bundle Orig and insert into MBB before InsertBefore.
Definition: TargetInstrInfo.cpp:433
llvm::TargetInstrInfo::areLoadsFromSameBasePtr
virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1, int64_t &Offset2) const
This is used by the pre-regalloc scheduler to determine if two loads are loading from the same base a...
Definition: TargetInstrInfo.h:1327
llvm::TargetInstrInfo::CreateTargetHazardRecognizer
virtual ScheduleHazardRecognizer * CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const
Allocate and return a hazard recognizer to use for this target when scheduling the machine instructio...
Definition: TargetInstrInfo.cpp:1050
llvm::DenseMapInfo< unsigned >
Definition: DenseMapInfo.h:125
llvm::TargetInstrInfo::replaceBranchWithTailCall
virtual void replaceBranchWithTailCall(MachineBasicBlock &MBB, SmallVectorImpl< MachineOperand > &Cond, const MachineInstr &TailCall) const
Replace the conditional branch in MBB with a conditional tail call.
Definition: TargetInstrInfo.h:1468
llvm::TargetInstrInfo::getCatchReturnOpcode
unsigned getCatchReturnOpcode() const
Definition: TargetInstrInfo.h:241
llvm::TargetInstrInfo::unfoldMemoryOperand
virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr &MI, unsigned Reg, bool UnfoldLoad, bool UnfoldStore, SmallVectorImpl< MachineInstr * > &NewMIs) const
unfoldMemoryOperand - Separate a single instruction which folded a load or a store or a load and a st...
Definition: TargetInstrInfo.h:1300
llvm::TargetInstrInfo::useMachineCombiner
virtual bool useMachineCombiner() const
Return true when a target supports MachineCombiner.
Definition: TargetInstrInfo.h:1219
llvm::TargetInstrInfo::analyzeBranchPredicate
virtual bool analyzeBranchPredicate(MachineBasicBlock &MBB, MachineBranchPredicate &MBP, bool AllowModify=false) const
Analyze the branching code at the end of MBB and parse it into the MachineBranchPredicate structure i...
Definition: TargetInstrInfo.h:683
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
llvm::TargetInstrInfo::MachineBranchPredicate
Represents a predicate at the MachineFunction level.
Definition: TargetInstrInfo.h:654
llvm::MachineInstr::mayLoadOrStore
bool mayLoadOrStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read or modify memory.
Definition: MachineInstr.h:1079
llvm::RegImmPair::Imm
int64_t Imm
Definition: TargetInstrInfo.h:80
llvm::Function
Definition: Function.h:60
llvm::TargetInstrInfo::getReturnOpcode
unsigned getReturnOpcode() const
Definition: TargetInstrInfo.h:242
llvm::TargetInstrInfo::isThroughputPattern
virtual bool isThroughputPattern(MachineCombinerPattern Pattern) const
Return true when a code sequence can improve throughput.
Definition: TargetInstrInfo.cpp:799
P
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
Definition: README-SSE.txt:411
llvm::MCAsmInfo
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
llvm::TargetInstrInfo::canInsertSelect
virtual bool canInsertSelect(const MachineBasicBlock &MBB, ArrayRef< MachineOperand > Cond, Register DstReg, Register TrueReg, Register FalseReg, int &CondCycles, int &TrueCycles, int &FalseCycles) const
Return true if it is possible to insert a select instruction that chooses between TrueReg and FalseRe...
Definition: TargetInstrInfo.h:901
llvm::TargetInstrInfo::getExtractSubregInputs
bool getExtractSubregInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPairAndIdx &InputReg) const
Build the equivalent inputs of a EXTRACT_SUBREG for the given MI and DefIdx.
Definition: TargetInstrInfo.cpp:1293
llvm::TargetInstrInfo::createPHIDestinationCopy
virtual MachineInstr * createPHIDestinationCopy(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsPt, const DebugLoc &DL, Register Src, Register Dst) const
During PHI eleimination lets target to make necessary checks and insert the copy to the PHI destinati...
Definition: TargetInstrInfo.h:1905
llvm::TargetInstrInfo::RegSubRegPairAndIdx
A pair composed of a pair of a register and a sub-register index, and another sub-register index.
Definition: TargetInstrInfo.h:512
llvm::TargetInstrInfo::getMachineCombinerPatterns
virtual bool getMachineCombinerPatterns(MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &Patterns, bool DoRegPressureReduce) const
Return true when there is potentially a faster code sequence for an instruction chain ending in Root.
Definition: TargetInstrInfo.cpp:775
llvm::TargetInstrInfo::isLoadFromStackSlot
virtual unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex, unsigned &MemBytes) const
Optional extension of isLoadFromStackSlot that returns the number of bytes loaded from the stack.
Definition: TargetInstrInfo.h:274
llvm::TargetInstrInfo::getUndefRegClearance
virtual unsigned getUndefRegClearance(const MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const
Return the minimum clearance before an instruction that reads an unused register.
Definition: TargetInstrInfo.h:1765
ErrorHandling.h
llvm::VirtRegMap
Definition: VirtRegMap.h:33
llvm::TargetInstrInfo::isCopyInstrImpl
virtual Optional< DestSourcePair > isCopyInstrImpl(const MachineInstr &MI) const
Target-dependent implementation for IsCopyInstr.
Definition: TargetInstrInfo.h:1013
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::DenseMapInfo< TargetInstrInfo::RegSubRegPair >::isEqual
static bool isEqual(const TargetInstrInfo::RegSubRegPair &LHS, const TargetInstrInfo::RegSubRegPair &RHS)
Definition: TargetInstrInfo.h:2045
llvm::TargetInstrInfo::copyPhysReg
virtual void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const
Emit instructions to copy a pair of physical registers.
Definition: TargetInstrInfo.h:987
llvm::TargetInstrInfo::isGenericOpcode
static bool isGenericOpcode(unsigned Opc)
Definition: TargetInstrInfo.h:109
llvm::SDNode
Represents one node in the SelectionDAG.
Definition: SelectionDAGNodes.h:462
RegisterClassInfo.h
llvm::TargetInstrInfo::optimizeCondBranch
virtual bool optimizeCondBranch(MachineInstr &MI) const
Definition: TargetInstrInfo.h:1572
MachineBasicBlock.h
llvm::TargetInstrInfo::MachineBranchPredicate::RHS
MachineOperand RHS
Definition: TargetInstrInfo.h:663
llvm::TargetInstrInfo::isTriviallyReMaterializable
bool isTriviallyReMaterializable(const MachineInstr &MI) const
Return true if the instruction is trivially rematerializable, meaning it has no side effects and requ...
Definition: TargetInstrInfo.h:130
llvm::TargetInstrInfo::getCalleeOperand
virtual const MachineOperand & getCalleeOperand(const MachineInstr &MI) const
Returns the callee operand from the given MI.
Definition: TargetInstrInfo.h:2013
llvm::TargetInstrInfo::isUnspillableTerminator
bool isUnspillableTerminator(const MachineInstr *MI) const
Return true if the given instruction is terminator that is unspillable, according to isUnspillableTer...
Definition: TargetInstrInfo.h:363
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:237
llvm::TargetInstrInfo::insertNoops
virtual void insertNoops(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned Quantity) const
Insert noops into the instruction stream at the specified point.
Definition: TargetInstrInfo.cpp:72
llvm::TargetInstrInfo::getIncrementValue
virtual bool getIncrementValue(const MachineInstr &MI, int &Value) const
If the instruction is an increment of a constant value, return the amount.
Definition: TargetInstrInfo.h:1400
llvm::outliner::InstrType
InstrType
Represents how an instruction should be mapped by the outliner.
Definition: MachineOutliner.h:33
llvm::TargetInstrInfo::ReplaceTailWithBranchTo
virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail, MachineBasicBlock *NewDest) const
Delete the instruction OldInst and everything after it, replacing it with an unconditional branch to ...
Definition: TargetInstrInfo.cpp:139
DenseMap.h
llvm::TargetInstrInfo::MachineBranchPredicate::FalseDest
MachineBasicBlock * FalseDest
Definition: TargetInstrInfo.h:665
llvm::TargetInstrInfo::getOutliningCandidateInfo
virtual outliner::OutlinedFunction getOutliningCandidateInfo(std::vector< outliner::Candidate > &RepeatedSequenceLocs) const
Returns a outliner::OutlinedFunction struct containing target-specific information for a set of outli...
Definition: TargetInstrInfo.h:1926
llvm::TargetInstrInfo::CreateTargetScheduleState
virtual DFAPacketizer * CreateTargetScheduleState(const TargetSubtargetInfo &) const
Create machine specific model for scheduling.
Definition: TargetInstrInfo.h:1793
llvm::Optional< bool >
llvm::DestSourcePair::Destination
const MachineOperand * Destination
Definition: TargetInstrInfo.h:70
llvm::TargetInstrInfo::isCopyInstr
Optional< DestSourcePair > isCopyInstr(const MachineInstr &MI) const
If the specific machine instruction is a instruction that moves/copies value from one register to ano...
Definition: TargetInstrInfo.h:1035
llvm::TargetInstrInfo::getNop
virtual MCInst getNop() const
Return the noop instruction to use for a noop.
Definition: TargetInstrInfo.cpp:473
llvm::ExtAddrMode::ScaledReg
Register ScaledReg
Definition: TargetInstrInfo.h:89
llvm::TargetInstrInfo::isBranchOffsetInRange
virtual bool isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const
Definition: TargetInstrInfo.h:592
llvm::TargetInstrInfo::hasHighOperandLatency
virtual bool hasHighOperandLatency(const TargetSchedModel &SchedModel, const MachineRegisterInfo *MRI, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const
Compute operand latency between a def of 'Reg' and a use in the current loop.
Definition: TargetInstrInfo.h:1655
llvm::TargetInstrInfo::isPredicable
virtual bool isPredicable(const MachineInstr &MI) const
Return true if the specified instruction can be predicated.
Definition: TargetInstrInfo.h:1502
llvm::TargetInstrInfo::insertOutlinedCall
virtual MachineBasicBlock::iterator insertOutlinedCall(Module &M, MachineBasicBlock &MBB, MachineBasicBlock::iterator &It, MachineFunction &MF, outliner::Candidate &C) const
Insert a call to an outlined function into the program.
Definition: TargetInstrInfo.h:1961
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
RHS
Value * RHS
Definition: X86PartialReduction.cpp:76
llvm::outliner::OutlinedFunction
The information necessary to create an outlined function for some class of candidate.
Definition: MachineOutliner.h:214
llvm::TargetInstrInfo::getInsertSubregInputs
bool getInsertSubregInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPair &BaseReg, RegSubRegPairAndIdx &InsertedReg) const
Build the equivalent inputs of a INSERT_SUBREG for the given MI and DefIdx.
Definition: TargetInstrInfo.cpp:1318
llvm::TargetInstrInfo::hasCommutePreference
virtual bool hasCommutePreference(MachineInstr &MI, bool &Commute) const
Returns true if the target has a preference on the operands order of the given machine instruction.
Definition: TargetInstrInfo.h:488
llvm::TargetInstrInfo::decomposeMachineOperandsTargetFlags
virtual std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned) const
Decompose the machine operand's target flags into two values - the direct target flag value and any o...
Definition: TargetInstrInfo.h:1854
llvm::TargetInstrInfo::RegSubRegPair::operator!=
bool operator!=(const RegSubRegPair &P) const
Definition: TargetInstrInfo.h:504
llvm::TargetInstrInfo::unfoldMemoryOperand
virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, SmallVectorImpl< SDNode * > &NewNodes) const
Definition: TargetInstrInfo.h:1306
llvm::TargetInstrInfo::shouldClusterMemOps
virtual bool shouldClusterMemOps(ArrayRef< const MachineOperand * > BaseOps1, ArrayRef< const MachineOperand * > BaseOps2, unsigned NumLoads, unsigned NumBytes) const
Returns true if the two given memory operations should be scheduled adjacent.
Definition: TargetInstrInfo.h:1416
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
llvm::TargetInstrInfo::foldMemoryOperandImpl
virtual MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI, LiveIntervals *LIS=nullptr) const
Target-dependent implementation for foldMemoryOperand.
Definition: TargetInstrInfo.h:1245
llvm::TargetInstrInfo::getPartialRegUpdateClearance
virtual unsigned getPartialRegUpdateClearance(const MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const
Returns the preferred minimum clearance before an instruction with an unwanted partial register updat...
Definition: TargetInstrInfo.h:1745
llvm::TargetInstrInfo::isHighLatencyDef
virtual bool isHighLatencyDef(int opc) const
Return true if this opcode has high latency to its result.
Definition: TargetInstrInfo.h:1648
F
#define F(x, y, z)
Definition: MD5.cpp:55
llvm::TargetInstrInfo::RegSubRegPair
A pair composed of a register and a sub-register index.
Definition: TargetInstrInfo.h:494
llvm::ExtAddrMode
Used to describe addressing mode similar to ExtAddrMode in CodeGenPrepare.
Definition: TargetInstrInfo.h:87
llvm::RegImmPair::Reg
Register Reg
Definition: TargetInstrInfo.h:79
llvm::TargetInstrInfo::insertBranch
virtual unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const
Insert branch code into the end of the specified MachineBasicBlock.
Definition: TargetInstrInfo.h:712
llvm::TargetInstrInfo::getMachineCSELookAheadLimit
virtual unsigned getMachineCSELookAheadLimit() const
Return the value to use for the MachineCSE's LookAheadLimit, which is a heuristic used for CSE'ing ph...
Definition: TargetInstrInfo.h:1820
llvm::TargetInstrInfo::RegSubRegPair::operator==
bool operator==(const RegSubRegPair &P) const
Definition: TargetInstrInfo.h:501
llvm::TargetInstrInfo::isZeroCost
bool isZeroCost(unsigned Opcode) const
Return true for pseudo instructions that don't consume any machine resources in their current form.
Definition: TargetInstrInfo.h:1610
llvm::TargetInstrInfo::getFrameSize
int64_t getFrameSize(const MachineInstr &I) const
Returns size of the frame associated with the given frame instruction.
Definition: TargetInstrInfo.h:223
llvm::BitmaskEnumDetail::Mask
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::TargetInstrInfo::PipelinerLoopInfo
Object returned by analyzeLoopForPipelining.
Definition: TargetInstrInfo.h:731
LHS
Value * LHS
Definition: X86PartialReduction.cpp:75
llvm::TargetInstrInfo::getRegClass
virtual const TargetRegisterClass * getRegClass(const MCInstrDesc &MCID, unsigned OpNum, const TargetRegisterInfo *TRI, const MachineFunction &MF) const
Given a machine instruction descriptor, returns the register class constraint for OpNum,...
Definition: TargetInstrInfo.cpp:45
llvm::DenseMapInfo
An information struct used to provide DenseMap with the various necessary components for a given valu...
Definition: APInt.h:34
llvm::TargetInstrInfo::MachineBranchPredicate::PRED_NE
@ PRED_NE
Definition: TargetInstrInfo.h:657
llvm::TargetInstrInfo::usePreRAHazardRecognizer
bool usePreRAHazardRecognizer() const
Provide a global flag for disabling the PreRA hazard recognizer that targets may choose to honor.
Definition: TargetInstrInfo.cpp:1044
llvm::TargetInstrInfo::getFrameTotalSize
int64_t getFrameTotalSize(const MachineInstr &I) const
Returns the total frame size, which is made up of the space set up inside the pair of frame start-sto...
Definition: TargetInstrInfo.h:232
llvm::MachineInstr::isCall
bool isCall(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:872
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:98
llvm::TargetInstrInfo::removeBranch
virtual unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const
Remove the branching code at the end of the specific MBB.
Definition: TargetInstrInfo.h:694
llvm::TargetInstrInfo::commuteInstructionImpl
virtual MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const
This method commutes the operands of the given machine instruction MI.
Definition: TargetInstrInfo.cpp:165
llvm::SelectionDAG
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:220
llvm::TargetInstrInfo::loadRegFromStackSlot
virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const
Load the specified register of the given register class from the specified stack frame index.
Definition: TargetInstrInfo.h:1076
llvm::MachineOperand::CreateImm
static MachineOperand CreateImm(int64_t Val)
Definition: MachineOperand.h:782
llvm::TargetInstrInfo::MachineBranchPredicate::ConditionDef
MachineInstr * ConditionDef
Definition: TargetInstrInfo.h:666
llvm::TargetInstrInfo::canCopyGluedNodeDuringSchedule
virtual bool canCopyGluedNodeDuringSchedule(SDNode *N) const
Return true if the given SDNode can be copied during scheduling even if it has glue.
Definition: TargetInstrInfo.h:1223
llvm::TargetInstrInfo::verifyInstruction
virtual bool verifyInstruction(const MachineInstr &MI, StringRef &ErrInfo) const
Perform target-specific instruction verification.
Definition: TargetInstrInfo.h:1670
llvm::TargetInstrInfo::getInsertSubregLikeInputs
virtual bool getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPair &BaseReg, RegSubRegPairAndIdx &InsertedReg) const
Target-dependent implementation of getInsertSubregInputs.
Definition: TargetInstrInfo.h:1289
llvm::TargetInstrInfo::PipelinerLoopInfo::adjustTripCount
virtual void adjustTripCount(int TripCountAdjust)=0
Modify the loop such that the trip count is OriginalTC + TripCountAdjust.
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::TargetInstrInfo::optimizeLoadInstr
virtual MachineInstr * optimizeLoadInstr(MachineInstr &MI, const MachineRegisterInfo *MRI, Register &FoldAsLoadDefReg, MachineInstr *&DefMI) const
Try to remove the load by folding it to a register operand at the use.
Definition: TargetInstrInfo.h:1581
llvm::TargetInstrInfo::setSpecialOperandAttr
virtual void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2, MachineInstr &NewMI1, MachineInstr &NewMI2) const
This is an architecture-specific helper function of reassociateOps.
Definition: TargetInstrInfo.h:1214
llvm::TargetInstrInfo::FoldImmediate
virtual bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg, MachineRegisterInfo *MRI) const
'Reg' is known to be defined by a move immediate instruction, try to fold the immediate into the use ...
Definition: TargetInstrInfo.h:1594
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::TargetInstrInfo::buildOutlinedFrame
virtual void buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF, const outliner::OutlinedFunction &OF) const
Insert a custom frame for outlined functions.
Definition: TargetInstrInfo.h:1951
llvm::TargetInstrInfo::getExtendResourceLenLimit
virtual int getExtendResourceLenLimit() const
The limit on resource length extension we accept in MachineCombiner Pass.
Definition: TargetInstrInfo.h:1210
MCInstrInfo.h
llvm::DFAPacketizer
Definition: DFAPacketizer.h:48
llvm::TargetInstrInfo::RegSubRegPairAndIdx::RegSubRegPairAndIdx
RegSubRegPairAndIdx(Register Reg=Register(), unsigned SubReg=0, unsigned SubIdx=0)
Definition: TargetInstrInfo.h:515
llvm::TargetInstrInfo::getRegSequenceLikeInputs
virtual bool getRegSequenceLikeInputs(const MachineInstr &MI, unsigned DefIdx, SmallVectorImpl< RegSubRegPairAndIdx > &InputRegs) const
Target-dependent implementation of getRegSequenceInputs.
Definition: TargetInstrInfo.h:1260
llvm::TargetInstrInfo::isReassociationCandidate
bool isReassociationCandidate(const MachineInstr &Inst, bool &Commuted) const
Return true if the input \P Inst is part of a chain of dependent ops that are suitable for reassociat...
Definition: TargetInstrInfo.cpp:747
llvm::TargetInstrInfo::shouldOutlineFromFunctionByDefault
virtual bool shouldOutlineFromFunctionByDefault(MachineFunction &MF) const
Return true if the function should be outlined from by default.
Definition: TargetInstrInfo.h:1979
Domain
Domain
Definition: CorrelatedValuePropagation.cpp:710
TBB
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
Definition: RISCVRedundantCopyElimination.cpp:76
llvm::TargetInstrInfo::expandPostRAPseudo
virtual bool expandPostRAPseudo(MachineInstr &MI) const
This function is called for all pseudo instructions that remain after register allocation.
Definition: TargetInstrInfo.h:1091
llvm::TargetInstrInfo::insertNoop
virtual void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const
Insert a noop into the instruction stream at the specified point.
Definition: TargetInstrInfo.cpp:65
llvm::TargetInstrInfo::getNumMicroOps
virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData, const MachineInstr &MI) const
Return the number of u-operations the given machine instruction will be decoded to on the target cpu.
Definition: TargetInstrInfo.cpp:1119
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:197
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48
llvm::TargetInstrInfo::isTailCall
virtual bool isTailCall(const MachineInstr &Inst) const
Determines whether Inst is a tail call instruction.
Definition: TargetInstrInfo.h:1891
llvm::TargetInstrInfo::MachineBranchPredicate::PRED_INVALID
@ PRED_INVALID
Definition: TargetInstrInfo.h:658
llvm::TargetInstrInfo::~TargetInstrInfo
virtual ~TargetInstrInfo()
llvm::TargetInstrInfo::isReallyTriviallyReMaterializable
virtual bool isReallyTriviallyReMaterializable(const MachineInstr &MI) const
For instructions with opcodes for which the M_REMATERIALIZABLE flag is set, this hook lets the target...
Definition: TargetInstrInfo.h:151
llvm::TargetInstrInfo::analyzeSelect
virtual bool analyzeSelect(const MachineInstr &MI, SmallVectorImpl< MachineOperand > &Cond, unsigned &TrueOp, unsigned &FalseOp, bool &Optimizable) const
Analyze the given select instruction, returning true if it cannot be understood.
Definition: TargetInstrInfo.h:949
llvm::TargetInstrInfo::isProfitableToDupForIfCvt
virtual bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const
Return true if it's profitable for if-converter to duplicate instructions of specified accumulated in...
Definition: TargetInstrInfo.h:848
llvm::TargetInstrInfo::shouldScheduleLoadsNear
virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1, int64_t Offset2, unsigned NumLoads) const
This is a used by the pre-regalloc scheduler to determine (in conjunction with areLoadsFromSameBasePt...
Definition: TargetInstrInfo.h:1341
llvm::TargetInstrInfo::mergeOutliningCandidateAttributes
virtual void mergeOutliningCandidateAttributes(Function &F, std::vector< outliner::Candidate > &Candidates) const
Optional target hook to create the LLVM IR attributes for the outlined function.
Definition: TargetInstrInfo.cpp:1404
MachineCombinerPattern.h
llvm::TargetInstrInfo::isStackSlotCopy
virtual bool isStackSlotCopy(const MachineInstr &MI, int &DestFrameIndex, int &SrcFrameIndex) const
Return true if the specified machine instruction is a copy of one stack slot to another and has no ot...
Definition: TargetInstrInfo.h:339
llvm::TargetInstrInfo::reverseBranchCondition
virtual bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const
Reverses the branch condition of the specified condition list, returning false on success and true if...
Definition: TargetInstrInfo.h:1425
llvm::TargetInstrInfo::defaultDefLatency
unsigned defaultDefLatency(const MCSchedModel &SchedModel, const MachineInstr &DefMI) const
Return the default expected latency for a def based on its opcode.
Definition: TargetInstrInfo.cpp:1135
llvm::TargetInstrInfo::PipelinerLoopInfo::disposed
virtual void disposed()=0
Called when the loop is being removed.
llvm::TargetInstrInfo::isMBBSafeToOutlineFrom
virtual bool isMBBSafeToOutlineFrom(MachineBasicBlock &MBB, unsigned &Flags) const
Optional target hook that returns true if MBB is safe to outline from, and returns any target-specifi...
Definition: TargetInstrInfo.cpp:1424
llvm::TargetInstrInfo::shouldSink
virtual bool shouldSink(const MachineInstr &MI) const
Return true if the instruction should be sunk by MachineSink.
Definition: TargetInstrInfo.h:386
llvm::None
const NoneType None
Definition: None.h:24
llvm::TargetInstrInfo::optimizeSelect
virtual MachineInstr * optimizeSelect(MachineInstr &MI, SmallPtrSetImpl< MachineInstr * > &NewMIs, bool PreferFalse=false) const
Given a select instruction that was understood by analyzeSelect and returned Optimizable = true,...
Definition: TargetInstrInfo.h:972
BranchProbability.h
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::TargetInstrInfo::isExtendLikelyToBeFolded
virtual bool isExtendLikelyToBeFolded(MachineInstr &ExtMI, MachineRegisterInfo &MRI) const
Given the generic extension instruction ExtMI, returns true if this extension is a likely candidate f...
Definition: TargetInstrInfo.h:1992
llvm::TargetInstrInfo::MachineBranchPredicate::PRED_EQ
@ PRED_EQ
Definition: TargetInstrInfo.h:656
llvm::TargetInstrInfo::hasReassociableOperands
virtual bool hasReassociableOperands(const MachineInstr &Inst, const MachineBasicBlock *MBB) const
Return true when \P Inst has reassociable operands in the same \P MBB.
Definition: TargetInstrInfo.cpp:698
llvm::TargetInstrInfo::isCoalescableExtInstr
virtual bool isCoalescableExtInstr(const MachineInstr &MI, Register &SrcReg, Register &DstReg, unsigned &SubIdx) const
Return true if the instruction is a "coalescable" extension instruction.
Definition: TargetInstrInfo.h:255
llvm::TargetInstrInfo::getBranchDestBlock
virtual MachineBasicBlock * getBranchDestBlock(const MachineInstr &MI) const
Definition: TargetInstrInfo.h:598
llvm::TargetInstrInfo::analyzeLoopForPipelining
virtual std::unique_ptr< PipelinerLoopInfo > analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const
Analyze loop L, which must be a single-basic-block loop, and if the conditions can be understood enou...
Definition: TargetInstrInfo.h:779
llvm::TargetInstrInfo::MachineBranchPredicate::SingleUseCondition
bool SingleUseCondition
SingleUseCondition is true if ConditionDef is dead except for the branch(es) at the end of the basic ...
Definition: TargetInstrInfo.h:671
llvm::TargetInstrInfo::RegSubRegPair::RegSubRegPair
RegSubRegPair(Register Reg=Register(), unsigned SubReg=0)
Definition: TargetInstrInfo.h:498
llvm::TargetInstrInfo::convertToThreeAddress
virtual MachineInstr * convertToThreeAddress(MachineInstr &MI, LiveVariables *LV, LiveIntervals *LIS) const
This method must be implemented by targets that set the M_CONVERTIBLE_TO_3_ADDR flag.
Definition: TargetInstrInfo.h:431
llvm::TargetInstrInfo::getBaseAndOffsetPosition
virtual bool getBaseAndOffsetPosition(const MachineInstr &MI, unsigned &BasePos, unsigned &OffsetPos) const
Return true if the instruction contains a base register and offset.
Definition: TargetInstrInfo.h:1372
llvm::CmpInst
This class is the base class for the comparison instructions.
Definition: InstrTypes.h:709
llvm::TargetInstrInfo::createMIROperandComment
virtual std::string createMIROperandComment(const MachineInstr &MI, const MachineOperand &Op, unsigned OpIdx, const TargetRegisterInfo *TRI) const
Definition: TargetInstrInfo.cpp:1347
llvm::TargetInstrInfo::isStoreToStackSlot
virtual unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex, unsigned &MemBytes) const
Optional extension of isStoreToStackSlot that returns the number of bytes stored to the stack.
Definition: TargetInstrInfo.h:312
llvm::TargetInstrInfo::isStoreToStackSlot
virtual unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const
If the specified machine instruction is a direct store to a stack slot, return the virtual or physica...
Definition: TargetInstrInfo.h:303
llvm::TargetInstrInfo::getOutliningType
virtual outliner::InstrType getOutliningType(MachineBasicBlock::iterator &MIT, unsigned Flags) const
Returns how or if MI should be outlined.
Definition: TargetInstrInfo.h:1940
llvm::TargetInstrInfo::isAssociativeAndCommutative
virtual bool isAssociativeAndCommutative(const MachineInstr &Inst) const
Return true when \P Inst is both associative and commutative.
Definition: TargetInstrInfo.h:1174
llvm::TargetInstrInfo::PredicateInstruction
virtual bool PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Pred) const
Convert the instruction into a predicated instruction.
Definition: TargetInstrInfo.cpp:329
llvm::TargetInstrInfo::canMakeTailCallConditional
virtual bool canMakeTailCallConditional(SmallVectorImpl< MachineOperand > &Cond, const MachineInstr &TailCall) const
Returns true if the tail call can be made conditional on BranchCond.
Definition: TargetInstrInfo.h:1462
llvm::TargetInstrInfo::shouldHoist
virtual bool shouldHoist(const MachineInstr &MI, const MachineLoop *FromLoop) const
Return false if the instruction should not be hoisted by MachineLICM.
Definition: TargetInstrInfo.h:394
llvm::DenseMapInfo< TargetInstrInfo::RegSubRegPair >::getHashValue
static unsigned getHashValue(const TargetInstrInfo::RegSubRegPair &Val)
Reuse getHashValue implementation from std::pair<unsigned, unsigned>.
Definition: TargetInstrInfo.h:2040
llvm::TargetInstrInfo::getStackSlotRange
virtual bool getStackSlotRange(const TargetRegisterClass *RC, unsigned SubIdx, unsigned &Size, unsigned &Offset, const MachineFunction &MF) const
Compute the size in bytes and offset within a stack slot of a spilled register or subregister.
Definition: TargetInstrInfo.cpp:387
llvm::TargetInstrInfo::getSerializableBitmaskMachineOperandTargetFlags
virtual ArrayRef< std::pair< unsigned, const char * > > getSerializableBitmaskMachineOperandTargetFlags() const
Return an array that contains the bitmask target flag values and their names.
Definition: TargetInstrInfo.h:1874
llvm::MachineLoop
Definition: MachineLoopInfo.h:44
llvm::TargetInstrInfo::RegSubRegPair::Reg
Register Reg
Definition: TargetInstrInfo.h:495
llvm::TargetSchedModel
Provide an instruction scheduling machine model to CodeGen passes.
Definition: TargetSchedule.h:30
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
VirtRegMap.h
llvm::ExtAddrMode::BaseReg
Register BaseReg
Definition: TargetInstrInfo.h:88
llvm::TargetInstrInfo::isPredicated
virtual bool isPredicated(const MachineInstr &MI) const
Returns true if the instruction is already predicated.
Definition: TargetInstrInfo.h:1445
llvm::TargetInstrInfo::getAddrModeFromMemoryOp
virtual Optional< ExtAddrMode > getAddrModeFromMemoryOp(const MachineInstr &MemI, const TargetRegisterInfo *TRI) const
Target dependent implementation to get the values constituting the address MachineInstr that is acces...
Definition: TargetInstrInfo.h:1383
llvm::TargetInstrInfo::TargetInstrInfo
TargetInstrInfo(unsigned CFSetupOpcode=~0u, unsigned CFDestroyOpcode=~0u, unsigned CatchRetOpcode=~0u, unsigned ReturnOpcode=~0u)
Definition: TargetInstrInfo.h:100
llvm::outliner::Candidate
An individual sequence of instructions to be replaced with a call to an outlined function.
Definition: MachineOutliner.h:37
llvm::TargetInstrInfo::breakPartialRegDependency
virtual void breakPartialRegDependency(MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const
Insert a dependency-breaking instruction before MI to eliminate an unwanted dependency on OpNum.
Definition: TargetInstrInfo.h:1788
llvm::DenseMap< unsigned, unsigned >
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::RegScavenger
Definition: RegisterScavenging.h:34
llvm::TargetInstrInfo::hasStoreToStackSlot
virtual bool hasStoreToStackSlot(const MachineInstr &MI, SmallVectorImpl< const MachineMemOperand * > &Accesses) const
If the specified machine instruction has a store to a stack slot, return true along with the FrameInd...
Definition: TargetInstrInfo.cpp:373
ArrayRef.h
llvm::TargetInstrInfo::isStoreToStackSlotPostFE
virtual unsigned isStoreToStackSlotPostFE(const MachineInstr &MI, int &FrameIndex) const
Check for post-frame ptr elimination stack locations as well.
Definition: TargetInstrInfo.h:321
llvm::ParamLoadedValue
std::pair< MachineOperand, DIExpression * > ParamLoadedValue
Definition: TargetInstrInfo.h:67
llvm::TargetInstrInfo::commuteInstruction
MachineInstr * commuteInstruction(MachineInstr &MI, bool NewMI=false, unsigned OpIdx1=CommuteAnyOperandIndex, unsigned OpIdx2=CommuteAnyOperandIndex) const
This method commutes the operands of the given machine instruction MI.
Definition: TargetInstrInfo.cpp:248
llvm::TargetInstrInfo::isAsCheapAsAMove
virtual bool isAsCheapAsAMove(const MachineInstr &MI) const
Return true if the instruction is as cheap as a move instruction.
Definition: TargetInstrInfo.h:377
RegSubRegPair
TargetInstrInfo::RegSubRegPair RegSubRegPair
Definition: PeepholeOptimizer.cpp:100
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::TargetInstrInfo::getInstSizeInBytes
virtual unsigned getInstSizeInBytes(const MachineInstr &MI) const
Returns the size in bytes of the specified MachineInstr, or ~0U when this function is not implemented...
Definition: TargetInstrInfo.h:369
llvm::TargetInstrInfo::insertUnconditionalBranch
unsigned insertUnconditionalBranch(MachineBasicBlock &MBB, MachineBasicBlock *DestBB, const DebugLoc &DL, int *BytesAdded=nullptr) const
Definition: TargetInstrInfo.h:720
llvm::RegisterClassInfo
Definition: RegisterClassInfo.h:29
llvm::TargetInstrInfo::describeLoadedValue
virtual Optional< ParamLoadedValue > describeLoadedValue(const MachineInstr &MI, Register Reg) const
Produce the expression describing the MI loading a value into the physical register Reg.
Definition: TargetInstrInfo.cpp:1174
llvm::TargetInstrInfo::MachineBranchPredicate::ComparePredicate
ComparePredicate
Definition: TargetInstrInfo.h:655
llvm::TargetInstrInfo::PipelinerLoopInfo::~PipelinerLoopInfo
virtual ~PipelinerLoopInfo()
llvm::TargetInstrInfo::isLoadFromStackSlotPostFE
virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI, int &FrameIndex) const
Check for post-frame ptr elimination stack locations as well.
Definition: TargetInstrInfo.h:283
MIRFormatter.h
llvm::TargetInstrInfo::getSerializableMachineMemOperandTargetFlags
virtual ArrayRef< std::pair< MachineMemOperand::Flags, const char * > > getSerializableMachineMemOperandTargetFlags() const
Return an array that contains the MMO target flag values and their names.
Definition: TargetInstrInfo.h:1884
llvm::TargetInstrInfo::isPCRelRegisterOperandLegal
virtual bool isPCRelRegisterOperandLegal(const MachineOperand &MO) const
Allow targets to tell MachineVerifier whether a specific register MachineOperand can be used as part ...
Definition: TargetInstrInfo.h:1003
llvm::TargetInstrInfo::produceSameValue
virtual bool produceSameValue(const MachineInstr &MI0, const MachineInstr &MI1, const MachineRegisterInfo *MRI=nullptr) const
Return true if two machine instructions would produce identical values.
Definition: TargetInstrInfo.cpp:427
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:97
llvm::Module
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
llvm::ScheduleDAGMI
ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...
Definition: MachineScheduler.h:273
llvm::TargetInstrInfo::createPHISourceCopy
virtual MachineInstr * createPHISourceCopy(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsPt, const DebugLoc &DL, Register Src, unsigned SrcSubReg, Register Dst) const
During PHI eleimination lets target to make necessary checks and insert the copy to the PHI destinati...
Definition: TargetInstrInfo.h:1915
llvm::RegImmPair
Used to describe a register and immediate addition.
Definition: TargetInstrInfo.h:78
llvm::CodeGenOpt::Aggressive
@ Aggressive
Definition: CodeGen.h:56
llvm::MachineInstr::isReturn
bool isReturn(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:862
llvm::TargetInstrInfo::getPatchpointUnfoldableRange
virtual std::pair< unsigned, unsigned > getPatchpointUnfoldableRange(const MachineInstr &MI) const
For a patchpoint, stackmap, or statepoint intrinsic, return the range of operands which can't be fold...
Definition: TargetInstrInfo.cpp:476
llvm::TargetInstrInfo::MachineBranchPredicate::Predicate
ComparePredicate Predicate
Definition: TargetInstrInfo.h:661
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::TargetInstrInfo::isLegalToSplitMBBAt
virtual bool isLegalToSplitMBBAt(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const
Return true if it's legal to split the given basic block at the specified instruction (i....
Definition: TargetInstrInfo.h:812
llvm::TargetInstrInfo::analyzeLoop
virtual bool analyzeLoop(MachineLoop &L, MachineInstr *&IndVarInst, MachineInstr *&CmpInst) const
Analyze the loop code, return true if it cannot be understood.
Definition: TargetInstrInfo.h:786
llvm::TargetInstrInfo::getSPAdjust
virtual int getSPAdjust(const MachineInstr &MI) const
Returns the actual stack pointer adjustment made by an instruction as part of a call sequence.
Definition: TargetInstrInfo.cpp:997
llvm::ScheduleDAG
Definition: ScheduleDAG.h:554
llvm::TargetInstrInfo::getPredicationCost
virtual unsigned getPredicationCost(const MachineInstr &MI) const
Definition: TargetInstrInfo.cpp:1146
llvm::TargetInstrInfo::hasLoadFromStackSlot
virtual bool hasLoadFromStackSlot(const MachineInstr &MI, SmallVectorImpl< const MachineMemOperand * > &Accesses) const
If the specified machine instruction has a load from a stack slot, return true along with the FrameIn...
Definition: TargetInstrInfo.cpp:359
llvm::TargetInstrInfo::ClobbersPredicate
virtual bool ClobbersPredicate(MachineInstr &MI, std::vector< MachineOperand > &Pred, bool SkipDead) const
If the specified instruction defines any predicate or condition code register(s) used for predication...
Definition: TargetInstrInfo.h:1493
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
None.h
llvm::TargetInstrInfo::RegSubRegPair::SubReg
unsigned SubReg
Definition: TargetInstrInfo.h:496
Cond
SmallVector< MachineOperand, 4 > Cond
Definition: BasicBlockSections.cpp:137
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
MBBI
MachineBasicBlock MachineBasicBlock::iterator MBBI
Definition: AArch64SLSHardening.cpp:75
llvm::TargetInstrInfo::isGenericAtomicRMWOpcode
static bool isGenericAtomicRMWOpcode(unsigned Opc)
Definition: TargetInstrInfo.h:113
llvm::TargetInstrInfo::getTailDuplicateSize
virtual unsigned getTailDuplicateSize(CodeGenOpt::Level OptLevel) const
Returns the target-specific default value for tail duplication.
Definition: TargetInstrInfo.h:2008
llvm::TargetInstrInfo::reMaterialize
virtual void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, unsigned SubIdx, const MachineInstr &Orig, const TargetRegisterInfo &TRI) const
Re-issue the specified 'original' instruction at the specific location targeting a new destination re...
Definition: TargetInstrInfo.cpp:417
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::TargetInstrInfo::storeRegToStackSlot
virtual void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const
Store the specified register of the given register class to the specified stack frame index.
Definition: TargetInstrInfo.h:1064
llvm::BranchProbability
Definition: BranchProbability.h:30
llvm::TargetInstrInfo::extraSizeToPredicateInstructions
virtual unsigned extraSizeToPredicateInstructions(const MachineFunction &MF, unsigned NumInsts) const
Return the increase in code size needed to predicate a contiguous run of NumInsts instructions.
Definition: TargetInstrInfo.h:856
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
Module
Machine Check Debug Module
Definition: MachineCheckDebugify.cpp:122
Node
Definition: ItaniumDemangle.h:155
llvm::CodeGenOpt::Level
Level
Definition: CodeGen.h:52
llvm::TargetInstrInfo::isUnpredicatedTerminator
bool isUnpredicatedTerminator(const MachineInstr &MI) const
Returns true if the instruction is a terminator instruction that has not been predicated.
Definition: TargetInstrInfo.cpp:318
llvm::MipsISD::TailCall
@ TailCall
Definition: MipsISelLowering.h:65
llvm::TargetInstrInfo::isFrameInstr
bool isFrameInstr(const MachineInstr &I) const
Returns true if the argument is a frame pseudo instruction.
Definition: TargetInstrInfo.h:205
llvm::TargetSubtargetInfo
TargetSubtargetInfo - Generic base class for all target subtargets.
Definition: TargetSubtargetInfo.h:60
llvm::DenseMapInfo< TargetInstrInfo::RegSubRegPair >::getEmptyKey
static TargetInstrInfo::RegSubRegPair getEmptyKey()
Definition: TargetInstrInfo.h:2028
llvm::TargetInstrInfo::predictBranchSizeForIfCvt
virtual unsigned predictBranchSizeForIfCvt(MachineInstr &MI) const
Return an estimate for the code size reduction (in bytes) which will be caused by removing the given ...
Definition: TargetInstrInfo.h:863
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::TargetInstrInfo::fixCommutedOpIndices
static bool fixCommutedOpIndices(unsigned &ResultIdx1, unsigned &ResultIdx2, unsigned CommutableOpIdx1, unsigned CommutableOpIdx2)
Assigns the (CommutableOpIdx1, CommutableOpIdx2) pair of commutable operand indices to (ResultIdx1,...
Definition: TargetInstrInfo.cpp:263
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::TargetInstrInfo::isProfitableToUnpredicate
virtual bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, MachineBasicBlock &FMBB) const
Return true if it's profitable to unpredicate one side of a 'diamond', i.e.
Definition: TargetInstrInfo.h:878
llvm::TargetInstrInfo::isSchedulingBoundary
virtual bool isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const
Test if the given instruction should be considered a scheduling boundary.
Definition: TargetInstrInfo.cpp:1021
llvm::TargetInstrInfo::isFunctionSafeToOutlineFrom
virtual bool isFunctionSafeToOutlineFrom(MachineFunction &MF, bool OutlineFromLinkOnceODRs) const
Return true if the function can safely be outlined from.
Definition: TargetInstrInfo.h:1972
llvm::ISD::FrameIndex
@ FrameIndex
Definition: ISDOpcodes.h:80
llvm::TargetInstrInfo::reduceLoopCount
virtual unsigned reduceLoopCount(MachineBasicBlock &MBB, MachineBasicBlock &PreHeader, MachineInstr *IndVar, MachineInstr &Cmp, SmallVectorImpl< MachineOperand > &Cond, SmallVectorImpl< MachineInstr * > &PrevInsts, unsigned Iter, unsigned MaxIter) const
Generate code to reduce the loop iteration by one and check if the loop is finished.
Definition: TargetInstrInfo.h:795
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::MCInstrInfo
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:26
llvm::TargetInstrInfo::getCallFrameDestroyOpcode
unsigned getCallFrameDestroyOpcode() const
Definition: TargetInstrInfo.h:202
llvm::TargetInstrInfo::getExecutionDomain
virtual std::pair< uint16_t, uint16_t > getExecutionDomain(const MachineInstr &MI) const
Return the current execution domain and bit mask of possible domains for instruction.
Definition: TargetInstrInfo.h:1695
llvm::TargetInstrInfo::isIgnorableUse
virtual bool isIgnorableUse(const MachineOperand &MO) const
Given MO is a PhysReg use return if it can be ignored for the purpose of instruction rematerializatio...
Definition: TargetInstrInfo.h:139
llvm::TargetInstrInfo::isUnconditionalTailCall
virtual bool isUnconditionalTailCall(const MachineInstr &MI) const
Returns true if MI is an unconditional tail call.
Definition: TargetInstrInfo.h:1457
llvm::TargetInstrInfo::isProfitableToIfCvt
virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const
Return true if it's profitable to predicate instructions with accumulated instruction latency of "Num...
Definition: TargetInstrInfo.h:822
llvm::TargetInstrInfo::isPostIncrement
virtual bool isPostIncrement(const MachineInstr &MI) const
Return true for post-incremented instructions.
Definition: TargetInstrInfo.h:1442
llvm::DestSourcePair
Definition: TargetInstrInfo.h:69
llvm::TargetInstrInfo::preservesZeroValueInReg
virtual bool preservesZeroValueInReg(const MachineInstr *MI, const Register NullValueReg, const TargetRegisterInfo *TRI) const
Returns true if MI's Def is NullValueReg, and the MI does not change the Zero value.
Definition: TargetInstrInfo.h:1393
llvm::TargetInstrInfo::operator=
TargetInstrInfo & operator=(const TargetInstrInfo &)=delete
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:348
llvm::TargetInstrInfo::getMemOperandsWithOffsetWidth
virtual bool getMemOperandsWithOffsetWidth(const MachineInstr &MI, SmallVectorImpl< const MachineOperand * > &BaseOps, int64_t &Offset, bool &OffsetIsScalable, unsigned &Width, const TargetRegisterInfo *TRI) const
Get zero or more base operands and the byte offset of an instruction that reads/writes memory.
Definition: TargetInstrInfo.h:1362
llvm::TargetInstrInfo::analyzeBranch
virtual bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const
Analyze the branching code at the end of MBB, returning true if it cannot be understood (e....
Definition: TargetInstrInfo.h:641
llvm::TargetInstrInfo::reassociateOps
void reassociateOps(MachineInstr &Root, MachineInstr &Prev, MachineCombinerPattern Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, DenseMap< unsigned, unsigned > &InstrIdxForVirtReg) const
Attempt to reassociate \P Root and \P Prev according to \P Pattern to reduce critical path length.
Definition: TargetInstrInfo.cpp:805
llvm::TargetInstrInfo::getRegSequenceInputs
bool getRegSequenceInputs(const MachineInstr &MI, unsigned DefIdx, SmallVectorImpl< RegSubRegPairAndIdx > &InputRegs) const
Build the equivalent inputs of a REG_SEQUENCE for the given MI and DefIdx.
Definition: TargetInstrInfo.cpp:1266
llvm::TargetInstrInfo::PipelinerLoopInfo::createTripCountGreaterCondition
virtual Optional< bool > createTripCountGreaterCondition(int TC, MachineBasicBlock &MBB, SmallVectorImpl< MachineOperand > &Cond)=0
Create a condition to determine if the trip count of the loop is greater than TC, where TC is always ...
llvm::TargetInstrInfo::CreateTargetMIHazardRecognizer
virtual ScheduleHazardRecognizer * CreateTargetMIHazardRecognizer(const InstrItineraryData *, const ScheduleDAGMI *DAG) const
Allocate and return a hazard recognizer to use for this target when scheduling the machine instructio...
Definition: TargetInstrInfo.cpp:1057
llvm::ExtAddrMode::Displacement
int64_t Displacement
Definition: TargetInstrInfo.h:91
llvm::TargetInstrInfo::areMemAccessesTriviallyDisjoint
virtual bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb) const
Sometimes, it is possible for the target to tell, even without aliasing information,...
Definition: TargetInstrInfo.h:1809
llvm::ExtAddrMode::Scale
int64_t Scale
Definition: TargetInstrInfo.h:90
llvm::MCSchedModel
Machine model for scheduling, bundling, and heuristics.
Definition: MCSchedule.h:244
llvm::TargetInstrInfo::getInstrLatency
virtual unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const
Compute the instruction latency of a given instruction.
Definition: TargetInstrInfo.cpp:1150
llvm::LiveIntervals
Definition: LiveIntervals.h:53
isEqual
static bool isEqual(const Function &Caller, const Function &Callee)
Definition: Attributes.cpp:1869
llvm::TargetInstrInfo::isBasicBlockPrologue
virtual bool isBasicBlockPrologue(const MachineInstr &MI) const
True if the instruction is bound to the top of its basic block and no other instructions shall be ins...
Definition: TargetInstrInfo.h:1898
llvm::AMDGPU::Hwreg::Width
Width
Definition: SIDefines.h:439
llvm::TargetInstrInfo::optimizeCompareInstr
virtual bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int64_t Mask, int64_t Value, const MachineRegisterInfo *MRI) const
See if the comparison instruction can be converted into something more efficient.
Definition: TargetInstrInfo.h:1566
llvm::TargetInstrInfo::hasLowDefLatency
virtual bool hasLowDefLatency(const TargetSchedModel &SchedModel, const MachineInstr &DefMI, unsigned DefIdx) const
Compute operand latency of a def of 'Reg'.
Definition: TargetInstrInfo.cpp:1161
llvm::TargetInstrInfo::MachineBranchPredicate::LHS
MachineOperand LHS
Definition: TargetInstrInfo.h:662
llvm::TargetInstrInfo::getCallFrameSetupOpcode
unsigned getCallFrameSetupOpcode() const
These methods return the opcode of the frame setup/destroy instructions if they exist (-1 otherwise).
Definition: TargetInstrInfo.h:201
llvm::TargetInstrInfo::isUnspillableTerminatorImpl
virtual bool isUnspillableTerminatorImpl(const MachineInstr *MI) const
Return true if the given terminator MI is not expected to spill.
Definition: TargetInstrInfo.h:1024
llvm::TargetInstrInfo::getMIRFormatter
virtual const MIRFormatter * getMIRFormatter() const
Return MIR formatter to format/parse MIR operands.
Definition: TargetInstrInfo.h:1999
llvm::MIRFormatter
MIRFormater - Interface to format MIR operand based on target.
Definition: MIRFormatter.h:28
llvm::TargetInstrInfo::shouldReduceRegisterPressure
virtual bool shouldReduceRegisterPressure(MachineBasicBlock *MBB, RegisterClassInfo *RegClassInfo) const
Return true if target supports reassociation of instructions in machine combiner pass to reduce regis...
Definition: TargetInstrInfo.h:1151
llvm::TargetInstrInfo::PipelinerLoopInfo::setPreheader
virtual void setPreheader(MachineBasicBlock *NewPreheader)=0
Called when the loop's preheader has been modified to NewPreheader.
llvm::Pattern
Definition: FileCheckImpl.h:614
llvm::TargetInstrInfo::foldMemoryOperandImpl
virtual MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const
Target-dependent implementation for foldMemoryOperand.
Definition: TargetInstrInfo.h:1232
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:357
llvm::DestSourcePair::Source
const MachineOperand * Source
Definition: TargetInstrInfo.h:71
llvm::TargetInstrInfo::getMemOperandAACheckLimit
virtual unsigned getMemOperandAACheckLimit() const
Return the maximal number of alias checks on memory operands.
Definition: TargetInstrInfo.h:1839
llvm::TargetInstrInfo::foldMemoryOperand
MachineInstr * foldMemoryOperand(MachineInstr &MI, ArrayRef< unsigned > Ops, int FI, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const
Attempt to fold a load or store of the specified stack slot into the specified machine instruction fo...
Definition: TargetInstrInfo.cpp:558
MachineInstrBuilder.h
llvm::TargetInstrInfo::findCommutedOpIndices
virtual bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const
Returns true iff the routine could find two commutable operands in the given machine instruction.
Definition: TargetInstrInfo.cpp:294
N
#define N
DefMI
MachineInstrBuilder MachineInstrBuilder & DefMI
Definition: AArch64ExpandPseudoInsts.cpp:106
llvm::TargetInstrInfo::genAlternativeCodeSequence
virtual void genAlternativeCodeSequence(MachineInstr &Root, MachineCombinerPattern Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, DenseMap< unsigned, unsigned > &InstIdxForVirtReg) const
When getMachineCombinerPatterns() finds patterns, this function generates the instructions that could...
Definition: TargetInstrInfo.cpp:891
llvm::TargetInstrInfo::getOperandLatency
virtual int getOperandLatency(const InstrItineraryData *ItinData, SDNode *DefNode, unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const
Definition: TargetInstrInfo.cpp:1088
llvm::DenseMapInfo< TargetInstrInfo::RegSubRegPair >::getTombstoneKey
static TargetInstrInfo::RegSubRegPair getTombstoneKey()
Definition: TargetInstrInfo.h:2033
llvm::TargetInstrInfo::isFrameSetup
bool isFrameSetup(const MachineInstr &I) const
Returns true if the argument is a frame setup pseudo instruction.
Definition: TargetInstrInfo.h:211
llvm::TargetInstrInfo::PipelinerLoopInfo::shouldIgnoreForPipelining
virtual bool shouldIgnoreForPipelining(const MachineInstr *MI) const =0
Return true if the given instruction should not be pipelined and should be ignored.
llvm::TargetInstrInfo::CreateTargetPostRAHazardRecognizer
virtual ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const MachineFunction &MF) const
Allocate and return a hazard recognizer to use for by non-scheduling passes.
Definition: TargetInstrInfo.h:1545
llvm::RegImmPair::RegImmPair
RegImmPair(Register Reg, int64_t Imm)
Definition: TargetInstrInfo.h:82
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
llvm::TargetInstrInfo::CreateTargetPostRAHazardRecognizer
virtual ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const InstrItineraryData *, const ScheduleDAG *DAG) const
Allocate and return a hazard recognizer to use for this target when scheduling the machine instructio...
Definition: TargetInstrInfo.cpp:1064
llvm::TargetInstrInfo::setExecutionDomain
virtual void setExecutionDomain(MachineInstr &MI, unsigned Domain) const
Change the opcode of MI to execute in Domain.
Definition: TargetInstrInfo.h:1703
MachineOperand.h
DenseMapInfo.h
llvm::SmallPtrSetImpl
A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...
Definition: SmallPtrSet.h:344
llvm::TargetInstrInfo::MachineBranchPredicate::TrueDest
MachineBasicBlock * TrueDest
Definition: TargetInstrInfo.h:664
llvm::CallingConv::Tail
@ Tail
Attemps to make calls as fast as possible while guaranteeing that tail call optimization can always b...
Definition: CallingConv.h:76
llvm::LiveVariables
Definition: LiveVariables.h:47
llvm::MCInstrInfo::get
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
Definition: MCInstrInfo.h:63
llvm::DestSourcePair::DestSourcePair
DestSourcePair(const MachineOperand &Dest, const MachineOperand &Src)
Definition: TargetInstrInfo.h:73
llvm::TargetInstrInfo::getSerializableDirectMachineOperandTargetFlags
virtual ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const
Return an array that contains the direct target flag values and their names.
Definition: TargetInstrInfo.h:1864
llvm::TargetInstrInfo::getOpcodeAfterMemoryUnfold
virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, bool UnfoldLoad, bool UnfoldStore, unsigned *LoadRegIndex=nullptr) const
Returns the opcode of the would be new instruction after load / store are unfolded from an instructio...
Definition: TargetInstrInfo.h:1318
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::TargetInstrInfo::CommuteAnyOperandIndex
static const unsigned CommuteAnyOperandIndex
Definition: TargetInstrInfo.h:441
MachineFunction.h
llvm::ScheduleHazardRecognizer
HazardRecognizer - This determines whether or not an instruction can be issued this cycle,...
Definition: ScheduleHazardRecognizer.h:25
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::TargetInstrInfo::isAddImmediate
virtual Optional< RegImmPair > isAddImmediate(const MachineInstr &MI, Register Reg) const
If the specific machine instruction is an instruction that adds an immediate value and a physical reg...
Definition: TargetInstrInfo.h:1046
llvm::TargetInstrInfo::finalizeInsInstrs
virtual void finalizeInsInstrs(MachineInstr &Root, MachineCombinerPattern &P, SmallVectorImpl< MachineInstr * > &InsInstrs) const
Fix up the placeholder we may add in genAlternativeCodeSequence().
Definition: TargetInstrInfo.h:1158
llvm::TargetInstrInfo::MachineBranchPredicate::MachineBranchPredicate
MachineBranchPredicate()=default
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::TargetInstrInfo::SubsumesPredicate
virtual bool SubsumesPredicate(ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const
Returns true if the first specified predicate subsumes the second, e.g.
Definition: TargetInstrInfo.h:1481
llvm::InstrItineraryData
Itinerary data supplied by a subtarget to be used by a target.
Definition: MCInstrItineraries.h:109
llvm::TargetInstrInfo::isProfitableToIfCvt
virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumTCycles, unsigned ExtraTCycles, MachineBasicBlock &FMBB, unsigned NumFCycles, unsigned ExtraFCycles, BranchProbability Probability) const
Second variant of isProfitableToIfCvt.
Definition: TargetInstrInfo.h:834
llvm::TargetInstrInfo::getExtractSubregLikeInputs
virtual bool getExtractSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPairAndIdx &InputReg) const
Target-dependent implementation of getExtractSubregInputs.
Definition: TargetInstrInfo.h:1274
llvm::TargetInstrInfo::RegSubRegPairAndIdx::SubIdx
unsigned SubIdx
Definition: TargetInstrInfo.h:513
llvm::TargetInstrInfo::getInlineAsmLength
virtual unsigned getInlineAsmLength(const char *Str, const MCAsmInfo &MAI, const TargetSubtargetInfo *STI=nullptr) const
Measure the specified inline asm to determine an approximation of its length.
Definition: TargetInstrInfo.cpp:98
llvm::SMSchedule
This class represents the scheduled code.
Definition: MachinePipeliner.h:532
llvm::TargetInstrInfo::isLoadFromStackSlot
virtual unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const
If the specified machine instruction is a direct load from a stack slot, return the virtual or physic...
Definition: TargetInstrInfo.h:265
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24
llvm::TargetInstrInfo::getSerializableTargetIndices
virtual ArrayRef< std::pair< int, const char * > > getSerializableTargetIndices() const
Return an array that contains the ids of the target indices (used for the TargetIndex machine operand...
Definition: TargetInstrInfo.h:1847
llvm::MachineCombinerPattern
MachineCombinerPattern
These are instruction patterns matched by the machine combiner pass.
Definition: MachineCombinerPattern.h:20
MachineOutliner.h