LLVM 19.0.0git
AArch64RegisterInfo.h
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1//==- AArch64RegisterInfo.h - AArch64 Register Information Impl --*- C++ -*-==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the AArch64 implementation of the MRegisterInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_AARCH64_AARCH64REGISTERINFO_H
14#define LLVM_LIB_TARGET_AARCH64_AARCH64REGISTERINFO_H
15
16#define GET_REGINFO_HEADER
17#include "AArch64GenRegisterInfo.inc"
18
19namespace llvm {
20
21class MachineFunction;
22class RegScavenger;
23class TargetRegisterClass;
24class Triple;
25
27 const Triple &TT;
28
29public:
30 AArch64RegisterInfo(const Triple &TT);
31
32 // FIXME: This should be tablegen'd like getDwarfRegNum is
33 int getSEHRegNum(unsigned i) const {
34 return getEncodingValue(i);
35 }
36
37 bool isReservedReg(const MachineFunction &MF, MCRegister Reg) const;
39 bool isAnyArgRegReserved(const MachineFunction &MF) const;
40 void emitReservedArgRegCallError(const MachineFunction &MF) const;
41
44 const uint32_t **Mask) const;
45
46 /// Code Generation virtual methods...
47 const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
49 const MCPhysReg *
52 CallingConv::ID) const override;
54 CallingConv::ID) const;
55
56 unsigned getCSRFirstUseCost() const override {
57 // The cost will be compared against BlockFrequency where entry has the
58 // value of 1 << 14. A value of 5 will choose to spill or split really
59 // cold path instead of using a callee-saved register.
60 return 5;
61 }
62
65 unsigned Idx) const override;
66
67 // Calls involved in thread-local variable lookup save more registers than
68 // normal calls, so they need a different mask to represent this.
69 const uint32_t *getTLSCallPreservedMask() const;
70
73
74 // Funclets on ARM64 Windows don't preserve any registers.
75 const uint32_t *getNoPreservedMask() const override;
76
77 // Unwinders may not preserve all Neon and SVE registers.
78 const uint32_t *
79 getCustomEHPadPreservedMask(const MachineFunction &MF) const override;
80
81 /// getThisReturnPreservedMask - Returns a call preserved mask specific to the
82 /// case that 'returned' is on an i64 first argument if the calling convention
83 /// is one that can (partially) model this attribute with a preserved mask
84 /// (i.e. it is a calling convention that uses the same register for the first
85 /// i64 argument and an i64 return value)
86 ///
87 /// Should return NULL in the case that the calling convention does not have
88 /// this property
90 CallingConv::ID) const;
91
92 /// Stack probing calls preserve different CSRs to the normal CC.
94
96 BitVector getReservedRegs(const MachineFunction &MF) const override;
97 std::optional<std::string>
99 MCRegister PhysReg) const override;
100 bool isAsmClobberable(const MachineFunction &MF,
101 MCRegister PhysReg) const override;
102 const TargetRegisterClass *
104 unsigned Kind = 0) const override;
105 const TargetRegisterClass *
106 getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
107
108 bool requiresRegisterScavenging(const MachineFunction &MF) const override;
109 bool useFPForScavengingIndex(const MachineFunction &MF) const override;
110 bool requiresFrameIndexScavenging(const MachineFunction &MF) const override;
111
112 bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override;
113 bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg,
114 int64_t Offset) const override;
116 int64_t Offset) const override;
118 int64_t Offset) const override;
120 unsigned FIOperandNum,
121 RegScavenger *RS = nullptr) const override;
122 bool cannotEliminateFrame(const MachineFunction &MF) const;
123
124 bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override;
125 bool hasBasePointer(const MachineFunction &MF) const;
126 unsigned getBaseRegister() const;
127
128 bool isArgumentRegister(const MachineFunction &MF,
129 MCRegister Reg) const override;
130
131 // Debug information queries.
132 Register getFrameRegister(const MachineFunction &MF) const override;
133
134 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
135 MachineFunction &MF) const override;
136
137 unsigned getLocalAddressRegister(const MachineFunction &MF) const;
138 bool regNeedsCFI(unsigned Reg, unsigned &RegToUseForCFI) const;
139
140 /// SrcRC and DstRC will be morphed into NewRC if this returns true
142 unsigned SubReg, const TargetRegisterClass *DstRC,
143 unsigned DstSubReg, const TargetRegisterClass *NewRC,
144 LiveIntervals &LIS) const override;
145
147 SmallVectorImpl<uint64_t> &Ops) const override;
148};
149
150} // end namespace llvm
151
152#endif
unsigned SubReg
MachineBasicBlock & MBB
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
IRTranslator LLVM IR MI
unsigned Reg
BitVector getStrictlyReservedRegs(const MachineFunction &MF) const
const TargetRegisterClass * getCrossCopyRegClass(const TargetRegisterClass *RC) const override
const uint32_t * getThisReturnPreservedMask(const MachineFunction &MF, CallingConv::ID) const
getThisReturnPreservedMask - Returns a call preserved mask specific to the case that 'returned' is on...
int getSEHRegNum(unsigned i) const
bool isReservedReg(const MachineFunction &MF, MCRegister Reg) const
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
unsigned getCSRFirstUseCost() const override
const MCPhysReg * getCalleeSavedRegsViaCopy(const MachineFunction *MF) const
BitVector getReservedRegs(const MachineFunction &MF) const override
bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg, const TargetRegisterClass *NewRC, LiveIntervals &LIS) const override
SrcRC and DstRC will be morphed into NewRC if this returns true.
bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override
const TargetRegisterClass * getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const override
unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const override
Register materializeFrameBaseRegister(MachineBasicBlock *MBB, int FrameIdx, int64_t Offset) const override
Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx at the beginning of the basic ...
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override
void UpdateCustomCalleeSavedRegs(MachineFunction &MF) const
bool requiresRegisterScavenging(const MachineFunction &MF) const override
bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg, int64_t Offset) const override
void resolveFrameIndex(MachineInstr &MI, Register BaseReg, int64_t Offset) const override
bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override
needsFrameBaseReg - Returns true if the instruction's frame index reference would be better served by...
const uint32_t * getWindowsStackProbePreservedMask() const
Stack probing calls preserve different CSRs to the normal CC.
bool isAnyArgRegReserved(const MachineFunction &MF) const
void emitReservedArgRegCallError(const MachineFunction &MF) const
bool regNeedsCFI(unsigned Reg, unsigned &RegToUseForCFI) const
Return whether the register needs a CFI entry.
bool isStrictlyReservedReg(const MachineFunction &MF, MCRegister Reg) const
bool eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
const uint32_t * getTLSCallPreservedMask() const
const uint32_t * getNoPreservedMask() const override
Register getFrameRegister(const MachineFunction &MF) const override
void getOffsetOpcodes(const StackOffset &Offset, SmallVectorImpl< uint64_t > &Ops) const override
const MCPhysReg * getDarwinCalleeSavedRegs(const MachineFunction *MF) const
bool isAsmClobberable(const MachineFunction &MF, MCRegister PhysReg) const override
const uint32_t * SMEABISupportRoutinesCallPreservedMaskFromX0() const
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Code Generation virtual methods...
const uint32_t * getCustomEHPadPreservedMask(const MachineFunction &MF) const override
unsigned getLocalAddressRegister(const MachineFunction &MF) const
bool hasBasePointer(const MachineFunction &MF) const
const uint32_t * getDarwinCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const
const uint32_t * getSMStartStopCallPreservedMask() const
bool useFPForScavengingIndex(const MachineFunction &MF) const override
bool cannotEliminateFrame(const MachineFunction &MF) const
bool isArgumentRegister(const MachineFunction &MF, MCRegister Reg) const override
void UpdateCustomCallPreservedMask(MachineFunction &MF, const uint32_t **Mask) const
std::optional< std::string > explainReservedReg(const MachineFunction &MF, MCRegister PhysReg) const override
bool requiresFrameIndexScavenging(const MachineFunction &MF) const override
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:33
Representation of each machine instruction.
Definition: MachineInstr.h:68
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:586
StackOffset holds a fixed and a scalable offset in bytes.
Definition: TypeSize.h:33
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:456