LLVM  16.0.0git
AArch64RegisterInfo.h
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1 //==- AArch64RegisterInfo.h - AArch64 Register Information Impl --*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the AArch64 implementation of the MRegisterInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64REGISTERINFO_H
14 #define LLVM_LIB_TARGET_AARCH64_AARCH64REGISTERINFO_H
15 
16 #define GET_REGINFO_HEADER
17 #include "AArch64GenRegisterInfo.inc"
18 
19 namespace llvm {
20 
21 class MachineFunction;
22 class RegScavenger;
23 class TargetRegisterClass;
24 class Triple;
25 
27  const Triple &TT;
28 
29 public:
30  AArch64RegisterInfo(const Triple &TT);
31 
32  // FIXME: This should be tablegen'd like getDwarfRegNum is
33  int getSEHRegNum(unsigned i) const {
34  return getEncodingValue(i);
35  }
36 
37  bool isReservedReg(const MachineFunction &MF, MCRegister Reg) const;
38  bool isStrictlyReservedReg(const MachineFunction &MF, MCRegister Reg) const;
39  bool isAnyArgRegReserved(const MachineFunction &MF) const;
40  void emitReservedArgRegCallError(const MachineFunction &MF) const;
41 
44  const uint32_t **Mask) const;
45 
46  /// Code Generation virtual methods...
47  const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
48  const MCPhysReg *getDarwinCalleeSavedRegs(const MachineFunction *MF) const;
49  const MCPhysReg *
52  CallingConv::ID) const override;
54  CallingConv::ID) const;
55 
56  unsigned getCSRFirstUseCost() const override {
57  // The cost will be compared against BlockFrequency where entry has the
58  // value of 1 << 14. A value of 5 will choose to spill or split really
59  // cold path instead of using a callee-saved register.
60  return 5;
61  }
62 
63  const TargetRegisterClass *
65  unsigned Idx) const override;
66 
67  // Calls involved in thread-local variable lookup save more registers than
68  // normal calls, so they need a different mask to represent this.
69  const uint32_t *getTLSCallPreservedMask() const;
70 
72 
73  // Funclets on ARM64 Windows don't preserve any registers.
74  const uint32_t *getNoPreservedMask() const override;
75 
76  // Unwinders may not preserve all Neon and SVE registers.
77  const uint32_t *
78  getCustomEHPadPreservedMask(const MachineFunction &MF) const override;
79 
80  /// getThisReturnPreservedMask - Returns a call preserved mask specific to the
81  /// case that 'returned' is on an i64 first argument if the calling convention
82  /// is one that can (partially) model this attribute with a preserved mask
83  /// (i.e. it is a calling convention that uses the same register for the first
84  /// i64 argument and an i64 return value)
85  ///
86  /// Should return NULL in the case that the calling convention does not have
87  /// this property
89  CallingConv::ID) const;
90 
91  /// Stack probing calls preserve different CSRs to the normal CC.
93 
95  BitVector getReservedRegs(const MachineFunction &MF) const override;
98  MCRegister PhysReg) const override;
99  bool isAsmClobberable(const MachineFunction &MF,
100  MCRegister PhysReg) const override;
101  const TargetRegisterClass *
103  unsigned Kind = 0) const override;
104  const TargetRegisterClass *
105  getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
106 
107  bool requiresRegisterScavenging(const MachineFunction &MF) const override;
108  bool useFPForScavengingIndex(const MachineFunction &MF) const override;
109  bool requiresFrameIndexScavenging(const MachineFunction &MF) const override;
110 
111  bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override;
112  bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg,
113  int64_t Offset) const override;
115  int64_t Offset) const override;
116  void resolveFrameIndex(MachineInstr &MI, Register BaseReg,
117  int64_t Offset) const override;
119  unsigned FIOperandNum,
120  RegScavenger *RS = nullptr) const override;
121  bool cannotEliminateFrame(const MachineFunction &MF) const;
122 
123  bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override;
124  bool hasBasePointer(const MachineFunction &MF) const;
125  unsigned getBaseRegister() const;
126 
127  bool isArgumentRegister(const MachineFunction &MF,
128  MCRegister Reg) const override;
129 
130  // Debug information queries.
131  Register getFrameRegister(const MachineFunction &MF) const override;
132 
133  unsigned getRegPressureLimit(const TargetRegisterClass *RC,
134  MachineFunction &MF) const override;
135 
136  unsigned getLocalAddressRegister(const MachineFunction &MF) const;
137  bool regNeedsCFI(unsigned Reg, unsigned &RegToUseForCFI) const;
138 
139  /// SrcRC and DstRC will be morphed into NewRC if this returns true
141  unsigned SubReg, const TargetRegisterClass *DstRC,
142  unsigned DstSubReg, const TargetRegisterClass *NewRC,
143  LiveIntervals &LIS) const override;
144 
145  void getOffsetOpcodes(const StackOffset &Offset,
146  SmallVectorImpl<uint64_t> &Ops) const override;
147 };
148 
149 } // end namespace llvm
150 
151 #endif
llvm::AArch64RegisterInfo::getSMStartStopCallPreservedMask
const uint32_t * getSMStartStopCallPreservedMask() const
Definition: AArch64RegisterInfo.cpp:324
i
i
Definition: README.txt:29
llvm::AArch64RegisterInfo::getCallPreservedMask
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
Definition: AArch64RegisterInfo.cpp:244
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:108
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::AArch64RegisterInfo::eliminateFrameIndex
void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
Definition: AArch64RegisterInfo.cpp:813
llvm::AArch64RegisterInfo::shouldCoalesce
bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg, const TargetRegisterClass *NewRC, LiveIntervals &LIS) const override
SrcRC and DstRC will be morphed into NewRC if this returns true.
Definition: AArch64RegisterInfo.cpp:960
AArch64GenRegisterInfo
llvm::AArch64RegisterInfo::UpdateCustomCallPreservedMask
void UpdateCustomCallPreservedMask(MachineFunction &MF, const uint32_t **Mask) const
Definition: AArch64RegisterInfo.cpp:304
llvm::AArch64RegisterInfo::explainReservedReg
llvm::Optional< std::string > explainReservedReg(const MachineFunction &MF, MCRegister PhysReg) const override
Definition: AArch64RegisterInfo.cpp:353
llvm::AArch64RegisterInfo::getBaseRegister
unsigned getBaseRegister() const
Definition: AArch64RegisterInfo.cpp:487
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::AArch64RegisterInfo::isAnyArgRegReserved
bool isAnyArgRegReserved(const MachineFunction &MF) const
Definition: AArch64RegisterInfo.cpp:449
llvm::AArch64RegisterInfo::getNoPreservedMask
const uint32_t * getNoPreservedMask() const override
Definition: AArch64RegisterInfo.cpp:328
llvm::AArch64RegisterInfo::isArgumentRegister
bool isArgumentRegister(const MachineFunction &MF, MCRegister Reg) const override
Definition: AArch64RegisterInfo.cpp:525
llvm::AArch64RegisterInfo::getCalleeSavedRegsViaCopy
const MCPhysReg * getCalleeSavedRegsViaCopy(const MachineFunction *MF) const
Definition: AArch64RegisterInfo.cpp:168
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
llvm::AArch64RegisterInfo::getFrameRegister
Register getFrameRegister(const MachineFunction &MF) const override
Definition: AArch64RegisterInfo.cpp:589
llvm::Optional< std::string >
llvm::AArch64RegisterInfo::getRegPressureLimit
unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const override
Definition: AArch64RegisterInfo.cpp:905
llvm::AArch64RegisterInfo::cannotEliminateFrame
bool cannotEliminateFrame(const MachineFunction &MF) const
Definition: AArch64RegisterInfo.cpp:628
llvm::AArch64RegisterInfo::getCrossCopyRegClass
const TargetRegisterClass * getCrossCopyRegClass(const TargetRegisterClass *RC) const override
Definition: AArch64RegisterInfo.cpp:481
llvm::BitmaskEnumDetail::Mask
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::AArch64RegisterInfo::getSubClassWithSubReg
const TargetRegisterClass * getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const override
Definition: AArch64RegisterInfo.cpp:195
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::AArch64RegisterInfo::getSEHRegNum
int getSEHRegNum(unsigned i) const
Definition: AArch64RegisterInfo.h:33
llvm::BitVector
Definition: BitVector.h:75
llvm::AArch64RegisterInfo::materializeFrameBaseRegister
Register materializeFrameBaseRegister(MachineBasicBlock *MBB, int FrameIdx, int64_t Offset) const override
Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx at the beginning of the basic ...
Definition: AArch64RegisterInfo.cpp:714
llvm::lltok::Kind
Kind
Definition: LLToken.h:18
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::AArch64RegisterInfo::isFrameOffsetLegal
bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg, int64_t Offset) const override
Definition: AArch64RegisterInfo.cpp:703
llvm::AArch64RegisterInfo::AArch64RegisterInfo
AArch64RegisterInfo(const Triple &TT)
Definition: AArch64RegisterInfo.cpp:42
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::AArch64RegisterInfo::isStrictlyReservedReg
bool isStrictlyReservedReg(const MachineFunction &MF, MCRegister Reg) const
Definition: AArch64RegisterInfo.cpp:444
llvm::AArch64RegisterInfo::needsFrameBaseReg
bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override
needsFrameBaseReg - Returns true if the instruction's frame index reference would be better served by...
Definition: AArch64RegisterInfo.cpp:639
llvm::RegScavenger
Definition: RegisterScavenging.h:34
llvm::AArch64RegisterInfo::getCSRFirstUseCost
unsigned getCSRFirstUseCost() const override
Definition: AArch64RegisterInfo.h:56
llvm::AArch64RegisterInfo::useFPForScavengingIndex
bool useFPForScavengingIndex(const MachineFunction &MF) const override
Definition: AArch64RegisterInfo.cpp:605
llvm::AArch64RegisterInfo::getCalleeSavedRegs
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Code Generation virtual methods...
Definition: AArch64RegisterInfo.cpp:71
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::AArch64RegisterInfo::getReservedRegs
BitVector getReservedRegs(const MachineFunction &MF) const override
Definition: AArch64RegisterInfo.cpp:427
llvm::AArch64RegisterInfo::requiresFrameIndexScavenging
bool requiresFrameIndexScavenging(const MachineFunction &MF) const override
Definition: AArch64RegisterInfo.cpp:622
llvm::AArch64RegisterInfo::isAsmClobberable
bool isAsmClobberable(const MachineFunction &MF, MCRegister PhysReg) const override
Definition: AArch64RegisterInfo.cpp:462
llvm::AArch64RegisterInfo::getLocalAddressRegister
unsigned getLocalAddressRegister(const MachineFunction &MF) const
Definition: AArch64RegisterInfo.cpp:949
uint32_t
llvm::StackOffset
StackOffset is a class to represent an offset with 2 dimensions, named fixed and scalable,...
Definition: TypeSize.h:134
llvm::AArch64RegisterInfo::getCustomEHPadPreservedMask
const uint32_t * getCustomEHPadPreservedMask(const MachineFunction &MF) const override
Definition: AArch64RegisterInfo.cpp:288
llvm::AArch64RegisterInfo
Definition: AArch64RegisterInfo.h:26
llvm::AArch64RegisterInfo::getThisReturnPreservedMask
const uint32_t * getThisReturnPreservedMask(const MachineFunction &MF, CallingConv::ID) const
getThisReturnPreservedMask - Returns a call preserved mask specific to the case that 'returned' is on...
Definition: AArch64RegisterInfo.cpp:333
llvm::AArch64RegisterInfo::getDarwinCallPreservedMask
const uint32_t * getDarwinCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const
Definition: AArch64RegisterInfo.cpp:208
llvm::AArch64RegisterInfo::emitReservedArgRegCallError
void emitReservedArgRegCallError(const MachineFunction &MF) const
Definition: AArch64RegisterInfo.cpp:455
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::AArch64RegisterInfo::getOffsetOpcodes
void getOffsetOpcodes(const StackOffset &Offset, SmallVectorImpl< uint64_t > &Ops) const override
Definition: AArch64RegisterInfo.cpp:786
uint16_t
llvm::LiveIntervals
Definition: LiveIntervals.h:53
llvm::AArch64RegisterInfo::getWindowsStackProbePreservedMask
const uint32_t * getWindowsStackProbePreservedMask() const
Stack probing calls preserve different CSRs to the normal CC.
Definition: AArch64RegisterInfo.cpp:348
llvm::AArch64RegisterInfo::resolveFrameIndex
void resolveFrameIndex(MachineInstr &MI, Register BaseReg, int64_t Offset) const override
Definition: AArch64RegisterInfo.cpp:738
llvm::AArch64RegisterInfo::getPointerRegClass
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override
Definition: AArch64RegisterInfo.cpp:475
llvm::AArch64RegisterInfo::UpdateCustomCalleeSavedRegs
void UpdateCustomCalleeSavedRegs(MachineFunction &MF) const
Definition: AArch64RegisterInfo.cpp:177
llvm::SmallVectorImpl< uint64_t >
llvm::AArch64RegisterInfo::getTLSCallPreservedMask
const uint32_t * getTLSCallPreservedMask() const
Definition: AArch64RegisterInfo.cpp:296
llvm::AArch64RegisterInfo::regNeedsCFI
bool regNeedsCFI(unsigned Reg, unsigned &RegToUseForCFI) const
Return whether the register needs a CFI entry.
Definition: AArch64RegisterInfo.cpp:52
llvm::AArch64RegisterInfo::requiresVirtualBaseRegisters
bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override
Definition: AArch64RegisterInfo.cpp:599
llvm::AArch64RegisterInfo::hasBasePointer
bool hasBasePointer(const MachineFunction &MF) const
Definition: AArch64RegisterInfo.cpp:489
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::AArch64RegisterInfo::requiresRegisterScavenging
bool requiresRegisterScavenging(const MachineFunction &MF) const override
Definition: AArch64RegisterInfo.cpp:594
llvm::AArch64RegisterInfo::getDarwinCalleeSavedRegs
const MCPhysReg * getDarwinCalleeSavedRegs(const MachineFunction *MF) const
Definition: AArch64RegisterInfo.cpp:125
SubReg
unsigned SubReg
Definition: AArch64AdvSIMDScalarPass.cpp:104
llvm::AArch64RegisterInfo::isReservedReg
bool isReservedReg(const MachineFunction &MF, MCRegister Reg) const
Definition: AArch64RegisterInfo.cpp:439
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24
llvm::AArch64RegisterInfo::getStrictlyReservedRegs
BitVector getStrictlyReservedRegs(const MachineFunction &MF) const
Definition: AArch64RegisterInfo.cpp:380