LLVM  14.0.0git
AArch64RegisterInfo.h
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1 //==- AArch64RegisterInfo.h - AArch64 Register Information Impl --*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the AArch64 implementation of the MRegisterInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64REGISTERINFO_H
14 #define LLVM_LIB_TARGET_AARCH64_AARCH64REGISTERINFO_H
15 
16 #define GET_REGINFO_HEADER
17 #include "AArch64GenRegisterInfo.inc"
18 
19 namespace llvm {
20 
21 class MachineFunction;
22 class RegScavenger;
23 class TargetRegisterClass;
24 class Triple;
25 
27  const Triple &TT;
28 
29 public:
30  AArch64RegisterInfo(const Triple &TT);
31 
32  // FIXME: This should be tablegen'd like getDwarfRegNum is
33  int getSEHRegNum(unsigned i) const {
34  return getEncodingValue(i);
35  }
36 
37  bool isReservedReg(const MachineFunction &MF, MCRegister Reg) const;
38  bool isAnyArgRegReserved(const MachineFunction &MF) const;
39  void emitReservedArgRegCallError(const MachineFunction &MF) const;
40 
43  const uint32_t **Mask) const;
44 
45  static bool hasSVEArgsOrReturn(const MachineFunction *MF);
46 
47  /// Code Generation virtual methods...
48  const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
49  const MCPhysReg *getDarwinCalleeSavedRegs(const MachineFunction *MF) const;
50  const MCPhysReg *
53  CallingConv::ID) const override;
55  CallingConv::ID) const;
56 
57  unsigned getCSRFirstUseCost() const override {
58  // The cost will be compared against BlockFrequency where entry has the
59  // value of 1 << 14. A value of 5 will choose to spill or split really
60  // cold path instead of using a callee-saved register.
61  return 5;
62  }
63 
64  const TargetRegisterClass *
66  unsigned Idx) const override;
67 
68  // Calls involved in thread-local variable lookup save more registers than
69  // normal calls, so they need a different mask to represent this.
70  const uint32_t *getTLSCallPreservedMask() const;
71 
72  // Funclets on ARM64 Windows don't preserve any registers.
73  const uint32_t *getNoPreservedMask() const override;
74 
75  // Unwinders may not preserve all Neon and SVE registers.
76  const uint32_t *
77  getCustomEHPadPreservedMask(const MachineFunction &MF) const override;
78 
79  /// getThisReturnPreservedMask - Returns a call preserved mask specific to the
80  /// case that 'returned' is on an i64 first argument if the calling convention
81  /// is one that can (partially) model this attribute with a preserved mask
82  /// (i.e. it is a calling convention that uses the same register for the first
83  /// i64 argument and an i64 return value)
84  ///
85  /// Should return NULL in the case that the calling convention does not have
86  /// this property
88  CallingConv::ID) const;
89 
90  /// Stack probing calls preserve different CSRs to the normal CC.
92 
93  BitVector getReservedRegs(const MachineFunction &MF) const override;
94  bool isAsmClobberable(const MachineFunction &MF,
95  MCRegister PhysReg) const override;
96  bool isConstantPhysReg(MCRegister PhysReg) const override;
97  const TargetRegisterClass *
99  unsigned Kind = 0) const override;
100  const TargetRegisterClass *
101  getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
102 
103  bool requiresRegisterScavenging(const MachineFunction &MF) const override;
104  bool useFPForScavengingIndex(const MachineFunction &MF) const override;
105  bool requiresFrameIndexScavenging(const MachineFunction &MF) const override;
106 
107  bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override;
108  bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg,
109  int64_t Offset) const override;
111  int64_t Offset) const override;
112  void resolveFrameIndex(MachineInstr &MI, Register BaseReg,
113  int64_t Offset) const override;
115  unsigned FIOperandNum,
116  RegScavenger *RS = nullptr) const override;
117  bool cannotEliminateFrame(const MachineFunction &MF) const;
118 
119  bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override;
120  bool hasBasePointer(const MachineFunction &MF) const;
121  unsigned getBaseRegister() const;
122 
123  // Debug information queries.
124  Register getFrameRegister(const MachineFunction &MF) const override;
125 
126  unsigned getRegPressureLimit(const TargetRegisterClass *RC,
127  MachineFunction &MF) const override;
128 
129  unsigned getLocalAddressRegister(const MachineFunction &MF) const;
130  bool regNeedsCFI(unsigned Reg, unsigned &RegToUseForCFI) const;
131 
132  /// SrcRC and DstRC will be morphed into NewRC if this returns true
134  unsigned SubReg, const TargetRegisterClass *DstRC,
135  unsigned DstSubReg, const TargetRegisterClass *NewRC,
136  LiveIntervals &LIS) const override;
137 
138  void getOffsetOpcodes(const StackOffset &Offset,
139  SmallVectorImpl<uint64_t> &Ops) const override;
140 };
141 
142 } // end namespace llvm
143 
144 #endif
i
i
Definition: README.txt:29
llvm::AArch64RegisterInfo::getCallPreservedMask
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
Definition: AArch64RegisterInfo.cpp:214
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:103
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::AArch64RegisterInfo::eliminateFrameIndex
void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
Definition: AArch64RegisterInfo.cpp:637
llvm::AArch64RegisterInfo::shouldCoalesce
bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg, const TargetRegisterClass *NewRC, LiveIntervals &LIS) const override
SrcRC and DstRC will be morphed into NewRC if this returns true.
Definition: AArch64RegisterInfo.cpp:784
AArch64GenRegisterInfo
llvm::AArch64RegisterInfo::UpdateCustomCallPreservedMask
void UpdateCustomCallPreservedMask(MachineFunction &MF, const uint32_t **Mask) const
Definition: AArch64RegisterInfo.cpp:270
llvm::AArch64RegisterInfo::getBaseRegister
unsigned getBaseRegister() const
Definition: AArch64RegisterInfo.cpp:382
llvm::AArch64RegisterInfo::isAnyArgRegReserved
bool isAnyArgRegReserved(const MachineFunction &MF) const
Definition: AArch64RegisterInfo.cpp:347
llvm::AArch64RegisterInfo::getNoPreservedMask
const uint32_t * getNoPreservedMask() const override
Definition: AArch64RegisterInfo.cpp:290
llvm::AArch64RegisterInfo::getCalleeSavedRegsViaCopy
const MCPhysReg * getCalleeSavedRegsViaCopy(const MachineFunction *MF) const
Definition: AArch64RegisterInfo.cpp:146
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:45
llvm::AArch64RegisterInfo::getFrameRegister
Register getFrameRegister(const MachineFunction &MF) const override
Definition: AArch64RegisterInfo.cpp:421
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
llvm::BitmaskEnumDetail::Mask
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::AArch64RegisterInfo::getRegPressureLimit
unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const override
Definition: AArch64RegisterInfo.cpp:729
llvm::AArch64RegisterInfo::cannotEliminateFrame
bool cannotEliminateFrame(const MachineFunction &MF) const
Definition: AArch64RegisterInfo.cpp:460
llvm::AArch64RegisterInfo::getCrossCopyRegClass
const TargetRegisterClass * getCrossCopyRegClass(const TargetRegisterClass *RC) const override
Definition: AArch64RegisterInfo.cpp:376
llvm::AArch64RegisterInfo::getSubClassWithSubReg
const TargetRegisterClass * getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const override
Definition: AArch64RegisterInfo.cpp:173
llvm::AArch64RegisterInfo::hasSVEArgsOrReturn
static bool hasSVEArgsOrReturn(const MachineFunction *MF)
Definition: AArch64RegisterInfo.cpp:66
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::AArch64RegisterInfo::getSEHRegNum
int getSEHRegNum(unsigned i) const
Definition: AArch64RegisterInfo.h:33
llvm::BitVector
Definition: BitVector.h:74
llvm::AArch64RegisterInfo::materializeFrameBaseRegister
Register materializeFrameBaseRegister(MachineBasicBlock *MBB, int FrameIdx, int64_t Offset) const override
Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx at the beginning of the basic ...
Definition: AArch64RegisterInfo.cpp:546
llvm::lltok::Kind
Kind
Definition: LLToken.h:18
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::AArch64RegisterInfo::isFrameOffsetLegal
bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg, int64_t Offset) const override
Definition: AArch64RegisterInfo.cpp:535
llvm::AArch64RegisterInfo::AArch64RegisterInfo
AArch64RegisterInfo(const Triple &TT)
Definition: AArch64RegisterInfo.cpp:38
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::AArch64RegisterInfo::needsFrameBaseReg
bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override
needsFrameBaseReg - Returns true if the instruction's frame index reference would be better served by...
Definition: AArch64RegisterInfo.cpp:471
llvm::RegScavenger
Definition: RegisterScavenging.h:34
llvm::AArch64RegisterInfo::getCSRFirstUseCost
unsigned getCSRFirstUseCost() const override
Definition: AArch64RegisterInfo.h:57
llvm::AArch64RegisterInfo::isConstantPhysReg
bool isConstantPhysReg(MCRegister PhysReg) const override
Definition: AArch64RegisterInfo.cpp:365
llvm::AArch64RegisterInfo::useFPForScavengingIndex
bool useFPForScavengingIndex(const MachineFunction &MF) const override
Definition: AArch64RegisterInfo.cpp:437
llvm::AArch64RegisterInfo::getCalleeSavedRegs
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Code Generation virtual methods...
Definition: AArch64RegisterInfo.cpp:75
llvm::MachineFunction
Definition: MachineFunction.h:230
llvm::AArch64RegisterInfo::getReservedRegs
BitVector getReservedRegs(const MachineFunction &MF) const override
Definition: AArch64RegisterInfo.cpp:315
llvm::AArch64RegisterInfo::requiresFrameIndexScavenging
bool requiresFrameIndexScavenging(const MachineFunction &MF) const override
Definition: AArch64RegisterInfo.cpp:454
llvm::AArch64RegisterInfo::isAsmClobberable
bool isAsmClobberable(const MachineFunction &MF, MCRegister PhysReg) const override
Definition: AArch64RegisterInfo.cpp:360
llvm::AArch64RegisterInfo::getLocalAddressRegister
unsigned getLocalAddressRegister(const MachineFunction &MF) const
Definition: AArch64RegisterInfo.cpp:773
uint32_t
llvm::StackOffset
StackOffset is a class to represent an offset with 2 dimensions, named fixed and scalable,...
Definition: TypeSize.h:134
llvm::AArch64RegisterInfo::getCustomEHPadPreservedMask
const uint32_t * getCustomEHPadPreservedMask(const MachineFunction &MF) const override
Definition: AArch64RegisterInfo.cpp:254
llvm::AArch64RegisterInfo
Definition: AArch64RegisterInfo.h:26
llvm::AArch64RegisterInfo::getThisReturnPreservedMask
const uint32_t * getThisReturnPreservedMask(const MachineFunction &MF, CallingConv::ID) const
getThisReturnPreservedMask - Returns a call preserved mask specific to the case that 'returned' is on...
Definition: AArch64RegisterInfo.cpp:295
llvm::AArch64RegisterInfo::getDarwinCallPreservedMask
const uint32_t * getDarwinCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const
Definition: AArch64RegisterInfo.cpp:186
llvm::AArch64RegisterInfo::emitReservedArgRegCallError
void emitReservedArgRegCallError(const MachineFunction &MF) const
Definition: AArch64RegisterInfo.cpp:353
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::AArch64RegisterInfo::getOffsetOpcodes
void getOffsetOpcodes(const StackOffset &Offset, SmallVectorImpl< uint64_t > &Ops) const override
Definition: AArch64RegisterInfo.cpp:610
uint16_t
llvm::LiveIntervals
Definition: LiveIntervals.h:54
llvm::AArch64RegisterInfo::getWindowsStackProbePreservedMask
const uint32_t * getWindowsStackProbePreservedMask() const
Stack probing calls preserve different CSRs to the normal CC.
Definition: AArch64RegisterInfo.cpp:310
llvm::AArch64RegisterInfo::resolveFrameIndex
void resolveFrameIndex(MachineInstr &MI, Register BaseReg, int64_t Offset) const override
Definition: AArch64RegisterInfo.cpp:570
llvm::AArch64RegisterInfo::getPointerRegClass
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override
Definition: AArch64RegisterInfo.cpp:370
llvm::AArch64RegisterInfo::UpdateCustomCalleeSavedRegs
void UpdateCustomCalleeSavedRegs(MachineFunction &MF) const
Definition: AArch64RegisterInfo.cpp:155
llvm::SmallVectorImpl< uint64_t >
llvm::AArch64RegisterInfo::getTLSCallPreservedMask
const uint32_t * getTLSCallPreservedMask() const
Definition: AArch64RegisterInfo.cpp:262
llvm::AArch64RegisterInfo::regNeedsCFI
bool regNeedsCFI(unsigned Reg, unsigned &RegToUseForCFI) const
Return whether the register needs a CFI entry.
Definition: AArch64RegisterInfo.cpp:48
llvm::AArch64RegisterInfo::requiresVirtualBaseRegisters
bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override
Definition: AArch64RegisterInfo.cpp:431
llvm::AArch64RegisterInfo::hasBasePointer
bool hasBasePointer(const MachineFunction &MF) const
Definition: AArch64RegisterInfo.cpp:384
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::AArch64RegisterInfo::requiresRegisterScavenging
bool requiresRegisterScavenging(const MachineFunction &MF) const override
Definition: AArch64RegisterInfo.cpp:426
llvm::AArch64RegisterInfo::getDarwinCalleeSavedRegs
const MCPhysReg * getDarwinCalleeSavedRegs(const MachineFunction *MF) const
Definition: AArch64RegisterInfo.cpp:117
SubReg
unsigned SubReg
Definition: AArch64AdvSIMDScalarPass.cpp:104
llvm::AArch64RegisterInfo::isReservedReg
bool isReservedReg(const MachineFunction &MF, MCRegister Reg) const
Definition: AArch64RegisterInfo.cpp:342
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:23