LLVM 20.0.0git
Public Member Functions | Static Public Member Functions | Protected Member Functions | List of all members
llvm::AArch64InstrInfo Class Referencefinal

#include "Target/AArch64/AArch64InstrInfo.h"

Inheritance diagram for llvm::AArch64InstrInfo:
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Public Member Functions

 AArch64InstrInfo (const AArch64Subtarget &STI)
 
const AArch64RegisterInfo & getRegisterInfo () const
 getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
 
unsigned getInstSizeInBytes (const MachineInstr &MI) const override
 GetInstSize - Return the number of bytes of code the specified instruction may be.
 
bool isAsCheapAsAMove (const MachineInstr &MI) const override
 
bool isCoalescableExtInstr (const MachineInstr &MI, Register &SrcReg, Register &DstReg, unsigned &SubIdx) const override
 
bool areMemAccessesTriviallyDisjoint (const MachineInstr &MIa, const MachineInstr &MIb) const override
 
Register isLoadFromStackSlot (const MachineInstr &MI, int &FrameIndex) const override
 
Register isStoreToStackSlot (const MachineInstr &MI, int &FrameIndex) const override
 
bool isCandidateToMergeOrPair (const MachineInstr &MI) const
 Return true if this is a load/store that can be potentially paired/merged.
 
std::optional< ExtAddrMode > getAddrModeFromMemoryOp (const MachineInstr &MemI, const TargetRegisterInfo *TRI) const override
 
bool canFoldIntoAddrMode (const MachineInstr &MemI, Register Reg, const MachineInstr &AddrI, ExtAddrMode &AM) const override
 
MachineInstr * emitLdStWithAddr (MachineInstr &MemI, const ExtAddrMode &AM) const override
 
bool getMemOperandsWithOffsetWidth (const MachineInstr &MI, SmallVectorImpl< const MachineOperand * > &BaseOps, int64_t &Offset, bool &OffsetIsScalable, LocationSize &Width, const TargetRegisterInfo *TRI) const override
 
bool getMemOperandWithOffsetWidth (const MachineInstr &MI, const MachineOperand *&BaseOp, int64_t &Offset, bool &OffsetIsScalable, TypeSize &Width, const TargetRegisterInfo *TRI) const
 If OffsetIsScalable is set to 'true', the offset is scaled by vscale.
 
MachineOperand & getMemOpBaseRegImmOfsOffsetOperand (MachineInstr &LdSt) const
 Return the immediate offset of the base register in a load/store LdSt.
 
bool shouldClusterMemOps (ArrayRef< const MachineOperand * > BaseOps1, int64_t Offset1, bool OffsetIsScalable1, ArrayRef< const MachineOperand * > BaseOps2, int64_t Offset2, bool OffsetIsScalable2, unsigned ClusterSize, unsigned NumBytes) const override
 Detect opportunities for ldp/stp formation.
 
void copyPhysRegTuple (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc, unsigned Opcode, llvm::ArrayRef< unsigned > Indices) const
 
void copyGPRRegTuple (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc, unsigned Opcode, unsigned ZeroReg, llvm::ArrayRef< unsigned > Indices) const
 
void copyPhysReg (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc, bool RenamableDest=false, bool RenamableSrc=false) const override
 
void storeRegToStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override
 
void loadRegFromStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override
 
bool isSubregFoldable () const override
 
MachineInstr * foldMemoryOperandImpl (MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const override
 
bool isBranchOffsetInRange (unsigned BranchOpc, int64_t BrOffset) const override
 
MachineBasicBlock * getBranchDestBlock (const MachineInstr &MI) const override
 
void insertIndirectBranch (MachineBasicBlock &MBB, MachineBasicBlock &NewDestBB, MachineBasicBlock &RestoreBB, const DebugLoc &DL, int64_t BrOffset, RegScavenger *RS) const override
 
bool analyzeBranch (MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override
 
bool analyzeBranchPredicate (MachineBasicBlock &MBB, MachineBranchPredicate &MBP, bool AllowModify) const override
 
unsigned removeBranch (MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
 
unsigned insertBranch (MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
 
std::unique_ptr< TargetInstrInfo::PipelinerLoopInfo > analyzeLoopForPipelining (MachineBasicBlock *LoopBB) const override
 
bool reverseBranchCondition (SmallVectorImpl< MachineOperand > &Cond) const override
 
bool canInsertSelect (const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, Register, Register, Register, int &, int &, int &) const override
 
void insertSelect (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, Register DstReg, ArrayRef< MachineOperand > Cond, Register TrueReg, Register FalseReg) const override
 
void insertNoop (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
 
MCInst getNop () const override
 
bool isSchedulingBoundary (const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override
 
bool analyzeCompare (const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int64_t &CmpMask, int64_t &CmpValue) const override
 analyzeCompare - For a comparison instruction, return the source registers in SrcReg and SrcReg2, and the value it compares against in CmpValue.
 
bool optimizeCompareInstr (MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int64_t CmpMask, int64_t CmpValue, const MachineRegisterInfo *MRI) const override
 optimizeCompareInstr - Convert the instruction supplying the argument to the comparison into one that sets the zero bit in the flags register.
 
bool optimizeCondBranch (MachineInstr &MI) const override
 Replace csincr-branch sequence by simple conditional branch.
 
CombinerObjective getCombinerObjective (unsigned Pattern) const override
 
bool isThroughputPattern (unsigned Pattern) const override
 Return true when a code sequence can improve throughput.
 
bool getMachineCombinerPatterns (MachineInstr &Root, SmallVectorImpl< unsigned > &Patterns, bool DoRegPressureReduce) const override
 Return true when there is potentially a faster code sequence for an instruction chain ending in Root.
 
bool isAssociativeAndCommutative (const MachineInstr &Inst, bool Invert) const override
 Return true when Inst is associative and commutative so that it can be reassociated.
 
void genAlternativeCodeSequence (MachineInstr &Root, unsigned Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, DenseMap< unsigned, unsigned > &InstrIdxForVirtReg) const override
 When getMachineCombinerPatterns() finds patterns, this function generates the instructions that could replace the original code sequence.
 
bool useMachineCombiner () const override
 AArch64 supports MachineCombiner.
 
bool expandPostRAPseudo (MachineInstr &MI) const override
 
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags (unsigned TF) const override
 
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags () const override
 
ArrayRef< std::pair< unsigned, const char * > > getSerializableBitmaskMachineOperandTargetFlags () const override
 
ArrayRef< std::pair< MachineMemOperand::Flags, const char * > > getSerializableMachineMemOperandTargetFlags () const override
 
bool isFunctionSafeToOutlineFrom (MachineFunction &MF, bool OutlineFromLinkOnceODRs) const override
 
std::optional< std::unique_ptr< outliner::OutlinedFunction > > getOutliningCandidateInfo (const MachineModuleInfo &MMI, std::vector< outliner::Candidate > &RepeatedSequenceLocs, unsigned MinRepeats) const override
 
void mergeOutliningCandidateAttributes (Function &F, std::vector< outliner::Candidate > &Candidates) const override
 
outliner::InstrType getOutliningTypeImpl (const MachineModuleInfo &MMI, MachineBasicBlock::iterator &MIT, unsigned Flags) const override
 
SmallVector< std::pair< MachineBasicBlock::iterator, MachineBasicBlock::iterator > > getOutlinableRanges (MachineBasicBlock &MBB, unsigned &Flags) const override
 
void buildOutlinedFrame (MachineBasicBlock &MBB, MachineFunction &MF, const outliner::OutlinedFunction &OF) const override
 
MachineBasicBlock::iterator insertOutlinedCall (Module &M, MachineBasicBlock &MBB, MachineBasicBlock::iterator &It, MachineFunction &MF, outliner::Candidate &C) const override
 
bool shouldOutlineFromFunctionByDefault (MachineFunction &MF) const override
 
void buildClearRegister (Register Reg, MachineBasicBlock &MBB, MachineBasicBlock::iterator Iter, DebugLoc &DL, bool AllowSideEffects=true) const override
 
uint64_t getElementSizeForOpcode (unsigned Opc) const
 Returns the vector element size (B, H, S or D) of an SVE opcode.
 
bool isPTestLikeOpcode (unsigned Opc) const
 Returns true if the opcode is for an SVE instruction that sets the condition codes as if it's results had been fed to a PTEST instruction along with the same general predicate.
 
bool isWhileOpcode (unsigned Opc) const
 Returns true if the opcode is for an SVE WHILE## instruction.
 
std::optional< RegImmPair > isAddImmediate (const MachineInstr &MI, Register Reg) const override
 
bool isFunctionSafeToSplit (const MachineFunction &MF) const override
 
bool isMBBSafeToSplitToCold (const MachineBasicBlock &MBB) const override
 
std::optional< ParamLoadedValue > describeLoadedValue (const MachineInstr &MI, Register Reg) const override
 
unsigned int getTailDuplicateSize (CodeGenOptLevel OptLevel) const override
 
bool isExtendLikelyToBeFolded (MachineInstr &ExtMI, MachineRegisterInfo &MRI) const override
 
bool isLegalAddressingMode (unsigned NumBytes, int64_t Offset, unsigned Scale) const
 
MachineBasicBlock::iterator probedStackAlloc (MachineBasicBlock::iterator MBBI, Register TargetReg, bool FrameSetup) const
 
virtual MachineInstr * foldMemoryOperandImpl (MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const
 Target-dependent implementation for foldMemoryOperand.
 
virtual MachineInstr * foldMemoryOperandImpl (MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI, LiveIntervals *LIS=nullptr) const
 Target-dependent implementation for foldMemoryOperand.
 

Static Public Member Functions

static bool isGPRZero (const MachineInstr &MI)
 Does this instruction set its full destination register to zero?
 
static bool isGPRCopy (const MachineInstr &MI)
 Does this instruction rename a GPR without modifying bits?
 
static bool isFPRCopy (const MachineInstr &MI)
 Does this instruction rename an FPR without modifying bits?
 
static bool isLdStPairSuppressed (const MachineInstr &MI)
 Return true if pairing the given load or store is hinted to be unprofitable.
 
static bool isStridedAccess (const MachineInstr &MI)
 Return true if the given load or store is a strided memory access.
 
static bool hasUnscaledLdStOffset (unsigned Opc)
 Return true if it has an unscaled load/store offset.
 
static bool hasUnscaledLdStOffset (MachineInstr &MI)
 
static std::optional< unsigned > getUnscaledLdSt (unsigned Opc)
 Returns the unscaled load/store for the scaled load/store opcode, if there is a corresponding unscaled variant available.
 
static int getMemScale (unsigned Opc)
 Scaling factor for (scaled or unscaled) load or store.
 
static int getMemScale (const MachineInstr &MI)
 
static bool isPreLd (const MachineInstr &MI)
 Returns whether the instruction is a pre-indexed load.
 
static bool isPreSt (const MachineInstr &MI)
 Returns whether the instruction is a pre-indexed store.
 
static bool isPreLdSt (const MachineInstr &MI)
 Returns whether the instruction is a pre-indexed load/store.
 
static bool isPairedLdSt (const MachineInstr &MI)
 Returns whether the instruction is a paired load/store.
 
static const MachineOperand & getLdStBaseOp (const MachineInstr &MI)
 Returns the base register operator of a load/store.
 
static const MachineOperand & getLdStOffsetOp (const MachineInstr &MI)
 Returns the immediate offset operator of a load/store.
 
static bool isFpOrNEON (Register Reg)
 Returns whether the physical register is FP or NEON.
 
static const MachineOperand & getLdStAmountOp (const MachineInstr &MI)
 Returns the shift amount operator of a load/store.
 
static bool isFpOrNEON (const MachineInstr &MI)
 Returns whether the instruction is FP or NEON.
 
static bool isHForm (const MachineInstr &MI)
 Returns whether the instruction is in H form (16 bit operands)
 
static bool isQForm (const MachineInstr &MI)
 Returns whether the instruction is in Q form (128 bit operands)
 
static bool hasBTISemantics (const MachineInstr &MI)
 Returns whether the instruction can be compatible with non-zero BTYPE.
 
static unsigned getLoadStoreImmIdx (unsigned Opc)
 Returns the index for the immediate for a given instruction.
 
static bool isPairableLdStInst (const MachineInstr &MI)
 Return true if pairing the given load or store may be paired with another.
 
static bool isTailCallReturnInst (const MachineInstr &MI)
 Returns true if MI is one of the TCRETURN* instructions.
 
static unsigned convertToFlagSettingOpc (unsigned Opc)
 Return the opcode that set flags when possible.
 
static void suppressLdStPair (MachineInstr &MI)
 Hint that pairing the given load or store is unprofitable.
 
static bool getMemOpInfo (unsigned Opcode, TypeSize &Scale, TypeSize &Width, int64_t &MinOffset, int64_t &MaxOffset)
 Returns true if opcode Opc is a memory operation.
 
static bool isFalkorShiftExtFast (const MachineInstr &MI)
 Returns true if the instruction has a shift by immediate that can be executed in one cycle less.
 
static bool isSEHInstruction (const MachineInstr &MI)
 Return true if the instructions is a SEH instruciton used for unwinding on Windows.
 
static void decomposeStackOffsetForFrameOffsets (const StackOffset &Offset, int64_t &NumBytes, int64_t &NumPredicateVectors, int64_t &NumDataVectors)
 Returns the offset in parts to which this frame offset can be decomposed for the purpose of describing a frame offset.
 
static void decomposeStackOffsetForDwarfOffsets (const StackOffset &Offset, int64_t &ByteSized, int64_t &VGSized)
 

Protected Member Functions

std::optional< DestSourcePair > isCopyInstrImpl (const MachineInstr &MI) const override
 If the specific machine instruction is an instruction that moves/copies value from one register to another register return destination and source registers as machine operands.
 
std::optional< DestSourcePair > isCopyLikeInstrImpl (const MachineInstr &MI) const override
 

Detailed Description

Definition at line 176 of file AArch64InstrInfo.h.

Constructor & Destructor Documentation

◆ AArch64InstrInfo()

AArch64InstrInfo::AArch64InstrInfo ( const AArch64Subtarget &  STI)
explicit

Definition at line 81 of file AArch64InstrInfo.cpp.

Member Function Documentation

◆ analyzeBranch()

bool AArch64InstrInfo::analyzeBranch ( MachineBasicBlock &  MBB,
MachineBasicBlock *&  TBB,
MachineBasicBlock *&  FBB,
SmallVectorImpl< MachineOperand > &  Cond,
bool  AllowModify = false 
) const
override

Definition at line 345 of file AArch64InstrInfo.cpp.

References assert(), llvm::MachineBasicBlock::begin(), Cond, llvm::MachineBasicBlock::end(), llvm::MachineInstr::eraseFromParent(), getBranchDestBlock(), llvm::MachineBasicBlock::getLastNonDebugInstr(), llvm::MachineOperand::getMBB(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), I, llvm::isCondBranchOpcode(), llvm::isIndirectBranchOpcode(), llvm::MachineBasicBlock::isLayoutSuccessor(), llvm::isUncondBranchOpcode(), MBB, parseCondBranch(), and TBB.

Referenced by analyzeLoopForPipelining().

◆ analyzeBranchPredicate()

bool AArch64InstrInfo::analyzeBranchPredicate ( MachineBasicBlock &  MBB,
MachineBranchPredicate &  MBP,
bool  AllowModify 
) const
override

Definition at line 461 of file AArch64InstrInfo.cpp.

References assert(), llvm::MachineOperand::CreateImm(), llvm::MachineBasicBlock::end(), llvm::MachineBasicBlock::getLastNonDebugInstr(), llvm::MachineOperand::getMBB(), llvm::ilist_node_with_parent< NodeTy, ParentTy, Options >::getNextNode(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), I, llvm::isCondBranchOpcode(), and MBB.

◆ analyzeCompare()

bool AArch64InstrInfo::analyzeCompare ( const MachineInstr &  MI,
Register &  SrcReg,
Register &  SrcReg2,
int64_t &  CmpMask,
int64_t &  CmpValue 
) const
override

analyzeCompare - For a comparison instruction, return the source registers in SrcReg and SrcReg2, and the value it compares against in CmpValue.

Return true if the comparison instruction can be analyzed.

Definition at line 1186 of file AArch64InstrInfo.cpp.

References assert(), llvm::AArch64_AM::decodeLogicalImmediate(), and MI.

◆ analyzeLoopForPipelining()

std::unique_ptr< TargetInstrInfo::PipelinerLoopInfo > AArch64InstrInfo::analyzeLoopForPipelining ( MachineBasicBlock *  LoopBB) const
override

Definition at line 10393 of file AArch64InstrInfo.cpp.

References analyzeBranch(), assert(), Cond, llvm::MachineBasicBlock::getFirstTerminator(), getIndVarInfo(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), getRegisterInfo(), isDefinedOutside(), isWhileOpcode(), MI, llvm::reverse(), reverseBranchCondition(), TBB, and TRI.

◆ areMemAccessesTriviallyDisjoint()

bool AArch64InstrInfo::areMemAccessesTriviallyDisjoint ( const MachineInstr &  MIa,
const MachineInstr &  MIb 
) const
override

Definition at line 1113 of file AArch64InstrInfo.cpp.

References assert(), llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getKnownMinValue(), getMemOperandWithOffsetWidth(), getRegisterInfo(), llvm::MachineInstr::hasOrderedMemoryRef(), llvm::MachineInstr::hasUnmodeledSideEffects(), llvm::MachineOperand::isIdenticalTo(), llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::isScalable(), llvm::MachineInstr::mayLoadOrStore(), and TRI.

◆ buildClearRegister()

void AArch64InstrInfo::buildClearRegister ( Register  Reg,
MachineBasicBlock &  MBB,
MachineBasicBlock::iterator  Iter,
DebugLoc &  DL,
bool  AllowSideEffects = true 
) const
override

Definition at line 9712 of file AArch64InstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), assert(), llvm::BuildMI(), DL, llvm::get(), llvm::MachineBasicBlock::getParent(), llvm::AArch64Subtarget::getRegisterInfo(), llvm::MachineFunction::getSubtarget(), llvm::AArch64Subtarget::isNeonAvailable(), llvm::AArch64Subtarget::isSVEorStreamingSVEAvailable(), MBB, and TRI.

◆ buildOutlinedFrame()

void AArch64InstrInfo::buildOutlinedFrame ( MachineBasicBlock &  MBB,
MachineFunction &  MF,
const outliner::OutlinedFunction &  OF 
) const
override

Definition at line 9502 of file AArch64InstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addCFIIndex(), llvm::MachineFunction::addFrameInst(), llvm::MachineInstrBuilder::addImm(), llvm::MachineBasicBlock::addLiveIn(), llvm::MachineInstrBuilder::addReg(), llvm::any_of(), assert(), llvm::MachineBasicBlock::begin(), llvm::BuildMI(), llvm::MCCFIInstruction::cfiDefCfaOffset(), llvm::MCCFIInstruction::createOffset(), llvm::RegState::Define, llvm::MachineBasicBlock::end(), llvm::outliner::OutlinedFunction::FrameConstructionID, llvm::MachineInstr::FrameSetup, llvm::get(), llvm::MachineFunction::getInfo(), llvm::TargetSubtargetInfo::getRegisterInfo(), llvm::MachineFunction::getSubtarget(), llvm::MachineBasicBlock::insert(), llvm::MachineBasicBlock::instr_end(), llvm::MachineBasicBlock::instrs(), llvm::MachineBasicBlock::isLiveIn(), MachineOutlinerDefault, MachineOutlinerTailCall, MachineOutlinerThunk, MBB, MI, MRI, llvm::AArch64FunctionInfo::needsDwarfUnwindInfo(), llvm::MachineInstrBuilder::setMIFlags(), llvm::AArch64FunctionInfo::setOutliningStyle(), llvm::AArch64FunctionInfo::shouldSignReturnAddress(), and signOutlinedFunction().

◆ canFoldIntoAddrMode()

bool AArch64InstrInfo::canFoldIntoAddrMode ( const MachineInstr &  MemI,
Register  Reg,
const MachineInstr &  AddrI,
ExtAddrMode &  AM 
) const
override

Definition at line 2886 of file AArch64InstrInfo.cpp.

References llvm::ExtAddrMode::BaseReg, llvm::ExtAddrMode::Basic, DefMI, llvm::ExtAddrMode::Displacement, llvm::ExtAddrMode::Form, llvm::AArch64_AM::getArithExtendType(), llvm::AArch64_AM::getArithShiftValue(), llvm::MachineFunction::getFunction(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getMF(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineInstrBuilder::getReg(), llvm::MachineFunction::getRegInfo(), llvm::AArch64_AM::getShiftType(), llvm::AArch64_AM::getShiftValue(), llvm::Function::hasOptSize(), isLegalAddressingMode(), llvm::MachineOperand::isReg(), llvm::Register::isVirtual(), llvm::AArch64_AM::LSL, MRI, llvm::ExtAddrMode::Scale, llvm::ExtAddrMode::ScaledReg, llvm::ExtAddrMode::SExtScaledReg, llvm::AArch64_AM::SXTW, llvm::AArch64_AM::UXTW, and llvm::ExtAddrMode::ZExtScaledReg.

◆ canInsertSelect()

bool AArch64InstrInfo::canInsertSelect ( const MachineBasicBlock &  MBB,
ArrayRef< MachineOperand >  Cond,
Register  DstReg,
Register  TrueReg,
Register  FalseReg,
int &  CondCycles,
int &  TrueCycles,
int &  FalseCycles 
) const
override

Definition at line 714 of file AArch64InstrInfo.cpp.

References canFoldIntoCSel(), Cond, llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), MBB, and MRI.

◆ convertToFlagSettingOpc()

unsigned AArch64InstrInfo::convertToFlagSettingOpc ( unsigned  Opc)
static

Return the opcode that set flags when possible.

The caller is responsible for ensuring the opc has a flag setting equivalent.

Definition at line 2686 of file AArch64InstrInfo.cpp.

References llvm_unreachable.

◆ copyGPRRegTuple()

void AArch64InstrInfo::copyGPRRegTuple ( MachineBasicBlock &  MBB,
MachineBasicBlock::iterator  I,
const DebugLoc &  DL,
MCRegister  DestReg,
MCRegister  SrcReg,
bool  KillSrc,
unsigned  Opcode,
unsigned  ZeroReg,
llvm::ArrayRef< unsigned >  Indices 
) const

Definition at line 4872 of file AArch64InstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), AddSubReg(), assert(), llvm::BuildMI(), llvm::RegState::Define, DL, llvm::get(), llvm::getKillRegState(), getRegisterInfo(), I, MBB, llvm::ArrayRef< T >::size(), SubReg, and TRI.

Referenced by copyPhysReg().

◆ copyPhysReg()

void AArch64InstrInfo::copyPhysReg ( MachineBasicBlock &  MBB,
MachineBasicBlock::iterator  I,
const DebugLoc &  DL,
MCRegister  DestReg,
MCRegister  SrcReg,
bool  KillSrc,
bool  RenamableDest = false,
bool  RenamableSrc = false 
) const
override

Definition at line 4897 of file AArch64InstrInfo.cpp.

References llvm::MachineInstrBuilder::addDef(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), contains(), copyGPRRegTuple(), copyPhysRegTuple(), llvm::RegState::Define, DL, llvm::errs(), llvm::get(), llvm::getKillRegState(), getRegisterInfo(), llvm::AArch64_AM::getShifterImm(), I, llvm::RegState::Implicit, llvm::AArch64Subtarget::isNeonAvailable(), llvm::AArch64Subtarget::isSVEorStreamingSVEAvailable(), llvm_unreachable, llvm::AArch64_AM::LSL, MBB, TRI, and llvm::RegState::Undef.

◆ copyPhysRegTuple()

void AArch64InstrInfo::copyPhysRegTuple ( MachineBasicBlock &  MBB,
MachineBasicBlock::iterator  I,
const DebugLoc &  DL,
MCRegister  DestReg,
MCRegister  SrcReg,
bool  KillSrc,
unsigned  Opcode,
llvm::ArrayRef< unsigned >  Indices 
) const

Definition at line 4845 of file AArch64InstrInfo.cpp.

References AddSubReg(), assert(), llvm::BuildMI(), llvm::RegState::Define, DL, End, forwardCopyWillClobberTuple(), llvm::get(), llvm::getKillRegState(), getRegisterInfo(), I, MBB, llvm::ArrayRef< T >::size(), SubReg, and TRI.

Referenced by copyPhysReg().

◆ decomposeMachineOperandsTargetFlags()

std::pair< unsigned, unsigned > AArch64InstrInfo::decomposeMachineOperandsTargetFlags ( unsigned  TF) const
override

Definition at line 8546 of file AArch64InstrInfo.cpp.

References llvm::AArch64II::MO_FRAGMENT.

◆ decomposeStackOffsetForDwarfOffsets()

void AArch64InstrInfo::decomposeStackOffsetForDwarfOffsets ( const StackOffset &  Offset,
int64_t &  ByteSized,
int64_t &  VGSized 
)
static

Definition at line 5607 of file AArch64InstrInfo.cpp.

References assert(), and llvm::Offset.

Referenced by llvm::createCFAOffset(), and createDefCFAExpression().

◆ decomposeStackOffsetForFrameOffsets()

void AArch64InstrInfo::decomposeStackOffsetForFrameOffsets ( const StackOffset &  Offset,
int64_t &  NumBytes,
int64_t &  NumPredicateVectors,
int64_t &  NumDataVectors 
)
static

Returns the offset in parts to which this frame offset can be decomposed for the purpose of describing a frame offset.

For non-scalable offsets this is simply its byte size.

Definition at line 5626 of file AArch64InstrInfo.cpp.

References assert(), and llvm::Offset.

Referenced by llvm::emitFrameOffset().

◆ describeLoadedValue()

std::optional< ParamLoadedValue > AArch64InstrInfo::describeLoadedValue ( const MachineInstr &  MI,
Register  Reg 
) const
override

Definition at line 9901 of file AArch64InstrInfo.cpp.

References llvm::MachineOperand::CreateImm(), llvm::TargetInstrInfo::describeLoadedValue(), describeORRLoadedValue(), llvm::TargetSubtargetInfo::getRegisterInfo(), llvm::MachineFunction::getSubtarget(), MI, and TRI.

◆ emitLdStWithAddr()

MachineInstr * AArch64InstrInfo::emitLdStWithAddr ( MachineInstr &  MemI,
const ExtAddrMode &  AM 
) const
override

Definition at line 3562 of file AArch64InstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), B, llvm::ExtAddrMode::BaseReg, llvm::ExtAddrMode::Basic, llvm::BuildMI(), llvm::RegState::Define, llvm::ExtAddrMode::Displacement, DL, llvm::ExtAddrMode::Form, llvm::get(), llvm::MachineInstr::getDebugLoc(), llvm::MachineInstr::getFlags(), llvm::MachineInstr::getMF(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::TargetRegisterClass::hasSuperClassEq(), llvm_unreachable, llvm::MachineInstr::mayLoad(), MBB, llvm::MachineInstr::memoperands(), MRI, offsetExtendOpcode(), regOffsetOpcode(), llvm::ExtAddrMode::Scale, scaledOffsetOpcode(), llvm::ExtAddrMode::ScaledReg, llvm::MachineInstrBuilder::setMemRefs(), llvm::MachineInstrBuilder::setMIFlags(), llvm::ExtAddrMode::SExtScaledReg, unscaledOffsetOpcode(), and llvm::ExtAddrMode::ZExtScaledReg.

◆ expandPostRAPseudo()

bool AArch64InstrInfo::expandPostRAPseudo ( MachineInstr &  MI) const
override

Definition at line 1979 of file AArch64InstrInfo.cpp.

References llvm::MachineInstrBuilder::addDef(), llvm::MachineInstrBuilder::addGlobalAddress(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstrBuilder::addReg(), llvm::MachineInstrBuilder::addUse(), assert(), llvm::MachineBasicBlock::begin(), llvm::BuildMI(), llvm::AArch64Subtarget::ClassifyGlobalReference(), llvm::RegState::Dead, llvm::RegState::Define, DL, llvm::AArch64SysReg::SysReg::Encoding, llvm::MachineBasicBlock::erase(), llvm::MachineInstr::FrameDestroy, llvm::get(), llvm::MachineFunction::getFunction(), llvm::TargetSubtargetInfo::getInstrInfo(), llvm::GlobalValue::getParent(), llvm::MachineBasicBlock::getParent(), llvm::AArch64Subtarget::getRegisterInfo(), llvm::MachineFunction::getSubtarget(), llvm::MachineFunction::getTarget(), llvm::RegState::Implicit, llvm::AArch64Subtarget::isTargetILP32(), llvm::RegState::Kill, llvm::CodeModel::Large, MBB, MBBI, MI, llvm::AArch64II::MO_G0, llvm::AArch64II::MO_G1, llvm::AArch64II::MO_G2, llvm::AArch64II::MO_G3, llvm::AArch64II::MO_GOT, llvm::AArch64II::MO_NC, llvm::AArch64II::MO_PAGE, llvm::AArch64II::MO_PAGEOFF, llvm::Offset, llvm::RegState::Renamable, llvm::report_fatal_error(), llvm::MachineBasicBlock::setMachineBlockAddressTaken(), TII, llvm::CodeModel::Tiny, and TRI.

◆ foldMemoryOperandImpl() [1/3]

virtual MachineInstr * llvm::TargetInstrInfo::foldMemoryOperandImpl ( MachineFunction &  MF,
MachineInstr &  MI,
ArrayRef< unsigned >  Ops,
MachineBasicBlock::iterator  InsertPt,
int  FrameIndex,
LiveIntervals *  LIS = nullptr,
VirtRegMap *  VRM = nullptr 
) const
inline

Target-dependent implementation for foldMemoryOperand.

Target-independent code in foldMemoryOperand will take care of adding a MachineMemOperand to the newly created instruction. The instruction and any auxiliary instructions necessary will be inserted at InsertPt.

Definition at line 1368 of file TargetInstrInfo.h.

◆ foldMemoryOperandImpl() [2/3]

MachineInstr * AArch64InstrInfo::foldMemoryOperandImpl ( MachineFunction &  MF,
MachineInstr &  MI,
ArrayRef< unsigned >  Ops,
MachineBasicBlock::iterator  InsertPt,
int  FrameIndex,
LiveIntervals *  LIS = nullptr,
VirtRegMap *  VRM = nullptr 
) const
override

Definition at line 5954 of file AArch64InstrInfo.cpp.

References assert(), llvm::MachineRegisterInfo::constrainRegClass(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), getRegClass(), llvm::MachineFunction::getRegInfo(), llvm::TargetSubtargetInfo::getRegisterInfo(), llvm::MachineOperand::getSubReg(), llvm::MachineFunction::getSubtarget(), llvm::MachineOperand::isKill(), llvm::MachineOperand::isUndef(), llvm::Register::isVirtual(), llvm::Register::isVirtualRegister(), loadRegFromStackSlot(), MBB, MI, MRI, llvm::MachineOperand::setIsUndef(), llvm::MachineOperand::setSubReg(), llvm::ArrayRef< T >::size(), storeRegToStackSlot(), and TRI.

◆ foldMemoryOperandImpl() [3/3]

virtual MachineInstr * llvm::TargetInstrInfo::foldMemoryOperandImpl ( MachineFunction &  MF,
MachineInstr &  MI,
ArrayRef< unsigned >  Ops,
MachineBasicBlock::iterator  InsertPt,
MachineInstr &  LoadMI,
LiveIntervals *  LIS = nullptr 
) const
inline

Target-dependent implementation for foldMemoryOperand.

Target-independent code in foldMemoryOperand will take care of adding a MachineMemOperand to the newly created instruction. The instruction and any auxiliary instructions necessary will be inserted at InsertPt.

Definition at line 1381 of file TargetInstrInfo.h.

◆ genAlternativeCodeSequence()

void AArch64InstrInfo::genAlternativeCodeSequence ( MachineInstr &  Root,
unsigned  Pattern,
SmallVectorImpl< MachineInstr * > &  InsInstrs,
SmallVectorImpl< MachineInstr * > &  DelInstrs,
DenseMap< unsigned, unsigned > &  InstrIdxForVirtReg 
) const
override

When getMachineCombinerPatterns() finds patterns, this function generates the instructions that could replace the original code sequence.

When getMachineCombinerPatterns() finds potential patterns, this function generates the instructions that could replace the original code sequence.

Definition at line 7428 of file AArch64InstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), llvm::AArch64_IMM::expandMOVImm(), llvm::FMLAv1i32_indexed_OP1, llvm::FMLAv1i32_indexed_OP2, llvm::FMLAv1i64_indexed_OP1, llvm::FMLAv1i64_indexed_OP2, llvm::FMLAv2f32_OP1, llvm::FMLAv2f32_OP2, llvm::FMLAv2f64_OP1, llvm::FMLAv2f64_OP2, llvm::FMLAv2i32_indexed_OP1, llvm::FMLAv2i32_indexed_OP2, llvm::FMLAv2i64_indexed_OP1, llvm::FMLAv2i64_indexed_OP2, llvm::FMLAv4f16_OP1, llvm::FMLAv4f16_OP2, llvm::FMLAv4f32_OP1, llvm::FMLAv4f32_OP2, llvm::FMLAv4i16_indexed_OP1, llvm::FMLAv4i16_indexed_OP2, llvm::FMLAv4i32_indexed_OP1, llvm::FMLAv4i32_indexed_OP2, llvm::FMLAv8f16_OP1, llvm::FMLAv8f16_OP2, llvm::FMLAv8i16_indexed_OP1, llvm::FMLAv8i16_indexed_OP2, llvm::FMLSv1i32_indexed_OP2, llvm::FMLSv1i64_indexed_OP2, llvm::FMLSv2f32_OP1, llvm::FMLSv2f32_OP2, llvm::FMLSv2f64_OP1, llvm::FMLSv2f64_OP2, llvm::FMLSv2i32_indexed_OP1, llvm::FMLSv2i32_indexed_OP2, llvm::FMLSv2i64_indexed_OP1, llvm::FMLSv2i64_indexed_OP2, llvm::FMLSv4f16_OP1, llvm::FMLSv4f16_OP2, llvm::FMLSv4f32_OP1, llvm::FMLSv4f32_OP2, llvm::FMLSv4i16_indexed_OP1, llvm::FMLSv4i16_indexed_OP2, llvm::FMLSv4i32_indexed_OP1, llvm::FMLSv4i32_indexed_OP2, llvm::FMLSv8f16_OP1, llvm::FMLSv8f16_OP2, llvm::FMLSv8i16_indexed_OP1, llvm::FMLSv8i16_indexed_OP2, llvm::FMULADDD_OP1, llvm::FMULADDD_OP2, llvm::FMULADDH_OP1, llvm::FMULADDH_OP2, llvm::FMULADDS_OP1, llvm::FMULADDS_OP2, llvm::FMULSUBD_OP1, llvm::FMULSUBD_OP2, llvm::FMULSUBH_OP1, llvm::FMULSUBH_OP2, llvm::FMULSUBS_OP1, llvm::FMULSUBS_OP2, llvm::FMULv2i32_indexed_OP1, llvm::FMULv2i32_indexed_OP2, llvm::FMULv2i64_indexed_OP1, llvm::FMULv2i64_indexed_OP2, llvm::FMULv4i16_indexed_OP1, llvm::FMULv4i16_indexed_OP2, llvm::FMULv4i32_indexed_OP1, llvm::FMULv4i32_indexed_OP2, llvm::FMULv8i16_indexed_OP1, llvm::FMULv8i16_indexed_OP2, llvm::FNMADD, llvm::FNMULSUBD_OP1, llvm::FNMULSUBH_OP1, llvm::FNMULSUBS_OP1, llvm::TargetInstrInfo::genAlternativeCodeSequence(), genFNegatedMAD(), genFusedMultiply(), genFusedMultiplyAcc(), genFusedMultiplyAccNeg(), genFusedMultiplyIdx(), genFusedMultiplyIdxNeg(), genIndexedMultiply(), genMaddR(), genSubAdd2SubSub(), llvm::MachineInstr::getFlags(), llvm::MachineOperand::getImm(), llvm::TargetSubtargetInfo::getInstrInfo(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineFunction::getRegInfo(), llvm::MachineFunction::getSubtarget(), llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::insert(), Insn, llvm::MachineOperand::isImm(), MBB, llvm::MachineInstr::mergeFlagsWith(), MI, MRI, llvm::MULADDv16i8_OP1, llvm::MULADDv16i8_OP2, llvm::MULADDv2i32_indexed_OP1, llvm::MULADDv2i32_indexed_OP2, llvm::MULADDv2i32_OP1, llvm::MULADDv2i32_OP2, llvm::MULADDv4i16_indexed_OP1, llvm::MULADDv4i16_indexed_OP2, llvm::MULADDv4i16_OP1, llvm::MULADDv4i16_OP2, llvm::MULADDv4i32_indexed_OP1, llvm::MULADDv4i32_indexed_OP2, llvm::MULADDv4i32_OP1, llvm::MULADDv4i32_OP2, llvm::MULADDv8i16_indexed_OP1, llvm::MULADDv8i16_indexed_OP2, llvm::MULADDv8i16_OP1, llvm::MULADDv8i16_OP2, llvm::MULADDv8i8_OP1, llvm::MULADDv8i8_OP2, llvm::MULADDW_OP1, llvm::MULADDW_OP2, llvm::MULADDWI_OP1, llvm::MULADDX_OP1, llvm::MULADDX_OP2, llvm::MULADDXI_OP1, llvm::MULSUBv16i8_OP1, llvm::MULSUBv16i8_OP2, llvm::MULSUBv2i32_indexed_OP1, llvm::MULSUBv2i32_indexed_OP2, llvm::MULSUBv2i32_OP1, llvm::MULSUBv2i32_OP2, llvm::MULSUBv4i16_indexed_OP1, llvm::MULSUBv4i16_indexed_OP2, llvm::MULSUBv4i16_OP1, llvm::MULSUBv4i16_OP2, llvm::MULSUBv4i32_indexed_OP1, llvm::MULSUBv4i32_indexed_OP2, llvm::MULSUBv4i32_OP1, llvm::MULSUBv4i32_OP2, llvm::MULSUBv8i16_indexed_OP1, llvm::MULSUBv8i16_indexed_OP2, llvm::MULSUBv8i16_OP1, llvm::MULSUBv8i16_OP2, llvm::MULSUBv8i8_OP1, llvm::MULSUBv8i8_OP2, llvm::MULSUBW_OP1, llvm::MULSUBW_OP2, llvm::MULSUBWI_OP1, llvm::MULSUBX_OP1, llvm::MULSUBX_OP2, llvm::MULSUBXI_OP1, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::SignExtend64(), llvm::SUBADD_OP1, llvm::SUBADD_OP2, and TII.

◆ getAddrModeFromMemoryOp()

std::optional< ExtAddrMode > AArch64InstrInfo::getAddrModeFromMemoryOp ( const MachineInstr &  MemI,
const TargetRegisterInfo *  TRI 
) const
override

Definition at line 2868 of file AArch64InstrInfo.cpp.

References llvm::sampleprof::Base, llvm::ExtAddrMode::BaseReg, llvm::ExtAddrMode::Displacement, llvm::Offset, llvm::ExtAddrMode::Scale, llvm::ExtAddrMode::ScaledReg, and TRI.

◆ getBranchDestBlock()

MachineBasicBlock * AArch64InstrInfo::getBranchDestBlock ( const MachineInstr &  MI) const
override

Definition at line 252 of file AArch64InstrInfo.cpp.

References llvm_unreachable, and MI.

Referenced by analyzeBranch().

◆ getCombinerObjective()

CombinerObjective AArch64InstrInfo::getCombinerObjective ( unsigned  Pattern) const
override

Definition at line 7046 of file AArch64InstrInfo.cpp.

References llvm::TargetInstrInfo::getCombinerObjective(), llvm::MustReduceDepth, llvm::SUBADD_OP1, and llvm::SUBADD_OP2.

◆ getElementSizeForOpcode()

uint64_t AArch64InstrInfo::getElementSizeForOpcode ( unsigned  Opc) const

Returns the vector element size (B, H, S or D) of an SVE opcode.

Definition at line 9948 of file AArch64InstrInfo.cpp.

References llvm::AArch64::ElementSizeMask, and llvm::get().

◆ getInstSizeInBytes()

unsigned AArch64InstrInfo::getInstSizeInBytes ( const MachineInstr &  MI) const
override

GetInstSize - Return the number of bytes of code the specified instruction may be.

This returns the maximum number of bytes.

Definition at line 88 of file AArch64InstrInfo.cpp.

References assert(), F, llvm::AArch64Subtarget::getAuthenticatedLRCheckMethod(), llvm::AArch64PAuth::getCheckerSizeInBytes(), llvm::MachineFunction::getFunction(), llvm::MachineFunction::getInfo(), llvm::TargetMachine::getMCAsmInfo(), llvm::StackMapOpers::getNumPatchBytes(), llvm::PatchPointOpers::getNumPatchBytes(), llvm::StatepointOpers::getNumPatchBytes(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getSubtarget(), llvm::MachineFunction::getTarget(), isTailCallReturnInst(), MBB, and MI.

Referenced by getOutliningCandidateInfo().

◆ getLdStAmountOp()

const MachineOperand & AArch64InstrInfo::getLdStAmountOp ( const MachineInstr &  MI)
static

Returns the shift amount operator of a load/store.

Definition at line 4553 of file AArch64InstrInfo.cpp.

References llvm_unreachable, and MI.

◆ getLdStBaseOp()

const MachineOperand & AArch64InstrInfo::getLdStBaseOp ( const MachineInstr &  MI)
static

Returns the base register operator of a load/store.

Definition at line 4535 of file AArch64InstrInfo.cpp.

References assert(), Idx, isPairedLdSt(), isPreLdSt(), and MI.

Referenced by isMergeableLdStUpdate(), and mayOverlapWrite().

◆ getLdStOffsetOp()

const MachineOperand & AArch64InstrInfo::getLdStOffsetOp ( const MachineInstr &  MI)
static

Returns the immediate offset operator of a load/store.

Definition at line 4544 of file AArch64InstrInfo.cpp.

References assert(), Idx, isPairedLdSt(), isPreLdSt(), and MI.

Referenced by isLdOffsetInRangeOfSt(), isMergeableLdStUpdate(), mayOverlapWrite(), and needReorderStoreMI().

◆ getLoadStoreImmIdx()

unsigned AArch64InstrInfo::getLoadStoreImmIdx ( unsigned  Opc)
static

Returns the index for the immediate for a given instruction.

Definition at line 2357 of file AArch64InstrInfo.cpp.

References llvm_unreachable.

Referenced by llvm::isAArch64FrameOffsetLegal().

◆ getMachineCombinerPatterns()

bool AArch64InstrInfo::getMachineCombinerPatterns ( MachineInstr &  Root,
SmallVectorImpl< unsigned > &  Patterns,
bool  DoRegPressureReduce 
) const
override

Return true when there is potentially a faster code sequence for an instruction chain ending in Root.

Return true when there is potentially a faster code sequence for an instruction chain ending in Root.

All potential patterns are listed in the Patterns array.

All potential patterns are listed in the Pattern vector. Pattern should be sorted in priority order since the pattern evaluator stops checking as soon as it finds a faster sequence.

Definition at line 7061 of file AArch64InstrInfo.cpp.

References getFMAPatterns(), getFMULPatterns(), getFNEGPatterns(), llvm::TargetInstrInfo::getMachineCombinerPatterns(), getMaddPatterns(), and getMiscPatterns().

◆ getMemOpBaseRegImmOfsOffsetOperand()

MachineOperand & AArch64InstrInfo::getMemOpBaseRegImmOfsOffsetOperand ( MachineInstr &  LdSt) const

Return the immediate offset of the base register in a load/store LdSt.

Definition at line 3911 of file AArch64InstrInfo.cpp.

References assert(), llvm::MachineInstr::getNumExplicitOperands(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::isImm(), and llvm::MachineInstr::mayLoadOrStore().

◆ getMemOperandsWithOffsetWidth()

bool AArch64InstrInfo::getMemOperandsWithOffsetWidth ( const MachineInstr &  MI,
SmallVectorImpl< const MachineOperand * > &  BaseOps,
int64_t &  Offset,
bool &  OffsetIsScalable,
LocationSize &  Width,
const TargetRegisterInfo *  TRI 
) const
override

Definition at line 2848 of file AArch64InstrInfo.cpp.

References getMemOperandWithOffsetWidth(), llvm::MachineInstr::mayLoadOrStore(), llvm::Offset, llvm::LocationSize::precise(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), and TRI.

◆ getMemOperandWithOffsetWidth()

bool AArch64InstrInfo::getMemOperandWithOffsetWidth ( const MachineInstr &  MI,
const MachineOperand *&  BaseOp,
int64_t &  Offset,
bool &  OffsetIsScalable,
TypeSize &  Width,
const TargetRegisterInfo *  TRI 
) const

If OffsetIsScalable is set to 'true', the offset is scaled by vscale.

This is true for some SVE instructions like ldr/str that have a 'reg + imm' addressing mode where the immediate is an index to the scalable vector located at 'reg + imm * vscale x #bytes'.

Definition at line 3862 of file AArch64InstrInfo.cpp.

References assert(), llvm::MachineOperand::getImm(), llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getKnownMinValue(), getMemOpInfo(), llvm::MachineInstr::getNumExplicitOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::isFI(), llvm::MachineOperand::isImm(), isPostIndexLdStOpcode(), llvm::MachineOperand::isReg(), llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::isScalable(), llvm::MachineInstr::mayLoadOrStore(), and llvm::Offset.

Referenced by areMemAccessesTriviallyDisjoint(), and getMemOperandsWithOffsetWidth().

◆ getMemOpInfo()

bool AArch64InstrInfo::getMemOpInfo ( unsigned  Opcode,
TypeSize &  Scale,
TypeSize &  Width,
int64_t &  MinOffset,
int64_t &  MaxOffset 
)
static

Returns true if opcode Opc is a memory operation.

If it is, set Scale, Width, MinOffset, and MaxOffset accordingly.

For unscaled instructions, Scale is set to 1. All values are in bytes. MinOffset/MaxOffset are the un-scaled limits of the immediate in the instruction, the actual offset limit is [MinOffset*Scale, MaxOffset*Scale].

Definition at line 3918 of file AArch64InstrInfo.cpp.

References llvm::TypeSize::getFixed(), and llvm::TypeSize::getScalable().

Referenced by emitLoad(), emitStore(), getMemOperandWithOffsetWidth(), and llvm::isAArch64FrameOffsetLegal().

◆ getMemScale() [1/2]

static int llvm::AArch64InstrInfo::getMemScale ( const MachineInstr &  MI)
inlinestatic

Definition at line 232 of file AArch64InstrInfo.h.

References getMemScale(), and MI.

◆ getMemScale() [2/2]

int AArch64InstrInfo::getMemScale ( unsigned  Opc)
static

Scaling factor for (scaled or unscaled) load or store.

Definition at line 4411 of file AArch64InstrInfo.cpp.

References llvm_unreachable.

Referenced by getMemScale(), getPrePostIndexedMemOpInfo(), mayOverlapWrite(), scaleOffset(), and shouldClusterFI().

◆ getNop()

MCInst AArch64InstrInfo::getNop ( ) const
override

Definition at line 6254 of file AArch64InstrInfo.cpp.

References llvm::MCInstBuilder::addImm().

◆ getOutlinableRanges()

SmallVector< std::pair< MachineBasicBlock::iterator, MachineBasicBlock::iterator > > AArch64InstrInfo::getOutlinableRanges ( MachineBasicBlock &  MBB,
unsigned &  Flags 
) const
override

Definition at line 9198 of file AArch64InstrInfo.cpp.

References llvm::LiveRegUnits::addLiveOuts(), assert(), llvm::LiveRegUnits::available(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), getRegisterInfo(), llvm::MachineBasicBlock::instr_rbegin(), llvm::MachineBasicBlock::instr_rend(), llvm::make_range(), MBB, MI, llvm::LiveRegUnits::stepBackward(), and llvm::MachineRegisterInfo::tracksLiveness().

◆ getOutliningCandidateInfo()

std::optional< std::unique_ptr< outliner::OutlinedFunction > > AArch64InstrInfo::getOutliningCandidateInfo ( const MachineModuleInfo &  MMI,
std::vector< outliner::Candidate > &  RepeatedSequenceLocs,
unsigned  MinRepeats 
) const
override

Definition at line 8732 of file AArch64InstrInfo.cpp.

References getInstSizeInBytes(), and MI.

◆ getOutliningTypeImpl()

outliner::InstrType AArch64InstrInfo::getOutliningTypeImpl ( const MachineModuleInfo &  MMI,
MachineBasicBlock::iterator &  MIT,
unsigned  Flags 
) const
override

Definition at line 9311 of file AArch64InstrInfo.cpp.

References assert(), llvm::SmallPtrSetImpl< PtrType >::count(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getInfo(), llvm::AArch64FunctionInfo::getLOHRelated(), llvm::MachineModuleInfo::getMachineFunction(), llvm::MachineFrameInfo::getNumObjects(), llvm::MachineBasicBlock::getParent(), getRegisterInfo(), llvm::MachineFrameInfo::getStackSize(), hasBTISemantics(), llvm::outliner::Illegal, llvm::MachineFrameInfo::isCalleeSavedInfoValid(), llvm::outliner::Legal, llvm::outliner::LegalTerminator, MBB, and MI.

◆ getRegisterInfo()

const AArch64RegisterInfo & llvm::AArch64InstrInfo::getRegisterInfo ( ) const
inline

getRegisterInfo - TargetInstrInfo is a superset of MRegister info.

As such, whenever a client has an instance of instruction info, it should always be able to get register info as well (through this method).

Definition at line 186 of file AArch64InstrInfo.h.

Referenced by analyzeLoopForPipelining(), areMemAccessesTriviallyDisjoint(), copyGPRRegTuple(), copyPhysReg(), copyPhysRegTuple(), getOutlinableRanges(), getOutliningTypeImpl(), llvm::AArch64Subtarget::getRegisterInfo(), isCandidateToMergeOrPair(), loadRegFromStackSlot(), optimizeCondBranch(), and storeRegToStackSlot().

◆ getSerializableBitmaskMachineOperandTargetFlags()

ArrayRef< std::pair< unsigned, const char * > > AArch64InstrInfo::getSerializableBitmaskMachineOperandTargetFlags ( ) const
override

Definition at line 8564 of file AArch64InstrInfo.cpp.

◆ getSerializableDirectMachineOperandTargetFlags()

ArrayRef< std::pair< unsigned, const char * > > AArch64InstrInfo::getSerializableDirectMachineOperandTargetFlags ( ) const
override

Definition at line 8552 of file AArch64InstrInfo.cpp.

◆ getSerializableMachineMemOperandTargetFlags()

ArrayRef< std::pair< MachineMemOperand::Flags, const char * > > AArch64InstrInfo::getSerializableMachineMemOperandTargetFlags ( ) const
override

Definition at line 8582 of file AArch64InstrInfo.cpp.

References llvm::MOStridedAccess, and llvm::MOSuppressPair.

◆ getTailDuplicateSize()

unsigned int AArch64InstrInfo::getTailDuplicateSize ( CodeGenOptLevel  OptLevel) const
override

Definition at line 9961 of file AArch64InstrInfo.cpp.

References llvm::Aggressive.

◆ getUnscaledLdSt()

std::optional< unsigned > AArch64InstrInfo::getUnscaledLdSt ( unsigned  Opc)
static

Returns the unscaled load/store for the scaled load/store opcode, if there is a corresponding unscaled variant available.

Definition at line 2327 of file AArch64InstrInfo.cpp.

Referenced by llvm::isAArch64FrameOffsetLegal().

◆ hasBTISemantics()

bool AArch64InstrInfo::hasBTISemantics ( const MachineInstr &  MI)
static

Returns whether the instruction can be compatible with non-zero BTYPE.

Definition at line 4611 of file AArch64InstrInfo.cpp.

References MI.

Referenced by getOutliningTypeImpl(), and isSchedulingBoundary().

◆ hasUnscaledLdStOffset() [1/2]

static bool llvm::AArch64InstrInfo::hasUnscaledLdStOffset ( MachineInstr &  MI)
inlinestatic

Definition at line 222 of file AArch64InstrInfo.h.

References hasUnscaledLdStOffset(), and MI.

◆ hasUnscaledLdStOffset() [2/2]

bool AArch64InstrInfo::hasUnscaledLdStOffset ( unsigned  Opc)
static

Return true if it has an unscaled load/store offset.

Definition at line 2291 of file AArch64InstrInfo.cpp.

Referenced by hasUnscaledLdStOffset(), mayOverlapWrite(), and shouldClusterMemOps().

◆ insertBranch()

unsigned AArch64InstrInfo::insertBranch ( MachineBasicBlock &  MBB,
MachineBasicBlock *  TBB,
MachineBasicBlock *  FBB,
ArrayRef< MachineOperand >  Cond,
const DebugLoc &  DL,
int *  BytesAdded = nullptr 
) const
override

Definition at line 604 of file AArch64InstrInfo.cpp.

References llvm::MachineInstrBuilder::addMBB(), assert(), llvm::BuildMI(), Cond, DL, llvm::get(), MBB, and TBB.

◆ insertIndirectBranch()

void AArch64InstrInfo::insertIndirectBranch ( MachineBasicBlock &  MBB,
MachineBasicBlock &  NewDestBB,
MachineBasicBlock &  RestoreBB,
const DebugLoc &  DL,
int64_t  BrOffset,
RegScavenger *  RS 
) const
override

Definition at line 272 of file AArch64InstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), llvm::MachineInstrBuilder::addSym(), assert(), llvm::BuildMI(), llvm::MBBSectionID::ColdSectionID, llvm::RegState::Define, DL, llvm::MachineBasicBlock::empty(), llvm::MachineBasicBlock::end(), llvm::RegScavenger::enterBasicBlockEnd(), llvm::RegScavenger::FindUnusedReg(), llvm::get(), llvm::MachineFunction::getInfo(), llvm::MachineBasicBlock::getParent(), llvm::MachineBasicBlock::getSectionID(), llvm::AArch64FunctionInfo::hasRedZone(), llvm::RegScavenger::isRegUsed(), MBB, llvm::AArch64II::MO_NC, llvm::AArch64II::MO_PAGE, llvm::AArch64II::MO_PAGEOFF, llvm::MachineBasicBlock::pred_size(), llvm::report_fatal_error(), and llvm::RegScavenger::setRegUsed().

◆ insertNoop()

void AArch64InstrInfo::insertNoop ( MachineBasicBlock &  MBB,
MachineBasicBlock::iterator  MI 
) const
override

Definition at line 6248 of file AArch64InstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::BuildMI(), DL, llvm::get(), MBB, and MI.

◆ insertOutlinedCall()

MachineBasicBlock::iterator AArch64InstrInfo::insertOutlinedCall ( Module &  M,
MachineBasicBlock &  MBB,
MachineBasicBlock::iterator &  It,
MachineFunction &  MF,
outliner::Candidate &  C 
) const
override

Definition at line 9631 of file AArch64InstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineBasicBlock::addLiveIn(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), llvm::CallingConv::C, llvm::RegState::Define, llvm::get(), llvm::MachineFunction::getName(), llvm::MachineBasicBlock::insert(), llvm::MachineBasicBlock::isLiveIn(), MachineOutlinerNoLRSave, MachineOutlinerRegSave, MachineOutlinerTailCall, MachineOutlinerThunk, and MBB.

◆ insertSelect()

void AArch64InstrInfo::insertSelect ( MachineBasicBlock &  MBB,
MachineBasicBlock::iterator  MI,
const DebugLoc &  DL,
Register  DstReg,
ArrayRef< MachineOperand >  Cond,
Register  TrueReg,
Register  FalseReg 
) const
override

Definition at line 763 of file AArch64InstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), canFoldIntoCSel(), CC, Cond, DL, llvm::AArch64_AM::encodeLogicalImmediate(), llvm::AArch64CC::EQ, llvm::get(), llvm::AArch64CC::getInvertedCondCode(), llvm::MachineBasicBlock::getParent(), getReg(), llvm::MachineFunction::getRegInfo(), I, llvm_unreachable, MBB, MRI, and llvm::AArch64CC::NE.

◆ isAddImmediate()

std::optional< RegImmPair > AArch64InstrInfo::isAddImmediate ( const MachineInstr &  MI,
Register  Reg 
) const
override

Definition at line 9778 of file AArch64InstrInfo.cpp.

References assert(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isReg(), MI, and llvm::Offset.

◆ isAsCheapAsAMove()

bool AArch64InstrInfo::isAsCheapAsAMove ( const MachineInstr &  MI) const
override

Definition at line 915 of file AArch64InstrInfo.cpp.

References isCheapImmediate(), and MI.

◆ isAssociativeAndCommutative()

bool AArch64InstrInfo::isAssociativeAndCommutative ( const MachineInstr &  Inst,
bool  Invert 
) const
override

Return true when Inst is associative and commutative so that it can be reassociated.

If Invert is true, then the inverse of Inst operation must be checked.

Definition at line 6419 of file AArch64InstrInfo.cpp.

References llvm::MachineInstr::FmNsz, llvm::MachineInstr::FmReassoc, llvm::MachineInstr::getFlag(), llvm::MachineInstr::getOpcode(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineFunction::getTarget(), llvm::TargetMachine::Options, and llvm::TargetOptions::UnsafeFPMath.

◆ isBranchOffsetInRange()

bool AArch64InstrInfo::isBranchOffsetInRange ( unsigned  BranchOpc,
int64_t  BrOffset 
) const
override
Returns
true if a branch from an instruction with opcode BranchOpc bytes is capable of jumping to a position BrOffset bytes away.

Definition at line 243 of file AArch64InstrInfo.cpp.

References assert(), getBranchDisplacementBits(), and llvm::isIntN().

◆ isCandidateToMergeOrPair()

bool AArch64InstrInfo::isCandidateToMergeOrPair ( const MachineInstr &  MI) const

Return true if this is a load/store that can be potentially paired/merged.

Definition at line 2778 of file AArch64InstrInfo.cpp.

References assert(), llvm::MachineInstr::FrameDestroy, llvm::MachineInstr::FrameSetup, getRegisterInfo(), isLdStPairSuppressed(), isPreLdSt(), MI, TRI, and llvm::MCAsmInfo::usesWindowsCFI().

Referenced by shouldClusterMemOps().

◆ isCoalescableExtInstr()

bool AArch64InstrInfo::isCoalescableExtInstr ( const MachineInstr &  MI,
Register &  SrcReg,
Register &  DstReg,
unsigned &  SubIdx 
) const
override

Definition at line 1093 of file AArch64InstrInfo.cpp.

References MI.

◆ isCopyInstrImpl()

std::optional< DestSourcePair > AArch64InstrInfo::isCopyInstrImpl ( const MachineInstr &  MI) const
overrideprotected

If the specific machine instruction is an instruction that moves/copies value from one register to another register return destination and source registers as machine operands.

Definition at line 9740 of file AArch64InstrInfo.cpp.

References MI.

◆ isCopyLikeInstrImpl()

std::optional< DestSourcePair > AArch64InstrInfo::isCopyLikeInstrImpl ( const MachineInstr &  MI) const
overrideprotected

Definition at line 9767 of file AArch64InstrInfo.cpp.

References MI.

◆ isExtendLikelyToBeFolded()

bool AArch64InstrInfo::isExtendLikelyToBeFolded ( MachineInstr &  ExtMI,
MachineRegisterInfo &  MRI 
) const
override

Definition at line 9928 of file AArch64InstrInfo.cpp.

References assert(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), and MRI.

◆ isFalkorShiftExtFast()

bool AArch64InstrInfo::isFalkorShiftExtFast ( const MachineInstr &  MI)
static

Returns true if the instruction has a shift by immediate that can be executed in one cycle less.

Definition at line 942 of file AArch64InstrInfo.cpp.

References llvm::AArch64_AM::ASR, llvm::AArch64_AM::getArithExtendType(), llvm::AArch64_AM::getArithShiftValue(), llvm::AArch64_AM::getShiftType(), llvm::AArch64_AM::getShiftValue(), llvm::AArch64_AM::LSL, MI, llvm::AArch64_AM::UXTB, llvm::AArch64_AM::UXTH, llvm::AArch64_AM::UXTW, and llvm::AArch64_AM::UXTX.

◆ isFpOrNEON() [1/2]

bool AArch64InstrInfo::isFpOrNEON ( const MachineInstr &  MI)
static

Returns whether the instruction is FP or NEON.

Definition at line 4648 of file AArch64InstrInfo.cpp.

References llvm::any_of(), getRegClass(), isFpOrNEON(), and MI.

◆ isFpOrNEON() [2/2]

bool AArch64InstrInfo::isFpOrNEON ( Register  Reg)
static

Returns whether the physical register is FP or NEON.

Definition at line 4637 of file AArch64InstrInfo.cpp.

References assert().

Referenced by llvm::AArch64FrameLowering::assignCalleeSavedSpillSlots(), computeCalleeSaveRegisterPairs(), isFpOrNEON(), and llvm::AArch64FrameLowering::orderFrameObjects().

◆ isFPRCopy()

bool AArch64InstrInfo::isFPRCopy ( const MachineInstr &  MI)
static

Does this instruction rename an FPR without modifying bits?

Definition at line 2204 of file AArch64InstrInfo.cpp.

References assert(), and MI.

◆ isFunctionSafeToOutlineFrom()

bool AArch64InstrInfo::isFunctionSafeToOutlineFrom ( MachineFunction &  MF,
bool  OutlineFromLinkOnceODRs 
) const
override

Definition at line 9160 of file AArch64InstrInfo.cpp.

References F, llvm::MachineFunction::getFunction(), llvm::MachineFunction::getInfo(), llvm::TargetMachine::getMCAsmInfo(), llvm::MachineFunction::getTarget(), llvm::AArch64FunctionInfo::hasRedZone(), llvm::AArch64FunctionInfo::hasStreamingModeChanges(), and llvm::MCAsmInfo::usesWindowsCFI().

◆ isFunctionSafeToSplit()

bool AArch64InstrInfo::isFunctionSafeToSplit ( const MachineFunction &  MF) const
override

Definition at line 9851 of file AArch64InstrInfo.cpp.

References llvm::MachineFunction::getInfo(), llvm::AArch64FunctionInfo::hasRedZone(), and llvm::TargetInstrInfo::isFunctionSafeToSplit().

◆ isGPRCopy()

bool AArch64InstrInfo::isGPRCopy ( const MachineInstr &  MI)
static

Does this instruction rename a GPR without modifying bits?

Definition at line 2174 of file AArch64InstrInfo.cpp.

References assert(), contains(), and MI.

◆ isGPRZero()

bool AArch64InstrInfo::isGPRZero ( const MachineInstr &  MI)
static

Does this instruction set its full destination register to zero?

Definition at line 2150 of file AArch64InstrInfo.cpp.

References assert(), and MI.

◆ isHForm()

bool AArch64InstrInfo::isHForm ( const MachineInstr &  MI)
static

Returns whether the instruction is in H form (16 bit operands)

Definition at line 4583 of file AArch64InstrInfo.cpp.

References llvm::any_of(), contains(), getRegClass(), and MI.

◆ isLdStPairSuppressed()

bool AArch64InstrInfo::isLdStPairSuppressed ( const MachineInstr &  MI)
static

Return true if pairing the given load or store is hinted to be unprofitable.

Check all MachineMemOperands for a hint to suppress pairing.

Definition at line 2271 of file AArch64InstrInfo.cpp.

References llvm::any_of(), and MI.

Referenced by isCandidateToMergeOrPair().

◆ isLegalAddressingMode()

bool AArch64InstrInfo::isLegalAddressingMode ( unsigned  NumBytes,
int64_t  Offset,
unsigned  Scale 
) const

Definition at line 9965 of file AArch64InstrInfo.cpp.

References llvm::Log2_64(), and llvm::Offset.

Referenced by canFoldIntoAddrMode(), and llvm::AArch64TargetLowering::isLegalAddressingMode().

◆ isLoadFromStackSlot()

Register AArch64InstrInfo::isLoadFromStackSlot ( const MachineInstr &  MI,
int &  FrameIndex 
) const
override

Definition at line 2223 of file AArch64InstrInfo.cpp.

References MI.

◆ isMBBSafeToSplitToCold()

bool AArch64InstrInfo::isMBBSafeToSplitToCold ( const MachineBasicBlock &  MBB) const
override

Definition at line 9862 of file AArch64InstrInfo.cpp.

References llvm::any_of(), llvm::MachineFunction::getJumpTableInfo(), llvm::MachineJumpTableInfo::getJumpTables(), llvm::MachineBasicBlock::getParent(), llvm::is_contained(), llvm::MachineBasicBlock::isInlineAsmBrIndirectTarget(), MBB, and MI.

◆ isPairableLdStInst()

bool AArch64InstrInfo::isPairableLdStInst ( const MachineInstr &  MI)
static

Return true if pairing the given load or store may be paired with another.

Definition at line 2625 of file AArch64InstrInfo.cpp.

References MI.

Referenced by shouldClusterMemOps().

◆ isPairedLdSt()

bool AArch64InstrInfo::isPairedLdSt ( const MachineInstr &  MI)
static

Returns whether the instruction is a paired load/store.

Definition at line 4515 of file AArch64InstrInfo.cpp.

References MI.

Referenced by getLdStBaseOp(), getLdStOffsetOp(), getLdStRegOp(), getPrePostIndexedMemOpInfo(), and mayOverlapWrite().

◆ isPreLd()

bool AArch64InstrInfo::isPreLd ( const MachineInstr &  MI)
static

Returns whether the instruction is a pre-indexed load.

Definition at line 4484 of file AArch64InstrInfo.cpp.

References MI.

Referenced by isPreLdSt().

◆ isPreLdSt()

bool AArch64InstrInfo::isPreLdSt ( const MachineInstr &  MI)
static

Returns whether the instruction is a pre-indexed load/store.

Definition at line 4511 of file AArch64InstrInfo.cpp.

References isPreLd(), isPreSt(), and MI.

Referenced by areCandidatesToMergeOrPair(), getLdStBaseOp(), getLdStOffsetOp(), getLdStRegOp(), and isCandidateToMergeOrPair().

◆ isPreSt()

bool AArch64InstrInfo::isPreSt ( const MachineInstr &  MI)
static

Returns whether the instruction is a pre-indexed store.

Definition at line 4498 of file AArch64InstrInfo.cpp.

References MI.

Referenced by isPreLdSt().

◆ isPTestLikeOpcode()

bool AArch64InstrInfo::isPTestLikeOpcode ( unsigned  Opc) const

Returns true if the opcode is for an SVE instruction that sets the condition codes as if it's results had been fed to a PTEST instruction along with the same general predicate.

Definition at line 9952 of file AArch64InstrInfo.cpp.

References llvm::get(), and llvm::AArch64::InstrFlagIsPTestLike.

◆ isQForm()

bool AArch64InstrInfo::isQForm ( const MachineInstr &  MI)
static

Returns whether the instruction is in Q form (128 bit operands)

Definition at line 4597 of file AArch64InstrInfo.cpp.

References llvm::any_of(), contains(), getRegClass(), and MI.

◆ isSchedulingBoundary()

bool AArch64InstrInfo::isSchedulingBoundary ( const MachineInstr &  MI,
const MachineBasicBlock *  MBB,
const MachineFunction &  MF 
) const
override

Definition at line 1152 of file AArch64InstrInfo.cpp.

References llvm::MachineBasicBlock::end(), hasBTISemantics(), llvm::TargetInstrInfo::isSchedulingBoundary(), isSEHInstruction(), MBB, and MI.

◆ isSEHInstruction()

bool AArch64InstrInfo::isSEHInstruction ( const MachineInstr &  MI)
static

Return true if the instructions is a SEH instruciton used for unwinding on Windows.

Definition at line 1064 of file AArch64InstrInfo.cpp.

References MI.

Referenced by convertCalleeSaveRestoreToSPPrePostIncDec(), llvm::AArch64FrameLowering::emitEpilogue(), fixupCalleeSaveRestoreStackOffset(), and isSchedulingBoundary().

◆ isStoreToStackSlot()

Register AArch64InstrInfo::isStoreToStackSlot ( const MachineInstr &  MI,
int &  FrameIndex 
) const
override

Definition at line 2247 of file AArch64InstrInfo.cpp.

References MI.

◆ isStridedAccess()

bool AArch64InstrInfo::isStridedAccess ( const MachineInstr &  MI)
static

Return true if the given load or store is a strided memory access.

Check all MachineMemOperands for a hint that the load/store is strided.

Definition at line 2285 of file AArch64InstrInfo.cpp.

References llvm::any_of(), and MI.

◆ isSubregFoldable()

bool llvm::AArch64InstrInfo::isSubregFoldable ( ) const
inlineoverride

Definition at line 364 of file AArch64InstrInfo.h.

◆ isTailCallReturnInst()

bool AArch64InstrInfo::isTailCallReturnInst ( const MachineInstr &  MI)
static

Returns true if MI is one of the TCRETURN* instructions.

Definition at line 2668 of file AArch64InstrInfo.cpp.

References assert(), and MI.

Referenced by getArgumentStackToRestore(), and getInstSizeInBytes().

◆ isThroughputPattern()

bool AArch64InstrInfo::isThroughputPattern ( unsigned  Pattern) const
override

Return true when a code sequence can improve throughput.

It should be called only for instructions in loops.

Parameters
Pattern- combiner pattern

Definition at line 6896 of file AArch64InstrInfo.cpp.

References llvm::FMLAv1i32_indexed_OP1, llvm::FMLAv1i32_indexed_OP2, llvm::FMLAv1i64_indexed_OP1, llvm::FMLAv1i64_indexed_OP2, llvm::FMLAv2f32_OP1, llvm::FMLAv2f32_OP2, llvm::FMLAv2f64_OP1, llvm::FMLAv2f64_OP2, llvm::FMLAv2i32_indexed_OP1, llvm::FMLAv2i32_indexed_OP2, llvm::FMLAv2i64_indexed_OP1, llvm::FMLAv2i64_indexed_OP2, llvm::FMLAv4f16_OP1, llvm::FMLAv4f16_OP2, llvm::FMLAv4f32_OP1, llvm::FMLAv4f32_OP2, llvm::FMLAv4i16_indexed_OP1, llvm::FMLAv4i16_indexed_OP2, llvm::FMLAv4i32_indexed_OP1, llvm::FMLAv4i32_indexed_OP2, llvm::FMLAv8f16_OP1, llvm::FMLAv8f16_OP2, llvm::FMLAv8i16_indexed_OP1, llvm::FMLAv8i16_indexed_OP2, llvm::FMLSv1i32_indexed_OP2, llvm::FMLSv1i64_indexed_OP2, llvm::FMLSv2f32_OP2, llvm::FMLSv2f64_OP2, llvm::FMLSv2i32_indexed_OP2, llvm::FMLSv2i64_indexed_OP2, llvm::FMLSv4f16_OP1, llvm::FMLSv4f16_OP2, llvm::FMLSv4f32_OP2, llvm::FMLSv4i16_indexed_OP1, llvm::FMLSv4i16_indexed_OP2, llvm::FMLSv4i32_indexed_OP2, llvm::FMLSv8f16_OP1, llvm::FMLSv8f16_OP2, llvm::FMLSv8i16_indexed_OP1, llvm::FMLSv8i16_indexed_OP2, llvm::FMULADDD_OP1, llvm::FMULADDD_OP2, llvm::FMULADDH_OP1, llvm::FMULADDH_OP2, llvm::FMULADDS_OP1, llvm::FMULADDS_OP2, llvm::FMULSUBD_OP1, llvm::FMULSUBD_OP2, llvm::FMULSUBH_OP1, llvm::FMULSUBH_OP2, llvm::FMULSUBS_OP1, llvm::FMULSUBS_OP2, llvm::FMULv2i32_indexed_OP1, llvm::FMULv2i32_indexed_OP2, llvm::FMULv2i64_indexed_OP1, llvm::FMULv2i64_indexed_OP2, llvm::FMULv4i16_indexed_OP1, llvm::FMULv4i16_indexed_OP2, llvm::FMULv4i32_indexed_OP1, llvm::FMULv4i32_indexed_OP2, llvm::FMULv8i16_indexed_OP1, llvm::FMULv8i16_indexed_OP2, llvm::FNMULSUBD_OP1, llvm::FNMULSUBH_OP1, llvm::FNMULSUBS_OP1, llvm::MULADDv16i8_OP1, llvm::MULADDv16i8_OP2, llvm::MULADDv2i32_indexed_OP1, llvm::MULADDv2i32_indexed_OP2, llvm::MULADDv2i32_OP1, llvm::MULADDv2i32_OP2, llvm::MULADDv4i16_indexed_OP1, llvm::MULADDv4i16_indexed_OP2, llvm::MULADDv4i16_OP1, llvm::MULADDv4i16_OP2, llvm::MULADDv4i32_indexed_OP1, llvm::MULADDv4i32_indexed_OP2, llvm::MULADDv4i32_OP1, llvm::MULADDv4i32_OP2, llvm::MULADDv8i16_indexed_OP1, llvm::MULADDv8i16_indexed_OP2, llvm::MULADDv8i16_OP1, llvm::MULADDv8i16_OP2, llvm::MULADDv8i8_OP1, llvm::MULADDv8i8_OP2, llvm::MULSUBv16i8_OP1, llvm::MULSUBv16i8_OP2, llvm::MULSUBv2i32_indexed_OP1, llvm::MULSUBv2i32_indexed_OP2, llvm::MULSUBv2i32_OP1, llvm::MULSUBv2i32_OP2, llvm::MULSUBv4i16_indexed_OP1, llvm::MULSUBv4i16_indexed_OP2, llvm::MULSUBv4i16_OP1, llvm::MULSUBv4i16_OP2, llvm::MULSUBv4i32_indexed_OP1, llvm::MULSUBv4i32_indexed_OP2, llvm::MULSUBv4i32_OP1, llvm::MULSUBv4i32_OP2, llvm::MULSUBv8i16_indexed_OP1, llvm::MULSUBv8i16_indexed_OP2, llvm::MULSUBv8i16_OP1, llvm::MULSUBv8i16_OP2, llvm::MULSUBv8i8_OP1, and llvm::MULSUBv8i8_OP2.

◆ isWhileOpcode()

bool AArch64InstrInfo::isWhileOpcode ( unsigned  Opc) const

Returns true if the opcode is for an SVE WHILE## instruction.

Definition at line 9956 of file AArch64InstrInfo.cpp.

References llvm::get(), and llvm::AArch64::InstrFlagIsWhile.

Referenced by analyzeLoopForPipelining().

◆ loadRegFromStackSlot()

void AArch64InstrInfo::loadRegFromStackSlot ( MachineBasicBlock &  MBB,
MachineBasicBlock::iterator  MBBI,
Register  DestReg,
int  FrameIndex,
const TargetRegisterClass *  RC,
const TargetRegisterInfo *  TRI,
Register  VReg,
MachineInstr::MIFlag  Flags = MachineInstr::NoFlags 
) const
override

Definition at line 5449 of file AArch64InstrInfo.cpp.

References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), llvm::MachineRegisterInfo::constrainRegClass(), llvm::TargetStackID::Default, llvm::get(), llvm::getDefRegState(), llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineFrameInfo::getObjectAlign(), llvm::MachineFrameInfo::getObjectSize(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), getRegisterInfo(), llvm::RegState::Implicit, llvm::AArch64Subtarget::isSVEorStreamingSVEAvailable(), llvm::Register::isValid(), llvm::Register::isVirtual(), loadRegPairFromStackSlot(), MBB, MBBI, MI, llvm::MachineMemOperand::MOLoad, llvm::MCRegister::NoRegister, llvm::Offset, llvm::TargetStackID::ScalableVector, llvm::MachineFrameInfo::setStackID(), and TRI.

Referenced by foldMemoryOperandImpl().

◆ mergeOutliningCandidateAttributes()

void AArch64InstrInfo::mergeOutliningCandidateAttributes ( Function &  F,
std::vector< outliner::Candidate > &  Candidates 
) const
override

Definition at line 9139 of file AArch64InstrInfo.cpp.

References F.

◆ optimizeCompareInstr()

bool AArch64InstrInfo::optimizeCompareInstr ( MachineInstr &  CmpInstr,
Register  SrcReg,
Register  SrcReg2,
int64_t  CmpMask,
int64_t  CmpValue,
const MachineRegisterInfo *  MRI 
) const
override

optimizeCompareInstr - Convert the instruction supplying the argument to the comparison into one that sets the zero bit in the flags register.

Try to optimize a compare instruction.

A compare instruction is an instruction which produces AArch64::NZCV. It can be truly compare instruction when there are no uses of its destination register.

The following steps are tried in order:

  1. Convert CmpInstr into an unconditional version.
  2. Remove CmpInstr if above there is an instruction producing a needed condition code or an instruction which can be converted into such an instruction. Only comparison with zero is supported.

Definition at line 1547 of file AArch64InstrInfo.cpp.

References assert(), convertToNonFlagSettingOpc(), llvm::MachineInstr::definesRegister(), llvm::MachineInstr::eraseFromParent(), llvm::MachineInstr::findRegisterDefOperandIdx(), llvm::get(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), MRI, llvm::MachineInstr::removeOperand(), llvm::MachineInstr::setDesc(), llvm::succeeded(), and UpdateOperandRegClass().

◆ optimizeCondBranch()

bool AArch64InstrInfo::optimizeCondBranch ( MachineInstr &  MI) const
override

Replace csincr-branch sequence by simple conditional branch.

Examples:

  1. csinc w9, wzr, wzr, <condition code>
    tbnz w9, #0, 0x44
    to
    b.<inverted condition code>
  2. csinc w9, wzr, wzr, <condition code>
    tbz w9, #0, 0x44
    to
    b.<condition code>

Replace compare and branch sequence by TBZ/TBNZ instruction when the compare's constant operand is power of 2.

Examples:

and w8, w8, #0x400
cbnz w8, L1

to

tbnz w8, #10, L1
Parameters
MIConditional Branch
Returns
True when the simple conditional branch is generated

Definition at line 8407 of file AArch64InstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), AK_Write, areCFlagsAccessedBetweenInstrs(), assert(), llvm::BuildMI(), CC, llvm::AArch64_AM::decodeLogicalImmediate(), DefMI, DL, llvm::MachineInstr::findRegisterDefOperandIdx(), llvm::get(), llvm::MachineOperand::getImm(), llvm::AArch64CC::getInvertedCondCode(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), getRegisterInfo(), llvm::MachineInstr::isCopy(), llvm::isPowerOf2_64(), llvm::Register::isVirtual(), llvm_unreachable, llvm::Log2_64(), MBB, MI, MRI, llvm::MachineOperand::setIsKill(), llvm::MachineOperand::setSubReg(), and TBB.

◆ probedStackAlloc()

MachineBasicBlock::iterator AArch64InstrInfo::probedStackAlloc ( MachineBasicBlock::iterator  MBBI,
Register  TargetReg,
bool  FrameSetup 
) const

Definition at line 9997 of file AArch64InstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), llvm::MachineBasicBlock::addSuccessor(), assert(), llvm::MachineBasicBlock::begin(), llvm::BuildMI(), llvm::MachineFunction::CreateMachineBasicBlock(), llvm::RegState::Define, DL, llvm::emitFrameOffset(), llvm::MachineBasicBlock::end(), llvm::MachineBasicBlock::findDebugLoc(), llvm::MachineInstr::FrameSetup, llvm::fullyRecomputeLiveIns(), llvm::AArch64_AM::getArithExtendImm(), llvm::MachineBasicBlock::getBasicBlock(), llvm::StackOffset::getFixed(), llvm::MachineFunction::getInfo(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), llvm::AArch64_AM::getShifterImm(), llvm::MachineFunction::getSubtarget(), llvm::MachineFunction::insert(), llvm::AArch64CC::LE, llvm::AArch64_AM::LSL, MBB, MBBI, llvm::MachineInstr::NoFlags, llvm::MachineRegisterInfo::reservedRegsFrozen(), llvm::MachineInstrBuilder::setMIFlags(), llvm::MachineBasicBlock::splice(), TII, llvm::MachineBasicBlock::transferSuccessorsAndUpdatePHIs(), and llvm::AArch64_AM::UXTX.

◆ removeBranch()

unsigned AArch64InstrInfo::removeBranch ( MachineBasicBlock &  MBB,
int *  BytesRemoved = nullptr 
) const
override

Definition at line 552 of file AArch64InstrInfo.cpp.

References llvm::MachineBasicBlock::begin(), llvm::MachineBasicBlock::end(), llvm::MachineBasicBlock::getLastNonDebugInstr(), I, llvm::isCondBranchOpcode(), llvm::isUncondBranchOpcode(), and MBB.

◆ reverseBranchCondition()

bool AArch64InstrInfo::reverseBranchCondition ( SmallVectorImpl< MachineOperand > &  Cond) const
override

Definition at line 511 of file AArch64InstrInfo.cpp.

References CC, Cond, llvm::AArch64CC::getInvertedCondCode(), and llvm_unreachable.

Referenced by analyzeLoopForPipelining().

◆ shouldClusterMemOps()

bool AArch64InstrInfo::shouldClusterMemOps ( ArrayRef< const MachineOperand * >  BaseOps1,
int64_t  OpOffset1,
bool  OffsetIsScalable1,
ArrayRef< const MachineOperand * >  BaseOps2,
int64_t  OpOffset2,
bool  OffsetIsScalable2,
unsigned  ClusterSize,
unsigned  NumBytes 
) const
override

Detect opportunities for ldp/stp formation.

Only called for LdSt for which getMemOperandWithOffset returns true.

Definition at line 4757 of file AArch64InstrInfo.cpp.

References assert(), canPairLdStOpc(), llvm::ArrayRef< T >::front(), llvm::MachineFunction::getFrameInfo(), llvm::MachineOperand::getImm(), llvm::MachineOperand::getIndex(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getParent(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getType(), hasUnscaledLdStOffset(), isCandidateToMergeOrPair(), llvm::MachineOperand::isFI(), llvm::MachineOperand::isIdenticalTo(), isPairableLdStInst(), llvm::MachineOperand::isReg(), scaleOffset(), shouldClusterFI(), and llvm::ArrayRef< T >::size().

◆ shouldOutlineFromFunctionByDefault()

bool AArch64InstrInfo::shouldOutlineFromFunctionByDefault ( MachineFunction &  MF) const
override

Definition at line 9707 of file AArch64InstrInfo.cpp.

References llvm::MachineFunction::getFunction(), and llvm::Function::hasMinSize().

◆ storeRegToStackSlot()

void AArch64InstrInfo::storeRegToStackSlot ( MachineBasicBlock &  MBB,
MachineBasicBlock::iterator  MBBI,
Register  SrcReg,
bool  isKill,
int  FrameIndex,
const TargetRegisterClass *  RC,
const TargetRegisterInfo *  TRI,
Register  VReg,
MachineInstr::MIFlag  Flags = MachineInstr::NoFlags 
) const
override

Definition at line 5276 of file AArch64InstrInfo.cpp.

References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), llvm::MachineRegisterInfo::constrainRegClass(), llvm::TargetStackID::Default, llvm::get(), llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getFrameInfo(), llvm::getKillRegState(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineFrameInfo::getObjectAlign(), llvm::MachineFrameInfo::getObjectSize(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), getRegisterInfo(), llvm::RegState::Implicit, llvm::AArch64Subtarget::isSVEorStreamingSVEAvailable(), llvm::MCRegister::isValid(), llvm::Register::isVirtual(), MBB, MBBI, MI, llvm::MachineMemOperand::MOStore, llvm::MCRegister::NoRegister, llvm::Offset, llvm::TargetStackID::ScalableVector, llvm::MachineFrameInfo::setStackID(), storeRegPairToStackSlot(), and TRI.

Referenced by foldMemoryOperandImpl().

◆ suppressLdStPair()

void AArch64InstrInfo::suppressLdStPair ( MachineInstr &  MI)
static

Hint that pairing the given load or store is unprofitable.

Set a flag on the first MachineMemOperand to suppress pairing.

Definition at line 2278 of file AArch64InstrInfo.cpp.

References MI, and llvm::MOSuppressPair.

◆ useMachineCombiner()

bool AArch64InstrInfo::useMachineCombiner ( ) const
override

AArch64 supports MachineCombiner.

Definition at line 6259 of file AArch64InstrInfo.cpp.

The documentation for this class was generated from the following files:
Generated on Mon Jun 23 2025 10:01:45 for LLVM by doxygen 1.9.6