llvm::AArch64InstrInfo Class Reference

#include "Target/AArch64/AArch64InstrInfo.h"

Inheritance diagram for llvm::AArch64InstrInfo:

Collaboration diagram for llvm::AArch64InstrInfo:

Public Member Functions
	AArch64InstrInfo (const AArch64Subtarget &STI)
const AArch64RegisterInfo &	getRegisterInfo () const
	getRegisterInfo - TargetInstrInfo is a superset of MRegister info. More...
unsigned	getInstSizeInBytes (const MachineInstr &MI) const override
	GetInstSize - Return the number of bytes of code the specified instruction may be. More...
bool	isAsCheapAsAMove (const MachineInstr &MI) const override
bool	isCoalescableExtInstr (const MachineInstr &MI, Register &SrcReg, Register &DstReg, unsigned &SubIdx) const override
bool	areMemAccessesTriviallyDisjoint (const MachineInstr &MIa, const MachineInstr &MIb) const override
unsigned	isLoadFromStackSlot (const MachineInstr &MI, int &FrameIndex) const override
unsigned	isStoreToStackSlot (const MachineInstr &MI, int &FrameIndex) const override
bool	isCandidateToMergeOrPair (const MachineInstr &MI) const
	Return true if this is a load/store that can be potentially paired/merged. More...
Optional< ExtAddrMode >	getAddrModeFromMemoryOp (const MachineInstr &MemI, const TargetRegisterInfo *TRI) const override
bool	getMemOperandsWithOffsetWidth (const MachineInstr &MI, SmallVectorImpl< const MachineOperand * > &BaseOps, int64_t &Offset, bool &OffsetIsScalable, unsigned &Width, const TargetRegisterInfo *TRI) const override
bool	getMemOperandWithOffsetWidth (const MachineInstr &MI, const MachineOperand *&BaseOp, int64_t &Offset, bool &OffsetIsScalable, unsigned &Width, const TargetRegisterInfo *TRI) const
	If OffsetIsScalable is set to 'true', the offset is scaled by vscale. More...
MachineOperand &	getMemOpBaseRegImmOfsOffsetOperand (MachineInstr &LdSt) const
	Return the immediate offset of the base register in a load/store LdSt. More...
bool	shouldClusterMemOps (ArrayRef< const MachineOperand * > BaseOps1, ArrayRef< const MachineOperand * > BaseOps2, unsigned NumLoads, unsigned NumBytes) const override
	Detect opportunities for ldp/stp formation. More...
void	copyPhysRegTuple (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc, unsigned Opcode, llvm::ArrayRef< unsigned > Indices) const
void	copyGPRRegTuple (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc, unsigned Opcode, unsigned ZeroReg, llvm::ArrayRef< unsigned > Indices) const
void	copyPhysReg (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
void	storeRegToStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
void	loadRegFromStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
bool	isSubregFoldable () const override
MachineInstr *	foldMemoryOperandImpl (MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const override
bool	isBranchOffsetInRange (unsigned BranchOpc, int64_t BrOffset) const override
MachineBasicBlock *	getBranchDestBlock (const MachineInstr &MI) const override
bool	analyzeBranch (MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override
bool	analyzeBranchPredicate (MachineBasicBlock &MBB, MachineBranchPredicate &MBP, bool AllowModify) const override
unsigned	removeBranch (MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
unsigned	insertBranch (MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
bool	reverseBranchCondition (SmallVectorImpl< MachineOperand > &Cond) const override
bool	canInsertSelect (const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, Register, Register, Register, int &, int &, int &) const override
void	insertSelect (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, Register DstReg, ArrayRef< MachineOperand > Cond, Register TrueReg, Register FalseReg) const override
MCInst	getNop () const override
bool	isSchedulingBoundary (const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override
bool	analyzeCompare (const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int64_t &CmpMask, int64_t &CmpValue) const override
	analyzeCompare - For a comparison instruction, return the source registers in SrcReg and SrcReg2, and the value it compares against in CmpValue. More...
bool	optimizeCompareInstr (MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int64_t CmpMask, int64_t CmpValue, const MachineRegisterInfo *MRI) const override
	optimizeCompareInstr - Convert the instruction supplying the argument to the comparison into one that sets the zero bit in the flags register. More...
bool	optimizeCondBranch (MachineInstr &MI) const override
	Replace csincr-branch sequence by simple conditional branch. More...
bool	isThroughputPattern (MachineCombinerPattern Pattern) const override
	Return true when a code sequence can improve throughput. More...
bool	getMachineCombinerPatterns (MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &Patterns, bool DoRegPressureReduce) const override
	Return true when there is potentially a faster code sequence for an instruction chain ending in Root. More...
bool	isAssociativeAndCommutative (const MachineInstr &Inst) const override
	Return true when Inst is associative and commutative so that it can be reassociated. More...
void	genAlternativeCodeSequence (MachineInstr &Root, MachineCombinerPattern Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, DenseMap< unsigned, unsigned > &InstrIdxForVirtReg) const override
	When getMachineCombinerPatterns() finds patterns, this function generates the instructions that could replace the original code sequence. More...
bool	useMachineCombiner () const override
	AArch64 supports MachineCombiner. More...
bool	expandPostRAPseudo (MachineInstr &MI) const override
std::pair< unsigned, unsigned >	decomposeMachineOperandsTargetFlags (unsigned TF) const override
ArrayRef< std::pair< unsigned, const char * > >	getSerializableDirectMachineOperandTargetFlags () const override
ArrayRef< std::pair< unsigned, const char * > >	getSerializableBitmaskMachineOperandTargetFlags () const override
ArrayRef< std::pair< MachineMemOperand::Flags, const char * > >	getSerializableMachineMemOperandTargetFlags () const override
bool	isFunctionSafeToOutlineFrom (MachineFunction &MF, bool OutlineFromLinkOnceODRs) const override
outliner::OutlinedFunction	getOutliningCandidateInfo (std::vector< outliner::Candidate > &RepeatedSequenceLocs) const override
outliner::InstrType	getOutliningType (MachineBasicBlock::iterator &MIT, unsigned Flags) const override
bool	isMBBSafeToOutlineFrom (MachineBasicBlock &MBB, unsigned &Flags) const override
void	buildOutlinedFrame (MachineBasicBlock &MBB, MachineFunction &MF, const outliner::OutlinedFunction &OF) const override
MachineBasicBlock::iterator	insertOutlinedCall (Module &M, MachineBasicBlock &MBB, MachineBasicBlock::iterator &It, MachineFunction &MF, outliner::Candidate &C) const override
bool	shouldOutlineFromFunctionByDefault (MachineFunction &MF) const override
uint64_t	getElementSizeForOpcode (unsigned Opc) const
	Returns the vector element size (B, H, S or D) of an SVE opcode. More...
bool	isPTestLikeOpcode (unsigned Opc) const
	Returns true if the opcode is for an SVE instruction that sets the condition codes as if it's results had been fed to a PTEST instruction along with the same general predicate. More...
bool	isWhileOpcode (unsigned Opc) const
	Returns true if the opcode is for an SVE WHILE## instruction. More...
Optional< RegImmPair >	isAddImmediate (const MachineInstr &MI, Register Reg) const override
Optional< ParamLoadedValue >	describeLoadedValue (const MachineInstr &MI, Register Reg) const override
unsigned int	getTailDuplicateSize (CodeGenOpt::Level OptLevel) const override
bool	isExtendLikelyToBeFolded (MachineInstr &ExtMI, MachineRegisterInfo &MRI) const override
virtual MachineInstr *	foldMemoryOperandImpl (MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const
	Target-dependent implementation for foldMemoryOperand. More...
virtual MachineInstr *	foldMemoryOperandImpl (MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI, LiveIntervals *LIS=nullptr) const
	Target-dependent implementation for foldMemoryOperand. More...

Static Public Member Functions
static bool	isGPRZero (const MachineInstr &MI)
	Does this instruction set its full destination register to zero? More...
static bool	isGPRCopy (const MachineInstr &MI)
	Does this instruction rename a GPR without modifying bits? More...
static bool	isFPRCopy (const MachineInstr &MI)
	Does this instruction rename an FPR without modifying bits? More...
static bool	isLdStPairSuppressed (const MachineInstr &MI)
	Return true if pairing the given load or store is hinted to be unprofitable. More...
static bool	isStridedAccess (const MachineInstr &MI)
	Return true if the given load or store is a strided memory access. More...
static bool	hasUnscaledLdStOffset (unsigned Opc)
	Return true if it has an unscaled load/store offset. More...
static bool	hasUnscaledLdStOffset (MachineInstr &MI)
static Optional< unsigned >	getUnscaledLdSt (unsigned Opc)
	Returns the unscaled load/store for the scaled load/store opcode, if there is a corresponding unscaled variant available. More...
static int	getMemScale (unsigned Opc)
	Scaling factor for (scaled or unscaled) load or store. More...
static int	getMemScale (const MachineInstr &MI)
static bool	isPreLd (const MachineInstr &MI)
	Returns whether the instruction is a pre-indexed load. More...
static bool	isPreSt (const MachineInstr &MI)
	Returns whether the instruction is a pre-indexed store. More...
static bool	isPreLdSt (const MachineInstr &MI)
	Returns whether the instruction is a pre-indexed load/store. More...
static bool	isFpOrNEON (const MachineInstr &MI)
	Returns whether the instruction is FP or NEON. More...
static bool	isQForm (const MachineInstr &MI)
	Returns whether the instruction is in Q form (128 bit operands) More...
static unsigned	getLoadStoreImmIdx (unsigned Opc)
	Returns the index for the immediate for a given instruction. More...
static bool	isPairableLdStInst (const MachineInstr &MI)
	Return true if pairing the given load or store may be paired with another. More...
static unsigned	convertToFlagSettingOpc (unsigned Opc, bool &Is64Bit)
	Return the opcode that set flags when possible. More...
static void	suppressLdStPair (MachineInstr &MI)
	Hint that pairing the given load or store is unprofitable. More...
static bool	getMemOpInfo (unsigned Opcode, TypeSize &Scale, unsigned &Width, int64_t &MinOffset, int64_t &MaxOffset)
	Returns true if opcode Opc is a memory operation. More...
static bool	isFalkorShiftExtFast (const MachineInstr &MI)
	Returns true if the instruction has a shift by immediate that can be executed in one cycle less. More...
static bool	isSEHInstruction (const MachineInstr &MI)
	Return true if the instructions is a SEH instruciton used for unwinding on Windows. More...
static void	decomposeStackOffsetForFrameOffsets (const StackOffset &Offset, int64_t &NumBytes, int64_t &NumPredicateVectors, int64_t &NumDataVectors)
	Returns the offset in parts to which this frame offset can be decomposed for the purpose of describing a frame offset. More...
static void	decomposeStackOffsetForDwarfOffsets (const StackOffset &Offset, int64_t &ByteSized, int64_t &VGSized)

Protected Member Functions
Optional< DestSourcePair >	isCopyInstrImpl (const MachineInstr &MI) const override
	If the specific machine instruction is an instruction that moves/copies value from one register to another register return destination and source registers as machine operands. More...

Detailed Description

Definition at line 37 of file AArch64InstrInfo.h.

Constructor & Destructor Documentation

AArch64InstrInfo()

AArch64InstrInfo::AArch64InstrInfo ( const AArch64Subtarget &  STI )

explicit

Definition at line 71 of file AArch64InstrInfo.cpp.

Member Function Documentation

analyzeBranch()

bool AArch64InstrInfo::analyzeBranch ( MachineBasicBlock &  MBB, MachineBasicBlock *&  TBB, MachineBasicBlock *&  FBB, SmallVectorImpl< MachineOperand > &  Cond, bool  AllowModify = false  ) const

override

Definition at line 232 of file AArch64InstrInfo.cpp.

References assert(), llvm::MachineBasicBlock::begin(), Cond, llvm::MachineBasicBlock::end(), llvm::MachineInstr::eraseFromParent(), getBranchDestBlock(), llvm::MachineBasicBlock::getLastNonDebugInstr(), llvm::MachineOperand::getMBB(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), I, llvm::isCondBranchOpcode(), llvm::isIndirectBranchOpcode(), llvm::MachineBasicBlock::isLayoutSuccessor(), llvm::isUncondBranchOpcode(), MBB, and parseCondBranch().

analyzeBranchPredicate()

bool AArch64InstrInfo::analyzeBranchPredicate ( MachineBasicBlock &  MBB, MachineBranchPredicate &  MBP, bool  AllowModify  ) const

override

Definition at line 350 of file AArch64InstrInfo.cpp.

References assert(), llvm::MachineOperand::CreateImm(), llvm::MachineBasicBlock::end(), llvm::MachineBasicBlock::getLastNonDebugInstr(), llvm::MachineOperand::getMBB(), llvm::ilist_node_with_parent< NodeTy, ParentTy, Options >::getNextNode(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), I, llvm::isCondBranchOpcode(), MBB, llvm::PPC::PRED_EQ, and llvm::PPC::PRED_NE.

analyzeCompare()

bool AArch64InstrInfo::analyzeCompare ( const MachineInstr &  MI, Register &  SrcReg, Register &  SrcReg2, int64_t &  CmpMask, int64_t &  CmpValue  ) const

override

analyzeCompare - For a comparison instruction, return the source registers in SrcReg and SrcReg2, and the value it compares against in CmpValue.

Return true if the comparison instruction can be analyzed.

Definition at line 1107 of file AArch64InstrInfo.cpp.

References assert(), llvm::AArch64_AM::decodeLogicalImmediate(), and MI.

areMemAccessesTriviallyDisjoint()

bool AArch64InstrInfo::areMemAccessesTriviallyDisjoint ( const MachineInstr &  MIa, const MachineInstr &  MIb  ) const

override

Definition at line 1043 of file AArch64InstrInfo.cpp.

References assert(), getMemOperandWithOffsetWidth(), getRegisterInfo(), llvm::MachineInstr::hasOrderedMemoryRef(), llvm::MachineInstr::hasUnmodeledSideEffects(), llvm::MachineOperand::isIdenticalTo(), llvm::MachineInstr::mayLoadOrStore(), and TRI.

buildOutlinedFrame()

void AArch64InstrInfo::buildOutlinedFrame ( MachineBasicBlock &  MBB, MachineFunction &  MF, const outliner::OutlinedFunction &  OF  ) const

override

Definition at line 7622 of file AArch64InstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addCFIIndex(), llvm::MachineFunction::addFrameInst(), llvm::MachineInstrBuilder::addImm(), llvm::MachineBasicBlock::addLiveIn(), llvm::MachineInstrBuilder::addReg(), llvm::any_of(), assert(), llvm::MachineBasicBlock::begin(), llvm::ARCISD::BL, llvm::BuildMI(), llvm::outliner::OutlinedFunction::Candidates, llvm::MCCFIInstruction::cfiDefCfaOffset(), llvm::MCCFIInstruction::createOffset(), llvm::RegState::Define, llvm::MachineBasicBlock::end(), llvm::outliner::OutlinedFunction::FrameConstructionID, llvm::MachineInstr::FrameSetup, get, llvm::MachineFunction::getInfo(), llvm::TargetSubtargetInfo::getRegisterInfo(), llvm::MachineFunction::getSubtarget(), llvm::MachineBasicBlock::insert(), llvm::MachineBasicBlock::instr_end(), llvm::MachineBasicBlock::instrs(), llvm::MachineBasicBlock::isLiveIn(), MachineOutlinerDefault, MachineOutlinerTailCall, MachineOutlinerThunk, MBB, MI, MRI, llvm::AArch64FunctionInfo::needsDwarfUnwindInfo(), llvm::ARCISD::RET, ret(), llvm::MachineInstrBuilder::setMIFlags(), llvm::AArch64FunctionInfo::setOutliningStyle(), llvm::AArch64FunctionInfo::shouldSignReturnAddress(), and signOutlinedFunction().

canInsertSelect()

bool AArch64InstrInfo::canInsertSelect ( const MachineBasicBlock &  MBB, ArrayRef< MachineOperand >  Cond, Register  DstReg, Register  TrueReg, Register  FalseReg, int &  CondCycles, int &  TrueCycles, int &  FalseCycles  ) const

override

Definition at line 601 of file AArch64InstrInfo.cpp.

References canFoldIntoCSel(), Cond, llvm::MachineBasicBlock::getParent(), llvm::MachineRegisterInfo::getRegClass(), llvm::MachineFunction::getRegInfo(), MBB, and MRI.

convertToFlagSettingOpc()

unsigned AArch64InstrInfo::convertToFlagSettingOpc ( unsigned  Opc, bool &  Is64Bit  )

static

Return the opcode that set flags when possible.

The caller is responsible for ensuring the opc has a flag setting equivalent.

Definition at line 2385 of file AArch64InstrInfo.cpp.

References llvm_unreachable.

copyGPRRegTuple()

void AArch64InstrInfo::copyGPRRegTuple	(	MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	I,
		DebugLoc	DL,
		unsigned	DestReg,
		unsigned	SrcReg,
		bool	KillSrc,
		unsigned	Opcode,
		unsigned	ZeroReg,
		llvm::ArrayRef< unsigned >	Indices
	)		const

Definition at line 3377 of file AArch64InstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), AddSubReg(), assert(), llvm::BuildMI(), llvm::RegState::Define, DL, get, llvm::MCRegisterInfo::getEncodingValue(), llvm::getKillRegState(), getRegisterInfo(), I, MBB, llvm::ArrayRef< T >::size(), SubReg, and TRI.

Referenced by copyPhysReg().

copyPhysReg()

void AArch64InstrInfo::copyPhysReg ( MachineBasicBlock &  MBB, MachineBasicBlock::iterator  I, const DebugLoc &  DL, MCRegister  DestReg, MCRegister  SrcReg, bool  KillSrc  ) const

override

Definition at line 3402 of file AArch64InstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), contains(), copyGPRRegTuple(), copyPhysRegTuple(), llvm::RegState::Define, DL, llvm::errs(), get, llvm::getKillRegState(), llvm::TargetRegisterInfo::getMatchingSuperReg(), llvm::TargetRegisterInfo::getRegAsmName(), getRegisterInfo(), llvm::AArch64_AM::getShifterImm(), I, llvm::RegState::Implicit, llvm_unreachable, llvm::AArch64_AM::LSL, MBB, llvm::AArch64ISD::MRS, TRI, and llvm::RegState::Undef.

copyPhysRegTuple()

void AArch64InstrInfo::copyPhysRegTuple	(	MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	I,
		const DebugLoc &	DL,
		MCRegister	DestReg,
		MCRegister	SrcReg,
		bool	KillSrc,
		unsigned	Opcode,
		llvm::ArrayRef< unsigned >	Indices
	)		const

Definition at line 3350 of file AArch64InstrInfo.cpp.

References assert(), llvm::MCRegisterInfo::getEncodingValue(), getRegisterInfo(), llvm::ArrayRef< T >::size(), SubReg, and TRI.

Referenced by copyPhysReg().

decomposeMachineOperandsTargetFlags()

std::pair< unsigned, unsigned > AArch64InstrInfo::decomposeMachineOperandsTargetFlags ( unsigned  TF ) const

override

Definition at line 6653 of file AArch64InstrInfo.cpp.

References llvm::BitmaskEnumDetail::Mask(), and llvm::AArch64II::MO_FRAGMENT.

decomposeStackOffsetForDwarfOffsets()

void AArch64InstrInfo::decomposeStackOffsetForDwarfOffsets ( const StackOffset &  Offset, int64_t &  ByteSized, int64_t &  VGSized  )

static

Definition at line 4041 of file AArch64InstrInfo.cpp.

References assert().

Referenced by llvm::createCFAOffset(), and createDefCFAExpression().

decomposeStackOffsetForFrameOffsets()

void AArch64InstrInfo::decomposeStackOffsetForFrameOffsets ( const StackOffset &  Offset, int64_t &  NumBytes, int64_t &  NumPredicateVectors, int64_t &  NumDataVectors  )

static

Returns the offset in parts to which this frame offset can be decomposed for the purpose of describing a frame offset.

For non-scalable offsets this is simply its byte size.

Definition at line 4060 of file AArch64InstrInfo.cpp.

References assert().

Referenced by llvm::emitFrameOffset().

describeLoadedValue()

Optional< ParamLoadedValue > AArch64InstrInfo::describeLoadedValue ( const MachineInstr &  MI, Register  Reg  ) const

override

Definition at line 7936 of file AArch64InstrInfo.cpp.

References llvm::MachineOperand::CreateImm(), llvm::TargetInstrInfo::describeLoadedValue(), describeORRLoadedValue(), llvm::TargetSubtargetInfo::getRegisterInfo(), llvm::MachineFunction::getSubtarget(), llvm::MCRegisterInfo::isSuperRegisterEq(), MI, llvm::None, Shift, and TRI.

expandPostRAPseudo()

bool AArch64InstrInfo::expandPostRAPseudo ( MachineInstr &  MI ) const

override

Definition at line 1835 of file AArch64InstrInfo.cpp.

References llvm::MachineInstrBuilder::addDef(), llvm::MachineInstrBuilder::addGlobalAddress(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstrBuilder::addReg(), llvm::MachineInstrBuilder::addUse(), llvm::AArch64ISD::ADR, llvm::AArch64ISD::ADRP, assert(), llvm::MachineBasicBlock::begin(), llvm::BuildMI(), llvm::ISD::CATCHRET, llvm::AArch64Subtarget::ClassifyGlobalReference(), llvm::RegState::Dead, llvm::RegState::Define, DL, llvm::AArch64SysReg::SysReg::Encoding, llvm::MachineBasicBlock::erase(), llvm::MachineInstr::FrameDestroy, get, llvm::MachineFunction::getFunction(), llvm::TargetSubtargetInfo::getInstrInfo(), llvm::MachineBasicBlock::getParent(), llvm::GlobalValue::getParent(), llvm::AArch64Subtarget::getRegisterInfo(), llvm::TargetRegisterInfo::getSubReg(), llvm::MachineFunction::getSubtarget(), llvm::MachineFunction::getTarget(), llvm::RegState::Implicit, llvm::AArch64Subtarget::isTargetILP32(), llvm::RegState::Kill, llvm::CodeModel::Large, llvm::AArch64ISD::LOADgot, llvm::AArch64SysReg::lookupSysRegByName(), M, MBB, MBBI, MI, llvm::AArch64II::MO_G0, llvm::AArch64II::MO_G1, llvm::AArch64II::MO_G2, llvm::AArch64II::MO_G3, llvm::AArch64II::MO_GOT, llvm::AArch64II::MO_NC, llvm::AArch64II::MO_PAGE, llvm::AArch64II::MO_PAGEOFF, llvm::AArch64ISD::MRS, llvm::RegState::Renamable, llvm::report_fatal_error(), TII, llvm::CodeModel::Tiny, TM, and TRI.

foldMemoryOperandImpl() [1/3]

virtual MachineInstr* llvm::TargetInstrInfo::foldMemoryOperandImpl

inline

Target-dependent implementation for foldMemoryOperand.

Target-independent code in foldMemoryOperand will take care of adding a MachineMemOperand to the newly created instruction. The instruction and any auxiliary instructions necessary will be inserted at InsertPt.

Definition at line 1222 of file TargetInstrInfo.h.

foldMemoryOperandImpl() [2/3]

MachineInstr * AArch64InstrInfo::foldMemoryOperandImpl ( MachineFunction &  MF, MachineInstr &  MI, ArrayRef< unsigned >  Ops, MachineBasicBlock::iterator  InsertPt, int  FrameIndex, LiveIntervals *  LIS = nullptr, VirtRegMap *  VRM = nullptr  ) const

override

Definition at line 4377 of file AArch64InstrInfo.cpp.

References assert(), llvm::MachineRegisterInfo::constrainRegClass(), contains(), llvm::ISD::FrameIndex, llvm::TargetRegisterInfo::getMatchingSuperReg(), llvm::TargetRegisterInfo::getMinimalPhysRegClass(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getRegClass(), getRegClass(), llvm::MachineFunction::getRegInfo(), llvm::TargetSubtargetInfo::getRegisterInfo(), llvm::TargetRegisterInfo::getRegSizeInBits(), llvm::MachineOperand::getSubReg(), llvm::MachineFunction::getSubtarget(), llvm::MachineOperand::isKill(), llvm::Register::isPhysicalRegister(), llvm::MachineOperand::isUndef(), llvm::Register::isVirtualRegister(), loadRegFromStackSlot(), MBB, MI, MRI, llvm::MachineOperand::setIsUndef(), llvm::MachineOperand::setSubReg(), llvm::ArrayRef< T >::size(), storeRegToStackSlot(), and TRI.

foldMemoryOperandImpl() [3/3]

virtual MachineInstr* llvm::TargetInstrInfo::foldMemoryOperandImpl

inline

Target-dependent implementation for foldMemoryOperand.

Target-independent code in foldMemoryOperand will take care of adding a MachineMemOperand to the newly created instruction. The instruction and any auxiliary instructions necessary will be inserted at InsertPt.

Definition at line 1235 of file TargetInstrInfo.h.

genAlternativeCodeSequence()

void AArch64InstrInfo::genAlternativeCodeSequence ( MachineInstr &  Root, MachineCombinerPattern  Pattern, SmallVectorImpl< MachineInstr * > &  InsInstrs, SmallVectorImpl< MachineInstr * > &  DelInstrs, DenseMap< unsigned, unsigned > &  InstrIdxForVirtReg  ) const

override

When getMachineCombinerPatterns() finds patterns, this function generates the instructions that could replace the original code sequence.

When getMachineCombinerPatterns() finds potential patterns, this function generates the instructions that could replace the original code sequence.

Definition at line 5594 of file AArch64InstrInfo.cpp.

References Accumulator, llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::FMLAv1i32_indexed_OP1, llvm::FMLAv1i32_indexed_OP2, llvm::FMLAv1i64_indexed_OP1, llvm::FMLAv1i64_indexed_OP2, llvm::FMLAv2f32_OP1, llvm::FMLAv2f32_OP2, llvm::FMLAv2f64_OP1, llvm::FMLAv2f64_OP2, llvm::FMLAv2i32_indexed_OP1, llvm::FMLAv2i32_indexed_OP2, llvm::FMLAv2i64_indexed_OP1, llvm::FMLAv2i64_indexed_OP2, llvm::FMLAv4f16_OP1, llvm::FMLAv4f16_OP2, llvm::FMLAv4f32_OP1, llvm::FMLAv4f32_OP2, llvm::FMLAv4i16_indexed_OP1, llvm::FMLAv4i16_indexed_OP2, llvm::FMLAv4i32_indexed_OP1, llvm::FMLAv4i32_indexed_OP2, llvm::FMLAv8f16_OP1, llvm::FMLAv8f16_OP2, llvm::FMLAv8i16_indexed_OP1, llvm::FMLAv8i16_indexed_OP2, llvm::FMLSv1i32_indexed_OP2, llvm::FMLSv1i64_indexed_OP2, llvm::FMLSv2f32_OP1, llvm::FMLSv2f32_OP2, llvm::FMLSv2f64_OP1, llvm::FMLSv2f64_OP2, llvm::FMLSv2i32_indexed_OP1, llvm::FMLSv2i32_indexed_OP2, llvm::FMLSv2i64_indexed_OP1, llvm::FMLSv2i64_indexed_OP2, llvm::FMLSv4f16_OP1, llvm::FMLSv4f16_OP2, llvm::FMLSv4f32_OP1, llvm::FMLSv4f32_OP2, llvm::FMLSv4i16_indexed_OP1, llvm::FMLSv4i16_indexed_OP2, llvm::FMLSv4i32_indexed_OP1, llvm::FMLSv4i32_indexed_OP2, llvm::FMLSv8f16_OP1, llvm::FMLSv8f16_OP2, llvm::FMLSv8i16_indexed_OP1, llvm::FMLSv8i16_indexed_OP2, llvm::FMULADDD_OP1, llvm::FMULADDD_OP2, llvm::FMULADDH_OP1, llvm::FMULADDH_OP2, llvm::FMULADDS_OP1, llvm::FMULADDS_OP2, llvm::FMULSUBD_OP1, llvm::FMULSUBD_OP2, llvm::FMULSUBH_OP1, llvm::FMULSUBH_OP2, llvm::FMULSUBS_OP1, llvm::FMULSUBS_OP2, llvm::FMULv2i32_indexed_OP1, llvm::FMULv2i32_indexed_OP2, llvm::FMULv2i64_indexed_OP1, llvm::FMULv2i64_indexed_OP2, llvm::FMULv4i16_indexed_OP1, llvm::FMULv4i16_indexed_OP2, llvm::FMULv4i32_indexed_OP1, llvm::FMULv4i32_indexed_OP2, llvm::FMULv8i16_indexed_OP1, llvm::FMULv8i16_indexed_OP2, llvm::FNMULSUBD_OP1, llvm::FNMULSUBH_OP1, llvm::FNMULSUBS_OP1, llvm::TargetInstrInfo::genAlternativeCodeSequence(), genFusedMultiply(), genFusedMultiplyAcc(), genFusedMultiplyAccNeg(), genFusedMultiplyIdx(), genFusedMultiplyIdxNeg(), genIndexedMultiply(), genMaddR(), llvm::MachineInstr::getDebugLoc(), llvm::MachineInstr::getFlags(), llvm::MachineOperand::getImm(), llvm::TargetSubtargetInfo::getInstrInfo(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineFunction::getRegInfo(), llvm::MachineFunction::getSubtarget(), llvm::RISCVMatInt::Imm, Indexed, llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::insert(), llvm::MachineOperand::isImm(), MBB, llvm::MachineInstr::mergeFlagsWith(), MI, MRI, llvm::ISD::MUL, llvm::MULADDv16i8_OP1, llvm::MULADDv16i8_OP2, llvm::MULADDv2i32_indexed_OP1, llvm::MULADDv2i32_indexed_OP2, llvm::MULADDv2i32_OP1, llvm::MULADDv2i32_OP2, llvm::MULADDv4i16_indexed_OP1, llvm::MULADDv4i16_indexed_OP2, llvm::MULADDv4i16_OP1, llvm::MULADDv4i16_OP2, llvm::MULADDv4i32_indexed_OP1, llvm::MULADDv4i32_indexed_OP2, llvm::MULADDv4i32_OP1, llvm::MULADDv4i32_OP2, llvm::MULADDv8i16_indexed_OP1, llvm::MULADDv8i16_indexed_OP2, llvm::MULADDv8i16_OP1, llvm::MULADDv8i16_OP2, llvm::MULADDv8i8_OP1, llvm::MULADDv8i8_OP2, llvm::MULADDW_OP1, llvm::MULADDW_OP2, llvm::MULADDWI_OP1, llvm::MULADDX_OP1, llvm::MULADDX_OP2, llvm::MULADDXI_OP1, llvm::MULSUBv16i8_OP1, llvm::MULSUBv16i8_OP2, llvm::MULSUBv2i32_indexed_OP1, llvm::MULSUBv2i32_indexed_OP2, llvm::MULSUBv2i32_OP1, llvm::MULSUBv2i32_OP2, llvm::MULSUBv4i16_indexed_OP1, llvm::MULSUBv4i16_indexed_OP2, llvm::MULSUBv4i16_OP1, llvm::MULSUBv4i16_OP2, llvm::MULSUBv4i32_indexed_OP1, llvm::MULSUBv4i32_indexed_OP2, llvm::MULSUBv4i32_OP1, llvm::MULSUBv4i32_OP2, llvm::MULSUBv8i16_indexed_OP1, llvm::MULSUBv8i16_indexed_OP2, llvm::MULSUBv8i16_OP1, llvm::MULSUBv8i16_OP2, llvm::MULSUBv8i8_OP1, llvm::MULSUBv8i8_OP2, llvm::MULSUBW_OP1, llvm::MULSUBW_OP2, llvm::MULSUBWI_OP1, llvm::MULSUBX_OP1, llvm::MULSUBX_OP2, llvm::MULSUBXI_OP1, llvm::AArch64_AM::processLogicalImmediate(), llvm::SignExtend64(), and TII.

getAddrModeFromMemoryOp()

Optional< ExtAddrMode > AArch64InstrInfo::getAddrModeFromMemoryOp ( const MachineInstr &  MemI, const TargetRegisterInfo *  TRI  ) const

override

Definition at line 2560 of file AArch64InstrInfo.cpp.

References llvm::sampleprof::Base, llvm::ExtAddrMode::BaseReg, llvm::ExtAddrMode::Displacement, llvm::None, llvm::ExtAddrMode::Scale, llvm::ExtAddrMode::ScaledReg, and TRI.

getBranchDestBlock()

MachineBasicBlock * AArch64InstrInfo::getBranchDestBlock ( const MachineInstr &  MI ) const

override

Definition at line 211 of file AArch64InstrInfo.cpp.

References B, llvm_unreachable, and MI.

Referenced by analyzeBranch().

getElementSizeForOpcode()

uint64_t AArch64InstrInfo::getElementSizeForOpcode

(

unsigned

Opc

)

const

Returns the vector element size (B, H, S or D) of an SVE opcode.

Definition at line 7983 of file AArch64InstrInfo.cpp.

References llvm::AArch64::ElementSizeMask, and get.

getInstSizeInBytes()

unsigned AArch64InstrInfo::getInstSizeInBytes ( const MachineInstr &  MI ) const

override

GetInstSize - Return the number of bytes of code the specified instruction may be.

This returns the maximum number of bytes.

Definition at line 78 of file AArch64InstrInfo.cpp.

References assert(), llvm::TargetMachine::getMCAsmInfo(), llvm::StackMapOpers::getNumPatchBytes(), llvm::PatchPointOpers::getNumPatchBytes(), llvm::StatepointOpers::getNumPatchBytes(), llvm::MCInstrDesc::getOpcode(), llvm::MachineBasicBlock::getParent(), llvm::MCInstrDesc::getSize(), llvm::MachineFunction::getTarget(), llvm::ISD::INLINEASM, llvm::ISD::INLINEASM_BR, MBB, and MI.

getLoadStoreImmIdx()

unsigned AArch64InstrInfo::getLoadStoreImmIdx ( unsigned  Opc )

static

Returns the index for the immediate for a given instruction.

Definition at line 2211 of file AArch64InstrInfo.cpp.

Referenced by llvm::isAArch64FrameOffsetLegal().

getMachineCombinerPatterns()

bool AArch64InstrInfo::getMachineCombinerPatterns ( MachineInstr &  Root, SmallVectorImpl< MachineCombinerPattern > &  Patterns, bool  DoRegPressureReduce  ) const

override

Return true when there is potentially a faster code sequence for an instruction chain ending in Root.

Return true when there is potentially a faster code sequence for an instruction chain ending in Root.

All potential patterns are listed in the Patterns array.

All potential patterns are listed in the Pattern vector. Pattern should be sorted in priority order since the pattern evaluator stops checking as soon as it finds a faster sequence.

Definition at line 5332 of file AArch64InstrInfo.cpp.

References getFMAPatterns(), getFMULPatterns(), llvm::TargetInstrInfo::getMachineCombinerPatterns(), and getMaddPatterns().

getMemOpBaseRegImmOfsOffsetOperand()

MachineOperand & AArch64InstrInfo::getMemOpBaseRegImmOfsOffsetOperand

(

MachineInstr &

LdSt

)

const

Return the immediate offset of the base register in a load/store LdSt.

Definition at line 2627 of file AArch64InstrInfo.cpp.

References assert(), llvm::MachineInstr::getNumExplicitOperands(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::isImm(), and llvm::MachineInstr::mayLoadOrStore().

getMemOperandsWithOffsetWidth()

bool AArch64InstrInfo::getMemOperandsWithOffsetWidth ( const MachineInstr &  MI, SmallVectorImpl< const MachineOperand * > &  BaseOps, int64_t &  Offset, bool &  OffsetIsScalable, unsigned &  Width, const TargetRegisterInfo *  TRI  ) const

override

Definition at line 2544 of file AArch64InstrInfo.cpp.

References getMemOperandWithOffsetWidth(), llvm::MachineInstr::mayLoadOrStore(), and TRI.

getMemOperandWithOffsetWidth()

bool AArch64InstrInfo::getMemOperandWithOffsetWidth	(	const MachineInstr &	MI,
		const MachineOperand *&	BaseOp,
		int64_t &	Offset,
		bool &	OffsetIsScalable,
		unsigned &	Width,
		const TargetRegisterInfo *	TRI
	)		const

If OffsetIsScalable is set to 'true', the offset is scaled by vscale.

This is true for some SVE instructions like ldr/str that have a 'reg + imm' addressing mode where the immediate is an index to the scalable vector located at 'reg + imm * vscale x #bytes'.

Definition at line 2578 of file AArch64InstrInfo.cpp.

References assert(), llvm::MachineOperand::getImm(), llvm::TypeSize::getKnownMinSize(), getMemOpInfo(), llvm::MachineInstr::getNumExplicitOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::isFI(), llvm::MachineOperand::isImm(), llvm::MachineOperand::isReg(), llvm::LinearPolySize< LeafTy >::isScalable(), and llvm::MachineInstr::mayLoadOrStore().

Referenced by areMemAccessesTriviallyDisjoint(), and getMemOperandsWithOffsetWidth().

getMemOpInfo()

bool AArch64InstrInfo::getMemOpInfo ( unsigned  Opcode, TypeSize &  Scale, unsigned &  Width, int64_t &  MinOffset, int64_t &  MaxOffset  )

static

Returns true if opcode Opc is a memory operation.

If it is, set Scale, Width, MinOffset, and MaxOffset accordingly.

For unscaled instructions, Scale is set to 1.

Definition at line 2634 of file AArch64InstrInfo.cpp.

References llvm::TypeSize::Fixed(), llvm::TypeSize::Scalable(), and llvm::AArch64::SVEMaxBitsPerVector.

Referenced by getMemOperandWithOffsetWidth(), and llvm::isAArch64FrameOffsetLegal().

getMemScale() [1/2]

static int llvm::AArch64InstrInfo::getMemScale ( const MachineInstr &  MI )

inlinestatic

Definition at line 93 of file AArch64InstrInfo.h.

References getMemScale(), and MI.

getMemScale() [2/2]

int AArch64InstrInfo::getMemScale ( unsigned  Opc )

static

Scaling factor for (scaled or unscaled) load or store.

Definition at line 3053 of file AArch64InstrInfo.cpp.

References llvm_unreachable.

Referenced by getMemScale(), getPrePostIndexedMemOpInfo(), scaleOffset(), and shouldClusterFI().

getNop()

MCInst AArch64InstrInfo::getNop ( ) const

override

Definition at line 4691 of file AArch64InstrInfo.cpp.

References llvm::MCInstBuilder::addImm().

getOutliningCandidateInfo()

outliner::OutlinedFunction AArch64InstrInfo::getOutliningCandidateInfo ( std::vector< outliner::Candidate > &  RepeatedSequenceLocs ) const

override

Definition at line 6836 of file AArch64InstrInfo.cpp.

References b, llvm::outliner::Candidate::back(), llvm::outliner::Candidate::front(), and MI.

getOutliningType()

outliner::InstrType AArch64InstrInfo::getOutliningType ( MachineBasicBlock::iterator &  MIT, unsigned  Flags  ) const

override

Definition at line 7369 of file AArch64InstrInfo.cpp.

References llvm::AArch64ISD::ADRP, llvm::ARCISD::BL, Callee, llvm::SmallPtrSetImpl< PtrType >::count(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getInfo(), llvm::AArch64FunctionInfo::getLOHRelated(), llvm::MachineModuleInfo::getMachineFunction(), llvm::MachineFunction::getMMI(), llvm::MachineFrameInfo::getNumObjects(), llvm::MachineBasicBlock::getParent(), getRegisterInfo(), llvm::MachineFrameInfo::getStackSize(), llvm::IRSimilarity::Illegal, llvm::RISCVMatInt::Imm, llvm::IRSimilarity::Invisible, llvm::MachineFrameInfo::isCalleeSavedInfoValid(), llvm::IRSimilarity::Legal, llvm::outliner::LegalTerminator, MBB, and MI.

getRegisterInfo()

const AArch64RegisterInfo& llvm::AArch64InstrInfo::getRegisterInfo ( ) const

inline

getRegisterInfo - TargetInstrInfo is a superset of MRegister info.

As such, whenever a client has an instance of instruction info, it should always be able to get register info as well (through this method).

Definition at line 47 of file AArch64InstrInfo.h.

Referenced by areMemAccessesTriviallyDisjoint(), copyGPRRegTuple(), copyPhysReg(), copyPhysRegTuple(), getOutliningType(), llvm::AArch64Subtarget::getRegisterInfo(), isCandidateToMergeOrPair(), isMBBSafeToOutlineFrom(), loadRegFromStackSlot(), optimizeCondBranch(), and storeRegToStackSlot().

getSerializableBitmaskMachineOperandTargetFlags()

ArrayRef< std::pair< unsigned, const char * > > AArch64InstrInfo::getSerializableBitmaskMachineOperandTargetFlags ( ) const

override

Definition at line 6671 of file AArch64InstrInfo.cpp.

References llvm::makeArrayRef(), llvm::AArch64II::MO_COFFSTUB, llvm::AArch64II::MO_DLLIMPORT, llvm::AArch64II::MO_GOT, llvm::AArch64II::MO_NC, llvm::AArch64II::MO_PREL, llvm::AArch64II::MO_S, llvm::AArch64II::MO_TAGGED, and llvm::AArch64II::MO_TLS.

getSerializableDirectMachineOperandTargetFlags()

ArrayRef< std::pair< unsigned, const char * > > AArch64InstrInfo::getSerializableDirectMachineOperandTargetFlags ( ) const

override

Definition at line 6659 of file AArch64InstrInfo.cpp.

References llvm::makeArrayRef(), llvm::AArch64II::MO_G0, llvm::AArch64II::MO_G1, llvm::AArch64II::MO_G2, llvm::AArch64II::MO_G3, llvm::AArch64II::MO_HI12, llvm::AArch64II::MO_PAGE, and llvm::AArch64II::MO_PAGEOFF.

getSerializableMachineMemOperandTargetFlags()

ArrayRef< std::pair< MachineMemOperand::Flags, const char * > > AArch64InstrInfo::getSerializableMachineMemOperandTargetFlags ( ) const

override

Definition at line 6687 of file AArch64InstrInfo.cpp.

References llvm::makeArrayRef(), llvm::MOStridedAccess, and llvm::MOSuppressPair.

getTailDuplicateSize()

unsigned int AArch64InstrInfo::getTailDuplicateSize ( CodeGenOpt::Level  OptLevel ) const

override

Definition at line 7996 of file AArch64InstrInfo.cpp.

References llvm::CodeGenOpt::Aggressive.

getUnscaledLdSt()

Optional< unsigned > AArch64InstrInfo::getUnscaledLdSt ( unsigned  Opc )

static

Returns the unscaled load/store for the scaled load/store opcode, if there is a corresponding unscaled variant available.

Definition at line 2181 of file AArch64InstrInfo.cpp.

Referenced by llvm::isAArch64FrameOffsetLegal().

hasUnscaledLdStOffset() [1/2]

static bool llvm::AArch64InstrInfo::hasUnscaledLdStOffset ( MachineInstr &  MI )

inlinestatic

Definition at line 83 of file AArch64InstrInfo.h.

References hasUnscaledLdStOffset(), and MI.

hasUnscaledLdStOffset() [2/2]

bool AArch64InstrInfo::hasUnscaledLdStOffset ( unsigned  Opc )

static

Return true if it has an unscaled load/store offset.

Definition at line 2146 of file AArch64InstrInfo.cpp.

Referenced by hasUnscaledLdStOffset(), and shouldClusterMemOps().

insertBranch()

unsigned AArch64InstrInfo::insertBranch ( MachineBasicBlock &  MBB, MachineBasicBlock *  TBB, MachineBasicBlock *  FBB, ArrayRef< MachineOperand >  Cond, const DebugLoc &  DL, int *  BytesAdded = nullptr  ) const

override

Definition at line 493 of file AArch64InstrInfo.cpp.

References llvm::MachineInstrBuilder::addMBB(), assert(), B, llvm::BuildMI(), Cond, DL, get, and MBB.

insertOutlinedCall()

MachineBasicBlock::iterator AArch64InstrInfo::insertOutlinedCall ( Module &  M, MachineBasicBlock &  MBB, MachineBasicBlock::iterator &  It, MachineFunction &  MF, outliner::Candidate &  C  ) const

override

Definition at line 7760 of file AArch64InstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineBasicBlock::addLiveIn(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::ARCISD::BL, llvm::BuildMI(), llvm::RegState::Define, get, llvm::MachineFunction::getName(), llvm::MachineBasicBlock::insert(), llvm::MachineBasicBlock::isLiveIn(), M, MachineOutlinerNoLRSave, MachineOutlinerRegSave, MachineOutlinerTailCall, MachineOutlinerThunk, and MBB.

insertSelect()

void AArch64InstrInfo::insertSelect ( MachineBasicBlock &  MBB, MachineBasicBlock::iterator  MI, const DebugLoc &  DL, Register  DstReg, ArrayRef< MachineOperand >  Cond, Register  TrueReg, Register  FalseReg  ) const

override

Definition at line 650 of file AArch64InstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), canFoldIntoCSel(), llvm::MachineRegisterInfo::clearKillFlags(), Cond, llvm::MachineRegisterInfo::constrainRegClass(), DL, llvm::AArch64_AM::encodeLogicalImmediate(), llvm::AArch64CC::EQ, get, llvm::AArch64CC::getInvertedCondCode(), llvm::MachineBasicBlock::getParent(), getReg(), llvm::MachineFunction::getRegInfo(), I, llvm_unreachable, MBB, MRI, and llvm::AArch64CC::NE.

isAddImmediate()

Optional< RegImmPair > AArch64InstrInfo::isAddImmediate ( const MachineInstr &  MI, Register  Reg  ) const

override

Definition at line 7861 of file AArch64InstrInfo.cpp.

References assert(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isReg(), LLVM_FALLTHROUGH, MI, llvm::None, and Shift.

isAsCheapAsAMove()

bool AArch64InstrInfo::isAsCheapAsAMove ( const MachineInstr &  MI ) const

override

Definition at line 796 of file AArch64InstrInfo.cpp.

References canBeExpandedToORR(), llvm_unreachable, and MI.

isAssociativeAndCommutative()

bool AArch64InstrInfo::isAssociativeAndCommutative ( const MachineInstr &  Inst ) const

override

Return true when Inst is associative and commutative so that it can be reassociated.

Definition at line 4852 of file AArch64InstrInfo.cpp.

References llvm::MachineInstr::getOpcode(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineFunction::getTarget(), llvm::TargetMachine::Options, and llvm::TargetOptions::UnsafeFPMath.

isBranchOffsetInRange()

bool AArch64InstrInfo::isBranchOffsetInRange ( unsigned  BranchOpc, int64_t  BrOffset  ) const

override

Returns

true if a branch from an instruction with opcode BranchOpc bytes is capable of jumping to a position BrOffset bytes away.

Definition at line 202 of file AArch64InstrInfo.cpp.

References assert(), llvm::tgtok::Bits, getBranchDisplacementBits(), and llvm::isIntN().

isCandidateToMergeOrPair()

bool AArch64InstrInfo::isCandidateToMergeOrPair

(

const MachineInstr &

MI

)

const

Return true if this is a load/store that can be potentially paired/merged.

Definition at line 2475 of file AArch64InstrInfo.cpp.

References assert(), llvm::MachineInstr::FrameDestroy, llvm::MachineInstr::FrameSetup, getRegisterInfo(), isLdStPairSuppressed(), isPreLdSt(), MI, TRI, and llvm::MCAsmInfo::usesWindowsCFI().

Referenced by shouldClusterMemOps().

isCoalescableExtInstr()

bool AArch64InstrInfo::isCoalescableExtInstr ( const MachineInstr &  MI, Register &  SrcReg, Register &  DstReg, unsigned &  SubIdx  ) const

override

Definition at line 1023 of file AArch64InstrInfo.cpp.

References MI.

isCopyInstrImpl()

Optional< DestSourcePair > AArch64InstrInfo::isCopyInstrImpl ( const MachineInstr &  MI ) const

overrideprotected

If the specific machine instruction is an instruction that moves/copies value from one register to another register return destination and source registers as machine operands.

Definition at line 7842 of file AArch64InstrInfo.cpp.

References MI, and llvm::None.

isExtendLikelyToBeFolded()

bool AArch64InstrInfo::isExtendLikelyToBeFolded ( MachineInstr &  ExtMI, MachineRegisterInfo &  MRI  ) const

override

Definition at line 7963 of file AArch64InstrInfo.cpp.

References assert(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::hasOneNonDBGUse(), MRI, and llvm::MachineRegisterInfo::use_instr_nodbg_begin().

isFalkorShiftExtFast()

bool AArch64InstrInfo::isFalkorShiftExtFast ( const MachineInstr &  MI )

static

Returns true if the instruction has a shift by immediate that can be executed in one cycle less.

Definition at line 875 of file AArch64InstrInfo.cpp.

References llvm::AArch64_AM::ASR, llvm::AArch64_AM::getArithExtendType(), llvm::AArch64_AM::getArithShiftValue(), llvm::AArch64_AM::getShiftType(), llvm::AArch64_AM::getShiftValue(), llvm::RISCVMatInt::Imm, llvm::AArch64_AM::LSL, MI, llvm::AArch64_AM::UXTB, llvm::AArch64_AM::UXTH, llvm::AArch64_AM::UXTW, and llvm::AArch64_AM::UXTX.

isFpOrNEON()

bool AArch64InstrInfo::isFpOrNEON ( const MachineInstr &  MI )

static

Returns whether the instruction is FP or NEON.

Definition at line 3177 of file AArch64InstrInfo.cpp.

References llvm::any_of(), contains(), getRegClass(), and MI.

isFPRCopy()

bool AArch64InstrInfo::isFPRCopy ( const MachineInstr &  MI )

static

Does this instruction rename an FPR without modifying bits?

Definition at line 2059 of file AArch64InstrInfo.cpp.

References assert(), and MI.

isFunctionSafeToOutlineFrom()

bool AArch64InstrInfo::isFunctionSafeToOutlineFrom ( MachineFunction &  MF, bool  OutlineFromLinkOnceODRs  ) const

override

Definition at line 7270 of file AArch64InstrInfo.cpp.

References F, llvm::MachineFunction::getFunction(), llvm::MachineFunction::getInfo(), llvm::TargetMachine::getMCAsmInfo(), llvm::MachineFunction::getTarget(), llvm::Optional< T >::getValueOr(), llvm::AArch64FunctionInfo::hasRedZone(), and llvm::MCAsmInfo::usesWindowsCFI().

isGPRCopy()

bool AArch64InstrInfo::isGPRCopy ( const MachineInstr &  MI )

static

Does this instruction rename a GPR without modifying bits?

Definition at line 2029 of file AArch64InstrInfo.cpp.

References assert(), contains(), and MI.

isGPRZero()

bool AArch64InstrInfo::isGPRZero ( const MachineInstr &  MI )

static

Does this instruction set its full destination register to zero?

Definition at line 2005 of file AArch64InstrInfo.cpp.

References assert(), and MI.

isLdStPairSuppressed()

bool AArch64InstrInfo::isLdStPairSuppressed ( const MachineInstr &  MI )

static

Return true if pairing the given load or store is hinted to be unprofitable.

Check all MachineMemOperands for a hint to suppress pairing.

Definition at line 2126 of file AArch64InstrInfo.cpp.

References llvm::any_of(), and MI.

Referenced by isCandidateToMergeOrPair().

isLoadFromStackSlot()

unsigned AArch64InstrInfo::isLoadFromStackSlot ( const MachineInstr &  MI, int &  FrameIndex  ) const

override

Definition at line 2078 of file AArch64InstrInfo.cpp.

References llvm::ISD::FrameIndex, and MI.

isMBBSafeToOutlineFrom()

bool AArch64InstrInfo::isMBBSafeToOutlineFrom ( MachineBasicBlock &  MBB, unsigned &  Flags  ) const

override

Definition at line 7300 of file AArch64InstrInfo.cpp.

References llvm::LiveRegUnits::addLiveOuts(), llvm::any_of(), assert(), llvm::LiveRegUnits::available(), llvm::for_each(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), getRegisterInfo(), llvm::TargetSubtargetInfo::getRegisterInfo(), llvm::MachineFunction::getSubtarget(), HasCalls, llvm::TargetInstrInfo::isMBBSafeToOutlineFrom(), llvm::AArch64RegisterInfo::isReservedReg(), LRUnavailableSomewhere, MBB, MI, llvm::MachineBasicBlock::rbegin(), llvm::MachineBasicBlock::rend(), llvm::MachineRegisterInfo::tracksLiveness(), and UnsafeRegsDead.

isPairableLdStInst()

bool AArch64InstrInfo::isPairableLdStInst ( const MachineInstr &  MI )

static

Return true if pairing the given load or store may be paired with another.

Definition at line 2343 of file AArch64InstrInfo.cpp.

References MI.

Referenced by shouldClusterMemOps().

isPreLd()

bool AArch64InstrInfo::isPreLd ( const MachineInstr &  MI )

static

Returns whether the instruction is a pre-indexed load.

Definition at line 3125 of file AArch64InstrInfo.cpp.

References MI.

Referenced by isPreLdSt().

isPreLdSt()

bool AArch64InstrInfo::isPreLdSt ( const MachineInstr &  MI )

static

Returns whether the instruction is a pre-indexed load/store.

Definition at line 3151 of file AArch64InstrInfo.cpp.

References isPreLd(), isPreSt(), and MI.

Referenced by areCandidatesToMergeOrPair(), getLdStBaseOp(), getLdStOffsetOp(), getLdStRegOp(), and isCandidateToMergeOrPair().

isPreSt()

bool AArch64InstrInfo::isPreSt ( const MachineInstr &  MI )

static

Returns whether the instruction is a pre-indexed store.

Definition at line 3138 of file AArch64InstrInfo.cpp.

References MI.

Referenced by isPreLdSt().

isPTestLikeOpcode()

bool AArch64InstrInfo::isPTestLikeOpcode

(

unsigned

Opc

)

const

Returns true if the opcode is for an SVE instruction that sets the condition codes as if it's results had been fed to a PTEST instruction along with the same general predicate.

Definition at line 7987 of file AArch64InstrInfo.cpp.

References get, and llvm::AArch64::InstrFlagIsPTestLike.

isQForm()

bool AArch64InstrInfo::isQForm ( const MachineInstr &  MI )

static

Returns whether the instruction is in Q form (128 bit operands)

Definition at line 3163 of file AArch64InstrInfo.cpp.

References llvm::any_of(), contains(), getRegClass(), and MI.

isSchedulingBoundary()

bool AArch64InstrInfo::isSchedulingBoundary ( const MachineInstr &  MI, const MachineBasicBlock *  MBB, const MachineFunction &  MF  ) const

override

Definition at line 1081 of file AArch64InstrInfo.cpp.

References llvm::MachineBasicBlock::end(), llvm::TargetInstrInfo::isSchedulingBoundary(), isSEHInstruction(), MBB, and MI.

isSEHInstruction()

bool AArch64InstrInfo::isSEHInstruction ( const MachineInstr &  MI )

static

Return true if the instructions is a SEH instruciton used for unwinding on Windows.

Definition at line 997 of file AArch64InstrInfo.cpp.

References MI.

Referenced by convertCalleeSaveRestoreToSPPrePostIncDec(), llvm::AArch64FrameLowering::emitEpilogue(), fixupCalleeSaveRestoreStackOffset(), and isSchedulingBoundary().

isStoreToStackSlot()

unsigned AArch64InstrInfo::isStoreToStackSlot ( const MachineInstr &  MI, int &  FrameIndex  ) const

override

Definition at line 2101 of file AArch64InstrInfo.cpp.

References llvm::ISD::FrameIndex, and MI.

isStridedAccess()

bool AArch64InstrInfo::isStridedAccess ( const MachineInstr &  MI )

static

Return true if the given load or store is a strided memory access.

Check all MachineMemOperands for a hint that the load/store is strided.

Definition at line 2140 of file AArch64InstrInfo.cpp.

References llvm::any_of(), and MI.

isSubregFoldable()

bool llvm::AArch64InstrInfo::isSubregFoldable ( ) const

inlineoverride

Definition at line 186 of file AArch64InstrInfo.h.

isThroughputPattern()

bool AArch64InstrInfo::isThroughputPattern ( MachineCombinerPattern  Pattern ) const

override

Return true when a code sequence can improve throughput.

It should be called only for instructions in loops.

Parameters

Pattern

- combiner pattern

Definition at line 5213 of file AArch64InstrInfo.cpp.

References llvm::FMLAv1i32_indexed_OP1, llvm::FMLAv1i32_indexed_OP2, llvm::FMLAv1i64_indexed_OP1, llvm::FMLAv1i64_indexed_OP2, llvm::FMLAv2f32_OP1, llvm::FMLAv2f32_OP2, llvm::FMLAv2f64_OP1, llvm::FMLAv2f64_OP2, llvm::FMLAv2i32_indexed_OP1, llvm::FMLAv2i32_indexed_OP2, llvm::FMLAv2i64_indexed_OP1, llvm::FMLAv2i64_indexed_OP2, llvm::FMLAv4f16_OP1, llvm::FMLAv4f16_OP2, llvm::FMLAv4f32_OP1, llvm::FMLAv4f32_OP2, llvm::FMLAv4i16_indexed_OP1, llvm::FMLAv4i16_indexed_OP2, llvm::FMLAv4i32_indexed_OP1, llvm::FMLAv4i32_indexed_OP2, llvm::FMLAv8f16_OP1, llvm::FMLAv8f16_OP2, llvm::FMLAv8i16_indexed_OP1, llvm::FMLAv8i16_indexed_OP2, llvm::FMLSv1i32_indexed_OP2, llvm::FMLSv1i64_indexed_OP2, llvm::FMLSv2f32_OP2, llvm::FMLSv2f64_OP2, llvm::FMLSv2i32_indexed_OP2, llvm::FMLSv2i64_indexed_OP2, llvm::FMLSv4f16_OP1, llvm::FMLSv4f16_OP2, llvm::FMLSv4f32_OP2, llvm::FMLSv4i16_indexed_OP1, llvm::FMLSv4i16_indexed_OP2, llvm::FMLSv4i32_indexed_OP2, llvm::FMLSv8f16_OP1, llvm::FMLSv8f16_OP2, llvm::FMLSv8i16_indexed_OP1, llvm::FMLSv8i16_indexed_OP2, llvm::FMULADDD_OP1, llvm::FMULADDD_OP2, llvm::FMULADDH_OP1, llvm::FMULADDH_OP2, llvm::FMULADDS_OP1, llvm::FMULADDS_OP2, llvm::FMULSUBD_OP1, llvm::FMULSUBD_OP2, llvm::FMULSUBH_OP1, llvm::FMULSUBH_OP2, llvm::FMULSUBS_OP1, llvm::FMULSUBS_OP2, llvm::FMULv2i32_indexed_OP1, llvm::FMULv2i32_indexed_OP2, llvm::FMULv2i64_indexed_OP1, llvm::FMULv2i64_indexed_OP2, llvm::FMULv4i16_indexed_OP1, llvm::FMULv4i16_indexed_OP2, llvm::FMULv4i32_indexed_OP1, llvm::FMULv4i32_indexed_OP2, llvm::FMULv8i16_indexed_OP1, llvm::FMULv8i16_indexed_OP2, llvm::FNMULSUBD_OP1, llvm::FNMULSUBH_OP1, llvm::FNMULSUBS_OP1, llvm::MULADDv16i8_OP1, llvm::MULADDv16i8_OP2, llvm::MULADDv2i32_indexed_OP1, llvm::MULADDv2i32_indexed_OP2, llvm::MULADDv2i32_OP1, llvm::MULADDv2i32_OP2, llvm::MULADDv4i16_indexed_OP1, llvm::MULADDv4i16_indexed_OP2, llvm::MULADDv4i16_OP1, llvm::MULADDv4i16_OP2, llvm::MULADDv4i32_indexed_OP1, llvm::MULADDv4i32_indexed_OP2, llvm::MULADDv4i32_OP1, llvm::MULADDv4i32_OP2, llvm::MULADDv8i16_indexed_OP1, llvm::MULADDv8i16_indexed_OP2, llvm::MULADDv8i16_OP1, llvm::MULADDv8i16_OP2, llvm::MULADDv8i8_OP1, llvm::MULADDv8i8_OP2, llvm::MULSUBv16i8_OP1, llvm::MULSUBv16i8_OP2, llvm::MULSUBv2i32_indexed_OP1, llvm::MULSUBv2i32_indexed_OP2, llvm::MULSUBv2i32_OP1, llvm::MULSUBv2i32_OP2, llvm::MULSUBv4i16_indexed_OP1, llvm::MULSUBv4i16_indexed_OP2, llvm::MULSUBv4i16_OP1, llvm::MULSUBv4i16_OP2, llvm::MULSUBv4i32_indexed_OP1, llvm::MULSUBv4i32_indexed_OP2, llvm::MULSUBv4i32_OP1, llvm::MULSUBv4i32_OP2, llvm::MULSUBv8i16_indexed_OP1, llvm::MULSUBv8i16_indexed_OP2, llvm::MULSUBv8i16_OP1, llvm::MULSUBv8i16_OP2, llvm::MULSUBv8i8_OP1, and llvm::MULSUBv8i8_OP2.

isWhileOpcode()

bool AArch64InstrInfo::isWhileOpcode

(

unsigned

Opc

)

const

Returns true if the opcode is for an SVE WHILE## instruction.

Definition at line 7991 of file AArch64InstrInfo.cpp.

References get, and llvm::AArch64::InstrFlagIsWhile.

loadRegFromStackSlot()

void AArch64InstrInfo::loadRegFromStackSlot ( MachineBasicBlock &  MBB, MachineBasicBlock::iterator  MBBI, Register  DestReg, int  FrameIndex, const TargetRegisterClass *  RC, const TargetRegisterInfo *  TRI  ) const

override

Definition at line 3901 of file AArch64InstrInfo.cpp.

References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), llvm::MachineRegisterInfo::constrainRegClass(), llvm::TargetStackID::Default, get, llvm::getDefRegState(), llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineFrameInfo::getObjectAlign(), llvm::MachineFrameInfo::getObjectSize(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), getRegisterInfo(), llvm::TargetRegisterInfo::getSpillSize(), llvm::Register::isVirtualRegister(), loadRegPairFromStackSlot(), MBB, MBBI, MI, llvm::MachineMemOperand::MOLoad, llvm::TargetStackID::ScalableVector, llvm::MachineFrameInfo::setStackID(), and TRI.

Referenced by foldMemoryOperandImpl().

optimizeCompareInstr()

bool AArch64InstrInfo::optimizeCompareInstr ( MachineInstr &  CmpInstr, Register  SrcReg, Register  SrcReg2, int64_t  CmpMask, int64_t  CmpValue, const MachineRegisterInfo *  MRI  ) const

override

optimizeCompareInstr - Convert the instruction supplying the argument to the comparison into one that sets the zero bit in the flags register.

Try to optimize a compare instruction.

A compare instruction is an instruction which produces AArch64::NZCV. It can be truly compare instruction when there are no uses of its destination register.

The following steps are tried in order:

1. Convert CmpInstr into an unconditional version.
2. Remove CmpInstr if above there is an instruction producing a needed condition code or an instruction which can be converted into such an instruction. Only comparison with zero is supported.

Definition at line 1422 of file AArch64InstrInfo.cpp.

References assert(), convertToNonFlagSettingOpc(), llvm::MachineInstr::definesRegister(), llvm::MachineInstr::eraseFromParent(), llvm::MachineInstr::findRegisterDefOperandIdx(), get, llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), MRI, llvm::MachineInstr::removeOperand(), llvm::MachineInstr::setDesc(), UpdateOperandRegClass(), and llvm::MachineRegisterInfo::use_nodbg_empty().

optimizeCondBranch()

bool AArch64InstrInfo::optimizeCondBranch ( MachineInstr &  MI ) const

override

Replace csincr-branch sequence by simple conditional branch.

Examples:

1. csinc  w9, wzr, wzr, <condition code>
   tbnz   w9, #0, 0x44

   to

   b.<inverted condition code>

2. csinc w9, wzr, wzr, <condition code>
   tbz   w9, #0, 0x44

   to

   b.<condition code>

Replace compare and branch sequence by TBZ/TBNZ instruction when the compare's constant operand is power of 2.

Examples:

and  w8, w8, #0x400
cbnz w8, L1

to

tbnz w8, #10, L1

Parameters

MI	Conditional Branch

Returns

True when the simple conditional branch is generated

Definition at line 6515 of file AArch64InstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), AK_Write, areCFlagsAccessedBetweenInstrs(), assert(), llvm::BuildMI(), llvm::AArch64_AM::decodeLogicalImmediate(), llvm::MachineRegisterInfo::def_empty(), DefMI, DL, llvm::MachineInstr::findRegisterDefOperandIdx(), get, llvm::MachineOperand::getImm(), llvm::AArch64CC::getInvertedCondCode(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), getRegisterInfo(), llvm::MachineRegisterInfo::getVRegDef(), llvm::MachineRegisterInfo::hasOneDef(), llvm::MachineRegisterInfo::hasOneNonDBGUse(), llvm::RISCVMatInt::Imm, llvm::MachineInstr::isCopy(), llvm::isPowerOf2_64(), llvm::Register::isVirtualRegister(), llvm_unreachable, llvm::Log2_64(), llvm::BitmaskEnumDetail::Mask(), MBB, MI, MRI, llvm::MachineOperand::setIsKill(), and llvm::MachineOperand::setSubReg().

removeBranch()

unsigned AArch64InstrInfo::removeBranch ( MachineBasicBlock &  MBB, int *  BytesRemoved = nullptr  ) const

override

Definition at line 441 of file AArch64InstrInfo.cpp.

References llvm::MachineBasicBlock::begin(), llvm::MachineBasicBlock::end(), llvm::MachineBasicBlock::getLastNonDebugInstr(), I, llvm::isCondBranchOpcode(), llvm::isUncondBranchOpcode(), and MBB.

reverseBranchCondition()

bool AArch64InstrInfo::reverseBranchCondition ( SmallVectorImpl< MachineOperand > &  Cond ) const

override

Definition at line 400 of file AArch64InstrInfo.cpp.

References Cond, llvm::AArch64CC::getInvertedCondCode(), and llvm_unreachable.

shouldClusterMemOps()

bool AArch64InstrInfo::shouldClusterMemOps ( ArrayRef< const MachineOperand * >  BaseOps1, ArrayRef< const MachineOperand * >  BaseOps2, unsigned  NumLoads, unsigned  NumBytes  ) const

override

Detect opportunities for ldp/stp formation.

Only called for LdSt for which getMemOperandWithOffset returns true.

Definition at line 3263 of file AArch64InstrInfo.cpp.

References assert(), canPairLdStOpc(), llvm::ArrayRef< T >::front(), llvm::MachineFunction::getFrameInfo(), llvm::MachineOperand::getImm(), llvm::MachineOperand::getIndex(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getParent(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getType(), hasUnscaledLdStOffset(), isCandidateToMergeOrPair(), llvm::MachineOperand::isFI(), llvm::MachineOperand::isIdenticalTo(), isPairableLdStInst(), llvm::MachineOperand::isReg(), scaleOffset(), shouldClusterFI(), and llvm::ArrayRef< T >::size().

shouldOutlineFromFunctionByDefault()

bool AArch64InstrInfo::shouldOutlineFromFunctionByDefault ( MachineFunction &  MF ) const

override

Definition at line 7836 of file AArch64InstrInfo.cpp.

References llvm::MachineFunction::getFunction(), and llvm::Function::hasMinSize().

storeRegToStackSlot()

void AArch64InstrInfo::storeRegToStackSlot ( MachineBasicBlock &  MBB, MachineBasicBlock::iterator  MBBI, Register  SrcReg, bool  isKill, int  FrameIndex, const TargetRegisterClass *  RC, const TargetRegisterInfo *  TRI  ) const

override

Definition at line 3747 of file AArch64InstrInfo.cpp.

References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), llvm::MachineRegisterInfo::constrainRegClass(), llvm::TargetStackID::Default, get, llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getFrameInfo(), llvm::getKillRegState(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineFrameInfo::getObjectAlign(), llvm::MachineFrameInfo::getObjectSize(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), getRegisterInfo(), llvm::TargetRegisterInfo::getSpillSize(), llvm::Register::isVirtualRegister(), MBB, MBBI, MI, llvm::MachineMemOperand::MOStore, llvm::TargetStackID::ScalableVector, llvm::MachineFrameInfo::setStackID(), storeRegPairToStackSlot(), and TRI.

Referenced by foldMemoryOperandImpl().

suppressLdStPair()

void AArch64InstrInfo::suppressLdStPair ( MachineInstr &  MI )

static

Hint that pairing the given load or store is unprofitable.

Set a flag on the first MachineMemOperand to suppress pairing.

Definition at line 2133 of file AArch64InstrInfo.cpp.

References MI, and llvm::MOSuppressPair.

useMachineCombiner()

bool AArch64InstrInfo::useMachineCombiner ( ) const

override

AArch64 supports MachineCombiner.

Definition at line 4696 of file AArch64InstrInfo.cpp.

---

The documentation for this class was generated from the following files:

• lib/Target/AArch64/AArch64InstrInfo.h
• lib/Target/AArch64/AArch64InstrInfo.cpp