20#define DEBUG_TYPE "regbankselect"
30 return "AMDGPURegBankSelect";
41 "AMDGPU Register Bank Select",
false,
false)
49 if (MF.getProperties().hasProperty(
53 LLVM_DEBUG(
dbgs() <<
"Assign register banks for: " << MF.getName() <<
'\n');
55 Mode SaveOptMode = OptMode;
60 assert(checkFunctionIsLegal(MF));
63 getAnalysis<MachineCycleInfoWrapperPass>().getCycleInfo();
70 assignRegisterBanks(MF);
72 OptMode = SaveOptMode;
amdgpu AMDGPU Register Bank Select
#define INITIALIZE_PASS_DEPENDENCY(depName)
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
#define INITIALIZE_PASS_BEGIN(passName, arg, name, cfg, analysis)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - This function should be overriden by passes that need analysis information to do t...
StringRef getPassName() const override
getPassName - Return a nice clean name for a pass.
AMDGPURegBankSelect(Mode RunningMode=Fast)
Represent the analysis usage information of a pass.
AnalysisUsage & addRequired()
Legacy analysis pass which computes a MachineCycleInfo.
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
MachineDomTree & getBase()
This pass implements the reg bank selector pass used in the GlobalISel pipeline.
Mode
List of the modes supported by the RegBankSelect pass.
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - This function should be overriden by passes that need analysis information to do t...
Wrapper class representing virtual and physical registers.
StringRef - Represent a constant reference to a string, i.e.
This is an optimization pass for GlobalISel generic memory operations.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
MachineUniformityInfo computeMachineUniformityInfo(MachineFunction &F, const MachineCycleInfo &cycleInfo, const MachineDomTree &domTree)
Compute uniformity information for a Machine IR function.