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32 #include "llvm/Config/llvm-config.h"
50 #define DEBUG_TYPE "regbankselect"
57 "Run the Fast mode (default mapping)"),
58 clEnumValN(RegBankSelect::Mode::Greedy,
"regbankselect-greedy",
59 "Use the Greedy mode (best local mapping)")));
64 "Assign register bank of generic virtual registers",
78 LLVM_DEBUG(
dbgs() <<
"RegBankSelect mode overrided by command line\n");
84 assert(RBI &&
"Cannot work without RegisterBankInfo");
87 TPC = &getAnalysis<TargetPassConfig>();
89 MBFI = &getAnalysis<MachineBlockFrequencyInfo>();
90 MBPI = &getAnalysis<MachineBranchProbabilityInfo>();
96 MORE = std::make_unique<MachineOptimizationRemarkEmitter>(MF, MBFI);
111 bool RegBankSelect::assignmentMatch(
113 bool &OnlyAssign)
const {
125 OnlyAssign = CurRegBank ==
nullptr;
127 if (CurRegBank)
dbgs() << *CurRegBank;
else dbgs() <<
"none";
128 dbgs() <<
" against ";
129 assert(DesiredRegBank &&
"The mapping must be valid");
130 dbgs() << *DesiredRegBank <<
'\n';);
131 return CurRegBank == DesiredRegBank;
134 bool RegBankSelect::repairReg(
140 "need new vreg for each breakdown");
143 assert(!NewVRegs.empty() &&
"We should not have to repair");
159 "We are about to create several defs for Dst");
179 MergeOp = TargetOpcode::G_BUILD_VECTOR;
186 "don't understand this value breakdown");
188 MergeOp = TargetOpcode::G_CONCAT_VECTORS;
191 MergeOp = TargetOpcode::G_MERGE_VALUES;
198 MergeBuilder.
addUse(SrcReg);
205 UnMergeBuilder.
addDef(DefReg);
218 std::unique_ptr<MachineInstr *[]> NewInstrs(
222 for (
const std::unique_ptr<InsertPoint> &InsertPt : RepairPt) {
228 InsertPt->insert(*CurMI);
229 NewInstrs[Idx++] = CurMI;
237 uint64_t RegBankSelect::getRepairCost(
240 assert(MO.
isReg() &&
"We should only repair register operand");
262 if (IsSameNumOfValues) {
279 unsigned Cost = RBI->
copyCost(*DesiredRegBank, *CurRegBank,
292 assert(!PossibleMappings.empty() &&
293 "Do not know how to map this instruction");
296 MappingCost Cost = MappingCost::ImpossibleCost();
300 MappingCost CurCost =
301 computeMapping(
MI, *CurMapping, LocalRepairPts, &Cost);
302 if (CurCost < Cost) {
305 BestMapping = CurMapping;
307 for (RepairingPlacement &RepairPt : LocalRepairPts)
315 BestMapping = *PossibleMappings.begin();
319 assert(BestMapping &&
"No suitable mapping for instruction");
323 void RegBankSelect::tryAvoidingSplit(
327 assert(RepairPt.
hasSplit() &&
"We should not have to adjust for split");
330 assert((
MI.isPHI() ||
MI.isTerminator()) &&
"Why do we split?");
333 "Repairing placement does not match operand");
339 assert((!
MI.isPHI() || !MO.
isDef()) &&
"Need split for phi def?");
343 if (
MI.isTerminator()) {
344 assert(&
MI != &(*
MI.getParent()->getFirstTerminator()) &&
345 "Need to split for the first terminator?!");
367 "This code is for the def of a terminator");
414 assert(&
MI == &(*
MI.getParent()->getFirstTerminator()) &&
415 "Do not know which outgoing edges are relevant");
418 "Do not know where each terminator ends up");
432 assert(
false &&
"Repairing cost may not be accurate");
437 RepairPt.
switchTo(RepairingPlacement::RepairingKind::Impossible);
442 RegBankSelect::MappingCost RegBankSelect::computeMapping(
445 const RegBankSelect::MappingCost *BestCost) {
446 assert((MBFI || !BestCost) &&
"Costs comparison require MBFI");
449 return MappingCost::ImpossibleCost();
453 bool Saturated = Cost.addLocalCost(InstrMapping.
getCost());
454 assert(!Saturated &&
"Possible mapping saturated the cost");
458 if (BestCost && Cost > *BestCost) {
459 LLVM_DEBUG(
dbgs() <<
"Mapping is too expensive from the start\n");
467 for (
unsigned OpIdx = 0, EndOpIdx = InstrMapping.
getNumOperands();
468 OpIdx != EndOpIdx; ++OpIdx) {
477 InstrMapping.getOperandMapping(OpIdx);
480 if (assignmentMatch(
Reg, ValMapping, Assign)) {
494 RepairingPlacement &RepairPt = RepairPts.back();
499 if (RepairPt.hasSplit())
500 tryAvoidingSplit(RepairPt, MO, ValMapping);
503 if (!RepairPt.canMaterialize()) {
505 return MappingCost::ImpossibleCost();
510 if (!BestCost || Saturated)
515 assert(MBFI && MBPI &&
"Cost computation requires MBFI and MBPI");
527 uint64_t RepairCost = getRepairCost(MO, ValMapping);
531 return MappingCost::ImpossibleCost();
534 const uint64_t PercentageForBias = 5;
535 uint64_t Bias = (RepairCost * PercentageForBias + 99) / 100;
540 assert(((RepairCost < RepairCost * PercentageForBias) &&
541 (RepairCost * PercentageForBias <
542 RepairCost * PercentageForBias + 99)) &&
543 "Repairing involves more than a billion of instructions?!");
544 for (
const std::unique_ptr<InsertPoint> &InsertPt : RepairPt) {
545 assert(InsertPt->canMaterialize() &&
"We should not have made it here");
547 if (!InsertPt->isSplit())
548 Saturated = Cost.addLocalCost(RepairCost);
550 uint64_t CostForInsertPt = RepairCost;
553 assert(CostForInsertPt + Bias > CostForInsertPt &&
554 "Repairing + split bias overflows");
555 CostForInsertPt += Bias;
556 uint64_t PtCost = InsertPt->frequency(*
this) * CostForInsertPt;
558 if ((Saturated = PtCost < CostForInsertPt))
561 Saturated = Cost.addNonLocalCost(PtCost);
566 if (BestCost && Cost > *BestCost) {
567 LLVM_DEBUG(
dbgs() <<
"Mapping is too expensive, stop processing\n");
581 bool RegBankSelect::applyMapping(
588 for (RepairingPlacement &RepairPt : RepairPts) {
589 if (!RepairPt.canMaterialize() ||
593 "This should not make its way in the list");
594 unsigned OpIdx = RepairPt.getOpIdx();
597 InstrMapping.getOperandMapping(OpIdx);
600 switch (RepairPt.getKind()) {
603 "Reassignment should only be for simple mapping");
607 OpdMapper.createVRegs(OpIdx);
608 if (!repairReg(MO, ValMapping, RepairPt, OpdMapper.getVRegs(OpIdx)))
617 LLVM_DEBUG(
dbgs() <<
"Actual mapping of the operands: " << OpdMapper <<
'\n');
626 unsigned Opc =
MI.getOpcode();
628 assert((Opc == TargetOpcode::G_ASSERT_ZEXT ||
629 Opc == TargetOpcode::G_ASSERT_SEXT) &&
630 "Unexpected hint opcode!");
636 assert(RB &&
"Expected source register to have a register bank?");
637 LLVM_DEBUG(
dbgs() <<
"... Hint always uses source's register bank.\n");
648 MappingCost DefaultCost = computeMapping(
MI, *BestMapping, RepairPts);
650 if (DefaultCost == MappingCost::ImpossibleCost())
655 if (PossibleMappings.empty())
657 BestMapping = &findBestMapping(
MI, PossibleMappings, RepairPts);
666 return applyMapping(
MI, *BestMapping, RepairPts);
677 Mode SaveOptMode = OptMode;
689 "instruction is not legal", *
MI);
715 if (
MI.isInlineAsm())
719 if (
MI.isDebugInstr())
723 if (
MI.isImplicitDef())
726 if (!assignInstr(
MI)) {
728 "unable to map instruction",
MI);
736 if (NextInstBB !=
MBB) {
737 LLVM_DEBUG(
dbgs() <<
"Instruction mapping changed control flow\n");
746 OptMode = SaveOptMode;
760 assert(MO.
isReg() &&
"Trying to repair a non-reg operand");
766 bool Before = !MO.
isDef();
769 if (!
MI.isPHI() && !
MI.isTerminator()) {
782 if (It !=
MI.getParent()->end())
794 for (
auto Begin = Pred.
begin(); It != Begin && It->isTerminator(); --It)
795 if (It->modifiesRegister(
Reg, &
TRI)) {
806 if (It == Pred.
end())
817 auto REnd =
MI.getParent()->rend();
819 for (; It != REnd && It->isTerminator(); ++It) {
821 "copy insertion in middle of terminators not handled");
839 "Do not know where to split");
866 InsertPoints.emplace_back(&Point);
875 "Splitting before phis requires more points");
877 "Splitting between phis does not make sense");
880 void RegBankSelect::InstrInsertPoint::materialize() {
905 return Instr.isTerminator();
908 return Instr.getPrevNode() && Instr.getPrevNode()->isTerminator();
918 return MBFI->
getBlockFreq(Instr.getParent()).getFrequency();
929 void RegBankSelect::EdgeInsertPoint::materialize() {
934 assert(Src.isSuccessor(DstOrSplit) && DstOrSplit->isPredecessor(&Src) &&
935 "This point has already been split");
937 assert(NewBB &&
"Invalid call to materialize");
963 assert(Src.succ_size() > 1 && DstOrSplit->pred_size() > 1 &&
964 "Edge is not critical");
965 return Src.canSplitCriticalEdge(DstOrSplit);
968 RegBankSelect::MappingCost::MappingCost(
const BlockFrequency &LocalFreq)
969 : LocalFreq(LocalFreq.getFrequency()) {}
971 bool RegBankSelect::MappingCost::addLocalCost(uint64_t Cost) {
973 if (LocalCost + Cost < LocalCost) {
978 return isSaturated();
981 bool RegBankSelect::MappingCost::addNonLocalCost(uint64_t Cost) {
983 if (NonLocalCost + Cost < NonLocalCost) {
987 NonLocalCost += Cost;
988 return isSaturated();
991 bool RegBankSelect::MappingCost::isSaturated()
const {
996 void RegBankSelect::MappingCost::saturate() {
997 *
this = ImpossibleCost();
1001 RegBankSelect::MappingCost RegBankSelect::MappingCost::ImpossibleCost() {
1011 if ((*
this == ImpossibleCost()) || (Cost == ImpossibleCost()))
1012 return (*
this == ImpossibleCost()) < (Cost == ImpossibleCost());
1015 if (isSaturated() || Cost.isSaturated())
1016 return isSaturated() < Cost.isSaturated();
1023 uint64_t ThisLocalAdjust;
1024 uint64_t OtherLocalAdjust;
1029 if (NonLocalCost == Cost.NonLocalCost)
1032 return LocalCost < Cost.LocalCost;
1036 ThisLocalAdjust = 0;
1037 OtherLocalAdjust = 0;
1038 if (LocalCost < Cost.LocalCost)
1039 OtherLocalAdjust = Cost.LocalCost - LocalCost;
1041 ThisLocalAdjust = LocalCost - Cost.LocalCost;
1043 ThisLocalAdjust = LocalCost;
1044 OtherLocalAdjust = Cost.LocalCost;
1048 uint64_t ThisNonLocalAdjust = 0;
1049 uint64_t OtherNonLocalAdjust = 0;
1050 if (NonLocalCost < Cost.NonLocalCost)
1051 OtherNonLocalAdjust = Cost.NonLocalCost - NonLocalCost;
1053 ThisNonLocalAdjust = NonLocalCost - Cost.NonLocalCost;
1055 uint64_t ThisScaledCost = ThisLocalAdjust * LocalFreq;
1057 bool ThisOverflows = ThisLocalAdjust && (ThisScaledCost < ThisLocalAdjust ||
1058 ThisScaledCost < LocalFreq);
1059 uint64_t OtherScaledCost = OtherLocalAdjust * Cost.LocalFreq;
1061 bool OtherOverflows =
1063 (OtherScaledCost < OtherLocalAdjust || OtherScaledCost < Cost.LocalFreq);
1065 ThisOverflows |= ThisNonLocalAdjust &&
1066 ThisScaledCost + ThisNonLocalAdjust < ThisNonLocalAdjust;
1067 ThisScaledCost += ThisNonLocalAdjust;
1068 OtherOverflows |= OtherNonLocalAdjust &&
1069 OtherScaledCost + OtherNonLocalAdjust < OtherNonLocalAdjust;
1070 OtherScaledCost += OtherNonLocalAdjust;
1073 if (ThisOverflows && OtherOverflows)
1076 if (ThisOverflows || OtherOverflows)
1077 return ThisOverflows < OtherOverflows;
1079 return ThisScaledCost < OtherScaledCost;
1083 return LocalCost == Cost.LocalCost && NonLocalCost == Cost.NonLocalCost &&
1084 LocalFreq == Cost.LocalFreq;
1087 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
1095 if (*
this == ImpossibleCost()) {
1099 if (isSaturated()) {
1103 OS << LocalFreq <<
" * " << LocalCost <<
" + " << NonLocalCost;
RepairingPlacement(MachineInstr &MI, unsigned OpIdx, const TargetRegisterInfo &TRI, Pass &P, RepairingKind Kind=RepairingKind::Insert)
Create a repairing placement for the OpIdx-th operand of MI.
void setMF(MachineFunction &MF)
void addInsertPoint(MachineBasicBlock &MBB, bool Beginning)
Abstract class used to represent an insertion point in a CFG.
bool hasProperty(Property P) const
#define LLVM_DUMP_METHOD
Mark debug helper function definitions like dump() that should not be stripped from debug builds.
unsigned getScalarSizeInBits() const
static void print(raw_ostream &Out, object::Archive::Kind Kind, T Val)
Vector Rotate Left Mask Mask Insert
bool isPreISelGenericOptimizationHint(unsigned Opcode)
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
InstrInsertPoint(MachineInstr &Instr, bool Before=true)
Create an insertion point before (Before=true) or after Instr.
NodeTy * getNextNode()
Get the next node, or nullptr for the list tail.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
bool verify(const MachineInstr &MI) const
Verifiy that this mapping makes sense for MI.
RegisterBank & getRegBank(unsigned ID)
Get the register bank identified by ID.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
cl::opt< bool > DisableGISelLegalityCheck
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
void getSelectionDAGFallbackAnalysisUsage(AnalysisUsage &AU)
Modify analysis usage so it preserves passes required for the SelectionDAG fallback.
MachineInstrBuilder buildInstrNoInsert(unsigned Opcode)
Build but don't insert <empty> = Opcode <empty>.
void dump(const SparseBitVector< ElementSize > &LHS, raw_ostream &out)
bool isValid() const
Check whether this object is valid.
unsigned const TargetRegisterInfo * TRI
INITIALIZE_PASS_END(RegBankSelect, DEBUG_TYPE, "Assign register bank of generic virtual registers", false, false) RegBankSelect
@ Insert
Reparing code needs to happen before InsertPoints.
uint64_t frequency(const Pass &P) const override
Frequency of the insertion point.
BlockFrequency getBlockFreq(const MachineBasicBlock *MBB) const
getblockFreq - Return block frequency.
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
const PartialMapping * BreakDown
How the value is broken down between the different register banks.
bool partsAllUniform() const
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
uint64_t frequency(const Pass &P) const override
Frequency of the insertion point.
virtual unsigned getBreakDownCost(const ValueMapping &ValMapping, const RegisterBank *CurBank=nullptr) const
Get the cost of using ValMapping to decompose a register.
bool isUnconditionalBranch(QueryType Type=AnyInBundle) const
Return true if this is a branch which always transfers control flow to some other block.
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
RepairingKind
Define the kind of action this repairing needs.
uint64_t frequency(const Pass &P) const override
Frequency of the insertion point.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
This class implements the register bank concept.
MachineBlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate machine basic b...
void setMBB(MachineBasicBlock &MBB)
Set the insertion point to the end of MBB.
unsigned getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
bool runOnMachineFunction(MachineFunction &MF) override
Walk through MF and assign a register bank to every virtual register that are still mapped to nothing...
void applyMapping(const OperandsMapper &OpdMapper) const
Apply OpdMapper.getInstrMapping() to OpdMapper.getMI().
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Represent the analysis usage information of a pass.
const MachineFunctionProperties & getProperties() const
Get the function properties.
InstructionMappings getInstrPossibleMappings(const MachineInstr &MI) const
Get the possible mapping for MI.
Insertion point on an edge.
MachineOperand class - Representation of each machine instruction operand.
bool isGlobalISelAbortEnabled() const
Check whether or not GlobalISel should abort on error.
INITIALIZE_PASS_BEGIN(RegBankSelect, DEBUG_TYPE, "Assign register bank of generic virtual registers", false, false)
const MachineInstr * machineFunctionIsIllegal(const MachineFunction &MF)
Checks that MIR is fully legal, returns an illegal instruction if it's not, nullptr otherwise.
MachineFunction & getMF()
Getter for the function we currently build.
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Insertion point before or after an instruction.
This class implements an extremely fast bulk output stream that can only output to a stream.
virtual bool canMaterialize() const
Check whether this insertion point can be materialized.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
@ Reassign
(Re)assign the register bank of the operand.
unsigned getSizeInBits(Register Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const
Get the size in bits of Reg.
virtual void print(raw_ostream &OS, const Module *M) const
print - Print out the internal state of the pass.
Helper class used to get/create the virtual registers that will be used to replace the MachineOperand...
Target-Independent Code Generator Pass Configuration Options.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
ValuesClass values(OptsTy... Options)
Helper to build a ValuesClass by forwarding a variable number of arguments as an initializer list to ...
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Representation of each machine instruction.
void setRegBank(Register Reg, const RegisterBank &RegBank)
Set the register bank to RegBank for Reg.
Helper class that represents how the value of an instruction may be mapped and what is the related co...
MachineInstr * CloneMachineInstr(const MachineInstr *Orig)
Create a new MachineInstr which is a copy of Orig, identical in all ways except the instruction has n...
INITIALIZE_PASS_DEPENDENCY(DominatorTreeWrapperPass)
unsigned getNumOperands() const
Get the number of operands.
@ Fast
Fast - This calling convention attempts to make calls as fast as possible (e.g.
compiles ldr LCPI1_0 ldr ldr mov lsr tst moveq r1 ldr LCPI1_1 and r0 bx lr It would be better to do something like to fold the shift into the conditional move
bool isSplit() const override
Does this point involve splitting an edge or block? As soon as ::getPoint is called and thus,...
uint64_t getFrequency() const
Returns the frequency as a fixpoint number scaled by the entry frequency.
uint16_t getNumElements() const
Returns the number of elements in a vector LLT.
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
typename SuperClass::const_iterator const_iterator
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
unsigned getCost() const
Get the cost.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
const MachineInstrBuilder & addUse(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
Register getReg() const
getReg - Returns the register number.
const RegisterBank * RegBank
Register bank where the partial value lives.
BranchProbability getEdgeProbability(const MachineBasicBlock *Src, const MachineBasicBlock *Dst) const
should just be implemented with a CLZ instruction Since there are other e that share this it would be best to implement this in a target independent as zero is the default value for the binary encoder e add r0 add r5 Register operands should be distinct That when the encoding does not require two syntactical operands to refer to the same register
bool readsRegister(Register Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr reads the specified register.
virtual const RegisterBankInfo * getRegBankInfo() const
If the information for the register banks is available, return it.
auto size(R &&Range, std::enable_if_t< std::is_base_of< std::random_access_iterator_tag, typename std::iterator_traits< decltype(Range.begin())>::iterator_category >::value, void > *=nullptr)
Get the size of a range.
Helper struct that represents how a value is mapped through different register banks.
@ None
Nothing to repair, just drop this action.
iterator_range< succ_iterator > successors()
iterator getLastNonDebugInstr(bool SkipPseudoOp=false)
Returns an iterator to the last non-debug instruction in the basic block, or end().
unsigned getNumInsertPoints() const
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Struct used to represent the placement of a repairing point for a given operand.
#define clEnumValN(ENUMVAL, FLAGNAME, DESC)
unsigned Length
Length of this mapping in bits.
Wrapper class representing virtual and physical registers.
bool canMaterialize() const override
Check whether this insertion point can be materialized.
bool operator==(const StringView &LHS, const StringView &RHS)
Function & getFunction()
Return the LLVM function that this machine code represents.
bool operator<(const DeltaInfo &LHS, int64_t Delta)
bool isTargetSpecificOpcode(unsigned Opcode)
Check whether the given Opcode is a target-specific opcode.
virtual bool isSplit() const
Does this point involve splitting an edge or block? As soon as ::getPoint is called and thus,...
const RegisterBank * getRegBankOrNull(Register Reg) const
Return the register bank of Reg, or null if Reg has not been assigned a register bank or has been ass...
virtual unsigned copyCost(const RegisterBank &A, const RegisterBank &B, unsigned Size) const
Get the cost of a copy from B to A, or put differently, get the cost of A = COPY B.
virtual const InstructionMapping & getInstrMapping(const MachineInstr &MI) const
Get the mapping of the different operands of MI on the register bank.
void reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC, MachineOptimizationRemarkEmitter &MORE, MachineOptimizationRemarkMissed &R)
Report an ISel error as a missed optimization remark to the LLVMContext's diagnostic stream.
unsigned NumBreakDowns
Number of partial mapping to break down this value.
Mode
List of the modes supported by the RegBankSelect pass.
Pass interface - Implemented by all 'passes'.
void switchTo(RepairingKind NewKind)
Change the type of this repairing placement to NewKind.
LLT getType(Register Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register.
Align max(MaybeAlign Lhs, Align Rhs)
A range adaptor for a pair of iterators.
#define LLVM_LIKELY(EXPR)
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
unsigned getOpIdx() const
This pass implements the reg bank selector pass used in the GlobalISel pipeline.
AnalysisUsage & addRequired()
Insertion point at the beginning or end of a basic block.
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
Implement PPCInstrInfo::isLoadFromStackSlot isStoreToStackSlot for vector registers
@ Impossible
Mark this repairing placement as impossible.
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - This function should be overriden by passes that need analysis information to do t...
Add support for conditional and other related patterns Instead of
static cl::opt< RegBankSelect::Mode > RegBankSelectMode(cl::desc("Mode of the RegBankSelect pass"), cl::Hidden, cl::Optional, cl::values(clEnumValN(RegBankSelect::Mode::Fast, "regbankselect-fast", "Run the Fast mode (default mapping)"), clEnumValN(RegBankSelect::Mode::Greedy, "regbankselect-greedy", "Use the Greedy mode (best local mapping)")))
reference emplace_back(ArgTypes &&... Args)