23 for (
auto &
op :
I.all_defs()) {
24 if (isDivergent(
op.getReg()))
33 bool insertedDivergent =
false;
34 const auto &
MRI =
F.getRegInfo();
35 const auto &RBI = *
F.getSubtarget().getRegBankInfo();
36 const auto &
TRI = *
MRI.getTargetRegisterInfo();
37 for (
auto &
op : Instr.all_defs()) {
38 if (!
op.getReg().isVirtual())
41 if (
TRI.isUniformReg(
MRI, RBI,
op.getReg()))
43 insertedDivergent |= markDivergent(
op.getReg());
45 return insertedDivergent;
50 const auto &
InstrInfo = *
F.getSubtarget().getInstrInfo();
55 if (
uniformity == InstructionUniformity::AlwaysUniform) {
56 addUniformOverride(
instr);
60 if (
uniformity == InstructionUniformity::NeverUniform) {
71 const auto &RegInfo =
F.getRegInfo();
72 for (
MachineInstr &UserInstr : RegInfo.use_instructions(Reg)) {
73 markDivergent(UserInstr);
80 assert(!isAlwaysUniform(Instr));
81 if (
Instr.isTerminator())
84 auto Reg =
op.getReg();
94 for (
auto &
Op :
I.operands()) {
95 if (!
Op.isReg() || !
Op.readsReg())
97 auto Reg =
Op.getReg();
101 if (
Reg.isPhysical())
104 auto *
Def =
F.getRegInfo().getVRegDef(Reg);
115 const auto &
RegInfo =
F.getRegInfo();
116 for (
auto &
Op :
I.all_defs()) {
117 if (!
Op.getReg().isVirtual())
119 auto Reg =
Op.getReg();
120 if (isDivergent(Reg))
123 if (DefCycle.
contains(UserInstr.getParent()))
125 markDivergent(UserInstr);
136 auto Reg = U.getReg();
137 if (isDivergent(Reg))
140 const auto &RegInfo =
F.getRegInfo();
141 auto *Def = RegInfo.getOneDef(Reg);
145 auto *DefInstr = Def->getParent();
146 auto *UseInstr = U.getParent();
147 return isTemporalDivergent(*UseInstr->getParent(), *DefInstr);
159 assert(
F.getRegInfo().isSSA() &&
"Expected to be run on SSA form!");
161 if (HasBranchDivergence)
175 MachineUniformityAnalysisPass();
191 MachineUniformityInfoPrinterPass();
199char MachineUniformityAnalysisPass::ID = 0;
201MachineUniformityAnalysisPass::MachineUniformityAnalysisPass()
207 "Machine Uniformity Info Analysis",
true,
true)
213void MachineUniformityAnalysisPass::getAnalysisUsage(
AnalysisUsage &AU)
const {
214 AU.setPreservesAll();
220bool MachineUniformityAnalysisPass::runOnMachineFunction(
MachineFunction &MF) {
221 auto &DomTree = getAnalysis<MachineDominatorTree>().getBase();
222 auto &CI = getAnalysis<MachineCycleInfoWrapperPass>().getCycleInfo();
231 OS <<
"MachineUniformityInfo for function: " << UI.getFunction().getName()
236char MachineUniformityInfoPrinterPass::ID = 0;
238MachineUniformityInfoPrinterPass::MachineUniformityInfoPrinterPass()
245 "print-machine-uniformity",
246 "Print Machine Uniformity Info Analysis",
true,
true)
252void MachineUniformityInfoPrinterPass::getAnalysisUsage(
254 AU.setPreservesAll();
255 AU.addRequired<MachineUniformityAnalysisPass>();
259bool MachineUniformityInfoPrinterPass::runOnMachineFunction(
261 auto &UI = getAnalysis<MachineUniformityAnalysisPass>();
unsigned const MachineRegisterInfo * MRI
static void print(raw_ostream &Out, object::Archive::Kind Kind, T Val)
This file declares a specialization of the GenericSSAContext<X> template class for Machine IR.
unsigned const TargetRegisterInfo * TRI
#define INITIALIZE_PASS_DEPENDENCY(depName)
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
#define INITIALIZE_PASS_BEGIN(passName, arg, name, cfg, analysis)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
unify loop Fixup each natural loop to have a single exit block
Represent the analysis usage information of a pass.
This class represents an Operation in the Expression.
Core dominator tree base class.
A possibly irreducible generalization of a Loop.
bool contains(const BlockT *Block) const
Return whether Block is contained in the cycle.
Legacy analysis pass which computes a MachineCycleInfo.
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
virtual bool runOnMachineFunction(MachineFunction &MF)=0
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
Representation of each machine instruction.
MachineOperand class - Representation of each machine instruction operand.
A Module instance is used to store all the information related to an LLVM module.
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
virtual void print(raw_ostream &OS, const Module *M) const
print - Print out the internal state of the pass.
Wrapper class representing virtual and physical registers.
This class implements an extremely fast bulk output stream that can only output to a stream.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Reg
All possible values of the reg field in the ModR/M byte.
NodeAddr< InstrNode * > Instr
NodeAddr< DefNode * > Def
This is an optimization pass for GlobalISel generic memory operations.
MachineUniformityInfo computeMachineUniformityInfo(MachineFunction &F, const MachineCycleInfo &cycleInfo, const MachineDomTree &domTree, bool HasBranchDivergence)
Compute uniformity information for a Machine IR function.
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
void initializeMachineUniformityAnalysisPassPass(PassRegistry &)
void initializeMachineUniformityInfoPrinterPassPass(PassRegistry &)