13#ifndef LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMADDRESSINGMODES_H
14#define LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMADDRESSINGMODES_H
86 inline unsigned rotr32(
unsigned Val,
unsigned Amt) {
87 assert(Amt < 32 &&
"Invalid rotate amount");
88 return (Val >> Amt) | (Val << ((32-Amt)&31));
93 inline unsigned rotl32(
unsigned Val,
unsigned Amt) {
94 assert(Amt < 32 &&
"Invalid rotate amount");
95 return (Val << Amt) | (Val >> ((32-Amt)&31));
113 return ShOp | (Imm << 3);
132 if ((Imm & ~255U) == 0)
return 0;
139 unsigned RotAmt = TZ & ~1;
142 if ((
rotr32(Imm, RotAmt) & ~255U) == 0)
143 return (32-RotAmt)&31;
149 unsigned RotAmt2 = TZ2 & ~1;
150 if ((
rotr32(Imm, RotAmt2) & ~255U) == 0)
151 return (32-RotAmt2)&31;
157 return (32-RotAmt)&31;
166 if ((
Arg & ~255U) == 0)
return Arg;
175 return rotl32(
Arg, RotAmt) | ((RotAmt>>1) << 8);
227 if ((Imm & ~255U) == 0)
return 0;
246 if ((Imm & ~65535U) == 0)
return 0;
279 if ((V & 0xffffff00) == 0)
283 Vs = ((V & 0xff) == 0) ? V >> 8 : V;
287 u = Imm | (Imm << 16);
291 return (((Vs == V) ? 1 : 2) << 8) | Imm;
294 if (Vs == (u | (u << 8)))
295 return (3 << 8) | Imm;
310 if ((
rotr32(0xff000000U, RotAmt) & V) == V)
311 return (
rotr32(V, 24 - RotAmt) & 0x7f) | ((RotAmt + 8) << 7);
335 if ((V & ~255U) == 0)
return 0;
338 return (32 - RotAmt) & 31;
370 "Immedate cannot be encoded as two part immediate!");
378 return Imm & 0xff00ff00U;
382 return Imm & 0x00ff00ffU;
390 "Unable to encode second part of T2 two part SO immediate");
414 unsigned IdxMode = 0) {
415 assert(Imm12 < (1 << 12) &&
"Imm too large!");
416 bool isSub = Opc ==
sub;
417 return Imm12 | ((int)isSub << 12) | (SO << 13) | (IdxMode << 16) ;
420 return AM2Opc & ((1 << 12)-1);
423 return ((AM2Opc >> 12) & 1) ?
sub :
add;
426 return (
ShiftOpc)((AM2Opc >> 13) & 7);
446 unsigned IdxMode = 0) {
447 bool isSub = Opc ==
sub;
448 return ((
int)isSub << 8) |
Offset | (IdxMode << 9);
450 inline unsigned char getAM3Offset(
unsigned AM3Opc) {
return AM3Opc & 0xFF; }
452 return ((AM3Opc >> 8) & 1) ?
sub :
add;
490 bool isSub = Opc ==
sub;
491 return ((
int)isSub << 8) |
Offset;
493 inline unsigned char getAM5Offset(
unsigned AM5Opc) {
return AM5Opc & 0xFF; }
495 return ((AM5Opc >> 8) & 1) ?
sub :
add;
511 bool isSub = Opc ==
sub;
512 return ((
int)isSub << 8) |
Offset;
515 return AM5Opc & 0xFF;
518 return ((AM5Opc >> 8) & 1) ?
sub :
add;
547 return (OpCmode << 8) | Val;
550 return (ModImm >> 8) & 0x1f;
562 if (OpCmode == 0xe) {
566 }
else if ((OpCmode & 0xc) == 0x8) {
568 unsigned ByteNum = (OpCmode & 0x6) >> 1;
569 Val = Imm8 << (8 * ByteNum);
571 }
else if ((OpCmode & 0x8) == 0) {
573 unsigned ByteNum = (OpCmode & 0x6) >> 1;
574 Val = Imm8 << (8 * ByteNum);
576 }
else if ((OpCmode & 0xe) == 0xc) {
578 unsigned ByteNum = 1 + (OpCmode & 0x1);
579 Val = (Imm8 << (8 * ByteNum)) | (0xffff >> (8 * (2 - ByteNum)));
581 }
else if (OpCmode == 0x1e) {
583 for (
unsigned ByteNum = 0; ByteNum < 8; ++ByteNum) {
584 if ((ModImm >> ByteNum) & 1)
585 Val |= (
uint64_t)0xff << (8 * ByteNum);
598 for (
unsigned i = 0; i <
Size; ++i) {
636 else if (
Value > 0xffffff)
647 uint8_t Sign = (Imm >> 7) & 0x1;
648 uint8_t Exp = (Imm >> 4) & 0x7;
649 uint8_t Mantissa = Imm & 0xf;
657 I |= ((Exp & 0x4) != 0 ? 0 : 1) << 30;
658 I |= ((Exp & 0x4) != 0 ? 0x1f : 0) << 25;
659 I |= (Exp & 0x3) << 23;
661 return bit_cast<float>(
I);
668 uint32_t Sign = Imm.lshr(15).getZExtValue() & 1;
669 int32_t Exp = (Imm.lshr(10).getSExtValue() & 0x1f) - 15;
670 int64_t Mantissa = Imm.getZExtValue() & 0x3ff;
679 if (Exp < -3 || Exp > 4)
681 Exp = ((Exp+3) & 0x7) ^ 4;
683 return ((
int)Sign << 7) | (Exp << 4) | Mantissa;
693 if (Imm.getActiveBits() > 16)
706 uint32_t Sign = Imm.lshr(31).getZExtValue() & 1;
707 int32_t Exp = (Imm.lshr(23).getSExtValue() & 0xff) - 127;
708 int64_t Mantissa = Imm.getZExtValue() & 0x7fffff;
712 if (Mantissa & 0x7ffff)
715 if ((Mantissa & 0xf) != Mantissa)
719 if (Exp < -3 || Exp > 4)
721 Exp = ((Exp+3) & 0x7) ^ 4;
723 return ((
int)Sign << 7) | (Exp << 4) | Mantissa;
734 uint64_t Sign = Imm.lshr(63).getZExtValue() & 1;
735 int64_t Exp = (Imm.lshr(52).getSExtValue() & 0x7ff) - 1023;
736 uint64_t Mantissa = Imm.getZExtValue() & 0xfffffffffffffULL;
740 if (Mantissa & 0xffffffffffffULL)
743 if ((Mantissa & 0xf) != Mantissa)
747 if (Exp < -3 || Exp > 4)
749 Exp = ((Exp+3) & 0x7) ^ 4;
751 return ((
int)Sign << 7) | (Exp << 4) | Mantissa;
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
This file declares a class to represent arbitrary precision floating point values and provide a varie...
This file implements a class to represent arbitrary precision integral constant values and operations...
static cl::opt< RegAllocEvictionAdvisorAnalysis::AdvisorMode > Mode("regalloc-enable-advisor", cl::Hidden, cl::init(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Default), cl::desc("Enable regalloc advisor mode"), cl::values(clEnumValN(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Default, "default", "Default"), clEnumValN(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Release, "release", "precompiled"), clEnumValN(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Development, "development", "for training")))
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file implements the C++20 <bit> header.
APInt bitcastToAPInt() const
Class for arbitrary precision integers.
LLVM Value Representation.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned char getAM3Offset(unsigned AM3Opc)
unsigned char getAM5FP16Offset(unsigned AM5Opc)
unsigned getSORegOffset(unsigned Op)
int getSOImmVal(unsigned Arg)
getSOImmVal - Given a 32-bit immediate, if it is something that can fit into an shifter_operand immed...
ShiftOpc getAM2ShiftOpc(unsigned AM2Opc)
int getFP32Imm(const APInt &Imm)
getFP32Imm - Return an 8-bit floating-point version of the 32-bit floating-point value.
uint64_t decodeVMOVModImm(unsigned ModImm, unsigned &EltBits)
decodeVMOVModImm - Decode a NEON/MVE modified immediate value into the element value and the element ...
unsigned getAM2IdxMode(unsigned AM2Opc)
unsigned getT2SOImmValRotate(unsigned V)
unsigned encodeNEONi16splat(unsigned Value)
unsigned getAM3IdxMode(unsigned AM3Opc)
unsigned getAM2Offset(unsigned AM2Opc)
unsigned getThumbImmNonShiftedVal(unsigned V)
getThumbImmNonShiftedVal - If V is a value that satisfies isThumbImmShiftedVal, return the non-shiftd...
unsigned getSOImmValRotate(unsigned Imm)
getSOImmValRotate - Try to handle Imm with an immediate shifter operand, computing the rotate amount ...
bool isThumbImmShiftedVal(unsigned V)
isThumbImmShiftedVal - Return true if the specified value can be obtained by left shifting a 8-bit im...
unsigned rotr32(unsigned Val, unsigned Amt)
rotr32 - Rotate a 32-bit unsigned value right by a specified # bits.
const char * getAMSubModeStr(AMSubMode Mode)
unsigned getVMOVModImmVal(unsigned ModImm)
float getFPImmFloat(unsigned Imm)
int getT2SOImmVal(unsigned Arg)
getT2SOImmVal - Given a 32-bit immediate, if it is something that can fit into a Thumb-2 shifter_oper...
unsigned getAM2Opc(AddrOpc Opc, unsigned Imm12, ShiftOpc SO, unsigned IdxMode=0)
int getT2SOImmValRotateVal(unsigned V)
getT2SOImmValRotateVal - Return the 12-bit encoded representation if the specified value is a rotated...
unsigned getAM5Opc(AddrOpc Opc, unsigned char Offset)
getAM5Opc - This function encodes the addrmode5 opc field.
unsigned getSOImmValRot(unsigned Imm)
getSOImmValRot - Given an encoded imm field for the reg/imm form, return the rotate amount.
ShiftOpc getSORegShOp(unsigned Op)
AddrOpc getAM5Op(unsigned AM5Opc)
unsigned createVMOVModImm(unsigned OpCmode, unsigned Val)
int getFP64Imm(const APInt &Imm)
getFP64Imm - Return an 8-bit floating-point version of the 64-bit floating-point value.
bool isNEONi16splat(unsigned Value)
Checks if Value is a correct immediate for instructions like VBIC/VORR.
bool isSOImmTwoPartValNeg(unsigned V)
isSOImmTwoPartValNeg - Return true if the specified value can be obtained by two SOImmVal,...
unsigned getSOImmTwoPartSecond(unsigned V)
getSOImmTwoPartSecond - If V is a value that satisfies isSOImmTwoPartVal, return the second chunk of ...
unsigned getVMOVModImmOpCmode(unsigned ModImm)
unsigned getAM5FP16Opc(AddrOpc Opc, unsigned char Offset)
getAM5FP16Opc - This function encodes the addrmode5fp16 opc field.
bool isSOImmTwoPartVal(unsigned V)
isSOImmTwoPartVal - Return true if the specified value can be obtained by or'ing together two SOImmVa...
unsigned getAM3Opc(AddrOpc Opc, unsigned char Offset, unsigned IdxMode=0)
getAM3Opc - This function encodes the addrmode3 opc field.
AddrOpc getAM5FP16Op(unsigned AM5Opc)
unsigned getAM4ModeImm(AMSubMode SubMode)
unsigned getThumbImm16ValShift(unsigned Imm)
getThumbImm16ValShift - Try to handle Imm with a 16-bit immediate followed by a left shift.
bool isNEONi32splat(unsigned Value)
Checks if Value is a correct immediate for instructions like VBIC/VORR.
int getFP16Imm(const APInt &Imm)
getFP16Imm - Return an 8-bit floating-point version of the 16-bit floating-point value.
unsigned getSORegOpc(ShiftOpc ShOp, unsigned Imm)
unsigned rotl32(unsigned Val, unsigned Amt)
rotl32 - Rotate a 32-bit unsigned value left by a specified # bits.
unsigned getShiftOpcEncoding(ShiftOpc Op)
unsigned getT2SOImmTwoPartSecond(unsigned Imm)
int getT2SOImmValSplatVal(unsigned V)
getT2SOImmValSplat - Return the 12-bit encoded representation if the specified value can be obtained ...
const char * getAddrOpcStr(AddrOpc Op)
const char * getShiftOpcStr(ShiftOpc Op)
int getFP32FP16Imm(const APInt &Imm)
If this is a FP16Imm encoded as a fp32 value, return the 8-bit encoding for it.
unsigned getSOImmValImm(unsigned Imm)
getSOImmValImm - Given an encoded imm field for the reg/imm form, return the 8-bit imm value.
unsigned getT2SOImmTwoPartFirst(unsigned Imm)
unsigned encodeNEONi32splat(unsigned Value)
Encode NEON 32 bits Splat immediate for instructions like VBIC/VORR.
bool isT2SOImmTwoPartVal(unsigned Imm)
bool isNEONBytesplat(unsigned Value, unsigned Size)
unsigned char getAM5Offset(unsigned AM5Opc)
unsigned getSOImmTwoPartFirst(unsigned V)
getSOImmTwoPartFirst - If V is a value that satisfies isSOImmTwoPartVal, return the first chunk of it...
AddrOpc getAM2Op(unsigned AM2Opc)
AddrOpc getAM3Op(unsigned AM3Opc)
AMSubMode getAM4SubMode(unsigned Mode)
unsigned getThumbImmValShift(unsigned Imm)
getThumbImmValShift - Try to handle Imm with a 8-bit immediate followed by a left shift.
bool isThumbImm16ShiftedVal(unsigned V)
isThumbImm16ShiftedVal - Return true if the specified value can be obtained by left shifting a 16-bit...
This is an optimization pass for GlobalISel generic memory operations.
int countr_zero(T Val)
Count number of 0's from the least significant bit to the most stopping at the first 1.
int countl_zero(T Val)
Count number of 0's from the most significant bit to the least stopping at the first 1.
auto count(R &&Range, const E &Element)
Wrapper function around std::count to count the number of times an element Element occurs in the give...