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53 if (!
f64AssignAPCS(ValNo, ValVT, LocVT, LocInfo, State,
true))
66 static const MCPhysReg LoRegList[] = { ARM::R1, ARM::R3 };
67 static const MCPhysReg ShadowRegList[] = { ARM::R0, ARM::R1 };
75 assert((!
Reg ||
Reg == ARM::R3) &&
"Wrong GPRs usage for f64");
88 for (
i = 0;
i < 2; ++
i)
89 if (HiRegList[
i] ==
Reg)
94 assert(
T == LoRegList[
i] &&
"Could not allocate register");
117 static const MCPhysReg LoRegList[] = { ARM::R1, ARM::R3 };
124 for (
i = 0;
i < 2; ++
i)
125 if (HiRegList[
i] ==
Reg)
156 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
157 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
158 ARM::S12, ARM::S13, ARM::S14, ARM::S15 };
160 ARM::D4, ARM::D5, ARM::D6, ARM::D7 };
177 if (PendingMembers.size() > 0)
178 assert(PendingMembers[0].getLocVT() == LocVT);
194 const Align FirstMemberAlign(PendingMembers[0].getExtraInfo());
205 unsigned RegAlign =
alignTo(Alignment.value(), 4) / 4;
206 while (RegIdx % RegAlign != 0 && RegIdx < RegList.
size())
231 unsigned RegResult = State.
AllocateRegBlock(RegList, PendingMembers.size());
233 for (
CCValAssign &PendingMember : PendingMembers) {
234 PendingMember.convertToReg(RegResult);
235 State.
addLoc(PendingMember);
238 PendingMembers.clear();
248 for (
auto &It : PendingMembers) {
249 if (RegIdx >= RegList.
size())
252 It.convertToReg(State.
AllocateReg(RegList[RegIdx++]));
256 PendingMembers.clear();
264 for (
auto Reg : RegList)
274 for (
auto &It : PendingMembers) {
277 Alignment =
Align(1);
281 PendingMembers.clear();
316 #include "ARMGenCallingConv.inc"
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
static bool f64AssignAAPCS(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, CCState &State, bool CanFail)
This is an optimization pass for GlobalISel generic memory operations.
static bool f64RetAssign(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, CCState &State)
static bool RetCC_ARM_APCS_Custom_f64(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCState - This class holds information needed while lowering arguments and return values.
bool isInConsecutiveRegsLast() const
void addLoc(const CCValAssign &V)
Reg
All possible values of the reg field in the ModR/M byte.
MachineFunction & getMachineFunction() const
static bool CC_ARM_AAPCS_Custom_f16(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
static CCValAssign getPending(unsigned ValNo, MVT ValVT, MVT LocVT, LocInfo HTP, unsigned ExtraInfo=0)
MCPhysReg AllocateRegBlock(ArrayRef< MCPhysReg > Regs, unsigned RegsRequired)
AllocateRegBlock - Attempt to allocate a block of RegsRequired consecutive registers.
static const MCPhysReg DRegList[]
CCValAssign - Represent assignment of one arg/retval to a location.
Align getNonZeroMemAlign() const
static bool CC_ARM_AAPCS_Custom_Aggregate(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
bool isTargetAEABI() const
static CCValAssign getCustomMem(unsigned ValNo, MVT ValVT, unsigned Offset, MVT LocVT, LocInfo HTP)
static bool CC_ARM_APCS_Custom_f64(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
This struct is a compact representation of a valid (non-zero power of two) alignment.
static bool RetCC_ARM_AAPCS_Custom_f64(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
Align getNonZeroOrigAlign() const
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
static bool CustomAssignInRegList(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, CCState &State, ArrayRef< MCPhysReg > RegList)
static const MCPhysReg GPRArgRegs[]
static bool CC_ARM_AAPCS_Custom_f64(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
static const MCPhysReg RRegList[]
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
TypeSize getSizeInBits() const
Returns the size of the specified MVT in bits.
static CCValAssign getCustomReg(unsigned ValNo, MVT ValVT, unsigned RegNo, MVT LocVT, LocInfo HTP)
SmallVectorImpl< CCValAssign > & getPendingLocs()
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Expected< ExpressionValue > min(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
MCRegister AllocateReg(MCPhysReg Reg)
AllocateReg - Attempt to allocate one register.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
unsigned getFirstUnallocated(ArrayRef< MCPhysReg > Regs) const
getFirstUnallocated - Return the index of the first unallocated register in the set,...
uint64_t value() const
This is a hole in the type system and should not be abused.
unsigned AllocateStack(unsigned Size, Align Alignment)
AllocateStack - Allocate a chunk of stack space with the specified size and alignment.
static const MCPhysReg QRegList[]
unsigned getNextStackOffset() const
getNextStackOffset - Return the next stack offset such that all stack slots satisfy their alignment r...
static bool CC_ARM_AAPCS_VFP_Custom_f16(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
static bool f64AssignAPCS(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, CCState &State, bool CanFail)
static const MCPhysReg SRegList[]
size_t size() const
size - Get the array size.
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...