#include "llvm/Support/MachineValueType.h"
Public Types | |
| enum | SimpleValueType : uint8_t { INVALID_SIMPLE_VALUE_TYPE = 0 , Other = 1 , i1 = 2 , i2 = 3 , i4 = 4 , i8 = 5 , i16 = 6 , i32 = 7 , i64 = 8 , i128 = 9 , FIRST_INTEGER_VALUETYPE = i1 , LAST_INTEGER_VALUETYPE = i128 , bf16 = 10 , f16 = 11 , f32 = 12 , f64 = 13 , f80 = 14 , f128 = 15 , ppcf128 = 16 , FIRST_FP_VALUETYPE = bf16 , LAST_FP_VALUETYPE = ppcf128 , v1i1 = 17 , v2i1 = 18 , v4i1 = 19 , v8i1 = 20 , v16i1 = 21 , v32i1 = 22 , v64i1 = 23 , v128i1 = 24 , v256i1 = 25 , v512i1 = 26 , v1024i1 = 27 , v2048i1 = 28 , v128i2 = 29 , v256i2 = 30 , v64i4 = 31 , v128i4 = 32 , v1i8 = 33 , v2i8 = 34 , v4i8 = 35 , v8i8 = 36 , v16i8 = 37 , v32i8 = 38 , v64i8 = 39 , v128i8 = 40 , v256i8 = 41 , v512i8 = 42 , v1024i8 = 43 , v1i16 = 44 , v2i16 = 45 , v3i16 = 46 , v4i16 = 47 , v8i16 = 48 , v16i16 = 49 , v32i16 = 50 , v64i16 = 51 , v128i16 = 52 , v256i16 = 53 , v512i16 = 54 , v1i32 = 55 , v2i32 = 56 , v3i32 = 57 , v4i32 = 58 , v5i32 = 59 , v6i32 = 60 , v7i32 = 61 , v8i32 = 62 , v9i32 = 63 , v10i32 = 64 , v11i32 = 65 , v12i32 = 66 , v16i32 = 67 , v32i32 = 68 , v64i32 = 69 , v128i32 = 70 , v256i32 = 71 , v512i32 = 72 , v1024i32 = 73 , v2048i32 = 74 , v1i64 = 75 , v2i64 = 76 , v3i64 = 77 , v4i64 = 78 , v8i64 = 79 , v16i64 = 80 , v32i64 = 81 , v64i64 = 82 , v128i64 = 83 , v256i64 = 84 , v1i128 = 85 , FIRST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE = v1i1 , LAST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE = v1i128 , v1f16 = 86 , v2f16 = 87 , v3f16 = 88 , v4f16 = 89 , v8f16 = 90 , v16f16 = 91 , v32f16 = 92 , v64f16 = 93 , v128f16 = 94 , v256f16 = 95 , v512f16 = 96 , v2bf16 = 97 , v3bf16 = 98 , v4bf16 = 99 , v8bf16 = 100 , v16bf16 = 101 , v32bf16 = 102 , v64bf16 = 103 , v128bf16 = 104 , v1f32 = 105 , v2f32 = 106 , v3f32 = 107 , v4f32 = 108 , v5f32 = 109 , v6f32 = 110 , v7f32 = 111 , v8f32 = 112 , v9f32 = 113 , v10f32 = 114 , v11f32 = 115 , v12f32 = 116 , v16f32 = 117 , v32f32 = 118 , v64f32 = 119 , v128f32 = 120 , v256f32 = 121 , v512f32 = 122 , v1024f32 = 123 , v2048f32 = 124 , v1f64 = 125 , v2f64 = 126 , v3f64 = 127 , v4f64 = 128 , v8f64 = 129 , v16f64 = 130 , v32f64 = 131 , v64f64 = 132 , v128f64 = 133 , v256f64 = 134 , FIRST_FP_FIXEDLEN_VECTOR_VALUETYPE = v1f16 , LAST_FP_FIXEDLEN_VECTOR_VALUETYPE = v256f64 , FIRST_FIXEDLEN_VECTOR_VALUETYPE = v1i1 , LAST_FIXEDLEN_VECTOR_VALUETYPE = v256f64 , nxv1i1 = 135 , nxv2i1 = 136 , nxv4i1 = 137 , nxv8i1 = 138 , nxv16i1 = 139 , nxv32i1 = 140 , nxv64i1 = 141 , nxv1i8 = 142 , nxv2i8 = 143 , nxv4i8 = 144 , nxv8i8 = 145 , nxv16i8 = 146 , nxv32i8 = 147 , nxv64i8 = 148 , nxv1i16 = 149 , nxv2i16 = 150 , nxv4i16 = 151 , nxv8i16 = 152 , nxv16i16 = 153 , nxv32i16 = 154 , nxv1i32 = 155 , nxv2i32 = 156 , nxv4i32 = 157 , nxv8i32 = 158 , nxv16i32 = 159 , nxv32i32 = 160 , nxv1i64 = 161 , nxv2i64 = 162 , nxv4i64 = 163 , nxv8i64 = 164 , nxv16i64 = 165 , nxv32i64 = 166 , FIRST_INTEGER_SCALABLE_VECTOR_VALUETYPE = nxv1i1 , LAST_INTEGER_SCALABLE_VECTOR_VALUETYPE = nxv32i64 , nxv1f16 = 167 , nxv2f16 = 168 , nxv4f16 = 169 , nxv8f16 = 170 , nxv16f16 = 171 , nxv32f16 = 172 , nxv1bf16 = 173 , nxv2bf16 = 174 , nxv4bf16 = 175 , nxv8bf16 = 176 , nxv16bf16 = 177 , nxv32bf16 = 178 , nxv1f32 = 179 , nxv2f32 = 180 , nxv4f32 = 181 , nxv8f32 = 182 , nxv16f32 = 183 , nxv1f64 = 184 , nxv2f64 = 185 , nxv4f64 = 186 , nxv8f64 = 187 , FIRST_FP_SCALABLE_VECTOR_VALUETYPE = nxv1f16 , LAST_FP_SCALABLE_VECTOR_VALUETYPE = nxv8f64 , FIRST_SCALABLE_VECTOR_VALUETYPE = nxv1i1 , LAST_SCALABLE_VECTOR_VALUETYPE = nxv8f64 , FIRST_VECTOR_VALUETYPE = v1i1 , LAST_VECTOR_VALUETYPE = nxv8f64 , x86mmx = 188 , Glue = 189 , isVoid = 190 , Untyped = 191 , funcref = 192 , externref = 193 , x86amx = 194 , i64x8 = 195 , aarch64svcount = 196 , spirvbuiltin = 197 , FIRST_VALUETYPE = 1 , LAST_VALUETYPE = spirvbuiltin , VALUETYPE_SIZE = LAST_VALUETYPE + 1 , MAX_ALLOWED_VALUETYPE = 224 , token = 248 , Metadata = 249 , iPTRAny = 250 , vAny = 251 , fAny = 252 , iAny = 253 , iPTR = 254 , Any = 255 } |
Public Member Functions | |
| constexpr | MVT ()=default |
| constexpr | MVT (SimpleValueType SVT) |
| bool | operator> (const MVT &S) const |
| bool | operator< (const MVT &S) const |
| bool | operator== (const MVT &S) const |
| bool | operator!= (const MVT &S) const |
| bool | operator>= (const MVT &S) const |
| bool | operator<= (const MVT &S) const |
| void | dump () const |
| Support for debugging, callable in GDB: VT.dump() | |
| void | print (raw_ostream &OS) const |
| Implement operator<<. | |
| bool | isValid () const |
| Return true if this is a valid simple valuetype. | |
| bool | isFloatingPoint () const |
| Return true if this is a FP or a vector FP type. | |
| bool | isInteger () const |
| Return true if this is an integer or a vector integer type. | |
| bool | isScalarInteger () const |
| Return true if this is an integer, not including vectors. | |
| bool | isVector () const |
| Return true if this is a vector value type. | |
| bool | isScalableVector () const |
| Return true if this is a vector value type where the runtime length is machine dependent. | |
| bool | isScalableTargetExtVT () const |
| Return true if this is a custom target type that has a scalable size. | |
| bool | isScalableVT () const |
| Return true if the type is a scalable type. | |
| bool | isFixedLengthVector () const |
| bool | is16BitVector () const |
| Return true if this is a 16-bit vector type. | |
| bool | is32BitVector () const |
| Return true if this is a 32-bit vector type. | |
| bool | is64BitVector () const |
| Return true if this is a 64-bit vector type. | |
| bool | is128BitVector () const |
| Return true if this is a 128-bit vector type. | |
| bool | is256BitVector () const |
| Return true if this is a 256-bit vector type. | |
| bool | is512BitVector () const |
| Return true if this is a 512-bit vector type. | |
| bool | is1024BitVector () const |
| Return true if this is a 1024-bit vector type. | |
| bool | is2048BitVector () const |
| Return true if this is a 2048-bit vector type. | |
| bool | isOverloaded () const |
| Return true if this is an overloaded type for TableGen. | |
| MVT | changeVectorElementTypeToInteger () const |
| Return a vector with the same number of elements as this vector, but with the element type converted to an integer type with the same bitwidth. | |
| MVT | changeVectorElementType (MVT EltVT) const |
| Return a VT for a vector type whose attributes match ourselves with the exception of the element type that is chosen by the caller. | |
| MVT | changeTypeToInteger () |
| Return the type converted to an equivalently sized integer or vector with integer element type. | |
| MVT | getHalfNumVectorElementsVT () const |
| Return a VT for a vector type with the same element type but half the number of elements. | |
| bool | isPow2VectorType () const |
| Returns true if the given vector is a power of 2. | |
| MVT | getPow2VectorType () const |
| Widens the length of the given vector MVT up to the nearest power of 2 and returns that type. | |
| MVT | getScalarType () const |
| If this is a vector, return the element type, otherwise return this. | |
| MVT | getVectorElementType () const |
| unsigned | getVectorMinNumElements () const |
| Given a vector type, return the minimum number of elements it contains. | |
| ElementCount | getVectorElementCount () const |
| unsigned | getVectorNumElements () const |
| TypeSize | getSizeInBits () const |
| Returns the size of the specified MVT in bits. | |
| uint64_t | getFixedSizeInBits () const |
| Return the size of the specified fixed width value type in bits. | |
| uint64_t | getScalarSizeInBits () const |
| TypeSize | getStoreSize () const |
| Return the number of bytes overwritten by a store of the specified value type. | |
| uint64_t | getScalarStoreSize () const |
| TypeSize | getStoreSizeInBits () const |
| Return the number of bits overwritten by a store of the specified value type. | |
| bool | isByteSized () const |
| Returns true if the number of bits for the type is a multiple of an 8-bit byte. | |
| bool | knownBitsGT (MVT VT) const |
| Return true if we know at compile time this has more bits than VT. | |
| bool | knownBitsGE (MVT VT) const |
| Return true if we know at compile time this has more than or the same bits as VT. | |
| bool | knownBitsLT (MVT VT) const |
| Return true if we know at compile time this has fewer bits than VT. | |
| bool | knownBitsLE (MVT VT) const |
| Return true if we know at compile time this has fewer than or the same bits as VT. | |
| bool | bitsGT (MVT VT) const |
| Return true if this has more bits than VT. | |
| bool | bitsGE (MVT VT) const |
| Return true if this has no less bits than VT. | |
| bool | bitsLT (MVT VT) const |
| Return true if this has less bits than VT. | |
| bool | bitsLE (MVT VT) const |
| Return true if this has no more bits than VT. | |
Static Public Member Functions | |
| static MVT | getFloatingPointVT (unsigned BitWidth) |
| static MVT | getIntegerVT (unsigned BitWidth) |
| static MVT | getVectorVT (MVT VT, unsigned NumElements) |
| static MVT | getScalableVectorVT (MVT VT, unsigned NumElements) |
| static MVT | getVectorVT (MVT VT, unsigned NumElements, bool IsScalable) |
| static MVT | getVectorVT (MVT VT, ElementCount EC) |
| static MVT | getVT (Type *Ty, bool HandleUnknown=false) |
| Return the value type corresponding to the specified type. | |
| static auto | all_valuetypes () |
| SimpleValueType Iteration. | |
| static auto | integer_valuetypes () |
| static auto | fp_valuetypes () |
| static auto | vector_valuetypes () |
| static auto | fixedlen_vector_valuetypes () |
| static auto | scalable_vector_valuetypes () |
| static auto | integer_fixedlen_vector_valuetypes () |
| static auto | fp_fixedlen_vector_valuetypes () |
| static auto | integer_scalable_vector_valuetypes () |
| static auto | fp_scalable_vector_valuetypes () |
Public Attributes | |
| SimpleValueType | SimpleTy = INVALID_SIMPLE_VALUE_TYPE |
Detailed Description
Every type that is supported natively by some processor targeted by LLVM occurs here. This means that any legal value type can be represented by an MVT.
Definition at line 31 of file MachineValueType.h.
Member Enumeration Documentation
◆ SimpleValueType
| enum llvm::MVT::SimpleValueType : uint8_t |
Definition at line 33 of file MachineValueType.h.
Constructor & Destructor Documentation
◆ MVT() [1/2]
|
constexprdefault |
Referenced by getVT().
◆ MVT() [2/2]
|
inlineconstexpr |
Definition at line 346 of file MachineValueType.h.
Member Function Documentation
◆ all_valuetypes()
|
inlinestatic |
SimpleValueType Iteration.
Definition at line 1535 of file MachineValueType.h.
References llvm::enum_seq_inclusive(), FIRST_VALUETYPE, llvm::force_iteration_on_noniterable_enum, and LAST_VALUETYPE.
Referenced by llvm::TargetLoweringBase::initActions().
◆ bitsGE()
Return true if this has no less bits than VT.
Definition at line 1224 of file MachineValueType.h.
References assert(), isScalableVector(), and knownBitsGE().
◆ bitsGT()
Return true if this has more bits than VT.
Definition at line 1217 of file MachineValueType.h.
References assert(), isScalableVector(), and knownBitsGT().
Referenced by LowerFCOPYSIGN(), and lowerVECTOR_SHUFFLE().
◆ bitsLE()
Return true if this has no more bits than VT.
Definition at line 1238 of file MachineValueType.h.
References assert(), isScalableVector(), and knownBitsLE().
Referenced by getMaskNode(), llvm::SITargetLowering::getPreferredVectorAction(), lowerBUILD_VECTOR(), lowerReductionSeq(), and lowerScalarInsert().
◆ bitsLT()
Return true if this has less bits than VT.
Definition at line 1231 of file MachineValueType.h.
References assert(), isScalableVector(), and knownBitsLT().
Referenced by LowerFCOPYSIGN(), lowerVectorIntrinsicScalars(), and selectVSplatSimmHelper().
◆ changeTypeToInteger()
|
inline |
Return the type converted to an equivalently sized integer or vector with integer element type.
Similar to changeVectorElementTypeToInteger, but also handles scalars.
Definition at line 522 of file MachineValueType.h.
References changeVectorElementTypeToInteger(), getIntegerVT(), getSizeInBits(), and isVector().
Referenced by llvm::EVT::changeTypeToInteger(), getWideningInterleave(), lowerShuffleWithPERMV(), lowerVECTOR_SHUFFLE(), and matchBinaryShuffle().
◆ changeVectorElementType()
Return a VT for a vector type whose attributes match ourselves with the exception of the element type that is chosen by the caller.
Definition at line 512 of file MachineValueType.h.
References assert(), getVectorElementCount(), getVectorVT(), INVALID_SIMPLE_VALUE_TYPE, and SimpleTy.
Referenced by llvm::EVT::changeVectorElementType(), lowerBUILD_VECTOR(), lowerFP_TO_INT_SAT(), lowerVECTOR_SHUFFLE(), matchUnaryShuffle(), promoteXINT_TO_FP(), and widenVectorOpsToi8().
◆ changeVectorElementTypeToInteger()
|
inline |
Return a vector with the same number of elements as this vector, but with the element type converted to an integer type with the same bitwidth.
Definition at line 501 of file MachineValueType.h.
References assert(), getIntegerVT(), getSizeInBits(), getVectorElementCount(), getVectorElementType(), getVectorVT(), INVALID_SIMPLE_VALUE_TYPE, and SimpleTy.
Referenced by changeTypeToInteger(), llvm::EVT::changeVectorElementTypeToInteger(), getDeinterleaveViaVNSRL(), lowerBUILD_VECTOR(), LowerBUILD_VECTORvXbf16(), and lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND().
◆ dump()
| void MVT::dump | ( | ) | const |
Support for debugging, callable in GDB: VT.dump()
Definition at line 632 of file ValueTypes.cpp.
References llvm::dbgs(), and print().
◆ fixedlen_vector_valuetypes()
|
inlinestatic |
Definition at line 1557 of file MachineValueType.h.
References llvm::enum_seq_inclusive(), FIRST_FIXEDLEN_VECTOR_VALUETYPE, llvm::force_iteration_on_noniterable_enum, and LAST_FIXEDLEN_VECTOR_VALUETYPE.
Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering(), llvm::ARMTargetLowering::ARMTargetLowering(), llvm::HexagonTargetLowering::HexagonTargetLowering(), llvm::MipsSETargetLowering::MipsSETargetLowering(), llvm::NVPTXTargetLowering::NVPTXTargetLowering(), llvm::PPCTargetLowering::PPCTargetLowering(), llvm::SystemZTargetLowering::SystemZTargetLowering(), llvm::WebAssemblyTargetLowering::WebAssemblyTargetLowering(), and llvm::X86TargetLowering::X86TargetLowering().
◆ fp_fixedlen_vector_valuetypes()
|
inlinestatic |
Definition at line 1575 of file MachineValueType.h.
References llvm::enum_seq_inclusive(), FIRST_FP_FIXEDLEN_VECTOR_VALUETYPE, llvm::force_iteration_on_noniterable_enum, and LAST_FP_FIXEDLEN_VECTOR_VALUETYPE.
Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering(), llvm::MipsTargetLowering::MipsTargetLowering(), and llvm::RISCVTargetLowering::RISCVTargetLowering().
◆ fp_scalable_vector_valuetypes()
|
inlinestatic |
Definition at line 1587 of file MachineValueType.h.
References llvm::enum_seq_inclusive(), FIRST_FP_SCALABLE_VECTOR_VALUETYPE, llvm::force_iteration_on_noniterable_enum, and LAST_FP_SCALABLE_VECTOR_VALUETYPE.
◆ fp_valuetypes()
|
inlinestatic |
Definition at line 1546 of file MachineValueType.h.
References llvm::enum_seq_inclusive(), FIRST_FP_VALUETYPE, llvm::force_iteration_on_noniterable_enum, and LAST_FP_VALUETYPE.
Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering(), llvm::ARMTargetLowering::ARMTargetLowering(), llvm::HexagonTargetLowering::HexagonTargetLowering(), llvm::TargetLoweringBase::initActions(), llvm::MipsTargetLowering::MipsTargetLowering(), llvm::PPCTargetLowering::PPCTargetLowering(), llvm::SparcTargetLowering::SparcTargetLowering(), and llvm::SystemZTargetLowering::SystemZTargetLowering().
◆ getFixedSizeInBits()
|
inline |
Return the size of the specified fixed width value type in bits.
The function will assert if the type is scalable.
Definition at line 1155 of file MachineValueType.h.
References llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getFixedValue(), and getSizeInBits().
Referenced by CC_AIX(), combineINSERT_SUBVECTOR(), combineTargetShuffle(), llvm::TargetLoweringBase::computeRegisterProperties(), getCopyToPartsVector(), llvm::MipsTargetLowering::getVectorTypeBreakdownForCallingConv(), LowerEXTEND_VECTOR_INREG(), LowerVSETCC(), MatchingStackOffset(), truncateScalarIntegerArg(), useRVVForFixedLengthVectorVT(), and widenSubVector().
◆ getFloatingPointVT()
Definition at line 1244 of file MachineValueType.h.
References llvm::BitWidth, f128, f16, f32, f64, f80, and llvm_unreachable.
Referenced by combineBitcast(), combineCVTP2I_CVTTP2I(), combinePredicateReduction(), combineX86ShuffleChain(), combineX86ShufflesConstants(), EltsFromConsecutiveLoads(), llvm::EVT::getFloatingPointVT(), lower256BitShuffle(), lowerVECTOR_SHUFFLE(), and tryWidenMaskForShuffle().
◆ getHalfNumVectorElementsVT()
|
inline |
Return a VT for a vector type with the same element type but half the number of elements.
Definition at line 530 of file MachineValueType.h.
References assert(), getVectorElementCount(), getVectorElementType(), and getVectorVT().
Referenced by combineSetCCMOVMSK(), combineTargetShuffle(), llvm::RISCVTargetLowering::decomposeSubvectorInsertExtractToSubRegs(), getHopForBuildVector(), getShuffleHalfVectors(), LowerAVXCONCAT_VECTORS(), LowerAVXExtend(), LowerCONCAT_VECTORSvXi1(), LowerEXTEND_VECTOR_INREG(), lowerShuffleWithUndefHalf(), LowerSIGN_EXTEND(), lowerV2X128Shuffle(), and lowerVECTOR_SHUFFLE().
◆ getIntegerVT()
Definition at line 1261 of file MachineValueType.h.
References llvm::BitWidth, i1, i128, i16, i2, i32, i4, i64, i8, and INVALID_SIMPLE_VALUE_TYPE.
Referenced by changeTypeToInteger(), changeVectorElementTypeToInteger(), combineBitcast(), combineConcatVectorOps(), combineX86INT_TO_FP(), combineX86ShuffleChain(), combineX86ShufflesConstants(), llvm::computeSignatureVTs(), EltsFromConsecutiveLoads(), ExtractBitFromMaskVector(), getDeinterleaveViaVNSRL(), llvm::EVT::getIntegerVT(), llvm::getMVTForLLT(), getPermuteNode(), llvm::TargetLoweringBase::getPointerMemTy(), llvm::TargetLoweringBase::getPointerTy(), llvm::AArch64TargetLowering::getPointerTy(), getRegistersForValue(), llvm::TargetLoweringBase::getScalarShiftAmountTy(), llvm::M68kTargetLowering::getScalarShiftAmountTy(), llvm::ARMTargetLowering::getTgtMemIntrinsic(), llvm::SPIRVTargetLowering::getVectorIdxTy(), getVT(), getWideningInterleave(), llvm::TargetLoweringBase::hasFastEqualityCompare(), llvm::X86TargetLowering::hasFastEqualityCompare(), llvm::TargetLoweringBase::initActions(), insert1BitVector(), InsertBitToMaskVector(), is128BitUnpackShuffleMask(), llvm::SystemZVectorConstantInfo::isVectorConstantLegal(), lowerBUILD_VECTOR(), LowerBUILD_VECTORvXi1(), lowerBuildVectorAsBroadcast(), LowerCTPOP(), lowerFCOPYSIGN64(), LowerFunnelShift(), llvm::RISCVTargetLowering::LowerOperation(), LowerRotate(), llvm::HexagonTargetLowering::LowerSETCC(), lowerShuffleAsBlend(), lowerShuffleAsPermuteAndUnpack(), lowerShuffleAsSpecificZeroOrAnyExtend(), lowerShuffleAsVTRUNC(), lowerShuffleToEXPAND(), lowerShuffleWithPACK(), lowerShuffleWithVPMOV(), LowerTruncateVecI1(), llvm::HexagonTargetLowering::LowerUnalignedLoad(), lowerVECTOR_SHUFFLE(), LowerVECTOR_SHUFFLE(), LowerVectorCTLZInRegLUT(), llvm::HexagonTargetLowering::LowerVSELECT(), lowerX86FPLogicOp(), matchShuffleAsBitRotate(), matchShuffleAsShift(), matchShuffleAsVTRUNC(), matchShuffleWithPACK(), matchUnaryPermuteShuffle(), matchUnaryShuffle(), memsetStore(), PerformVECREDUCE_ADDCombine(), PerformVQDMULHCombine(), llvm::X86TargetLowering::ReplaceNodeResults(), scaleVectorType(), llvm::AArch64TargetLowering::shouldTransformSignedTruncationCheck(), llvm::X86TargetLowering::shouldTransformSignedTruncationCheck(), ShrinkLoadReplaceStoreWithStore(), llvm::X86TargetLowering::SimplifyDemandedBitsForTargetNode(), skipExtensionForVectorMULL(), SkipExtensionForVMULL(), llvm::SparcTargetLowering::SparcTargetLowering(), llvm::HexagonDAGToDAGISel::StoreInstrForLoadIntrinsic(), llvm::SystemZTargetLowering::SystemZTargetLowering(), TryCombineBaseUpdate(), tryWidenMaskForShuffle(), unpackFromMemLoc(), and llvm::X86TargetLowering::X86TargetLowering().
◆ getPow2VectorType()
|
inline |
Widens the length of the given vector MVT up to the nearest power of 2 and returns that type.
Definition at line 545 of file MachineValueType.h.
References llvm::ElementCount::get(), llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getKnownMinValue(), getVectorElementCount(), getVectorElementType(), getVectorVT(), isPow2VectorType(), llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::isScalable(), and llvm::Log2_32_Ceil().
Referenced by llvm::TargetLoweringBase::computeRegisterProperties().
◆ getScalableVectorVT()
Definition at line 1436 of file MachineValueType.h.
References bf16, f16, f32, f64, i1, i16, i32, i64, i8, INVALID_SIMPLE_VALUE_TYPE, nxv16bf16, nxv16f16, nxv16f32, nxv16i1, nxv16i16, nxv16i32, nxv16i64, nxv16i8, nxv1bf16, nxv1f16, nxv1f32, nxv1f64, nxv1i1, nxv1i16, nxv1i32, nxv1i64, nxv1i8, nxv2bf16, nxv2f16, nxv2f32, nxv2f64, nxv2i1, nxv2i16, nxv2i32, nxv2i64, nxv2i8, nxv32bf16, nxv32f16, nxv32i1, nxv32i16, nxv32i32, nxv32i64, nxv32i8, nxv4bf16, nxv4f16, nxv4f32, nxv4f64, nxv4i1, nxv4i16, nxv4i32, nxv4i64, nxv4i8, nxv64i1, nxv64i8, nxv8bf16, nxv8f16, nxv8f32, nxv8f64, nxv8i1, nxv8i16, nxv8i32, nxv8i64, nxv8i8, and SimpleTy.
Referenced by getContainerForFixedLengthVector(), getLMUL1VT(), and getVectorVT().
◆ getScalarSizeInBits()
|
inline |
Definition at line 1159 of file MachineValueType.h.
References llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getFixedValue(), getScalarType(), and getSizeInBits().
Referenced by canonicalizeBitSelect(), CC_RISCV(), CC_RISCV_FastCC(), combineAddOfPMADDWD(), combineAndnp(), combineConcatVectorOps(), combineCVTP2I_CVTTP2I(), combineMOVMSK(), combineSetCCMOVMSK(), combineStore(), combineTargetShuffle(), combineVEXTRACT_STORE(), combineX86INT_TO_FP(), combineX86ShuffleChain(), llvm::X86TargetLowering::ComputeNumSignBitsForTargetNode(), llvm::TargetLoweringBase::computeRegisterProperties(), createPackShuffleMask(), createVariablePermute(), DecodePALIGNRMask(), expandFP_TO_UINT_SSE(), llvm::X86TTIImpl::getArithmeticReductionCost(), getAVX512Node(), getAVX512TruncNode(), llvm::X86TTIImpl::getCmpSelInstrCost(), getConstantVector(), getConstVector(), llvm::RegsForValue::getCopyFromRegs(), getDeinterleaveViaVNSRL(), getFauxShuffleMask(), llvm::AArch64TTIImpl::getIntrinsicInstrCost(), getMemCmpLoad(), llvm::X86TTIImpl::getMinMaxReductionCost(), getPack(), llvm::PPCTargetLowering::getPreferredVectorAction(), llvm::SystemZTargetLowering::getPreferredVectorAction(), getPSHUFShuffleMask(), llvm::X86TTIImpl::getReplicationShuffleCost(), getScalarValueForVectorElement(), llvm::RISCVTTIImpl::getShuffleCost(), getTargetShuffleMask(), getTargetVShiftNode(), getVectorTypeBreakdownMVT(), getWideningInterleave(), is128BitLaneCrossingShuffleMask(), isDeinterleaveShuffle(), isHorizontalBinOp(), isInterleaveShuffle(), isRepeatedShuffleMask(), isRepeatedTargetShuffleMask(), lower256BitShuffle(), LowerADDSAT_SUBSAT(), LowerBITREVERSE_XOP(), lowerBUILD_VECTOR(), lowerBuildVectorAsBroadcast(), lowerBuildVectorToBitOp(), LowerCTTZ(), LowerEXTEND_VECTOR_INREG(), LowerFABSorFNEG(), LowerFCOPYSIGN(), LowerFunnelShift(), LowerINTRINSIC_W_CHAIN(), LowerMGATHER(), LowerMLOAD(), LowerMSCATTER(), LowerMSTORE(), LowerRotate(), LowerShift(), LowerShiftByScalarImmediate(), lowerShuffleAsBitRotate(), lowerShuffleAsBlend(), lowerShuffleAsBlendAndPermute(), lowerShuffleAsBroadcast(), lowerShuffleAsByteRotateAndPermute(), lowerShuffleAsByteShiftMask(), lowerShuffleAsDecomposedShuffleMerge(), lowerShuffleAsLanePermuteAndRepeatedMask(), lowerShuffleAsPermuteAndUnpack(), lowerShuffleAsRepeatedMaskAndLanePermute(), lowerShuffleAsShift(), lowerShuffleAsSpecificZeroOrAnyExtend(), lowerShuffleAsVTRUNC(), lowerShuffleAsZeroOrAnyExtend(), lowerShuffleOfExtractsAsVperm(), lowerShuffleWithPACK(), lowerShuffleWithPSHUFB(), lowerShuffleWithVPMOV(), LowerTruncateVecI1(), lowerV4X128Shuffle(), lowerVECTOR_SHUFFLE(), LowerVectorCTLZInRegLUT(), lowerVectorIntrinsicScalars(), LowerVSETCC(), lowerX86FPLogicOp(), LowerZERO_EXTEND_Mask(), matchBinaryPermuteShuffle(), matchBinaryShuffle(), matchShuffleAsBlend(), matchShuffleAsEXTRQ(), matchShuffleAsINSERTQ(), matchShuffleAsVTRUNC(), matchShuffleWithPACK(), matchShuffleWithSHUFPD(), matchUnaryPermuteShuffle(), matchUnaryShuffle(), llvm::X86::mayFoldLoadIntoBroadcastFromMem(), performFP_TO_INTCombine(), PerformVQDMULHCombine(), scaleVectorType(), llvm::RISCVDAGToDAGISel::Select(), llvm::RISCVDAGToDAGISel::selectVLSEG(), llvm::RISCVDAGToDAGISel::selectVLSEGFF(), llvm::RISCVDAGToDAGISel::selectVLXSEG(), llvm::RISCVDAGToDAGISel::selectVSSEG(), llvm::RISCVDAGToDAGISel::selectVSXSEG(), llvm::X86TargetLowering::SimplifyDemandedBitsForTargetNode(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), supportedVectorShiftWithImm(), supportedVectorVarShift(), and vectorizeExtractedCast().
◆ getScalarStoreSize()
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Definition at line 1176 of file MachineValueType.h.
References llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getFixedValue(), getScalarType(), and getStoreSize().
◆ getScalarType()
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If this is a vector, return the element type, otherwise return this.
Definition at line 556 of file MachineValueType.h.
References getVectorElementType(), and isVector().
Referenced by llvm::AMDGPUTargetLowering::analyzeFormalArgumentsCompute(), canCombineAsMaskOperation(), combineConcatVectorOps(), combineEXTRACT_SUBVECTOR(), combineMOVMSK(), combineStore(), combineTargetShuffle(), combineVectorSignBitsTruncation(), constructDup(), createVariablePermute(), llvm::TargetLowering::expandBSWAP(), llvm::TargetLowering::expandVPBSWAP(), llvm::X86TTIImpl::getArithmeticReductionCost(), getAVX512Node(), getAVX512TruncNode(), getFauxShuffleMask(), getIEEEProperties(), llvm::SITargetLowering::getPreferredVectorAction(), llvm::NVPTXTargetLowering::getPreferredVectorAction(), llvm::X86TTIImpl::getReplicationShuffleCost(), getScalarSizeInBits(), getScalarStoreSize(), getTargetShuffleMask(), getTargetVShiftNode(), isInlineableLiteralOp16(), llvm::X86TargetLowering::isShuffleMaskLegal(), LowerBITREVERSE(), lowerBuildVectorAsBroadcast(), lowerBuildVectorToBitOp(), LowerMLOAD(), LowerMSTORE(), lowerShuffleAsBroadcast(), lowerShuffleAsVALIGN(), lowerShuffleAsVTRUNC(), llvm::AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(), lowerVECTOR_SHUFFLE(), LowerVectorCTPOP(), matchUnaryShuffle(), scalarizeVectorStore(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), vectorizeExtractedCast(), and widenSubVector().
◆ getSizeInBits()
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Returns the size of the specified MVT in bits.
If the value type is a scalable vector type, the scalable property will be set and the runtime size will be a positive integer multiple of the base size.
Definition at line 937 of file MachineValueType.h.
References aarch64svcount, Any, bf16, externref, f128, f16, f32, f64, f80, fAny, llvm::TypeSize::Fixed(), funcref, i1, i128, i16, i2, i32, i4, i64, i64x8, i8, iAny, iPTR, iPTRAny, llvm_unreachable, Metadata, nxv16bf16, nxv16f16, nxv16f32, nxv16i1, nxv16i16, nxv16i32, nxv16i64, nxv16i8, nxv1bf16, nxv1f16, nxv1f32, nxv1f64, nxv1i1, nxv1i16, nxv1i32, nxv1i64, nxv1i8, nxv2bf16, nxv2f16, nxv2f32, nxv2f64, nxv2i1, nxv2i16, nxv2i32, nxv2i64, nxv2i8, nxv32bf16, nxv32f16, nxv32i1, nxv32i16, nxv32i32, nxv32i64, nxv32i8, nxv4bf16, nxv4f16, nxv4f32, nxv4f64, nxv4i1, nxv4i16, nxv4i32, nxv4i64, nxv4i8, nxv64i1, nxv64i8, nxv8bf16, nxv8f16, nxv8f32, nxv8f64, nxv8i1, nxv8i16, nxv8i32, nxv8i64, nxv8i8, Other, ppcf128, llvm::details::FixedOrScalableQuantity< TypeSize, uint64_t >::Scalable, SimpleTy, spirvbuiltin, token, v1024f32, v1024i1, v1024i32, v1024i8, v10f32, v10i32, v11f32, v11i32, v128bf16, v128f16, v128f32, v128f64, v128i1, v128i16, v128i2, v128i32, v128i4, v128i64, v128i8, v12f32, v12i32, v16bf16, v16f16, v16f32, v16f64, v16i1, v16i16, v16i32, v16i64, v16i8, v1f16, v1f32, v1f64, v1i1, v1i128, v1i16, v1i32, v1i64, v1i8, v2048f32, v2048i1, v2048i32, v256f16, v256f32, v256f64, v256i1, v256i16, v256i2, v256i32, v256i64, v256i8, v2bf16, v2f16, v2f32, v2f64, v2i1, v2i16, v2i32, v2i64, v2i8, v32bf16, v32f16, v32f32, v32f64, v32i1, v32i16, v32i32, v32i64, v32i8, v3bf16, v3f16, v3f32, v3f64, v3i16, v3i32, v3i64, v4bf16, v4f16, v4f32, v4f64, v4i1, v4i16, v4i32, v4i64, v4i8, v512f16, v512f32, v512i1, v512i16, v512i32, v512i8, v5f32, v5i32, v64bf16, v64f16, v64f32, v64f64, v64i1, v64i16, v64i32, v64i4, v64i64, v64i8, v6f32, v6i32, v7f32, v7i32, v8bf16, v8f16, v8f32, v8f64, v8i1, v8i16, v8i32, v8i64, v8i8, v9f32, v9i32, vAny, x86amx, and x86mmx.
Referenced by Analyze_CC_Sparc64_Full(), Analyze_CC_Sparc64_Half(), canCombineAsMaskOperation(), canonicalizeBitSelect(), CC_ARM_AAPCS_Custom_Aggregate(), CC_X86_32_VectorCall(), CC_X86_64_VectorCall(), changeTypeToInteger(), changeVectorElementTypeToInteger(), combineAndLoadToBZHI(), combineEXTRACT_SUBVECTOR(), combinePredicateReduction(), combineSetCCMOVMSK(), combineShiftRightArithmetic(), combineTargetShuffle(), combineVectorHADDSUB(), combineVectorSignBitsTruncation(), combineX86ShuffleChain(), combineX86ShufflesConstants(), combineX86ShufflesRecursively(), convertShiftLeftToScale(), createPackShuffleMask(), createShuffleStride(), createVariablePermute(), createVPDPBUSD(), DecodePALIGNRMask(), llvm::TargetLowering::expandUnalignedLoad(), llvm::TargetLowering::expandUnalignedStore(), llvm::FastISel::fastEmit_ri_(), finishStackBlock(), genShuffleBland(), getAVX512Node(), getAVX512TruncNode(), getCopyFromParts(), getCopyFromPartsVector(), getCopyToParts(), getCopyToPartsVector(), getFauxShuffleMask(), getFixedSizeInBits(), getFltSemantics(), getHopForBuildVector(), llvm::getLLTForMVT(), llvm::RISCVTargetLowering::getLMUL(), getLMUL1VT(), llvm::TargetLoweringBase::getNumRegisters(), getPack(), llvm::HvxSelector::getPairVT(), llvm::PPCTargetLowering::getPreferredVectorAction(), getPromotedVectorElementType(), getPSHUFShuffleMask(), llvm::SITargetLowering::getRegForInlineAsmConstraint(), llvm::ARMTargetLowering::getRegForInlineAsmConstraint(), llvm::HexagonTargetLowering::getRegForInlineAsmConstraint(), llvm::SystemZTargetLowering::getRegForInlineAsmConstraint(), llvm::X86TargetLowering::getRegForInlineAsmConstraint(), getRegistersForValue(), llvm::RegsForValue::getRegsAndSizes(), getScalarSizeInBits(), getScalarValueForVectorElement(), llvm::X86TargetLowering::getSetCCResultType(), llvm::TargetLoweringBase::getShiftAmountTy(), llvm::X86TTIImpl::getShuffleCost(), llvm::HvxSelector::getSingleVT(), getStoreSize(), getTargetShuffleAndZeroables(), getTargetVShiftByConstNode(), getTargetVShiftNode(), llvm::HexagonSubtarget::getTypeAlignment(), llvm::TargetLoweringBase::getVaListSizeInBits(), llvm::AArch64TargetLowering::getVaListSizeInBits(), llvm::TargetLoweringBase::getVectorTypeBreakdown(), llvm::MipsTargetLowering::getVectorTypeBreakdownForCallingConv(), getZeroVector(), group2Shuffle(), hasBZHI(), insert1BitVector(), isByteSized(), IsElementEquivalent(), isHorizontalBinOp(), llvm::X86TargetLowering::isShuffleMaskLegal(), isSupportedType(), isTargetShuffleEquivalent(), llvm::RISCVTargetLowering::joinRegisterPartsIntoValue(), knownBitsGE(), knownBitsGT(), knownBitsLE(), knownBitsLT(), llvm::LLT::LLT(), llvm::X86TargetLowering::LowerAsmOutputForConstraint(), LowerAsSplatVectorLoad(), llvm::HexagonTargetLowering::LowerBITCAST(), LowerBITREVERSE_XOP(), llvm::HexagonTargetLowering::LowerBUILD_VECTOR(), lowerBUILD_VECTOR(), LowerBUILD_VECTORvXi1(), lowerBuildVectorAsBroadcast(), llvm::SystemZTargetLowering::LowerCall(), llvm::TargetLowering::LowerCallTo(), llvm::HexagonTargetLowering::LowerCONCAT_VECTORS(), LowerCTLZ(), LowerEXTEND_VECTOR_INREG(), LowerEXTRACT_VECTOR_ELT_SSE4(), llvm::HexagonTargetLowering::LowerFormalArguments(), llvm::VETargetLowering::LowerFormalArguments(), llvm::SparcTargetLowering::LowerFormalArguments_64(), lowerFP_TO_INT_SAT(), lowerFPToIntToFP(), LowerHorizontalByteSum(), LowerMGATHER(), LowerMLOAD(), LowerMSCATTER(), LowerMSTORE(), llvm::RISCVTargetLowering::LowerOperation(), LowerPARITY(), LowerSCALAR_TO_VECTOR(), llvm::HexagonTargetLowering::LowerSETCC(), lowerShuffleAsBlend(), lowerShuffleAsBlendOfPSHUFBs(), lowerShuffleAsByteRotate(), lowerShuffleAsByteRotateAndPermute(), lowerShuffleAsDecomposedShuffleMerge(), lowerShuffleAsElementInsertion(), lowerShuffleAsLanePermuteAndPermute(), lowerShuffleAsLanePermuteAndRepeatedMask(), lowerShuffleAsRepeatedMaskAndLanePermute(), lowerShuffleAsSplitOrBlend(), lowerShuffleAsTruncBroadcast(), lowerShuffleAsUNPCKAndPermute(), lowerShuffleAsZeroOrAnyExtend(), lowerShuffleWithPACK(), lowerShuffleWithPERMV(), lowerShuffleWithPSHUFB(), lowerShuffleWithUndefHalf(), LowerSIGN_EXTEND_Mask(), llvm::LanaiTargetLowering::LowerSRL_PARTS(), LowerTruncateVecI1(), llvm::HexagonTargetLowering::LowerUnalignedLoad(), llvm::HexagonTargetLowering::LowerVECTOR_SHIFT(), lowerVECTOR_SHUFFLE(), llvm::HexagonTargetLowering::LowerVECTOR_SHUFFLE(), LowerVectorCTLZ_AVX512CDI(), LowerVectorCTPOP(), lowerVectorIntrinsicScalars(), llvm::HexagonTargetLowering::LowerVSELECT(), LowerVSETCC(), lowerX86FPLogicOp(), LowerZERO_EXTEND_Mask(), matchBinaryPermuteShuffle(), matchBinaryShuffle(), MatchingStackOffset(), matchShuffleAsBlend(), matchUnaryPermuteShuffle(), narrowExtractedVectorSelect(), llvm::TargetLowering::ParseConstraints(), llvm::RISCVTargetLowering::PerformDAGCombine(), performFDivCombine(), performFpToIntCombine(), performScatterStoreCombine(), PerformTruncatingStoreCombine(), PerformVCVTCombine(), PerformVDIVCombine(), llvm::X86TargetLowering::ReplaceNodeResults(), llvm::HexagonDAGToDAGISel::SelectExtractSubvector(), llvm::HexagonDAGToDAGISel::SelectQ2V(), llvm::RISCVDAGToDAGISel::selectSExtBits(), llvm::LoongArchDAGToDAGISel::selectSExti32(), llvm::HexagonDAGToDAGISel::SelectV2Q(), llvm::HexagonDAGToDAGISel::SelectVAlign(), selectVSplatSimmHelper(), llvm::RISCVDAGToDAGISel::selectZExtBits(), llvm::LoongArchDAGToDAGISel::selectZExti32(), setGroupSize(), shouldTransformMulToShiftsAddsSubs(), splitAndLowerShuffle(), llvm::RISCVTargetLowering::splitValueIntoRegisterParts(), TryCombineBaseUpdate(), tryCombineShiftImm(), llvm::RISCVDAGToDAGISel::trySignedBitfieldExtract(), UnpackFromArgumentSlot(), and useRVVForFixedLengthVectorVT().
◆ getStoreSize()
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Return the number of bytes overwritten by a store of the specified value type.
If the value type is a scalable vector type, the scalable property will be set and the runtime size will be a positive integer multiple of the base size.
Definition at line 1169 of file MachineValueType.h.
References llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getKnownMinValue(), getSizeInBits(), and llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::isScalable().
Referenced by llvm::analyzeArguments(), llvm::analyzeReturnValues(), CC_AIX(), CC_MipsO32(), CC_RISCV(), CC_RISCV_FastCC(), llvm::PPCTargetLowering::emitEHSjLjLongJmp(), llvm::PPCTargetLowering::emitEHSjLjSetJmp(), llvm::BasicTTIImplBase< T >::getInterleavedMemoryOpCost(), llvm::X86TTIImpl::getInterleavedMemoryOpCostAVX512(), llvm::MSP430TargetLowering::getReturnAddressFrameIndex(), getScalarStoreSize(), llvm::X86TTIImpl::getShuffleCost(), getStoreSizeInBits(), llvm::SITargetLowering::LowerCall(), lowerShuffleAsBroadcast(), lowerV2X128Shuffle(), lowerVECTOR_SHUFFLE(), scalarizeVectorStore(), and llvm::RISCVDAGToDAGISel::Select().
◆ getStoreSizeInBits()
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Return the number of bits overwritten by a store of the specified value type.
If the value type is a scalable vector type, the scalable property will be set and the runtime size will be a positive integer multiple of the base size.
Definition at line 1186 of file MachineValueType.h.
References getStoreSize().
Referenced by llvm::HexagonTargetLowering::LowerCall(), and llvm::HexagonTargetLowering::LowerFormalArguments().
◆ getVectorElementCount()
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Definition at line 919 of file MachineValueType.h.
References llvm::ElementCount::get(), getVectorMinNumElements(), and isScalableVector().
Referenced by changeVectorElementType(), changeVectorElementTypeToInteger(), llvm::TargetLoweringBase::computeRegisterProperties(), llvm::RISCVTargetLowering::decomposeSubvectorInsertExtractToSubRegs(), getCopyToPartsVector(), getDeinterleaveViaVNSRL(), getHalfNumVectorElementsVT(), llvm::getLLTForMVT(), getMaskTypeFor(), getPow2VectorType(), llvm::TargetLoweringBase::getPreferredVectorAction(), getVectorTypeBreakdownMVT(), getWideningInterleave(), llvm::LLT::LLT(), lowerFP_TO_INT_SAT(), llvm::RISCVTargetLowering::LowerOperation(), lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND(), lowerVectorIntrinsicScalars(), llvm::RISCVTargetLowering::RISCVTargetLowering(), llvm::RISCVDAGToDAGISel::Select(), llvm::RISCVDAGToDAGISel::selectVLXSEG(), llvm::RISCVDAGToDAGISel::selectVSXSEG(), and splatPartsI64WithVL().
◆ getVectorElementType()
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Definition at line 560 of file MachineValueType.h.
References bf16, f16, f32, f64, i1, i128, i16, i2, i32, i4, i64, i8, llvm_unreachable, nxv16bf16, nxv16f16, nxv16f32, nxv16i1, nxv16i16, nxv16i32, nxv16i64, nxv16i8, nxv1bf16, nxv1f16, nxv1f32, nxv1f64, nxv1i1, nxv1i16, nxv1i32, nxv1i64, nxv1i8, nxv2bf16, nxv2f16, nxv2f32, nxv2f64, nxv2i1, nxv2i16, nxv2i32, nxv2i64, nxv2i8, nxv32bf16, nxv32f16, nxv32i1, nxv32i16, nxv32i32, nxv32i64, nxv32i8, nxv4bf16, nxv4f16, nxv4f32, nxv4f64, nxv4i1, nxv4i16, nxv4i32, nxv4i64, nxv4i8, nxv64i1, nxv64i8, nxv8bf16, nxv8f16, nxv8f32, nxv8f64, nxv8i1, nxv8i16, nxv8i32, nxv8i64, nxv8i8, SimpleTy, v1024f32, v1024i1, v1024i32, v1024i8, v10f32, v10i32, v11f32, v11i32, v128bf16, v128f16, v128f32, v128f64, v128i1, v128i16, v128i2, v128i32, v128i4, v128i64, v128i8, v12f32, v12i32, v16bf16, v16f16, v16f32, v16f64, v16i1, v16i16, v16i32, v16i64, v16i8, v1f16, v1f32, v1f64, v1i1, v1i128, v1i16, v1i32, v1i64, v1i8, v2048f32, v2048i1, v2048i32, v256f16, v256f32, v256f64, v256i1, v256i16, v256i2, v256i32, v256i64, v256i8, v2bf16, v2f16, v2f32, v2f64, v2i1, v2i16, v2i32, v2i64, v2i8, v32bf16, v32f16, v32f32, v32f64, v32i1, v32i16, v32i32, v32i64, v32i8, v3bf16, v3f16, v3f32, v3f64, v3i16, v3i32, v3i64, v4bf16, v4f16, v4f32, v4f64, v4i1, v4i16, v4i32, v4i64, v4i8, v512f16, v512f32, v512i1, v512i16, v512i32, v512i8, v5f32, v5i32, v64bf16, v64f16, v64f32, v64f64, v64i1, v64i16, v64i32, v64i4, v64i64, v64i8, v6f32, v6i32, v7f32, v7i32, v8bf16, v8f16, v8f32, v8f64, v8i1, v8i16, v8i32, v8i64, v8i8, v9f32, and v9i32.
Referenced by changeVectorElementTypeToInteger(), combineBitcast(), combineEXTRACT_SUBVECTOR(), combineINSERT_SUBVECTOR(), combineShuffleToAddSubOrFMAddSub(), combineTargetShuffle(), llvm::TargetLoweringBase::computeRegisterProperties(), convertShiftLeftToScale(), ExtendToType(), getConstVector(), getContainerForFixedLengthVector(), getDeinterleaveViaVNSRL(), getHalfNumVectorElementsVT(), llvm::X86TTIImpl::getIntrinsicInstrCost(), llvm::getLLTForMVT(), llvm::RISCVTargetLowering::getLMUL(), getLMUL1VT(), getPow2VectorType(), llvm::HexagonTargetLowering::getPreferredVectorAction(), llvm::X86TargetLowering::getPreferredVectorAction(), llvm::RISCVTargetLowering::getRegClassIDForVecVT(), getScalarType(), getScalarValueForVectorElement(), llvm::X86TargetLowering::getSetCCResultType(), llvm::X86TTIImpl::getShuffleCost(), getShuffleScalarElt(), getTargetVShiftByConstNode(), getTargetVShiftNode(), llvm::X86TargetLowering::getTgtMemIntrinsic(), llvm::TargetLoweringBase::getTypeConversion(), getUnderlyingExtractedFromVec(), getVectorTypeBreakdownMVT(), getWideningInterleave(), getZeroVector(), incDecVectorConstant(), llvm::HexagonTargetLowering::isExtractSubvectorCheap(), llvm::HexagonSubtarget::isHVXElementType(), llvm::HexagonSubtarget::isHVXVectorType(), isLegalT2AddressImmediate(), llvm::RISCVTargetLowering::joinRegisterPartsIntoValue(), llvm::LLT::LLT(), LowerANY_EXTEND(), LowerAVXExtend(), LowerBITCAST(), lowerBUILD_VECTOR(), LowerBUILD_VECTORvXi1(), LowerBuildVectorv4x32(), LowerCONCAT_VECTORS(), llvm::HexagonTargetLowering::LowerCONCAT_VECTORS(), LowerEXTEND_VECTOR_INREG(), llvm::HexagonTargetLowering::LowerEXTRACT_VECTOR_ELT(), lowerFP_TO_INT_SAT(), LowerHorizontalByteSum(), LowerIntVSETCC_AVX512(), LowerLoad(), LowerMGATHER(), LowerMLOAD(), LowerMSCATTER(), llvm::RISCVTargetLowering::LowerOperation(), LowerSCALAR_TO_VECTOR(), llvm::HexagonTargetLowering::LowerSETCC(), lowerShuffleAsBitBlend(), lowerShuffleAsBitMask(), lowerShuffleAsBroadcast(), lowerShuffleAsElementInsertion(), lowerShuffleAsTruncBroadcast(), lowerShuffleWithUndefHalf(), LowerSIGN_EXTEND(), LowerSIGN_EXTEND_Mask(), LowerTruncateVecI1(), lowerV2X128Shuffle(), lowerV4X128Shuffle(), lowerV8I16GeneralSingleInputShuffle(), llvm::HexagonTargetLowering::LowerVECTOR_SHIFT(), llvm::HexagonTargetLowering::LowerVECTOR_SHUFFLE(), lowerVECTOR_SHUFFLE(), LowerVectorCTLZ(), LowerVectorCTLZ_AVX512CDI(), LowerVectorCTPOP(), LowerVectorCTPOPInRegLUT(), lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND(), lowerVectorIntrinsicScalars(), llvm::HexagonTargetLowering::LowerVSELECT(), LowerVSETCC(), LowerVSETCCWithSUBUS(), LowerZERO_EXTEND(), LowerZERO_EXTEND_Mask(), matchSplatAsGather(), narrowExtractedVectorSelect(), performConcatVectorsCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), preAssignMask(), llvm::RISCVDAGToDAGISel::PreprocessISelDAG(), llvm::RISCVTargetLowering::ReplaceNodeResults(), llvm::X86TargetLowering::ReplaceNodeResults(), llvm::RISCVTargetLowering::RISCVTargetLowering(), scaleVectorType(), llvm::RISCVDAGToDAGISel::Select(), llvm::HexagonDAGToDAGISel::SelectExtractSubvector(), llvm::HvxSelector::selectExtractSubvector(), splitAndLowerShuffle(), llvm::RISCVTargetLowering::splitValueIntoRegisterParts(), llvm::splitVectorType(), tryExtendDUPToExtractHigh(), useRVVForFixedLengthVectorVT(), and llvm::X86TargetLowering::X86TargetLowering().
◆ getVectorMinNumElements()
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Given a vector type, return the minimum number of elements it contains.
Definition at line 741 of file MachineValueType.h.
References llvm_unreachable, nxv16bf16, nxv16f16, nxv16f32, nxv16i1, nxv16i16, nxv16i32, nxv16i64, nxv16i8, nxv1bf16, nxv1f16, nxv1f32, nxv1f64, nxv1i1, nxv1i16, nxv1i32, nxv1i64, nxv1i8, nxv2bf16, nxv2f16, nxv2f32, nxv2f64, nxv2i1, nxv2i16, nxv2i32, nxv2i64, nxv2i8, nxv32bf16, nxv32f16, nxv32i1, nxv32i16, nxv32i32, nxv32i64, nxv32i8, nxv4bf16, nxv4f16, nxv4f32, nxv4f64, nxv4i1, nxv4i16, nxv4i32, nxv4i64, nxv4i8, nxv64i1, nxv64i8, nxv8bf16, nxv8f16, nxv8f32, nxv8f64, nxv8i1, nxv8i16, nxv8i32, nxv8i64, nxv8i8, SimpleTy, v1024f32, v1024i1, v1024i32, v1024i8, v10f32, v10i32, v11f32, v11i32, v128bf16, v128f16, v128f32, v128f64, v128i1, v128i16, v128i2, v128i32, v128i4, v128i64, v128i8, v12f32, v12i32, v16bf16, v16f16, v16f32, v16f64, v16i1, v16i16, v16i32, v16i64, v16i8, v1f16, v1f32, v1f64, v1i1, v1i128, v1i16, v1i32, v1i64, v1i8, v2048f32, v2048i1, v2048i32, v256f16, v256f32, v256f64, v256i1, v256i16, v256i2, v256i32, v256i64, v256i8, v2bf16, v2f16, v2f32, v2f64, v2i1, v2i16, v2i32, v2i64, v2i8, v32bf16, v32f16, v32f32, v32f64, v32i1, v32i16, v32i32, v32i64, v32i8, v3bf16, v3f16, v3f32, v3f64, v3i16, v3i32, v3i64, v4bf16, v4f16, v4f32, v4f64, v4i1, v4i16, v4i32, v4i64, v4i8, v512f16, v512f32, v512i1, v512i16, v512i32, v512i8, v5f32, v5i32, v64bf16, v64f16, v64f32, v64f64, v64i1, v64i16, v64i32, v64i4, v64i64, v64i8, v6f32, v6i32, v7f32, v7i32, v8bf16, v8f16, v8f32, v8f64, v8i1, v8i16, v8i32, v8i64, v8i8, v9f32, and v9i32.
Referenced by llvm::RISCVTargetLowering::computeVLMax(), llvm::HexagonTargetLowering::getPreferredVectorAction(), getVectorElementCount(), getVectorNumElements(), isPow2VectorType(), and llvm::LLT::LLT().
◆ getVectorNumElements()
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inline |
Definition at line 923 of file MachineValueType.h.
References getVectorMinNumElements(), isScalableVector(), and llvm::reportInvalidSizeRequest().
Referenced by llvm::AMDGPUTargetLowering::analyzeFormalArgumentsCompute(), combineAndnp(), combineBitcast(), combineConcatVectorOps(), combineCVTP2I_CVTTP2I(), combineEXTRACT_SUBVECTOR(), combineINSERT_SUBVECTOR(), combineMOVMSK(), combinePredicateReduction(), combineSetCCMOVMSK(), combineStore(), combineTargetShuffle(), combineVectorSignBitsTruncation(), combineVEXTRACT_STORE(), combineX86INT_TO_FP(), combineX86ShuffleChain(), llvm::X86TargetLowering::ComputeNumSignBitsForTargetNode(), convertShiftLeftToScale(), createPackShuffleMask(), createShuffleStride(), llvm::createSplat2ShuffleMask(), createVariablePermute(), DecodePALIGNRMask(), ExpandHorizontalBinOp(), ExtendToType(), ExtractBitFromMaskVector(), genShuffleBland(), llvm::AArch64TTIImpl::getArithmeticReductionCost(), llvm::X86TTIImpl::getArithmeticReductionCost(), getAVX512TruncNode(), getConstVector(), getContainerForFixedLengthVector(), getDefaultVLOps(), getFauxShuffleMask(), getGatherNode(), getHopForBuildVector(), llvm::X86TTIImpl::getInterleavedMemoryOpCostAVX512(), getMemCmpLoad(), llvm::X86TTIImpl::getMinMaxReductionCost(), getMOVL(), getPack(), llvm::SITargetLowering::getPreferredVectorAction(), llvm::NVPTXTargetLowering::getPreferredVectorAction(), llvm::PPCTargetLowering::getPreferredVectorAction(), llvm::X86TargetLowering::getPreferredVectorAction(), llvm::X86TTIImpl::getReplicationShuffleCost(), llvm::X86TTIImpl::getShuffleCost(), getShuffleHalfVectors(), getShuffleScalarElt(), getShuffleVectorZeroOrUndef(), getTargetShuffleAndZeroables(), getTargetShuffleMask(), getTargetVShiftNode(), llvm::ARMTargetLowering::getTgtMemIntrinsic(), llvm::X86TargetLowering::getTgtMemIntrinsic(), getUnderlyingExtractedFromVec(), getVectorMaskingNode(), getZeroVector(), group2Shuffle(), incDecVectorConstant(), insert1BitVector(), InsertBitToMaskVector(), isAddSubOrSubAdd(), IsElementEquivalent(), llvm::HexagonTargetLowering::isExtractSubvectorCheap(), isHopBuildVector(), isHorizontalBinOp(), isInterleaveShuffle(), lower1BitShuffle(), lower256BitShuffle(), LowerAsSplatVectorLoad(), LowerAVXCONCAT_VECTORS(), LowerAVXExtend(), LowerBITCAST(), LowerBITREVERSE(), LowerBITREVERSE_XOP(), llvm::HexagonTargetLowering::LowerBUILD_VECTOR(), llvm::VETargetLowering::lowerBUILD_VECTOR(), lowerBUILD_VECTOR(), lowerBuildVectorAsBroadcast(), LowerBuildVectorAsInsert(), lowerBuildVectorToBitOp(), llvm::HexagonTargetLowering::LowerCONCAT_VECTORS(), LowerCONCAT_VECTORSvXi1(), LowerEXTEND_VECTOR_INREG(), LowerEXTRACT_SUBVECTOR(), LowerFunnelShift(), LowerLoad(), LowerMGATHER(), LowerMSCATTER(), LowerMUL(), LowerMULH(), LowerMULO(), LowerRotate(), LowerSCALAR_TO_VECTOR(), llvm::HexagonTargetLowering::LowerSETCC(), LowerShift(), LowerShiftByScalarImmediate(), LowerShiftByScalarVariable(), lowerShuffleAsBlend(), lowerShuffleAsBroadcast(), lowerShuffleAsByteRotateAndPermute(), lowerShuffleAsElementInsertion(), lowerShuffleAsLanePermuteAndPermute(), lowerShuffleAsRepeatedMaskAndLanePermute(), lowerShuffleAsShift(), lowerShuffleAsSpecificZeroOrAnyExtend(), lowerShuffleAsVTRUNC(), lowerShuffleAsZeroOrAnyExtend(), lowerShuffleOfExtractsAsVperm(), lowerShufflePairAsUNPCKAndPermute(), lowerShuffleToEXPAND(), lowerShuffleWithPERMV(), lowerShuffleWithUndefHalf(), lowerShuffleWithVPMOV(), LowerSIGN_EXTEND(), llvm::AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(), LowerSIGN_EXTEND_Mask(), lowerToAddSubOrFMAddSub(), LowerToHorizontalOp(), LowerTruncateVecI1(), lowerV8I16GeneralSingleInputShuffle(), llvm::HexagonTargetLowering::LowerVECTOR_SHIFT(), lowerVECTOR_SHUFFLE(), lowerVECTOR_SHUFFLEAsVSlideup(), LowerVectorCTLZ_AVX512CDI(), LowerVectorCTLZInRegLUT(), LowerVectorCTPOP(), LowerVectorCTPOPInRegLUT(), llvm::HexagonTargetLowering::LowerVSELECT(), LowerVSETCC(), LowervXi8MulWithUNPCK(), LowerZERO_EXTEND_Mask(), matchShuffleAsEXTRQ(), matchShuffleAsINSERTQ(), matchShuffleWithPACK(), matchShuffleWithSHUFPD(), matchShuffleWithUNPCK(), matchUnaryShuffle(), narrowExtractedVectorSelect(), performConcatVectorsCombine(), performLOADCombine(), PerformVECREDUCE_ADDCombine(), performVECTOR_SHUFFLECombine(), llvm::X86TargetLowering::ReplaceNodeResults(), scalarizeVectorStore(), scaleVectorType(), llvm::HexagonDAGToDAGISel::SelectExtractSubvector(), llvm::HvxSelector::selectExtractSubvector(), setGroupSize(), llvm::X86TargetLowering::SimplifyDemandedBitsForTargetNode(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), llvm::X86TargetLowering::SimplifyMultipleUseDemandedBitsForTargetNode(), splitAndLowerShuffle(), tryExtendDUPToExtractHigh(), useRVVForFixedLengthVectorVT(), and vectorizeExtractedCast().
◆ getVectorVT() [1/3]
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inlinestatic |
Definition at line 1521 of file MachineValueType.h.
References getScalableVectorVT(), and getVectorVT().
◆ getVectorVT() [2/3]
Definition at line 1284 of file MachineValueType.h.
References bf16, f16, f32, f64, i1, i128, i16, i2, i32, i4, i64, i8, INVALID_SIMPLE_VALUE_TYPE, SimpleTy, v1024f32, v1024i1, v1024i32, v1024i8, v10f32, v10i32, v11f32, v11i32, v128bf16, v128f16, v128f32, v128f64, v128i1, v128i16, v128i2, v128i32, v128i4, v128i64, v128i8, v12f32, v12i32, v16bf16, v16f16, v16f32, v16f64, v16i1, v16i16, v16i32, v16i64, v16i8, v1f16, v1f32, v1f64, v1i1, v1i128, v1i16, v1i32, v1i64, v1i8, v2048f32, v2048i1, v2048i32, v256f16, v256f32, v256f64, v256i1, v256i16, v256i2, v256i32, v256i64, v256i8, v2bf16, v2f16, v2f32, v2f64, v2i1, v2i16, v2i32, v2i64, v2i8, v32bf16, v32f16, v32f32, v32f64, v32i1, v32i16, v32i32, v32i64, v32i8, v3bf16, v3f16, v3f32, v3f64, v3i16, v3i32, v3i64, v4bf16, v4f16, v4f32, v4f64, v4i1, v4i16, v4i32, v4i64, v4i8, v512f16, v512f32, v512i1, v512i16, v512i32, v512i8, v5f32, v5i32, v64bf16, v64f16, v64f32, v64f64, v64i1, v64i16, v64i32, v64i4, v64i64, v64i8, v6f32, v6i32, v7f32, v7i32, v8bf16, v8f16, v8f32, v8f64, v8i1, v8i16, v8i32, v8i64, v8i8, v9f32, and v9i32.
Referenced by AddCombineBUILD_VECTORToVPADDL(), canonicalizeBitSelect(), canonicalizeShuffleMaskWithHorizOp(), changeVectorElementType(), changeVectorElementTypeToInteger(), combineArithReduction(), combineBitcast(), combineConcatVectorOps(), combineCVTP2I_CVTTP2I(), combineExtractVectorElt(), combineExtractWithShuffle(), combineFaddCFmul(), combineMOVMSK(), combineMulToPMADDWD(), combinePredicateReduction(), combineStore(), combineTargetShuffle(), combineVectorHADDSUB(), combineX86INT_TO_FP(), combineX86ShuffleChain(), combineX86ShufflesConstants(), constructDup(), constructRetValue(), createPSADBW(), createVariablePermute(), createVPDPBUSD(), EltsFromConsecutiveLoads(), ExtractBitFromMaskVector(), llvm::X86TTIImpl::getArithmeticInstrCost(), getAVX512Node(), getAVX512TruncNode(), llvm::HvxSelector::getBoolVT(), getBuildDwordsVector(), getConstVector(), getDeinterleaveViaVNSRL(), getGatherNode(), getHalfNumVectorElementsVT(), llvm::X86TTIImpl::getInterleavedMemoryOpCostAVX512(), llvm::getLegalVectorType(), llvm::VECustomDAG::getMaskBroadcast(), getMaskNode(), getMaskTypeFor(), llvm::getMVTForLLT(), getOnesVector(), llvm::HvxSelector::getPairVT(), getPermuteNode(), getPow2VectorType(), getPrefetchNode(), getPromotedVectorElementType(), getScatterNode(), llvm::ARMTargetLowering::getSetCCResultType(), llvm::HvxSelector::getSingleVT(), getTargetVShiftNode(), llvm::ARMTargetLowering::getTgtMemIntrinsic(), llvm::X86TargetLowering::getTgtMemIntrinsic(), llvm::TargetLoweringBase::getTypeConversion(), getVectorMaskingNode(), getVectorTypeBreakdownMVT(), llvm::EVT::getVectorVT(), getVectorVT(), getVT(), getWideningInterleave(), getZeroVector(), llvm::HexagonTargetLowering::HexagonTargetLowering(), InsertBitToMaskVector(), is128BitUnpackShuffleMask(), llvm::HexagonSubtarget::isTypeForHVX(), llvm::SystemZVectorConstantInfo::isVectorConstantLegal(), lower1BitShuffle(), lower256BitShuffle(), LowerBITCAST(), LowerBITREVERSE(), LowerBITREVERSE_XOP(), lowerBUILD_VECTOR(), lowerBuildVectorAsBroadcast(), LowerCONCAT_VECTORS_i1(), LowerCTPOP(), LowerEXTRACT_SUBVECTOR(), lowerFPToIntToFP(), LowerFunnelShift(), LowerHorizontalByteSum(), LowerI64IntToFP_AVX512DQ(), LowerINTRINSIC_W_CHAIN(), LowerMGATHER(), LowerMLOAD(), LowerMSCATTER(), LowerMSTORE(), LowerMUL(), LowerMULH(), LowerMULO(), llvm::RISCVTargetLowering::LowerOperation(), LowerRotate(), LowerSCALAR_TO_VECTOR(), llvm::HexagonTargetLowering::LowerSETCC(), LowerShift(), LowerShiftByScalarImmediate(), LowerShiftByScalarVariable(), lowerShuffleAsBitMask(), lowerShuffleAsBlend(), lowerShuffleAsBlendOfPSHUFBs(), lowerShuffleAsBroadcast(), lowerShuffleAsByteRotate(), lowerShuffleAsByteRotateAndPermute(), lowerShuffleAsElementInsertion(), lowerShuffleAsPermuteAndUnpack(), lowerShuffleAsSpecificZeroOrAnyExtend(), lowerShuffleAsVTRUNC(), lowerShuffleToEXPAND(), lowerShuffleWithPACK(), lowerShuffleWithPSHUFB(), lowerShuffleWithVPMOV(), LowerSIGN_EXTEND_Mask(), LowerStore(), LowerTruncateVecI1(), llvm::HexagonTargetLowering::LowerUnalignedLoad(), lowerV2X128Shuffle(), lowerV4X128Shuffle(), lowerV8I16GeneralSingleInputShuffle(), llvm::HexagonTargetLowering::LowerVECTOR_SHIFT(), LowerVECTOR_SHUFFLE(), lowerVECTOR_SHUFFLE(), LowerVectorCTLZ_AVX512CDI(), LowerVectorCTLZInRegLUT(), LowerVectorCTPOP(), lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND(), lowerVectorIntrinsicScalars(), llvm::HexagonTargetLowering::LowerVSELECT(), LowervXi8MulWithUNPCK(), lowerX86FPLogicOp(), LowerZERO_EXTEND_Mask(), matchBinaryPermuteShuffle(), matchShuffleAsBitRotate(), matchShuffleAsShift(), matchShuffleAsVTRUNC(), matchShuffleWithPACK(), matchUnaryPermuteShuffle(), matchUnaryShuffle(), llvm::MipsTargetLowering::MipsTargetLowering(), narrowExtractedVectorSelect(), NarrowVector(), performConcatVectorsCombine(), performLOADCombine(), PerformVQDMULHCombine(), llvm::X86TargetLowering::ReplaceNodeResults(), llvm::RISCVTargetLowering::RISCVTargetLowering(), scaleVectorType(), llvm::X86TargetLowering::SimplifyDemandedBitsForTargetNode(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), skipExtensionForVectorMULL(), SkipExtensionForVMULL(), splatPartsI64WithVL(), splitAndLowerShuffle(), llvm::splitVectorType(), TryCombineBaseUpdate(), tryExtendDUPToExtractHigh(), tryWidenMaskForShuffle(), vectorizeExtractedCast(), widenSubVector(), and WidenVector().
◆ getVectorVT() [3/3]
Definition at line 1515 of file MachineValueType.h.
References getScalableVectorVT(), and getVectorVT().
◆ getVT()
Return the value type corresponding to the specified type.
This returns all pointers as iPTR. If HandleUnknown is true, unknown types are returned as Other, otherwise they are invalid.
This returns all pointers as MVT::iPTR. If HandleUnknown is true, unknown types are returned as Other, otherwise they are invalid.
Definition at line 573 of file ValueTypes.cpp.
References aarch64svcount, bf16, llvm::Type::BFloatTyID, llvm::Type::DoubleTyID, f128, f16, f32, f64, f80, llvm::Type::FixedVectorTyID, llvm::Type::FloatTyID, llvm::Type::FP128TyID, getBitWidth(), llvm::VectorType::getElementCount(), llvm::VectorType::getElementType(), getIntegerVT(), llvm::TargetExtType::getName(), llvm::Type::getTypeID(), getVectorVT(), getVT(), llvm::Type::HalfTyID, llvm::Type::IntegerTyID, iPTR, isVoid, llvm_unreachable, MVT(), Other, llvm::Type::PointerTyID, llvm::Type::PPC_FP128TyID, ppcf128, llvm::Type::ScalableVectorTyID, spirvbuiltin, llvm::StringRef::starts_with(), llvm::Type::TargetExtTyID, llvm::Type::VoidTyID, llvm::Type::X86_AMXTyID, llvm::Type::X86_FP80TyID, llvm::Type::X86_MMXTyID, x86amx, and x86mmx.
Referenced by llvm::CallLowering::checkReturn(), getConvRTLibDesc(), llvm::EVT::getEVT(), llvm::X86TTIImpl::getInterleavedMemoryOpCostAVX512(), llvm::SITargetLowering::getTgtMemIntrinsic(), llvm::AArch64TargetLowering::getTgtMemIntrinsic(), llvm::ARMTargetLowering::getTgtMemIntrinsic(), llvm::HexagonTargetLowering::getTgtMemIntrinsic(), llvm::X86TargetLowering::getTgtMemIntrinsic(), getVT(), llvm::GCNTTIImpl::isReadRegisterSourceOfDivergence(), and llvm::AArch64CallLowering::lowerReturn().
◆ integer_fixedlen_vector_valuetypes()
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inlinestatic |
Definition at line 1569 of file MachineValueType.h.
References llvm::enum_seq_inclusive(), FIRST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE, llvm::force_iteration_on_noniterable_enum, and LAST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE.
Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering(), llvm::AMDGPUTargetLowering::AMDGPUTargetLowering(), llvm::ARMTargetLowering::ARMTargetLowering(), llvm::RISCVTargetLowering::RISCVTargetLowering(), llvm::SparcTargetLowering::SparcTargetLowering(), llvm::SystemZTargetLowering::SystemZTargetLowering(), and llvm::WebAssemblyTargetLowering::WebAssemblyTargetLowering().
◆ integer_scalable_vector_valuetypes()
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inlinestatic |
Definition at line 1581 of file MachineValueType.h.
References llvm::enum_seq_inclusive(), FIRST_INTEGER_SCALABLE_VECTOR_VALUETYPE, llvm::force_iteration_on_noniterable_enum, and LAST_INTEGER_SCALABLE_VECTOR_VALUETYPE.
Referenced by llvm::RISCVTargetLowering::RISCVTargetLowering().
◆ integer_valuetypes()
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inlinestatic |
Definition at line 1540 of file MachineValueType.h.
References llvm::enum_seq_inclusive(), FIRST_INTEGER_VALUETYPE, llvm::force_iteration_on_noniterable_enum, and LAST_INTEGER_VALUETYPE.
Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering(), llvm::AMDGPUTargetLowering::AMDGPUTargetLowering(), llvm::ARMTargetLowering::ARMTargetLowering(), llvm::AVRTargetLowering::AVRTargetLowering(), llvm::BPFTargetLowering::BPFTargetLowering(), findMemType(), llvm::HexagonTargetLowering::HexagonTargetLowering(), llvm::LanaiTargetLowering::LanaiTargetLowering(), llvm::M68kTargetLowering::M68kTargetLowering(), llvm::MipsTargetLowering::MipsTargetLowering(), llvm::MSP430TargetLowering::MSP430TargetLowering(), llvm::NVPTXTargetLowering::NVPTXTargetLowering(), PerformTruncatingStoreCombine(), llvm::PPCTargetLowering::PPCTargetLowering(), llvm::R600TargetLowering::R600TargetLowering(), llvm::SparcTargetLowering::SparcTargetLowering(), llvm::SystemZTargetLowering::SystemZTargetLowering(), llvm::WebAssemblyTargetLowering::WebAssemblyTargetLowering(), llvm::X86TargetLowering::X86TargetLowering(), and llvm::XCoreTargetLowering::XCoreTargetLowering().
◆ is1024BitVector()
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◆ is128BitVector()
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Return true if this is a 128-bit vector type.
Definition at line 445 of file MachineValueType.h.
References SimpleTy, v128i1, v16i8, v1i128, v2f64, v2i64, v4f32, v4i32, v8bf16, v8f16, and v8i16.
Referenced by CC_AArch64_Custom_Block(), CC_PPC64_ELF_Shadow_GPR_Regs(), llvm::CC_XPLINK64_Shadow_Reg(), combineAndNotIntoANDNP(), combineCVTP2I_CVTTP2I(), combineEXTRACT_SUBVECTOR(), combineSetCCMOVMSK(), combineX86INT_TO_FP(), combineX86ShuffleChain(), llvm::X86TTIImpl::getCmpSelInstrCost(), llvm::X86TTIImpl::getIntrinsicInstrCost(), getZeroVector(), isHorizontalBinOp(), LowerBITREVERSE_XOP(), lowerBuildVectorAsBroadcast(), LowerBuildVectorv4x32(), LowerEXTEND_VECTOR_INREG(), LowerEXTRACT_VECTOR_ELT_SSE4(), LowerRotate(), LowerSCALAR_TO_VECTOR(), lowerShuffleAsBitRotate(), lowerShuffleAsByteRotate(), lowerShuffleAsByteRotateAndPermute(), lowerShuffleAsByteShiftMask(), lowerShuffleAsElementInsertion(), lowerShuffleAsPermuteAndUnpack(), lowerShuffleAsSpecificZeroOrAnyExtend(), lowerShuffleAsVALIGN(), lowerShuffleAsVTRUNC(), lowerShuffleOfExtractsAsVperm(), lowerShuffleWithPSHUFB(), lowerShuffleWithUndefHalf(), LowerTruncateVecI1(), lowerVECTOR_SHUFFLE(), LowerVectorCTPOP(), LowerVSETCC(), matchBinaryPermuteShuffle(), matchBinaryShuffle(), matchShuffleAsInsertPS(), matchUnaryPermuteShuffle(), matchUnaryShuffle(), narrowExtractedVectorSelect(), performAddSubLongCombine(), performVECTOR_SHUFFLECombine(), scalarizeVectorStore(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), supportedVectorShiftWithImm(), and supportedVectorVarShift().
◆ is16BitVector()
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◆ is2048BitVector()
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◆ is256BitVector()
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Return true if this is a 256-bit vector type.
Definition at line 454 of file MachineValueType.h.
References SimpleTy, v128i2, v16bf16, v16f16, v16i16, v256i1, v32i8, v4f64, v4i64, v64i4, v8f32, and v8i32.
Referenced by CC_X86_VectorCallGetSSEs(), combineAndNotIntoANDNP(), combineConcatVectorOps(), combineEXTRACT_SUBVECTOR(), combineSetCCMOVMSK(), combineVectorSignBitsTruncation(), combineX86ShuffleChain(), ExpandHorizontalBinOp(), getHopForBuildVector(), llvm::X86TTIImpl::getIntrinsicInstrCost(), getZeroVector(), isHopBuildVector(), isHorizontalBinOp(), LowerABD(), LowerABS(), LowerADDSAT_SUBSAT(), LowerAVG(), LowerAVXCONCAT_VECTORS(), LowerBITREVERSE_XOP(), lowerBuildVectorAsBroadcast(), LowerCONCAT_VECTORS(), LowerEXTEND_VECTOR_INREG(), LowerFunnelShift(), LowerMINMAX(), LowerMUL(), LowerMULH(), LowerRotate(), LowerShift(), lowerShuffleAsBroadcast(), lowerShuffleAsByteRotateAndPermute(), lowerShuffleAsLanePermuteAndShuffle(), lowerShuffleAsRepeatedMaskAndLanePermute(), lowerShuffleAsVALIGN(), lowerShuffleAsVTRUNC(), lowerShuffleOfExtractsAsVperm(), lowerShuffleWithPSHUFB(), lowerShuffleWithUndefHalf(), LowerStore(), LowerToHorizontalOp(), LowerTruncateVecI1(), lowerVECTOR_SHUFFLE(), LowerVectorCTLZ(), LowerVectorCTLZ_AVX512CDI(), LowerVectorCTPOP(), LowerVSETCC(), matchBinaryPermuteShuffle(), matchBinaryShuffle(), matchShuffleAsBlend(), matchUnaryPermuteShuffle(), matchUnaryShuffle(), narrowExtractedVectorSelect(), narrowShuffle(), llvm::X86TargetLowering::SimplifyDemandedBitsForTargetNode(), supportedVectorShiftWithImm(), and supportedVectorVarShift().
◆ is32BitVector()
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Return true if this is a 32-bit vector type.
Definition at line 428 of file MachineValueType.h.
References SimpleTy, v1f32, v1i32, v2bf16, v2f16, v2i16, v32i1, and v4i8.
Referenced by CC_AArch64_Custom_Block(), and LowerStore().
◆ is512BitVector()
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Return true if this is a 512-bit vector type.
Definition at line 464 of file MachineValueType.h.
References SimpleTy, v128i4, v16f32, v16i32, v256i2, v32bf16, v32f16, v32i16, v512i1, v64i8, v8f64, and v8i64.
Referenced by CC_X86_VectorCallGetSSEs(), combineAndNotIntoANDNP(), combineConcatVectorOps(), combineShuffleToAddSubOrFMAddSub(), combineVectorSignBitsTruncation(), combineX86ShuffleChain(), getAVX512Node(), getAVX512TruncNode(), llvm::X86TTIImpl::getIntrinsicInstrCost(), llvm::X86TargetLowering::getSetCCResultType(), getZeroVector(), LowerAVXCONCAT_VECTORS(), LowerBITREVERSE(), lowerBuildVectorAsBroadcast(), LowerCONCAT_VECTORS(), LowerEXTEND_VECTOR_INREG(), LowerFunnelShift(), LowerMGATHER(), LowerMLOAD(), LowerMSCATTER(), LowerMSTORE(), LowerRotate(), LowerShift(), LowerShiftByScalarImmediate(), lowerShuffleAsBroadcast(), lowerShuffleAsByteRotate(), lowerShuffleAsByteRotateAndPermute(), lowerShuffleWithPERMV(), lowerShuffleWithPSHUFB(), lowerShuffleWithUndefHalf(), LowerSIGN_EXTEND_Mask(), lowerToAddSubOrFMAddSub(), lowerV4X128Shuffle(), lowerVECTOR_SHUFFLE(), LowerVectorCTLZ(), LowerVectorCTLZ_AVX512CDI(), LowerVectorCTPOP(), LowerVSETCC(), LowerZERO_EXTEND_Mask(), matchBinaryPermuteShuffle(), matchBinaryShuffle(), matchShuffleAsVTRUNC(), matchUnaryPermuteShuffle(), matchUnaryShuffle(), narrowExtractedVectorSelect(), narrowShuffle(), supportedVectorShiftWithImm(), supportedVectorVarShift(), and useVPTERNLOG().
◆ is64BitVector()
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Return true if this is a 64-bit vector type.
Definition at line 436 of file MachineValueType.h.
References SimpleTy, v1f64, v1i64, v2f32, v2i32, v4bf16, v4f16, v4i16, v64i1, and v8i8.
Referenced by CC_AArch64_Custom_Block(), LowerStore(), and tryExtendDUPToExtractHigh().
◆ isByteSized()
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Returns true if the number of bits for the type is a multiple of an 8-bit byte.
Definition at line 1192 of file MachineValueType.h.
References getSizeInBits(), and llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::isKnownMultipleOf().
◆ isFixedLengthVector()
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inline |
Definition at line 416 of file MachineValueType.h.
References FIRST_FIXEDLEN_VECTOR_VALUETYPE, LAST_FIXEDLEN_VECTOR_VALUETYPE, and SimpleTy.
Referenced by CC_RISCV(), CC_RISCV_FastCC(), convertLocVTToValVT(), convertValVTToLocVT(), getContainerForFixedLengthVector(), getDefaultVLOps(), getDeinterleaveViaVNSRL(), getWideningInterleave(), lowerBUILD_VECTOR(), lowerFP_TO_INT_SAT(), llvm::RISCVTargetLowering::LowerOperation(), lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND(), matchSplatAsGather(), performFP_TO_INTCombine(), llvm::RISCVTargetLowering::ReplaceNodeResults(), llvm::RISCVDAGToDAGISel::Select(), and useRVVForFixedLengthVectorVT().
◆ isFloatingPoint()
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Return true if this is a FP or a vector FP type.
Definition at line 368 of file MachineValueType.h.
References FIRST_FP_FIXEDLEN_VECTOR_VALUETYPE, FIRST_FP_SCALABLE_VECTOR_VALUETYPE, FIRST_FP_VALUETYPE, LAST_FP_FIXEDLEN_VECTOR_VALUETYPE, LAST_FP_SCALABLE_VECTOR_VALUETYPE, LAST_FP_VALUETYPE, and SimpleTy.
Referenced by llvm::AMDGPUTargetLowering::analyzeFormalArgumentsCompute(), CC_LoongArch(), CC_MipsO32(), CC_RISCV(), CC_X86_32_VectorCall(), CC_X86_64_VectorCall(), combineTargetShuffle(), combineX86ShuffleChain(), combineX86ShufflesConstants(), getConstantVector(), getCopyFromParts(), getCopyToParts(), getTargetShuffleAndZeroables(), llvm::TargetLoweringBase::getTypeToPromoteTo(), getVCmpInst(), getZeroVector(), isAddSubOrSubAdd(), isHorizontalBinOp(), lowerBUILD_VECTOR(), LowerFABSorFNEG(), LowerFCOPYSIGN(), lowerScalarInsert(), lowerScalarSplat(), lowerShuffleAsBroadcast(), lowerShuffleAsElementInsertion(), lowerShuffleAsLanePermuteAndShuffle(), lowerShuffleAsPermuteAndUnpack(), lowerVECTOR_SHUFFLE(), LowerVSETCC(), and performScatterStoreCombine().
◆ isInteger()
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inline |
Return true if this is an integer or a vector integer type.
Definition at line 378 of file MachineValueType.h.
References FIRST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE, FIRST_INTEGER_SCALABLE_VECTOR_VALUETYPE, FIRST_INTEGER_VALUETYPE, LAST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE, LAST_INTEGER_SCALABLE_VECTOR_VALUETYPE, LAST_INTEGER_VALUETYPE, and SimpleTy.
Referenced by llvm::AMDGPUTargetLowering::analyzeFormalArgumentsCompute(), convertLocVTToValVT(), convertValVTToLocVT(), llvm::TargetLowering::findOptimalMemOpLowering(), getCopyFromParts(), llvm::RegsForValue::getCopyFromRegs(), getCopyToParts(), getCopyToPartsVector(), getRegistersForValue(), llvm::X86TTIImpl::getScalarizationOverhead(), getShuffleScalarElt(), llvm::TargetLoweringBase::getTypeToPromoteTo(), llvm::X86TTIImpl::getVectorInstrCost(), isValueTypeInRegForCC(), llvm::TargetLowering::LegalizeSetCCCondCode(), lower256BitShuffle(), LowerABS(), llvm::X86TargetLowering::LowerAsmOutputForConstraint(), lowerBUILD_VECTOR(), LowerLoad(), llvm::RISCVTargetLowering::LowerOperation(), LowerSCALAR_TO_VECTOR(), lowerShuffleAsBitBlend(), lowerShuffleAsBroadcast(), lowerShuffleAsTruncBroadcast(), LowerStore(), lowerVECTOR_SHUFFLE(), matchUnaryShuffle(), llvm::TargetLowering::ParseConstraints(), llvm::RISCVDAGToDAGISel::PreprocessISelDAG(), and llvm::X86TargetLowering::ReplaceNodeResults().
◆ isOverloaded()
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inline |
◆ isPow2VectorType()
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inline |
Returns true if the given vector is a power of 2.
Definition at line 538 of file MachineValueType.h.
References getVectorMinNumElements().
Referenced by getPow2VectorType(), llvm::TargetLoweringBase::getPreferredVectorAction(), llvm::SITargetLowering::getPreferredVectorAction(), and useRVVForFixedLengthVectorVT().
◆ isScalableTargetExtVT()
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inline |
Return true if this is a custom target type that has a scalable size.
Definition at line 407 of file MachineValueType.h.
References aarch64svcount, and SimpleTy.
Referenced by isScalableVT(), and llvm::LLT::LLT().
◆ isScalableVector()
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inline |
Return true if this is a vector value type where the runtime length is machine dependent.
Definition at line 401 of file MachineValueType.h.
References FIRST_SCALABLE_VECTOR_VALUETYPE, LAST_SCALABLE_VECTOR_VALUETYPE, and SimpleTy.
Referenced by bitsGE(), bitsGT(), bitsLE(), bitsLT(), CC_AArch64_Custom_Block(), CC_RISCV(), llvm::TargetLoweringBase::computeRegisterProperties(), llvm::RISCVTargetLowering::computeVLMax(), convertLocVTToValVT(), finishStackBlock(), getDefaultScalableVLOps(), getDefaultVLOps(), llvm::RISCVTargetLowering::getLMUL(), llvm::SITargetLowering::getPreferredVectorAction(), llvm::HexagonTargetLowering::getPreferredVectorAction(), llvm::NVPTXTargetLowering::getPreferredVectorAction(), llvm::PPCTargetLowering::getPreferredVectorAction(), llvm::X86TargetLowering::getPreferredVectorAction(), getVectorElementCount(), getVectorNumElements(), getVectorTypeBreakdownMVT(), isScalableVT(), llvm::RISCVTargetLowering::joinRegisterPartsIntoValue(), llvm::RISCVTargetLowering::LowerFormalArguments(), llvm::RISCVTargetLowering::PerformDAGCombine(), llvm::RISCVDAGToDAGISel::PreprocessISelDAG(), llvm::RISCVDAGToDAGISel::Select(), and llvm::RISCVTargetLowering::splitValueIntoRegisterParts().
◆ isScalableVT()
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inline |
Return true if the type is a scalable type.
Definition at line 412 of file MachineValueType.h.
References isScalableTargetExtVT(), and isScalableVector().
◆ isScalarInteger()
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inline |
Return true if this is an integer, not including vectors.
Definition at line 388 of file MachineValueType.h.
References FIRST_INTEGER_VALUETYPE, LAST_INTEGER_VALUETYPE, and SimpleTy.
Referenced by CC_LoongArch(), CC_RISCV(), hasBZHI(), LowerBITCAST(), llvm::RISCVTargetLowering::LowerOperation(), llvm::HexagonTargetLowering::LowerSETCC(), lowerVectorIntrinsicScalars(), llvm::HexagonTargetLowering::LowerVSELECT(), llvm::X86TargetLowering::SimplifyDemandedBitsForTargetNode(), and truncateScalarIntegerArg().
◆ isValid()
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Return true if this is a valid simple valuetype.
Definition at line 362 of file MachineValueType.h.
References FIRST_VALUETYPE, LAST_VALUETYPE, and SimpleTy.
Referenced by llvm::TargetLoweringBase::initActions(), llvm::HexagonSubtarget::isTypeForHVX(), llvm::LLT::LLT(), llvm::MipsTargetLowering::MipsTargetLowering(), llvm::TargetLoweringBase::setCondCodeAction(), llvm::TargetLoweringBase::setLoadExtAction(), and llvm::TargetLoweringBase::setTruncStoreAction().
◆ isVector()
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inline |
Return true if this is a vector value type.
Definition at line 394 of file MachineValueType.h.
References FIRST_VECTOR_VALUETYPE, LAST_VECTOR_VALUETYPE, and SimpleTy.
Referenced by llvm::PPCTargetLowering::allowsMisalignedMemoryAccesses(), llvm::AMDGPUTargetLowering::analyzeFormalArgumentsCompute(), canonicalizeBitSelect(), CC_RISCV(), CC_RISCV_FastCC(), CC_X86_32_VectorCall(), CC_X86_64_VectorCall(), changeTypeToInteger(), combineAndnp(), combineX86ShuffleChain(), combineX86ShufflesRecursively(), constructRetValue(), convertLocVTToValVT(), convertValVTToLocVT(), llvm::X86TTIImpl::getArithmeticReductionCost(), getAVX512Node(), llvm::X86TTIImpl::getCmpSelInstrCost(), getCopyFromParts(), getCopyToPartsVector(), llvm::X86TTIImpl::getInterleavedMemoryOpCost(), llvm::AArch64TTIImpl::getIntrinsicInstrCost(), llvm::X86TTIImpl::getIntrinsicInstrCost(), llvm::getLLTForMVT(), getMaskTypeFor(), getMemCmpLoad(), llvm::X86TTIImpl::getMinMaxReductionCost(), llvm::PPCTargetLowering::getRegForInlineAsmConstraint(), llvm::RISCVTargetLowering::getRegForInlineAsmConstraint(), llvm::X86TargetLowering::getRegForInlineAsmConstraint(), llvm::X86TTIImpl::getReplicationShuffleCost(), getScalarType(), getScalarValueForVectorElement(), llvm::X86TargetLowering::getSetCCResultType(), llvm::X86TTIImpl::getShuffleCost(), llvm::CallLowering::ValueHandler::getStackValueStoreType(), getTargetVShiftNode(), llvm::TargetLoweringBase::getTypeConversion(), llvm::HexagonSubtarget::isHVXElementType(), isValueTypeInRegForCC(), llvm::LLT::LLT(), LowerADDSAT_SUBSAT(), llvm::X86TargetLowering::LowerAsmOutputForConstraint(), LowerAVXExtend(), LowerBITCAST(), LowerBITREVERSE_XOP(), llvm::RISCVTargetLowering::LowerCall(), LowerCTLZ(), LowerCTTZ(), LowerFABSorFNEG(), LowerFCOPYSIGN(), llvm::RISCVTargetLowering::LowerFormalArguments(), lowerFP_TO_INT_SAT(), lowerFPToIntToFP(), lowerFTRUNC_FCEIL_FFLOOR_FROUND(), LowerFunnelShift(), LowerLoad(), LowerMINMAX(), LowerMULO(), llvm::RISCVTargetLowering::LowerOperation(), llvm::AArch64CallLowering::lowerReturn(), LowerRotate(), llvm::HexagonTargetLowering::LowerSETCC(), LowerShift(), lowerShuffleAsTruncBroadcast(), LowerSIGN_EXTEND(), llvm::AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(), lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND(), lowerX86FPLogicOp(), performConcatVectorsCombine(), preAssignMask(), promoteXINT_TO_FP(), llvm::X86TargetLowering::ReplaceNodeResults(), llvm::X86TargetLowering::SimplifyDemandedBitsForTargetNode(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), llvm::splitVectorType(), and VerifyVectorType().
◆ knownBitsGE()
Return true if we know at compile time this has more than or the same bits as VT.
Definition at line 1201 of file MachineValueType.h.
References getSizeInBits(), and llvm::details::FixedOrScalableQuantity< TypeSize, uint64_t >::isKnownGE().
Referenced by bitsGE().
◆ knownBitsGT()
Return true if we know at compile time this has more bits than VT.
Definition at line 1195 of file MachineValueType.h.
References getSizeInBits(), and llvm::details::FixedOrScalableQuantity< TypeSize, uint64_t >::isKnownGT().
Referenced by bitsGT().
◆ knownBitsLE()
Return true if we know at compile time this has fewer than or the same bits as VT.
Definition at line 1212 of file MachineValueType.h.
References getSizeInBits(), and llvm::details::FixedOrScalableQuantity< TypeSize, uint64_t >::isKnownLE().
Referenced by bitsLE().
◆ knownBitsLT()
Return true if we know at compile time this has fewer bits than VT.
Definition at line 1206 of file MachineValueType.h.
References getSizeInBits(), and llvm::details::FixedOrScalableQuantity< TypeSize, uint64_t >::isKnownLT().
Referenced by bitsLT().
◆ operator!=()
Definition at line 351 of file MachineValueType.h.
References SimpleTy.
◆ operator<()
Definition at line 349 of file MachineValueType.h.
References SimpleTy.
◆ operator<=()
Definition at line 353 of file MachineValueType.h.
References SimpleTy.
◆ operator==()
Definition at line 350 of file MachineValueType.h.
References SimpleTy.
◆ operator>()
Definition at line 348 of file MachineValueType.h.
References SimpleTy.
◆ operator>=()
Definition at line 352 of file MachineValueType.h.
References SimpleTy.
◆ print()
| void MVT::print | ( | raw_ostream & | OS | ) | const |
Implement operator<<.
Definition at line 638 of file ValueTypes.cpp.
References llvm::EVT::getEVTString(), and OS.
Referenced by dump(), and llvm::operator<<().
◆ scalable_vector_valuetypes()
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inlinestatic |
Definition at line 1563 of file MachineValueType.h.
References llvm::enum_seq_inclusive(), FIRST_SCALABLE_VECTOR_VALUETYPE, llvm::force_iteration_on_noniterable_enum, and LAST_SCALABLE_VECTOR_VALUETYPE.
Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering().
◆ vector_valuetypes()
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Definition at line 1551 of file MachineValueType.h.
References llvm::enum_seq_inclusive(), FIRST_VECTOR_VALUETYPE, llvm::force_iteration_on_noniterable_enum, and LAST_VECTOR_VALUETYPE.
Referenced by findMemType().
Member Data Documentation
◆ SimpleTy
| SimpleValueType llvm::MVT::SimpleTy = INVALID_SIMPLE_VALUE_TYPE |
Definition at line 343 of file MachineValueType.h.
Referenced by AddCombineBUILD_VECTORToVPADDL(), llvm::TargetLoweringBase::AddPromotedToType(), llvm::TargetLoweringBase::addRegisterClass(), llvm::ARMTargetLowering::allowsMisalignedMemoryAccesses(), llvm::MipsSETargetLowering::allowsMisalignedMemoryAccesses(), AVRDAGToDAGISel::select< ISD::LOAD >(), CC_AArch64_Custom_Block(), CC_AIX(), CC_ARM_AAPCS_Custom_Aggregate(), changeVectorElementType(), changeVectorElementTypeToInteger(), combineBitcastvxi1(), llvm::VETargetLowering::combineSelectCC(), createVariablePermute(), llvm::SITargetLowering::denormalsEnabledForType(), llvm::SelectionDAG::EVTToAPFloatSemantics(), llvm::TargetLowering::expandBSWAP(), llvm::TargetLowering::expandVPBSWAP(), llvm::TargetLowering::findOptimalMemOpLowering(), llvm::TargetLoweringBase::findRepresentativeClass(), llvm::ARMTargetLowering::findRepresentativeClass(), llvm::X86TargetLowering::findRepresentativeClass(), foldVectorXorShiftIntoCmp(), llvm::R600RegisterInfo::getCFGStructurizerRegClass(), llvm::TargetLoweringBase::getCondCodeAction(), getContainerForFixedLengthVector(), llvm::EVT::getEVTString(), getExtensionTo64Bits(), getIEEEProperties(), getImplicitScaleFactor(), getLdStRegType(), llvm::TargetLoweringBase::getLoadExtAction(), llvm::TargetLoweringBase::getNumRegisters(), llvm::TargetLoweringBase::getOperationAction(), llvm::RTLIB::getOUTLINE_ATOMIC(), getPackedSVEVectorVT(), getPredicateForFixedLengthVector(), llvm::TargetLoweringBase::getRegClassFor(), llvm::SITargetLowering::getRegForInlineAsmConstraint(), llvm::HexagonTargetLowering::getRegForInlineAsmConstraint(), llvm::M68kTargetLowering::getRegForInlineAsmConstraint(), llvm::RISCVTargetLowering::getRegForInlineAsmConstraint(), llvm::X86TargetLowering::getRegForInlineAsmConstraint(), llvm::TargetLoweringBase::getRegisterType(), llvm::TargetLoweringBase::getRepRegClassCostFor(), llvm::TargetLoweringBase::getRepRegClassFor(), getScalableVectorVT(), llvm::TargetLoweringBase::getSetCCResultType(), getSizeInBits(), getSVEContainerType(), llvm::TargetLoweringBase::getTruncStoreAction(), llvm::TargetLoweringBase::ValueTypeActionImpl::getTypeAction(), llvm::TargetLoweringBase::getTypeConversion(), llvm::EVT::getTypeForEVT(), llvm::TargetLoweringBase::getTypeToPromoteTo(), llvm::SelectionDAG::getValueType(), getVectorElementType(), getVectorMinNumElements(), getVectorTyFromPredicateVector(), getVectorVT(), getVPTESTMOpc(), is1024BitVector(), is128BitVector(), is16BitVector(), is2048BitVector(), is256BitVector(), is32Bit(), is32BitVector(), is512BitVector(), is64BitVector(), isConstantSplatVectorMaskForType(), isFixedLengthVector(), isFloatingPoint(), llvm::AArch64TargetLowering::isFMAFasterThanFMulAndFAdd(), llvm::SITargetLowering::isFMAFasterThanFMulAndFAdd(), llvm::LoongArchTargetLowering::isFMAFasterThanFMulAndFAdd(), llvm::RISCVTargetLowering::isFMAFasterThanFMulAndFAdd(), llvm::SystemZTargetLowering::isFMAFasterThanFMulAndFAdd(), llvm::X86TargetLowering::isFMAFasterThanFMulAndFAdd(), llvm::ARMTargetLowering::isFNegFree(), llvm::PPCTargetLowering::isFPImmLegal(), isInteger(), isLegalAddressImmediate(), llvm::ARMTargetLowering::isLegalAddressingMode(), isLegalT1AddressImmediate(), isLegalT2AddressImmediate(), llvm::ARMTargetLowering::isLegalT2ScaledAddressingMode(), isOverloaded(), IsPTXVectorType(), isScalableTargetExtVT(), isScalableVector(), isScalarInteger(), llvm::TargetLoweringBase::isTypeLegal(), isValid(), llvm::HexagonInstrInfo::isValidAutoIncImm(), isValidIndexedLoad(), isVector(), llvm::ARMTargetLowering::isZExtFree(), llvm::X86TargetLowering::isZExtFree(), llvm::XCoreTargetLowering::isZExtFree(), lower128BitShuffle(), lower1BitShuffle(), lower256BitShuffle(), lower512BitShuffle(), LowerADDSUBSAT(), llvm::SystemZTargetLowering::LowerFormalArguments(), lowerRegToMasks(), lowerShuffleAsBlend(), lowerUINT_TO_FP_vec(), operator!=(), llvm::EVT::operator!=(), operator<(), operator<=(), operator==(), operator>(), operator>=(), performUzpCombine(), performVSelectCombine(), ReplaceINTRINSIC_W_CHAIN(), ReplaceLoadVector(), llvm::RISCVDAGToDAGISel::Select(), llvm::HexagonDAGToDAGISel::SelectIndexedLoad(), llvm::HexagonDAGToDAGISel::SelectIndexedStore(), selectUmullSmull(), llvm::TargetLoweringBase::setCondCodeAction(), llvm::TargetLoweringBase::setLoadExtAction(), llvm::TargetLoweringBase::setOperationAction(), llvm::TargetLoweringBase::setTruncStoreAction(), llvm::TargetLoweringBase::ValueTypeActionImpl::setTypeAction(), llvm::ARMTargetLowering::shouldConvertFpToSat(), llvm::RISCVTargetLowering::shouldConvertFpToSat(), llvm::X86InstrInfo::shouldScheduleLoadsNear(), unpackFromRegLoc(), usePartialVectorLoads(), useRVVForFixedLengthVectorVT(), llvm::AArch64TargetLowering::useSVEForFixedLengthVectorVT(), X86ChooseCmpImmediateOpcode(), and X86ChooseCmpOpcode().
The documentation for this class was generated from the following files:
- include/llvm/Support/MachineValueType.h
- lib/CodeGen/ValueTypes.cpp
