LLVM 18.0.0git
|
#include "llvm/CodeGen/MachineValueType.h"
Public Types | |
enum | SimpleValueType : uint8_t { INVALID_SIMPLE_VALUE_TYPE = 0 , VALUETYPE_SIZE = LAST_VALUETYPE + 1 , MAX_ALLOWED_VALUETYPE = 224 } |
Public Member Functions | |
constexpr | MVT ()=default |
constexpr | MVT (SimpleValueType SVT) |
bool | operator> (const MVT &S) const |
bool | operator< (const MVT &S) const |
bool | operator== (const MVT &S) const |
bool | operator!= (const MVT &S) const |
bool | operator>= (const MVT &S) const |
bool | operator<= (const MVT &S) const |
void | dump () const |
Support for debugging, callable in GDB: VT.dump() | |
void | print (raw_ostream &OS) const |
Implement operator<<. | |
bool | isValid () const |
Return true if this is a valid simple valuetype. | |
bool | isFloatingPoint () const |
Return true if this is a FP or a vector FP type. | |
bool | isInteger () const |
Return true if this is an integer or a vector integer type. | |
bool | isScalarInteger () const |
Return true if this is an integer, not including vectors. | |
bool | isVector () const |
Return true if this is a vector value type. | |
bool | isScalableVector () const |
Return true if this is a vector value type where the runtime length is machine dependent. | |
bool | isScalableTargetExtVT () const |
Return true if this is a custom target type that has a scalable size. | |
bool | isScalableVT () const |
Return true if the type is a scalable type. | |
bool | isFixedLengthVector () const |
bool | is16BitVector () const |
Return true if this is a 16-bit vector type. | |
bool | is32BitVector () const |
Return true if this is a 32-bit vector type. | |
bool | is64BitVector () const |
Return true if this is a 64-bit vector type. | |
bool | is128BitVector () const |
Return true if this is a 128-bit vector type. | |
bool | is256BitVector () const |
Return true if this is a 256-bit vector type. | |
bool | is512BitVector () const |
Return true if this is a 512-bit vector type. | |
bool | is1024BitVector () const |
Return true if this is a 1024-bit vector type. | |
bool | is2048BitVector () const |
Return true if this is a 2048-bit vector type. | |
bool | isOverloaded () const |
Return true if this is an overloaded type for TableGen. | |
MVT | changeVectorElementTypeToInteger () const |
Return a vector with the same number of elements as this vector, but with the element type converted to an integer type with the same bitwidth. | |
MVT | changeVectorElementType (MVT EltVT) const |
Return a VT for a vector type whose attributes match ourselves with the exception of the element type that is chosen by the caller. | |
MVT | changeTypeToInteger () |
Return the type converted to an equivalently sized integer or vector with integer element type. | |
MVT | getHalfNumVectorElementsVT () const |
Return a VT for a vector type with the same element type but half the number of elements. | |
MVT | getDoubleNumVectorElementsVT () const |
bool | isPow2VectorType () const |
Returns true if the given vector is a power of 2. | |
MVT | getPow2VectorType () const |
Widens the length of the given vector MVT up to the nearest power of 2 and returns that type. | |
MVT | getScalarType () const |
If this is a vector, return the element type, otherwise return this. | |
MVT | getVectorElementType () const |
unsigned | getVectorMinNumElements () const |
Given a vector type, return the minimum number of elements it contains. | |
ElementCount | getVectorElementCount () const |
unsigned | getVectorNumElements () const |
TypeSize | getSizeInBits () const |
Returns the size of the specified MVT in bits. | |
uint64_t | getFixedSizeInBits () const |
Return the size of the specified fixed width value type in bits. | |
uint64_t | getScalarSizeInBits () const |
TypeSize | getStoreSize () const |
Return the number of bytes overwritten by a store of the specified value type. | |
uint64_t | getScalarStoreSize () const |
TypeSize | getStoreSizeInBits () const |
Return the number of bits overwritten by a store of the specified value type. | |
bool | isByteSized () const |
Returns true if the number of bits for the type is a multiple of an 8-bit byte. | |
bool | knownBitsGT (MVT VT) const |
Return true if we know at compile time this has more bits than VT. | |
bool | knownBitsGE (MVT VT) const |
Return true if we know at compile time this has more than or the same bits as VT. | |
bool | knownBitsLT (MVT VT) const |
Return true if we know at compile time this has fewer bits than VT. | |
bool | knownBitsLE (MVT VT) const |
Return true if we know at compile time this has fewer than or the same bits as VT. | |
bool | bitsGT (MVT VT) const |
Return true if this has more bits than VT. | |
bool | bitsGE (MVT VT) const |
Return true if this has no less bits than VT. | |
bool | bitsLT (MVT VT) const |
Return true if this has less bits than VT. | |
bool | bitsLE (MVT VT) const |
Return true if this has no more bits than VT. | |
Static Public Member Functions | |
static MVT | getFloatingPointVT (unsigned BitWidth) |
static MVT | getIntegerVT (unsigned BitWidth) |
static MVT | getVectorVT (MVT VT, unsigned NumElements) |
static MVT | getScalableVectorVT (MVT VT, unsigned NumElements) |
static MVT | getVectorVT (MVT VT, unsigned NumElements, bool IsScalable) |
static MVT | getVectorVT (MVT VT, ElementCount EC) |
static MVT | getVT (Type *Ty, bool HandleUnknown=false) |
Return the value type corresponding to the specified type. | |
static auto | all_valuetypes () |
SimpleValueType Iteration. | |
static auto | integer_valuetypes () |
static auto | fp_valuetypes () |
static auto | vector_valuetypes () |
static auto | fixedlen_vector_valuetypes () |
static auto | scalable_vector_valuetypes () |
static auto | integer_fixedlen_vector_valuetypes () |
static auto | fp_fixedlen_vector_valuetypes () |
static auto | integer_scalable_vector_valuetypes () |
static auto | fp_scalable_vector_valuetypes () |
Public Attributes | |
SimpleValueType | SimpleTy = INVALID_SIMPLE_VALUE_TYPE |
Every type that is supported natively by some processor targeted by LLVM occurs here. This means that any legal value type can be represented by an MVT.
Definition at line 34 of file MachineValueType.h.
enum llvm::MVT::SimpleValueType : uint8_t |
Enumerator | |
---|---|
INVALID_SIMPLE_VALUE_TYPE | |
VALUETYPE_SIZE | |
MAX_ALLOWED_VALUETYPE |
Definition at line 36 of file MachineValueType.h.
|
constexprdefault |
Referenced by getVT().
|
inlineconstexpr |
Definition at line 61 of file MachineValueType.h.
|
inlinestatic |
SimpleValueType Iteration.
Definition at line 487 of file MachineValueType.h.
References llvm::enum_seq_inclusive(), and llvm::force_iteration_on_noniterable_enum.
Referenced by llvm::TargetLoweringBase::initActions().
Return true if this has no less bits than VT.
Definition at line 407 of file MachineValueType.h.
References assert(), isScalableVector(), and knownBitsGE().
Return true if this has more bits than VT.
Definition at line 400 of file MachineValueType.h.
References assert(), isScalableVector(), and knownBitsGT().
Referenced by getSmallestVTForIndex(), getVRGatherIndexType(), LowerFCOPYSIGN(), and lowerVECTOR_SHUFFLE().
Return true if this has no more bits than VT.
Definition at line 421 of file MachineValueType.h.
References assert(), isScalableVector(), and knownBitsLE().
Referenced by getMaskNode(), llvm::SITargetLowering::getPreferredVectorAction(), lowerBuildVectorOfConstants(), lowerReductionSeq(), lowerScalarInsert(), and llvm::RISCVTargetLowering::PerformDAGCombine().
Return true if this has less bits than VT.
Definition at line 414 of file MachineValueType.h.
References assert(), isScalableVector(), and knownBitsLT().
Referenced by LowerFCOPYSIGN(), lowerVectorIntrinsicScalars(), and llvm::RISCVTargetLowering::PerformDAGCombine().
|
inline |
Return the type converted to an equivalently sized integer or vector with integer element type.
Similar to changeVectorElementTypeToInteger, but also handles scalars.
Definition at line 213 of file MachineValueType.h.
References changeVectorElementTypeToInteger(), getIntegerVT(), getSizeInBits(), and isVector().
Referenced by llvm::EVT::changeTypeToInteger(), getVRGatherIndexType(), getWideningInterleave(), lowerShuffleWithPERMV(), lowerVECTOR_SHUFFLE(), and matchBinaryShuffle().
Return a VT for a vector type whose attributes match ourselves with the exception of the element type that is chosen by the caller.
Definition at line 203 of file MachineValueType.h.
References assert(), getVectorElementCount(), getVectorVT(), INVALID_SIMPLE_VALUE_TYPE, and SimpleTy.
Referenced by llvm::EVT::changeVectorElementType(), getVRGatherIndexType(), lowerBUILD_VECTOR(), lowerBuildVectorOfConstants(), lowerBuildVectorViaDominantValues(), lowerFP_TO_INT_SAT(), llvm::RISCVTargetLowering::LowerOperation(), lowerVECTOR_SHUFFLE(), LowerVectorAllEqual(), matchUnaryShuffle(), performCONCAT_VECTORSCombine(), promoteXINT_TO_FP(), and widenVectorOpsToi8().
|
inline |
Return a vector with the same number of elements as this vector, but with the element type converted to an integer type with the same bitwidth.
Definition at line 192 of file MachineValueType.h.
References assert(), getIntegerVT(), getSizeInBits(), getVectorElementCount(), getVectorElementType(), getVectorVT(), INVALID_SIMPLE_VALUE_TYPE, and SimpleTy.
Referenced by changeTypeToInteger(), llvm::EVT::changeVectorElementTypeToInteger(), combineSetCCMOVMSK(), getDeinterleaveViaVNSRL(), LowerBUILD_VECTORvXbf16(), lowerBuildVectorOfConstants(), lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND(), and lowerVectorStrictFTRUNC_FCEIL_FFLOOR_FROUND().
void MVT::dump | ( | ) | const |
Support for debugging, callable in GDB: VT.dump()
Definition at line 633 of file ValueTypes.cpp.
References llvm::dbgs(), and print().
|
inlinestatic |
Definition at line 509 of file MachineValueType.h.
References llvm::enum_seq_inclusive(), and llvm::force_iteration_on_noniterable_enum.
Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering(), llvm::ARMTargetLowering::ARMTargetLowering(), llvm::HexagonTargetLowering::HexagonTargetLowering(), llvm::MipsSETargetLowering::MipsSETargetLowering(), llvm::NVPTXTargetLowering::NVPTXTargetLowering(), llvm::PPCTargetLowering::PPCTargetLowering(), llvm::SystemZTargetLowering::SystemZTargetLowering(), llvm::WebAssemblyTargetLowering::WebAssemblyTargetLowering(), and llvm::X86TargetLowering::X86TargetLowering().
|
inlinestatic |
Definition at line 527 of file MachineValueType.h.
References llvm::enum_seq_inclusive(), and llvm::force_iteration_on_noniterable_enum.
Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering(), llvm::MipsTargetLowering::MipsTargetLowering(), and llvm::RISCVTargetLowering::RISCVTargetLowering().
|
inlinestatic |
Definition at line 539 of file MachineValueType.h.
References llvm::enum_seq_inclusive(), and llvm::force_iteration_on_noniterable_enum.
|
inlinestatic |
Definition at line 498 of file MachineValueType.h.
References llvm::enum_seq_inclusive(), and llvm::force_iteration_on_noniterable_enum.
Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering(), llvm::ARMTargetLowering::ARMTargetLowering(), llvm::HexagonTargetLowering::HexagonTargetLowering(), llvm::TargetLoweringBase::initActions(), llvm::MipsTargetLowering::MipsTargetLowering(), llvm::PPCTargetLowering::PPCTargetLowering(), llvm::SparcTargetLowering::SparcTargetLowering(), and llvm::SystemZTargetLowering::SystemZTargetLowering().
|
inline |
Definition at line 230 of file MachineValueType.h.
References getVectorElementCount(), getVectorElementType(), and getVectorVT().
Referenced by combinePTESTCC(), and getSmallestVTForIndex().
|
inline |
Return the size of the specified fixed width value type in bits.
The function will assert if the type is scalable.
Definition at line 338 of file MachineValueType.h.
References llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getFixedValue(), and getSizeInBits().
Referenced by CC_AIX(), combineINSERT_SUBVECTOR(), combineTargetShuffle(), llvm::TargetLoweringBase::computeRegisterProperties(), getCopyToPartsVector(), is1024BitVector(), is128BitVector(), is16BitVector(), is2048BitVector(), is256BitVector(), is32BitVector(), is512BitVector(), is64BitVector(), LowerEXTEND_VECTOR_INREG(), LowerFunnelShift(), LowerVSETCC(), MatchingStackOffset(), truncateScalarIntegerArg(), useRVVForFixedLengthVectorVT(), and widenSubVector().
Definition at line 427 of file MachineValueType.h.
References llvm_unreachable.
Referenced by combineBitcast(), combineCVTP2I_CVTTP2I(), combinePredicateReduction(), combinePTESTCC(), combineSetCCMOVMSK(), combineX86ShuffleChain(), combineX86ShufflesConstants(), EltsFromConsecutiveLoads(), llvm::EVT::getFloatingPointVT(), lower256BitShuffle(), lowerVECTOR_SHUFFLE(), and tryWidenMaskForShuffle().
|
inline |
Return a VT for a vector type with the same element type but half the number of elements.
Definition at line 221 of file MachineValueType.h.
References assert(), getVectorElementCount(), getVectorElementType(), and getVectorVT().
Referenced by canonicalizeShuffleMaskWithHorizOp(), combineSetCCMOVMSK(), combineTargetShuffle(), llvm::RISCVTargetLowering::decomposeSubvectorInsertExtractToSubRegs(), getHopForBuildVector(), getShuffleHalfVectors(), LowerAVXCONCAT_VECTORS(), LowerAVXExtend(), LowerCONCAT_VECTORSvXi1(), LowerEXTEND_VECTOR_INREG(), lowerShuffleWithUndefHalf(), LowerSIGN_EXTEND(), LowerTruncateVecPack(), LowerTruncateVecPackWithSignBits(), lowerV2X128Shuffle(), lowerVECTOR_SHUFFLE(), and llvm::RISCVTargetLowering::PerformDAGCombine().
Definition at line 437 of file MachineValueType.h.
References INVALID_SIMPLE_VALUE_TYPE.
Referenced by changeTypeToInteger(), changeVectorElementTypeToInteger(), combineBitcast(), combineConcatVectorOps(), combineX86INT_TO_FP(), combineX86ShuffleChain(), combineX86ShufflesConstants(), llvm::computeSignatureVTs(), EltsFromConsecutiveLoads(), ExtractBitFromMaskVector(), llvm::SelectionDAG::getBitcastedAnyExtOrTrunc(), llvm::SelectionDAG::getBitcastedSExtOrTrunc(), llvm::SelectionDAG::getBitcastedZExtOrTrunc(), getDeinterleaveViaVNSRL(), llvm::EVT::getIntegerVT(), llvm::getMVTForLLT(), llvm::RISCVTargetLowering::getOptimalMemOpType(), getPermuteNode(), llvm::TargetLoweringBase::getPointerMemTy(), llvm::TargetLoweringBase::getPointerTy(), llvm::AArch64TargetLowering::getPointerTy(), getRegistersForValue(), llvm::TargetLoweringBase::getScalarShiftAmountTy(), llvm::M68kTargetLowering::getScalarShiftAmountTy(), llvm::ARMTargetLowering::getTgtMemIntrinsic(), getVectorBitwiseReduce(), llvm::SPIRVTargetLowering::getVectorIdxTy(), getVT(), getWideningInterleave(), llvm::TargetLoweringBase::hasFastEqualityCompare(), llvm::X86TargetLowering::hasFastEqualityCompare(), llvm::TargetLoweringBase::initActions(), insert1BitVector(), InsertBitToMaskVector(), is128BitUnpackShuffleMask(), llvm::SystemZVectorConstantInfo::isVectorConstantLegal(), LowerABD(), LowerBUILD_VECTORvXi1(), lowerBuildVectorAsBroadcast(), lowerBuildVectorOfConstants(), LowerCTPOP(), lowerFCOPYSIGN64(), LowerFunnelShift(), llvm::RISCVTargetLowering::LowerOperation(), LowerRotate(), llvm::HexagonTargetLowering::LowerSETCC(), lowerShuffleAsBlend(), lowerShuffleAsPermuteAndUnpack(), lowerShuffleAsSpecificZeroOrAnyExtend(), lowerShuffleAsVTRUNC(), lowerShuffleToEXPAND(), lowerShuffleWithPACK(), lowerShuffleWithVPMOV(), LowerTruncateVecI1(), llvm::HexagonTargetLowering::LowerUnalignedLoad(), lowerVECTOR_SHUFFLE(), LowerVECTOR_SHUFFLE(), lowerVECTOR_SHUFFLEAsRotate(), LowerVectorCTLZInRegLUT(), llvm::HexagonTargetLowering::LowerVSELECT(), lowerX86FPLogicOp(), matchPERM(), matchShuffleAsBitRotate(), matchShuffleAsShift(), matchShuffleAsVTRUNC(), matchShuffleWithPACK(), matchUnaryPermuteShuffle(), matchUnaryShuffle(), memsetStore(), performBitcastCombine(), performCONCAT_VECTORSCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), PerformEXTRACTCombine(), performSETCCCombine(), PerformVECREDUCE_ADDCombine(), PerformVQDMULHCombine(), llvm::X86TargetLowering::ReplaceNodeResults(), scaleVectorType(), llvm::AArch64TargetLowering::shouldTransformSignedTruncationCheck(), llvm::X86TargetLowering::shouldTransformSignedTruncationCheck(), ShrinkLoadReplaceStoreWithStore(), llvm::X86TargetLowering::SimplifyDemandedBitsForTargetNode(), skipExtensionForVectorMULL(), SkipExtensionForVMULL(), llvm::SparcTargetLowering::SparcTargetLowering(), llvm::HexagonDAGToDAGISel::StoreInstrForLoadIntrinsic(), llvm::SystemZTargetLowering::SystemZTargetLowering(), TryCombineBaseUpdate(), tryWidenMaskForShuffle(), unpackFromMemLoc(), vectorToScalarBitmask(), and llvm::X86TargetLowering::X86TargetLowering().
|
inline |
Widens the length of the given vector MVT up to the nearest power of 2 and returns that type.
Definition at line 244 of file MachineValueType.h.
References llvm::ElementCount::get(), llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getKnownMinValue(), getVectorElementCount(), getVectorElementType(), getVectorVT(), isPow2VectorType(), llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::isScalable(), and llvm::Log2_32_Ceil().
Referenced by llvm::TargetLoweringBase::computeRegisterProperties().
Definition at line 457 of file MachineValueType.h.
References INVALID_SIMPLE_VALUE_TYPE.
Referenced by getContainerForFixedLengthVector(), getLMUL1VT(), and getVectorVT().
|
inline |
Definition at line 342 of file MachineValueType.h.
References llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getFixedValue(), getScalarType(), and getSizeInBits().
Referenced by canonicalizeBitSelect(), llvm::RISCV::CC_RISCV(), llvm::RISCV::CC_RISCV_FastCC(), combineAddOfPMADDWD(), combineAndnp(), combineBitOpWithPACK(), combineConcatVectorOps(), combineCVTP2I_CVTTP2I(), combineMOVMSK(), combineSetCCMOVMSK(), combineStore(), combineTargetShuffle(), combineTESTP(), combineVEXTRACT_STORE(), combineX86INT_TO_FP(), combineX86ShuffleChain(), llvm::X86TargetLowering::ComputeNumSignBitsForTargetNode(), llvm::TargetLoweringBase::computeRegisterProperties(), createPackShuffleMask(), createVariablePermute(), DecodePALIGNRMask(), expandFP_TO_UINT_SSE(), llvm::X86TTIImpl::getArithmeticReductionCost(), getAVX512Node(), getAVX512TruncNode(), llvm::X86TTIImpl::getCmpSelInstrCost(), getConstantVector(), getConstVector(), llvm::RegsForValue::getCopyFromRegs(), getDeinterleaveViaVNSRL(), getFauxShuffleMask(), llvm::AArch64TTIImpl::getIntrinsicInstrCost(), getMemCmpLoad(), llvm::X86TTIImpl::getMinMaxReductionCost(), getPack(), llvm::PPCTargetLowering::getPreferredVectorAction(), llvm::SystemZTargetLowering::getPreferredVectorAction(), getPSHUFShuffleMask(), llvm::X86TTIImpl::getReplicationShuffleCost(), getScalarValueForVectorElement(), llvm::RISCVTTIImpl::getShuffleCost(), getSmallestVTForIndex(), getTargetShuffleMask(), getTargetVShiftNode(), getVectorTypeBreakdownMVT(), getVRGatherIndexType(), getWideningInterleave(), is128BitLaneCrossingShuffleMask(), isDeinterleaveShuffle(), isHorizontalBinOp(), isInterleaveShuffle(), isRepeatedShuffleMask(), isRepeatedTargetShuffleMask(), lower256BitShuffle(), LowerABD(), LowerADDSAT_SUBSAT(), LowerBITREVERSE_XOP(), lowerBuildVectorAsBroadcast(), lowerBuildVectorOfConstants(), lowerBuildVectorToBitOp(), LowerCTTZ(), LowerEXTEND_VECTOR_INREG(), LowerFABSorFNEG(), LowerFCOPYSIGN(), LowerFunnelShift(), LowerINTRINSIC_W_CHAIN(), LowerMGATHER(), LowerMLOAD(), LowerMSCATTER(), LowerMSTORE(), LowerRotate(), LowerShift(), LowerShiftByScalarImmediate(), lowerShuffleAsBitRotate(), lowerShuffleAsBlend(), lowerShuffleAsBlendAndPermute(), lowerShuffleAsBroadcast(), lowerShuffleAsByteRotateAndPermute(), lowerShuffleAsByteShiftMask(), lowerShuffleAsDecomposedShuffleMerge(), lowerShuffleAsElementInsertion(), lowerShuffleAsLanePermuteAndRepeatedMask(), lowerShuffleAsPermuteAndUnpack(), lowerShuffleAsRepeatedMaskAndLanePermute(), lowerShuffleAsShift(), lowerShuffleAsSpecificZeroOrAnyExtend(), lowerShuffleAsVTRUNC(), lowerShuffleAsZeroOrAnyExtend(), lowerShuffleOfExtractsAsVperm(), lowerShuffleWithPACK(), lowerShuffleWithPSHUFB(), lowerShuffleWithVPMOV(), LowerTruncateVecI1(), lowerV4X128Shuffle(), lowerVECTOR_SHUFFLE(), LowerVectorCTLZInRegLUT(), lowerVectorIntrinsicScalars(), LowerVSETCC(), lowerX86FPLogicOp(), LowerZERO_EXTEND_Mask(), matchBinaryPermuteShuffle(), matchBinaryShuffle(), matchShuffleAsBlend(), matchShuffleAsEXTRQ(), matchShuffleAsINSERTQ(), matchShuffleAsVTRUNC(), matchShuffleWithPACK(), matchShuffleWithSHUFPD(), matchUnaryPermuteShuffle(), matchUnaryShuffle(), llvm::X86::mayFoldLoadIntoBroadcastFromMem(), llvm::RISCVTargetLowering::PerformDAGCombine(), performFP_TO_INTCombine(), PerformVQDMULHCombine(), processPSInputArgs(), scaleVectorType(), llvm::RISCVDAGToDAGISel::Select(), llvm::RISCVDAGToDAGISel::selectVLSEG(), llvm::RISCVDAGToDAGISel::selectVLSEGFF(), llvm::RISCVDAGToDAGISel::selectVLXSEG(), llvm::RISCVDAGToDAGISel::selectVSSEG(), llvm::RISCVDAGToDAGISel::selectVSXSEG(), llvm::X86TargetLowering::SimplifyDemandedBitsForTargetNode(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), and vectorizeExtractedCast().
|
inline |
Definition at line 359 of file MachineValueType.h.
References llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getFixedValue(), getScalarType(), and getStoreSize().
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
|
inline |
If this is a vector, return the element type, otherwise return this.
Definition at line 255 of file MachineValueType.h.
References getVectorElementType(), and isVector().
Referenced by llvm::AMDGPUTargetLowering::analyzeFormalArgumentsCompute(), combineConcatVectorOps(), combineEXTRACT_SUBVECTOR(), combineMOVMSK(), combineStore(), combineTargetShuffle(), constructDup(), createVariablePermute(), llvm::TargetLowering::expandBSWAP(), llvm::TargetLowering::expandVPBSWAP(), llvm::X86TTIImpl::getArithmeticReductionCost(), getAVX512Node(), getAVX512TruncNode(), getFauxShuffleMask(), getIEEEProperties(), llvm::SITargetLowering::getPreferredVectorAction(), llvm::NVPTXTargetLowering::getPreferredVectorAction(), llvm::X86TTIImpl::getReplicationShuffleCost(), getScalarSizeInBits(), getScalarStoreSize(), getTargetShuffleMask(), getTargetVShiftNode(), getVRGatherIndexType(), isInlineableLiteralOp16(), llvm::RISCVTargetLowering::isShuffleMaskLegal(), llvm::X86TargetLowering::isShuffleMaskLegal(), LowerBITREVERSE(), lowerBuildVectorAsBroadcast(), lowerBuildVectorToBitOp(), LowerMLOAD(), LowerMSTORE(), lowerShuffleAsBroadcast(), lowerShuffleAsVALIGN(), lowerShuffleAsVTRUNC(), llvm::AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(), lowerVECTOR_SHUFFLE(), lowerVECTOR_SHUFFLEAsRotate(), LowerVectorCTPOP(), matchUnaryShuffle(), scalarizeVectorStore(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), vectorizeExtractedCast(), and widenSubVector().
|
inline |
Returns the size of the specified MVT in bits.
If the value type is a scalable vector type, the scalable property will be set and the runtime size will be a positive integer multiple of the base size.
Definition at line 304 of file MachineValueType.h.
References assert(), INVALID_SIMPLE_VALUE_TYPE, llvm_unreachable, llvm::Other, SimpleTy, and VALUETYPE_SIZE.
Referenced by Analyze_CC_Sparc64_Full(), Analyze_CC_Sparc64_Half(), canonicalizeBitSelect(), CC_ARM_AAPCS_Custom_Aggregate(), CC_X86_32_VectorCall(), CC_X86_64_VectorCall(), changeTypeToInteger(), changeVectorElementTypeToInteger(), combineAndLoadToBZHI(), combineEXTRACT_SUBVECTOR(), combinePredicateReduction(), combinePTESTCC(), combineSetCCMOVMSK(), combineShiftRightArithmetic(), combineTargetShuffle(), combineVectorHADDSUB(), combineX86ShuffleChain(), combineX86ShufflesConstants(), combineX86ShufflesRecursively(), convertShiftLeftToScale(), createPackShuffleMask(), createShuffleStride(), createVariablePermute(), createVPDPBUSD(), DecodePALIGNRMask(), llvm::TargetLowering::expandUnalignedLoad(), llvm::TargetLowering::expandUnalignedStore(), llvm::FastISel::fastEmit_ri_(), finishStackBlock(), genShuffleBland(), getAVX512Node(), getAVX512TruncNode(), getCopyFromParts(), getCopyFromPartsVector(), getCopyToParts(), getCopyToPartsVector(), getFauxShuffleMask(), getFixedSizeInBits(), getFltSemantics(), getHopForBuildVector(), llvm::getLLTForMVT(), llvm::RISCVTargetLowering::getLMUL(), getLMUL1VT(), llvm::RISCVTargetLowering::getLMULCost(), llvm::TargetLoweringBase::getNumRegisters(), getPack(), llvm::HvxSelector::getPairVT(), llvm::PPCTargetLowering::getPreferredVectorAction(), getPromotedVectorElementType(), getPSHUFShuffleMask(), llvm::SITargetLowering::getRegForInlineAsmConstraint(), llvm::ARMTargetLowering::getRegForInlineAsmConstraint(), llvm::HexagonTargetLowering::getRegForInlineAsmConstraint(), llvm::SystemZTargetLowering::getRegForInlineAsmConstraint(), llvm::X86TargetLowering::getRegForInlineAsmConstraint(), getRegistersForValue(), llvm::RegsForValue::getRegsAndSizes(), getScalarSizeInBits(), getScalarValueForVectorElement(), llvm::X86TargetLowering::getSetCCResultType(), llvm::TargetLoweringBase::getShiftAmountTy(), llvm::X86TTIImpl::getShuffleCost(), llvm::HvxSelector::getSingleVT(), getStoreSize(), getTargetShuffleAndZeroables(), getTargetVShiftByConstNode(), getTargetVShiftNode(), llvm::HexagonSubtarget::getTypeAlignment(), llvm::TargetLoweringBase::getVaListSizeInBits(), llvm::AArch64TargetLowering::getVaListSizeInBits(), llvm::TargetLoweringBase::getVectorTypeBreakdown(), getZeroVector(), group2Shuffle(), hasBZHI(), insert1BitVector(), isByteSized(), IsElementEquivalent(), isHorizontalBinOp(), llvm::X86TargetLowering::isShuffleMaskLegal(), isSupportedType(), isTargetShuffleEquivalent(), llvm::RISCVTargetLowering::joinRegisterPartsIntoValue(), knownBitsGE(), knownBitsGT(), knownBitsLE(), knownBitsLT(), llvm::LLT::LLT(), llvm::X86TargetLowering::LowerAsmOutputForConstraint(), LowerAsSplatVectorLoad(), llvm::HexagonTargetLowering::LowerBITCAST(), LowerBITREVERSE_XOP(), llvm::HexagonTargetLowering::LowerBUILD_VECTOR(), lowerBUILD_VECTOR(), LowerBUILD_VECTORvXi1(), lowerBuildVectorAsBroadcast(), lowerBuildVectorOfConstants(), llvm::SystemZTargetLowering::LowerCall(), llvm::TargetLowering::LowerCallTo(), llvm::HexagonTargetLowering::LowerCONCAT_VECTORS(), LowerCTLZ(), LowerEXTEND_VECTOR_INREG(), LowerEXTRACT_VECTOR_ELT_SSE4(), llvm::HexagonTargetLowering::LowerFormalArguments(), llvm::VETargetLowering::LowerFormalArguments(), llvm::SparcTargetLowering::LowerFormalArguments_64(), lowerFP_TO_INT_SAT(), lowerFPToIntToFP(), LowerHorizontalByteSum(), LowerMGATHER(), LowerMLOAD(), LowerMSCATTER(), LowerMSTORE(), llvm::RISCVTargetLowering::LowerOperation(), LowerPARITY(), LowerSCALAR_TO_VECTOR(), llvm::HexagonTargetLowering::LowerSETCC(), lowerShuffleAsBlend(), lowerShuffleAsBlendOfPSHUFBs(), lowerShuffleAsByteRotate(), lowerShuffleAsByteRotateAndPermute(), lowerShuffleAsDecomposedShuffleMerge(), lowerShuffleAsElementInsertion(), lowerShuffleAsLanePermuteAndPermute(), lowerShuffleAsLanePermuteAndRepeatedMask(), lowerShuffleAsRepeatedMaskAndLanePermute(), lowerShuffleAsSplitOrBlend(), lowerShuffleAsTruncBroadcast(), lowerShuffleAsUNPCKAndPermute(), lowerShuffleAsZeroOrAnyExtend(), lowerShuffleWithPACK(), lowerShuffleWithPERMV(), lowerShuffleWithPSHUFB(), lowerShuffleWithUndefHalf(), LowerSIGN_EXTEND_Mask(), llvm::LanaiTargetLowering::LowerSRL_PARTS(), LowerTruncateVecI1(), LowerTruncateVecPack(), LowerTruncateVecPackWithSignBits(), llvm::HexagonTargetLowering::LowerUnalignedLoad(), llvm::HexagonTargetLowering::LowerVECTOR_SHIFT(), llvm::HexagonTargetLowering::LowerVECTOR_SHUFFLE(), lowerVECTOR_SHUFFLE(), LowerVectorAllEqual(), LowerVectorCTLZ_AVX512CDI(), LowerVectorCTPOP(), lowerVectorIntrinsicScalars(), llvm::HexagonTargetLowering::LowerVSELECT(), LowerVSETCC(), lowerX86FPLogicOp(), LowerZERO_EXTEND_Mask(), matchBinaryPermuteShuffle(), matchBinaryShuffle(), MatchingStackOffset(), matchShuffleAsBlend(), matchUnaryPermuteShuffle(), narrowExtractedVectorSelect(), llvm::TargetLowering::ParseConstraints(), performCONCAT_VECTORSCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), performFDivCombine(), performFpToIntCombine(), performScatterStoreCombine(), PerformTruncatingStoreCombine(), PerformVCVTCombine(), PerformVDIVCombine(), llvm::X86TargetLowering::ReplaceNodeResults(), llvm::HexagonDAGToDAGISel::SelectExtractSubvector(), llvm::HexagonDAGToDAGISel::SelectQ2V(), llvm::RISCVDAGToDAGISel::selectSExtBits(), llvm::LoongArchDAGToDAGISel::selectSExti32(), llvm::HexagonDAGToDAGISel::SelectV2Q(), llvm::HexagonDAGToDAGISel::SelectVAlign(), llvm::RISCVDAGToDAGISel::selectZExtBits(), llvm::LoongArchDAGToDAGISel::selectZExti32(), setGroupSize(), shouldTransformMulToShiftsAddsSubs(), splitAndLowerShuffle(), llvm::RISCVTargetLowering::splitValueIntoRegisterParts(), TryCombineBaseUpdate(), tryCombineShiftImm(), llvm::RISCVDAGToDAGISel::trySignedBitfieldExtract(), UnpackFromArgumentSlot(), and useRVVForFixedLengthVectorVT().
|
inline |
Return the number of bytes overwritten by a store of the specified value type.
If the value type is a scalable vector type, the scalable property will be set and the runtime size will be a positive integer multiple of the base size.
Definition at line 352 of file MachineValueType.h.
References llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getKnownMinValue(), getSizeInBits(), and llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::isScalable().
Referenced by llvm::analyzeArguments(), llvm::analyzeReturnValues(), CC_AIX(), CC_MipsO32(), llvm::RISCV::CC_RISCV(), llvm::RISCV::CC_RISCV_FastCC(), llvm::PPCTargetLowering::emitEHSjLjLongJmp(), llvm::PPCTargetLowering::emitEHSjLjSetJmp(), llvm::BasicTTIImplBase< T >::getInterleavedMemoryOpCost(), llvm::X86TTIImpl::getInterleavedMemoryOpCostAVX512(), llvm::RISCVTargetLowering::getOptimalMemOpType(), llvm::MSP430TargetLowering::getReturnAddressFrameIndex(), getScalarStoreSize(), llvm::X86TTIImpl::getShuffleCost(), getStoreSizeInBits(), llvm::SITargetLowering::LowerCall(), lowerShuffleAsBroadcast(), lowerV2X128Shuffle(), lowerVECTOR_SHUFFLE(), scalarizeVectorStore(), and llvm::RISCVDAGToDAGISel::Select().
|
inline |
Return the number of bits overwritten by a store of the specified value type.
If the value type is a scalable vector type, the scalable property will be set and the runtime size will be a positive integer multiple of the base size.
Definition at line 369 of file MachineValueType.h.
References getStoreSize().
Referenced by llvm::HexagonTargetLowering::LowerCall(), and llvm::HexagonTargetLowering::LowerFormalArguments().
|
inline |
Definition at line 286 of file MachineValueType.h.
References llvm::ElementCount::get(), getVectorMinNumElements(), and isScalableVector().
Referenced by changeVectorElementType(), changeVectorElementTypeToInteger(), llvm::TargetLoweringBase::computeRegisterProperties(), llvm::RISCVTargetLowering::computeVLMax(), llvm::RISCVTargetLowering::decomposeSubvectorInsertExtractToSubRegs(), getCopyToPartsVector(), getDeinterleaveViaVNSRL(), getDoubleNumVectorElementsVT(), getHalfNumVectorElementsVT(), llvm::getLLTForMVT(), getMaskTypeFor(), getPow2VectorType(), llvm::TargetLoweringBase::getPreferredVectorAction(), getVectorTypeBreakdownMVT(), getWideningInterleave(), llvm::LLT::LLT(), lowerFP_TO_INT_SAT(), llvm::RISCVTargetLowering::LowerOperation(), lowerVECTOR_SHUFFLE(), lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND(), lowerVectorIntrinsicScalars(), llvm::RISCVTargetLowering::RISCVTargetLowering(), llvm::RISCVDAGToDAGISel::Select(), llvm::RISCVDAGToDAGISel::selectVLXSEG(), llvm::RISCVDAGToDAGISel::selectVSXSEG(), and splatPartsI64WithVL().
|
inline |
Definition at line 259 of file MachineValueType.h.
References llvm_unreachable, and SimpleTy.
Referenced by changeVectorElementTypeToInteger(), combineBitcast(), combineEXTRACT_SUBVECTOR(), combineINSERT_SUBVECTOR(), combineShuffleToAddSubOrFMAddSub(), combineTargetShuffle(), llvm::TargetLoweringBase::computeRegisterProperties(), convertShiftLeftToScale(), ExtendToType(), getConstVector(), getContainerForFixedLengthVector(), getDeinterleaveViaVNSRL(), getDoubleNumVectorElementsVT(), getHalfNumVectorElementsVT(), llvm::X86TTIImpl::getIntrinsicInstrCost(), llvm::getLLTForMVT(), llvm::RISCVTargetLowering::getLMUL(), getLMUL1VT(), getPow2VectorType(), llvm::HexagonTargetLowering::getPreferredVectorAction(), llvm::X86TargetLowering::getPreferredVectorAction(), llvm::RISCVTargetLowering::getRegClassIDForVecVT(), getScalarType(), getScalarValueForVectorElement(), llvm::X86TargetLowering::getSetCCResultType(), llvm::X86TTIImpl::getShuffleCost(), getShuffleScalarElt(), getTargetVShiftByConstNode(), getTargetVShiftNode(), llvm::AArch64TargetLowering::getTgtMemIntrinsic(), llvm::X86TargetLowering::getTgtMemIntrinsic(), llvm::TargetLoweringBase::getTypeConversion(), getUnderlyingExtractedFromVec(), getVectorTypeBreakdownMVT(), getWideningInterleave(), getZeroVector(), incDecVectorConstant(), llvm::HexagonTargetLowering::isExtractSubvectorCheap(), llvm::HexagonSubtarget::isHVXElementType(), llvm::HexagonSubtarget::isHVXVectorType(), isLegalT2AddressImmediate(), llvm::RISCVTargetLowering::joinRegisterPartsIntoValue(), llvm::LLT::LLT(), LowerANY_EXTEND(), LowerAVXExtend(), LowerBITCAST(), lowerBitreverseShuffle(), lowerBUILD_VECTOR(), LowerBUILD_VECTORvXi1(), lowerBuildVectorOfConstants(), LowerBuildVectorv4x32(), LowerCONCAT_VECTORS(), llvm::HexagonTargetLowering::LowerCONCAT_VECTORS(), LowerEXTEND_VECTOR_INREG(), llvm::HexagonTargetLowering::LowerEXTRACT_VECTOR_ELT(), lowerFP_TO_INT_SAT(), LowerHorizontalByteSum(), LowerIntVSETCC_AVX512(), LowerLoad(), LowerMGATHER(), LowerMLOAD(), LowerMSCATTER(), llvm::RISCVTargetLowering::LowerOperation(), LowerSCALAR_TO_VECTOR(), llvm::HexagonTargetLowering::LowerSETCC(), lowerShuffleAsBitBlend(), lowerShuffleAsBitMask(), lowerShuffleAsBroadcast(), lowerShuffleAsElementInsertion(), lowerShuffleAsTruncBroadcast(), lowerShuffleWithUndefHalf(), LowerSIGN_EXTEND(), LowerSIGN_EXTEND_Mask(), LowerTruncateVecI1(), LowerTruncateVecPack(), LowerTruncateVecPackWithSignBits(), lowerV2X128Shuffle(), lowerV4X128Shuffle(), lowerV8I16GeneralSingleInputShuffle(), llvm::HexagonTargetLowering::LowerVECTOR_SHIFT(), llvm::HexagonTargetLowering::LowerVECTOR_SHUFFLE(), lowerVECTOR_SHUFFLE(), LowerVectorCTLZ(), LowerVectorCTLZ_AVX512CDI(), LowerVectorCTPOP(), LowerVectorCTPOPInRegLUT(), lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND(), lowerVectorIntrinsicScalars(), lowerVectorStrictFTRUNC_FCEIL_FFLOOR_FROUND(), llvm::HexagonTargetLowering::LowerVSELECT(), LowerVSETCC(), LowerVSETCCWithSUBUS(), LowerZERO_EXTEND(), LowerZERO_EXTEND_Mask(), matchSplatAsGather(), narrowExtractedVectorSelect(), performConcatVectorsCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), preAssignMask(), llvm::RISCVDAGToDAGISel::PreprocessISelDAG(), llvm::RISCVTargetLowering::ReplaceNodeResults(), llvm::X86TargetLowering::ReplaceNodeResults(), llvm::RISCVTargetLowering::RISCVTargetLowering(), scaleVectorType(), llvm::RISCVDAGToDAGISel::Select(), llvm::HexagonDAGToDAGISel::SelectExtractSubvector(), llvm::HvxSelector::selectExtractSubvector(), llvm::X86TargetLowering::SimplifyDemandedBitsForTargetNode(), splitAndLowerShuffle(), llvm::RISCVTargetLowering::splitValueIntoRegisterParts(), llvm::splitVectorType(), tryExtendDUPToExtractHigh(), useRVVForFixedLengthVectorVT(), widenMaskVectorType(), and llvm::X86TargetLowering::X86TargetLowering().
|
inline |
Given a vector type, return the minimum number of elements it contains.
Definition at line 273 of file MachineValueType.h.
References llvm_unreachable, and SimpleTy.
Referenced by llvm::HexagonTargetLowering::getPreferredVectorAction(), getVectorElementCount(), getVectorNumElements(), isPow2VectorType(), and llvm::LLT::LLT().
|
inline |
Definition at line 290 of file MachineValueType.h.
References getVectorMinNumElements(), isScalableVector(), and llvm::reportInvalidSizeRequest().
Referenced by llvm::AMDGPUTargetLowering::analyzeFormalArgumentsCompute(), canonicalizeShuffleMaskWithHorizOp(), combineAndnp(), combineBitcast(), combineConcatVectorOps(), combineCVTP2I_CVTTP2I(), combineEXTRACT_SUBVECTOR(), combineINSERT_SUBVECTOR(), combineMOVMSK(), combinePredicateReduction(), combineSetCCMOVMSK(), combineStore(), combineTargetShuffle(), combineVEXTRACT_STORE(), combineX86INT_TO_FP(), combineX86ShuffleChain(), llvm::X86TargetLowering::ComputeNumSignBitsForTargetNode(), convertShiftLeftToScale(), createPackShuffleMask(), createShuffleStride(), llvm::createSplat2ShuffleMask(), createVariablePermute(), DecodePALIGNRMask(), ExpandHorizontalBinOp(), ExtendToType(), ExtractBitFromMaskVector(), genShuffleBland(), llvm::AArch64TTIImpl::getArithmeticReductionCost(), llvm::X86TTIImpl::getArithmeticReductionCost(), getAVX512TruncNode(), getConstVector(), getContainerForFixedLengthVector(), getDefaultVLOps(), getExtractedDemandedElts(), getFauxShuffleMask(), getGatherNode(), getHopForBuildVector(), llvm::X86TTIImpl::getInterleavedMemoryOpCostAVX512(), getMemCmpLoad(), llvm::X86TTIImpl::getMinMaxReductionCost(), getPack(), llvm::SITargetLowering::getPreferredVectorAction(), llvm::NVPTXTargetLowering::getPreferredVectorAction(), llvm::PPCTargetLowering::getPreferredVectorAction(), llvm::X86TargetLowering::getPreferredVectorAction(), llvm::X86TTIImpl::getReplicationShuffleCost(), llvm::X86TTIImpl::getShuffleCost(), getShuffleHalfVectors(), getShuffleScalarElt(), getShuffleVectorZeroOrUndef(), getTargetShuffleAndZeroables(), getTargetShuffleMask(), getTargetVShiftNode(), llvm::ARMTargetLowering::getTgtMemIntrinsic(), llvm::X86TargetLowering::getTgtMemIntrinsic(), getUnderlyingExtractedFromVec(), getVectorMaskingNode(), getVRGatherIndexType(), getZeroVector(), group2Shuffle(), incDecVectorConstant(), insert1BitVector(), InsertBitToMaskVector(), isAddSubOrSubAdd(), IsElementEquivalent(), llvm::HexagonTargetLowering::isExtractSubvectorCheap(), isHopBuildVector(), isHorizontalBinOp(), isInterleaveShuffle(), lower1BitShuffle(), lower256BitShuffle(), LowerAsSplatVectorLoad(), LowerAVXCONCAT_VECTORS(), LowerAVXExtend(), LowerBITCAST(), LowerBITREVERSE(), LowerBITREVERSE_XOP(), lowerBitreverseShuffle(), llvm::HexagonTargetLowering::LowerBUILD_VECTOR(), llvm::VETargetLowering::lowerBUILD_VECTOR(), lowerBUILD_VECTOR(), lowerBuildVectorAsBroadcast(), LowerBuildVectorAsInsert(), lowerBuildVectorOfConstants(), lowerBuildVectorToBitOp(), llvm::HexagonTargetLowering::LowerCONCAT_VECTORS(), LowerCONCAT_VECTORSvXi1(), LowerEXTEND_VECTOR_INREG(), LowerFunnelShift(), LowerLoad(), LowerMGATHER(), LowerMSCATTER(), LowerMUL(), LowerMULH(), LowerMULO(), LowerRotate(), LowerSCALAR_TO_VECTOR(), llvm::HexagonTargetLowering::LowerSETCC(), LowerShift(), LowerShiftByScalarImmediate(), LowerShiftByScalarVariable(), lowerShuffleAsBlend(), lowerShuffleAsBroadcast(), lowerShuffleAsByteRotateAndPermute(), lowerShuffleAsElementInsertion(), lowerShuffleAsLanePermuteAndPermute(), lowerShuffleAsRepeatedMaskAndLanePermute(), lowerShuffleAsShift(), lowerShuffleAsSpecificZeroOrAnyExtend(), lowerShuffleAsVTRUNC(), lowerShuffleAsZeroOrAnyExtend(), lowerShuffleOfExtractsAsVperm(), lowerShufflePairAsUNPCKAndPermute(), lowerShuffleToEXPAND(), lowerShuffleWithPERMV(), lowerShuffleWithUndefHalf(), lowerShuffleWithVPMOV(), LowerSIGN_EXTEND(), llvm::AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(), LowerSIGN_EXTEND_Mask(), lowerToAddSubOrFMAddSub(), LowerToHorizontalOp(), LowerTruncateVecI1(), LowerTruncateVecPack(), lowerV8I16GeneralSingleInputShuffle(), llvm::HexagonTargetLowering::LowerVECTOR_SHIFT(), lowerVECTOR_SHUFFLE(), lowerVECTOR_SHUFFLEAsVSlide1(), lowerVECTOR_SHUFFLEAsVSlideup(), LowerVectorCTLZ_AVX512CDI(), LowerVectorCTLZInRegLUT(), LowerVectorCTPOP(), LowerVectorCTPOPInRegLUT(), llvm::HexagonTargetLowering::LowerVSELECT(), LowerVSETCC(), LowervXi8MulWithUNPCK(), LowerZERO_EXTEND_Mask(), matchShuffleAsEXTRQ(), matchShuffleAsINSERTQ(), matchShuffleWithPACK(), matchShuffleWithSHUFPD(), matchShuffleWithUNPCK(), matchUnaryShuffle(), narrowExtractedVectorSelect(), performConcatVectorsCombine(), performLOADCombine(), PerformVECREDUCE_ADDCombine(), performVECTOR_SHUFFLECombine(), llvm::X86TargetLowering::ReplaceNodeResults(), scalarizeVectorStore(), scaleVectorType(), llvm::HexagonDAGToDAGISel::SelectExtractSubvector(), llvm::HvxSelector::selectExtractSubvector(), setGroupSize(), llvm::X86TargetLowering::SimplifyDemandedBitsForTargetNode(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), llvm::X86TargetLowering::SimplifyMultipleUseDemandedBitsForTargetNode(), splitAndLowerShuffle(), tryExtendDUPToExtractHigh(), useRVVForFixedLengthVectorVT(), vectorizeExtractedCast(), and widenMaskVectorType().
|
inlinestatic |
Definition at line 473 of file MachineValueType.h.
References getScalableVectorVT(), and getVectorVT().
Definition at line 447 of file MachineValueType.h.
References INVALID_SIMPLE_VALUE_TYPE.
Referenced by AddCombineBUILD_VECTORToVPADDL(), canonicalizeBitSelect(), canonicalizeShuffleMaskWithHorizOp(), changeVectorElementType(), changeVectorElementTypeToInteger(), combineArithReduction(), combineBitcast(), combineConcatVectorOps(), combineCVTP2I_CVTTP2I(), combineExtractVectorElt(), combineExtractWithShuffle(), combineFaddCFmul(), combineMOVMSK(), combineMulToPMADDWD(), combinePredicateReduction(), combinePTESTCC(), combineSetCCMOVMSK(), combineStore(), combineTargetShuffle(), combineVectorHADDSUB(), combineX86INT_TO_FP(), combineX86ShuffleChain(), combineX86ShufflesConstants(), constructDup(), constructRetValue(), createPSADBW(), createVariablePermute(), createVPDPBUSD(), EltsFromConsecutiveLoads(), ExtractBitFromMaskVector(), llvm::X86TTIImpl::getArithmeticInstrCost(), getAVX512Node(), getAVX512TruncNode(), llvm::HvxSelector::getBoolVT(), getBuildDwordsVector(), getConstVector(), getDeinterleaveViaVNSRL(), getDoubleNumVectorElementsVT(), getGatherNode(), getHalfNumVectorElementsVT(), llvm::X86TTIImpl::getInterleavedMemoryOpCostAVX512(), llvm::getLegalVectorType(), llvm::VECustomDAG::getMaskBroadcast(), getMaskNode(), getMaskTypeFor(), llvm::getMVTForLLT(), getOnesVector(), llvm::RISCVTargetLowering::getOptimalMemOpType(), llvm::HvxSelector::getPairVT(), getPermuteNode(), getPow2VectorType(), getPrefetchNode(), getPromotedVectorElementType(), getScatterNode(), llvm::ARMTargetLowering::getSetCCResultType(), llvm::HvxSelector::getSingleVT(), getTargetVShiftNode(), llvm::ARMTargetLowering::getTgtMemIntrinsic(), llvm::X86TargetLowering::getTgtMemIntrinsic(), llvm::TargetLoweringBase::getTypeConversion(), getVectorMaskingNode(), getVectorTypeBreakdownMVT(), llvm::EVT::getVectorVT(), getVectorVT(), getVT(), getWideningInterleave(), getZeroVector(), llvm::HexagonTargetLowering::HexagonTargetLowering(), InsertBitToMaskVector(), is128BitUnpackShuffleMask(), llvm::HexagonSubtarget::isTypeForHVX(), llvm::SystemZVectorConstantInfo::isVectorConstantLegal(), lower1BitShuffle(), lower256BitShuffle(), LowerBITCAST(), LowerBITREVERSE(), LowerBITREVERSE_XOP(), lowerBuildVectorAsBroadcast(), lowerBuildVectorOfConstants(), LowerCONCAT_VECTORS_i1(), LowerCTPOP(), LowerEXTRACT_SUBVECTOR(), LowerFMINIMUM_FMAXIMUM(), lowerFPToIntToFP(), LowerFunnelShift(), LowerHorizontalByteSum(), LowerI64IntToFP_AVX512DQ(), LowerINTRINSIC_W_CHAIN(), LowerMGATHER(), LowerMLOAD(), LowerMSCATTER(), LowerMSTORE(), LowerMUL(), LowerMULH(), LowerMULO(), llvm::RISCVTargetLowering::LowerOperation(), LowerRotate(), LowerSCALAR_TO_VECTOR(), llvm::HexagonTargetLowering::LowerSETCC(), LowerShift(), LowerShiftByScalarImmediate(), LowerShiftByScalarVariable(), lowerShuffleAsBitMask(), lowerShuffleAsBlend(), lowerShuffleAsBlendOfPSHUFBs(), lowerShuffleAsBroadcast(), lowerShuffleAsByteRotate(), lowerShuffleAsByteRotateAndPermute(), lowerShuffleAsElementInsertion(), lowerShuffleAsPermuteAndUnpack(), lowerShuffleAsSpecificZeroOrAnyExtend(), lowerShuffleAsVTRUNC(), lowerShuffleToEXPAND(), lowerShuffleWithPACK(), lowerShuffleWithPSHUFB(), lowerShuffleWithVPMOV(), LowerSIGN_EXTEND_Mask(), LowerStore(), LowerTruncateVecI1(), LowerTruncateVecPack(), llvm::HexagonTargetLowering::LowerUnalignedLoad(), lowerV2X128Shuffle(), lowerV4X128Shuffle(), lowerV8I16GeneralSingleInputShuffle(), llvm::HexagonTargetLowering::LowerVECTOR_SHIFT(), LowerVECTOR_SHUFFLE(), lowerVECTOR_SHUFFLE(), lowerVECTOR_SHUFFLEAsRotate(), LowerVectorAllEqual(), LowerVectorCTLZ_AVX512CDI(), LowerVectorCTLZInRegLUT(), LowerVectorCTPOP(), lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND(), lowerVectorIntrinsicScalars(), llvm::HexagonTargetLowering::LowerVSELECT(), LowervXi8MulWithUNPCK(), lowerX86FPLogicOp(), LowerZERO_EXTEND_Mask(), matchBinaryPermuteShuffle(), matchShuffleAsBitRotate(), matchShuffleAsShift(), matchShuffleAsVTRUNC(), matchShuffleWithPACK(), matchUnaryPermuteShuffle(), matchUnaryShuffle(), llvm::MipsTargetLowering::MipsTargetLowering(), narrowExtractedVectorSelect(), NarrowVector(), performCONCAT_VECTORSCombine(), performConcatVectorsCombine(), performLOADCombine(), PerformVQDMULHCombine(), llvm::X86TargetLowering::ReplaceNodeResults(), llvm::RISCVTargetLowering::RISCVTargetLowering(), scaleVectorType(), llvm::X86TargetLowering::SimplifyDemandedBitsForTargetNode(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), skipExtensionForVectorMULL(), SkipExtensionForVMULL(), splatPartsI64WithVL(), splitAndLowerShuffle(), llvm::splitVectorType(), TryCombineBaseUpdate(), tryExtendDUPToExtractHigh(), tryWidenMaskForShuffle(), vectorizeExtractedCast(), vectorToScalarBitmask(), widenSubVector(), and WidenVector().
Definition at line 467 of file MachineValueType.h.
References getScalableVectorVT(), and getVectorVT().
Return the value type corresponding to the specified type.
This returns all pointers as iPTR. If HandleUnknown is true, unknown types are returned as Other, otherwise they are invalid.
This returns all pointers as MVT::iPTR. If HandleUnknown is true, unknown types are returned as Other, otherwise they are invalid.
Definition at line 573 of file ValueTypes.cpp.
References assert(), llvm::Type::BFloatTyID, llvm::Type::DoubleTyID, llvm::Type::FixedVectorTyID, llvm::Type::FloatTyID, llvm::Type::FP128TyID, getBitWidth(), llvm::VectorType::getElementCount(), llvm::VectorType::getElementType(), getIntegerVT(), llvm::TargetExtType::getName(), llvm::Type::getTypeID(), getVectorVT(), getVT(), llvm::Type::HalfTyID, llvm::Type::IntegerTyID, llvm_unreachable, MVT(), llvm::Type::PointerTyID, llvm::Type::PPC_FP128TyID, llvm::Type::ScalableVectorTyID, llvm::StringRef::starts_with(), llvm::Type::TargetExtTyID, llvm::Type::VoidTyID, llvm::Type::X86_AMXTyID, llvm::Type::X86_FP80TyID, and llvm::Type::X86_MMXTyID.
Referenced by llvm::CallLowering::checkReturn(), getConvRTLibDesc(), llvm::EVT::getEVT(), llvm::X86TTIImpl::getInterleavedMemoryOpCostAVX512(), llvm::SITargetLowering::getTgtMemIntrinsic(), llvm::AArch64TargetLowering::getTgtMemIntrinsic(), llvm::ARMTargetLowering::getTgtMemIntrinsic(), llvm::HexagonTargetLowering::getTgtMemIntrinsic(), llvm::X86TargetLowering::getTgtMemIntrinsic(), getVT(), llvm::GCNTTIImpl::isReadRegisterSourceOfDivergence(), and llvm::AArch64CallLowering::lowerReturn().
|
inlinestatic |
Definition at line 521 of file MachineValueType.h.
References llvm::enum_seq_inclusive(), and llvm::force_iteration_on_noniterable_enum.
Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering(), llvm::AMDGPUTargetLowering::AMDGPUTargetLowering(), llvm::ARMTargetLowering::ARMTargetLowering(), llvm::RISCVTargetLowering::RISCVTargetLowering(), llvm::SparcTargetLowering::SparcTargetLowering(), llvm::SystemZTargetLowering::SystemZTargetLowering(), and llvm::WebAssemblyTargetLowering::WebAssemblyTargetLowering().
|
inlinestatic |
Definition at line 533 of file MachineValueType.h.
References llvm::enum_seq_inclusive(), and llvm::force_iteration_on_noniterable_enum.
Referenced by llvm::RISCVTargetLowering::RISCVTargetLowering().
|
inlinestatic |
Definition at line 492 of file MachineValueType.h.
References llvm::enum_seq_inclusive(), and llvm::force_iteration_on_noniterable_enum.
Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering(), llvm::AMDGPUTargetLowering::AMDGPUTargetLowering(), llvm::ARMTargetLowering::ARMTargetLowering(), llvm::AVRTargetLowering::AVRTargetLowering(), llvm::BPFTargetLowering::BPFTargetLowering(), findMemType(), llvm::HexagonTargetLowering::HexagonTargetLowering(), llvm::LanaiTargetLowering::LanaiTargetLowering(), llvm::M68kTargetLowering::M68kTargetLowering(), llvm::MipsTargetLowering::MipsTargetLowering(), llvm::MSP430TargetLowering::MSP430TargetLowering(), llvm::NVPTXTargetLowering::NVPTXTargetLowering(), PerformTruncatingStoreCombine(), llvm::PPCTargetLowering::PPCTargetLowering(), llvm::R600TargetLowering::R600TargetLowering(), llvm::SparcTargetLowering::SparcTargetLowering(), llvm::SystemZTargetLowering::SystemZTargetLowering(), llvm::WebAssemblyTargetLowering::WebAssemblyTargetLowering(), llvm::X86TargetLowering::X86TargetLowering(), and llvm::XCoreTargetLowering::XCoreTargetLowering().
|
inline |
Return true if this is a 1024-bit vector type.
Definition at line 167 of file MachineValueType.h.
References getFixedSizeInBits(), and isFixedLengthVector().
|
inline |
Return true if this is a 128-bit vector type.
Definition at line 152 of file MachineValueType.h.
References getFixedSizeInBits(), and isFixedLengthVector().
Referenced by CC_AArch64_Custom_Block(), CC_LoongArch(), CC_PPC64_ELF_Shadow_GPR_Regs(), llvm::CC_XPLINK64_Shadow_Reg(), combineAndNotIntoANDNP(), combineCVTP2I_CVTTP2I(), combineEXTRACT_SUBVECTOR(), combinePTESTCC(), combineSetCCMOVMSK(), combineX86INT_TO_FP(), combineX86ShuffleChain(), llvm::X86TTIImpl::getCmpSelInstrCost(), llvm::X86TTIImpl::getIntrinsicInstrCost(), getZeroVector(), isHorizontalBinOp(), LowerBITREVERSE_XOP(), lowerBuildVectorAsBroadcast(), LowerBuildVectorv4x32(), LowerEXTEND_VECTOR_INREG(), LowerEXTRACT_VECTOR_ELT_SSE4(), LowerRotate(), LowerSCALAR_TO_VECTOR(), lowerShuffleAsBitRotate(), lowerShuffleAsByteRotate(), lowerShuffleAsByteRotateAndPermute(), lowerShuffleAsByteShiftMask(), lowerShuffleAsElementInsertion(), lowerShuffleAsPermuteAndUnpack(), lowerShuffleAsSpecificZeroOrAnyExtend(), lowerShuffleAsVALIGN(), lowerShuffleAsVTRUNC(), lowerShuffleOfExtractsAsVperm(), lowerShuffleWithPSHUFB(), lowerShuffleWithUndefHalf(), LowerTruncateVecI1(), lowerVECTOR_SHUFFLE(), LowerVectorCTPOP(), LowerVSETCC(), matchBinaryPermuteShuffle(), matchBinaryShuffle(), matchShuffleAsInsertPS(), matchUnaryPermuteShuffle(), matchUnaryShuffle(), narrowExtractedVectorSelect(), performAddSubLongCombine(), performVECTOR_SHUFFLECombine(), scalarizeVectorStore(), llvm::LoongArchDAGToDAGISel::Select(), and llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode().
|
inline |
Return true if this is a 16-bit vector type.
Definition at line 137 of file MachineValueType.h.
References getFixedSizeInBits(), and isFixedLengthVector().
|
inline |
Return true if this is a 2048-bit vector type.
Definition at line 172 of file MachineValueType.h.
References getFixedSizeInBits(), and isFixedLengthVector().
|
inline |
Return true if this is a 256-bit vector type.
Definition at line 157 of file MachineValueType.h.
References getFixedSizeInBits(), and isFixedLengthVector().
Referenced by CC_LoongArch(), CC_X86_VectorCallGetSSEs(), combineAndNotIntoANDNP(), combineConcatVectorOps(), combineEXTRACT_SUBVECTOR(), combineSetCCMOVMSK(), combineX86ShuffleChain(), ExpandHorizontalBinOp(), getHopForBuildVector(), llvm::X86TTIImpl::getIntrinsicInstrCost(), getZeroVector(), isHopBuildVector(), isHorizontalBinOp(), LowerABD(), LowerABS(), LowerADDSAT_SUBSAT(), LowerAVG(), LowerAVXCONCAT_VECTORS(), LowerBITREVERSE_XOP(), lowerBuildVectorAsBroadcast(), LowerCONCAT_VECTORS(), LowerEXTEND_VECTOR_INREG(), LowerFunnelShift(), LowerMINMAX(), LowerMUL(), LowerMULH(), LowerRotate(), LowerShift(), lowerShuffleAsBroadcast(), lowerShuffleAsByteRotateAndPermute(), lowerShuffleAsLanePermuteAndShuffle(), lowerShuffleAsRepeatedMaskAndLanePermute(), lowerShuffleAsVALIGN(), lowerShuffleAsVTRUNC(), lowerShuffleOfExtractsAsVperm(), lowerShuffleWithPSHUFB(), lowerShuffleWithUndefHalf(), LowerStore(), LowerToHorizontalOp(), LowerTruncateVecI1(), lowerVECTOR_SHUFFLE(), LowerVectorCTLZ(), LowerVectorCTLZ_AVX512CDI(), LowerVectorCTPOP(), LowerVSETCC(), matchBinaryPermuteShuffle(), matchBinaryShuffle(), matchShuffleAsBlend(), matchUnaryPermuteShuffle(), matchUnaryShuffle(), narrowExtractedVectorSelect(), and llvm::X86TargetLowering::SimplifyDemandedBitsForTargetNode().
|
inline |
Return true if this is a 32-bit vector type.
Definition at line 142 of file MachineValueType.h.
References getFixedSizeInBits(), and isFixedLengthVector().
Referenced by CC_AArch64_Custom_Block(), and LowerStore().
|
inline |
Return true if this is a 512-bit vector type.
Definition at line 162 of file MachineValueType.h.
References getFixedSizeInBits(), and isFixedLengthVector().
Referenced by CC_X86_VectorCallGetSSEs(), combineAndNotIntoANDNP(), combineConcatVectorOps(), combineShuffleToAddSubOrFMAddSub(), combineX86ShuffleChain(), getAVX512Node(), getAVX512TruncNode(), llvm::X86TTIImpl::getIntrinsicInstrCost(), llvm::X86TargetLowering::getSetCCResultType(), getZeroVector(), LowerAVXCONCAT_VECTORS(), LowerBITREVERSE(), lowerBuildVectorAsBroadcast(), LowerCONCAT_VECTORS(), LowerEXTEND_VECTOR_INREG(), LowerFunnelShift(), LowerMGATHER(), LowerMLOAD(), LowerMSCATTER(), LowerMSTORE(), LowerRotate(), LowerShift(), LowerShiftByScalarImmediate(), lowerShuffleAsBroadcast(), lowerShuffleAsByteRotate(), lowerShuffleAsByteRotateAndPermute(), lowerShuffleWithPERMV(), lowerShuffleWithPSHUFB(), lowerShuffleWithUndefHalf(), LowerSIGN_EXTEND_Mask(), lowerToAddSubOrFMAddSub(), lowerV4X128Shuffle(), lowerVECTOR_SHUFFLE(), LowerVectorCTLZ(), LowerVectorCTLZ_AVX512CDI(), LowerVectorCTPOP(), LowerVSETCC(), LowerZERO_EXTEND_Mask(), matchBinaryPermuteShuffle(), matchBinaryShuffle(), matchShuffleAsVTRUNC(), matchUnaryPermuteShuffle(), matchUnaryShuffle(), narrowExtractedVectorSelect(), llvm::LoongArchDAGToDAGISel::Select(), and useVPTERNLOG().
|
inline |
Return true if this is a 64-bit vector type.
Definition at line 147 of file MachineValueType.h.
References getFixedSizeInBits(), and isFixedLengthVector().
Referenced by CC_AArch64_Custom_Block(), LowerStore(), and tryExtendDUPToExtractHigh().
|
inline |
Returns true if the number of bits for the type is a multiple of an 8-bit byte.
Definition at line 375 of file MachineValueType.h.
References getSizeInBits(), and llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::isKnownMultipleOf().
|
inline |
Definition at line 131 of file MachineValueType.h.
References SimpleTy.
Referenced by llvm::RISCV::CC_RISCV(), llvm::RISCV::CC_RISCV_FastCC(), convertLocVTToValVT(), convertValVTToLocVT(), getContainerForFixedLengthVector(), getDefaultVLOps(), getDeinterleaveViaVNSRL(), getWideningInterleave(), is1024BitVector(), is128BitVector(), is16BitVector(), is2048BitVector(), is256BitVector(), is32BitVector(), is512BitVector(), is64BitVector(), lowerBUILD_VECTOR(), lowerBuildVectorOfConstants(), lowerBuildVectorViaDominantValues(), lowerFMAXIMUM_FMINIMUM(), lowerFP_TO_INT_SAT(), llvm::RISCVTargetLowering::LowerOperation(), lowerScalarInsert(), lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND(), lowerVectorStrictFTRUNC_FCEIL_FFLOOR_FROUND(), matchSplatAsGather(), performFP_TO_INTCombine(), llvm::RISCVTargetLowering::ReplaceNodeResults(), llvm::RISCVDAGToDAGISel::Select(), and useRVVForFixedLengthVectorVT().
|
inline |
Return true if this is a FP or a vector FP type.
Definition at line 83 of file MachineValueType.h.
References SimpleTy.
Referenced by llvm::AMDGPUTargetLowering::analyzeFormalArgumentsCompute(), CC_LoongArch(), CC_MipsO32(), llvm::RISCV::CC_RISCV(), CC_X86_32_VectorCall(), CC_X86_64_VectorCall(), combineConcatVectorOps(), combineTargetShuffle(), combineX86ShuffleChain(), combineX86ShufflesConstants(), getConstantVector(), getCopyFromParts(), getCopyToParts(), getTargetShuffleAndZeroables(), llvm::TargetLoweringBase::getTypeToPromoteTo(), getVCmpInst(), getZeroVector(), isAddSubOrSubAdd(), isHorizontalBinOp(), lowerBUILD_VECTOR(), lowerBuildVectorOfConstants(), lowerBuildVectorViaDominantValues(), LowerFABSorFNEG(), LowerFCOPYSIGN(), lowerScalarInsert(), lowerScalarSplat(), lowerShuffleAsElementInsertion(), lowerShuffleAsLanePermuteAndShuffle(), lowerShuffleAsPermuteAndUnpack(), lowerVECTOR_SHUFFLE(), lowerVECTOR_SHUFFLEAsVSlide1(), LowerVSETCC(), and performScatterStoreCombine().
|
inline |
Return true if this is an integer or a vector integer type.
Definition at line 93 of file MachineValueType.h.
References SimpleTy.
Referenced by llvm::AMDGPUTargetLowering::analyzeFormalArgumentsCompute(), convertLocVTToValVT(), convertValVTToLocVT(), llvm::TargetLowering::findOptimalMemOpLowering(), getCopyFromParts(), llvm::RegsForValue::getCopyFromRegs(), getCopyToParts(), getCopyToPartsVector(), getRegistersForValue(), llvm::X86TTIImpl::getScalarizationOverhead(), getShuffleScalarElt(), llvm::TargetLoweringBase::getTypeToPromoteTo(), llvm::X86TTIImpl::getVectorInstrCost(), isValueTypeInRegForCC(), llvm::TargetLowering::LegalizeSetCCCondCode(), lower256BitShuffle(), LowerABS(), llvm::X86TargetLowering::LowerAsmOutputForConstraint(), lowerBuildVectorOfConstants(), LowerLoad(), llvm::RISCVTargetLowering::LowerOperation(), LowerSCALAR_TO_VECTOR(), lowerShuffleAsBitBlend(), lowerShuffleAsBroadcast(), lowerShuffleAsTruncBroadcast(), LowerStore(), lowerVECTOR_SHUFFLE(), matchUnaryShuffle(), llvm::TargetLowering::ParseConstraints(), llvm::RISCVDAGToDAGISel::PreprocessISelDAG(), and llvm::X86TargetLowering::ReplaceNodeResults().
|
inline |
Return true if this is an overloaded type for TableGen.
Definition at line 177 of file MachineValueType.h.
References SimpleTy.
|
inline |
Returns true if the given vector is a power of 2.
Definition at line 237 of file MachineValueType.h.
References getVectorMinNumElements().
Referenced by getPow2VectorType(), llvm::TargetLoweringBase::getPreferredVectorAction(), llvm::SITargetLowering::getPreferredVectorAction(), and useRVVForFixedLengthVectorVT().
|
inline |
Return true if this is a custom target type that has a scalable size.
Definition at line 122 of file MachineValueType.h.
References SimpleTy.
Referenced by isScalableVT(), and llvm::LLT::LLT().
|
inline |
Return true if this is a vector value type where the runtime length is machine dependent.
Definition at line 116 of file MachineValueType.h.
References SimpleTy.
Referenced by bitsGE(), bitsGT(), bitsLE(), bitsLT(), CC_AArch64_Custom_Block(), llvm::RISCV::CC_RISCV(), llvm::TargetLoweringBase::computeRegisterProperties(), llvm::RISCVTargetLowering::computeVLMax(), convertLocVTToValVT(), finishStackBlock(), getDefaultScalableVLOps(), getDefaultVLOps(), llvm::RISCVTargetLowering::getLMUL(), llvm::RISCVTargetLowering::getLMULCost(), llvm::SITargetLowering::getPreferredVectorAction(), llvm::HexagonTargetLowering::getPreferredVectorAction(), llvm::NVPTXTargetLowering::getPreferredVectorAction(), llvm::PPCTargetLowering::getPreferredVectorAction(), llvm::X86TargetLowering::getPreferredVectorAction(), getSmallestVTForIndex(), getVectorElementCount(), getVectorNumElements(), getVectorTypeBreakdownMVT(), isScalableVT(), llvm::RISCVTargetLowering::joinRegisterPartsIntoValue(), llvm::RISCVTargetLowering::LowerFormalArguments(), lowerScalarInsert(), llvm::RISCVTargetLowering::PerformDAGCombine(), llvm::RISCVDAGToDAGISel::PreprocessISelDAG(), llvm::RISCVDAGToDAGISel::Select(), and llvm::RISCVTargetLowering::splitValueIntoRegisterParts().
|
inline |
Return true if the type is a scalable type.
Definition at line 127 of file MachineValueType.h.
References isScalableTargetExtVT(), and isScalableVector().
|
inline |
Return true if this is an integer, not including vectors.
Definition at line 103 of file MachineValueType.h.
References SimpleTy.
Referenced by CC_LoongArch(), llvm::RISCV::CC_RISCV(), hasBZHI(), LowerABD(), LowerBITCAST(), llvm::RISCVTargetLowering::LowerOperation(), llvm::HexagonTargetLowering::LowerSETCC(), lowerVectorIntrinsicScalars(), llvm::HexagonTargetLowering::LowerVSELECT(), llvm::X86TargetLowering::SimplifyDemandedBitsForTargetNode(), and truncateScalarIntegerArg().
|
inline |
Return true if this is a valid simple valuetype.
Definition at line 77 of file MachineValueType.h.
References SimpleTy.
Referenced by getSmallestVTForIndex(), llvm::TargetLoweringBase::initActions(), llvm::HexagonSubtarget::isTypeForHVX(), llvm::LLT::LLT(), llvm::MipsTargetLowering::MipsTargetLowering(), llvm::TargetLoweringBase::setCondCodeAction(), llvm::TargetLoweringBase::setLoadExtAction(), and llvm::TargetLoweringBase::setTruncStoreAction().
|
inline |
Return true if this is a vector value type.
Definition at line 109 of file MachineValueType.h.
References SimpleTy.
Referenced by llvm::PPCTargetLowering::allowsMisalignedMemoryAccesses(), llvm::AMDGPUTargetLowering::analyzeFormalArgumentsCompute(), canonicalizeBitSelect(), llvm::RISCV::CC_RISCV(), llvm::RISCV::CC_RISCV_FastCC(), CC_X86_32_VectorCall(), CC_X86_64_VectorCall(), changeTypeToInteger(), combineAndnp(), combineX86ShuffleChain(), combineX86ShufflesRecursively(), constructRetValue(), convertLocVTToValVT(), convertValVTToLocVT(), llvm::X86TTIImpl::getArithmeticReductionCost(), getAVX512Node(), llvm::X86TTIImpl::getCmpSelInstrCost(), getCopyFromParts(), getCopyToPartsVector(), llvm::X86TTIImpl::getInterleavedMemoryOpCost(), llvm::AArch64TTIImpl::getIntrinsicInstrCost(), llvm::X86TTIImpl::getIntrinsicInstrCost(), llvm::getLLTForMVT(), llvm::RISCVTargetLowering::getLMULCost(), getMaskTypeFor(), getMemCmpLoad(), llvm::X86TTIImpl::getMinMaxReductionCost(), llvm::PPCTargetLowering::getRegForInlineAsmConstraint(), llvm::RISCVTargetLowering::getRegForInlineAsmConstraint(), llvm::X86TargetLowering::getRegForInlineAsmConstraint(), llvm::X86TTIImpl::getReplicationShuffleCost(), getScalarType(), getScalarValueForVectorElement(), llvm::X86TargetLowering::getSetCCResultType(), llvm::X86TTIImpl::getShuffleCost(), llvm::CallLowering::ValueHandler::getStackValueStoreType(), getTargetVShiftNode(), llvm::TargetLoweringBase::getTypeConversion(), llvm::HexagonSubtarget::isHVXElementType(), isValueTypeInRegForCC(), llvm::LLT::LLT(), LowerADDSAT_SUBSAT(), llvm::X86TargetLowering::LowerAsmOutputForConstraint(), LowerAVXExtend(), LowerBITCAST(), LowerBITREVERSE_XOP(), llvm::RISCVTargetLowering::LowerCall(), LowerCTLZ(), LowerCTTZ(), LowerFABSorFNEG(), LowerFCOPYSIGN(), lowerFMAXIMUM_FMINIMUM(), llvm::RISCVTargetLowering::LowerFormalArguments(), lowerFP_TO_INT_SAT(), lowerFPToIntToFP(), lowerFTRUNC_FCEIL_FFLOOR_FROUND(), LowerFunnelShift(), LowerLoad(), LowerMULO(), llvm::RISCVTargetLowering::LowerOperation(), llvm::AArch64CallLowering::lowerReturn(), LowerRotate(), llvm::HexagonTargetLowering::LowerSETCC(), LowerShift(), lowerShuffleAsTruncBroadcast(), LowerSIGN_EXTEND(), llvm::AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(), lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND(), lowerX86FPLogicOp(), performConcatVectorsCombine(), preAssignMask(), processPSInputArgs(), promoteXINT_TO_FP(), llvm::X86TargetLowering::ReplaceNodeResults(), llvm::X86TargetLowering::SimplifyDemandedBitsForTargetNode(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), llvm::splitVectorType(), and VerifyVectorType().
Return true if we know at compile time this has more than or the same bits as VT.
Definition at line 384 of file MachineValueType.h.
References getSizeInBits(), and llvm::details::FixedOrScalableQuantity< TypeSize, uint64_t >::isKnownGE().
Referenced by bitsGE().
Return true if we know at compile time this has more bits than VT.
Definition at line 378 of file MachineValueType.h.
References getSizeInBits(), and llvm::details::FixedOrScalableQuantity< TypeSize, uint64_t >::isKnownGT().
Referenced by bitsGT().
Return true if we know at compile time this has fewer than or the same bits as VT.
Definition at line 395 of file MachineValueType.h.
References getSizeInBits(), and llvm::details::FixedOrScalableQuantity< TypeSize, uint64_t >::isKnownLE().
Referenced by bitsLE().
Return true if we know at compile time this has fewer bits than VT.
Definition at line 389 of file MachineValueType.h.
References getSizeInBits(), and llvm::details::FixedOrScalableQuantity< TypeSize, uint64_t >::isKnownLT().
Referenced by bitsLT().
Definition at line 66 of file MachineValueType.h.
References SimpleTy.
Definition at line 64 of file MachineValueType.h.
References SimpleTy.
Definition at line 68 of file MachineValueType.h.
References SimpleTy.
Definition at line 65 of file MachineValueType.h.
References SimpleTy.
Definition at line 63 of file MachineValueType.h.
References SimpleTy.
Definition at line 67 of file MachineValueType.h.
References SimpleTy.
void MVT::print | ( | raw_ostream & | OS | ) | const |
Implement operator<<.
Definition at line 639 of file ValueTypes.cpp.
References llvm::EVT::getEVTString(), INVALID_SIMPLE_VALUE_TYPE, OS, and SimpleTy.
Referenced by dump(), and llvm::operator<<().
|
inlinestatic |
Definition at line 515 of file MachineValueType.h.
References llvm::enum_seq_inclusive(), and llvm::force_iteration_on_noniterable_enum.
Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering().
|
inlinestatic |
Definition at line 503 of file MachineValueType.h.
References llvm::enum_seq_inclusive(), and llvm::force_iteration_on_noniterable_enum.
Referenced by findMemType().
SimpleValueType llvm::MVT::SimpleTy = INVALID_SIMPLE_VALUE_TYPE |
Definition at line 58 of file MachineValueType.h.
Referenced by AddCombineBUILD_VECTORToVPADDL(), llvm::TargetLoweringBase::AddPromotedToType(), llvm::TargetLoweringBase::addRegisterClass(), llvm::ARMTargetLowering::allowsMisalignedMemoryAccesses(), llvm::MipsSETargetLowering::allowsMisalignedMemoryAccesses(), AVRDAGToDAGISel::select< ISD::LOAD >(), CC_AArch64_Custom_Block(), CC_AIX(), CC_ARM_AAPCS_Custom_Aggregate(), changeVectorElementType(), changeVectorElementTypeToInteger(), combineBitcastvxi1(), llvm::VETargetLowering::combineSelectCC(), ComputePTXValueVTs(), convertFPToInt(), createVariablePermute(), llvm::SITargetLowering::denormalsEnabledForType(), llvm::SelectionDAG::EVTToAPFloatSemantics(), llvm::TargetLowering::expandBSWAP(), llvm::TargetLowering::expandVPBSWAP(), llvm::TargetLowering::findOptimalMemOpLowering(), llvm::TargetLoweringBase::findRepresentativeClass(), llvm::ARMTargetLowering::findRepresentativeClass(), llvm::X86TargetLowering::findRepresentativeClass(), foldVectorXorShiftIntoCmp(), llvm::R600RegisterInfo::getCFGStructurizerRegClass(), llvm::TargetLoweringBase::getCondCodeAction(), getContainerForFixedLengthVector(), llvm::EVT::getEVTString(), getExtensionTo64Bits(), getIEEEProperties(), getImplicitScaleFactor(), getLdStRegType(), llvm::TargetLoweringBase::getLoadExtAction(), llvm::TargetLoweringBase::getNumRegisters(), llvm::TargetLoweringBase::getOperationAction(), llvm::RTLIB::getOUTLINE_ATOMIC(), getPackedSVEVectorVT(), getPredicateForFixedLengthVector(), llvm::TargetLoweringBase::getRegClassFor(), llvm::SITargetLowering::getRegForInlineAsmConstraint(), llvm::HexagonTargetLowering::getRegForInlineAsmConstraint(), llvm::M68kTargetLowering::getRegForInlineAsmConstraint(), llvm::RISCVTargetLowering::getRegForInlineAsmConstraint(), llvm::X86TargetLowering::getRegForInlineAsmConstraint(), llvm::TargetLoweringBase::getRegisterType(), llvm::TargetLoweringBase::getRepRegClassCostFor(), llvm::TargetLoweringBase::getRepRegClassFor(), llvm::TargetLoweringBase::getSetCCResultType(), getSizeInBits(), getSVEContainerType(), llvm::TargetLoweringBase::getTruncStoreAction(), llvm::TargetLoweringBase::ValueTypeActionImpl::getTypeAction(), llvm::TargetLoweringBase::getTypeConversion(), llvm::EVT::getTypeForEVT(), llvm::TargetLoweringBase::getTypeToPromoteTo(), llvm::SelectionDAG::getValueType(), getVectorElementType(), getVectorMinNumElements(), getVectorTyFromPredicateVector(), getVPTESTMOpc(), Is16bitsType(), is32Bit(), isConstantSplatVectorMaskForType(), isFixedLengthVector(), isFloatingPoint(), llvm::AArch64TargetLowering::isFMAFasterThanFMulAndFAdd(), llvm::SITargetLowering::isFMAFasterThanFMulAndFAdd(), llvm::LoongArchTargetLowering::isFMAFasterThanFMulAndFAdd(), llvm::RISCVTargetLowering::isFMAFasterThanFMulAndFAdd(), llvm::SystemZTargetLowering::isFMAFasterThanFMulAndFAdd(), llvm::X86TargetLowering::isFMAFasterThanFMulAndFAdd(), llvm::ARMTargetLowering::isFNegFree(), llvm::PPCTargetLowering::isFPImmLegal(), isInteger(), isLegalAddressImmediate(), llvm::ARMTargetLowering::isLegalAddressingMode(), llvm::RISCVTargetLowering::isLegalElementTypeForRVV(), isLegalT1AddressImmediate(), isLegalT2AddressImmediate(), llvm::ARMTargetLowering::isLegalT2ScaledAddressingMode(), isOverloaded(), IsPTXVectorType(), isScalableTargetExtVT(), isScalableVector(), isScalarInteger(), llvm::TargetLoweringBase::isTypeLegal(), isValid(), llvm::HexagonInstrInfo::isValidAutoIncImm(), isValidIndexedLoad(), isVector(), llvm::ARMTargetLowering::isZExtFree(), llvm::X86TargetLowering::isZExtFree(), llvm::XCoreTargetLowering::isZExtFree(), lower128BitShuffle(), lower1BitShuffle(), lower256BitShuffle(), lower512BitShuffle(), LowerADDSUBSAT(), llvm::SystemZTargetLowering::LowerFormalArguments(), lowerRegToMasks(), lowerShuffleAsBlend(), lowerUINT_TO_FP_vec(), operator!=(), llvm::EVT::operator!=(), operator<(), operator<=(), operator==(), operator>(), operator>=(), performUzpCombine(), performVSelectCombine(), print(), ReplaceINTRINSIC_W_CHAIN(), ReplaceLoadVector(), llvm::RISCVDAGToDAGISel::Select(), llvm::HexagonDAGToDAGISel::SelectIndexedLoad(), llvm::HexagonDAGToDAGISel::SelectIndexedStore(), llvm::TargetLoweringBase::setCondCodeAction(), llvm::TargetLoweringBase::setLoadExtAction(), llvm::TargetLoweringBase::setOperationAction(), llvm::TargetLoweringBase::setTruncStoreAction(), llvm::TargetLoweringBase::ValueTypeActionImpl::setTypeAction(), llvm::ARMTargetLowering::shouldConvertFpToSat(), llvm::RISCVTargetLowering::shouldConvertFpToSat(), llvm::X86InstrInfo::shouldScheduleLoadsNear(), unpackFromRegLoc(), usePartialVectorLoads(), useRVVForFixedLengthVectorVT(), llvm::AArch64TargetLowering::useSVEForFixedLengthVectorVT(), X86ChooseCmpImmediateOpcode(), and X86ChooseCmpOpcode().