LLVM
15.0.0git
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#include "llvm/Support/MachineValueType.h"
Public Member Functions | |
constexpr | MVT ()=default |
constexpr | MVT (SimpleValueType SVT) |
bool | operator> (const MVT &S) const |
bool | operator< (const MVT &S) const |
bool | operator== (const MVT &S) const |
bool | operator!= (const MVT &S) const |
bool | operator>= (const MVT &S) const |
bool | operator<= (const MVT &S) const |
bool | isValid () const |
Return true if this is a valid simple valuetype. More... | |
bool | isFloatingPoint () const |
Return true if this is a FP or a vector FP type. More... | |
bool | isInteger () const |
Return true if this is an integer or a vector integer type. More... | |
bool | isScalarInteger () const |
Return true if this is an integer, not including vectors. More... | |
bool | isVector () const |
Return true if this is a vector value type. More... | |
bool | isScalableVector () const |
Return true if this is a vector value type where the runtime length is machine dependent. More... | |
bool | isFixedLengthVector () const |
bool | is16BitVector () const |
Return true if this is a 16-bit vector type. More... | |
bool | is32BitVector () const |
Return true if this is a 32-bit vector type. More... | |
bool | is64BitVector () const |
Return true if this is a 64-bit vector type. More... | |
bool | is128BitVector () const |
Return true if this is a 128-bit vector type. More... | |
bool | is256BitVector () const |
Return true if this is a 256-bit vector type. More... | |
bool | is512BitVector () const |
Return true if this is a 512-bit vector type. More... | |
bool | is1024BitVector () const |
Return true if this is a 1024-bit vector type. More... | |
bool | is2048BitVector () const |
Return true if this is a 2048-bit vector type. More... | |
bool | isOverloaded () const |
Return true if this is an overloaded type for TableGen. More... | |
MVT | changeVectorElementTypeToInteger () const |
Return a vector with the same number of elements as this vector, but with the element type converted to an integer type with the same bitwidth. More... | |
MVT | changeVectorElementType (MVT EltVT) const |
Return a VT for a vector type whose attributes match ourselves with the exception of the element type that is chosen by the caller. More... | |
MVT | changeTypeToInteger () |
Return the type converted to an equivalently sized integer or vector with integer element type. More... | |
MVT | getHalfNumVectorElementsVT () const |
Return a VT for a vector type with the same element type but half the number of elements. More... | |
bool | isPow2VectorType () const |
Returns true if the given vector is a power of 2. More... | |
MVT | getPow2VectorType () const |
Widens the length of the given vector MVT up to the nearest power of 2 and returns that type. More... | |
MVT | getScalarType () const |
If this is a vector, return the element type, otherwise return this. More... | |
MVT | getVectorElementType () const |
unsigned | getVectorMinNumElements () const |
Given a vector type, return the minimum number of elements it contains. More... | |
ElementCount | getVectorElementCount () const |
unsigned | getVectorNumElements () const |
TypeSize | getSizeInBits () const |
Returns the size of the specified MVT in bits. More... | |
uint64_t | getFixedSizeInBits () const |
Return the size of the specified fixed width value type in bits. More... | |
uint64_t | getScalarSizeInBits () const |
TypeSize | getStoreSize () const |
Return the number of bytes overwritten by a store of the specified value type. More... | |
uint64_t | getScalarStoreSize () const |
TypeSize | getStoreSizeInBits () const |
Return the number of bits overwritten by a store of the specified value type. More... | |
bool | isByteSized () const |
Returns true if the number of bits for the type is a multiple of an 8-bit byte. More... | |
bool | knownBitsGT (MVT VT) const |
Return true if we know at compile time this has more bits than VT. More... | |
bool | knownBitsGE (MVT VT) const |
Return true if we know at compile time this has more than or the same bits as VT. More... | |
bool | knownBitsLT (MVT VT) const |
Return true if we know at compile time this has fewer bits than VT. More... | |
bool | knownBitsLE (MVT VT) const |
Return true if we know at compile time this has fewer than or the same bits as VT. More... | |
bool | bitsGT (MVT VT) const |
Return true if this has more bits than VT. More... | |
bool | bitsGE (MVT VT) const |
Return true if this has no less bits than VT. More... | |
bool | bitsLT (MVT VT) const |
Return true if this has less bits than VT. More... | |
bool | bitsLE (MVT VT) const |
Return true if this has no more bits than VT. More... | |
Static Public Member Functions | |
static MVT | getFloatingPointVT (unsigned BitWidth) |
static MVT | getIntegerVT (unsigned BitWidth) |
static MVT | getVectorVT (MVT VT, unsigned NumElements) |
static MVT | getScalableVectorVT (MVT VT, unsigned NumElements) |
static MVT | getVectorVT (MVT VT, unsigned NumElements, bool IsScalable) |
static MVT | getVectorVT (MVT VT, ElementCount EC) |
static MVT | getVT (Type *Ty, bool HandleUnknown=false) |
Return the value type corresponding to the specified type. More... | |
static auto | all_valuetypes () |
SimpleValueType Iteration. More... | |
static auto | integer_valuetypes () |
static auto | fp_valuetypes () |
static auto | vector_valuetypes () |
static auto | fixedlen_vector_valuetypes () |
static auto | scalable_vector_valuetypes () |
static auto | integer_fixedlen_vector_valuetypes () |
static auto | fp_fixedlen_vector_valuetypes () |
static auto | integer_scalable_vector_valuetypes () |
static auto | fp_scalable_vector_valuetypes () |
Public Attributes | |
SimpleValueType | SimpleTy = INVALID_SIMPLE_VALUE_TYPE |
Every type that is supported natively by some processor targeted by LLVM occurs here. This means that any legal value type can be represented by an MVT.
Definition at line 31 of file MachineValueType.h.
enum llvm::MVT::SimpleValueType : uint8_t |
Definition at line 33 of file MachineValueType.h.
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constexprdefault |
Referenced by getVT().
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inlineconstexpr |
Definition at line 332 of file MachineValueType.h.
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inlinestatic |
SimpleValueType Iteration.
Definition at line 1456 of file MachineValueType.h.
References llvm::enum_seq_inclusive(), FIRST_VALUETYPE, llvm::force_iteration_on_noniterable_enum, and LAST_VALUETYPE.
Referenced by llvm::TargetLoweringBase::initActions().
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Return true if this has no less bits than VT.
Definition at line 1156 of file MachineValueType.h.
References assert(), isScalableVector(), and knownBitsGE().
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Return true if this has more bits than VT.
Definition at line 1149 of file MachineValueType.h.
References assert(), isScalableVector(), and knownBitsGT().
Referenced by LowerFCOPYSIGN(), and lowerVECTOR_SHUFFLE().
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Return true if this has no more bits than VT.
Definition at line 1170 of file MachineValueType.h.
References assert(), isScalableVector(), and knownBitsLE().
Referenced by getMaskNode(), llvm::SITargetLowering::getPreferredVectorAction(), and lowerBUILD_VECTOR().
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Return true if this has less bits than VT.
Definition at line 1163 of file MachineValueType.h.
References assert(), isScalableVector(), and knownBitsLT().
Referenced by LowerFCOPYSIGN(), lowerVectorIntrinsicScalars(), and selectVSplatSimmHelper().
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Return the type converted to an equivalently sized integer or vector with integer element type.
Similar to changeVectorElementTypeToInteger, but also handles scalars.
Definition at line 490 of file MachineValueType.h.
References changeVectorElementTypeToInteger(), getIntegerVT(), getSizeInBits(), and isVector().
Referenced by llvm::EVT::changeTypeToInteger(), lowerShuffleWithPERMV(), lowerVECTOR_SHUFFLE(), and matchBinaryShuffle().
Return a VT for a vector type whose attributes match ourselves with the exception of the element type that is chosen by the caller.
Definition at line 480 of file MachineValueType.h.
References assert(), getVectorElementCount(), getVectorVT(), INVALID_SIMPLE_VALUE_TYPE, and SimpleTy.
Referenced by llvm::EVT::changeVectorElementType(), lowerBUILD_VECTOR(), llvm::RISCVTargetLowering::LowerOperation(), lowerVECTOR_SHUFFLE(), matchUnaryShuffle(), and promoteXINT_TO_FP().
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Return a vector with the same number of elements as this vector, but with the element type converted to an integer type with the same bitwidth.
Definition at line 469 of file MachineValueType.h.
References assert(), getIntegerVT(), getSizeInBits(), getVectorElementCount(), getVectorElementType(), getVectorVT(), INVALID_SIMPLE_VALUE_TYPE, and SimpleTy.
Referenced by changeTypeToInteger(), llvm::EVT::changeVectorElementTypeToInteger(), lowerCTLZ_CTTZ_ZERO_UNDEF(), lowerFROUND(), and lowerFTRUNC_FCEIL_FFLOOR().
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inlinestatic |
Definition at line 1478 of file MachineValueType.h.
References llvm::enum_seq_inclusive(), FIRST_FIXEDLEN_VECTOR_VALUETYPE, llvm::force_iteration_on_noniterable_enum, and LAST_FIXEDLEN_VECTOR_VALUETYPE.
Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering(), llvm::ARMTargetLowering::ARMTargetLowering(), llvm::HexagonTargetLowering::HexagonTargetLowering(), llvm::MipsSETargetLowering::MipsSETargetLowering(), llvm::NVPTXTargetLowering::NVPTXTargetLowering(), llvm::PPCTargetLowering::PPCTargetLowering(), llvm::SystemZTargetLowering::SystemZTargetLowering(), llvm::WebAssemblyTargetLowering::WebAssemblyTargetLowering(), and llvm::X86TargetLowering::X86TargetLowering().
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inlinestatic |
Definition at line 1496 of file MachineValueType.h.
References llvm::enum_seq_inclusive(), FIRST_FP_FIXEDLEN_VECTOR_VALUETYPE, llvm::force_iteration_on_noniterable_enum, and LAST_FP_FIXEDLEN_VECTOR_VALUETYPE.
Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering(), llvm::MipsTargetLowering::MipsTargetLowering(), and llvm::RISCVTargetLowering::RISCVTargetLowering().
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inlinestatic |
Definition at line 1508 of file MachineValueType.h.
References llvm::enum_seq_inclusive(), FIRST_FP_SCALABLE_VECTOR_VALUETYPE, llvm::force_iteration_on_noniterable_enum, and LAST_FP_SCALABLE_VECTOR_VALUETYPE.
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inlinestatic |
Definition at line 1467 of file MachineValueType.h.
References llvm::enum_seq_inclusive(), FIRST_FP_VALUETYPE, llvm::force_iteration_on_noniterable_enum, and LAST_FP_VALUETYPE.
Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering(), llvm::ARMTargetLowering::ARMTargetLowering(), llvm::HexagonTargetLowering::HexagonTargetLowering(), llvm::TargetLoweringBase::initActions(), llvm::MipsTargetLowering::MipsTargetLowering(), llvm::PPCTargetLowering::PPCTargetLowering(), llvm::SparcTargetLowering::SparcTargetLowering(), and llvm::SystemZTargetLowering::SystemZTargetLowering().
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Return the size of the specified fixed width value type in bits.
The function will assert if the type is scalable.
Definition at line 1087 of file MachineValueType.h.
References llvm::TypeSize::getFixedSize(), and getSizeInBits().
Referenced by CC_AIX(), combineINSERT_SUBVECTOR(), combineTargetShuffle(), llvm::TargetLoweringBase::computeRegisterProperties(), getCopyToPartsVector(), llvm::MipsTargetLowering::getVectorTypeBreakdownForCallingConv(), LowerEXTEND_VECTOR_INREG(), LowerVSETCC(), MatchingStackOffset(), truncateScalarIntegerArg(), useRVVForFixedLengthVectorVT(), and widenSubVector().
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inlinestatic |
Definition at line 1176 of file MachineValueType.h.
References llvm::BitWidth, f128, f16, f32, f64, f80, and llvm_unreachable.
Referenced by combineBitcast(), combineCVTP2I_CVTTP2I(), combinePredicateReduction(), combineX86ShuffleChain(), combineX86ShufflesConstants(), EltsFromConsecutiveLoads(), llvm::EVT::getFloatingPointVT(), lower256BitShuffle(), lowerVECTOR_SHUFFLE(), and tryWidenMaskForShuffle().
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Return a VT for a vector type with the same element type but half the number of elements.
Definition at line 498 of file MachineValueType.h.
References assert(), getVectorElementCount(), getVectorElementType(), and getVectorVT().
Referenced by combineSetCCMOVMSK(), combineTargetShuffle(), llvm::RISCVTargetLowering::decomposeSubvectorInsertExtractToSubRegs(), getHopForBuildVector(), getShuffleHalfVectors(), LowerAVXCONCAT_VECTORS(), LowerAVXExtend(), LowerCONCAT_VECTORSvXi1(), LowerEXTEND_VECTOR_INREG(), lowerShuffleWithUndefHalf(), LowerSIGN_EXTEND(), lowerV2X128Shuffle(), and lowerVECTOR_SHUFFLE().
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inlinestatic |
Definition at line 1193 of file MachineValueType.h.
References llvm::BitWidth, i1, i128, i16, i2, i32, i4, i64, i8, and INVALID_SIMPLE_VALUE_TYPE.
Referenced by changeTypeToInteger(), changeVectorElementTypeToInteger(), combineADDSUB_VLToVWADDSUB_VL(), combineBitcast(), combineConcatVectorOps(), combineMUL_VLToVWMUL_VL(), combineX86INT_TO_FP(), combineX86ShuffleChain(), combineX86ShufflesConstants(), llvm::computeSignatureVTs(), EltsFromConsecutiveLoads(), ExtractBitFromMaskVector(), llvm::EVT::getIntegerVT(), llvm::getMVTForLLT(), getPermuteNode(), llvm::TargetLoweringBase::getPointerMemTy(), llvm::TargetLoweringBase::getPointerTy(), llvm::AArch64TargetLowering::getPointerTy(), getRegistersForValue(), llvm::M68kTargetLowering::getScalarShiftAmountTy(), llvm::TargetLoweringBase::getScalarShiftAmountTy(), llvm::ARMTargetLowering::getTgtMemIntrinsic(), llvm::SPIRVTargetLowering::getVectorIdxTy(), getVT(), llvm::TargetLoweringBase::hasFastEqualityCompare(), llvm::X86TargetLowering::hasFastEqualityCompare(), llvm::TargetLoweringBase::initActions(), insert1BitVector(), InsertBitToMaskVector(), is128BitUnpackShuffleMask(), llvm::SystemZVectorConstantInfo::isVectorConstantLegal(), lowerBUILD_VECTOR(), LowerBUILD_VECTORvXi1(), lowerBuildVectorAsBroadcast(), LowerCTPOP(), lowerFCOPYSIGN64(), LowerFunnelShift(), llvm::RISCVTargetLowering::LowerOperation(), LowerRotate(), llvm::HexagonTargetLowering::LowerSETCC(), lowerShuffleAsBlend(), lowerShuffleAsPermuteAndUnpack(), lowerShuffleAsSpecificZeroOrAnyExtend(), lowerShuffleAsVTRUNC(), lowerShuffleToEXPAND(), lowerShuffleWithPACK(), LowerTruncateVecI1(), llvm::HexagonTargetLowering::LowerUnalignedLoad(), lowerVECTOR_SHUFFLE(), LowerVectorCTLZInRegLUT(), llvm::HexagonTargetLowering::LowerVSELECT(), lowerX86FPLogicOp(), matchShuffleAsBitRotate(), matchShuffleAsShift(), matchShuffleAsVTRUNC(), matchShuffleWithPACK(), matchUnaryPermuteShuffle(), matchUnaryShuffle(), memsetStore(), llvm::TargetLowering::ParseConstraints(), PerformVECREDUCE_ADDCombine(), PerformVQDMULHCombine(), llvm::X86TargetLowering::ReplaceNodeResults(), scaleVectorType(), llvm::AArch64TargetLowering::shouldTransformSignedTruncationCheck(), llvm::X86TargetLowering::shouldTransformSignedTruncationCheck(), ShrinkLoadReplaceStoreWithStore(), llvm::X86TargetLowering::SimplifyDemandedBitsForTargetNode(), skipExtensionForVectorMULL(), SkipExtensionForVMULL(), llvm::SparcTargetLowering::SparcTargetLowering(), llvm::HexagonDAGToDAGISel::StoreInstrForLoadIntrinsic(), llvm::SystemZTargetLowering::SystemZTargetLowering(), TryCombineBaseUpdate(), tryWidenMaskForShuffle(), unpackFromMemLoc(), and llvm::X86TargetLowering::X86TargetLowering().
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Widens the length of the given vector MVT up to the nearest power of 2 and returns that type.
Definition at line 513 of file MachineValueType.h.
References llvm::LinearPolySize< ElementCount >::get(), llvm::LinearPolySize< LeafTy >::getKnownMinValue(), getVectorElementCount(), getVectorElementType(), getVectorVT(), isPow2VectorType(), llvm::LinearPolySize< LeafTy >::isScalable(), and llvm::Log2_32_Ceil().
Referenced by llvm::TargetLoweringBase::computeRegisterProperties().
Definition at line 1357 of file MachineValueType.h.
References bf16, f16, f32, f64, i1, i16, i32, i64, i8, INVALID_SIMPLE_VALUE_TYPE, nxv16bf16, nxv16f16, nxv16f32, nxv16i1, nxv16i16, nxv16i32, nxv16i64, nxv16i8, nxv1bf16, nxv1f16, nxv1f32, nxv1f64, nxv1i1, nxv1i16, nxv1i32, nxv1i64, nxv1i8, nxv2bf16, nxv2f16, nxv2f32, nxv2f64, nxv2i1, nxv2i16, nxv2i32, nxv2i64, nxv2i8, nxv32bf16, nxv32f16, nxv32i1, nxv32i16, nxv32i32, nxv32i64, nxv32i8, nxv4bf16, nxv4f16, nxv4f32, nxv4f64, nxv4i1, nxv4i16, nxv4i32, nxv4i64, nxv4i8, nxv64i1, nxv64i8, nxv8bf16, nxv8f16, nxv8f32, nxv8f64, nxv8i1, nxv8i16, nxv8i32, nxv8i64, nxv8i8, and SimpleTy.
Referenced by getContainerForFixedLengthVector(), getLMUL1VT(), and getVectorVT().
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Definition at line 1091 of file MachineValueType.h.
References llvm::TypeSize::getFixedSize(), getScalarType(), and getSizeInBits().
Referenced by canonicalizeBitSelect(), CC_RISCV(), CC_RISCV_FastCC(), combineAddOfPMADDWD(), combineADDSUB_VLToVWADDSUB_VL(), combineAndnp(), combineConcatVectorOps(), combineCVTP2I_CVTTP2I(), combineMOVMSK(), combineMUL_VLToVWMUL_VL(), combineSetCCMOVMSK(), combineStore(), combineTargetShuffle(), combineVEXTRACT_STORE(), combineVWADD_W_VL_VWSUB_W_VL(), combineX86INT_TO_FP(), combineX86ShuffleChain(), llvm::X86TargetLowering::ComputeNumSignBitsForTargetNode(), llvm::TargetLoweringBase::computeRegisterProperties(), createPackShuffleMask(), createVariablePermute(), DecodePALIGNRMask(), expandFP_TO_UINT_SSE(), getAVX512Node(), getAVX512TruncNode(), llvm::X86TTIImpl::getCmpSelInstrCost(), getConstantVector(), getConstVector(), llvm::RegsForValue::getCopyFromRegs(), getFauxShuffleMask(), getMemCmpLoad(), getPack(), llvm::SystemZTargetLowering::getPreferredVectorAction(), llvm::PPCTargetLowering::getPreferredVectorAction(), getPSHUFShuffleMask(), llvm::X86TTIImpl::getReplicationShuffleCost(), getScalarValueForVectorElement(), getTargetShuffleMask(), getTargetVShiftNode(), getVectorTypeBreakdownMVT(), is128BitLaneCrossingShuffleMask(), isHorizontalBinOp(), isInterleaveShuffle(), isRepeatedShuffleMask(), isRepeatedTargetShuffleMask(), lower256BitShuffle(), LowerADDSAT_SUBSAT(), LowerBITREVERSE_XOP(), lowerBUILD_VECTOR(), lowerBuildVectorAsBroadcast(), lowerBuildVectorToBitOp(), lowerCTLZ_CTTZ_ZERO_UNDEF(), LowerCTTZ(), LowerEXTEND_VECTOR_INREG(), LowerFABSorFNEG(), LowerFCOPYSIGN(), LowerFunnelShift(), LowerINTRINSIC_W_CHAIN(), LowerMGATHER(), LowerMLOAD(), LowerMSCATTER(), LowerMSTORE(), LowerRotate(), LowerShift(), LowerShiftByScalarImmediate(), lowerShuffleAsBitRotate(), lowerShuffleAsBlend(), lowerShuffleAsBlendAndPermute(), lowerShuffleAsBroadcast(), lowerShuffleAsByteRotateAndPermute(), lowerShuffleAsByteShiftMask(), lowerShuffleAsLanePermuteAndRepeatedMask(), lowerShuffleAsPermuteAndUnpack(), lowerShuffleAsRepeatedMaskAndLanePermute(), lowerShuffleAsShift(), lowerShuffleAsSpecificZeroOrAnyExtend(), lowerShuffleAsVTRUNC(), lowerShuffleAsZeroOrAnyExtend(), lowerShuffleOfExtractsAsVperm(), lowerShuffleWithPACK(), lowerShuffleWithPSHUFB(), lowerShuffleWithVPMOV(), LowerTruncateVecI1(), lowerV4X128Shuffle(), lowerVECTOR_SHUFFLE(), LowerVectorCTLZInRegLUT(), lowerVectorIntrinsicScalars(), LowerVSETCC(), lowerX86FPLogicOp(), LowerZERO_EXTEND_Mask(), matchBinaryPermuteShuffle(), matchBinaryShuffle(), matchShuffleAsEXTRQ(), matchShuffleAsINSERTQ(), matchShuffleAsVTRUNC(), matchShuffleWithPACK(), matchShuffleWithSHUFPD(), matchUnaryPermuteShuffle(), matchUnaryShuffle(), llvm::X86::mayFoldLoadIntoBroadcastFromMem(), PerformVQDMULHCombine(), scaleVectorType(), llvm::X86TargetLowering::SimplifyDemandedBitsForTargetNode(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), supportedVectorShiftWithImm(), supportedVectorVarShift(), and vectorizeExtractedCast().
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Definition at line 1108 of file MachineValueType.h.
References llvm::TypeSize::getFixedSize(), getScalarType(), and getStoreSize().
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If this is a vector, return the element type, otherwise return this.
Definition at line 524 of file MachineValueType.h.
References getVectorElementType(), and isVector().
Referenced by llvm::AMDGPUTargetLowering::analyzeFormalArgumentsCompute(), combineConcatVectorOps(), combineEXTRACT_SUBVECTOR(), combineMOVMSK(), combineStore(), combineVectorSignBitsTruncation(), constructDup(), createVariablePermute(), llvm::TargetLowering::expandBSWAP(), getAVX512Node(), getAVX512TruncNode(), getFauxShuffleMask(), llvm::SITargetLowering::getPreferredVectorAction(), llvm::NVPTXTargetLowering::getPreferredVectorAction(), llvm::X86TTIImpl::getReplicationShuffleCost(), getScalarSizeInBits(), getScalarStoreSize(), getTargetShuffleMask(), getTargetVShiftNode(), llvm::X86TargetLowering::isShuffleMaskLegal(), LowerBITREVERSE(), lowerBuildVectorAsBroadcast(), lowerBuildVectorToBitOp(), LowerMLOAD(), LowerMSTORE(), lowerShuffleAsBroadcast(), lowerShuffleAsVALIGN(), lowerShuffleAsVTRUNC(), llvm::AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(), lowerVECTOR_SHUFFLE(), LowerVectorCTPOP(), matchUnaryShuffle(), scalarizeVectorStore(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), vectorizeExtractedCast(), and widenSubVector().
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Returns the size of the specified MVT in bits.
If the value type is a scalable vector type, the scalable property will be set and the runtime size will be a positive integer multiple of the base size.
Definition at line 883 of file MachineValueType.h.
References Any, bf16, externref, f128, f16, f32, f64, f80, fAny, llvm::TypeSize::Fixed(), funcref, i1, i128, i16, i2, i32, i4, i64, i64x8, i8, iAny, iPTR, iPTRAny, llvm_unreachable, Metadata, nxv16bf16, nxv16f16, nxv16f32, nxv16i1, nxv16i16, nxv16i32, nxv16i64, nxv16i8, nxv1bf16, nxv1f16, nxv1f32, nxv1f64, nxv1i1, nxv1i16, nxv1i32, nxv1i64, nxv1i8, nxv2bf16, nxv2f16, nxv2f32, nxv2f64, nxv2i1, nxv2i16, nxv2i32, nxv2i64, nxv2i8, nxv32bf16, nxv32f16, nxv32i1, nxv32i16, nxv32i32, nxv32i64, nxv32i8, nxv4bf16, nxv4f16, nxv4f32, nxv4f64, nxv4i1, nxv4i16, nxv4i32, nxv4i64, nxv4i8, nxv64i1, nxv64i8, nxv8bf16, nxv8f16, nxv8f32, nxv8f64, nxv8i1, nxv8i16, nxv8i32, nxv8i64, nxv8i8, Other, ppcf128, llvm::TypeSize::Scalable(), SimpleTy, token, v1024f32, v1024i1, v1024i32, v1024i8, v128bf16, v128f16, v128f32, v128f64, v128i1, v128i16, v128i2, v128i32, v128i64, v128i8, v16bf16, v16f16, v16f32, v16f64, v16i1, v16i16, v16i32, v16i64, v16i8, v1f16, v1f32, v1f64, v1i1, v1i128, v1i16, v1i32, v1i64, v1i8, v2048f32, v2048i32, v256f16, v256f32, v256f64, v256i1, v256i16, v256i32, v256i64, v256i8, v2bf16, v2f16, v2f32, v2f64, v2i1, v2i16, v2i32, v2i64, v2i8, v32bf16, v32f16, v32f32, v32f64, v32i1, v32i16, v32i32, v32i64, v32i8, v3bf16, v3f16, v3f32, v3f64, v3i16, v3i32, v3i64, v4bf16, v4f16, v4f32, v4f64, v4i1, v4i16, v4i32, v4i64, v4i8, v512f16, v512f32, v512i1, v512i16, v512i32, v512i8, v5f32, v5i32, v64bf16, v64f16, v64f32, v64f64, v64i1, v64i16, v64i32, v64i4, v64i64, v64i8, v6f32, v6i32, v7f32, v7i32, v8bf16, v8f16, v8f32, v8f64, v8i1, v8i16, v8i32, v8i64, v8i8, vAny, x86amx, and x86mmx.
Referenced by canonicalizeBitSelect(), CC_ARM_AAPCS_Custom_Aggregate(), CC_Sparc64_Full(), CC_Sparc64_Half(), CC_X86_32_VectorCall(), CC_X86_64_VectorCall(), llvm::CC_XPLINK64_Shadow_Stack(), changeTypeToInteger(), changeVectorElementTypeToInteger(), combineEXTRACT_SUBVECTOR(), combinePredicateReduction(), combineSetCCMOVMSK(), combineShiftRightArithmetic(), combineTargetShuffle(), combineVectorHADDSUB(), combineVectorSignBitsTruncation(), combineX86ShuffleChain(), combineX86ShufflesConstants(), combineX86ShufflesRecursively(), convertShiftLeftToScale(), createPackShuffleMask(), createShuffleStride(), createVariablePermute(), createVPDPBUSD(), DecodePALIGNRMask(), EltsFromConsecutiveLoads(), llvm::TargetLowering::expandUnalignedLoad(), llvm::TargetLowering::expandUnalignedStore(), llvm::FastISel::fastEmit_ri_(), finishStackBlock(), genShuffleBland(), getAVX512Node(), getAVX512TruncNode(), getCopyFromParts(), getCopyFromPartsVector(), getCopyToParts(), getCopyToPartsVector(), getFauxShuffleMask(), getFixedSizeInBits(), getHopForBuildVector(), llvm::getLLTForMVT(), llvm::RISCVTargetLowering::getLMUL(), getLMUL1VT(), llvm::TargetLoweringBase::getNumRegisters(), getPack(), llvm::HvxSelector::getPairVT(), llvm::PPCTargetLowering::getPreferredVectorAction(), getPromotedVectorElementType(), getPSHUFShuffleMask(), llvm::HexagonTargetLowering::getRegForInlineAsmConstraint(), llvm::SITargetLowering::getRegForInlineAsmConstraint(), llvm::ARMTargetLowering::getRegForInlineAsmConstraint(), llvm::X86TargetLowering::getRegForInlineAsmConstraint(), getRegistersForValue(), llvm::RegsForValue::getRegsAndSizes(), getScalarSizeInBits(), getScalarValueForVectorElement(), llvm::X86TargetLowering::getSetCCResultType(), llvm::TargetLoweringBase::getShiftAmountTy(), llvm::HvxSelector::getSingleVT(), llvm::EVT::getSizeInBits(), getStoreSize(), getTargetShuffleAndZeroables(), getTargetVShiftByConstNode(), getTargetVShiftNode(), llvm::HexagonSubtarget::getTypeAlignment(), llvm::AArch64TargetLowering::getVaListSizeInBits(), llvm::TargetLoweringBase::getVaListSizeInBits(), llvm::TargetLoweringBase::getVectorTypeBreakdown(), llvm::MipsTargetLowering::getVectorTypeBreakdownForCallingConv(), getZeroVector(), group2Shuffle(), hasBZHI(), insert1BitVector(), isByteSized(), IsElementEquivalent(), isHorizontalBinOp(), llvm::HexagonSubtarget::isHVXVectorType(), llvm::X86TargetLowering::isShuffleMaskLegal(), isSupportedType(), isTargetShuffleEquivalent(), llvm::HexagonSubtarget::isTypeForHVX(), llvm::RISCVTargetLowering::joinRegisterPartsIntoValue(), knownBitsGE(), knownBitsGT(), knownBitsLE(), knownBitsLT(), llvm::LLT::LLT(), llvm::X86TargetLowering::LowerAsmOutputForConstraint(), LowerAsSplatVectorLoad(), llvm::HexagonTargetLowering::LowerBITCAST(), LowerBITREVERSE_XOP(), llvm::HexagonTargetLowering::LowerBUILD_VECTOR(), lowerBUILD_VECTOR(), LowerBUILD_VECTORvXi1(), lowerBuildVectorAsBroadcast(), llvm::SystemZTargetLowering::LowerCall(), llvm::TargetLowering::LowerCallTo(), llvm::HexagonTargetLowering::LowerCONCAT_VECTORS(), LowerCTLZ(), LowerEXTEND_VECTOR_INREG(), LowerEXTRACT_VECTOR_ELT_SSE4(), llvm::VETargetLowering::LowerFormalArguments(), llvm::HexagonTargetLowering::LowerFormalArguments(), llvm::SparcTargetLowering::LowerFormalArguments_64(), lowerFPToIntToFP(), LowerHorizontalByteSum(), LowerMGATHER(), LowerMLOAD(), LowerMSCATTER(), LowerMSTORE(), llvm::RISCVTargetLowering::LowerOperation(), LowerPARITY(), LowerSCALAR_TO_VECTOR(), llvm::HexagonTargetLowering::LowerSETCC(), lowerShuffleAsBlend(), lowerShuffleAsBlendOfPSHUFBs(), lowerShuffleAsByteRotate(), lowerShuffleAsByteRotateAndPermute(), lowerShuffleAsDecomposedShuffleMerge(), lowerShuffleAsElementInsertion(), lowerShuffleAsLanePermuteAndPermute(), lowerShuffleAsLanePermuteAndRepeatedMask(), lowerShuffleAsRepeatedMaskAndLanePermute(), lowerShuffleAsSplitOrBlend(), lowerShuffleAsTruncBroadcast(), lowerShuffleAsUNPCKAndPermute(), lowerShuffleAsZeroOrAnyExtend(), lowerShuffleWithPACK(), lowerShuffleWithPERMV(), lowerShuffleWithPSHUFB(), lowerShuffleWithUndefHalf(), LowerSIGN_EXTEND_Mask(), llvm::LanaiTargetLowering::LowerSRL_PARTS(), LowerTruncateVecI1(), llvm::HexagonTargetLowering::LowerUnalignedLoad(), llvm::HexagonTargetLowering::LowerVECTOR_SHUFFLE(), lowerVECTOR_SHUFFLE(), LowerVectorCTLZ_AVX512CDI(), LowerVectorCTPOP(), lowerVectorIntrinsicScalars(), llvm::HexagonTargetLowering::LowerVSELECT(), LowerVSETCC(), lowerX86FPLogicOp(), LowerZERO_EXTEND_Mask(), matchBinaryPermuteShuffle(), MatchingStackOffset(), matchUnaryPermuteShuffle(), narrowExtractedVectorSelect(), llvm::TargetLowering::ParseConstraints(), llvm::RISCVTargetLowering::PerformDAGCombine(), performFDivCombine(), performFpToIntCombine(), performScatterStoreCombine(), PerformTruncatingStoreCombine(), PerformVCVTCombine(), PerformVDIVCombine(), llvm::RISCVTargetLowering::ReplaceNodeResults(), llvm::X86TargetLowering::ReplaceNodeResults(), llvm::HexagonDAGToDAGISel::SelectQ2V(), llvm::RISCVDAGToDAGISel::selectSExti32(), llvm::HexagonDAGToDAGISel::SelectV2Q(), llvm::HexagonDAGToDAGISel::SelectVAlign(), selectVSplatSimmHelper(), llvm::RISCVDAGToDAGISel::selectZExti32(), setGroupSize(), splitAndLowerShuffle(), llvm::RISCVTargetLowering::splitValueIntoRegisterParts(), TryCombineBaseUpdate(), tryCombineShiftImm(), UnpackFromArgumentSlot(), and useRVVForFixedLengthVectorVT().
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Return the number of bytes overwritten by a store of the specified value type.
If the value type is a scalable vector type, the scalable property will be set and the runtime size will be a positive integer multiple of the base size.
Definition at line 1101 of file MachineValueType.h.
References llvm::TypeSize::getKnownMinSize(), getSizeInBits(), and llvm::LinearPolySize< LeafTy >::isScalable().
Referenced by llvm::analyzeArguments(), llvm::analyzeReturnValues(), CC_AIX(), CC_MipsO32(), CC_RISCV(), CC_RISCV_FastCC(), llvm::PPCTargetLowering::emitEHSjLjLongJmp(), llvm::PPCTargetLowering::emitEHSjLjSetJmp(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getInterleavedMemoryOpCost(), llvm::X86TTIImpl::getInterleavedMemoryOpCostAVX512(), llvm::MSP430TargetLowering::getReturnAddressFrameIndex(), getScalarStoreSize(), getStoreSizeInBits(), llvm::SITargetLowering::LowerCall(), lowerShuffleAsBroadcast(), lowerV2X128Shuffle(), lowerVECTOR_SHUFFLE(), and scalarizeVectorStore().
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Return the number of bits overwritten by a store of the specified value type.
If the value type is a scalable vector type, the scalable property will be set and the runtime size will be a positive integer multiple of the base size.
Definition at line 1118 of file MachineValueType.h.
References getStoreSize().
Referenced by llvm::HexagonTargetLowering::LowerCall(), and llvm::HexagonTargetLowering::LowerFormalArguments().
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Definition at line 865 of file MachineValueType.h.
References llvm::LinearPolySize< ElementCount >::get(), getVectorMinNumElements(), and isScalableVector().
Referenced by changeVectorElementType(), changeVectorElementTypeToInteger(), combineADDSUB_VLToVWADDSUB_VL(), combineMUL_VLToVWMUL_VL(), llvm::TargetLoweringBase::computeRegisterProperties(), llvm::RISCVTargetLowering::decomposeSubvectorInsertExtractToSubRegs(), getCopyToPartsVector(), getHalfNumVectorElementsVT(), llvm::getLLTForMVT(), getPow2VectorType(), llvm::TargetLoweringBase::getPreferredVectorAction(), llvm::EVT::getVectorElementCount(), getVectorTypeBreakdownMVT(), llvm::LLT::LLT(), lowerCTLZ_CTTZ_ZERO_UNDEF(), lowerFROUND(), lowerFTRUNC_FCEIL_FFLOOR(), llvm::RISCVTargetLowering::LowerOperation(), lowerVECTOR_SHUFFLE(), lowerVectorIntrinsicScalars(), llvm::RISCVTargetLowering::RISCVTargetLowering(), and splatPartsI64WithVL().
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Definition at line 528 of file MachineValueType.h.
References bf16, f16, f32, f64, i1, i128, i16, i2, i32, i4, i64, i8, llvm_unreachable, nxv16bf16, nxv16f16, nxv16f32, nxv16i1, nxv16i16, nxv16i32, nxv16i64, nxv16i8, nxv1bf16, nxv1f16, nxv1f32, nxv1f64, nxv1i1, nxv1i16, nxv1i32, nxv1i64, nxv1i8, nxv2bf16, nxv2f16, nxv2f32, nxv2f64, nxv2i1, nxv2i16, nxv2i32, nxv2i64, nxv2i8, nxv32bf16, nxv32f16, nxv32i1, nxv32i16, nxv32i32, nxv32i64, nxv32i8, nxv4bf16, nxv4f16, nxv4f32, nxv4f64, nxv4i1, nxv4i16, nxv4i32, nxv4i64, nxv4i8, nxv64i1, nxv64i8, nxv8bf16, nxv8f16, nxv8f32, nxv8f64, nxv8i1, nxv8i16, nxv8i32, nxv8i64, nxv8i8, SimpleTy, v1024f32, v1024i1, v1024i32, v1024i8, v128bf16, v128f16, v128f32, v128f64, v128i1, v128i16, v128i2, v128i32, v128i64, v128i8, v16bf16, v16f16, v16f32, v16f64, v16i1, v16i16, v16i32, v16i64, v16i8, v1f16, v1f32, v1f64, v1i1, v1i128, v1i16, v1i32, v1i64, v1i8, v2048f32, v2048i32, v256f16, v256f32, v256f64, v256i1, v256i16, v256i32, v256i64, v256i8, v2bf16, v2f16, v2f32, v2f64, v2i1, v2i16, v2i32, v2i64, v2i8, v32bf16, v32f16, v32f32, v32f64, v32i1, v32i16, v32i32, v32i64, v32i8, v3bf16, v3f16, v3f32, v3f64, v3i16, v3i32, v3i64, v4bf16, v4f16, v4f32, v4f64, v4i1, v4i16, v4i32, v4i64, v4i8, v512f16, v512f32, v512i1, v512i16, v512i32, v512i8, v5f32, v5i32, v64bf16, v64f16, v64f32, v64f64, v64i1, v64i16, v64i32, v64i4, v64i64, v64i8, v6f32, v6i32, v7f32, v7i32, v8bf16, v8f16, v8f32, v8f64, v8i1, v8i16, v8i32, v8i64, and v8i8.
Referenced by changeVectorElementTypeToInteger(), combineBitcast(), combineEXTRACT_SUBVECTOR(), combineINSERT_SUBVECTOR(), combineRedundantDWordShuffle(), combineShuffleToAddSubOrFMAddSub(), combineTargetShuffle(), llvm::TargetLoweringBase::computeRegisterProperties(), convertShiftLeftToScale(), ExtendToType(), getConstVector(), getContainerForFixedLengthVector(), getHalfNumVectorElementsVT(), llvm::getLLTForMVT(), llvm::RISCVTargetLowering::getLMUL(), getLMUL1VT(), getPow2VectorType(), llvm::HexagonTargetLowering::getPreferredVectorAction(), llvm::X86TargetLowering::getPreferredVectorAction(), llvm::RISCVTargetLowering::getRegClassIDForVecVT(), getScalarType(), getScalarValueForVectorElement(), llvm::X86TargetLowering::getSetCCResultType(), getShuffleScalarElt(), getTargetVShiftByConstNode(), getTargetVShiftNode(), llvm::X86TargetLowering::getTgtMemIntrinsic(), llvm::X86TTIImpl::getTypeBasedIntrinsicInstrCost(), getUnderlyingExtractedFromVec(), llvm::EVT::getVectorElementType(), getVectorTypeBreakdownMVT(), getZeroVector(), incDecVectorConstant(), llvm::HexagonSubtarget::isHVXElementType(), llvm::HexagonSubtarget::isHVXVectorType(), isLegalT2AddressImmediate(), llvm::RISCVTargetLowering::joinRegisterPartsIntoValue(), llvm::LLT::LLT(), LowerANY_EXTEND(), LowerAVXExtend(), LowerBITCAST(), lowerBUILD_VECTOR(), LowerBUILD_VECTORvXi1(), LowerBuildVectorv4x32(), llvm::HexagonTargetLowering::LowerCONCAT_VECTORS(), LowerCONCAT_VECTORS(), LowerEXTEND_VECTOR_INREG(), llvm::HexagonTargetLowering::LowerEXTRACT_VECTOR_ELT(), LowerHorizontalByteSum(), LowerIntVSETCC_AVX512(), LowerLoad(), LowerMGATHER(), LowerMLOAD(), LowerMSCATTER(), llvm::RISCVTargetLowering::LowerOperation(), LowerSCALAR_TO_VECTOR(), llvm::HexagonTargetLowering::LowerSETCC(), lowerShuffleAsBitBlend(), lowerShuffleAsBitMask(), lowerShuffleAsBroadcast(), lowerShuffleAsElementInsertion(), lowerShuffleAsTruncBroadcast(), lowerShuffleWithUndefHalf(), lowerShuffleWithVPMOV(), LowerSIGN_EXTEND(), LowerSIGN_EXTEND_Mask(), LowerTruncateVecI1(), lowerV2X128Shuffle(), lowerV4X128Shuffle(), lowerV8I16GeneralSingleInputShuffle(), llvm::HexagonTargetLowering::LowerVECTOR_SHUFFLE(), lowerVECTOR_SHUFFLE(), LowerVectorCTLZ(), LowerVectorCTLZ_AVX512CDI(), LowerVectorCTPOP(), LowerVectorCTPOPInRegLUT(), lowerVectorIntrinsicScalars(), llvm::HexagonTargetLowering::LowerVSELECT(), LowerVSETCC(), LowerVSETCCWithSUBUS(), LowerZERO_EXTEND(), LowerZERO_EXTEND_Mask(), matchSplatAsGather(), narrowExtractedVectorSelect(), performConcatVectorsCombine(), preAssignMask(), llvm::RISCVDAGToDAGISel::PreprocessISelDAG(), llvm::RISCVTargetLowering::ReplaceNodeResults(), llvm::X86TargetLowering::ReplaceNodeResults(), llvm::RISCVTargetLowering::RISCVTargetLowering(), scaleVectorType(), splitAndLowerShuffle(), llvm::RISCVTargetLowering::splitValueIntoRegisterParts(), llvm::splitVectorType(), tryExtendDUPToExtractHigh(), and useRVVForFixedLengthVectorVT().
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Given a vector type, return the minimum number of elements it contains.
Definition at line 698 of file MachineValueType.h.
References llvm_unreachable, nxv16bf16, nxv16f16, nxv16f32, nxv16i1, nxv16i16, nxv16i32, nxv16i64, nxv16i8, nxv1bf16, nxv1f16, nxv1f32, nxv1f64, nxv1i1, nxv1i16, nxv1i32, nxv1i64, nxv1i8, nxv2bf16, nxv2f16, nxv2f32, nxv2f64, nxv2i1, nxv2i16, nxv2i32, nxv2i64, nxv2i8, nxv32bf16, nxv32f16, nxv32i1, nxv32i16, nxv32i32, nxv32i64, nxv32i8, nxv4bf16, nxv4f16, nxv4f32, nxv4f64, nxv4i1, nxv4i16, nxv4i32, nxv4i64, nxv4i8, nxv64i1, nxv64i8, nxv8bf16, nxv8f16, nxv8f32, nxv8f64, nxv8i1, nxv8i16, nxv8i32, nxv8i64, nxv8i8, SimpleTy, v1024f32, v1024i1, v1024i32, v1024i8, v128bf16, v128f16, v128f32, v128f64, v128i1, v128i16, v128i2, v128i32, v128i64, v128i8, v16bf16, v16f16, v16f32, v16f64, v16i1, v16i16, v16i32, v16i64, v16i8, v1f16, v1f32, v1f64, v1i1, v1i128, v1i16, v1i32, v1i64, v1i8, v2048f32, v2048i32, v256f16, v256f32, v256f64, v256i1, v256i16, v256i32, v256i64, v256i8, v2bf16, v2f16, v2f32, v2f64, v2i1, v2i16, v2i32, v2i64, v2i8, v32bf16, v32f16, v32f32, v32f64, v32i1, v32i16, v32i32, v32i64, v32i8, v3bf16, v3f16, v3f32, v3f64, v3i16, v3i32, v3i64, v4bf16, v4f16, v4f32, v4f64, v4i1, v4i16, v4i32, v4i64, v4i8, v512f16, v512f32, v512i1, v512i16, v512i32, v512i8, v5f32, v5i32, v64bf16, v64f16, v64f32, v64f64, v64i1, v64i16, v64i32, v64i4, v64i64, v64i8, v6f32, v6i32, v7f32, v7i32, v8bf16, v8f16, v8f32, v8f64, v8i1, v8i16, v8i32, v8i64, and v8i8.
Referenced by llvm::HexagonTargetLowering::getPreferredVectorAction(), getVectorElementCount(), getVectorNumElements(), isPow2VectorType(), and llvm::LLT::LLT().
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Definition at line 869 of file MachineValueType.h.
References getVectorMinNumElements(), isScalableVector(), and llvm::reportInvalidSizeRequest().
Referenced by llvm::AMDGPUTargetLowering::analyzeFormalArgumentsCompute(), combineAndnp(), combineBitcast(), combineConcatVectorOps(), combineCVTP2I_CVTTP2I(), combineEXTRACT_SUBVECTOR(), combineINSERT_SUBVECTOR(), combineMOVMSK(), combinePredicateReduction(), combineSetCCMOVMSK(), combineStore(), combineTargetShuffle(), combineVectorSignBitsTruncation(), combineVEXTRACT_STORE(), combineX86INT_TO_FP(), combineX86ShuffleChain(), llvm::X86TargetLowering::ComputeNumSignBitsForTargetNode(), convertShiftLeftToScale(), createPackShuffleMask(), createShuffleStride(), llvm::createSplat2ShuffleMask(), createVariablePermute(), DecodePALIGNRMask(), ExpandHorizontalBinOp(), ExtendToType(), ExtractBitFromMaskVector(), genShuffleBland(), getAVX512TruncNode(), getConstVector(), getContainerForFixedLengthVector(), getDefaultVLOps(), getFauxShuffleMask(), getGatherNode(), getHopForBuildVector(), llvm::X86TTIImpl::getInterleavedMemoryOpCostAVX512(), getMemCmpLoad(), getMOVL(), getPack(), llvm::SITargetLowering::getPreferredVectorAction(), llvm::NVPTXTargetLowering::getPreferredVectorAction(), llvm::PPCTargetLowering::getPreferredVectorAction(), llvm::X86TargetLowering::getPreferredVectorAction(), llvm::X86TTIImpl::getReplicationShuffleCost(), getShuffleHalfVectors(), getShuffleScalarElt(), getShuffleVectorZeroOrUndef(), getTargetShuffleAndZeroables(), getTargetShuffleMask(), getTargetVShiftNode(), llvm::ARMTargetLowering::getTgtMemIntrinsic(), llvm::X86TargetLowering::getTgtMemIntrinsic(), getUnderlyingExtractedFromVec(), getVectorMaskingNode(), llvm::EVT::getVectorNumElements(), getZeroVector(), group2Shuffle(), incDecVectorConstant(), insert1BitVector(), InsertBitToMaskVector(), isAddSubOrSubAdd(), IsElementEquivalent(), isHopBuildVector(), isHorizontalBinOp(), llvm::HexagonSubtarget::isHVXVectorType(), isInterleaveShuffle(), lower1BitShuffle(), lower256BitShuffle(), LowerAsSplatVectorLoad(), LowerAVXCONCAT_VECTORS(), LowerAVXExtend(), LowerBITCAST(), LowerBITREVERSE(), LowerBITREVERSE_XOP(), llvm::VETargetLowering::lowerBUILD_VECTOR(), llvm::HexagonTargetLowering::LowerBUILD_VECTOR(), lowerBUILD_VECTOR(), lowerBuildVectorAsBroadcast(), LowerBuildVectorAsInsert(), lowerBuildVectorToBitOp(), llvm::HexagonTargetLowering::LowerCONCAT_VECTORS(), LowerCONCAT_VECTORSvXi1(), LowerEXTEND_VECTOR_INREG(), LowerEXTRACT_SUBVECTOR(), LowerFunnelShift(), LowerLoad(), LowerMGATHER(), LowerMSCATTER(), LowerMUL(), LowerMULH(), LowerMULO(), LowerRotate(), LowerSCALAR_TO_VECTOR(), llvm::HexagonTargetLowering::LowerSETCC(), LowerShift(), LowerShiftByScalarImmediate(), LowerShiftByScalarVariable(), lowerShuffleAsBlend(), lowerShuffleAsBroadcast(), lowerShuffleAsByteRotateAndPermute(), lowerShuffleAsElementInsertion(), lowerShuffleAsLanePermuteAndPermute(), lowerShuffleAsRepeatedMaskAndLanePermute(), lowerShuffleAsShift(), lowerShuffleAsSpecificZeroOrAnyExtend(), lowerShuffleAsVTRUNC(), lowerShuffleAsZeroOrAnyExtend(), lowerShuffleOfExtractsAsVperm(), lowerShuffleToEXPAND(), lowerShuffleWithPERMV(), lowerShuffleWithUndefHalf(), lowerShuffleWithVPMOV(), LowerSIGN_EXTEND(), llvm::AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(), LowerSIGN_EXTEND_Mask(), lowerToAddSubOrFMAddSub(), LowerToHorizontalOp(), LowerTruncateVecI1(), lowerV8I16GeneralSingleInputShuffle(), lowerVECTOR_SHUFFLE(), LowerVectorCTLZ_AVX512CDI(), LowerVectorCTLZInRegLUT(), LowerVectorCTPOP(), LowerVectorCTPOPInRegLUT(), llvm::HexagonTargetLowering::LowerVSELECT(), LowerVSETCC(), LowervXi8MulWithUNPCK(), LowerZERO_EXTEND_Mask(), matchBinaryShuffle(), matchShuffleAsEXTRQ(), matchShuffleAsINSERTQ(), matchShuffleWithPACK(), matchShuffleWithSHUFPD(), matchShuffleWithUNPCK(), matchUnaryShuffle(), narrowExtractedVectorSelect(), performConcatVectorsCombine(), PerformVECREDUCE_ADDCombine(), performVECTOR_SHUFFLECombine(), llvm::X86TargetLowering::ReplaceNodeResults(), scalarizeVectorStore(), scaleVectorType(), setGroupSize(), llvm::X86TargetLowering::SimplifyDemandedBitsForTargetNode(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), llvm::X86TargetLowering::SimplifyMultipleUseDemandedBitsForTargetNode(), splitAndLowerShuffle(), tryExtendDUPToExtractHigh(), useRVVForFixedLengthVectorVT(), and vectorizeExtractedCast().
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Definition at line 1442 of file MachineValueType.h.
References getScalableVectorVT(), and getVectorVT().
Definition at line 1216 of file MachineValueType.h.
References bf16, f16, f32, f64, i1, i128, i16, i2, i32, i4, i64, i8, INVALID_SIMPLE_VALUE_TYPE, SimpleTy, v1024f32, v1024i1, v1024i32, v1024i8, v128bf16, v128f16, v128f32, v128f64, v128i1, v128i16, v128i2, v128i32, v128i64, v128i8, v16bf16, v16f16, v16f32, v16f64, v16i1, v16i16, v16i32, v16i64, v16i8, v1f16, v1f32, v1f64, v1i1, v1i128, v1i16, v1i32, v1i64, v1i8, v2048f32, v2048i32, v256f16, v256f32, v256f64, v256i1, v256i16, v256i32, v256i64, v256i8, v2bf16, v2f16, v2f32, v2f64, v2i1, v2i16, v2i32, v2i64, v2i8, v32bf16, v32f16, v32f32, v32f64, v32i1, v32i16, v32i32, v32i64, v32i8, v3bf16, v3f16, v3f32, v3f64, v3i16, v3i32, v3i64, v4bf16, v4f16, v4f32, v4f64, v4i1, v4i16, v4i32, v4i64, v4i8, v512f16, v512f32, v512i1, v512i16, v512i32, v512i8, v5f32, v5i32, v64bf16, v64f16, v64f32, v64f64, v64i1, v64i16, v64i32, v64i4, v64i64, v64i8, v6f32, v6i32, v7f32, v7i32, v8bf16, v8f16, v8f32, v8f64, v8i1, v8i16, v8i32, v8i64, and v8i8.
Referenced by AddCombineBUILD_VECTORToVPADDL(), canonicalizeBitSelect(), canonicalizeShuffleMaskWithHorizOp(), changeVectorElementType(), changeVectorElementTypeToInteger(), combineADDSUB_VLToVWADDSUB_VL(), combineArithReduction(), combineBitcast(), combineConcatVectorOps(), combineCVTP2I_CVTTP2I(), combineExtractWithShuffle(), combineFaddCFmul(), combineMOVMSK(), combineMUL_VLToVWMUL_VL(), combineMulToPMADDWD(), combinePredicateReduction(), combineStore(), combineTargetShuffle(), combineVectorHADDSUB(), combineX86INT_TO_FP(), combineX86ShuffleChain(), combineX86ShufflesConstants(), constructDup(), constructRetValue(), createPSADBW(), createVariablePermute(), createVPDPBUSD(), EltsFromConsecutiveLoads(), ExtractBitFromMaskVector(), llvm::X86TTIImpl::getArithmeticInstrCost(), getAVX512Node(), getAVX512TruncNode(), llvm::HvxSelector::getBoolVT(), getBuildDwordsVector(), getConstVector(), getGatherNode(), getHalfNumVectorElementsVT(), llvm::X86TTIImpl::getInterleavedMemoryOpCostAVX512(), llvm::getLegalVectorType(), llvm::VECustomDAG::getMaskBroadcast(), getMaskNode(), getMaskTypeFor(), llvm::getMVTForLLT(), getOnesVector(), llvm::HvxSelector::getPairVT(), getPermuteNode(), getPow2VectorType(), getPrefetchNode(), getPromotedVectorElementType(), getScatterNode(), llvm::ARMTargetLowering::getSetCCResultType(), llvm::HvxSelector::getSingleVT(), getTargetVShiftNode(), llvm::ARMTargetLowering::getTgtMemIntrinsic(), llvm::X86TargetLowering::getTgtMemIntrinsic(), getVectorMaskingNode(), getVectorTypeBreakdownMVT(), llvm::EVT::getVectorVT(), getVectorVT(), getVT(), getZeroVector(), llvm::HexagonTargetLowering::HexagonTargetLowering(), InsertBitToMaskVector(), is128BitUnpackShuffleMask(), llvm::HexagonSubtarget::isTypeForHVX(), llvm::SystemZVectorConstantInfo::isVectorConstantLegal(), lower1BitShuffle(), lower256BitShuffle(), LowerBITCAST(), LowerBITREVERSE(), LowerBITREVERSE_XOP(), lowerBUILD_VECTOR(), lowerBuildVectorAsBroadcast(), LowerCONCAT_VECTORS_i1(), lowerCTLZ_CTTZ_ZERO_UNDEF(), LowerCTPOP(), LowerEXTRACT_SUBVECTOR(), lowerFPToIntToFP(), lowerFROUND(), lowerFTRUNC_FCEIL_FFLOOR(), LowerFunnelShift(), LowerHorizontalByteSum(), LowerI64IntToFP_AVX512DQ(), LowerINTRINSIC_W_CHAIN(), LowerMGATHER(), LowerMLOAD(), LowerMSCATTER(), LowerMSTORE(), LowerMUL(), LowerMULH(), LowerMULO(), llvm::RISCVTargetLowering::LowerOperation(), LowerRotate(), LowerSCALAR_TO_VECTOR(), llvm::HexagonTargetLowering::LowerSETCC(), LowerShift(), LowerShiftByScalarImmediate(), LowerShiftByScalarVariable(), lowerShuffleAsBitMask(), lowerShuffleAsBlend(), lowerShuffleAsBlendOfPSHUFBs(), lowerShuffleAsBroadcast(), lowerShuffleAsByteRotate(), lowerShuffleAsByteRotateAndPermute(), lowerShuffleAsElementInsertion(), lowerShuffleAsPermuteAndUnpack(), lowerShuffleAsSpecificZeroOrAnyExtend(), lowerShuffleAsVTRUNC(), lowerShuffleToEXPAND(), lowerShuffleWithPACK(), lowerShuffleWithPSHUFB(), LowerSIGN_EXTEND_Mask(), LowerStore(), LowerTruncateVecI1(), llvm::HexagonTargetLowering::LowerUnalignedLoad(), lowerV2X128Shuffle(), lowerV4X128Shuffle(), lowerV8I16GeneralSingleInputShuffle(), lowerVECTOR_SHUFFLE(), LowerVectorCTLZ_AVX512CDI(), LowerVectorCTLZInRegLUT(), LowerVectorCTPOP(), lowerVectorIntrinsicScalars(), llvm::HexagonTargetLowering::LowerVSELECT(), LowervXi8MulWithUNPCK(), lowerX86FPLogicOp(), LowerZERO_EXTEND_Mask(), matchBinaryPermuteShuffle(), matchShuffleAsBitRotate(), matchShuffleAsShift(), matchShuffleAsVTRUNC(), matchShuffleWithPACK(), matchUnaryPermuteShuffle(), matchUnaryShuffle(), llvm::MipsTargetLowering::MipsTargetLowering(), narrowExtractedVectorSelect(), NarrowVector(), performConcatVectorsCombine(), PerformVQDMULHCombine(), llvm::X86TargetLowering::ReplaceNodeResults(), llvm::RISCVTargetLowering::RISCVTargetLowering(), scaleVectorType(), llvm::X86TargetLowering::SimplifyDemandedBitsForTargetNode(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), skipExtensionForVectorMULL(), SkipExtensionForVMULL(), splatPartsI64WithVL(), splitAndLowerShuffle(), llvm::splitVectorType(), TryCombineBaseUpdate(), tryExtendDUPToExtractHigh(), tryWidenMaskForShuffle(), vectorizeExtractedCast(), widenSubVector(), and WidenVector().
Definition at line 1436 of file MachineValueType.h.
References getScalableVectorVT(), and getVectorVT().
Return the value type corresponding to the specified type.
This returns all pointers as iPTR. If HandleUnknown is true, unknown types are returned as Other, otherwise they are invalid.
This returns all pointers as MVT::iPTR. If HandleUnknown is true, unknown types are returned as Other, otherwise they are invalid.
Definition at line 541 of file ValueTypes.cpp.
References bf16, llvm::Type::BFloatTyID, llvm::Type::DoubleTyID, f128, f16, f32, f64, f80, llvm::Type::FixedVectorTyID, llvm::Type::FloatTyID, llvm::Type::FP128TyID, getBitWidth(), llvm::VectorType::getElementCount(), llvm::VectorType::getElementType(), getIntegerVT(), llvm::Type::getTypeID(), getVectorVT(), llvm::Type::HalfTyID, llvm::Type::IntegerTyID, iPTR, isVoid, llvm_unreachable, MVT(), Other, llvm::Type::PointerTyID, llvm::Type::PPC_FP128TyID, ppcf128, llvm::Type::ScalableVectorTyID, llvm::Type::VoidTyID, llvm::Type::X86_AMXTyID, llvm::Type::X86_FP80TyID, llvm::Type::X86_MMXTyID, x86amx, and x86mmx.
Referenced by llvm::CallLowering::checkReturn(), getConvRTLibDesc(), llvm::EVT::getEVT(), llvm::X86TTIImpl::getInterleavedMemoryOpCostAVX512(), llvm::HexagonTargetLowering::getTgtMemIntrinsic(), llvm::SITargetLowering::getTgtMemIntrinsic(), llvm::AArch64TargetLowering::getTgtMemIntrinsic(), llvm::ARMTargetLowering::getTgtMemIntrinsic(), llvm::X86TargetLowering::getTgtMemIntrinsic(), llvm::AArch64CallLowering::lowerReturn(), and llvm::TargetLowering::ParseConstraints().
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Definition at line 1490 of file MachineValueType.h.
References llvm::enum_seq_inclusive(), FIRST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE, llvm::force_iteration_on_noniterable_enum, and LAST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE.
Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering(), llvm::AMDGPUTargetLowering::AMDGPUTargetLowering(), llvm::ARMTargetLowering::ARMTargetLowering(), llvm::RISCVTargetLowering::RISCVTargetLowering(), llvm::SparcTargetLowering::SparcTargetLowering(), llvm::SystemZTargetLowering::SystemZTargetLowering(), and llvm::WebAssemblyTargetLowering::WebAssemblyTargetLowering().
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Definition at line 1502 of file MachineValueType.h.
References llvm::enum_seq_inclusive(), FIRST_INTEGER_SCALABLE_VECTOR_VALUETYPE, llvm::force_iteration_on_noniterable_enum, and LAST_INTEGER_SCALABLE_VECTOR_VALUETYPE.
Referenced by llvm::RISCVTargetLowering::RISCVTargetLowering().
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Definition at line 1461 of file MachineValueType.h.
References llvm::enum_seq_inclusive(), FIRST_INTEGER_VALUETYPE, llvm::force_iteration_on_noniterable_enum, and LAST_INTEGER_VALUETYPE.
Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering(), llvm::AMDGPUTargetLowering::AMDGPUTargetLowering(), llvm::ARMTargetLowering::ARMTargetLowering(), llvm::AVRTargetLowering::AVRTargetLowering(), llvm::BPFTargetLowering::BPFTargetLowering(), findMemType(), llvm::HexagonTargetLowering::HexagonTargetLowering(), llvm::LanaiTargetLowering::LanaiTargetLowering(), llvm::M68kTargetLowering::M68kTargetLowering(), llvm::MipsTargetLowering::MipsTargetLowering(), llvm::MSP430TargetLowering::MSP430TargetLowering(), llvm::NVPTXTargetLowering::NVPTXTargetLowering(), PerformTruncatingStoreCombine(), llvm::PPCTargetLowering::PPCTargetLowering(), llvm::R600TargetLowering::R600TargetLowering(), llvm::SparcTargetLowering::SparcTargetLowering(), llvm::SystemZTargetLowering::SystemZTargetLowering(), llvm::WebAssemblyTargetLowering::WebAssemblyTargetLowering(), llvm::X86TargetLowering::X86TargetLowering(), and llvm::XCoreTargetLowering::XCoreTargetLowering().
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Return true if this is a 128-bit vector type.
Definition at line 415 of file MachineValueType.h.
References SimpleTy, v128i1, v16i8, v1i128, v2f64, v2i64, v4f32, v4i32, v8bf16, v8f16, and v8i16.
Referenced by CC_AArch64_Custom_Block(), llvm::CC_XPLINK64_Shadow_Reg(), combineAndNotIntoANDNP(), combineCVTP2I_CVTTP2I(), combineEXTRACT_SUBVECTOR(), combineSetCCMOVMSK(), combineX86INT_TO_FP(), combineX86ShuffleChain(), llvm::X86TTIImpl::getCmpSelInstrCost(), llvm::X86TTIImpl::getTypeBasedIntrinsicInstrCost(), getZeroVector(), llvm::EVT::is128BitVector(), isHorizontalBinOp(), LowerBITREVERSE_XOP(), lowerBuildVectorAsBroadcast(), LowerBuildVectorv4x32(), LowerEXTEND_VECTOR_INREG(), LowerEXTRACT_VECTOR_ELT_SSE4(), LowerRotate(), LowerSCALAR_TO_VECTOR(), lowerShuffleAsBitRotate(), lowerShuffleAsByteRotate(), lowerShuffleAsByteRotateAndPermute(), lowerShuffleAsByteShiftMask(), lowerShuffleAsElementInsertion(), lowerShuffleAsPermuteAndUnpack(), lowerShuffleAsSpecificZeroOrAnyExtend(), lowerShuffleAsVALIGN(), lowerShuffleAsVTRUNC(), lowerShuffleOfExtractsAsVperm(), lowerShuffleWithPSHUFB(), lowerShuffleWithUndefHalf(), LowerTruncateVecI1(), lowerVECTOR_SHUFFLE(), LowerVectorCTPOP(), LowerVSETCC(), matchBinaryPermuteShuffle(), matchBinaryShuffle(), matchShuffleAsInsertPS(), matchUnaryPermuteShuffle(), matchUnaryShuffle(), narrowExtractedVectorSelect(), performAddSubLongCombine(), performVECTOR_SHUFFLECombine(), scalarizeVectorStore(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), supportedVectorShiftWithImm(), and supportedVectorVarShift().
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Return true if this is a 16-bit vector type.
Definition at line 392 of file MachineValueType.h.
References SimpleTy, v16i1, v1f16, v1i16, and v2i8.
Referenced by llvm::EVT::is16BitVector().
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Return true if this is a 256-bit vector type.
Definition at line 424 of file MachineValueType.h.
References SimpleTy, v128i2, v16bf16, v16f16, v16i16, v256i1, v32i8, v4f64, v4i64, v64i4, v8f32, and v8i32.
Referenced by CC_X86_VectorCallGetSSEs(), combineAndNotIntoANDNP(), combineConcatVectorOps(), combineEXTRACT_SUBVECTOR(), combineSetCCMOVMSK(), combineVectorSignBitsTruncation(), combineX86ShuffleChain(), ExpandHorizontalBinOp(), getHopForBuildVector(), llvm::X86TTIImpl::getTypeBasedIntrinsicInstrCost(), getZeroVector(), llvm::EVT::is256BitVector(), isHopBuildVector(), isHorizontalBinOp(), LowerABS(), LowerADDSAT_SUBSAT(), LowerAVG(), LowerAVXCONCAT_VECTORS(), LowerBITREVERSE_XOP(), lowerBuildVectorAsBroadcast(), LowerCONCAT_VECTORS(), LowerEXTEND_VECTOR_INREG(), LowerFunnelShift(), LowerMINMAX(), LowerMUL(), LowerMULH(), LowerRotate(), LowerShift(), lowerShuffleAsBroadcast(), lowerShuffleAsByteRotateAndPermute(), lowerShuffleAsLanePermuteAndShuffle(), lowerShuffleAsRepeatedMaskAndLanePermute(), lowerShuffleAsVALIGN(), lowerShuffleAsVTRUNC(), lowerShuffleOfExtractsAsVperm(), lowerShuffleWithPSHUFB(), lowerShuffleWithUndefHalf(), LowerStore(), LowerToHorizontalOp(), LowerTruncateVecI1(), lowerVECTOR_SHUFFLE(), LowerVectorCTLZ(), LowerVectorCTLZ_AVX512CDI(), LowerVectorCTPOP(), LowerVSETCC(), matchBinaryPermuteShuffle(), matchBinaryShuffle(), matchUnaryPermuteShuffle(), matchUnaryShuffle(), narrowExtractedVectorSelect(), narrowShuffle(), llvm::X86TargetLowering::SimplifyDemandedBitsForTargetNode(), supportedVectorShiftWithImm(), and supportedVectorVarShift().
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Return true if this is a 32-bit vector type.
Definition at line 398 of file MachineValueType.h.
References SimpleTy, v1f32, v1i32, v2bf16, v2f16, v2i16, v32i1, and v4i8.
Referenced by CC_AArch64_Custom_Block(), llvm::EVT::is32BitVector(), and LowerStore().
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Return true if this is a 512-bit vector type.
Definition at line 434 of file MachineValueType.h.
References SimpleTy, v16f32, v16i32, v32bf16, v32f16, v32i16, v512i1, v64i8, v8f64, and v8i64.
Referenced by CC_X86_VectorCallGetSSEs(), combineAndNotIntoANDNP(), combineConcatVectorOps(), combineShuffleToAddSubOrFMAddSub(), combineVectorSignBitsTruncation(), combineX86ShuffleChain(), getAVX512Node(), getAVX512TruncNode(), llvm::X86TargetLowering::getSetCCResultType(), llvm::X86TTIImpl::getTypeBasedIntrinsicInstrCost(), getZeroVector(), llvm::EVT::is512BitVector(), LowerAVXCONCAT_VECTORS(), LowerBITREVERSE(), lowerBuildVectorAsBroadcast(), LowerCONCAT_VECTORS(), LowerEXTEND_VECTOR_INREG(), LowerFunnelShift(), LowerMGATHER(), LowerMLOAD(), LowerMSCATTER(), LowerMSTORE(), LowerRotate(), LowerShift(), LowerShiftByScalarImmediate(), lowerShuffleAsBroadcast(), lowerShuffleAsByteRotate(), lowerShuffleAsByteRotateAndPermute(), lowerShuffleWithPERMV(), lowerShuffleWithPSHUFB(), lowerShuffleWithUndefHalf(), LowerSIGN_EXTEND_Mask(), lowerToAddSubOrFMAddSub(), lowerV4X128Shuffle(), lowerVECTOR_SHUFFLE(), LowerVectorCTLZ(), LowerVectorCTLZ_AVX512CDI(), LowerVectorCTPOP(), LowerVSETCC(), LowerZERO_EXTEND_Mask(), matchBinaryPermuteShuffle(), matchBinaryShuffle(), matchShuffleAsVTRUNC(), matchUnaryPermuteShuffle(), matchUnaryShuffle(), narrowExtractedVectorSelect(), narrowShuffle(), supportedVectorShiftWithImm(), supportedVectorVarShift(), and useVPTERNLOG().
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Return true if this is a 64-bit vector type.
Definition at line 406 of file MachineValueType.h.
References SimpleTy, v1f64, v1i64, v2f32, v2i32, v4bf16, v4f16, v4i16, v64i1, and v8i8.
Referenced by CC_AArch64_Custom_Block(), llvm::EVT::is64BitVector(), LowerStore(), and tryExtendDUPToExtractHigh().
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Returns true if the number of bits for the type is a multiple of an 8-bit byte.
Definition at line 1124 of file MachineValueType.h.
References getSizeInBits(), and llvm::LinearPolySize< LeafTy >::isKnownMultipleOf().
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Definition at line 386 of file MachineValueType.h.
References FIRST_FIXEDLEN_VECTOR_VALUETYPE, LAST_FIXEDLEN_VECTOR_VALUETYPE, and SimpleTy.
Referenced by CC_RISCV(), CC_RISCV_FastCC(), convertLocVTToValVT(), convertValVTToLocVT(), getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::EVT::isFixedLengthVector(), lowerBUILD_VECTOR(), llvm::RISCVTargetLowering::LowerOperation(), matchSplatAsGather(), llvm::RISCVTargetLowering::ReplaceNodeResults(), and useRVVForFixedLengthVectorVT().
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Return true if this is a FP or a vector FP type.
Definition at line 348 of file MachineValueType.h.
References FIRST_FP_FIXEDLEN_VECTOR_VALUETYPE, FIRST_FP_SCALABLE_VECTOR_VALUETYPE, FIRST_FP_VALUETYPE, LAST_FP_FIXEDLEN_VECTOR_VALUETYPE, LAST_FP_SCALABLE_VECTOR_VALUETYPE, LAST_FP_VALUETYPE, and SimpleTy.
Referenced by llvm::AMDGPUTargetLowering::analyzeFormalArgumentsCompute(), CC_MipsO32(), CC_RISCV(), CC_X86_32_VectorCall(), CC_X86_64_VectorCall(), combineConcatVectorOps(), combineTargetShuffle(), combineX86ShuffleChain(), combineX86ShufflesConstants(), EltsFromConsecutiveLoads(), getConstantVector(), getCopyFromParts(), getCopyToParts(), getTargetShuffleAndZeroables(), llvm::TargetLoweringBase::getTypeToPromoteTo(), getVCmpInst(), getZeroVector(), isAddSubOrSubAdd(), llvm::EVT::isFloatingPoint(), isHorizontalBinOp(), lowerBUILD_VECTOR(), LowerFABSorFNEG(), LowerFCOPYSIGN(), lowerScalarSplat(), lowerShuffleAsBroadcast(), lowerShuffleAsElementInsertion(), lowerShuffleAsLanePermuteAndShuffle(), lowerShuffleAsPermuteAndUnpack(), lowerVECTOR_SHUFFLE(), LowerVSETCC(), and performScatterStoreCombine().
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Return true if this is an integer or a vector integer type.
Definition at line 358 of file MachineValueType.h.
References FIRST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE, FIRST_INTEGER_SCALABLE_VECTOR_VALUETYPE, FIRST_INTEGER_VALUETYPE, LAST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE, LAST_INTEGER_SCALABLE_VECTOR_VALUETYPE, LAST_INTEGER_VALUETYPE, and SimpleTy.
Referenced by llvm::AMDGPUTargetLowering::analyzeFormalArgumentsCompute(), convertLocVTToValVT(), convertValVTToLocVT(), llvm::TargetLowering::findOptimalMemOpLowering(), getCopyFromParts(), llvm::RegsForValue::getCopyFromRegs(), getCopyToParts(), getRegistersForValue(), llvm::X86TTIImpl::getScalarizationOverhead(), getShuffleScalarElt(), llvm::TargetLoweringBase::getTypeToPromoteTo(), llvm::EVT::isInteger(), isValueTypeInRegForCC(), llvm::TargetLowering::LegalizeSetCCCondCode(), lower256BitShuffle(), LowerABS(), llvm::X86TargetLowering::LowerAsmOutputForConstraint(), lowerBUILD_VECTOR(), LowerLoad(), llvm::RISCVTargetLowering::LowerOperation(), LowerSCALAR_TO_VECTOR(), lowerShuffleAsBitBlend(), lowerShuffleAsBroadcast(), lowerShuffleAsTruncBroadcast(), LowerStore(), lowerVECTOR_SHUFFLE(), matchUnaryShuffle(), llvm::TargetLowering::ParseConstraints(), and llvm::RISCVDAGToDAGISel::PreprocessISelDAG().
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Returns true if the given vector is a power of 2.
Definition at line 506 of file MachineValueType.h.
References getVectorMinNumElements().
Referenced by getPow2VectorType(), llvm::SITargetLowering::getPreferredVectorAction(), llvm::TargetLoweringBase::getPreferredVectorAction(), and useRVVForFixedLengthVectorVT().
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Return true if this is a vector value type where the runtime length is machine dependent.
Definition at line 381 of file MachineValueType.h.
References FIRST_SCALABLE_VECTOR_VALUETYPE, LAST_SCALABLE_VECTOR_VALUETYPE, and SimpleTy.
Referenced by bitsGE(), bitsGT(), bitsLE(), bitsLT(), CC_AArch64_Custom_Block(), CC_RISCV(), llvm::TargetLoweringBase::computeRegisterProperties(), convertLocVTToValVT(), finishStackBlock(), getDefaultScalableVLOps(), getDefaultVLOps(), llvm::RISCVTargetLowering::getLMUL(), llvm::HexagonTargetLowering::getPreferredVectorAction(), llvm::SITargetLowering::getPreferredVectorAction(), llvm::NVPTXTargetLowering::getPreferredVectorAction(), llvm::PPCTargetLowering::getPreferredVectorAction(), llvm::X86TargetLowering::getPreferredVectorAction(), getVectorElementCount(), getVectorNumElements(), getVectorTypeBreakdownMVT(), llvm::HexagonSubtarget::isHVXVectorType(), llvm::EVT::isScalableVector(), llvm::RISCVTargetLowering::joinRegisterPartsIntoValue(), llvm::RISCVTargetLowering::LowerFormalArguments(), llvm::RISCVDAGToDAGISel::PreprocessISelDAG(), and llvm::RISCVTargetLowering::splitValueIntoRegisterParts().
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Return true if this is an integer, not including vectors.
Definition at line 368 of file MachineValueType.h.
References FIRST_INTEGER_VALUETYPE, LAST_INTEGER_VALUETYPE, and SimpleTy.
Referenced by CC_RISCV(), hasBZHI(), llvm::EVT::isScalarInteger(), LowerBITCAST(), llvm::HexagonTargetLowering::LowerSETCC(), lowerVectorIntrinsicScalars(), llvm::HexagonTargetLowering::LowerVSELECT(), llvm::X86TargetLowering::SimplifyDemandedBitsForTargetNode(), and truncateScalarIntegerArg().
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Return true if this is a valid simple valuetype.
Definition at line 342 of file MachineValueType.h.
References FIRST_VALUETYPE, LAST_VALUETYPE, and SimpleTy.
Referenced by llvm::TargetLoweringBase::initActions(), llvm::HexagonSubtarget::isTypeForHVX(), llvm::LLT::LLT(), llvm::MipsTargetLowering::MipsTargetLowering(), llvm::TargetLoweringBase::setCondCodeAction(), llvm::TargetLoweringBase::setLoadExtAction(), and llvm::TargetLoweringBase::setTruncStoreAction().
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Return true if this is a vector value type.
Definition at line 374 of file MachineValueType.h.
References FIRST_VECTOR_VALUETYPE, LAST_VECTOR_VALUETYPE, and SimpleTy.
Referenced by llvm::PPCTargetLowering::allowsMisalignedMemoryAccesses(), llvm::AMDGPUTargetLowering::analyzeFormalArgumentsCompute(), canonicalizeBitSelect(), CC_RISCV(), CC_RISCV_FastCC(), CC_X86_32_VectorCall(), CC_X86_64_VectorCall(), changeTypeToInteger(), combineAndnp(), combineX86ShuffleChain(), combineX86ShufflesRecursively(), constructRetValue(), convertLocVTToValVT(), convertValVTToLocVT(), getAVX512Node(), llvm::X86TTIImpl::getCmpSelInstrCost(), getCopyFromParts(), getCopyToPartsVector(), llvm::X86TTIImpl::getInterleavedMemoryOpCost(), llvm::getLLTForMVT(), getMemCmpLoad(), llvm::RISCVTargetLowering::getRegForInlineAsmConstraint(), llvm::PPCTargetLowering::getRegForInlineAsmConstraint(), llvm::X86TargetLowering::getRegForInlineAsmConstraint(), llvm::X86TTIImpl::getReplicationShuffleCost(), getScalarType(), getScalarValueForVectorElement(), llvm::X86TargetLowering::getSetCCResultType(), llvm::CallLowering::ValueHandler::getStackValueStoreType(), getTargetVShiftNode(), llvm::X86TTIImpl::getTypeBasedIntrinsicInstrCost(), llvm::HexagonSubtarget::isHVXElementType(), llvm::HexagonSubtarget::isHVXVectorType(), isValueTypeInRegForCC(), llvm::EVT::isVector(), llvm::LLT::LLT(), LowerADDSAT_SUBSAT(), llvm::X86TargetLowering::LowerAsmOutputForConstraint(), LowerAVXExtend(), LowerBITCAST(), LowerBITREVERSE_XOP(), llvm::RISCVTargetLowering::LowerCall(), LowerCTLZ(), LowerCTTZ(), LowerFABSorFNEG(), LowerFCOPYSIGN(), llvm::RISCVTargetLowering::LowerFormalArguments(), lowerFPToIntToFP(), lowerFROUND(), lowerFTRUNC_FCEIL_FFLOOR(), LowerFunnelShift(), LowerLoad(), LowerMULO(), llvm::RISCVTargetLowering::LowerOperation(), llvm::AArch64CallLowering::lowerReturn(), LowerRotate(), llvm::HexagonTargetLowering::LowerSETCC(), LowerShift(), lowerShuffleAsTruncBroadcast(), LowerSIGN_EXTEND(), llvm::AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(), lowerX86FPLogicOp(), performConcatVectorsCombine(), preAssignMask(), promoteXINT_TO_FP(), llvm::X86TargetLowering::SimplifyDemandedBitsForTargetNode(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), llvm::splitVectorType(), and VerifyVectorType().
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Return true if we know at compile time this has more than or the same bits as VT.
Definition at line 1133 of file MachineValueType.h.
References getSizeInBits(), and llvm::LinearPolySize< TypeSize >::isKnownGE().
Referenced by bitsGE().
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Return true if we know at compile time this has more bits than VT.
Definition at line 1127 of file MachineValueType.h.
References getSizeInBits(), and llvm::LinearPolySize< TypeSize >::isKnownGT().
Referenced by bitsGT().
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Return true if we know at compile time this has fewer than or the same bits as VT.
Definition at line 1144 of file MachineValueType.h.
References getSizeInBits(), and llvm::LinearPolySize< TypeSize >::isKnownLE().
Referenced by bitsLE().
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Return true if we know at compile time this has fewer bits than VT.
Definition at line 1138 of file MachineValueType.h.
References getSizeInBits(), and llvm::LinearPolySize< TypeSize >::isKnownLT().
Referenced by bitsLT().
Definition at line 337 of file MachineValueType.h.
Definition at line 335 of file MachineValueType.h.
Definition at line 339 of file MachineValueType.h.
Definition at line 336 of file MachineValueType.h.
Definition at line 334 of file MachineValueType.h.
Definition at line 338 of file MachineValueType.h.
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Definition at line 1484 of file MachineValueType.h.
References llvm::enum_seq_inclusive(), FIRST_SCALABLE_VECTOR_VALUETYPE, llvm::force_iteration_on_noniterable_enum, and LAST_SCALABLE_VECTOR_VALUETYPE.
Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering().
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Definition at line 1472 of file MachineValueType.h.
References llvm::enum_seq_inclusive(), FIRST_VECTOR_VALUETYPE, llvm::force_iteration_on_noniterable_enum, and LAST_VECTOR_VALUETYPE.
Referenced by findMemType().
SimpleValueType llvm::MVT::SimpleTy = INVALID_SIMPLE_VALUE_TYPE |
Definition at line 329 of file MachineValueType.h.
Referenced by AddCombineBUILD_VECTORToVPADDL(), llvm::TargetLoweringBase::AddPromotedToType(), llvm::TargetLoweringBase::addRegisterClass(), llvm::MipsSETargetLowering::allowsMisalignedMemoryAccesses(), llvm::ARMTargetLowering::allowsMisalignedMemoryAccesses(), llvm::AVRDAGToDAGISel::select< ISD::LOAD >(), CC_AArch64_Custom_Block(), CC_AIX(), CC_ARM_AAPCS_Custom_Aggregate(), llvm::CC_XPLINK64_Shadow_Stack(), changeVectorElementType(), changeVectorElementTypeToInteger(), combineBitcastvxi1(), createVariablePermute(), llvm::SITargetLowering::denormalsEnabledForType(), llvm::SelectionDAG::EVTToAPFloatSemantics(), llvm::TargetLowering::expandBSWAP(), llvm::TargetLowering::findOptimalMemOpLowering(), llvm::ARMTargetLowering::findRepresentativeClass(), llvm::X86TargetLowering::findRepresentativeClass(), llvm::TargetLoweringBase::findRepresentativeClass(), foldVectorXorShiftIntoCmp(), llvm::R600RegisterInfo::getCFGStructurizerRegClass(), llvm::TargetLoweringBase::getCondCodeAction(), getContainerForFixedLengthVector(), llvm::EVT::getEVTString(), getExtensionTo64Bits(), getImplicitScaleFactor(), llvm::TargetLoweringBase::getLoadExtAction(), llvm::TargetLoweringBase::getNumRegisters(), llvm::TargetLoweringBase::getOperationAction(), llvm::RTLIB::getOUTLINE_ATOMIC(), getPackedSVEVectorVT(), getPredicateForFixedLengthVector(), llvm::EVT::getRawBits(), llvm::TargetLoweringBase::getRegClassFor(), llvm::M68kTargetLowering::getRegForInlineAsmConstraint(), llvm::HexagonTargetLowering::getRegForInlineAsmConstraint(), llvm::SITargetLowering::getRegForInlineAsmConstraint(), llvm::RISCVTargetLowering::getRegForInlineAsmConstraint(), llvm::X86TargetLowering::getRegForInlineAsmConstraint(), llvm::TargetLoweringBase::getRegisterType(), llvm::TargetLoweringBase::getRepRegClassCostFor(), llvm::TargetLoweringBase::getRepRegClassFor(), getScalableVectorVT(), llvm::TargetLoweringBase::getSetCCResultType(), getSizeInBits(), getSVEContainerType(), llvm::TargetLoweringBase::getTruncStoreAction(), llvm::TargetLoweringBase::ValueTypeActionImpl::getTypeAction(), llvm::EVT::getTypeForEVT(), llvm::TargetLoweringBase::getTypeToPromoteTo(), llvm::SelectionDAG::getValueType(), getVectorElementType(), getVectorMinNumElements(), getVectorTyFromPredicateVector(), getVectorVT(), getVPTESTMOpc(), is1024BitVector(), is128BitVector(), is16BitVector(), is2048BitVector(), is256BitVector(), is32Bit(), is32BitVector(), is512BitVector(), is64BitVector(), isConstantSplatVectorMaskForType(), isFixedLengthVector(), isFloatingPoint(), llvm::SITargetLowering::isFMAFasterThanFMulAndFAdd(), llvm::SystemZTargetLowering::isFMAFasterThanFMulAndFAdd(), llvm::RISCVTargetLowering::isFMAFasterThanFMulAndFAdd(), llvm::AArch64TargetLowering::isFMAFasterThanFMulAndFAdd(), llvm::X86TargetLowering::isFMAFasterThanFMulAndFAdd(), llvm::ARMTargetLowering::isFNegFree(), llvm::PPCTargetLowering::isFPImmLegal(), isInteger(), isLegalAddressImmediate(), llvm::ARMTargetLowering::isLegalAddressingMode(), isLegalT1AddressImmediate(), isLegalT2AddressImmediate(), llvm::ARMTargetLowering::isLegalT2ScaledAddressingMode(), isOverloaded(), IsPTXVectorType(), isScalableVector(), isScalarInteger(), llvm::EVT::isSimple(), llvm::TargetLoweringBase::isTypeLegal(), isValid(), llvm::HexagonInstrInfo::isValidAutoIncImm(), isValidIndexedLoad(), isVector(), llvm::XCoreTargetLowering::isZExtFree(), llvm::ARMTargetLowering::isZExtFree(), llvm::X86TargetLowering::isZExtFree(), lower128BitShuffle(), lower1BitShuffle(), lower256BitShuffle(), lower512BitShuffle(), LowerADDSUBSAT(), llvm::SystemZTargetLowering::LowerFormalArguments(), lowerRegToMasks(), lowerShuffleAsBlend(), lowerUINT_TO_FP_vec(), llvm::EVT::operator!=(), operator!=(), llvm::EVT::compareRawBits::operator()(), operator<(), operator<=(), operator==(), operator>(), operator>=(), performUzpCombine(), performVSelectCombine(), ReplaceINTRINSIC_W_CHAIN(), ReplaceLoadVector(), llvm::AVRDAGToDAGISel::selectIndexedLoad(), llvm::HexagonDAGToDAGISel::SelectIndexedLoad(), llvm::AVRDAGToDAGISel::selectIndexedProgMemLoad(), llvm::HexagonDAGToDAGISel::SelectIndexedStore(), llvm::TargetLoweringBase::setCondCodeAction(), llvm::TargetLoweringBase::setLoadExtAction(), llvm::TargetLoweringBase::setOperationAction(), llvm::TargetLoweringBase::setTruncStoreAction(), llvm::TargetLoweringBase::ValueTypeActionImpl::setTypeAction(), llvm::RISCVTargetLowering::shouldConvertFpToSat(), llvm::ARMTargetLowering::shouldConvertFpToSat(), llvm::X86InstrInfo::shouldScheduleLoadsNear(), unpackFromRegLoc(), usePartialVectorLoads(), useRVVForFixedLengthVectorVT(), X86ChooseCmpImmediateOpcode(), and X86ChooseCmpOpcode().