LLVM  15.0.0git
Public Types | Public Member Functions | Protected Types | Protected Attributes | List of all members
llvm::ARMSubtarget Class Reference

#include "Target/ARM/ARMSubtarget.h"

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Public Types

enum  ARMLdStMultipleTiming { DoubleIssue, DoubleIssueCheckUnalignedAccess, SingleIssue, SingleIssuePlusExtras }
 What kind of timing do load multiple/store multiple instructions have. More...
 

Public Member Functions

 ARMSubtarget (const Triple &TT, const std::string &CPU, const std::string &FS, const ARMBaseTargetMachine &TM, bool IsLittle, bool MinSize=false)
 This constructor initializes the data members to match that of the specified triple. More...
 
unsigned getMaxInlineSizeThreshold () const
 getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size that still makes it profitable to inline the call. More...
 
unsigned getMaxMemcpyTPInlineSizeThreshold () const
 getMaxMemcpyTPInlineSizeThreshold - Returns the maximum size that still makes it profitable to inline a llvm.memcpy as a Tail Predicated loop. More...
 
void ParseSubtargetFeatures (StringRef CPU, StringRef TuneCPU, StringRef FS)
 ParseSubtargetFeatures - Parses features string setting specified subtarget options. More...
 
ARMSubtargetinitializeSubtargetDependencies (StringRef CPU, StringRef FS)
 initializeSubtargetDependencies - Initializes using a CPU and feature string so that we can use initializer lists for subtarget initialization. More...
 
const ARMSelectionDAGInfogetSelectionDAGInfo () const override
 
const ARMBaseInstrInfogetInstrInfo () const override
 
const ARMTargetLoweringgetTargetLowering () const override
 
const ARMFrameLoweringgetFrameLowering () const override
 
const ARMBaseRegisterInfogetRegisterInfo () const override
 
const CallLoweringgetCallLowering () const override
 
InstructionSelectorgetInstructionSelector () const override
 
const LegalizerInfogetLegalizerInfo () const override
 
const RegisterBankInfogetRegBankInfo () const override
 
void computeIssueWidth ()
 
bool hasARMOps () const
 
bool useNEONForSinglePrecisionFP () const
 
bool hasVFP2Base () const
 
bool hasVFP3Base () const
 
bool hasVFP4Base () const
 
bool hasFPARMv8Base () const
 
bool hasAnyDataBarrier () const
 
bool useMulOps () const
 
bool useFPVMLx () const
 
bool useFPVFMx () const
 
bool useFPVFMx16 () const
 
bool useFPVFMx64 () const
 
bool useSjLjEH () const
 
bool hasBaseDSP () const
 
bool hasFusion () const
 Return true if the CPU supports any kind of instruction fusion. More...
 
const TriplegetTargetTriple () const
 
bool isTargetDarwin () const
 
bool isTargetIOS () const
 
bool isTargetWatchOS () const
 
bool isTargetWatchABI () const
 
bool isTargetDriverKit () const
 
bool isTargetLinux () const
 
bool isTargetNaCl () const
 
bool isTargetNetBSD () const
 
bool isTargetWindows () const
 
bool isTargetCOFF () const
 
bool isTargetELF () const
 
bool isTargetMachO () const
 
bool isTargetAEABI () const
 
bool isTargetGNUAEABI () const
 
bool isTargetMuslAEABI () const
 
bool isTargetEHABICompatible () const
 
bool isTargetHardFloat () const
 
bool isTargetAndroid () const
 
bool isXRaySupported () const override
 
bool isAPCS_ABI () const
 
bool isAAPCS_ABI () const
 
bool isAAPCS16_ABI () const
 
bool isROPI () const
 
bool isRWPI () const
 
bool useMachineScheduler () const
 
bool useMachinePipeliner () const
 
bool hasMinSize () const
 
bool isThumb1Only () const
 
bool isThumb2 () const
 
bool isMClass () const
 
bool isRClass () const
 
bool isAClass () const
 
bool isR9Reserved () const
 
MCPhysReg getFramePointerReg () const
 
bool splitFramePushPop (const MachineFunction &MF) const
 Returns true if the frame setup is split into two separate pushes (first r0-r7,lr then r8-r11), principally so that the frame pointer is adjacent to lr. More...
 
bool useStride4VFPs () const
 
bool useMovt () const
 
bool supportsTailCall () const
 
bool allowsUnalignedMem () const
 
bool restrictIT () const
 
const std::string & getCPUString () const
 
bool isLittle () const
 
unsigned getMispredictionPenalty () const
 
bool enableMachineScheduler () const override
 Returns true if machine scheduler should be enabled. More...
 
bool enableMachinePipeliner () const override
 Returns true if machine pipeliner should be enabled. More...
 
bool useDFAforSMS () const override
 
bool enablePostRAScheduler () const override
 True for some subtargets at > -O0. More...
 
bool enablePostRAMachineScheduler () const override
 True for some subtargets at > -O0. More...
 
bool enableSubRegLiveness () const override
 Check whether this subtarget wants to use subregister liveness. More...
 
bool useAA () const override
 Enable use of alias analysis during code generation (during MI scheduling, DAGCombine, etc.). More...
 
const InstrItineraryDatagetInstrItineraryData () const override
 getInstrItins - Return the instruction itineraries based on subtarget selection. More...
 
Align getStackAlignment () const
 getStackAlignment - Returns the minimum alignment known to hold of the stack frame on entry to the function and which must be maintained by every function for this subtarget. More...
 
unsigned getMaxInterleaveFactor () const
 
unsigned getPartialUpdateClearance () const
 
ARMLdStMultipleTiming getLdStMultipleTiming () const
 
int getPreISelOperandLatencyAdjustment () const
 
bool isGVIndirectSymbol (const GlobalValue *GV) const
 True if the GV will be accessed via an indirect symbol. More...
 
bool isGVInGOT (const GlobalValue *GV) const
 Returns the constant pool modifier needed to access the GV. More...
 
bool useFastISel () const
 True if fast-isel is used. More...
 
unsigned getReturnOpcode () const
 Returns the correct return opcode for the current feature set. More...
 
bool allowPositionIndependentMovt () const
 Allow movt+movw for PIC global address calculation. More...
 
unsigned getPrefLoopLogAlignment () const
 
unsigned getMVEVectorCostFactor (TargetTransformInfo::TargetCostKind CostKind) const
 
bool ignoreCSRForAllocationOrder (const MachineFunction &MF, unsigned PhysReg) const override
 
unsigned getGPRAllocationOrder (const MachineFunction &MF) const
 
bool isCortexA5 () const
 
bool isCortexA7 () const
 
bool isCortexA8 () const
 
bool isCortexA9 () const
 
bool isCortexA15 () const
 
bool isSwift () const
 
bool isCortexM3 () const
 
bool isCortexM7 () const
 
bool isLikeA9 () const
 
bool isCortexR5 () const
 
bool isKrait () const
 

Protected Types

enum  ARMProcFamilyEnum {
  Others, CortexA12, CortexA15, CortexA17,
  CortexA32, CortexA35, CortexA5, CortexA53,
  CortexA55, CortexA57, CortexA7, CortexA72,
  CortexA73, CortexA75, CortexA76, CortexA77,
  CortexA78, CortexA78C, CortexA710, CortexA8,
  CortexA9, CortexM3, CortexM7, CortexR4,
  CortexR4F, CortexR5, CortexR52, CortexR7,
  CortexX1, CortexX1C, Exynos, Krait,
  Kryo, NeoverseN1, NeoverseN2, NeoverseV1,
  Swift
}
 
enum  ARMProcClassEnum { None, AClass, MClass, RClass }
 
enum  ARMArchEnum {
  ARMv2, ARMv2a, ARMv3, ARMv3m,
  ARMv4, ARMv4t, ARMv5, ARMv5t,
  ARMv5te, ARMv5tej, ARMv6, ARMv6k,
  ARMv6kz, ARMv6m, ARMv6sm, ARMv6t2,
  ARMv7a, ARMv7em, ARMv7m, ARMv7r,
  ARMv7ve, ARMv81a, ARMv82a, ARMv83a,
  ARMv84a, ARMv85a, ARMv86a, ARMv87a,
  ARMv88a, ARMv8a, ARMv8mBaseline, ARMv8mMainline,
  ARMv8r, ARMv81mMainline, ARMv9a, ARMv91a,
  ARMv92a, ARMv93a
}
 

Protected Attributes

ARMProcFamilyEnum ARMProcFamily = Others
 ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others. More...
 
ARMProcClassEnum ARMProcClass = None
 ARMProcClass - ARM processor class: None, AClass, RClass or MClass. More...
 
ARMArchEnum ARMArch = ARMv4t
 ARMArch - ARM architecture. More...
 
bool UseMulOps = false
 UseMulOps - True if non-microcoded fused integer multiply-add and multiply-subtract instructions should be used. More...
 
bool SupportsTailCall = false
 SupportsTailCall - True if the OS supports tail call. More...
 
bool RestrictIT = false
 RestrictIT - If true, the subtarget disallows generation of complex IT blocks. More...
 
bool UseSjLjEH = false
 UseSjLjEH - If true, the target uses SjLj exception handling (e.g. iOS). More...
 
Align stackAlignment = Align(4)
 stackAlignment - The minimum alignment known to hold of the stack frame on entry to the function and which must be maintained by every function. More...
 
std::string CPUString
 CPUString - String name of used CPU. More...
 
unsigned MaxInterleaveFactor = 1
 
unsigned PartialUpdateClearance = 0
 Clearance before partial register updates (in number of instructions) More...
 
ARMLdStMultipleTiming LdStMultipleTiming = SingleIssue
 What kind of timing do load multiple/store multiple have (double issue, single issue etc). More...
 
int PreISelOperandLatencyAdjustment = 2
 The adjustment that we need to apply to get the operand latency from the operand cycle returned by the itinerary data for pre-ISel operands. More...
 
unsigned PrefLoopLogAlignment = 0
 What alignment is preferred for loop bodies, in log2(bytes). More...
 
unsigned MVEVectorCostFactor = 0
 The cost factor for MVE instructions, representing the multiple beats an. More...
 
bool OptMinSize = false
 OptMinSize - True if we're optimising for minimum code size, equal to the function attribute. More...
 
bool IsLittle
 IsLittle - The target is Little Endian. More...
 
Triple TargetTriple
 TargetTriple - What processor and OS we're targeting. More...
 
MCSchedModel SchedModel
 SchedModel - Processor specific instruction costs. More...
 
InstrItineraryData InstrItins
 Selected instruction itineraries (one entry per itinerary class.) More...
 
const TargetOptionsOptions
 Options passed via command line that could influence the target. More...
 
const ARMBaseTargetMachineTM
 

Detailed Description

Definition at line 47 of file ARMSubtarget.h.

Member Enumeration Documentation

◆ ARMArchEnum

Enumerator
ARMv2 
ARMv2a 
ARMv3 
ARMv3m 
ARMv4 
ARMv4t 
ARMv5 
ARMv5t 
ARMv5te 
ARMv5tej 
ARMv6 
ARMv6k 
ARMv6kz 
ARMv6m 
ARMv6sm 
ARMv6t2 
ARMv7a 
ARMv7em 
ARMv7m 
ARMv7r 
ARMv7ve 
ARMv81a 
ARMv82a 
ARMv83a 
ARMv84a 
ARMv85a 
ARMv86a 
ARMv87a 
ARMv88a 
ARMv8a 
ARMv8mBaseline 
ARMv8mMainline 
ARMv8r 
ARMv81mMainline 
ARMv9a 
ARMv91a 
ARMv92a 
ARMv93a 

Definition at line 96 of file ARMSubtarget.h.

◆ ARMLdStMultipleTiming

What kind of timing do load multiple/store multiple instructions have.

Enumerator
DoubleIssue 

Can load/store 2 registers/cycle.

DoubleIssueCheckUnalignedAccess 

Can load/store 2 registers/cycle, but needs an extra cycle if the access is not 64-bit aligned.

SingleIssue 

Can load/store 1 register/cycle.

SingleIssuePlusExtras 

Can load/store 1 register/cycle, but needs an extra cycle for address computation and potentially also for register writeback.

Definition at line 139 of file ARMSubtarget.h.

◆ ARMProcClassEnum

Enumerator
None 
AClass 
MClass 
RClass 

Definition at line 89 of file ARMSubtarget.h.

◆ ARMProcFamilyEnum

Enumerator
Others 
CortexA12 
CortexA15 
CortexA17 
CortexA32 
CortexA35 
CortexA5 
CortexA53 
CortexA55 
CortexA57 
CortexA7 
CortexA72 
CortexA73 
CortexA75 
CortexA76 
CortexA77 
CortexA78 
CortexA78C 
CortexA710 
CortexA8 
CortexA9 
CortexM3 
CortexM7 
CortexR4 
CortexR4F 
CortexR5 
CortexR52 
CortexR7 
CortexX1 
CortexX1C 
Exynos 
Krait 
Kryo 
NeoverseN1 
NeoverseN2 
NeoverseV1 
Swift 

Definition at line 49 of file ARMSubtarget.h.

Constructor & Destructor Documentation

◆ ARMSubtarget()

ARMSubtarget::ARMSubtarget ( const Triple TT,
const std::string &  CPU,
const std::string &  FS,
const ARMBaseTargetMachine TM,
bool  IsLittle,
bool  MinSize = false 
)

This constructor initializes the data members to match that of the specified triple.

Definition at line 93 of file ARMSubtarget.cpp.

References llvm::createARMInstructionSelector(), getRegisterInfo(), getTargetLowering(), and TM.

Member Function Documentation

◆ allowPositionIndependentMovt()

bool llvm::ARMSubtarget::allowPositionIndependentMovt ( ) const
inline

Allow movt+movw for PIC global address calculation.

ELF does not have GOT relocations for movt+movw. ROPI does not use GOT.

Definition at line 532 of file ARMSubtarget.h.

References isROPI(), and isTargetELF().

◆ allowsUnalignedMem()

bool llvm::ARMSubtarget::allowsUnalignedMem ( ) const
inline

◆ computeIssueWidth()

void llvm::ARMSubtarget::computeIssueWidth ( )

◆ enableMachinePipeliner()

bool ARMSubtarget::enableMachinePipeliner ( ) const
override

Returns true if machine pipeliner should be enabled.

Definition at line 396 of file ARMSubtarget.cpp.

References useMachinePipeliner().

Referenced by llvm::ARMBaseInstrInfo::analyzeBranch().

◆ enableMachineScheduler()

bool ARMSubtarget::enableMachineScheduler ( ) const
override

Returns true if machine scheduler should be enabled.

Definition at line 375 of file ARMSubtarget.cpp.

References hasMinSize(), isMClass(), and useMachineScheduler().

Referenced by enablePostRAMachineScheduler(), and enablePostRAScheduler().

◆ enablePostRAMachineScheduler()

bool ARMSubtarget::enablePostRAMachineScheduler ( ) const
override

True for some subtargets at > -O0.

Definition at line 414 of file ARMSubtarget.cpp.

References enableMachineScheduler(), and isThumb1Only().

◆ enablePostRAScheduler()

bool ARMSubtarget::enablePostRAScheduler ( ) const
override

True for some subtargets at > -O0.

Definition at line 405 of file ARMSubtarget.cpp.

References enableMachineScheduler(), and isThumb1Only().

◆ enableSubRegLiveness()

bool ARMSubtarget::enableSubRegLiveness ( ) const
override

Check whether this subtarget wants to use subregister liveness.

Definition at line 388 of file ARMSubtarget.cpp.

References EnableSubRegLiveness, and llvm::cl::Option::getNumOccurrences().

◆ getCallLowering()

const CallLowering * ARMSubtarget::getCallLowering ( ) const
override

Definition at line 124 of file ARMSubtarget.cpp.

◆ getCPUString()

const std::string& llvm::ARMSubtarget::getCPUString ( ) const
inline

Definition at line 460 of file ARMSubtarget.h.

References CPUString.

◆ getFrameLowering()

const ARMFrameLowering* llvm::ARMSubtarget::getFrameLowering ( ) const
inlineoverride

◆ getFramePointerReg()

MCPhysReg llvm::ARMSubtarget::getFramePointerReg ( ) const
inline

◆ getGPRAllocationOrder()

unsigned ARMSubtarget::getGPRAllocationOrder ( const MachineFunction MF) const

◆ getInstrInfo()

const ARMBaseInstrInfo* llvm::ARMSubtarget::getInstrInfo ( ) const
inlineoverride

◆ getInstrItineraryData()

const InstrItineraryData* llvm::ARMSubtarget::getInstrItineraryData ( ) const
inlineoverride

getInstrItins - Return the instruction itineraries based on subtarget selection.

Definition at line 488 of file ARMSubtarget.h.

References InstrItins.

Referenced by llvm::ARMTargetLowering::ARMTargetLowering().

◆ getInstructionSelector()

InstructionSelector * ARMSubtarget::getInstructionSelector ( ) const
override

Definition at line 128 of file ARMSubtarget.cpp.

◆ getLdStMultipleTiming()

ARMLdStMultipleTiming llvm::ARMSubtarget::getLdStMultipleTiming ( ) const
inline

Definition at line 501 of file ARMSubtarget.h.

References LdStMultipleTiming.

Referenced by llvm::ARMBaseInstrInfo::getNumMicroOps().

◆ getLegalizerInfo()

const LegalizerInfo * ARMSubtarget::getLegalizerInfo ( ) const
override

Definition at line 132 of file ARMSubtarget.cpp.

◆ getMaxInlineSizeThreshold()

unsigned llvm::ARMSubtarget::getMaxInlineSizeThreshold ( ) const
inline

getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size that still makes it profitable to inline the call.

Definition at line 242 of file ARMSubtarget.h.

Referenced by llvm::ARMSelectionDAGInfo::EmitTargetCodeForMemcpy(), and shouldGenerateInlineTPLoop().

◆ getMaxInterleaveFactor()

unsigned llvm::ARMSubtarget::getMaxInterleaveFactor ( ) const
inline

Definition at line 497 of file ARMSubtarget.h.

References MaxInterleaveFactor.

◆ getMaxMemcpyTPInlineSizeThreshold()

unsigned llvm::ARMSubtarget::getMaxMemcpyTPInlineSizeThreshold ( ) const
inline

getMaxMemcpyTPInlineSizeThreshold - Returns the maximum size that still makes it profitable to inline a llvm.memcpy as a Tail Predicated loop.

This threshold should only be used for constant size inputs.

Definition at line 250 of file ARMSubtarget.h.

Referenced by shouldGenerateInlineTPLoop().

◆ getMispredictionPenalty()

unsigned ARMSubtarget::getMispredictionPenalty ( ) const

◆ getMVEVectorCostFactor()

unsigned llvm::ARMSubtarget::getMVEVectorCostFactor ( TargetTransformInfo::TargetCostKind  CostKind) const
inline

◆ getPartialUpdateClearance()

unsigned llvm::ARMSubtarget::getPartialUpdateClearance ( ) const
inline

◆ getPrefLoopLogAlignment()

unsigned llvm::ARMSubtarget::getPrefLoopLogAlignment ( ) const
inline

Definition at line 536 of file ARMSubtarget.h.

References PrefLoopLogAlignment.

Referenced by llvm::ARMTargetLowering::ARMTargetLowering().

◆ getPreISelOperandLatencyAdjustment()

int llvm::ARMSubtarget::getPreISelOperandLatencyAdjustment ( ) const
inline

◆ getRegBankInfo()

const RegisterBankInfo * ARMSubtarget::getRegBankInfo ( ) const
override

Definition at line 136 of file ARMSubtarget.cpp.

Referenced by llvm::ARMCallLowering::lowerCall().

◆ getRegisterInfo()

const ARMBaseRegisterInfo* llvm::ARMSubtarget::getRegisterInfo ( ) const
inlineoverride

◆ getReturnOpcode()

unsigned llvm::ARMSubtarget::getReturnOpcode ( ) const
inline

Returns the correct return opcode for the current feature set.

Use BX if available to allow mixing thumb/arm code, but fall back to plain mov pc,lr on ARMv4.

Definition at line 521 of file ARMSubtarget.h.

References isThumb().

Referenced by llvm::ARMBaseInstrInfo::buildOutlinedFrame().

◆ getSelectionDAGInfo()

const ARMSelectionDAGInfo* llvm::ARMSubtarget::getSelectionDAGInfo ( ) const
inlineoverride

Definition at line 260 of file ARMSubtarget.h.

◆ getStackAlignment()

Align llvm::ARMSubtarget::getStackAlignment ( ) const
inline

getStackAlignment - Returns the minimum alignment known to hold of the stack frame on entry to the function and which must be maintained by every function for this subtarget.

Definition at line 495 of file ARMSubtarget.h.

References stackAlignment.

Referenced by llvm::ARMBaseInstrInfo::getOutliningType().

◆ getTargetLowering()

const ARMTargetLowering* llvm::ARMSubtarget::getTargetLowering ( ) const
inlineoverride

◆ getTargetTriple()

const Triple& llvm::ARMSubtarget::getTargetTriple ( ) const
inline

◆ hasAnyDataBarrier()

bool llvm::ARMSubtarget::hasAnyDataBarrier ( ) const
inline

Definition at line 339 of file ARMSubtarget.h.

References isThumb().

Referenced by llvm::ARMTargetLowering::ARMTargetLowering().

◆ hasARMOps()

bool llvm::ARMSubtarget::hasARMOps ( ) const
inline

Definition at line 328 of file ARMSubtarget.h.

Referenced by llvm::ARMTargetLowering::ARMTargetLowering(), and isXRaySupported().

◆ hasBaseDSP()

bool llvm::ARMSubtarget::hasBaseDSP ( ) const
inline

Definition at line 351 of file ARMSubtarget.h.

References isThumb().

Referenced by AddCombineTo64BitSMLAL16(), and llvm::ARMTargetLowering::ARMTargetLowering().

◆ hasFPARMv8Base()

bool llvm::ARMSubtarget::hasFPARMv8Base ( ) const
inline

◆ hasFusion()

bool llvm::ARMSubtarget::hasFusion ( ) const
inline

Return true if the CPU supports any kind of instruction fusion.

Definition at line 359 of file ARMSubtarget.h.

◆ hasMinSize()

bool llvm::ARMSubtarget::hasMinSize ( ) const
inline

◆ hasVFP2Base()

bool llvm::ARMSubtarget::hasVFP2Base ( ) const
inline

◆ hasVFP3Base()

bool llvm::ARMSubtarget::hasVFP3Base ( ) const
inline

Definition at line 335 of file ARMSubtarget.h.

Referenced by llvm::ARMTargetLowering::isFPImmLegal().

◆ hasVFP4Base()

bool llvm::ARMSubtarget::hasVFP4Base ( ) const
inline

Definition at line 336 of file ARMSubtarget.h.

Referenced by llvm::ARMTargetLowering::ARMTargetLowering(), and useFPVFMx().

◆ ignoreCSRForAllocationOrder()

bool ARMSubtarget::ignoreCSRForAllocationOrder ( const MachineFunction MF,
unsigned  PhysReg 
) const
override

◆ initializeSubtargetDependencies()

ARMSubtarget & ARMSubtarget::initializeSubtargetDependencies ( StringRef  CPU,
StringRef  FS 
)

initializeSubtargetDependencies - Initializes using a CPU and feature string so that we can use initializer lists for subtarget initialization.

Definition at line 77 of file ARMSubtarget.cpp.

References llvm::X86AS::FS.

◆ isAAPCS16_ABI()

bool ARMSubtarget::isAAPCS16_ABI ( ) const

◆ isAAPCS_ABI()

bool ARMSubtarget::isAAPCS_ABI ( ) const

◆ isAClass()

bool llvm::ARMSubtarget::isAClass ( ) const
inline

Definition at line 426 of file ARMSubtarget.h.

References AClass, and ARMProcClass.

◆ isAPCS_ABI()

bool ARMSubtarget::isAPCS_ABI ( ) const

◆ isCortexA15()

bool llvm::ARMSubtarget::isCortexA15 ( ) const
inline

Definition at line 319 of file ARMSubtarget.h.

References ARMProcFamily, and CortexA15.

Referenced by isLikeA9().

◆ isCortexA5()

bool llvm::ARMSubtarget::isCortexA5 ( ) const
inline

These functions are obsolete, please consider adding subtarget features or properties instead of calling them.

Definition at line 315 of file ARMSubtarget.h.

References ARMProcFamily, and CortexA5.

◆ isCortexA7()

bool llvm::ARMSubtarget::isCortexA7 ( ) const
inline

Definition at line 316 of file ARMSubtarget.h.

References ARMProcFamily, and CortexA7.

Referenced by adjustDefLatency(), and llvm::ARMBaseInstrInfo::getOperandLatency().

◆ isCortexA8()

bool llvm::ARMSubtarget::isCortexA8 ( ) const
inline

◆ isCortexA9()

bool llvm::ARMSubtarget::isCortexA9 ( ) const
inline

Definition at line 318 of file ARMSubtarget.h.

References ARMProcFamily, and CortexA9.

Referenced by isLikeA9().

◆ isCortexM3()

bool llvm::ARMSubtarget::isCortexM3 ( ) const
inline

Definition at line 321 of file ARMSubtarget.h.

References ARMProcFamily, and CortexM3.

◆ isCortexM7()

bool llvm::ARMSubtarget::isCortexM7 ( ) const
inline

Definition at line 322 of file ARMSubtarget.h.

References ARMProcFamily, and CortexM7.

Referenced by llvm::ARMBaseInstrInfo::CreateTargetMIHazardRecognizer().

◆ isCortexR5()

bool llvm::ARMSubtarget::isCortexR5 ( ) const
inline

Definition at line 324 of file ARMSubtarget.h.

References ARMProcFamily, and CortexR5.

◆ isGVIndirectSymbol()

bool ARMSubtarget::isGVIndirectSymbol ( const GlobalValue GV) const

◆ isGVInGOT()

bool ARMSubtarget::isGVInGOT ( const GlobalValue GV) const

◆ isKrait()

bool llvm::ARMSubtarget::isKrait ( ) const
inline

Definition at line 325 of file ARMSubtarget.h.

References ARMProcFamily, and Krait.

Referenced by isLikeA9().

◆ isLikeA9()

bool llvm::ARMSubtarget::isLikeA9 ( ) const
inline

◆ isLittle()

bool llvm::ARMSubtarget::isLittle ( ) const
inline

◆ isMClass()

bool llvm::ARMSubtarget::isMClass ( ) const
inline

◆ isR9Reserved()

bool llvm::ARMSubtarget::isR9Reserved ( ) const
inline

◆ isRClass()

bool llvm::ARMSubtarget::isRClass ( ) const
inline

Definition at line 425 of file ARMSubtarget.h.

References ARMProcClass, and RClass.

◆ isROPI()

bool ARMSubtarget::isROPI ( ) const

◆ isRWPI()

bool ARMSubtarget::isRWPI ( ) const

◆ isSwift()

bool llvm::ARMSubtarget::isSwift ( ) const
inline

◆ isTargetAEABI()

bool llvm::ARMSubtarget::isTargetAEABI ( ) const
inline

◆ isTargetAndroid()

bool llvm::ARMSubtarget::isTargetAndroid ( ) const
inline

Definition at line 408 of file ARMSubtarget.h.

References llvm::Triple::isAndroid(), and TargetTriple.

Referenced by llvm::ARMTargetLowering::ARMTargetLowering().

◆ isTargetCOFF()

bool llvm::ARMSubtarget::isTargetCOFF ( ) const
inline

◆ isTargetDarwin()

bool llvm::ARMSubtarget::isTargetDarwin ( ) const
inline

◆ isTargetDriverKit()

bool llvm::ARMSubtarget::isTargetDriverKit ( ) const
inline

◆ isTargetEHABICompatible()

bool llvm::ARMSubtarget::isTargetEHABICompatible ( ) const
inline

◆ isTargetELF()

bool llvm::ARMSubtarget::isTargetELF ( ) const
inline

◆ isTargetGNUAEABI()

bool llvm::ARMSubtarget::isTargetGNUAEABI ( ) const
inline

◆ isTargetHardFloat()

bool ARMSubtarget::isTargetHardFloat ( ) const

Definition at line 327 of file ARMSubtarget.cpp.

References llvm::ARMBaseTargetMachine::isTargetHardFloat(), and TM.

◆ isTargetIOS()

bool llvm::ARMSubtarget::isTargetIOS ( ) const
inline

Definition at line 364 of file ARMSubtarget.h.

References llvm::Triple::isiOS(), and TargetTriple.

Referenced by llvm::ARMTargetLowering::ARMTargetLowering().

◆ isTargetLinux()

bool llvm::ARMSubtarget::isTargetLinux ( ) const
inline

◆ isTargetMachO()

bool llvm::ARMSubtarget::isTargetMachO ( ) const
inline

◆ isTargetMuslAEABI()

bool llvm::ARMSubtarget::isTargetMuslAEABI ( ) const
inline

◆ isTargetNaCl()

bool llvm::ARMSubtarget::isTargetNaCl ( ) const
inline

Definition at line 369 of file ARMSubtarget.h.

References llvm::Triple::isOSNaCl(), and TargetTriple.

Referenced by useFastISel().

◆ isTargetNetBSD()

bool llvm::ARMSubtarget::isTargetNetBSD ( ) const
inline

Definition at line 370 of file ARMSubtarget.h.

References llvm::Triple::isOSNetBSD(), and TargetTriple.

◆ isTargetWatchABI()

bool llvm::ARMSubtarget::isTargetWatchABI ( ) const
inline

◆ isTargetWatchOS()

bool llvm::ARMSubtarget::isTargetWatchOS ( ) const
inline

Definition at line 365 of file ARMSubtarget.h.

References llvm::Triple::isWatchOS(), and TargetTriple.

Referenced by llvm::ARMTargetLowering::ARMTargetLowering().

◆ isTargetWindows()

bool llvm::ARMSubtarget::isTargetWindows ( ) const
inline

◆ isThumb1Only()

bool llvm::ARMSubtarget::isThumb1Only ( ) const
inline

Definition at line 422 of file ARMSubtarget.h.

References isThumb().

Referenced by llvm::ARMBaseInstrInfo::areLoadsFromSameBasePtr(), llvm::ARMTargetLowering::ARMTargetLowering(), llvm::ThumbRegisterInfo::eliminateFrameIndex(), llvm::ARMAsmPrinter::emitJumpTableTBInst(), llvm::ThumbRegisterInfo::emitLoadConstPool(), llvm::ARMSelectionDAGInfo::EmitTargetCodeForMemcpy(), enablePostRAMachineScheduler(), enablePostRAScheduler(), getGPRAllocationOrder(), llvm::ThumbRegisterInfo::getLargestLegalSuperClass(), llvm::ThumbRegisterInfo::getPointerRegClass(), llvm::ARMTargetLowering::getPostIndexedAddressParts(), llvm::ARMTargetLowering::getPreIndexedAddressParts(), llvm::ARMTargetLowering::getRegForInlineAsmConstraint(), llvm::ARMBaseRegisterInfo::getSjLjDispatchPreservedMask(), llvm::ARMTTIImpl::getUnrollingPreferences(), llvm::ARMTargetLowering::isDesirableToCommuteWithShift(), isLegalAddressImmediate(), llvm::ARMTargetLowering::isLegalAddressingMode(), llvm::ARMTargetLowering::LowerAsmOperandForConstraint(), llvm::ARMCallLowering::lowerCall(), LowerPREFETCH(), LowerSTORE(), PerformAddcSubcCombine(), PerformADDECombine(), PerformAddeSubeCombine(), PerformANDCombine(), llvm::ARMTargetLowering::PerformCMOVCombine(), PerformMULCombine(), PerformORCombine(), PerformORCombineToBFI(), PerformXORCombine(), llvm::ARMTargetLowering::preferIncOfAddToSubOfNot(), llvm::ThumbRegisterInfo::resolveFrameIndex(), llvm::ThumbRegisterInfo::rewriteFrameIndex(), llvm::ARMTargetLowering::shouldFoldConstantShiftPairToMask(), llvm::ARMBaseInstrInfo::shouldScheduleLoadsNear(), splitFramePushPop(), useFastISel(), and llvm::ThumbRegisterInfo::useFPForScavengingIndex().

◆ isThumb2()

bool llvm::ARMSubtarget::isThumb2 ( ) const
inline

◆ isXRaySupported()

bool ARMSubtarget::isXRaySupported ( ) const
override

Definition at line 140 of file ARMSubtarget.cpp.

References hasARMOps(), and isTargetWindows().

◆ ParseSubtargetFeatures()

void llvm::ARMSubtarget::ParseSubtargetFeatures ( StringRef  CPU,
StringRef  TuneCPU,
StringRef  FS 
)

ParseSubtargetFeatures - Parses features string setting specified subtarget options.

Definition of function is auto generated by tblgen.

◆ restrictIT()

bool llvm::ARMSubtarget::restrictIT ( ) const
inline

◆ splitFramePushPop()

bool llvm::ARMSubtarget::splitFramePushPop ( const MachineFunction MF) const
inline

Returns true if the frame setup is split into two separate pushes (first r0-r7,lr then r8-r11), principally so that the frame pointer is adjacent to lr.

This is always required on Thumb1-only targets, as the push and pop instructions can't access the high registers.

Definition at line 442 of file ARMSubtarget.h.

References llvm::TargetOptions::DisableFramePointerElim(), getFramePointerReg(), llvm::MachineFunction::getInfo(), llvm::MachineFunction::getTarget(), isThumb1Only(), llvm::TargetMachine::Options, and llvm::ARMFunctionInfo::shouldSignReturnAddress().

Referenced by llvm::ARMFrameLowering::determineCalleeSaves(), llvm::Thumb1FrameLowering::emitPrologue(), llvm::ARMFrameLowering::emitPrologue(), and llvm::ARMBaseRegisterInfo::getCalleeSavedRegs().

◆ supportsTailCall()

bool llvm::ARMSubtarget::supportsTailCall ( ) const
inline

Definition at line 454 of file ARMSubtarget.h.

References SupportsTailCall.

◆ useAA()

bool llvm::ARMSubtarget::useAA ( ) const
inlineoverride

Enable use of alias analysis during code generation (during MI scheduling, DAGCombine, etc.).

Definition at line 484 of file ARMSubtarget.h.

◆ useDFAforSMS()

bool ARMSubtarget::useDFAforSMS ( ) const
override

Definition at line 402 of file ARMSubtarget.cpp.

◆ useFastISel()

bool ARMSubtarget::useFastISel ( ) const

◆ useFPVFMx()

bool llvm::ARMSubtarget::useFPVFMx ( ) const
inline

Definition at line 345 of file ARMSubtarget.h.

References hasVFP4Base(), and isTargetDarwin().

Referenced by useFPVFMx16(), and useFPVFMx64().

◆ useFPVFMx16()

bool llvm::ARMSubtarget::useFPVFMx16 ( ) const
inline

Definition at line 348 of file ARMSubtarget.h.

References useFPVFMx().

◆ useFPVFMx64()

bool llvm::ARMSubtarget::useFPVFMx64 ( ) const
inline

Definition at line 349 of file ARMSubtarget.h.

References useFPVFMx().

◆ useFPVMLx()

bool llvm::ARMSubtarget::useFPVMLx ( ) const
inline

Definition at line 344 of file ARMSubtarget.h.

◆ useMachinePipeliner()

bool llvm::ARMSubtarget::useMachinePipeliner ( ) const
inline

Definition at line 420 of file ARMSubtarget.h.

Referenced by enableMachinePipeliner().

◆ useMachineScheduler()

bool llvm::ARMSubtarget::useMachineScheduler ( ) const
inline

Definition at line 419 of file ARMSubtarget.h.

Referenced by enableMachineScheduler().

◆ useMovt()

bool ARMSubtarget::useMovt ( ) const

Definition at line 430 of file ARMSubtarget.cpp.

References isTargetWindows(), and OptMinSize.

Referenced by llvm::ConstantMaterializationCost().

◆ useMulOps()

bool llvm::ARMSubtarget::useMulOps ( ) const
inline

Definition at line 343 of file ARMSubtarget.h.

References UseMulOps.

Referenced by AddCombineTo64bitMLAL().

◆ useNEONForSinglePrecisionFP()

bool llvm::ARMSubtarget::useNEONForSinglePrecisionFP ( ) const
inline

◆ useSjLjEH()

bool llvm::ARMSubtarget::useSjLjEH ( ) const
inline

◆ useStride4VFPs()

bool ARMSubtarget::useStride4VFPs ( ) const

Definition at line 422 of file ARMSubtarget.cpp.

References isTargetWatchABI(), and OptMinSize.

Member Data Documentation

◆ ARMArch

ARMArchEnum llvm::ARMSubtarget::ARMArch = ARMv4t
protected

ARMArch - ARM architecture.

Definition at line 165 of file ARMSubtarget.h.

◆ ARMProcClass

ARMProcClassEnum llvm::ARMSubtarget::ARMProcClass = None
protected

ARMProcClass - ARM processor class: None, AClass, RClass or MClass.

Definition at line 162 of file ARMSubtarget.h.

Referenced by isAClass(), isMClass(), and isRClass().

◆ ARMProcFamily

ARMProcFamilyEnum llvm::ARMSubtarget::ARMProcFamily = Others
protected

ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.

Definition at line 159 of file ARMSubtarget.h.

Referenced by isCortexA15(), isCortexA5(), isCortexA7(), isCortexA8(), isCortexA9(), isCortexM3(), isCortexM7(), isCortexR5(), isKrait(), and isSwift().

◆ CPUString

std::string llvm::ARMSubtarget::CPUString
protected

CPUString - String name of used CPU.

Definition at line 188 of file ARMSubtarget.h.

Referenced by getCPUString().

◆ InstrItins

InstrItineraryData llvm::ARMSubtarget::InstrItins
protected

Selected instruction itineraries (one entry per itinerary class.)

Definition at line 225 of file ARMSubtarget.h.

Referenced by getInstrItineraryData().

◆ IsLittle

bool llvm::ARMSubtarget::IsLittle
protected

IsLittle - The target is Little Endian.

Definition at line 216 of file ARMSubtarget.h.

Referenced by isLittle().

◆ LdStMultipleTiming

ARMLdStMultipleTiming llvm::ARMSubtarget::LdStMultipleTiming = SingleIssue
protected

What kind of timing do load multiple/store multiple have (double issue, single issue etc).

Definition at line 197 of file ARMSubtarget.h.

Referenced by getLdStMultipleTiming().

◆ MaxInterleaveFactor

unsigned llvm::ARMSubtarget::MaxInterleaveFactor = 1
protected

Definition at line 190 of file ARMSubtarget.h.

Referenced by getMaxInterleaveFactor().

◆ MVEVectorCostFactor

unsigned llvm::ARMSubtarget::MVEVectorCostFactor = 0
protected

The cost factor for MVE instructions, representing the multiple beats an.

Definition at line 209 of file ARMSubtarget.h.

Referenced by getMVEVectorCostFactor().

◆ Options

const TargetOptions& llvm::ARMSubtarget::Options
protected

Options passed via command line that could influence the target.

Definition at line 228 of file ARMSubtarget.h.

◆ OptMinSize

bool llvm::ARMSubtarget::OptMinSize = false
protected

OptMinSize - True if we're optimising for minimum code size, equal to the function attribute.

Definition at line 213 of file ARMSubtarget.h.

Referenced by hasMinSize(), useMovt(), and useStride4VFPs().

◆ PartialUpdateClearance

unsigned llvm::ARMSubtarget::PartialUpdateClearance = 0
protected

Clearance before partial register updates (in number of instructions)

Definition at line 193 of file ARMSubtarget.h.

Referenced by getPartialUpdateClearance().

◆ PrefLoopLogAlignment

unsigned llvm::ARMSubtarget::PrefLoopLogAlignment = 0
protected

What alignment is preferred for loop bodies, in log2(bytes).

Definition at line 204 of file ARMSubtarget.h.

Referenced by getPrefLoopLogAlignment().

◆ PreISelOperandLatencyAdjustment

int llvm::ARMSubtarget::PreISelOperandLatencyAdjustment = 2
protected

The adjustment that we need to apply to get the operand latency from the operand cycle returned by the itinerary data for pre-ISel operands.

Definition at line 201 of file ARMSubtarget.h.

Referenced by getPreISelOperandLatencyAdjustment().

◆ RestrictIT

bool llvm::ARMSubtarget::RestrictIT = false
protected

RestrictIT - If true, the subtarget disallows generation of complex IT blocks.

Definition at line 178 of file ARMSubtarget.h.

Referenced by restrictIT().

◆ SchedModel

MCSchedModel llvm::ARMSubtarget::SchedModel
protected

SchedModel - Processor specific instruction costs.

Definition at line 222 of file ARMSubtarget.h.

Referenced by getMispredictionPenalty().

◆ stackAlignment

Align llvm::ARMSubtarget::stackAlignment = Align(4)
protected

stackAlignment - The minimum alignment known to hold of the stack frame on entry to the function and which must be maintained by every function.

Definition at line 185 of file ARMSubtarget.h.

Referenced by getStackAlignment().

◆ SupportsTailCall

bool llvm::ARMSubtarget::SupportsTailCall = false
protected

SupportsTailCall - True if the OS supports tail call.

The dynamic linker must be able to synthesize call stubs for interworking between ARM and Thumb.

Definition at line 174 of file ARMSubtarget.h.

Referenced by supportsTailCall().

◆ TargetTriple

Triple llvm::ARMSubtarget::TargetTriple
protected

◆ TM

const ARMBaseTargetMachine& llvm::ARMSubtarget::TM
protected

◆ UseMulOps

bool llvm::ARMSubtarget::UseMulOps = false
protected

UseMulOps - True if non-microcoded fused integer multiply-add and multiply-subtract instructions should be used.

Definition at line 169 of file ARMSubtarget.h.

Referenced by useMulOps().

◆ UseSjLjEH

bool llvm::ARMSubtarget::UseSjLjEH = false
protected

UseSjLjEH - If true, the target uses SjLj exception handling (e.g. iOS).

Definition at line 181 of file ARMSubtarget.h.

Referenced by useSjLjEH().


The documentation for this class was generated from the following files: