LLVM 17.0.0git
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#include "Target/ARM/ARMSubtarget.h"
Public Types | |
enum | ARMLdStMultipleTiming { DoubleIssue , DoubleIssueCheckUnalignedAccess , SingleIssue , SingleIssuePlusExtras } |
What kind of timing do load multiple/store multiple instructions have. More... | |
Protected Types | |
enum | ARMProcFamilyEnum { Others , CortexA12 , CortexA15 , CortexA17 , CortexA32 , CortexA35 , CortexA5 , CortexA53 , CortexA55 , CortexA57 , CortexA7 , CortexA72 , CortexA73 , CortexA75 , CortexA76 , CortexA77 , CortexA78 , CortexA78C , CortexA710 , CortexA8 , CortexA9 , CortexM3 , CortexM7 , CortexR4 , CortexR4F , CortexR5 , CortexR52 , CortexR7 , CortexX1 , CortexX1C , Exynos , Krait , Kryo , NeoverseN1 , NeoverseN2 , NeoverseV1 , Swift } |
enum | ARMProcClassEnum { None , AClass , MClass , RClass } |
enum | ARMArchEnum { ARMv4 , ARMv4t , ARMv5 , ARMv5t , ARMv5te , ARMv5tej , ARMv6 , ARMv6k , ARMv6kz , ARMv6m , ARMv6sm , ARMv6t2 , ARMv7a , ARMv7em , ARMv7m , ARMv7r , ARMv7ve , ARMv81a , ARMv82a , ARMv83a , ARMv84a , ARMv85a , ARMv86a , ARMv87a , ARMv88a , ARMv89a , ARMv8a , ARMv8mBaseline , ARMv8mMainline , ARMv8r , ARMv81mMainline , ARMv9a , ARMv91a , ARMv92a , ARMv93a , ARMv94a } |
Protected Attributes | |
ARMProcFamilyEnum | ARMProcFamily = Others |
ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others. | |
ARMProcClassEnum | ARMProcClass = None |
ARMProcClass - ARM processor class: None, AClass, RClass or MClass. | |
ARMArchEnum | ARMArch = ARMv4t |
ARMArch - ARM architecture. | |
bool | UseMulOps = false |
UseMulOps - True if non-microcoded fused integer multiply-add and multiply-subtract instructions should be used. | |
bool | SupportsTailCall = false |
SupportsTailCall - True if the OS supports tail call. | |
bool | RestrictIT = false |
RestrictIT - If true, the subtarget disallows generation of complex IT blocks. | |
bool | UseSjLjEH = false |
UseSjLjEH - If true, the target uses SjLj exception handling (e.g. iOS). | |
Align | stackAlignment = Align(4) |
stackAlignment - The minimum alignment known to hold of the stack frame on entry to the function and which must be maintained by every function. | |
std::string | CPUString |
CPUString - String name of used CPU. | |
unsigned | MaxInterleaveFactor = 1 |
unsigned | PartialUpdateClearance = 0 |
Clearance before partial register updates (in number of instructions) | |
ARMLdStMultipleTiming | LdStMultipleTiming = SingleIssue |
What kind of timing do load multiple/store multiple have (double issue, single issue etc). | |
int | PreISelOperandLatencyAdjustment = 2 |
The adjustment that we need to apply to get the operand latency from the operand cycle returned by the itinerary data for pre-ISel operands. | |
unsigned | PrefLoopLogAlignment = 0 |
What alignment is preferred for loop bodies, in log2(bytes). | |
unsigned | MVEVectorCostFactor = 0 |
The cost factor for MVE instructions, representing the multiple beats an. | |
bool | OptMinSize = false |
OptMinSize - True if we're optimising for minimum code size, equal to the function attribute. | |
bool | IsLittle |
IsLittle - The target is Little Endian. | |
Triple | TargetTriple |
TargetTriple - What processor and OS we're targeting. | |
MCSchedModel | SchedModel |
SchedModel - Processor specific instruction costs. | |
InstrItineraryData | InstrItins |
Selected instruction itineraries (one entry per itinerary class.) | |
const TargetOptions & | Options |
Options passed via command line that could influence the target. | |
const ARMBaseTargetMachine & | TM |
Definition at line 47 of file ARMSubtarget.h.
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Definition at line 96 of file ARMSubtarget.h.
What kind of timing do load multiple/store multiple instructions have.
Definition at line 137 of file ARMSubtarget.h.
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Enumerator | |
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None | |
AClass | |
MClass | |
RClass |
Definition at line 89 of file ARMSubtarget.h.
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Definition at line 49 of file ARMSubtarget.h.
ARMSubtarget::ARMSubtarget | ( | const Triple & | TT, |
const std::string & | CPU, | ||
const std::string & | FS, | ||
const ARMBaseTargetMachine & | TM, | ||
bool | IsLittle, | ||
bool | MinSize = false |
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This constructor initializes the data members to match that of the specified triple.
Definition at line 92 of file ARMSubtarget.cpp.
References llvm::createARMInstructionSelector(), getRegisterInfo(), getTargetLowering(), InstrInfo, and TM.
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Allow movt+movw for PIC global address calculation.
ELF does not have GOT relocations for movt+movw. ROPI does not use GOT.
Definition at line 532 of file ARMSubtarget.h.
References isROPI(), and isTargetELF().
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Definition at line 456 of file ARMSubtarget.h.
Referenced by llvm::ARMTargetLowering::allowsMisalignedMemoryAccesses().
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Returns true if machine pipeliner should be enabled.
Definition at line 395 of file ARMSubtarget.cpp.
References useMachinePipeliner().
Referenced by llvm::ARMBaseInstrInfo::analyzeBranch().
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Returns true if machine scheduler should be enabled.
Definition at line 374 of file ARMSubtarget.cpp.
References hasMinSize(), isMClass(), and useMachineScheduler().
Referenced by enablePostRAMachineScheduler(), and enablePostRAScheduler().
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True for some subtargets at > -O0.
Definition at line 413 of file ARMSubtarget.cpp.
References enableMachineScheduler(), and isThumb1Only().
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True for some subtargets at > -O0.
Definition at line 404 of file ARMSubtarget.cpp.
References enableMachineScheduler(), and isThumb1Only().
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Check whether this subtarget wants to use subregister liveness.
Definition at line 387 of file ARMSubtarget.cpp.
References EnableSubRegLiveness.
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Definition at line 123 of file ARMSubtarget.cpp.
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Definition at line 460 of file ARMSubtarget.h.
References CPUString.
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Definition at line 270 of file ARMSubtarget.h.
Referenced by llvm::ThumbRegisterInfo::eliminateFrameIndex(), and llvm::ARMFrameLowering::emitPrologue().
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Definition at line 429 of file ARMSubtarget.h.
References isTargetDarwin(), isTargetWindows(), and isThumb().
Referenced by llvm::ARMBaseRegisterInfo::canRealignStack(), llvm::ARMAsmPrinter::emitInstruction(), llvm::ARMBaseRegisterInfo::getFrameRegister(), llvm::ARMBaseRegisterInfo::getReservedRegs(), llvm::ARMBaseRegisterInfo::isInlineAsmReadOnlyReg(), and splitFramePushPop().
unsigned ARMSubtarget::getGPRAllocationOrder | ( | const MachineFunction & | MF | ) | const |
Definition at line 452 of file ARMSubtarget.cpp.
References llvm::MachineFunction::getFunction(), llvm::Function::hasMinSize(), isThumb1Only(), and isThumb2().
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Definition at line 262 of file ARMSubtarget.h.
Referenced by llvm::ARMTargetLowering::AdjustInstrPostInstrSelection(), llvm::Thumb1FrameLowering::eliminateCallFramePseudoInstr(), llvm::ThumbRegisterInfo::eliminateFrameIndex(), llvm::ARMFrameLowering::emitEpilogue(), llvm::Thumb1FrameLowering::emitEpilogue(), llvm::ARMTargetLowering::EmitInstrWithCustomInserter(), llvm::ARMFrameLowering::emitPrologue(), llvm::Thumb1FrameLowering::emitPrologue(), emitThumb1LoadConstPool(), llvm::ARMTargetLowering::getSchedulingPreference(), llvm::ARMCallLowering::lowerCall(), llvm::ThumbRegisterInfo::resolveFrameIndex(), llvm::Thumb1FrameLowering::restoreCalleeSavedRegisters(), llvm::ARMFrameLowering::spillCalleeSavedRegisters(), and llvm::Thumb1FrameLowering::spillCalleeSavedRegisters().
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getInstrItins - Return the instruction itineraries based on subtarget selection.
Definition at line 488 of file ARMSubtarget.h.
References InstrItins.
Referenced by llvm::ARMTargetLowering::ARMTargetLowering().
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Definition at line 127 of file ARMSubtarget.cpp.
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Definition at line 501 of file ARMSubtarget.h.
References LdStMultipleTiming.
Referenced by llvm::ARMBaseInstrInfo::getNumMicroOps().
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Definition at line 131 of file ARMSubtarget.cpp.
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getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size that still makes it profitable to inline the call.
Definition at line 240 of file ARMSubtarget.h.
Referenced by llvm::ARMSelectionDAGInfo::EmitTargetCodeForMemcpy(), and shouldGenerateInlineTPLoop().
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Definition at line 497 of file ARMSubtarget.h.
References MaxInterleaveFactor.
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getMaxMemcpyTPInlineSizeThreshold - Returns the maximum size that still makes it profitable to inline a llvm.memcpy as a Tail Predicated loop.
This threshold should only be used for constant size inputs.
Definition at line 248 of file ARMSubtarget.h.
Referenced by shouldGenerateInlineTPLoop().
unsigned ARMSubtarget::getMispredictionPenalty | ( | ) | const |
Definition at line 370 of file ARMSubtarget.cpp.
References llvm::MCSchedModel::MispredictPenalty, and SchedModel.
Referenced by llvm::ARMBaseInstrInfo::isProfitableToIfCvt().
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Definition at line 539 of file ARMSubtarget.h.
References CostKind, MVEVectorCostFactor, and llvm::TargetTransformInfo::TCK_CodeSize.
Referenced by llvm::ARMTTIImpl::getArithmeticInstrCost(), llvm::ARMTTIImpl::getArithmeticReductionCost(), llvm::ARMTTIImpl::getCastInstrCost(), llvm::ARMTTIImpl::getCmpSelInstrCost(), llvm::ARMTTIImpl::getExtendedReductionCost(), llvm::ARMTTIImpl::getGatherScatterOpCost(), llvm::ARMTTIImpl::getInterleavedMemoryOpCost(), llvm::ARMTTIImpl::getIntrinsicInstrCost(), llvm::ARMTTIImpl::getMaskedMemoryOpCost(), llvm::ARMTTIImpl::getMemoryOpCost(), llvm::ARMTTIImpl::getMulAccReductionCost(), and llvm::ARMTTIImpl::getShuffleCost().
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Definition at line 499 of file ARMSubtarget.h.
References PartialUpdateClearance.
Referenced by llvm::ARMBaseInstrInfo::getPartialRegUpdateClearance().
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Definition at line 536 of file ARMSubtarget.h.
References PrefLoopLogAlignment.
Referenced by llvm::ARMTargetLowering::ARMTargetLowering().
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Definition at line 505 of file ARMSubtarget.h.
References PreISelOperandLatencyAdjustment.
Referenced by llvm::ARMBaseInstrInfo::getOperandLatency().
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Definition at line 135 of file ARMSubtarget.cpp.
Referenced by llvm::ARMCallLowering::lowerCall().
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Definition at line 274 of file ARMSubtarget.h.
Referenced by llvm::ARMFrameLowering::adjustForSegmentedStacks(), ARMSubtarget(), llvm::ARMTargetLowering::ARMTargetLowering(), llvm::Thumb1InstrInfo::copyPhysReg(), llvm::Thumb1FrameLowering::eliminateCallFramePseudoInstr(), llvm::Thumb1FrameLowering::emitEpilogue(), llvm::ARMTargetLowering::EmitInstrWithCustomInserter(), llvm::ARMFrameLowering::emitPrologue(), llvm::Thumb1FrameLowering::emitPrologue(), insertSEH(), llvm::ARMCallLowering::lowerCall(), and splitFramePointerPush().
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Returns the correct return opcode for the current feature set.
Use BX if available to allow mixing thumb/arm code, but fall back to plain mov pc,lr on ARMv4.
Definition at line 521 of file ARMSubtarget.h.
References isThumb().
Referenced by llvm::ARMBaseInstrInfo::buildOutlinedFrame().
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Definition at line 258 of file ARMSubtarget.h.
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getStackAlignment - Returns the minimum alignment known to hold of the stack frame on entry to the function and which must be maintained by every function for this subtarget.
Definition at line 495 of file ARMSubtarget.h.
References stackAlignment.
Referenced by llvm::ARMBaseInstrInfo::getOutliningTypeImpl().
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Definition at line 266 of file ARMSubtarget.h.
Referenced by AlignBlocks(), ARMSubtarget(), llvm::ARMSelectionDAGInfo::EmitSpecializedLibcall(), llvm::ARMBaseRegisterInfo::getCalleeSavedRegs(), llvm::ARMBaseRegisterInfo::getCallPreservedMask(), and PerformXORCombine().
Definition at line 357 of file ARMSubtarget.h.
References TargetTriple.
Referenced by llvm::ARMTargetLowering::ARMTargetLowering(), llvm::ARMTargetLowering::getSDagStackGuard(), llvm::ARMTargetLowering::getSSPStackGuardCheck(), and llvm::ARMTargetLowering::insertSSPDeclarations().
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Definition at line 335 of file ARMSubtarget.h.
References isThumb().
Referenced by llvm::ARMTargetLowering::ARMTargetLowering().
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Definition at line 324 of file ARMSubtarget.h.
Referenced by llvm::ARMTargetLowering::ARMTargetLowering(), llvm::ARMTTIImpl::hasArmWideBranch(), and isXRaySupported().
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Definition at line 347 of file ARMSubtarget.h.
References isThumb().
Referenced by AddCombineTo64BitSMLAL16(), and llvm::ARMTargetLowering::ARMTargetLowering().
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Definition at line 333 of file ARMSubtarget.h.
Referenced by llvm::ARMTargetLowering::ARMTargetLowering(), llvm::ARMTTIImpl::isLoweredToCall(), and llvm::ARMTTIImpl::maybeLoweredToCall().
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Return true if the CPU supports any kind of instruction fusion.
Definition at line 355 of file ARMSubtarget.h.
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Definition at line 418 of file ARMSubtarget.h.
References OptMinSize.
Referenced by llvm::ARMTargetLowering::ARMTargetLowering(), llvm::ARMSelectionDAGInfo::EmitTargetCodeForMemcpy(), enableMachineScheduler(), llvm::ARMTargetLowering::preferredShiftLegalizationStrategy(), and llvm::tryFoldSPUpdateIntoPushPop().
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Definition at line 330 of file ARMSubtarget.h.
Referenced by llvm::ARMTargetLowering::ARMTargetLowering(), llvm::ARMBaseInstrInfo::CreateTargetPostRAHazardRecognizer(), llvm::ARMTTIImpl::getCastInstrCost(), llvm::ARMRegisterBankInfo::getInstrMapping(), llvm::ARMTTIImpl::getIntImmCostInst(), llvm::ARMTTIImpl::getIntrinsicInstrCost(), llvm::ARMBaseRegisterInfo::getSjLjDispatchPreservedMask(), isLegalAddressImmediate(), isLegalT2AddressImmediate(), llvm::ARMTTIImpl::isLoweredToCall(), llvm::ARMTargetLowering::LowerXConstraint(), and llvm::ARMTargetLowering::shouldConvertFpToSat().
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Definition at line 331 of file ARMSubtarget.h.
Referenced by llvm::ARMTargetLowering::isFPImmLegal().
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Definition at line 332 of file ARMSubtarget.h.
Referenced by llvm::ARMTargetLowering::ARMTargetLowering(), and useFPVFMx().
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Definition at line 483 of file ARMSubtarget.cpp.
References llvm::MachineFunction::getFunction(), llvm::Function::hasMinSize(), and isThumb2().
ARMSubtarget & ARMSubtarget::initializeSubtargetDependencies | ( | StringRef | CPU, |
StringRef | FS | ||
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initializeSubtargetDependencies - Initializes using a CPU and feature string so that we can use initializer lists for subtarget initialization.
Definition at line 76 of file ARMSubtarget.cpp.
bool ARMSubtarget::isAAPCS16_ABI | ( | ) | const |
Definition at line 337 of file ARMSubtarget.cpp.
References llvm::ARMBaseTargetMachine::ARM_ABI_AAPCS16, llvm::ARMBaseTargetMachine::ARM_ABI_UNKNOWN, assert(), llvm::ARMBaseTargetMachine::TargetABI, and TM.
bool ARMSubtarget::isAAPCS_ABI | ( | ) | const |
Definition at line 332 of file ARMSubtarget.cpp.
References llvm::ARMBaseTargetMachine::ARM_ABI_AAPCS, llvm::ARMBaseTargetMachine::ARM_ABI_AAPCS16, llvm::ARMBaseTargetMachine::ARM_ABI_UNKNOWN, assert(), llvm::ARMBaseTargetMachine::TargetABI, and TM.
Referenced by llvm::ARMTargetLowering::ARMTargetLowering().
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Definition at line 423 of file ARMSubtarget.h.
References AClass, and ARMProcClass.
bool ARMSubtarget::isAPCS_ABI | ( | ) | const |
Definition at line 328 of file ARMSubtarget.cpp.
References llvm::ARMBaseTargetMachine::ARM_ABI_APCS, llvm::ARMBaseTargetMachine::ARM_ABI_UNKNOWN, assert(), llvm::ARMBaseTargetMachine::TargetABI, and TM.
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Definition at line 315 of file ARMSubtarget.h.
References ARMProcFamily, and CortexA15.
Referenced by isLikeA9().
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These functions are obsolete, please consider adding subtarget features or properties instead of calling them.
Definition at line 311 of file ARMSubtarget.h.
References ARMProcFamily, and CortexA5.
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Definition at line 312 of file ARMSubtarget.h.
References ARMProcFamily, and CortexA7.
Referenced by adjustDefLatency(), and llvm::ARMBaseInstrInfo::getOperandLatency().
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Definition at line 313 of file ARMSubtarget.h.
References ARMProcFamily, and CortexA8.
Referenced by adjustDefLatency(), llvm::ARMBaseInstrInfo::getExecutionDomain(), and llvm::ARMBaseInstrInfo::getOperandLatency().
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Definition at line 314 of file ARMSubtarget.h.
References ARMProcFamily, and CortexA9.
Referenced by isLikeA9().
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Definition at line 317 of file ARMSubtarget.h.
References ARMProcFamily, and CortexM3.
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Definition at line 318 of file ARMSubtarget.h.
References ARMProcFamily, and CortexM7.
Referenced by llvm::ARMBaseInstrInfo::CreateTargetMIHazardRecognizer().
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Definition at line 320 of file ARMSubtarget.h.
References ARMProcFamily, and CortexR5.
bool ARMSubtarget::isGVIndirectSymbol | ( | const GlobalValue * | GV | ) | const |
True if the GV will be accessed via an indirect symbol.
Definition at line 351 of file ARMSubtarget.cpp.
References llvm::GlobalValue::getParent(), llvm::GlobalValue::hasCommonLinkage(), llvm::GlobalValue::isDeclarationForLinker(), llvm::TargetMachine::isPositionIndependent(), isTargetMachO(), llvm::TargetMachine::shouldAssumeDSOLocal(), and TM.
Referenced by llvm::ARMBaseInstrInfo::expandLoadStackGuardBase().
bool ARMSubtarget::isGVInGOT | ( | const GlobalValue * | GV | ) | const |
Returns the constant pool modifier needed to access the GV.
Definition at line 365 of file ARMSubtarget.cpp.
References llvm::GlobalValue::getParent(), llvm::TargetMachine::isPositionIndependent(), isTargetELF(), llvm::TargetMachine::shouldAssumeDSOLocal(), and TM.
Referenced by llvm::ARMBaseInstrInfo::expandLoadStackGuardBase().
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Definition at line 321 of file ARMSubtarget.h.
References ARMProcFamily, and Krait.
Referenced by isLikeA9().
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Definition at line 319 of file ARMSubtarget.h.
References isCortexA15(), isCortexA9(), and isKrait().
Referenced by adjustDefLatency(), and llvm::ARMBaseInstrInfo::getOperandLatency().
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Definition at line 462 of file ARMSubtarget.h.
References IsLittle.
Referenced by llvm::ARMTargetLowering::allowsMisalignedMemoryAccesses(), llvm::ARMTargetLowering::emitLoadLinked(), llvm::ARMTargetLowering::emitStoreConditional(), llvm::ARMTargetLowering::getPostIndexedAddressParts(), llvm::ARMTargetLowering::getPreIndexedAddressParts(), PerformMVEVMULLCombine(), and PerformVMOVRRDCombine().
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Definition at line 421 of file ARMSubtarget.h.
References ARMProcClass, and MClass.
Referenced by llvm::ARMTargetLowering::alignLoopsWithOptSize(), llvm::ARMFunctionInfo::ARMFunctionInfo(), llvm::ARMTargetLowering::ARMTargetLowering(), llvm::ARMBaseInstrInfo::copyFromCPSR(), llvm::ARMBaseInstrInfo::copyToCPSR(), enableMachineScheduler(), GetBranchTargetEnforcement(), llvm::ARMBaseRegisterInfo::getCalleeSavedRegs(), llvm::ARMTTIImpl::getPreferredAddressingMode(), llvm::ARMTTIImpl::getUnrollingPreferences(), LowerATOMIC_FENCE(), llvm::ARMTargetLowering::makeDMB(), llvm::ARMTargetLowering::shouldAlignPointerArgs(), llvm::ARMTargetLowering::shouldExpandAtomicCmpXchgInIR(), llvm::ARMTargetLowering::shouldExpandAtomicLoadInIR(), llvm::ARMTargetLowering::shouldExpandAtomicRMWInIR(), llvm::ARMTargetLowering::shouldExpandAtomicStoreInIR(), and llvm::ARMBaseInstrInfo::shouldOutlineFromFunctionByDefault().
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Definition at line 425 of file ARMSubtarget.h.
References isTargetMachO().
Referenced by llvm::ARMBaseRegisterInfo::getRegPressureLimit(), and llvm::ARMBaseRegisterInfo::getReservedRegs().
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Definition at line 422 of file ARMSubtarget.h.
References ARMProcClass, and RClass.
bool ARMSubtarget::isROPI | ( | ) | const |
Definition at line 342 of file ARMSubtarget.cpp.
References llvm::TargetMachine::getRelocationModel(), llvm::Reloc::ROPI, llvm::Reloc::ROPI_RWPI, and TM.
Referenced by allowPositionIndependentMovt(), llvm::ARMAsmPrinter::emitJumpTableAddrs(), llvm::ARMBaseInstrInfo::expandLoadStackGuardBase(), promoteToConstantPool(), and llvm::ARMTargetLowering::useLoadStackGuardNode().
bool ARMSubtarget::isRWPI | ( | ) | const |
Definition at line 346 of file ARMSubtarget.cpp.
References llvm::TargetMachine::getRelocationModel(), llvm::Reloc::ROPI_RWPI, llvm::Reloc::RWPI, and TM.
Referenced by llvm::ARMBaseInstrInfo::expandLoadStackGuardBase(), and llvm::ARMTargetLowering::useLoadStackGuardNode().
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Definition at line 316 of file ARMSubtarget.h.
References ARMProcFamily, and Swift.
Referenced by adjustDefLatency(), llvm::ARMBaseInstrInfo::getNumMicroOps(), and llvm::ARMBaseInstrInfo::getOperandLatency().
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Definition at line 380 of file ARMSubtarget.h.
References llvm::Triple::EABI, llvm::Triple::EABIHF, llvm::Triple::getEnvironment(), isTargetDarwin(), isTargetWindows(), and TargetTriple.
Referenced by llvm::ARMTargetLowering::ARMTargetLowering(), CC_ARM_AAPCS_Custom_Aggregate(), and llvm::ARMAsmPrinter::emitEndOfAsmFile().
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Definition at line 405 of file ARMSubtarget.h.
References llvm::Triple::isAndroid(), and TargetTriple.
Referenced by llvm::ARMTargetLowering::ARMTargetLowering().
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Definition at line 369 of file ARMSubtarget.h.
References llvm::Triple::isOSBinFormatCOFF(), and TargetTriple.
Referenced by llvm::ARMBaseInstrInfo::expandLoadStackGuardBase(), and llvm::ARMAsmPrinter::runOnMachineFunction().
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Definition at line 359 of file ARMSubtarget.h.
References llvm::Triple::isOSDarwin(), and TargetTriple.
Referenced by llvm::ARMTargetLowering::ARMTargetLowering(), llvm::ARMAsmPrinter::emitInstruction(), llvm::ARMBaseRegisterInfo::getCalleeSavedRegs(), llvm::ARMBaseRegisterInfo::getCallPreservedMask(), getFramePointerReg(), llvm::ARMBaseRegisterInfo::getThisReturnPreservedMask(), llvm::ARMBaseRegisterInfo::getTLSCallPreservedMask(), isTargetAEABI(), isTargetGNUAEABI(), isTargetMuslAEABI(), and useFPVFMx().
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Definition at line 363 of file ARMSubtarget.h.
References llvm::Triple::isDriverKit(), and TargetTriple.
Referenced by llvm::ARMTargetLowering::ARMTargetLowering().
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Definition at line 399 of file ARMSubtarget.h.
References llvm::Triple::isTargetEHABICompatible(), and TargetTriple.
Referenced by llvm::ARMAsmPrinter::emitInstruction().
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Definition at line 370 of file ARMSubtarget.h.
References llvm::Triple::isOSBinFormatELF(), and TargetTriple.
Referenced by allowPositionIndependentMovt(), llvm::ARMFrameLowering::emitPrologue(), llvm::Thumb1FrameLowering::emitPrologue(), llvm::ARMAsmPrinter::emitXXStructor(), and isGVInGOT().
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Definition at line 385 of file ARMSubtarget.h.
References llvm::Triple::getEnvironment(), llvm::Triple::GNUEABI, llvm::Triple::GNUEABIHF, isTargetDarwin(), isTargetWindows(), and TargetTriple.
Referenced by llvm::ARMTargetLowering::ARMTargetLowering(), and llvm::ARMAsmPrinter::emitEndOfAsmFile().
bool ARMSubtarget::isTargetHardFloat | ( | ) | const |
Definition at line 326 of file ARMSubtarget.cpp.
References llvm::ARMBaseTargetMachine::isTargetHardFloat(), and TM.
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Definition at line 360 of file ARMSubtarget.h.
References llvm::Triple::isiOS(), and TargetTriple.
Referenced by llvm::ARMTargetLowering::ARMTargetLowering().
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Definition at line 364 of file ARMSubtarget.h.
References llvm::Triple::isOSLinux(), and TargetTriple.
Referenced by llvm::ARMTargetLowering::ARMTargetLowering(), and useFastISel().
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Definition at line 371 of file ARMSubtarget.h.
References llvm::Triple::isOSBinFormatMachO(), and TargetTriple.
Referenced by llvm::ARMTargetLowering::ARMTargetLowering(), llvm::ARMBaseInstrInfo::buildOutlinedFrame(), llvm::ARMAsmPrinter::emitInstruction(), llvm::ARMAsmPrinter::emitMachineConstantPoolValue(), llvm::ARMBaseInstrInfo::expandLoadStackGuardBase(), llvm::ARMBaseInstrInfo::insertOutlinedCall(), isGVIndirectSymbol(), isR9Reserved(), and useFastISel().
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Definition at line 390 of file ARMSubtarget.h.
References llvm::Triple::getEnvironment(), isTargetDarwin(), isTargetWindows(), llvm::Triple::MuslEABI, llvm::Triple::MuslEABIHF, llvm::Triple::OpenHOS, and TargetTriple.
Referenced by llvm::ARMTargetLowering::ARMTargetLowering(), and llvm::ARMAsmPrinter::emitEndOfAsmFile().
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Definition at line 365 of file ARMSubtarget.h.
References llvm::Triple::isOSNaCl(), and TargetTriple.
Referenced by useFastISel().
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Definition at line 366 of file ARMSubtarget.h.
References llvm::Triple::isOSNetBSD(), and TargetTriple.
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Definition at line 362 of file ARMSubtarget.h.
References llvm::Triple::isWatchABI(), and TargetTriple.
Referenced by llvm::ARMTargetLowering::ARMTargetLowering(), and useStride4VFPs().
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Definition at line 361 of file ARMSubtarget.h.
References llvm::Triple::isWatchOS(), and TargetTriple.
Referenced by llvm::ARMTargetLowering::ARMTargetLowering().
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Definition at line 367 of file ARMSubtarget.h.
References llvm::Triple::isOSWindows(), and TargetTriple.
Referenced by llvm::ARMTargetLowering::ARMTargetLowering(), llvm::ARMFrameLowering::determineCalleeSaves(), llvm::ARMAsmPrinter::emitInstruction(), llvm::ARMFrameLowering::emitPrologue(), getDivRemArgList(), getFramePointerReg(), isTargetAEABI(), isTargetGNUAEABI(), isTargetMuslAEABI(), isXRaySupported(), llvm::ARMTargetLowering::LowerOperation(), llvm::ARMTargetLowering::preferredShiftLegalizationStrategy(), llvm::ARMTargetLowering::ReplaceNodeResults(), and useMovt().
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Definition at line 419 of file ARMSubtarget.h.
References isThumb().
Referenced by llvm::ARMTargetLowering::AdjustInstrPostInstrSelection(), llvm::ARMBaseInstrInfo::areLoadsFromSameBasePtr(), llvm::ARMTargetLowering::ARMTargetLowering(), attachMEMCPYScratchRegs(), llvm::ThumbRegisterInfo::eliminateFrameIndex(), llvm::ARMAsmPrinter::emitJumpTableTBInst(), llvm::ThumbRegisterInfo::emitLoadConstPool(), llvm::ARMSelectionDAGInfo::EmitTargetCodeForMemcpy(), enablePostRAMachineScheduler(), enablePostRAScheduler(), llvm::ARMTTIImpl::getArithmeticInstrCost(), getGPRAllocationOrder(), llvm::ThumbRegisterInfo::getLargestLegalSuperClass(), llvm::ThumbRegisterInfo::getPointerRegClass(), llvm::ARMTargetLowering::getPostIndexedAddressParts(), llvm::ARMTargetLowering::getPreIndexedAddressParts(), llvm::ARMTargetLowering::getRegForInlineAsmConstraint(), llvm::ARMBaseRegisterInfo::getSjLjDispatchPreservedMask(), llvm::ARMTTIImpl::getUnrollingPreferences(), llvm::ARMTargetLowering::isDesirableToCommuteWithShift(), isLegalAddressImmediate(), llvm::ARMTargetLowering::isLegalAddressingMode(), LowerADDSUBSAT(), llvm::ARMTargetLowering::LowerAsmOperandForConstraint(), llvm::ARMCallLowering::lowerCall(), LowerPREFETCH(), LowerSTORE(), PerformAddcSubcCombine(), PerformADDECombine(), PerformAddeSubeCombine(), PerformANDCombine(), llvm::ARMTargetLowering::PerformCMOVCombine(), PerformMULCombine(), PerformORCombine(), PerformORCombineToBFI(), PerformXORCombine(), llvm::ARMTargetLowering::preferIncOfAddToSubOfNot(), llvm::ThumbRegisterInfo::resolveFrameIndex(), llvm::ThumbRegisterInfo::rewriteFrameIndex(), llvm::ARMTargetLowering::shouldFoldConstantShiftPairToMask(), llvm::ARMBaseInstrInfo::shouldScheduleLoadsNear(), splitFramePushPop(), useFastISel(), and llvm::ThumbRegisterInfo::useFPForScavengingIndex().
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Definition at line 420 of file ARMSubtarget.h.
References isThumb().
Referenced by llvm::ARMTargetLowering::ARMTargetLowering(), llvm::ARMBaseInstrInfo::copyPhysReg(), llvm::ARMBaseInstrInfo::CreateTargetPostRAHazardRecognizer(), llvm::ARMTargetLowering::EmitInstrWithCustomInserter(), llvm::ARMBaseInstrInfo::extraSizeToPredicateInstructions(), getGPRAllocationOrder(), llvm::ARMTTIImpl::getIntImmCost(), llvm::ARMTTIImpl::getIntImmCostInst(), llvm::ARMTargetLowering::getPostIndexedAddressParts(), llvm::ARMTTIImpl::getPreferredAddressingMode(), llvm::ARMTargetLowering::getPreIndexedAddressParts(), llvm::ARMTTIImpl::hasArmWideBranch(), ignoreCSRForAllocationOrder(), llvm::ARMTargetLowering::isLegalAddImmediate(), isLegalAddressImmediate(), llvm::ARMTargetLowering::isLegalAddressingMode(), llvm::ARMTargetLowering::isLegalICmpImmediate(), llvm::ARMTargetLowering::isMaskAndCmp0FoldingBeneficial(), llvm::ARMBaseInstrInfo::isProfitableToIfCvt(), llvm::ARMTargetLowering::LowerAsmOperandForConstraint(), LowerPREFETCH(), PerformMinMaxToSatCombine(), and llvm::ARMBaseInstrInfo::predictBranchSizeForIfCvt().
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Definition at line 139 of file ARMSubtarget.cpp.
References hasARMOps(), and isTargetWindows().
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
Definition of function is auto generated by tblgen.
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Definition at line 458 of file ARMSubtarget.h.
References RestrictIT.
Referenced by llvm::ARMBaseInstrInfo::extraSizeToPredicateInstructions(), and llvm::ARMBaseInstrInfo::isPredicable().
bool ARMSubtarget::splitFramePointerPush | ( | const MachineFunction & | MF | ) | const |
Definition at line 494 of file ARMSubtarget.cpp.
References F, llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getFunction(), llvm::TargetMachine::getMCAsmInfo(), getRegisterInfo(), llvm::MachineFunction::getTarget(), llvm::MachineFrameInfo::hasVarSizedObjects(), and llvm::MCAsmInfo::usesWindowsCFI().
Referenced by llvm::ARMFrameLowering::emitEpilogue(), llvm::ARMFrameLowering::emitPrologue(), llvm::ARMBaseRegisterInfo::getCalleeSavedRegs(), getMaxFPOffset(), llvm::ARMFrameLowering::restoreCalleeSavedRegisters(), and llvm::ARMFrameLowering::spillCalleeSavedRegisters().
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Returns true if the frame setup is split into two separate pushes (first r0-r7,lr then r8-r11), principally so that the frame pointer is adjacent to lr.
This is always required on Thumb1-only targets, as the push and pop instructions can't access the high registers.
Definition at line 440 of file ARMSubtarget.h.
References llvm::TargetOptions::DisableFramePointerElim(), getFramePointerReg(), llvm::MachineFunction::getInfo(), llvm::MachineFunction::getTarget(), isThumb1Only(), llvm::TargetMachine::Options, and llvm::ARMFunctionInfo::shouldSignReturnAddress().
Referenced by llvm::ARMFrameLowering::determineCalleeSaves(), llvm::ARMFrameLowering::emitPrologue(), llvm::Thumb1FrameLowering::emitPrologue(), and llvm::ARMBaseRegisterInfo::getCalleeSavedRegs().
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Definition at line 454 of file ARMSubtarget.h.
References SupportsTailCall.
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Enable use of alias analysis during code generation (during MI scheduling, DAGCombine, etc.).
Definition at line 484 of file ARMSubtarget.h.
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Definition at line 401 of file ARMSubtarget.cpp.
bool ARMSubtarget::useFastISel | ( | ) | const |
True if fast-isel is used.
Definition at line 437 of file ARMSubtarget.cpp.
References llvm::TargetOptions::EnableFastISel, ForceFastISel, isTargetLinux(), isTargetMachO(), isTargetNaCl(), isThumb(), isThumb1Only(), llvm::TargetMachine::Options, and TM.
Referenced by llvm::ARM::createFastISel().
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Definition at line 341 of file ARMSubtarget.h.
References hasVFP4Base(), and isTargetDarwin().
Referenced by useFPVFMx16(), and useFPVFMx64().
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Definition at line 344 of file ARMSubtarget.h.
References useFPVFMx().
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Definition at line 345 of file ARMSubtarget.h.
References useFPVFMx().
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Definition at line 340 of file ARMSubtarget.h.
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Definition at line 417 of file ARMSubtarget.h.
Referenced by enableMachinePipeliner().
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Definition at line 416 of file ARMSubtarget.h.
Referenced by enableMachineScheduler().
bool ARMSubtarget::useMovt | ( | ) | const |
Definition at line 429 of file ARMSubtarget.cpp.
References isTargetWindows(), and OptMinSize.
Referenced by llvm::ConstantMaterializationCost().
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Definition at line 339 of file ARMSubtarget.h.
References UseMulOps.
Referenced by AddCombineTo64bitMLAL().
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Definition at line 326 of file ARMSubtarget.h.
Referenced by llvm::ARMTargetLowering::ARMTargetLowering(), and llvm::ARMTargetLowering::findRepresentativeClass().
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Definition at line 346 of file ARMSubtarget.h.
References UseSjLjEH.
Referenced by llvm::ARMTargetLowering::ARMTargetLowering(), llvm::ARMTargetLowering::getExceptionPointerRegister(), and llvm::ARMTargetLowering::getExceptionSelectorRegister().
bool ARMSubtarget::useStride4VFPs | ( | ) | const |
Definition at line 421 of file ARMSubtarget.cpp.
References isTargetWatchABI(), and OptMinSize.
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ARMArch - ARM architecture.
Definition at line 163 of file ARMSubtarget.h.
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ARMProcClass - ARM processor class: None, AClass, RClass or MClass.
Definition at line 160 of file ARMSubtarget.h.
Referenced by isAClass(), isMClass(), and isRClass().
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ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.
Definition at line 157 of file ARMSubtarget.h.
Referenced by isCortexA15(), isCortexA5(), isCortexA7(), isCortexA8(), isCortexA9(), isCortexM3(), isCortexM7(), isCortexR5(), isKrait(), and isSwift().
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CPUString - String name of used CPU.
Definition at line 186 of file ARMSubtarget.h.
Referenced by getCPUString().
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Selected instruction itineraries (one entry per itinerary class.)
Definition at line 223 of file ARMSubtarget.h.
Referenced by getInstrItineraryData().
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IsLittle - The target is Little Endian.
Definition at line 214 of file ARMSubtarget.h.
Referenced by isLittle().
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What kind of timing do load multiple/store multiple have (double issue, single issue etc).
Definition at line 195 of file ARMSubtarget.h.
Referenced by getLdStMultipleTiming().
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Definition at line 188 of file ARMSubtarget.h.
Referenced by getMaxInterleaveFactor().
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The cost factor for MVE instructions, representing the multiple beats an.
Definition at line 207 of file ARMSubtarget.h.
Referenced by getMVEVectorCostFactor().
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Options passed via command line that could influence the target.
Definition at line 226 of file ARMSubtarget.h.
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OptMinSize - True if we're optimising for minimum code size, equal to the function attribute.
Definition at line 211 of file ARMSubtarget.h.
Referenced by hasMinSize(), useMovt(), and useStride4VFPs().
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Clearance before partial register updates (in number of instructions)
Definition at line 191 of file ARMSubtarget.h.
Referenced by getPartialUpdateClearance().
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What alignment is preferred for loop bodies, in log2(bytes).
Definition at line 202 of file ARMSubtarget.h.
Referenced by getPrefLoopLogAlignment().
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The adjustment that we need to apply to get the operand latency from the operand cycle returned by the itinerary data for pre-ISel operands.
Definition at line 199 of file ARMSubtarget.h.
Referenced by getPreISelOperandLatencyAdjustment().
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RestrictIT - If true, the subtarget disallows generation of complex IT blocks.
Definition at line 176 of file ARMSubtarget.h.
Referenced by restrictIT().
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SchedModel - Processor specific instruction costs.
Definition at line 220 of file ARMSubtarget.h.
Referenced by getMispredictionPenalty().
stackAlignment - The minimum alignment known to hold of the stack frame on entry to the function and which must be maintained by every function.
Definition at line 183 of file ARMSubtarget.h.
Referenced by getStackAlignment().
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SupportsTailCall - True if the OS supports tail call.
The dynamic linker must be able to synthesize call stubs for interworking between ARM and Thumb.
Definition at line 172 of file ARMSubtarget.h.
Referenced by supportsTailCall().
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TargetTriple - What processor and OS we're targeting.
Definition at line 217 of file ARMSubtarget.h.
Referenced by getTargetTriple(), isTargetAEABI(), isTargetAndroid(), isTargetCOFF(), isTargetDarwin(), isTargetDriverKit(), isTargetEHABICompatible(), isTargetELF(), isTargetGNUAEABI(), isTargetIOS(), isTargetLinux(), isTargetMachO(), isTargetMuslAEABI(), isTargetNaCl(), isTargetNetBSD(), isTargetWatchABI(), isTargetWatchOS(), and isTargetWindows().
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Definition at line 228 of file ARMSubtarget.h.
Referenced by ARMSubtarget(), isAAPCS16_ABI(), isAAPCS_ABI(), isAPCS_ABI(), isGVIndirectSymbol(), isGVInGOT(), isROPI(), isRWPI(), isTargetHardFloat(), and useFastISel().
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UseMulOps - True if non-microcoded fused integer multiply-add and multiply-subtract instructions should be used.
Definition at line 167 of file ARMSubtarget.h.
Referenced by useMulOps().
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UseSjLjEH - If true, the target uses SjLj exception handling (e.g. iOS).
Definition at line 179 of file ARMSubtarget.h.
Referenced by useSjLjEH().