LLVM  16.0.0git
ARMSubtarget.h
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1 //===-- ARMSubtarget.h - Define Subtarget for the ARM ----------*- C++ -*--===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file declares the ARM specific subclass of TargetSubtargetInfo.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H
14 #define LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H
15 
16 #include "ARMBaseInstrInfo.h"
17 #include "ARMBaseRegisterInfo.h"
18 #include "ARMConstantPoolValue.h"
19 #include "ARMFrameLowering.h"
20 #include "ARMISelLowering.h"
21 #include "ARMMachineFunctionInfo.h"
22 #include "ARMSelectionDAGInfo.h"
23 #include "llvm/ADT/Triple.h"
32 #include "llvm/MC/MCSchedule.h"
35 #include <memory>
36 #include <string>
37 
38 #define GET_SUBTARGETINFO_HEADER
39 #include "ARMGenSubtargetInfo.inc"
40 
41 namespace llvm {
42 
43 class ARMBaseTargetMachine;
44 class GlobalValue;
45 class StringRef;
46 
48 protected:
51 
88  };
91 
95  };
96  enum ARMArchEnum {
131  };
132 
133 public:
134  /// What kind of timing do load multiple/store multiple instructions have.
136  /// Can load/store 2 registers/cycle.
138  /// Can load/store 2 registers/cycle, but needs an extra cycle if the access
139  /// is not 64-bit aligned.
141  /// Can load/store 1 register/cycle.
143  /// Can load/store 1 register/cycle, but needs an extra cycle for address
144  /// computation and potentially also for register writeback.
146  };
147 
148 protected:
149 // Bool members corresponding to the SubtargetFeatures defined in tablegen
150 #define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \
151  bool ATTRIBUTE = DEFAULT;
152 #include "ARMGenSubtargetInfo.inc"
153 
154  /// ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.
156 
157  /// ARMProcClass - ARM processor class: None, AClass, RClass or MClass.
159 
160  /// ARMArch - ARM architecture
162 
163  /// UseMulOps - True if non-microcoded fused integer multiply-add and
164  /// multiply-subtract instructions should be used.
165  bool UseMulOps = false;
166 
167  /// SupportsTailCall - True if the OS supports tail call. The dynamic linker
168  /// must be able to synthesize call stubs for interworking between ARM and
169  /// Thumb.
170  bool SupportsTailCall = false;
171 
172  /// RestrictIT - If true, the subtarget disallows generation of complex IT
173  /// blocks.
174  bool RestrictIT = false;
175 
176  /// UseSjLjEH - If true, the target uses SjLj exception handling (e.g. iOS).
177  bool UseSjLjEH = false;
178 
179  /// stackAlignment - The minimum alignment known to hold of the stack frame on
180  /// entry to the function and which must be maintained by every function.
182 
183  /// CPUString - String name of used CPU.
184  std::string CPUString;
185 
186  unsigned MaxInterleaveFactor = 1;
187 
188  /// Clearance before partial register updates (in number of instructions)
190 
191  /// What kind of timing do load multiple/store multiple have (double issue,
192  /// single issue etc).
194 
195  /// The adjustment that we need to apply to get the operand latency from the
196  /// operand cycle returned by the itinerary data for pre-ISel operands.
198 
199  /// What alignment is preferred for loop bodies, in log2(bytes).
200  unsigned PrefLoopLogAlignment = 0;
201 
202  /// The cost factor for MVE instructions, representing the multiple beats an
203  // instruction can take. The default is 2, (set in initSubtargetFeatures so
204  // that we can use subtarget features less than 2).
205  unsigned MVEVectorCostFactor = 0;
206 
207  /// OptMinSize - True if we're optimising for minimum code size, equal to
208  /// the function attribute.
209  bool OptMinSize = false;
210 
211  /// IsLittle - The target is Little Endian
212  bool IsLittle;
213 
214  /// TargetTriple - What processor and OS we're targeting.
216 
217  /// SchedModel - Processor specific instruction costs.
219 
220  /// Selected instruction itineraries (one entry per itinerary class.)
222 
223  /// Options passed via command line that could influence the target
225 
227 
228 public:
229  /// This constructor initializes the data members to match that
230  /// of the specified triple.
231  ///
232  ARMSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS,
233  const ARMBaseTargetMachine &TM, bool IsLittle,
234  bool MinSize = false);
235 
236  /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
237  /// that still makes it profitable to inline the call.
238  unsigned getMaxInlineSizeThreshold() const {
239  return 64;
240  }
241 
242  /// getMaxMemcpyTPInlineSizeThreshold - Returns the maximum size
243  /// that still makes it profitable to inline a llvm.memcpy as a Tail
244  /// Predicated loop.
245  /// This threshold should only be used for constant size inputs.
246  unsigned getMaxMemcpyTPInlineSizeThreshold() const { return 128; }
247 
248  /// ParseSubtargetFeatures - Parses features string setting specified
249  /// subtarget options. Definition of function is auto generated by tblgen.
251 
252  /// initializeSubtargetDependencies - Initializes using a CPU and feature string
253  /// so that we can use initializer lists for subtarget initialization.
255 
256  const ARMSelectionDAGInfo *getSelectionDAGInfo() const override {
257  return &TSInfo;
258  }
259 
260  const ARMBaseInstrInfo *getInstrInfo() const override {
261  return InstrInfo.get();
262  }
263 
264  const ARMTargetLowering *getTargetLowering() const override {
265  return &TLInfo;
266  }
267 
268  const ARMFrameLowering *getFrameLowering() const override {
269  return FrameLowering.get();
270  }
271 
272  const ARMBaseRegisterInfo *getRegisterInfo() const override {
273  return &InstrInfo->getRegisterInfo();
274  }
275 
276  const CallLowering *getCallLowering() const override;
278  const LegalizerInfo *getLegalizerInfo() const override;
279  const RegisterBankInfo *getRegBankInfo() const override;
280 
281 private:
282  ARMSelectionDAGInfo TSInfo;
283  // Either Thumb1FrameLowering or ARMFrameLowering.
284  std::unique_ptr<ARMFrameLowering> FrameLowering;
285  // Either Thumb1InstrInfo or Thumb2InstrInfo.
286  std::unique_ptr<ARMBaseInstrInfo> InstrInfo;
287  ARMTargetLowering TLInfo;
288 
289  /// GlobalISel related APIs.
290  std::unique_ptr<CallLowering> CallLoweringInfo;
291  std::unique_ptr<InstructionSelector> InstSelector;
292  std::unique_ptr<LegalizerInfo> Legalizer;
293  std::unique_ptr<RegisterBankInfo> RegBankInfo;
294 
295  void initializeEnvironment();
296  void initSubtargetFeatures(StringRef CPU, StringRef FS);
297  ARMFrameLowering *initializeFrameLowering(StringRef CPU, StringRef FS);
298 
299  std::bitset<8> CoprocCDE = {};
300 public:
301 // Getters for SubtargetFeatures defined in tablegen
302 #define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \
303  bool GETTER() const { return ATTRIBUTE; }
304 #include "ARMGenSubtargetInfo.inc"
305 
306  void computeIssueWidth();
307 
308  /// @{
309  /// These functions are obsolete, please consider adding subtarget features
310  /// or properties instead of calling them.
311  bool isCortexA5() const { return ARMProcFamily == CortexA5; }
312  bool isCortexA7() const { return ARMProcFamily == CortexA7; }
313  bool isCortexA8() const { return ARMProcFamily == CortexA8; }
314  bool isCortexA9() const { return ARMProcFamily == CortexA9; }
315  bool isCortexA15() const { return ARMProcFamily == CortexA15; }
316  bool isSwift() const { return ARMProcFamily == Swift; }
317  bool isCortexM3() const { return ARMProcFamily == CortexM3; }
318  bool isCortexM7() const { return ARMProcFamily == CortexM7; }
319  bool isLikeA9() const { return isCortexA9() || isCortexA15() || isKrait(); }
320  bool isCortexR5() const { return ARMProcFamily == CortexR5; }
321  bool isKrait() const { return ARMProcFamily == Krait; }
322  /// @}
323 
324  bool hasARMOps() const { return !NoARM; }
325 
327  return hasNEON() && hasNEONForFP();
328  }
329 
330  bool hasVFP2Base() const { return hasVFPv2SP(); }
331  bool hasVFP3Base() const { return hasVFPv3D16SP(); }
332  bool hasVFP4Base() const { return hasVFPv4D16SP(); }
333  bool hasFPARMv8Base() const { return hasFPARMv8D16SP(); }
334 
335  bool hasAnyDataBarrier() const {
336  return HasDataBarrier || (hasV6Ops() && !isThumb());
337  }
338 
339  bool useMulOps() const { return UseMulOps; }
340  bool useFPVMLx() const { return !SlowFPVMLx; }
341  bool useFPVFMx() const {
342  return !isTargetDarwin() && hasVFP4Base() && !SlowFPVFMx;
343  }
344  bool useFPVFMx16() const { return useFPVFMx() && hasFullFP16(); }
345  bool useFPVFMx64() const { return useFPVFMx() && hasFP64(); }
346  bool useSjLjEH() const { return UseSjLjEH; }
347  bool hasBaseDSP() const {
348  if (isThumb())
349  return hasDSP();
350  else
351  return hasV5TEOps();
352  }
353 
354  /// Return true if the CPU supports any kind of instruction fusion.
355  bool hasFusion() const { return hasFuseAES() || hasFuseLiterals(); }
356 
357  const Triple &getTargetTriple() const { return TargetTriple; }
358 
359  bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
360  bool isTargetIOS() const { return TargetTriple.isiOS(); }
361  bool isTargetWatchOS() const { return TargetTriple.isWatchOS(); }
362  bool isTargetWatchABI() const { return TargetTriple.isWatchABI(); }
363  bool isTargetDriverKit() const { return TargetTriple.isDriverKit(); }
364  bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
365  bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
366  bool isTargetNetBSD() const { return TargetTriple.isOSNetBSD(); }
367  bool isTargetWindows() const { return TargetTriple.isOSWindows(); }
368 
369  bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
370  bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
371  bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
372 
373  // ARM EABI is the bare-metal EABI described in ARM ABI documents and
374  // can be accessed via -target arm-none-eabi. This is NOT GNUEABI.
375  // FIXME: Add a flag for bare-metal for that target and set Triple::EABI
376  // even for GNUEABI, so we can make a distinction here and still conform to
377  // the EABI on GNU (and Android) mode. This requires change in Clang, too.
378  // FIXME: The Darwin exception is temporary, while we move users to
379  // "*-*-*-macho" triples as quickly as possible.
380  bool isTargetAEABI() const {
384  }
385  bool isTargetGNUAEABI() const {
389  }
390  bool isTargetMuslAEABI() const {
394  }
395 
396  // ARM Targets that support EHABI exception handling standard
397  // Darwin uses SjLj. Other targets might need more checks.
398  bool isTargetEHABICompatible() const {
400  }
401 
402  bool isTargetHardFloat() const;
403 
404  bool isTargetAndroid() const { return TargetTriple.isAndroid(); }
405 
406  bool isXRaySupported() const override;
407 
408  bool isAPCS_ABI() const;
409  bool isAAPCS_ABI() const;
410  bool isAAPCS16_ABI() const;
411 
412  bool isROPI() const;
413  bool isRWPI() const;
414 
415  bool useMachineScheduler() const { return UseMISched; }
416  bool useMachinePipeliner() const { return UseMIPipeliner; }
417  bool hasMinSize() const { return OptMinSize; }
418  bool isThumb1Only() const { return isThumb() && !hasThumb2(); }
419  bool isThumb2() const { return isThumb() && hasThumb2(); }
420  bool isMClass() const { return ARMProcClass == MClass; }
421  bool isRClass() const { return ARMProcClass == RClass; }
422  bool isAClass() const { return ARMProcClass == AClass; }
423 
424  bool isR9Reserved() const {
425  return isTargetMachO() ? (ReserveR9 || !HasV6Ops) : ReserveR9;
426  }
427 
429  if (isTargetDarwin() ||
430  (!isTargetWindows() && isThumb() && !createAAPCSFrameChain()))
431  return ARM::R7;
432  return ARM::R11;
433  }
434 
435  /// Returns true if the frame setup is split into two separate pushes (first
436  /// r0-r7,lr then r8-r11), principally so that the frame pointer is adjacent
437  /// to lr. This is always required on Thumb1-only targets, as the push and
438  /// pop instructions can't access the high registers.
439  bool splitFramePushPop(const MachineFunction &MF) const {
441  return true;
442  return (getFramePointerReg() == ARM::R7 &&
444  isThumb1Only();
445  }
446 
447  bool splitFramePointerPush(const MachineFunction &MF) const;
448 
449  bool useStride4VFPs() const;
450 
451  bool useMovt() const;
452 
453  bool supportsTailCall() const { return SupportsTailCall; }
454 
455  bool allowsUnalignedMem() const { return !StrictAlign; }
456 
457  bool restrictIT() const { return RestrictIT; }
458 
459  const std::string & getCPUString() const { return CPUString; }
460 
461  bool isLittle() const { return IsLittle; }
462 
463  unsigned getMispredictionPenalty() const;
464 
465  /// Returns true if machine scheduler should be enabled.
466  bool enableMachineScheduler() const override;
467 
468  /// Returns true if machine pipeliner should be enabled.
469  bool enableMachinePipeliner() const override;
470  bool useDFAforSMS() const override;
471 
472  /// True for some subtargets at > -O0.
473  bool enablePostRAScheduler() const override;
474 
475  /// True for some subtargets at > -O0.
476  bool enablePostRAMachineScheduler() const override;
477 
478  /// Check whether this subtarget wants to use subregister liveness.
479  bool enableSubRegLiveness() const override;
480 
481  /// Enable use of alias analysis during code generation (during MI
482  /// scheduling, DAGCombine, etc.).
483  bool useAA() const override { return true; }
484 
485  /// getInstrItins - Return the instruction itineraries based on subtarget
486  /// selection.
487  const InstrItineraryData *getInstrItineraryData() const override {
488  return &InstrItins;
489  }
490 
491  /// getStackAlignment - Returns the minimum alignment known to hold of the
492  /// stack frame on entry to the function and which must be maintained by every
493  /// function for this subtarget.
495 
496  unsigned getMaxInterleaveFactor() const { return MaxInterleaveFactor; }
497 
499 
501  return LdStMultipleTiming;
502  }
503 
506  }
507 
508  /// True if the GV will be accessed via an indirect symbol.
509  bool isGVIndirectSymbol(const GlobalValue *GV) const;
510 
511  /// Returns the constant pool modifier needed to access the GV.
512  bool isGVInGOT(const GlobalValue *GV) const;
513 
514  /// True if fast-isel is used.
515  bool useFastISel() const;
516 
517  /// Returns the correct return opcode for the current feature set.
518  /// Use BX if available to allow mixing thumb/arm code, but fall back
519  /// to plain mov pc,lr on ARMv4.
520  unsigned getReturnOpcode() const {
521  if (isThumb())
522  return ARM::tBX_RET;
523  if (hasV4TOps())
524  return ARM::BX_RET;
525  return ARM::MOVPCLR;
526  }
527 
528  /// Allow movt+movw for PIC global address calculation.
529  /// ELF does not have GOT relocations for movt+movw.
530  /// ROPI does not use GOT.
532  return isROPI() || !isTargetELF();
533  }
534 
535  unsigned getPrefLoopLogAlignment() const { return PrefLoopLogAlignment; }
536 
537  unsigned
540  return 1;
541  return MVEVectorCostFactor;
542  }
543 
545  unsigned PhysReg) const override;
546  unsigned getGPRAllocationOrder(const MachineFunction &MF) const;
547 };
548 
549 } // end namespace llvm
550 
551 #endif // LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H
llvm::ARMSubtarget::SupportsTailCall
bool SupportsTailCall
SupportsTailCall - True if the OS supports tail call.
Definition: ARMSubtarget.h:170
llvm::ARMSubtarget::CortexA17
@ CortexA17
Definition: ARMSubtarget.h:54
llvm::ARMSubtarget::UseSjLjEH
bool UseSjLjEH
UseSjLjEH - If true, the target uses SjLj exception handling (e.g. iOS).
Definition: ARMSubtarget.h:177
llvm::ARMSubtarget::useSjLjEH
bool useSjLjEH() const
Definition: ARMSubtarget.h:346
llvm::ARMSubtarget::hasBaseDSP
bool hasBaseDSP() const
Definition: ARMSubtarget.h:347
llvm::ARMSubtarget::TM
const ARMBaseTargetMachine & TM
Definition: ARMSubtarget.h:226
llvm::ARMSubtarget::CortexR7
@ CortexR7
Definition: ARMSubtarget.h:78
llvm::ARMSubtarget::enableSubRegLiveness
bool enableSubRegLiveness() const override
Check whether this subtarget wants to use subregister liveness.
Definition: ARMSubtarget.cpp:388
llvm::ARMFunctionInfo
ARMFunctionInfo - This class is derived from MachineFunctionInfo and contains private ARM-specific in...
Definition: ARMMachineFunctionInfo.h:27
llvm::TargetTransformInfo::TargetCostKind
TargetCostKind
The kind of cost model.
Definition: TargetTransformInfo.h:217
llvm::ARMBaseTargetMachine
Definition: ARMTargetMachine.h:27
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::ARMSubtarget::ARMProcFamilyEnum
ARMProcFamilyEnum
Definition: ARMSubtarget.h:49
llvm::ARMSubtarget::hasFusion
bool hasFusion() const
Return true if the CPU supports any kind of instruction fusion.
Definition: ARMSubtarget.h:355
llvm::ARMSubtarget::ARMv9a
@ ARMv9a
Definition: ARMSubtarget.h:127
llvm::ARMSubtarget::hasARMOps
bool hasARMOps() const
Definition: ARMSubtarget.h:324
llvm::ARMSubtarget::isTargetAndroid
bool isTargetAndroid() const
Definition: ARMSubtarget.h:404
llvm::ARMSubtarget::computeIssueWidth
void computeIssueWidth()
llvm::ARMSubtarget::getLegalizerInfo
const LegalizerInfo * getLegalizerInfo() const override
Definition: ARMSubtarget.cpp:132
llvm::ARMSubtarget::enableMachineScheduler
bool enableMachineScheduler() const override
Returns true if machine scheduler should be enabled.
Definition: ARMSubtarget.cpp:375
CallLowering.h
llvm::ARMSubtarget::CortexA57
@ CortexA57
Definition: ARMSubtarget.h:60
ARMGenSubtargetInfo
llvm::TargetOptions
Definition: TargetOptions.h:124
llvm::Triple::isOSBinFormatCOFF
bool isOSBinFormatCOFF() const
Tests whether the OS uses the COFF binary format.
Definition: Triple.h:668
llvm::ARMSubtarget
Definition: ARMSubtarget.h:47
llvm::ARMSubtarget::ARMv7m
@ ARMv7m
Definition: ARMSubtarget.h:111
llvm::ARMSubtarget::CortexX1C
@ CortexX1C
Definition: ARMSubtarget.h:80
llvm::ARMSubtarget::isAClass
bool isAClass() const
Definition: ARMSubtarget.h:422
llvm::ARMSubtarget::isTargetWatchOS
bool isTargetWatchOS() const
Definition: ARMSubtarget.h:361
llvm::ARMSubtarget::getMispredictionPenalty
unsigned getMispredictionPenalty() const
Definition: ARMSubtarget.cpp:371
llvm::ARMSubtarget::getPartialUpdateClearance
unsigned getPartialUpdateClearance() const
Definition: ARMSubtarget.h:498
llvm::ARMSubtarget::isCortexM3
bool isCortexM3() const
Definition: ARMSubtarget.h:317
llvm::ARMSubtarget::hasFPARMv8Base
bool hasFPARMv8Base() const
Definition: ARMSubtarget.h:333
llvm::ARMSubtarget::ARMProcFamily
ARMProcFamilyEnum ARMProcFamily
ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.
Definition: ARMSubtarget.h:155
llvm::Triple::MuslEABIHF
@ MuslEABIHF
Definition: Triple.h:241
ARMMachineFunctionInfo.h
RegisterBankInfo.h
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
llvm::ARMSubtarget::useFPVFMx
bool useFPVFMx() const
Definition: ARMSubtarget.h:341
llvm::TargetTransformInfo::TCK_CodeSize
@ TCK_CodeSize
Instruction code size.
Definition: TargetTransformInfo.h:220
llvm::ARMSubtarget::getTargetTriple
const Triple & getTargetTriple() const
Definition: ARMSubtarget.h:357
llvm::ARMSubtarget::isRWPI
bool isRWPI() const
Definition: ARMSubtarget.cpp:347
llvm::Triple::isDriverKit
bool isDriverKit() const
Is this an Apple DriverKit triple.
Definition: Triple.h:504
llvm::ARMSubtarget::ParseSubtargetFeatures
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
llvm::ARMSubtarget::ARMv7r
@ ARMv7r
Definition: ARMSubtarget.h:112
llvm::ARMSubtarget::getPreISelOperandLatencyAdjustment
int getPreISelOperandLatencyAdjustment() const
Definition: ARMSubtarget.h:504
llvm::ARMTargetLowering
Definition: ARMISelLowering.h:390
llvm::ARMSubtarget::getInstrItineraryData
const InstrItineraryData * getInstrItineraryData() const override
getInstrItins - Return the instruction itineraries based on subtarget selection.
Definition: ARMSubtarget.h:487
llvm::ARMSubtarget::isTargetDriverKit
bool isTargetDriverKit() const
Definition: ARMSubtarget.h:363
llvm::ARMSubtarget::getTargetLowering
const ARMTargetLowering * getTargetLowering() const override
Definition: ARMSubtarget.h:264
llvm::ARMSubtarget::ARMv83a
@ ARMv83a
Definition: ARMSubtarget.h:116
llvm::ARMSubtarget::getInstrInfo
const ARMBaseInstrInfo * getInstrInfo() const override
Definition: ARMSubtarget.h:260
llvm::ARMSubtarget::CortexM7
@ CortexM7
Definition: ARMSubtarget.h:73
llvm::Triple::isOSLinux
bool isOSLinux() const
Tests whether the OS is Linux.
Definition: Triple.h:626
llvm::ARMSubtarget::getSelectionDAGInfo
const ARMSelectionDAGInfo * getSelectionDAGInfo() const override
Definition: ARMSubtarget.h:256
llvm::ARMSubtarget::ARMv7a
@ ARMv7a
Definition: ARMSubtarget.h:109
llvm::ARMSubtarget::getStackAlignment
Align getStackAlignment() const
getStackAlignment - Returns the minimum alignment known to hold of the stack frame on entry to the fu...
Definition: ARMSubtarget.h:494
llvm::ARMSubtarget::isTargetLinux
bool isTargetLinux() const
Definition: ARMSubtarget.h:364
llvm::ARMSubtarget::supportsTailCall
bool supportsTailCall() const
Definition: ARMSubtarget.h:453
llvm::ARMSubtarget::getMaxInlineSizeThreshold
unsigned getMaxInlineSizeThreshold() const
getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size that still makes it profitable t...
Definition: ARMSubtarget.h:238
llvm::ARMSubtarget::ARMLdStMultipleTiming
ARMLdStMultipleTiming
What kind of timing do load multiple/store multiple instructions have.
Definition: ARMSubtarget.h:135
LegalizerInfo.h
llvm::ARMSubtarget::RClass
@ RClass
Definition: ARMSubtarget.h:94
llvm::ARMSubtarget::Kryo
@ Kryo
Definition: ARMSubtarget.h:83
llvm::ARMSubtarget::isTargetWatchABI
bool isTargetWatchABI() const
Definition: ARMSubtarget.h:362
llvm::Triple::GNUEABI
@ GNUEABI
Definition: Triple.h:231
llvm::ARMSubtarget::ARMv92a
@ ARMv92a
Definition: ARMSubtarget.h:129
llvm::ARMSubtarget::ARMv93a
@ ARMv93a
Definition: ARMSubtarget.h:130
llvm::ARMSubtarget::OptMinSize
bool OptMinSize
OptMinSize - True if we're optimising for minimum code size, equal to the function attribute.
Definition: ARMSubtarget.h:209
llvm::ARMSubtarget::ARMv84a
@ ARMv84a
Definition: ARMSubtarget.h:117
llvm::ARMSubtarget::NeoverseN1
@ NeoverseN1
Definition: ARMSubtarget.h:84
llvm::ARMSubtarget::splitFramePushPop
bool splitFramePushPop(const MachineFunction &MF) const
Returns true if the frame setup is split into two separate pushes (first r0-r7,lr then r8-r11),...
Definition: ARMSubtarget.h:439
llvm::ARMSubtarget::isTargetMuslAEABI
bool isTargetMuslAEABI() const
Definition: ARMSubtarget.h:390
ARMConstantPoolValue.h
llvm::ARMSubtarget::ARMv6sm
@ ARMv6sm
Definition: ARMSubtarget.h:107
llvm::ARMSubtarget::ARMv7ve
@ ARMv7ve
Definition: ARMSubtarget.h:113
llvm::Triple::isAndroid
bool isAndroid() const
Tests whether the target is Android.
Definition: Triple.h:713
MCInstrItineraries.h
llvm::ARMSubtarget::CortexA73
@ CortexA73
Definition: ARMSubtarget.h:63
llvm::Triple::isOSBinFormatELF
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:663
llvm::ARMSubtarget::ARMv6
@ ARMv6
Definition: ARMSubtarget.h:103
TargetMachine.h
llvm::ARMSubtarget::CortexR5
@ CortexR5
Definition: ARMSubtarget.h:76
llvm::ARMSubtarget::NeoverseN2
@ NeoverseN2
Definition: ARMSubtarget.h:85
llvm::ARMSubtarget::AClass
@ AClass
Definition: ARMSubtarget.h:92
llvm::ARMSubtarget::IsLittle
bool IsLittle
IsLittle - The target is Little Endian.
Definition: ARMSubtarget.h:212
llvm::ARMSubtarget::useAA
bool useAA() const override
Enable use of alias analysis during code generation (during MI scheduling, DAGCombine,...
Definition: ARMSubtarget.h:483
llvm::ARMSubtarget::useFPVMLx
bool useFPVMLx() const
Definition: ARMSubtarget.h:340
llvm::ARMSubtarget::isLikeA9
bool isLikeA9() const
Definition: ARMSubtarget.h:319
llvm::ARMSubtarget::SchedModel
MCSchedModel SchedModel
SchedModel - Processor specific instruction costs.
Definition: ARMSubtarget.h:218
llvm::ARMSubtarget::ARMv8r
@ ARMv8r
Definition: ARMSubtarget.h:125
llvm::Triple::isOSDarwin
bool isOSDarwin() const
Is this a "Darwin" OS (macOS, iOS, tvOS, watchOS, or DriverKit).
Definition: Triple.h:509
llvm::MachineFunction::getInfo
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Definition: MachineFunction.h:754
llvm::ARMSubtarget::MaxInterleaveFactor
unsigned MaxInterleaveFactor
Definition: ARMSubtarget.h:186
llvm::ARMSubtarget::isCortexM7
bool isCortexM7() const
Definition: ARMSubtarget.h:318
llvm::Legalizer
Definition: Legalizer.h:36
llvm::ARMSubtarget::isCortexA5
bool isCortexA5() const
Definition: ARMSubtarget.h:311
llvm::ARMSubtarget::CortexA72
@ CortexA72
Definition: ARMSubtarget.h:62
llvm::ARMSubtarget::useMulOps
bool useMulOps() const
Definition: ARMSubtarget.h:339
llvm::ARMSubtarget::DoubleIssue
@ DoubleIssue
Can load/store 2 registers/cycle.
Definition: ARMSubtarget.h:137
llvm::ARMSubtarget::useMovt
bool useMovt() const
Definition: ARMSubtarget.cpp:430
llvm::ARMSubtarget::isCortexA15
bool isCortexA15() const
Definition: ARMSubtarget.h:315
llvm::ARMSubtarget::isTargetHardFloat
bool isTargetHardFloat() const
Definition: ARMSubtarget.cpp:327
llvm::ARMSubtarget::ARMArchEnum
ARMArchEnum
Definition: ARMSubtarget.h:96
llvm::ARMSubtarget::isAAPCS16_ABI
bool isAAPCS16_ABI() const
Definition: ARMSubtarget.cpp:338
llvm::ARMSubtarget::CortexA55
@ CortexA55
Definition: ARMSubtarget.h:59
llvm::ARMSubtarget::ARMv5
@ ARMv5
Definition: ARMSubtarget.h:99
llvm::ARMSubtarget::DoubleIssueCheckUnalignedAccess
@ DoubleIssueCheckUnalignedAccess
Can load/store 2 registers/cycle, but needs an extra cycle if the access is not 64-bit aligned.
Definition: ARMSubtarget.h:140
llvm::Triple::isOSBinFormatMachO
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
Definition: Triple.h:676
llvm::ARMSubtarget::ARMv81a
@ ARMv81a
Definition: ARMSubtarget.h:114
llvm::ARMSubtarget::ARMv5tej
@ ARMv5tej
Definition: ARMSubtarget.h:102
llvm::ARMSubtarget::isTargetAEABI
bool isTargetAEABI() const
Definition: ARMSubtarget.h:380
llvm::ARMSubtarget::PrefLoopLogAlignment
unsigned PrefLoopLogAlignment
What alignment is preferred for loop bodies, in log2(bytes).
Definition: ARMSubtarget.h:200
llvm::ARMSubtarget::CortexA78C
@ CortexA78C
Definition: ARMSubtarget.h:68
llvm::ARMSubtarget::ARMv4
@ ARMv4
Definition: ARMSubtarget.h:97
llvm::ARMSubtarget::enablePostRAScheduler
bool enablePostRAScheduler() const override
True for some subtargets at > -O0.
Definition: ARMSubtarget.cpp:405
llvm::ARMSubtarget::isKrait
bool isKrait() const
Definition: ARMSubtarget.h:321
isThumb
static bool isThumb(const MCSubtargetInfo &STI)
Definition: ARMAsmPrinter.cpp:468
llvm::Triple::MuslEABI
@ MuslEABI
Definition: Triple.h:240
Align
uint64_t Align
Definition: ELFObjHandler.cpp:81
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::ARMSubtarget::ARMv8a
@ ARMv8a
Definition: ARMSubtarget.h:122
llvm::ARMSubtarget::CortexA7
@ CortexA7
Definition: ARMSubtarget.h:61
llvm::ARMSubtarget::ARMv8mBaseline
@ ARMv8mBaseline
Definition: ARMSubtarget.h:123
llvm::ARMSubtarget::useMachinePipeliner
bool useMachinePipeliner() const
Definition: ARMSubtarget.h:416
llvm::ARMSubtarget::getMVEVectorCostFactor
unsigned getMVEVectorCostFactor(TargetTransformInfo::TargetCostKind CostKind) const
Definition: ARMSubtarget.h:538
llvm::Triple::isOSNaCl
bool isOSNaCl() const
Tests whether the OS is NaCl (Native Client)
Definition: Triple.h:621
llvm::ARMSubtarget::getRegBankInfo
const RegisterBankInfo * getRegBankInfo() const override
Definition: ARMSubtarget.cpp:136
llvm::ARMSubtarget::hasVFP3Base
bool hasVFP3Base() const
Definition: ARMSubtarget.h:331
llvm::ARMSubtarget::isSwift
bool isSwift() const
Definition: ARMSubtarget.h:316
llvm::ARMSubtarget::ARMv91a
@ ARMv91a
Definition: ARMSubtarget.h:128
llvm::ARMSubtarget::ARMProcClassEnum
ARMProcClassEnum
Definition: ARMSubtarget.h:89
llvm::ARMSubtarget::TargetTriple
Triple TargetTriple
TargetTriple - What processor and OS we're targeting.
Definition: ARMSubtarget.h:215
llvm::ARMSubtarget::ARMv6t2
@ ARMv6t2
Definition: ARMSubtarget.h:108
InstructionSelector.h
llvm::TargetOptions::DisableFramePointerElim
bool DisableFramePointerElim(const MachineFunction &MF) const
DisableFramePointerElim - This returns true if frame pointer elimination optimization should be disab...
Definition: TargetOptionsImpl.cpp:23
ARMSelectionDAGInfo.h
llvm::ARMSubtarget::CortexA9
@ CortexA9
Definition: ARMSubtarget.h:71
llvm::Triple::isTargetEHABICompatible
bool isTargetEHABICompatible() const
Tests whether the target supports the EHABI exception handling standard.
Definition: Triple.h:774
llvm::RegisterBankInfo
Holds all the information related to register banks.
Definition: RegisterBankInfo.h:39
llvm::GlobalValue
Definition: GlobalValue.h:44
llvm::InstructionSelector
Provides the logic to select generic machine instructions.
Definition: InstructionSelector.h:428
ARMBaseRegisterInfo.h
MCSchedule.h
llvm::ARMSubtarget::isThumb1Only
bool isThumb1Only() const
Definition: ARMSubtarget.h:418
llvm::ARMSubtarget::getCPUString
const std::string & getCPUString() const
Definition: ARMSubtarget.h:459
llvm::ARMSubtarget::allowPositionIndependentMovt
bool allowPositionIndependentMovt() const
Allow movt+movw for PIC global address calculation.
Definition: ARMSubtarget.h:531
llvm::ARMSubtarget::isRClass
bool isRClass() const
Definition: ARMSubtarget.h:421
llvm::ARMSubtarget::InstrItins
InstrItineraryData InstrItins
Selected instruction itineraries (one entry per itinerary class.)
Definition: ARMSubtarget.h:221
llvm::ARMSubtarget::LdStMultipleTiming
ARMLdStMultipleTiming LdStMultipleTiming
What kind of timing do load multiple/store multiple have (double issue, single issue etc).
Definition: ARMSubtarget.h:193
llvm::ARMSubtarget::ARMv82a
@ ARMv82a
Definition: ARMSubtarget.h:115
llvm::ARMSubtarget::ARMSubtarget
ARMSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS, const ARMBaseTargetMachine &TM, bool IsLittle, bool MinSize=false)
This constructor initializes the data members to match that of the specified triple.
Definition: ARMSubtarget.cpp:93
llvm::ARMSubtarget::isR9Reserved
bool isR9Reserved() const
Definition: ARMSubtarget.h:424
llvm::ARMSubtarget::getLdStMultipleTiming
ARMLdStMultipleTiming getLdStMultipleTiming() const
Definition: ARMSubtarget.h:500
llvm::ARMSubtarget::CortexA75
@ CortexA75
Definition: ARMSubtarget.h:64
llvm::ARMSubtarget::isTargetNetBSD
bool isTargetNetBSD() const
Definition: ARMSubtarget.h:366
llvm::ARMSubtarget::isMClass
bool isMClass() const
Definition: ARMSubtarget.h:420
llvm::ARMSubtarget::stackAlignment
Align stackAlignment
stackAlignment - The minimum alignment known to hold of the stack frame on entry to the function and ...
Definition: ARMSubtarget.h:181
llvm::ARMSubtarget::initializeSubtargetDependencies
ARMSubtarget & initializeSubtargetDependencies(StringRef CPU, StringRef FS)
initializeSubtargetDependencies - Initializes using a CPU and feature string so that we can use initi...
Definition: ARMSubtarget.cpp:77
llvm::ARMBaseInstrInfo
Definition: ARMBaseInstrInfo.h:37
llvm::ARMSubtarget::getFramePointerReg
MCPhysReg getFramePointerReg() const
Definition: ARMSubtarget.h:428
llvm::ARMSubtarget::isTargetIOS
bool isTargetIOS() const
Definition: ARMSubtarget.h:360
llvm::Triple::isWatchABI
bool isWatchABI() const
Definition: Triple.h:499
llvm::ARMSubtarget::CPUString
std::string CPUString
CPUString - String name of used CPU.
Definition: ARMSubtarget.h:184
llvm::ARMSubtarget::isTargetELF
bool isTargetELF() const
Definition: ARMSubtarget.h:370
llvm::ARMSubtarget::MVEVectorCostFactor
unsigned MVEVectorCostFactor
The cost factor for MVE instructions, representing the multiple beats an.
Definition: ARMSubtarget.h:205
llvm::ARMSubtarget::Options
const TargetOptions & Options
Options passed via command line that could influence the target.
Definition: ARMSubtarget.h:224
llvm::ARMSubtarget::RestrictIT
bool RestrictIT
RestrictIT - If true, the subtarget disallows generation of complex IT blocks.
Definition: ARMSubtarget.h:174
llvm::ARMSubtarget::getFrameLowering
const ARMFrameLowering * getFrameLowering() const override
Definition: ARMSubtarget.h:268
llvm::ARMSubtarget::isTargetCOFF
bool isTargetCOFF() const
Definition: ARMSubtarget.h:369
llvm::ARMSubtarget::useDFAforSMS
bool useDFAforSMS() const override
Definition: ARMSubtarget.cpp:402
llvm::TargetMachine::Options
TargetOptions Options
Definition: TargetMachine.h:118
llvm::ARMSubtarget::splitFramePointerPush
bool splitFramePointerPush(const MachineFunction &MF) const
Definition: ARMSubtarget.cpp:495
llvm::ARMSubtarget::isROPI
bool isROPI() const
Definition: ARMSubtarget.cpp:343
llvm::ARMFrameLowering
Definition: ARMFrameLowering.h:21
llvm::ARMSubtarget::CortexA77
@ CortexA77
Definition: ARMSubtarget.h:66
llvm::X86AS::FS
@ FS
Definition: X86.h:200
ARMBaseInstrInfo.h
llvm::ARMSubtarget::ARMv4t
@ ARMv4t
Definition: ARMSubtarget.h:98
llvm::ARMSubtarget::enablePostRAMachineScheduler
bool enablePostRAMachineScheduler() const override
True for some subtargets at > -O0.
Definition: ARMSubtarget.cpp:414
llvm::ARMSubtarget::allowsUnalignedMem
bool allowsUnalignedMem() const
Definition: ARMSubtarget.h:455
llvm::ARMSubtarget::CortexM3
@ CortexM3
Definition: ARMSubtarget.h:72
llvm::ARMSubtarget::ARMv7em
@ ARMv7em
Definition: ARMSubtarget.h:110
llvm::ARMSubtarget::useNEONForSinglePrecisionFP
bool useNEONForSinglePrecisionFP() const
Definition: ARMSubtarget.h:326
llvm::ARMSubtarget::isLittle
bool isLittle() const
Definition: ARMSubtarget.h:461
llvm::ARMSubtarget::ARMv81mMainline
@ ARMv81mMainline
Definition: ARMSubtarget.h:126
llvm::ARMSubtarget::useFastISel
bool useFastISel() const
True if fast-isel is used.
Definition: ARMSubtarget.cpp:438
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::ARMSubtarget::Exynos
@ Exynos
Definition: ARMSubtarget.h:81
llvm::ARMSubtarget::None
@ None
Definition: ARMSubtarget.h:90
Triple.h
llvm::ARMSubtarget::ARMv6k
@ ARMv6k
Definition: ARMSubtarget.h:104
TargetOptions.h
llvm::ARMSubtarget::getCallLowering
const CallLowering * getCallLowering() const override
Definition: ARMSubtarget.cpp:124
llvm::ARMSubtarget::getRegisterInfo
const ARMBaseRegisterInfo * getRegisterInfo() const override
Definition: ARMSubtarget.h:272
llvm::ARMSubtarget::CortexR4F
@ CortexR4F
Definition: ARMSubtarget.h:75
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
llvm::ARMSubtarget::useMachineScheduler
bool useMachineScheduler() const
Definition: ARMSubtarget.h:415
llvm::ARMSubtarget::ARMv87a
@ ARMv87a
Definition: ARMSubtarget.h:120
llvm::ARMSubtarget::PartialUpdateClearance
unsigned PartialUpdateClearance
Clearance before partial register updates (in number of instructions)
Definition: ARMSubtarget.h:189
CostKind
static cl::opt< TargetTransformInfo::TargetCostKind > CostKind("cost-kind", cl::desc("Target cost kind"), cl::init(TargetTransformInfo::TCK_RecipThroughput), cl::values(clEnumValN(TargetTransformInfo::TCK_RecipThroughput, "throughput", "Reciprocal throughput"), clEnumValN(TargetTransformInfo::TCK_Latency, "latency", "Instruction latency"), clEnumValN(TargetTransformInfo::TCK_CodeSize, "code-size", "Code size"), clEnumValN(TargetTransformInfo::TCK_SizeAndLatency, "size-latency", "Code size and latency")))
llvm::ARMFunctionInfo::shouldSignReturnAddress
bool shouldSignReturnAddress() const
Definition: ARMMachineFunctionInfo.h:291
TargetSubtargetInfo.h
llvm::ARMSubtarget::getInstructionSelector
InstructionSelector * getInstructionSelector() const override
Definition: ARMSubtarget.cpp:128
llvm::ARMSubtarget::useFPVFMx64
bool useFPVFMx64() const
Definition: ARMSubtarget.h:345
llvm::Triple::isiOS
bool isiOS() const
Is this an iOS triple.
Definition: Triple.h:485
llvm::ARMSubtarget::getMaxInterleaveFactor
unsigned getMaxInterleaveFactor() const
Definition: ARMSubtarget.h:496
llvm::ARMSubtarget::isCortexA7
bool isCortexA7() const
Definition: ARMSubtarget.h:312
llvm::ARMSubtarget::ARMProcClass
ARMProcClassEnum ARMProcClass
ARMProcClass - ARM processor class: None, AClass, RClass or MClass.
Definition: ARMSubtarget.h:158
llvm::ARMSubtarget::CortexA15
@ CortexA15
Definition: ARMSubtarget.h:53
llvm::ARMSubtarget::ARMv86a
@ ARMv86a
Definition: ARMSubtarget.h:119
llvm::Triple::isWatchOS
bool isWatchOS() const
Is this an Apple watchOS triple.
Definition: Triple.h:495
llvm::ARMSelectionDAGInfo
Definition: ARMSelectionDAGInfo.h:38
llvm::ARMSubtarget::PreISelOperandLatencyAdjustment
int PreISelOperandLatencyAdjustment
The adjustment that we need to apply to get the operand latency from the operand cycle returned by th...
Definition: ARMSubtarget.h:197
llvm::ARMSubtarget::isCortexA9
bool isCortexA9() const
Definition: ARMSubtarget.h:314
llvm::ARMSubtarget::isTargetWindows
bool isTargetWindows() const
Definition: ARMSubtarget.h:367
llvm::ARMSubtarget::isGVInGOT
bool isGVInGOT(const GlobalValue *GV) const
Returns the constant pool modifier needed to access the GV.
Definition: ARMSubtarget.cpp:366
llvm::ARMSubtarget::ARMv5t
@ ARMv5t
Definition: ARMSubtarget.h:100
llvm::ARMBaseRegisterInfo
Definition: ARMBaseRegisterInfo.h:127
llvm::Triple::isOSWindows
bool isOSWindows() const
Tests whether the OS is Windows.
Definition: Triple.h:572
llvm::ARMSubtarget::ignoreCSRForAllocationOrder
bool ignoreCSRForAllocationOrder(const MachineFunction &MF, unsigned PhysReg) const override
Definition: ARMSubtarget.cpp:484
llvm::ARMSubtarget::Swift
@ Swift
Definition: ARMSubtarget.h:87
llvm::ARMSubtarget::CortexR4
@ CortexR4
Definition: ARMSubtarget.h:74
llvm::ARMSubtarget::CortexR52
@ CortexR52
Definition: ARMSubtarget.h:77
llvm::ARMSubtarget::UseMulOps
bool UseMulOps
UseMulOps - True if non-microcoded fused integer multiply-add and multiply-subtract instructions shou...
Definition: ARMSubtarget.h:165
llvm::ARMSubtarget::ARMv8mMainline
@ ARMv8mMainline
Definition: ARMSubtarget.h:124
llvm::ARMSubtarget::ARMArch
ARMArchEnum ARMArch
ARMArch - ARM architecture.
Definition: ARMSubtarget.h:161
ARMFrameLowering.h
llvm::ARMSubtarget::isTargetDarwin
bool isTargetDarwin() const
Definition: ARMSubtarget.h:359
llvm::ARMSubtarget::Krait
@ Krait
Definition: ARMSubtarget.h:82
uint16_t
llvm::MachineFunction::getTarget
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Definition: MachineFunction.h:652
llvm::ARMSubtarget::isCortexR5
bool isCortexR5() const
Definition: ARMSubtarget.h:320
llvm::ARMSubtarget::isAPCS_ABI
bool isAPCS_ABI() const
Definition: ARMSubtarget.cpp:329
llvm::ARMSubtarget::SingleIssue
@ SingleIssue
Can load/store 1 register/cycle.
Definition: ARMSubtarget.h:142
llvm::ARMSubtarget::isTargetMachO
bool isTargetMachO() const
Definition: ARMSubtarget.h:371
llvm::ARMSubtarget::useFPVFMx16
bool useFPVFMx16() const
Definition: ARMSubtarget.h:344
llvm::ARMSubtarget::isAAPCS_ABI
bool isAAPCS_ABI() const
Definition: ARMSubtarget.cpp:333
llvm::ARMSubtarget::NeoverseV1
@ NeoverseV1
Definition: ARMSubtarget.h:86
llvm::ARMSubtarget::Others
@ Others
Definition: ARMSubtarget.h:50
llvm::MCSchedModel
Machine model for scheduling, bundling, and heuristics.
Definition: MCSchedule.h:244
llvm::ARMSubtarget::CortexX1
@ CortexX1
Definition: ARMSubtarget.h:79
llvm::ARMSubtarget::getMaxMemcpyTPInlineSizeThreshold
unsigned getMaxMemcpyTPInlineSizeThreshold() const
getMaxMemcpyTPInlineSizeThreshold - Returns the maximum size that still makes it profitable to inline...
Definition: ARMSubtarget.h:246
llvm::ARMSubtarget::SingleIssuePlusExtras
@ SingleIssuePlusExtras
Can load/store 1 register/cycle, but needs an extra cycle for address computation and potentially als...
Definition: ARMSubtarget.h:145
llvm::ARMSubtarget::hasVFP4Base
bool hasVFP4Base() const
Definition: ARMSubtarget.h:332
llvm::ARMSubtarget::enableMachinePipeliner
bool enableMachinePipeliner() const override
Returns true if machine pipeliner should be enabled.
Definition: ARMSubtarget.cpp:396
llvm::ARMSubtarget::ARMv6m
@ ARMv6m
Definition: ARMSubtarget.h:106
llvm::ARMSubtarget::MClass
@ MClass
Definition: ARMSubtarget.h:93
llvm::ARMSubtarget::CortexA8
@ CortexA8
Definition: ARMSubtarget.h:70
ARMISelLowering.h
llvm::ARMSubtarget::ARMv5te
@ ARMv5te
Definition: ARMSubtarget.h:101
llvm::ARMSubtarget::CortexA12
@ CortexA12
Definition: ARMSubtarget.h:52
llvm::ARMSubtarget::CortexA76
@ CortexA76
Definition: ARMSubtarget.h:65
llvm::Triple::isOSNetBSD
bool isOSNetBSD() const
Definition: Triple.h:527
llvm::ARMSubtarget::isTargetEHABICompatible
bool isTargetEHABICompatible() const
Definition: ARMSubtarget.h:398
llvm::ARMSubtarget::CortexA35
@ CortexA35
Definition: ARMSubtarget.h:56
llvm::ARMSubtarget::CortexA78
@ CortexA78
Definition: ARMSubtarget.h:67
llvm::ARMSubtarget::hasMinSize
bool hasMinSize() const
Definition: ARMSubtarget.h:417
llvm::ARMSubtarget::CortexA53
@ CortexA53
Definition: ARMSubtarget.h:58
TargetTransformInfo.h
llvm::ARMSubtarget::restrictIT
bool restrictIT() const
Definition: ARMSubtarget.h:457
llvm::ARMSubtarget::isGVIndirectSymbol
bool isGVIndirectSymbol(const GlobalValue *GV) const
True if the GV will be accessed via an indirect symbol.
Definition: ARMSubtarget.cpp:352
llvm::Triple::getEnvironment
EnvironmentType getEnvironment() const
Get the parsed environment type of this triple.
Definition: Triple.h:363
llvm::ARMSubtarget::ARMv85a
@ ARMv85a
Definition: ARMSubtarget.h:118
llvm::Triple::EABIHF
@ EABIHF
Definition: Triple.h:237
llvm::ARMSubtarget::CortexA5
@ CortexA5
Definition: ARMSubtarget.h:57
llvm::LegalizerInfo
Definition: LegalizerInfo.h:1182
llvm::Triple::GNUEABIHF
@ GNUEABIHF
Definition: Triple.h:232
llvm::ARMSubtarget::CortexA32
@ CortexA32
Definition: ARMSubtarget.h:55
llvm::ARMSubtarget::isThumb2
bool isThumb2() const
Definition: ARMSubtarget.h:419
llvm::ARMSubtarget::getPrefLoopLogAlignment
unsigned getPrefLoopLogAlignment() const
Definition: ARMSubtarget.h:535
llvm::ARMSubtarget::ARMv88a
@ ARMv88a
Definition: ARMSubtarget.h:121
llvm::ARMSubtarget::CortexA710
@ CortexA710
Definition: ARMSubtarget.h:69
llvm::ARMSubtarget::getGPRAllocationOrder
unsigned getGPRAllocationOrder(const MachineFunction &MF) const
Definition: ARMSubtarget.cpp:453
MachineFunction.h
llvm::Triple::EABI
@ EABI
Definition: Triple.h:236
llvm::CallLowering
Definition: CallLowering.h:44
llvm::ARMSubtarget::isTargetNaCl
bool isTargetNaCl() const
Definition: ARMSubtarget.h:365
llvm::ARMSubtarget::isXRaySupported
bool isXRaySupported() const override
Definition: ARMSubtarget.cpp:140
llvm::InstrItineraryData
Itinerary data supplied by a subtarget to be used by a target.
Definition: MCInstrItineraries.h:109
llvm::ARMSubtarget::isCortexA8
bool isCortexA8() const
Definition: ARMSubtarget.h:313
llvm::ARMSubtarget::isTargetGNUAEABI
bool isTargetGNUAEABI() const
Definition: ARMSubtarget.h:385
llvm::ARMSubtarget::hasAnyDataBarrier
bool hasAnyDataBarrier() const
Definition: ARMSubtarget.h:335
llvm::ARMSubtarget::useStride4VFPs
bool useStride4VFPs() const
Definition: ARMSubtarget.cpp:422
llvm::ARMSubtarget::hasVFP2Base
bool hasVFP2Base() const
Definition: ARMSubtarget.h:330
llvm::ARMSubtarget::getReturnOpcode
unsigned getReturnOpcode() const
Returns the correct return opcode for the current feature set.
Definition: ARMSubtarget.h:520
llvm::ARMSubtarget::ARMv6kz
@ ARMv6kz
Definition: ARMSubtarget.h:105