LLVM  14.0.0git
ARMSubtarget.h
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1 //===-- ARMSubtarget.h - Define Subtarget for the ARM ----------*- C++ -*--===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file declares the ARM specific subclass of TargetSubtargetInfo.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H
14 #define LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H
15 
16 #include "ARMBaseInstrInfo.h"
17 #include "ARMBaseRegisterInfo.h"
18 #include "ARMConstantPoolValue.h"
19 #include "ARMFrameLowering.h"
20 #include "ARMISelLowering.h"
21 #include "ARMSelectionDAGInfo.h"
22 #include "llvm/ADT/Triple.h"
31 #include "llvm/MC/MCSchedule.h"
34 #include <memory>
35 #include <string>
36 
37 #define GET_SUBTARGETINFO_HEADER
38 #include "ARMGenSubtargetInfo.inc"
39 
40 namespace llvm {
41 
42 class ARMBaseTargetMachine;
43 class GlobalValue;
44 class StringRef;
45 
47 protected:
50 
85  };
88 
92  };
93  enum ARMArchEnum {
130  };
131 
132 public:
133  /// What kind of timing do load multiple/store multiple instructions have.
135  /// Can load/store 2 registers/cycle.
137  /// Can load/store 2 registers/cycle, but needs an extra cycle if the access
138  /// is not 64-bit aligned.
140  /// Can load/store 1 register/cycle.
142  /// Can load/store 1 register/cycle, but needs an extra cycle for address
143  /// computation and potentially also for register writeback.
145  };
146 
147 protected:
148  /// ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.
150 
151  /// ARMProcClass - ARM processor class: None, AClass, RClass or MClass.
153 
154  /// ARMArch - ARM architecture
156 
157  /// HasV4TOps, HasV5TOps, HasV5TEOps,
158  /// HasV6Ops, HasV6MOps, HasV6KOps, HasV6T2Ops, HasV7Ops, HasV8Ops -
159  /// Specify whether target support specific ARM ISA variants.
160  bool HasV4TOps = false;
161  bool HasV5TOps = false;
162  bool HasV5TEOps = false;
163  bool HasV6Ops = false;
164  bool HasV6MOps = false;
165  bool HasV6KOps = false;
166  bool HasV6T2Ops = false;
167  bool HasV7Ops = false;
168  bool HasV8Ops = false;
169  bool HasV8_1aOps = false;
170  bool HasV8_2aOps = false;
171  bool HasV8_3aOps = false;
172  bool HasV8_4aOps = false;
173  bool HasV8_5aOps = false;
174  bool HasV8_6aOps = false;
175  bool HasV8_7aOps = false;
176  bool HasV9_0aOps = false;
177  bool HasV9_1aOps = false;
178  bool HasV9_2aOps = false;
179  bool HasV8MBaselineOps = false;
180  bool HasV8MMainlineOps = false;
181  bool HasV8_1MMainlineOps = false;
182  bool HasMVEIntegerOps = false;
183  bool HasMVEFloatOps = false;
184  bool HasCDEOps = false;
185 
186  /// HasVFPv2, HasVFPv3, HasVFPv4, HasFPARMv8, HasNEON - Specify what
187  /// floating point ISAs are supported.
188  bool HasVFPv2 = false;
189  bool HasVFPv3 = false;
190  bool HasVFPv4 = false;
191  bool HasFPARMv8 = false;
192  bool HasNEON = false;
193  bool HasFPRegs = false;
194  bool HasFPRegs16 = false;
195  bool HasFPRegs64 = false;
196 
197  /// Versions of the VFP flags restricted to single precision, or to
198  /// 16 d-registers, or both.
199  bool HasVFPv2SP = false;
200  bool HasVFPv3SP = false;
201  bool HasVFPv4SP = false;
202  bool HasFPARMv8SP = false;
203  bool HasVFPv3D16 = false;
204  bool HasVFPv4D16 = false;
205  bool HasFPARMv8D16 = false;
206  bool HasVFPv3D16SP = false;
207  bool HasVFPv4D16SP = false;
208  bool HasFPARMv8D16SP = false;
209 
210  /// HasDotProd - True if the ARMv8.2A dot product instructions are supported.
211  bool HasDotProd = false;
212 
213  /// UseNEONForSinglePrecisionFP - if the NEONFP attribute has been
214  /// specified. Use the method useNEONForSinglePrecisionFP() to
215  /// determine if NEON should actually be used.
217 
218  /// UseMulOps - True if non-microcoded fused integer multiply-add and
219  /// multiply-subtract instructions should be used.
220  bool UseMulOps = false;
221 
222  /// SlowFPVMLx - If the VFP2 / NEON instructions are available, indicates
223  /// whether the FP VML[AS] instructions are slow (if so, don't use them).
224  bool SlowFPVMLx = false;
225 
226  /// SlowFPVFMx - If the VFP4 / NEON instructions are available, indicates
227  /// whether the FP VFM[AS] instructions are slow (if so, don't use them).
228  bool SlowFPVFMx = false;
229 
230  /// HasVMLxForwarding - If true, NEON has special multiplier accumulator
231  /// forwarding to allow mul + mla being issued back to back.
232  bool HasVMLxForwarding = false;
233 
234  /// SlowFPBrcc - True if floating point compare + branch is slow.
235  bool SlowFPBrcc = false;
236 
237  /// InThumbMode - True if compiling for Thumb, false for ARM.
238  bool InThumbMode = false;
239 
240  /// UseSoftFloat - True if we're using software floating point features.
241  bool UseSoftFloat = false;
242 
243  /// UseMISched - True if MachineScheduler should be used for this subtarget.
244  bool UseMISched = false;
245 
246  /// DisablePostRAScheduler - False if scheduling should happen again after
247  /// register allocation.
249 
250  /// HasThumb2 - True if Thumb2 instructions are supported.
251  bool HasThumb2 = false;
252 
253  /// NoARM - True if subtarget does not support ARM mode execution.
254  bool NoARM = false;
255 
256  /// ReserveR9 - True if R9 is not available as a general purpose register.
257  bool ReserveR9 = false;
258 
259  /// NoMovt - True if MOVT / MOVW pairs are not used for materialization of
260  /// 32-bit imms (including global addresses).
261  bool NoMovt = false;
262 
263  /// SupportsTailCall - True if the OS supports tail call. The dynamic linker
264  /// must be able to synthesize call stubs for interworking between ARM and
265  /// Thumb.
266  bool SupportsTailCall = false;
267 
268  /// HasFP16 - True if subtarget supports half-precision FP conversions
269  bool HasFP16 = false;
270 
271  /// HasFullFP16 - True if subtarget supports half-precision FP operations
272  bool HasFullFP16 = false;
273 
274  /// HasFP16FML - True if subtarget supports half-precision FP fml operations
275  bool HasFP16FML = false;
276 
277  /// HasBF16 - True if subtarget supports BFloat16 floating point operations
278  bool HasBF16 = false;
279 
280  /// HasMatMulInt8 - True if subtarget supports 8-bit integer matrix multiply
281  bool HasMatMulInt8 = false;
282 
283  /// HasD32 - True if subtarget has the full 32 double precision
284  /// FP registers for VFPv3.
285  bool HasD32 = false;
286 
287  /// HasHardwareDivide - True if subtarget supports [su]div in Thumb mode
289 
290  /// HasHardwareDivideInARM - True if subtarget supports [su]div in ARM mode
292 
293  /// HasDataBarrier - True if the subtarget supports DMB / DSB data barrier
294  /// instructions.
295  bool HasDataBarrier = false;
296 
297  /// HasFullDataBarrier - True if the subtarget supports DFB data barrier
298  /// instruction.
299  bool HasFullDataBarrier = false;
300 
301  /// HasV7Clrex - True if the subtarget supports CLREX instructions
302  bool HasV7Clrex = false;
303 
304  /// HasAcquireRelease - True if the subtarget supports v8 atomics (LDA/LDAEX etc)
305  /// instructions
306  bool HasAcquireRelease = false;
307 
308  /// Pref32BitThumb - If true, codegen would prefer 32-bit Thumb instructions
309  /// over 16-bit ones.
310  bool Pref32BitThumb = false;
311 
312  /// AvoidCPSRPartialUpdate - If true, codegen would avoid using instructions
313  /// that partially update CPSR and add false dependency on the previous
314  /// CPSR setting instruction.
316 
317  /// CheapPredicableCPSRDef - If true, disable +1 predication cost
318  /// for instructions updating CPSR. Enabled for Cortex-A57.
320 
321  /// AvoidMOVsShifterOperand - If true, codegen should avoid using flag setting
322  /// movs with shifter operand (i.e. asr, lsl, lsr).
324 
325  /// HasRetAddrStack - Some processors perform return stack prediction. CodeGen should
326  /// avoid issue "normal" call instructions to callees which do not return.
327  bool HasRetAddrStack = false;
328 
329  /// HasBranchPredictor - True if the subtarget has a branch predictor. Having
330  /// a branch predictor or not changes the expected cost of taking a branch
331  /// which affects the choice of whether to use predicated instructions.
332  bool HasBranchPredictor = true;
333 
334  /// HasMPExtension - True if the subtarget supports Multiprocessing
335  /// extension (ARMv7 only).
336  bool HasMPExtension = false;
337 
338  /// HasVirtualization - True if the subtarget supports the Virtualization
339  /// extension.
340  bool HasVirtualization = false;
341 
342  /// HasFP64 - If true, the floating point unit supports double
343  /// precision.
344  bool HasFP64 = false;
345 
346  /// If true, the processor supports the Performance Monitor Extensions. These
347  /// include a generic cycle-counter as well as more fine-grained (often
348  /// implementation-specific) events.
349  bool HasPerfMon = false;
350 
351  /// HasTrustZone - if true, processor supports TrustZone security extensions
352  bool HasTrustZone = false;
353 
354  /// Has8MSecExt - if true, processor supports ARMv8-M Security Extensions
355  bool Has8MSecExt = false;
356 
357  /// HasSHA2 - if true, processor supports SHA1 and SHA256
358  bool HasSHA2 = false;
359 
360  /// HasAES - if true, processor supports AES
361  bool HasAES = false;
362 
363  /// HasCrypto - if true, processor supports Cryptography extensions
364  bool HasCrypto = false;
365 
366  /// HasCRC - if true, processor supports CRC instructions
367  bool HasCRC = false;
368 
369  /// HasRAS - if true, the processor supports RAS extensions
370  bool HasRAS = false;
371 
372  /// HasLOB - if true, the processor supports the Low Overhead Branch extension
373  bool HasLOB = false;
374 
375  /// If true, the instructions "vmov.i32 d0, #0" and "vmov.i32 q0, #0" are
376  /// particularly effective at zeroing a VFP register.
377  bool HasZeroCycleZeroing = false;
378 
379  /// HasFPAO - if true, processor does positive address offset computation faster
380  bool HasFPAO = false;
381 
382  /// HasFuseAES - if true, processor executes back to back AES instruction
383  /// pairs faster.
384  bool HasFuseAES = false;
385 
386  /// HasFuseLiterals - if true, processor executes back to back
387  /// bottom and top halves of literal generation faster.
388  bool HasFuseLiterals = false;
389 
390  /// If true, if conversion may decide to leave some instructions unpredicated.
392 
393  /// If true, VMOV will be favored over VGETLNi32.
394  bool HasSlowVGETLNi32 = false;
395 
396  /// If true, VMOV will be favored over VDUP.
397  bool HasSlowVDUP32 = false;
398 
399  /// If true, VMOVSR will be favored over VMOVDRR.
400  bool PreferVMOVSR = false;
401 
402  /// If true, ISHST barriers will be used for Release semantics.
403  bool PreferISHST = false;
404 
405  /// If true, a VLDM/VSTM starting with an odd register number is considered to
406  /// take more microops than single VLDRS/VSTRS.
407  bool SlowOddRegister = false;
408 
409  /// If true, loading into a D subregister will be penalized.
410  bool SlowLoadDSubregister = false;
411 
412  /// If true, use a wider stride when allocating VFP registers.
413  bool UseWideStrideVFP = false;
414 
415  /// If true, the AGU and NEON/FPU units are multiplexed.
416  bool HasMuxedUnits = false;
417 
418  /// If true, VMOVS will never be widened to VMOVD.
419  bool DontWidenVMOVS = false;
420 
421  /// If true, splat a register between VFP and NEON instructions.
422  bool SplatVFPToNeon = false;
423 
424  /// If true, run the MLx expansion pass.
425  bool ExpandMLx = false;
426 
427  /// If true, VFP/NEON VMLA/VMLS have special RAW hazards.
428  bool HasVMLxHazards = false;
429 
430  // If true, read thread pointer from coprocessor register.
431  bool ReadTPHard = false;
432 
433  /// If true, VMOVRS, VMOVSR and VMOVS will be converted from VFP to NEON.
434  bool UseNEONForFPMovs = false;
435 
436  /// If true, VLDn instructions take an extra cycle for unaligned accesses.
437  bool CheckVLDnAlign = false;
438 
439  /// If true, VFP instructions are not pipelined.
440  bool NonpipelinedVFP = false;
441 
442  /// StrictAlign - If true, the subtarget disallows unaligned memory
443  /// accesses for some types. For details, see
444  /// ARMTargetLowering::allowsMisalignedMemoryAccesses().
445  bool StrictAlign = false;
446 
447  /// RestrictIT - If true, the subtarget disallows generation of deprecated IT
448  /// blocks to conform to ARMv8 rule.
449  bool RestrictIT = false;
450 
451  /// HasDSP - If true, the subtarget supports the DSP (saturating arith
452  /// and such) instructions.
453  bool HasDSP = false;
454 
455  /// NaCl TRAP instruction is generated instead of the regular TRAP.
456  bool UseNaClTrap = false;
457 
458  /// Generate calls via indirect call instructions.
459  bool GenLongCalls = false;
460 
461  /// Generate code that does not contain data access to code sections.
462  bool GenExecuteOnly = false;
463 
464  /// Target machine allowed unsafe FP math (such as use of NEON fp)
465  bool UnsafeFPMath = false;
466 
467  /// UseSjLjEH - If true, the target uses SjLj exception handling (e.g. iOS).
468  bool UseSjLjEH = false;
469 
470  /// Has speculation barrier
471  bool HasSB = false;
472 
473  /// Implicitly convert an instruction to a different one if its immediates
474  /// cannot be encoded. For example, ADD r0, r1, #FFFFFFFF -> SUB r0, r1, #1.
475  bool NegativeImmediates = true;
476 
477  /// Mitigate against the cve-2021-35465 security vulnurability.
479 
480  /// Harden against Straight Line Speculation for Returns and Indirect
481  /// Branches.
482  bool HardenSlsRetBr = false;
483 
484  /// Harden against Straight Line Speculation for indirect calls.
485  bool HardenSlsBlr = false;
486 
487  /// Generate thunk code for SLS mitigation in the normal text section.
488  bool HardenSlsNoComdat = false;
489 
490  /// stackAlignment - The minimum alignment known to hold of the stack frame on
491  /// entry to the function and which must be maintained by every function.
493 
494  /// CPUString - String name of used CPU.
495  std::string CPUString;
496 
497  unsigned MaxInterleaveFactor = 1;
498 
499  /// Clearance before partial register updates (in number of instructions)
501 
502  /// What kind of timing do load multiple/store multiple have (double issue,
503  /// single issue etc).
505 
506  /// The adjustment that we need to apply to get the operand latency from the
507  /// operand cycle returned by the itinerary data for pre-ISel operands.
509 
510  /// What alignment is preferred for loop bodies, in log2(bytes).
511  unsigned PrefLoopLogAlignment = 0;
512 
513  /// The cost factor for MVE instructions, representing the multiple beats an
514  // instruction can take. The default is 2, (set in initSubtargetFeatures so
515  // that we can use subtarget features less than 2).
516  unsigned MVEVectorCostFactor = 0;
517 
518  /// OptMinSize - True if we're optimising for minimum code size, equal to
519  /// the function attribute.
520  bool OptMinSize = false;
521 
522  /// IsLittle - The target is Little Endian
523  bool IsLittle;
524 
525  /// TargetTriple - What processor and OS we're targeting.
527 
528  /// SchedModel - Processor specific instruction costs.
530 
531  /// Selected instruction itineraries (one entry per itinerary class.)
533 
534  /// Options passed via command line that could influence the target
536 
538 
539 public:
540  /// This constructor initializes the data members to match that
541  /// of the specified triple.
542  ///
543  ARMSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS,
544  const ARMBaseTargetMachine &TM, bool IsLittle,
545  bool MinSize = false);
546 
547  /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
548  /// that still makes it profitable to inline the call.
549  unsigned getMaxInlineSizeThreshold() const {
550  return 64;
551  }
552 
553  /// getMaxMemcpyTPInlineSizeThreshold - Returns the maximum size
554  /// that still makes it profitable to inline a llvm.memcpy as a Tail
555  /// Predicated loop.
556  /// This threshold should only be used for constant size inputs.
557  unsigned getMaxMemcpyTPInlineSizeThreshold() const { return 128; }
558 
559  /// ParseSubtargetFeatures - Parses features string setting specified
560  /// subtarget options. Definition of function is auto generated by tblgen.
562 
563  /// initializeSubtargetDependencies - Initializes using a CPU and feature string
564  /// so that we can use initializer lists for subtarget initialization.
566 
567  const ARMSelectionDAGInfo *getSelectionDAGInfo() const override {
568  return &TSInfo;
569  }
570 
571  const ARMBaseInstrInfo *getInstrInfo() const override {
572  return InstrInfo.get();
573  }
574 
575  const ARMTargetLowering *getTargetLowering() const override {
576  return &TLInfo;
577  }
578 
579  const ARMFrameLowering *getFrameLowering() const override {
580  return FrameLowering.get();
581  }
582 
583  const ARMBaseRegisterInfo *getRegisterInfo() const override {
584  return &InstrInfo->getRegisterInfo();
585  }
586 
587  const CallLowering *getCallLowering() const override;
589  const LegalizerInfo *getLegalizerInfo() const override;
590  const RegisterBankInfo *getRegBankInfo() const override;
591 
592 private:
593  ARMSelectionDAGInfo TSInfo;
594  // Either Thumb1FrameLowering or ARMFrameLowering.
595  std::unique_ptr<ARMFrameLowering> FrameLowering;
596  // Either Thumb1InstrInfo or Thumb2InstrInfo.
597  std::unique_ptr<ARMBaseInstrInfo> InstrInfo;
598  ARMTargetLowering TLInfo;
599 
600  /// GlobalISel related APIs.
601  std::unique_ptr<CallLowering> CallLoweringInfo;
602  std::unique_ptr<InstructionSelector> InstSelector;
603  std::unique_ptr<LegalizerInfo> Legalizer;
604  std::unique_ptr<RegisterBankInfo> RegBankInfo;
605 
606  void initializeEnvironment();
607  void initSubtargetFeatures(StringRef CPU, StringRef FS);
608  ARMFrameLowering *initializeFrameLowering(StringRef CPU, StringRef FS);
609 
610  std::bitset<8> CoprocCDE = {};
611 public:
612  void computeIssueWidth();
613 
614  bool hasV4TOps() const { return HasV4TOps; }
615  bool hasV5TOps() const { return HasV5TOps; }
616  bool hasV5TEOps() const { return HasV5TEOps; }
617  bool hasV6Ops() const { return HasV6Ops; }
618  bool hasV6MOps() const { return HasV6MOps; }
619  bool hasV6KOps() const { return HasV6KOps; }
620  bool hasV6T2Ops() const { return HasV6T2Ops; }
621  bool hasV7Ops() const { return HasV7Ops; }
622  bool hasV8Ops() const { return HasV8Ops; }
623  bool hasV8_1aOps() const { return HasV8_1aOps; }
624  bool hasV8_2aOps() const { return HasV8_2aOps; }
625  bool hasV8_3aOps() const { return HasV8_3aOps; }
626  bool hasV8_4aOps() const { return HasV8_4aOps; }
627  bool hasV8_5aOps() const { return HasV8_5aOps; }
628  bool hasV8_6aOps() const { return HasV8_6aOps; }
629  bool hasV8_7aOps() const { return HasV8_7aOps; }
630  bool hasV9_0aOps() const { return HasV9_0aOps; }
631  bool hasV9_1aOps() const { return HasV9_1aOps; }
632  bool hasV9_2aOps() const { return HasV9_2aOps; }
633  bool hasV8MBaselineOps() const { return HasV8MBaselineOps; }
634  bool hasV8MMainlineOps() const { return HasV8MMainlineOps; }
635  bool hasV8_1MMainlineOps() const { return HasV8_1MMainlineOps; }
636  bool hasMVEIntegerOps() const { return HasMVEIntegerOps; }
637  bool hasMVEFloatOps() const { return HasMVEFloatOps; }
638  bool hasCDEOps() const { return HasCDEOps; }
639  bool hasFPRegs() const { return HasFPRegs; }
640  bool hasFPRegs16() const { return HasFPRegs16; }
641  bool hasFPRegs64() const { return HasFPRegs64; }
642 
643  /// @{
644  /// These functions are obsolete, please consider adding subtarget features
645  /// or properties instead of calling them.
646  bool isCortexA5() const { return ARMProcFamily == CortexA5; }
647  bool isCortexA7() const { return ARMProcFamily == CortexA7; }
648  bool isCortexA8() const { return ARMProcFamily == CortexA8; }
649  bool isCortexA9() const { return ARMProcFamily == CortexA9; }
650  bool isCortexA15() const { return ARMProcFamily == CortexA15; }
651  bool isSwift() const { return ARMProcFamily == Swift; }
652  bool isCortexM3() const { return ARMProcFamily == CortexM3; }
653  bool isCortexM7() const { return ARMProcFamily == CortexM7; }
654  bool isLikeA9() const { return isCortexA9() || isCortexA15() || isKrait(); }
655  bool isCortexR5() const { return ARMProcFamily == CortexR5; }
656  bool isKrait() const { return ARMProcFamily == Krait; }
657  /// @}
658 
659  bool hasARMOps() const { return !NoARM; }
660 
661  bool hasVFP2Base() const { return HasVFPv2SP; }
662  bool hasVFP3Base() const { return HasVFPv3D16SP; }
663  bool hasVFP4Base() const { return HasVFPv4D16SP; }
664  bool hasFPARMv8Base() const { return HasFPARMv8D16SP; }
665  bool hasNEON() const { return HasNEON; }
666  bool hasSHA2() const { return HasSHA2; }
667  bool hasAES() const { return HasAES; }
668  bool hasCrypto() const { return HasCrypto; }
669  bool hasDotProd() const { return HasDotProd; }
670  bool hasCRC() const { return HasCRC; }
671  bool hasRAS() const { return HasRAS; }
672  bool hasLOB() const { return HasLOB; }
673  bool hasVirtualization() const { return HasVirtualization; }
674 
677  }
678 
681  bool hasDataBarrier() const { return HasDataBarrier; }
682  bool hasFullDataBarrier() const { return HasFullDataBarrier; }
683  bool hasV7Clrex() const { return HasV7Clrex; }
684  bool hasAcquireRelease() const { return HasAcquireRelease; }
685 
686  bool hasAnyDataBarrier() const {
687  return HasDataBarrier || (hasV6Ops() && !isThumb());
688  }
689 
690  bool useMulOps() const { return UseMulOps; }
691  bool useFPVMLx() const { return !SlowFPVMLx; }
692  bool useFPVFMx() const {
693  return !isTargetDarwin() && hasVFP4Base() && !SlowFPVFMx;
694  }
695  bool useFPVFMx16() const { return useFPVFMx() && hasFullFP16(); }
696  bool useFPVFMx64() const { return useFPVFMx() && hasFP64(); }
697  bool hasVMLxForwarding() const { return HasVMLxForwarding; }
698  bool isFPBrccSlow() const { return SlowFPBrcc; }
699  bool hasFP64() const { return HasFP64; }
700  bool hasPerfMon() const { return HasPerfMon; }
701  bool hasTrustZone() const { return HasTrustZone; }
702  bool has8MSecExt() const { return Has8MSecExt; }
703  bool hasZeroCycleZeroing() const { return HasZeroCycleZeroing; }
704  bool hasFPAO() const { return HasFPAO; }
706  bool hasSlowVGETLNi32() const { return HasSlowVGETLNi32; }
707  bool hasSlowVDUP32() const { return HasSlowVDUP32; }
708  bool preferVMOVSR() const { return PreferVMOVSR; }
709  bool preferISHSTBarriers() const { return PreferISHST; }
710  bool expandMLx() const { return ExpandMLx; }
711  bool hasVMLxHazards() const { return HasVMLxHazards; }
712  bool hasSlowOddRegister() const { return SlowOddRegister; }
714  bool useWideStrideVFP() const { return UseWideStrideVFP; }
715  bool hasMuxedUnits() const { return HasMuxedUnits; }
716  bool dontWidenVMOVS() const { return DontWidenVMOVS; }
717  bool useSplatVFPToNeon() const { return SplatVFPToNeon; }
718  bool useNEONForFPMovs() const { return UseNEONForFPMovs; }
719  bool checkVLDnAccessAlignment() const { return CheckVLDnAlign; }
720  bool nonpipelinedVFP() const { return NonpipelinedVFP; }
721  bool prefers32BitThumb() const { return Pref32BitThumb; }
725  bool hasRetAddrStack() const { return HasRetAddrStack; }
726  bool hasBranchPredictor() const { return HasBranchPredictor; }
727  bool hasMPExtension() const { return HasMPExtension; }
728  bool hasDSP() const { return HasDSP; }
729  bool useNaClTrap() const { return UseNaClTrap; }
730  bool useSjLjEH() const { return UseSjLjEH; }
731  bool hasSB() const { return HasSB; }
732  bool genLongCalls() const { return GenLongCalls; }
733  bool genExecuteOnly() const { return GenExecuteOnly; }
734  bool hasBaseDSP() const {
735  if (isThumb())
736  return hasDSP();
737  else
738  return hasV5TEOps();
739  }
740 
741  bool hasFP16() const { return HasFP16; }
742  bool hasD32() const { return HasD32; }
743  bool hasFullFP16() const { return HasFullFP16; }
744  bool hasFP16FML() const { return HasFP16FML; }
745  bool hasBF16() const { return HasBF16; }
746 
747  bool hasFuseAES() const { return HasFuseAES; }
748  bool hasFuseLiterals() const { return HasFuseLiterals; }
749  /// Return true if the CPU supports any kind of instruction fusion.
750  bool hasFusion() const { return hasFuseAES() || hasFuseLiterals(); }
751 
752  bool hasMatMulInt8() const { return HasMatMulInt8; }
753 
754  const Triple &getTargetTriple() const { return TargetTriple; }
755 
756  bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
757  bool isTargetIOS() const { return TargetTriple.isiOS(); }
758  bool isTargetWatchOS() const { return TargetTriple.isWatchOS(); }
759  bool isTargetWatchABI() const { return TargetTriple.isWatchABI(); }
760  bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
761  bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
762  bool isTargetNetBSD() const { return TargetTriple.isOSNetBSD(); }
763  bool isTargetWindows() const { return TargetTriple.isOSWindows(); }
764 
765  bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
766  bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
767  bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
768 
769  // ARM EABI is the bare-metal EABI described in ARM ABI documents and
770  // can be accessed via -target arm-none-eabi. This is NOT GNUEABI.
771  // FIXME: Add a flag for bare-metal for that target and set Triple::EABI
772  // even for GNUEABI, so we can make a distinction here and still conform to
773  // the EABI on GNU (and Android) mode. This requires change in Clang, too.
774  // FIXME: The Darwin exception is temporary, while we move users to
775  // "*-*-*-macho" triples as quickly as possible.
776  bool isTargetAEABI() const {
780  }
781  bool isTargetGNUAEABI() const {
785  }
786  bool isTargetMuslAEABI() const {
790  }
791 
792  // ARM Targets that support EHABI exception handling standard
793  // Darwin uses SjLj. Other targets might need more checks.
794  bool isTargetEHABICompatible() const {
801  isTargetAndroid()) &&
803  }
804 
805  bool isTargetHardFloat() const;
806 
807  bool isTargetAndroid() const { return TargetTriple.isAndroid(); }
808 
809  bool isXRaySupported() const override;
810 
811  bool isAPCS_ABI() const;
812  bool isAAPCS_ABI() const;
813  bool isAAPCS16_ABI() const;
814 
815  bool isROPI() const;
816  bool isRWPI() const;
817 
818  bool useMachineScheduler() const { return UseMISched; }
820  bool useSoftFloat() const { return UseSoftFloat; }
821  bool isThumb() const { return InThumbMode; }
822  bool hasMinSize() const { return OptMinSize; }
823  bool isThumb1Only() const { return InThumbMode && !HasThumb2; }
824  bool isThumb2() const { return InThumbMode && HasThumb2; }
825  bool hasThumb2() const { return HasThumb2; }
826  bool isMClass() const { return ARMProcClass == MClass; }
827  bool isRClass() const { return ARMProcClass == RClass; }
828  bool isAClass() const { return ARMProcClass == AClass; }
829  bool isReadTPHard() const { return ReadTPHard; }
830 
831  bool isR9Reserved() const {
832  return isTargetMachO() ? (ReserveR9 || !HasV6Ops) : ReserveR9;
833  }
834 
836  if (isTargetDarwin() || (!isTargetWindows() && isThumb()))
837  return ARM::R7;
838  return ARM::R11;
839  }
840 
841  /// Returns true if the frame setup is split into two separate pushes (first
842  /// r0-r7,lr then r8-r11), principally so that the frame pointer is adjacent
843  /// to lr. This is always required on Thumb1-only targets, as the push and
844  /// pop instructions can't access the high registers.
845  bool splitFramePushPop(const MachineFunction &MF) const {
846  return (getFramePointerReg() == ARM::R7 &&
848  isThumb1Only();
849  }
850 
851  bool useStride4VFPs() const;
852 
853  bool useMovt() const;
854 
855  bool supportsTailCall() const { return SupportsTailCall; }
856 
857  bool allowsUnalignedMem() const { return !StrictAlign; }
858 
859  bool restrictIT() const { return RestrictIT; }
860 
861  const std::string & getCPUString() const { return CPUString; }
862 
863  bool isLittle() const { return IsLittle; }
864 
865  unsigned getMispredictionPenalty() const;
866 
867  /// Returns true if machine scheduler should be enabled.
868  bool enableMachineScheduler() const override;
869 
870  /// True for some subtargets at > -O0.
871  bool enablePostRAScheduler() const override;
872 
873  /// True for some subtargets at > -O0.
874  bool enablePostRAMachineScheduler() const override;
875 
876  /// Check whether this subtarget wants to use subregister liveness.
877  bool enableSubRegLiveness() const override;
878 
879  /// Enable use of alias analysis during code generation (during MI
880  /// scheduling, DAGCombine, etc.).
881  bool useAA() const override { return true; }
882 
883  // enableAtomicExpand- True if we need to expand our atomics.
884  bool enableAtomicExpand() const override;
885 
886  /// getInstrItins - Return the instruction itineraries based on subtarget
887  /// selection.
888  const InstrItineraryData *getInstrItineraryData() const override {
889  return &InstrItins;
890  }
891 
892  /// getStackAlignment - Returns the minimum alignment known to hold of the
893  /// stack frame on entry to the function and which must be maintained by every
894  /// function for this subtarget.
896 
897  unsigned getMaxInterleaveFactor() const { return MaxInterleaveFactor; }
898 
900 
902  return LdStMultipleTiming;
903  }
904 
907  }
908 
909  /// True if the GV will be accessed via an indirect symbol.
910  bool isGVIndirectSymbol(const GlobalValue *GV) const;
911 
912  /// Returns the constant pool modifier needed to access the GV.
913  bool isGVInGOT(const GlobalValue *GV) const;
914 
915  /// True if fast-isel is used.
916  bool useFastISel() const;
917 
918  /// Returns the correct return opcode for the current feature set.
919  /// Use BX if available to allow mixing thumb/arm code, but fall back
920  /// to plain mov pc,lr on ARMv4.
921  unsigned getReturnOpcode() const {
922  if (isThumb())
923  return ARM::tBX_RET;
924  if (hasV4TOps())
925  return ARM::BX_RET;
926  return ARM::MOVPCLR;
927  }
928 
929  /// Allow movt+movw for PIC global address calculation.
930  /// ELF does not have GOT relocations for movt+movw.
931  /// ROPI does not use GOT.
933  return isROPI() || !isTargetELF();
934  }
935 
936  unsigned getPrefLoopLogAlignment() const { return PrefLoopLogAlignment; }
937 
938  unsigned
941  return 1;
942  return MVEVectorCostFactor;
943  }
944 
946  unsigned PhysReg) const override;
947  unsigned getGPRAllocationOrder(const MachineFunction &MF) const;
948 
950 
951  bool hardenSlsRetBr() const { return HardenSlsRetBr; }
952  bool hardenSlsBlr() const { return HardenSlsBlr; }
953  bool hardenSlsNoComdat() const { return HardenSlsNoComdat; }
954 };
955 
956 } // end namespace llvm
957 
958 #endif // LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H
llvm::ARMSubtarget::HasCDEOps
bool HasCDEOps
Definition: ARMSubtarget.h:184
llvm::ARMSubtarget::HasV8_3aOps
bool HasV8_3aOps
Definition: ARMSubtarget.h:171
llvm::ARMSubtarget::SupportsTailCall
bool SupportsTailCall
SupportsTailCall - True if the OS supports tail call.
Definition: ARMSubtarget.h:266
llvm::ARMSubtarget::CortexA17
@ CortexA17
Definition: ARMSubtarget.h:53
llvm::ARMSubtarget::HasV5TEOps
bool HasV5TEOps
Definition: ARMSubtarget.h:162
llvm::ARMSubtarget::UseSjLjEH
bool UseSjLjEH
UseSjLjEH - If true, the target uses SjLj exception handling (e.g. iOS).
Definition: ARMSubtarget.h:468
llvm::ARMSubtarget::useSjLjEH
bool useSjLjEH() const
Definition: ARMSubtarget.h:730
llvm::ARMSubtarget::hasBaseDSP
bool hasBaseDSP() const
Definition: ARMSubtarget.h:734
llvm::ARMSubtarget::TM
const ARMBaseTargetMachine & TM
Definition: ARMSubtarget.h:537
llvm::ARMSubtarget::CortexR7
@ CortexR7
Definition: ARMSubtarget.h:76
llvm::ARMSubtarget::hasRAS
bool hasRAS() const
Definition: ARMSubtarget.h:671
llvm::ARMSubtarget::enableSubRegLiveness
bool enableSubRegLiveness() const override
Check whether this subtarget wants to use subregister liveness.
Definition: ARMSubtarget.cpp:392
llvm::TargetTransformInfo::TargetCostKind
TargetCostKind
The kind of cost model.
Definition: TargetTransformInfo.h:211
llvm::ARMSubtarget::HasVFPv3SP
bool HasVFPv3SP
Definition: ARMSubtarget.h:200
llvm::ARMSubtarget::HasCrypto
bool HasCrypto
HasCrypto - if true, processor supports Cryptography extensions.
Definition: ARMSubtarget.h:364
llvm::ARMSubtarget::hardenSlsRetBr
bool hardenSlsRetBr() const
Definition: ARMSubtarget.h:951
llvm::ARMSubtarget::hasV6MOps
bool hasV6MOps() const
Definition: ARMSubtarget.h:618
llvm::ARMSubtarget::HasAcquireRelease
bool HasAcquireRelease
HasAcquireRelease - True if the subtarget supports v8 atomics (LDA/LDAEX etc) instructions.
Definition: ARMSubtarget.h:306
llvm::ARMSubtarget::fixCMSE_CVE_2021_35465
bool fixCMSE_CVE_2021_35465() const
Definition: ARMSubtarget.h:949
llvm::ARMSubtarget::genLongCalls
bool genLongCalls() const
Definition: ARMSubtarget.h:732
llvm::ARMBaseTargetMachine
Definition: ARMTargetMachine.h:27
llvm::ARMSubtarget::hasV8_5aOps
bool hasV8_5aOps() const
Definition: ARMSubtarget.h:627
llvm::ARMSubtarget::hasSB
bool hasSB() const
Definition: ARMSubtarget.h:731
llvm::ARMSubtarget::hasV5TOps
bool hasV5TOps() const
Definition: ARMSubtarget.h:615
llvm
This file implements support for optimizing divisions by a constant.
Definition: AllocatorList.h:23
llvm::ARMSubtarget::ARMProcFamilyEnum
ARMProcFamilyEnum
Definition: ARMSubtarget.h:48
llvm::ARMSubtarget::SlowFPBrcc
bool SlowFPBrcc
SlowFPBrcc - True if floating point compare + branch is slow.
Definition: ARMSubtarget.h:235
llvm::ARMSubtarget::hasFusion
bool hasFusion() const
Return true if the CPU supports any kind of instruction fusion.
Definition: ARMSubtarget.h:750
llvm::ARMSubtarget::ARMv9a
@ ARMv9a
Definition: ARMSubtarget.h:127
llvm::ARMSubtarget::hasMVEFloatOps
bool hasMVEFloatOps() const
Definition: ARMSubtarget.h:637
llvm::ARMSubtarget::hasARMOps
bool hasARMOps() const
Definition: ARMSubtarget.h:659
llvm::ARMSubtarget::isTargetAndroid
bool isTargetAndroid() const
Definition: ARMSubtarget.h:807
llvm::ARMSubtarget::computeIssueWidth
void computeIssueWidth()
llvm::ARMSubtarget::HasSlowVDUP32
bool HasSlowVDUP32
If true, VMOV will be favored over VDUP.
Definition: ARMSubtarget.h:397
llvm::ARMSubtarget::getLegalizerInfo
const LegalizerInfo * getLegalizerInfo() const override
Definition: ARMSubtarget.cpp:135
llvm::ARMSubtarget::HasVMLxForwarding
bool HasVMLxForwarding
HasVMLxForwarding - If true, NEON has special multiplier accumulator forwarding to allow mul + mla be...
Definition: ARMSubtarget.h:232
llvm::ARMSubtarget::HasVirtualization
bool HasVirtualization
HasVirtualization - True if the subtarget supports the Virtualization extension.
Definition: ARMSubtarget.h:340
llvm::ARMSubtarget::enableMachineScheduler
bool enableMachineScheduler() const override
Returns true if machine scheduler should be enabled.
Definition: ARMSubtarget.cpp:379
llvm::ARMSubtarget::NoARM
bool NoARM
NoARM - True if subtarget does not support ARM mode execution.
Definition: ARMSubtarget.h:254
llvm::ARMSubtarget::hasV9_0aOps
bool hasV9_0aOps() const
Definition: ARMSubtarget.h:630
CallLowering.h
llvm::ARMSubtarget::HasV8_1MMainlineOps
bool HasV8_1MMainlineOps
Definition: ARMSubtarget.h:181
llvm::ARMSubtarget::CortexA57
@ CortexA57
Definition: ARMSubtarget.h:59
ARMGenSubtargetInfo
llvm::TargetOptions
Definition: TargetOptions.h:124
llvm::ARMSubtarget::HasVFPv2
bool HasVFPv2
HasVFPv2, HasVFPv3, HasVFPv4, HasFPARMv8, HasNEON - Specify what floating point ISAs are supported.
Definition: ARMSubtarget.h:188
llvm::Triple::isOSBinFormatCOFF
bool isOSBinFormatCOFF() const
Tests whether the OS uses the COFF binary format.
Definition: Triple.h:640
llvm::ARMSubtarget::GenLongCalls
bool GenLongCalls
Generate calls via indirect call instructions.
Definition: ARMSubtarget.h:459
llvm::ARMSubtarget
Definition: ARMSubtarget.h:46
llvm::ARMSubtarget::ARMv7m
@ ARMv7m
Definition: ARMSubtarget.h:112
llvm::ARMSubtarget::HasTrustZone
bool HasTrustZone
HasTrustZone - if true, processor supports TrustZone security extensions.
Definition: ARMSubtarget.h:352
llvm::ARMSubtarget::hasVMLxForwarding
bool hasVMLxForwarding() const
Definition: ARMSubtarget.h:697
llvm::ARMSubtarget::HasNEON
bool HasNEON
Definition: ARMSubtarget.h:192
llvm::ARMSubtarget::isAClass
bool isAClass() const
Definition: ARMSubtarget.h:828
llvm::ARMSubtarget::hasFPRegs64
bool hasFPRegs64() const
Definition: ARMSubtarget.h:641
llvm::ARMSubtarget::HasFPARMv8SP
bool HasFPARMv8SP
Definition: ARMSubtarget.h:202
llvm::ARMSubtarget::isTargetWatchOS
bool isTargetWatchOS() const
Definition: ARMSubtarget.h:758
llvm::ARMSubtarget::getMispredictionPenalty
unsigned getMispredictionPenalty() const
Definition: ARMSubtarget.cpp:375
llvm::ARMSubtarget::HasFullDataBarrier
bool HasFullDataBarrier
HasFullDataBarrier - True if the subtarget supports DFB data barrier instruction.
Definition: ARMSubtarget.h:299
llvm::ARMSubtarget::HasThumb2
bool HasThumb2
HasThumb2 - True if Thumb2 instructions are supported.
Definition: ARMSubtarget.h:251
llvm::ARMSubtarget::getPartialUpdateClearance
unsigned getPartialUpdateClearance() const
Definition: ARMSubtarget.h:899
llvm::ARMSubtarget::isCortexM3
bool isCortexM3() const
Definition: ARMSubtarget.h:652
llvm::ARMSubtarget::Has8MSecExt
bool Has8MSecExt
Has8MSecExt - if true, processor supports ARMv8-M Security Extensions.
Definition: ARMSubtarget.h:355
llvm::ARMSubtarget::Pref32BitThumb
bool Pref32BitThumb
Pref32BitThumb - If true, codegen would prefer 32-bit Thumb instructions over 16-bit ones.
Definition: ARMSubtarget.h:310
llvm::ARMSubtarget::hasFPARMv8Base
bool hasFPARMv8Base() const
Definition: ARMSubtarget.h:664
llvm::ARMSubtarget::StrictAlign
bool StrictAlign
StrictAlign - If true, the subtarget disallows unaligned memory accesses for some types.
Definition: ARMSubtarget.h:445
llvm::ARMSubtarget::ARMProcFamily
ARMProcFamilyEnum ARMProcFamily
ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.
Definition: ARMSubtarget.h:149
llvm::ARMSubtarget::hasSHA2
bool hasSHA2() const
Definition: ARMSubtarget.h:666
llvm::ARMSubtarget::isReadTPHard
bool isReadTPHard() const
Definition: ARMSubtarget.h:829
llvm::Triple::MuslEABIHF
@ MuslEABIHF
Definition: Triple.h:223
llvm::ARMSubtarget::hasFP16FML
bool hasFP16FML() const
Definition: ARMSubtarget.h:744
RegisterBankInfo.h
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:45
llvm::ARMSubtarget::useFPVFMx
bool useFPVFMx() const
Definition: ARMSubtarget.h:692
llvm::ARMSubtarget::HasFPARMv8D16
bool HasFPARMv8D16
Definition: ARMSubtarget.h:205
llvm::ARMSubtarget::hasBF16
bool hasBF16() const
Definition: ARMSubtarget.h:745
llvm::TargetTransformInfo::TCK_CodeSize
@ TCK_CodeSize
Instruction code size.
Definition: TargetTransformInfo.h:214
llvm::ARMSubtarget::hasV6T2Ops
bool hasV6T2Ops() const
Definition: ARMSubtarget.h:620
llvm::ARMSubtarget::getTargetTriple
const Triple & getTargetTriple() const
Definition: ARMSubtarget.h:754
llvm::ARMSubtarget::HasV8MMainlineOps
bool HasV8MMainlineOps
Definition: ARMSubtarget.h:180
llvm::ARMSubtarget::isRWPI
bool isRWPI() const
Definition: ARMSubtarget.cpp:351
llvm::ARMSubtarget::HardenSlsBlr
bool HardenSlsBlr
Harden against Straight Line Speculation for indirect calls.
Definition: ARMSubtarget.h:485
llvm::ARMSubtarget::ParseSubtargetFeatures
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
llvm::ARMSubtarget::ARMv7r
@ ARMv7r
Definition: ARMSubtarget.h:113
llvm::ARMSubtarget::getPreISelOperandLatencyAdjustment
int getPreISelOperandLatencyAdjustment() const
Definition: ARMSubtarget.h:905
llvm::ARMSubtarget::hasV8_3aOps
bool hasV8_3aOps() const
Definition: ARMSubtarget.h:625
llvm::ARMSubtarget::HasRAS
bool HasRAS
HasRAS - if true, the processor supports RAS extensions.
Definition: ARMSubtarget.h:370
llvm::ARMTargetLowering
Definition: ARMISelLowering.h:389
llvm::ARMSubtarget::getInstrItineraryData
const InstrItineraryData * getInstrItineraryData() const override
getInstrItins - Return the instruction itineraries based on subtarget selection.
Definition: ARMSubtarget.h:888
llvm::ARMSubtarget::HasFuseAES
bool HasFuseAES
HasFuseAES - if true, processor executes back to back AES instruction pairs faster.
Definition: ARMSubtarget.h:384
llvm::ARMSubtarget::hasThumb2
bool hasThumb2() const
Definition: ARMSubtarget.h:825
llvm::ARMSubtarget::getTargetLowering
const ARMTargetLowering * getTargetLowering() const override
Definition: ARMSubtarget.h:575
llvm::ARMSubtarget::NegativeImmediates
bool NegativeImmediates
Implicitly convert an instruction to a different one if its immediates cannot be encoded.
Definition: ARMSubtarget.h:475
llvm::ARMSubtarget::ARMv83a
@ ARMv83a
Definition: ARMSubtarget.h:117
llvm::ARMSubtarget::HasRetAddrStack
bool HasRetAddrStack
HasRetAddrStack - Some processors perform return stack prediction.
Definition: ARMSubtarget.h:327
llvm::ARMSubtarget::hasDivideInARMMode
bool hasDivideInARMMode() const
Definition: ARMSubtarget.h:680
llvm::ARMSubtarget::getInstrInfo
const ARMBaseInstrInfo * getInstrInfo() const override
Definition: ARMSubtarget.h:571
llvm::ARMSubtarget::hasAES
bool hasAES() const
Definition: ARMSubtarget.h:667
llvm::ARMSubtarget::CortexM7
@ CortexM7
Definition: ARMSubtarget.h:71
llvm::ARMSubtarget::HasVFPv4SP
bool HasVFPv4SP
Definition: ARMSubtarget.h:201
llvm::ARMSubtarget::hasMVEIntegerOps
bool hasMVEIntegerOps() const
Definition: ARMSubtarget.h:636
llvm::Triple::isOSLinux
bool isOSLinux() const
Tests whether the OS is Linux.
Definition: Triple.h:598
llvm::ARMSubtarget::getSelectionDAGInfo
const ARMSelectionDAGInfo * getSelectionDAGInfo() const override
Definition: ARMSubtarget.h:567
llvm::ARMSubtarget::HasVMLxHazards
bool HasVMLxHazards
If true, VFP/NEON VMLA/VMLS have special RAW hazards.
Definition: ARMSubtarget.h:428
llvm::ARMSubtarget::ARMv7a
@ ARMv7a
Definition: ARMSubtarget.h:110
llvm::ARMSubtarget::hasV9_2aOps
bool hasV9_2aOps() const
Definition: ARMSubtarget.h:632
llvm::ARMSubtarget::getStackAlignment
Align getStackAlignment() const
getStackAlignment - Returns the minimum alignment known to hold of the stack frame on entry to the fu...
Definition: ARMSubtarget.h:895
llvm::ARMSubtarget::hasSlowVGETLNi32
bool hasSlowVGETLNi32() const
Definition: ARMSubtarget.h:706
llvm::ARMSubtarget::hardenSlsNoComdat
bool hardenSlsNoComdat() const
Definition: ARMSubtarget.h:953
llvm::ARMSubtarget::HasBF16
bool HasBF16
HasBF16 - True if subtarget supports BFloat16 floating point operations.
Definition: ARMSubtarget.h:278
llvm::ARMSubtarget::expandMLx
bool expandMLx() const
Definition: ARMSubtarget.h:710
llvm::ARMSubtarget::hasV9_1aOps
bool hasV9_1aOps() const
Definition: ARMSubtarget.h:631
llvm::ARMSubtarget::hasV8_6aOps
bool hasV8_6aOps() const
Definition: ARMSubtarget.h:628
llvm::ARMSubtarget::HasV8_1aOps
bool HasV8_1aOps
Definition: ARMSubtarget.h:169
llvm::ARMSubtarget::isTargetLinux
bool isTargetLinux() const
Definition: ARMSubtarget.h:760
llvm::ARMSubtarget::supportsTailCall
bool supportsTailCall() const
Definition: ARMSubtarget.h:855
llvm::ARMSubtarget::useNEONForFPMovs
bool useNEONForFPMovs() const
Definition: ARMSubtarget.h:718
llvm::ARMSubtarget::getMaxInlineSizeThreshold
unsigned getMaxInlineSizeThreshold() const
getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size that still makes it profitable t...
Definition: ARMSubtarget.h:549
llvm::ARMSubtarget::ARMLdStMultipleTiming
ARMLdStMultipleTiming
What kind of timing do load multiple/store multiple instructions have.
Definition: ARMSubtarget.h:134
llvm::ARMSubtarget::UseMISched
bool UseMISched
UseMISched - True if MachineScheduler should be used for this subtarget.
Definition: ARMSubtarget.h:244
LegalizerInfo.h
llvm::ARMSubtarget::hasSlowVDUP32
bool hasSlowVDUP32() const
Definition: ARMSubtarget.h:707
llvm::ARMSubtarget::RClass
@ RClass
Definition: ARMSubtarget.h:91
llvm::ARMSubtarget::HasMVEFloatOps
bool HasMVEFloatOps
Definition: ARMSubtarget.h:183
llvm::ARMSubtarget::PreferISHST
bool PreferISHST
If true, ISHST barriers will be used for Release semantics.
Definition: ARMSubtarget.h:403
llvm::ARMSubtarget::Kryo
@ Kryo
Definition: ARMSubtarget.h:80
llvm::ARMSubtarget::isTargetWatchABI
bool isTargetWatchABI() const
Definition: ARMSubtarget.h:759
llvm::ARMSubtarget::ARMv2
@ ARMv2
Definition: ARMSubtarget.h:94
llvm::Triple::GNUEABI
@ GNUEABI
Definition: Triple.h:213
llvm::ARMSubtarget::ARMv92a
@ ARMv92a
Definition: ARMSubtarget.h:129
llvm::ARMSubtarget::OptMinSize
bool OptMinSize
OptMinSize - True if we're optimising for minimum code size, equal to the function attribute.
Definition: ARMSubtarget.h:520
llvm::ARMSubtarget::HasAES
bool HasAES
HasAES - if true, processor supports AES.
Definition: ARMSubtarget.h:361
llvm::ARMSubtarget::ARMv84a
@ ARMv84a
Definition: ARMSubtarget.h:118
llvm::ARMSubtarget::HasVFPv2SP
bool HasVFPv2SP
Versions of the VFP flags restricted to single precision, or to 16 d-registers, or both.
Definition: ARMSubtarget.h:199
llvm::ARMSubtarget::HasV6KOps
bool HasV6KOps
Definition: ARMSubtarget.h:165
llvm::ARMSubtarget::hasDSP
bool hasDSP() const
Definition: ARMSubtarget.h:728
llvm::ARMSubtarget::HasV9_0aOps
bool HasV9_0aOps
Definition: ARMSubtarget.h:176
llvm::ARMSubtarget::hasD32
bool hasD32() const
Definition: ARMSubtarget.h:742
llvm::ARMSubtarget::HasVFPv4D16
bool HasVFPv4D16
Definition: ARMSubtarget.h:204
llvm::ARMSubtarget::avoidMOVsShifterOperand
bool avoidMOVsShifterOperand() const
Definition: ARMSubtarget.h:724
llvm::ARMSubtarget::preferVMOVSR
bool preferVMOVSR() const
Definition: ARMSubtarget.h:708
llvm::ARMSubtarget::NeoverseN1
@ NeoverseN1
Definition: ARMSubtarget.h:81
llvm::ARMSubtarget::splitFramePushPop
bool splitFramePushPop(const MachineFunction &MF) const
Returns true if the frame setup is split into two separate pushes (first r0-r7,lr then r8-r11),...
Definition: ARMSubtarget.h:845
llvm::ARMSubtarget::hasLOB
bool hasLOB() const
Definition: ARMSubtarget.h:672
llvm::ARMSubtarget::isTargetMuslAEABI
bool isTargetMuslAEABI() const
Definition: ARMSubtarget.h:786
ARMConstantPoolValue.h
llvm::ARMSubtarget::HasZeroCycleZeroing
bool HasZeroCycleZeroing
If true, the instructions "vmov.i32 d0, #0" and "vmov.i32 q0, #0" are particularly effective at zeroi...
Definition: ARMSubtarget.h:377
llvm::ARMSubtarget::ARMv6sm
@ ARMv6sm
Definition: ARMSubtarget.h:108
llvm::ARMSubtarget::ARMv7ve
@ ARMv7ve
Definition: ARMSubtarget.h:114
llvm::Triple::isAndroid
bool isAndroid() const
Tests whether the target is Android.
Definition: Triple.h:676
llvm::ARMSubtarget::hasMPExtension
bool hasMPExtension() const
Definition: ARMSubtarget.h:727
MCInstrItineraries.h
llvm::ARMSubtarget::CortexA73
@ CortexA73
Definition: ARMSubtarget.h:62
llvm::Triple::isOSBinFormatELF
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:635
llvm::ARMSubtarget::ARMv6
@ ARMv6
Definition: ARMSubtarget.h:104
TargetMachine.h
llvm::ARMSubtarget::useSoftFloat
bool useSoftFloat() const
Definition: ARMSubtarget.h:820
llvm::ARMSubtarget::CortexR5
@ CortexR5
Definition: ARMSubtarget.h:74
llvm::ARMSubtarget::NeoverseN2
@ NeoverseN2
Definition: ARMSubtarget.h:82
llvm::ARMSubtarget::AClass
@ AClass
Definition: ARMSubtarget.h:89
llvm::ARMSubtarget::IsLittle
bool IsLittle
IsLittle - The target is Little Endian.
Definition: ARMSubtarget.h:523
llvm::ARMSubtarget::useAA
bool useAA() const override
Enable use of alias analysis during code generation (during MI scheduling, DAGCombine,...
Definition: ARMSubtarget.h:881
llvm::ARMSubtarget::useFPVMLx
bool useFPVMLx() const
Definition: ARMSubtarget.h:691
llvm::ARMSubtarget::isFPBrccSlow
bool isFPBrccSlow() const
Definition: ARMSubtarget.h:698
llvm::ARMSubtarget::isLikeA9
bool isLikeA9() const
Definition: ARMSubtarget.h:654
llvm::ARMSubtarget::SchedModel
MCSchedModel SchedModel
SchedModel - Processor specific instruction costs.
Definition: ARMSubtarget.h:529
llvm::ARMSubtarget::ARMv8r
@ ARMv8r
Definition: ARMSubtarget.h:125
llvm::Triple::isOSDarwin
bool isOSDarwin() const
isOSDarwin - Is this a "Darwin" OS (macOS, iOS, tvOS or watchOS).
Definition: Triple.h:487
llvm::ARMSubtarget::disablePostRAScheduler
bool disablePostRAScheduler() const
Definition: ARMSubtarget.h:819
llvm::ARMSubtarget::HasVFPv3
bool HasVFPv3
Definition: ARMSubtarget.h:189
llvm::ARMSubtarget::enableAtomicExpand
bool enableAtomicExpand() const override
Definition: ARMSubtarget.cpp:418
llvm::ARMSubtarget::MaxInterleaveFactor
unsigned MaxInterleaveFactor
Definition: ARMSubtarget.h:497
llvm::ARMSubtarget::isCortexM7
bool isCortexM7() const
Definition: ARMSubtarget.h:653
llvm::Legalizer
Definition: Legalizer.h:31
llvm::ARMSubtarget::isCortexA5
bool isCortexA5() const
Definition: ARMSubtarget.h:646
llvm::ARMSubtarget::HasV4TOps
bool HasV4TOps
HasV4TOps, HasV5TOps, HasV5TEOps, HasV6Ops, HasV6MOps, HasV6KOps, HasV6T2Ops, HasV7Ops,...
Definition: ARMSubtarget.h:160
llvm::ARMSubtarget::CortexA72
@ CortexA72
Definition: ARMSubtarget.h:61
llvm::ARMSubtarget::hasV6KOps
bool hasV6KOps() const
Definition: ARMSubtarget.h:619
llvm::ARMSubtarget::DisablePostRAScheduler
bool DisablePostRAScheduler
DisablePostRAScheduler - False if scheduling should happen again after register allocation.
Definition: ARMSubtarget.h:248
llvm::ARMSubtarget::hasBranchPredictor
bool hasBranchPredictor() const
Definition: ARMSubtarget.h:726
llvm::ARMSubtarget::checkVLDnAccessAlignment
bool checkVLDnAccessAlignment() const
Definition: ARMSubtarget.h:719
llvm::ARMSubtarget::useMulOps
bool useMulOps() const
Definition: ARMSubtarget.h:690
llvm::ARMSubtarget::DoubleIssue
@ DoubleIssue
Can load/store 2 registers/cycle.
Definition: ARMSubtarget.h:136
llvm::ARMSubtarget::useMovt
bool useMovt() const
Definition: ARMSubtarget.cpp:428
llvm::ARMSubtarget::isCortexA15
bool isCortexA15() const
Definition: ARMSubtarget.h:650
llvm::ARMSubtarget::hasCrypto
bool hasCrypto() const
Definition: ARMSubtarget.h:668
llvm::ARMSubtarget::isTargetHardFloat
bool isTargetHardFloat() const
Definition: ARMSubtarget.cpp:331
llvm::ARMSubtarget::nonpipelinedVFP
bool nonpipelinedVFP() const
Definition: ARMSubtarget.h:720
llvm::ARMSubtarget::ARMArchEnum
ARMArchEnum
Definition: ARMSubtarget.h:93
llvm::ARMSubtarget::ReadTPHard
bool ReadTPHard
Definition: ARMSubtarget.h:431
llvm::ARMSubtarget::isAAPCS16_ABI
bool isAAPCS16_ABI() const
Definition: ARMSubtarget.cpp:342
llvm::ARMSubtarget::CortexA55
@ CortexA55
Definition: ARMSubtarget.h:58
llvm::ARMSubtarget::HardenSlsNoComdat
bool HardenSlsNoComdat
Generate thunk code for SLS mitigation in the normal text section.
Definition: ARMSubtarget.h:488
llvm::ARMSubtarget::HasHardwareDivideInARM
bool HasHardwareDivideInARM
HasHardwareDivideInARM - True if subtarget supports [su]div in ARM mode.
Definition: ARMSubtarget.h:291
llvm::ARMSubtarget::CheckVLDnAlign
bool CheckVLDnAlign
If true, VLDn instructions take an extra cycle for unaligned accesses.
Definition: ARMSubtarget.h:437
llvm::ARMSubtarget::HasSHA2
bool HasSHA2
HasSHA2 - if true, processor supports SHA1 and SHA256.
Definition: ARMSubtarget.h:358
llvm::ARMSubtarget::ARMv5
@ ARMv5
Definition: ARMSubtarget.h:100
llvm::ARMSubtarget::HasDSP
bool HasDSP
HasDSP - If true, the subtarget supports the DSP (saturating arith and such) instructions.
Definition: ARMSubtarget.h:453
llvm::ARMSubtarget::ExpandMLx
bool ExpandMLx
If true, run the MLx expansion pass.
Definition: ARMSubtarget.h:425
llvm::ARMSubtarget::DoubleIssueCheckUnalignedAccess
@ DoubleIssueCheckUnalignedAccess
Can load/store 2 registers/cycle, but needs an extra cycle if the access is not 64-bit aligned.
Definition: ARMSubtarget.h:139
llvm::Triple::isOSBinFormatMachO
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
Definition: Triple.h:648
llvm::ARMSubtarget::UseSoftFloat
bool UseSoftFloat
UseSoftFloat - True if we're using software floating point features.
Definition: ARMSubtarget.h:241
llvm::ARMSubtarget::HasFP16
bool HasFP16
HasFP16 - True if subtarget supports half-precision FP conversions.
Definition: ARMSubtarget.h:269
llvm::X86AS::FS
@ FS
Definition: X86.h:188
llvm::ARMSubtarget::ARMv81a
@ ARMv81a
Definition: ARMSubtarget.h:115
llvm::ARMSubtarget::DontWidenVMOVS
bool DontWidenVMOVS
If true, VMOVS will never be widened to VMOVD.
Definition: ARMSubtarget.h:419
llvm::ARMSubtarget::ARMv5tej
@ ARMv5tej
Definition: ARMSubtarget.h:103
llvm::ARMSubtarget::isTargetAEABI
bool isTargetAEABI() const
Definition: ARMSubtarget.h:776
llvm::ARMSubtarget::HasV6Ops
bool HasV6Ops
Definition: ARMSubtarget.h:163
llvm::ARMSubtarget::hasSlowOddRegister
bool hasSlowOddRegister() const
Definition: ARMSubtarget.h:712
llvm::ARMSubtarget::PrefLoopLogAlignment
unsigned PrefLoopLogAlignment
What alignment is preferred for loop bodies, in log2(bytes).
Definition: ARMSubtarget.h:511
llvm::ARMSubtarget::HasDotProd
bool HasDotProd
HasDotProd - True if the ARMv8.2A dot product instructions are supported.
Definition: ARMSubtarget.h:211
llvm::ARMSubtarget::CortexA78C
@ CortexA78C
Definition: ARMSubtarget.h:67
llvm::ARMSubtarget::ARMv4
@ ARMv4
Definition: ARMSubtarget.h:98
llvm::ARMSubtarget::enablePostRAScheduler
bool enablePostRAScheduler() const override
True for some subtargets at > -O0.
Definition: ARMSubtarget.cpp:401
llvm::ARMSubtarget::isKrait
bool isKrait() const
Definition: ARMSubtarget.h:656
llvm::ARMSubtarget::hasV6Ops
bool hasV6Ops() const
Definition: ARMSubtarget.h:617
llvm::Triple::MuslEABI
@ MuslEABI
Definition: Triple.h:222
llvm::ARMSubtarget::has8MSecExt
bool has8MSecExt() const
Definition: ARMSubtarget.h:702
Align
uint64_t Align
Definition: ELFObjHandler.cpp:83
llvm::ARMSubtarget::hasCDEOps
bool hasCDEOps() const
Definition: ARMSubtarget.h:638
llvm::ARMSubtarget::hasFP64
bool hasFP64() const
Definition: ARMSubtarget.h:699
llvm::ARMSubtarget::HasMVEIntegerOps
bool HasMVEIntegerOps
Definition: ARMSubtarget.h:182
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::ARMSubtarget::ARMv8a
@ ARMv8a
Definition: ARMSubtarget.h:122
llvm::ARMSubtarget::HasFPARMv8
bool HasFPARMv8
Definition: ARMSubtarget.h:191
llvm::ARMSubtarget::CortexA7
@ CortexA7
Definition: ARMSubtarget.h:60
llvm::ARMSubtarget::ARMv8mBaseline
@ ARMv8mBaseline
Definition: ARMSubtarget.h:123
llvm::ARMSubtarget::HasFuseLiterals
bool HasFuseLiterals
HasFuseLiterals - if true, processor executes back to back bottom and top halves of literal generatio...
Definition: ARMSubtarget.h:388
llvm::ARMSubtarget::getMVEVectorCostFactor
unsigned getMVEVectorCostFactor(TargetTransformInfo::TargetCostKind CostKind) const
Definition: ARMSubtarget.h:939
llvm::Triple::isOSNaCl
bool isOSNaCl() const
Tests whether the OS is NaCl (Native Client)
Definition: Triple.h:593
llvm::ARMSubtarget::ARMv3
@ ARMv3
Definition: ARMSubtarget.h:96
llvm::ARMSubtarget::getRegBankInfo
const RegisterBankInfo * getRegBankInfo() const override
Definition: ARMSubtarget.cpp:139
llvm::ARMSubtarget::hasVFP3Base
bool hasVFP3Base() const
Definition: ARMSubtarget.h:662
llvm::ARMSubtarget::hasFP16
bool hasFP16() const
Definition: ARMSubtarget.h:741
llvm::ARMSubtarget::isSwift
bool isSwift() const
Definition: ARMSubtarget.h:651
llvm::ARMSubtarget::FixCMSE_CVE_2021_35465
bool FixCMSE_CVE_2021_35465
Mitigate against the cve-2021-35465 security vulnurability.
Definition: ARMSubtarget.h:478
llvm::ARMSubtarget::HasV6T2Ops
bool HasV6T2Ops
Definition: ARMSubtarget.h:166
llvm::ARMSubtarget::HasSlowVGETLNi32
bool HasSlowVGETLNi32
If true, VMOV will be favored over VGETLNi32.
Definition: ARMSubtarget.h:394
llvm::ARMSubtarget::ARMv91a
@ ARMv91a
Definition: ARMSubtarget.h:128
llvm::ARMSubtarget::ARMProcClassEnum
ARMProcClassEnum
Definition: ARMSubtarget.h:86
llvm::ARMSubtarget::HasFullFP16
bool HasFullFP16
HasFullFP16 - True if subtarget supports half-precision FP operations.
Definition: ARMSubtarget.h:272
llvm::ARMSubtarget::HasV8Ops
bool HasV8Ops
Definition: ARMSubtarget.h:168
llvm::ARMSubtarget::TargetTriple
Triple TargetTriple
TargetTriple - What processor and OS we're targeting.
Definition: ARMSubtarget.h:526
llvm::ARMSubtarget::ARMv6t2
@ ARMv6t2
Definition: ARMSubtarget.h:109
InstructionSelector.h
llvm::TargetOptions::DisableFramePointerElim
bool DisableFramePointerElim(const MachineFunction &MF) const
DisableFramePointerElim - This returns true if frame pointer elimination optimization should be disab...
Definition: TargetOptionsImpl.cpp:24
ARMSelectionDAGInfo.h
llvm::ARMSubtarget::SlowLoadDSubregister
bool SlowLoadDSubregister
If true, loading into a D subregister will be penalized.
Definition: ARMSubtarget.h:410
llvm::ARMSubtarget::hasV8_4aOps
bool hasV8_4aOps() const
Definition: ARMSubtarget.h:626
llvm::ARMSubtarget::CortexA9
@ CortexA9
Definition: ARMSubtarget.h:69
llvm::ARMSubtarget::PreferVMOVSR
bool PreferVMOVSR
If true, VMOVSR will be favored over VMOVDRR.
Definition: ARMSubtarget.h:400
llvm::ARMSubtarget::hasFPRegs16
bool hasFPRegs16() const
Definition: ARMSubtarget.h:640
llvm::ARMSubtarget::HasFPRegs16
bool HasFPRegs16
Definition: ARMSubtarget.h:194
llvm::ARMSubtarget::hardenSlsBlr
bool hardenSlsBlr() const
Definition: ARMSubtarget.h:952
llvm::ARMSubtarget::hasTrustZone
bool hasTrustZone() const
Definition: ARMSubtarget.h:701
llvm::RegisterBankInfo
Holds all the information related to register banks.
Definition: RegisterBankInfo.h:39
llvm::GlobalValue
Definition: GlobalValue.h:44
llvm::InstructionSelector
Provides the logic to select generic machine instructions.
Definition: InstructionSelector.h:423
llvm::ARMSubtarget::CheapPredicableCPSRDef
bool CheapPredicableCPSRDef
CheapPredicableCPSRDef - If true, disable +1 predication cost for instructions updating CPSR.
Definition: ARMSubtarget.h:319
ARMBaseRegisterInfo.h
MCSchedule.h
llvm::ARMSubtarget::HasV9_1aOps
bool HasV9_1aOps
Definition: ARMSubtarget.h:177
llvm::ARMSubtarget::isThumb1Only
bool isThumb1Only() const
Definition: ARMSubtarget.h:823
llvm::ARMSubtarget::getCPUString
const std::string & getCPUString() const
Definition: ARMSubtarget.h:861
llvm::ARMSubtarget::cheapPredicableCPSRDef
bool cheapPredicableCPSRDef() const
Definition: ARMSubtarget.h:723
llvm::ARMSubtarget::allowPositionIndependentMovt
bool allowPositionIndependentMovt() const
Allow movt+movw for PIC global address calculation.
Definition: ARMSubtarget.h:932
llvm::ARMSubtarget::isRClass
bool isRClass() const
Definition: ARMSubtarget.h:827
llvm::ARMSubtarget::hasMuxedUnits
bool hasMuxedUnits() const
Definition: ARMSubtarget.h:715
llvm::ARMSubtarget::preferISHSTBarriers
bool preferISHSTBarriers() const
Definition: ARMSubtarget.h:709
llvm::ARMSubtarget::InstrItins
InstrItineraryData InstrItins
Selected instruction itineraries (one entry per itinerary class.)
Definition: ARMSubtarget.h:532
llvm::ARMSubtarget::hasZeroCycleZeroing
bool hasZeroCycleZeroing() const
Definition: ARMSubtarget.h:703
llvm::ARMSubtarget::LdStMultipleTiming
ARMLdStMultipleTiming LdStMultipleTiming
What kind of timing do load multiple/store multiple have (double issue, single issue etc).
Definition: ARMSubtarget.h:504
llvm::ARMSubtarget::ARMv82a
@ ARMv82a
Definition: ARMSubtarget.h:116
llvm::ARMSubtarget::hasPerfMon
bool hasPerfMon() const
Definition: ARMSubtarget.h:700
llvm::ARMSubtarget::prefers32BitThumb
bool prefers32BitThumb() const
Definition: ARMSubtarget.h:721
llvm::ARMSubtarget::hasFPAO
bool hasFPAO() const
Definition: ARMSubtarget.h:704
llvm::ARMSubtarget::HasV8_6aOps
bool HasV8_6aOps
Definition: ARMSubtarget.h:174
llvm::ARMSubtarget::ARMSubtarget
ARMSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS, const ARMBaseTargetMachine &TM, bool IsLittle, bool MinSize=false)
This constructor initializes the data members to match that of the specified triple.
Definition: ARMSubtarget.cpp:96
llvm::ARMSubtarget::isR9Reserved
bool isR9Reserved() const
Definition: ARMSubtarget.h:831
llvm::ARMSubtarget::getLdStMultipleTiming
ARMLdStMultipleTiming getLdStMultipleTiming() const
Definition: ARMSubtarget.h:901
llvm::ARMSubtarget::CortexA75
@ CortexA75
Definition: ARMSubtarget.h:63
llvm::ARMSubtarget::GenExecuteOnly
bool GenExecuteOnly
Generate code that does not contain data access to code sections.
Definition: ARMSubtarget.h:462
llvm::ARMSubtarget::isTargetNetBSD
bool isTargetNetBSD() const
Definition: ARMSubtarget.h:762
llvm::ARMSubtarget::isMClass
bool isMClass() const
Definition: ARMSubtarget.h:826
llvm::ARMSubtarget::stackAlignment
Align stackAlignment
stackAlignment - The minimum alignment known to hold of the stack frame on entry to the function and ...
Definition: ARMSubtarget.h:492
llvm::ARMSubtarget::HasV6MOps
bool HasV6MOps
Definition: ARMSubtarget.h:164
llvm::ARMSubtarget::avoidCPSRPartialUpdate
bool avoidCPSRPartialUpdate() const
Definition: ARMSubtarget.h:722
llvm::ARMSubtarget::HasBranchPredictor
bool HasBranchPredictor
HasBranchPredictor - True if the subtarget has a branch predictor.
Definition: ARMSubtarget.h:332
llvm::ARMSubtarget::initializeSubtargetDependencies
ARMSubtarget & initializeSubtargetDependencies(StringRef CPU, StringRef FS)
initializeSubtargetDependencies - Initializes using a CPU and feature string so that we can use initi...
Definition: ARMSubtarget.cpp:80
llvm::ARMSubtarget::InThumbMode
bool InThumbMode
InThumbMode - True if compiling for Thumb, false for ARM.
Definition: ARMSubtarget.h:238
llvm::ARMSubtarget::SlowFPVFMx
bool SlowFPVFMx
SlowFPVFMx - If the VFP4 / NEON instructions are available, indicates whether the FP VFM[AS] instruct...
Definition: ARMSubtarget.h:228
llvm::ARMSubtarget::isProfitableToUnpredicate
bool isProfitableToUnpredicate() const
Definition: ARMSubtarget.h:705
llvm::ARMSubtarget::HasHardwareDivideInThumb
bool HasHardwareDivideInThumb
HasHardwareDivide - True if subtarget supports [su]div in Thumb mode.
Definition: ARMSubtarget.h:288
llvm::ARMBaseInstrInfo
Definition: ARMBaseInstrInfo.h:37
llvm::ARMSubtarget::getFramePointerReg
MCPhysReg getFramePointerReg() const
Definition: ARMSubtarget.h:835
llvm::ARMSubtarget::isTargetIOS
bool isTargetIOS() const
Definition: ARMSubtarget.h:757
llvm::ARMSubtarget::dontWidenVMOVS
bool dontWidenVMOVS() const
Definition: ARMSubtarget.h:716
llvm::Triple::isWatchABI
bool isWatchABI() const
Definition: Triple.h:480
llvm::ARMSubtarget::CPUString
std::string CPUString
CPUString - String name of used CPU.
Definition: ARMSubtarget.h:495
llvm::ARMSubtarget::isTargetELF
bool isTargetELF() const
Definition: ARMSubtarget.h:766
llvm::ARMSubtarget::hasV7Ops
bool hasV7Ops() const
Definition: ARMSubtarget.h:621
llvm::ARMSubtarget::NoMovt
bool NoMovt
NoMovt - True if MOVT / MOVW pairs are not used for materialization of 32-bit imms (including global ...
Definition: ARMSubtarget.h:261
llvm::ARMSubtarget::useSplatVFPToNeon
bool useSplatVFPToNeon() const
Definition: ARMSubtarget.h:717
llvm::ARMSubtarget::MVEVectorCostFactor
unsigned MVEVectorCostFactor
The cost factor for MVE instructions, representing the multiple beats an.
Definition: ARMSubtarget.h:516
llvm::ARMSubtarget::Options
const TargetOptions & Options
Options passed via command line that could influence the target.
Definition: ARMSubtarget.h:535
llvm::ARMSubtarget::RestrictIT
bool RestrictIT
RestrictIT - If true, the subtarget disallows generation of deprecated IT blocks to conform to ARMv8 ...
Definition: ARMSubtarget.h:449
llvm::ARMSubtarget::hasDataBarrier
bool hasDataBarrier() const
Definition: ARMSubtarget.h:681
llvm::ARMSubtarget::getFrameLowering
const ARMFrameLowering * getFrameLowering() const override
Definition: ARMSubtarget.h:579
llvm::ARMSubtarget::isTargetCOFF
bool isTargetCOFF() const
Definition: ARMSubtarget.h:765
llvm::TargetMachine::Options
TargetOptions Options
Definition: TargetMachine.h:120
llvm::ARMSubtarget::isROPI
bool isROPI() const
Definition: ARMSubtarget.cpp:347
llvm::ARMSubtarget::useNaClTrap
bool useNaClTrap() const
Definition: ARMSubtarget.h:729
llvm::ARMFrameLowering
Definition: ARMFrameLowering.h:21
llvm::ARMSubtarget::CortexA77
@ CortexA77
Definition: ARMSubtarget.h:65
llvm::ARMSubtarget::hasSlowLoadDSubregister
bool hasSlowLoadDSubregister() const
Definition: ARMSubtarget.h:713
ARMBaseInstrInfo.h
llvm::ARMSubtarget::ARMv4t
@ ARMv4t
Definition: ARMSubtarget.h:99
llvm::ARMSubtarget::hasFullFP16
bool hasFullFP16() const
Definition: ARMSubtarget.h:743
llvm::ARMSubtarget::enablePostRAMachineScheduler
bool enablePostRAMachineScheduler() const override
True for some subtargets at > -O0.
Definition: ARMSubtarget.cpp:410
llvm::ARMSubtarget::allowsUnalignedMem
bool allowsUnalignedMem() const
Definition: ARMSubtarget.h:857
llvm::ARMSubtarget::CortexM3
@ CortexM3
Definition: ARMSubtarget.h:70
llvm::ARMSubtarget::ARMv7em
@ ARMv7em
Definition: ARMSubtarget.h:111
llvm::ARMSubtarget::useNEONForSinglePrecisionFP
bool useNEONForSinglePrecisionFP() const
Definition: ARMSubtarget.h:675
llvm::ARMSubtarget::isLittle
bool isLittle() const
Definition: ARMSubtarget.h:863
llvm::ARMSubtarget::ARMv81mMainline
@ ARMv81mMainline
Definition: ARMSubtarget.h:126
llvm::ARMSubtarget::useFastISel
bool useFastISel() const
True if fast-isel is used.
Definition: ARMSubtarget.cpp:436
llvm::ARMSubtarget::ARMv3m
@ ARMv3m
Definition: ARMSubtarget.h:97
llvm::ARMSubtarget::UnsafeFPMath
bool UnsafeFPMath
Target machine allowed unsafe FP math (such as use of NEON fp)
Definition: ARMSubtarget.h:465
llvm::ARMSubtarget::HasFP64
bool HasFP64
HasFP64 - If true, the floating point unit supports double precision.
Definition: ARMSubtarget.h:344
llvm::MachineFunction
Definition: MachineFunction.h:230
llvm::ARMSubtarget::Exynos
@ Exynos
Definition: ARMSubtarget.h:78
llvm::ARMSubtarget::HasV8_7aOps
bool HasV8_7aOps
Definition: ARMSubtarget.h:175
llvm::ARMSubtarget::None
@ None
Definition: ARMSubtarget.h:87
llvm::ARMSubtarget::hasV7Clrex
bool hasV7Clrex() const
Definition: ARMSubtarget.h:683
Triple.h
llvm::ARMSubtarget::hasV8_2aOps
bool hasV8_2aOps() const
Definition: ARMSubtarget.h:624
llvm::ARMSubtarget::HasCRC
bool HasCRC
HasCRC - if true, processor supports CRC instructions.
Definition: ARMSubtarget.h:367
llvm::ARMSubtarget::ARMv6k
@ ARMv6k
Definition: ARMSubtarget.h:105
llvm::ARMSubtarget::HasFP16FML
bool HasFP16FML
HasFP16FML - True if subtarget supports half-precision FP fml operations.
Definition: ARMSubtarget.h:275
llvm::ARMSubtarget::hasDotProd
bool hasDotProd() const
Definition: ARMSubtarget.h:669
TargetOptions.h
llvm::ARMSubtarget::NonpipelinedVFP
bool NonpipelinedVFP
If true, VFP instructions are not pipelined.
Definition: ARMSubtarget.h:440
llvm::ARMSubtarget::getCallLowering
const CallLowering * getCallLowering() const override
Definition: ARMSubtarget.cpp:127
llvm::ARMSubtarget::SlowFPVMLx
bool SlowFPVMLx
SlowFPVMLx - If the VFP2 / NEON instructions are available, indicates whether the FP VML[AS] instruct...
Definition: ARMSubtarget.h:224
llvm::ARMSubtarget::hasNEON
bool hasNEON() const
Definition: ARMSubtarget.h:665
llvm::ARMSubtarget::getRegisterInfo
const ARMBaseRegisterInfo * getRegisterInfo() const override
Definition: ARMSubtarget.h:583
llvm::ARMSubtarget::hasMatMulInt8
bool hasMatMulInt8() const
Definition: ARMSubtarget.h:752
llvm::ARMSubtarget::hasVMLxHazards
bool hasVMLxHazards() const
Definition: ARMSubtarget.h:711
llvm::ARMSubtarget::CortexR4F
@ CortexR4F
Definition: ARMSubtarget.h:73
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::ARMSubtarget::useMachineScheduler
bool useMachineScheduler() const
Definition: ARMSubtarget.h:818
llvm::ARMSubtarget::hasCRC
bool hasCRC() const
Definition: ARMSubtarget.h:670
llvm::ARMSubtarget::ARMv87a
@ ARMv87a
Definition: ARMSubtarget.h:121
llvm::ARMSubtarget::hasRetAddrStack
bool hasRetAddrStack() const
Definition: ARMSubtarget.h:725
llvm::ARMSubtarget::HasVFPv3D16SP
bool HasVFPv3D16SP
Definition: ARMSubtarget.h:206
llvm::ARMSubtarget::PartialUpdateClearance
unsigned PartialUpdateClearance
Clearance before partial register updates (in number of instructions)
Definition: ARMSubtarget.h:500
CostKind
static cl::opt< TargetTransformInfo::TargetCostKind > CostKind("cost-kind", cl::desc("Target cost kind"), cl::init(TargetTransformInfo::TCK_RecipThroughput), cl::values(clEnumValN(TargetTransformInfo::TCK_RecipThroughput, "throughput", "Reciprocal throughput"), clEnumValN(TargetTransformInfo::TCK_Latency, "latency", "Instruction latency"), clEnumValN(TargetTransformInfo::TCK_CodeSize, "code-size", "Code size"), clEnumValN(TargetTransformInfo::TCK_SizeAndLatency, "size-latency", "Code size and latency")))
llvm::ARMSubtarget::ARMv2a
@ ARMv2a
Definition: ARMSubtarget.h:95
TargetSubtargetInfo.h
llvm::ARMSubtarget::getInstructionSelector
InstructionSelector * getInstructionSelector() const override
Definition: ARMSubtarget.cpp:131
llvm::ARMSubtarget::UseNEONForSinglePrecisionFP
bool UseNEONForSinglePrecisionFP
UseNEONForSinglePrecisionFP - if the NEONFP attribute has been specified.
Definition: ARMSubtarget.h:216
llvm::ARMSubtarget::useFPVFMx64
bool useFPVFMx64() const
Definition: ARMSubtarget.h:696
llvm::Triple::isiOS
bool isiOS() const
Is this an iOS triple.
Definition: Triple.h:466
llvm::ARMSubtarget::getMaxInterleaveFactor
unsigned getMaxInterleaveFactor() const
Definition: ARMSubtarget.h:897
llvm::ARMSubtarget::isCortexA7
bool isCortexA7() const
Definition: ARMSubtarget.h:647
llvm::ARMSubtarget::ARMProcClass
ARMProcClassEnum ARMProcClass
ARMProcClass - ARM processor class: None, AClass, RClass or MClass.
Definition: ARMSubtarget.h:152
llvm::ARMSubtarget::HasV8_2aOps
bool HasV8_2aOps
Definition: ARMSubtarget.h:170
llvm::ARMSubtarget::hasVirtualization
bool hasVirtualization() const
Definition: ARMSubtarget.h:673
llvm::ARMSubtarget::CortexA15
@ CortexA15
Definition: ARMSubtarget.h:52
llvm::ARMSubtarget::hasV4TOps
bool hasV4TOps() const
Definition: ARMSubtarget.h:614
llvm::ARMSubtarget::ARMv86a
@ ARMv86a
Definition: ARMSubtarget.h:120
llvm::Triple::isWatchOS
bool isWatchOS() const
Is this an Apple watchOS triple.
Definition: Triple.h:476
llvm::ARMSelectionDAGInfo
Definition: ARMSelectionDAGInfo.h:38
llvm::ARMSubtarget::PreISelOperandLatencyAdjustment
int PreISelOperandLatencyAdjustment
The adjustment that we need to apply to get the operand latency from the operand cycle returned by th...
Definition: ARMSubtarget.h:508
llvm::ARMSubtarget::isCortexA9
bool isCortexA9() const
Definition: ARMSubtarget.h:649
llvm::ARMSubtarget::isTargetWindows
bool isTargetWindows() const
Definition: ARMSubtarget.h:763
llvm::ARMSubtarget::HasD32
bool HasD32
HasD32 - True if subtarget has the full 32 double precision FP registers for VFPv3.
Definition: ARMSubtarget.h:285
llvm::ARMSubtarget::isGVInGOT
bool isGVInGOT(const GlobalValue *GV) const
Returns the constant pool modifier needed to access the GV.
Definition: ARMSubtarget.cpp:370
llvm::ARMSubtarget::ARMv5t
@ ARMv5t
Definition: ARMSubtarget.h:101
llvm::ARMBaseRegisterInfo
Definition: ARMBaseRegisterInfo.h:100
llvm::Triple::isOSWindows
bool isOSWindows() const
Tests whether the OS is Windows.
Definition: Triple.h:550
llvm::ARMSubtarget::ignoreCSRForAllocationOrder
bool ignoreCSRForAllocationOrder(const MachineFunction &MF, unsigned PhysReg) const override
Definition: ARMSubtarget.cpp:482
llvm::ARMSubtarget::AvoidMOVsShifterOperand
bool AvoidMOVsShifterOperand
AvoidMOVsShifterOperand - If true, codegen should avoid using flag setting movs with shifter operand ...
Definition: ARMSubtarget.h:323
llvm::ARMSubtarget::Swift
@ Swift
Definition: ARMSubtarget.h:84
llvm::ARMSubtarget::CortexR4
@ CortexR4
Definition: ARMSubtarget.h:72
llvm::ARMSubtarget::CortexR52
@ CortexR52
Definition: ARMSubtarget.h:75
llvm::ARMSubtarget::UseMulOps
bool UseMulOps
UseMulOps - True if non-microcoded fused integer multiply-add and multiply-subtract instructions shou...
Definition: ARMSubtarget.h:220
llvm::ARMSubtarget::ARMv8mMainline
@ ARMv8mMainline
Definition: ARMSubtarget.h:124
llvm::ARMSubtarget::ARMArch
ARMArchEnum ARMArch
ARMArch - ARM architecture.
Definition: ARMSubtarget.h:155
llvm::ARMSubtarget::hasFPRegs
bool hasFPRegs() const
Definition: ARMSubtarget.h:639
ARMFrameLowering.h
llvm::ARMSubtarget::isTargetDarwin
bool isTargetDarwin() const
Definition: ARMSubtarget.h:756
llvm::ARMSubtarget::Krait
@ Krait
Definition: ARMSubtarget.h:79
uint16_t
llvm::ARMSubtarget::UseWideStrideVFP
bool UseWideStrideVFP
If true, use a wider stride when allocating VFP registers.
Definition: ARMSubtarget.h:413
llvm::MachineFunction::getTarget
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Definition: MachineFunction.h:622
llvm::ARMSubtarget::HasV8_4aOps
bool HasV8_4aOps
Definition: ARMSubtarget.h:172
llvm::ARMSubtarget::isCortexR5
bool isCortexR5() const
Definition: ARMSubtarget.h:655
llvm::ARMSubtarget::isAPCS_ABI
bool isAPCS_ABI() const
Definition: ARMSubtarget.cpp:333
llvm::ARMSubtarget::SingleIssue
@ SingleIssue
Can load/store 1 register/cycle.
Definition: ARMSubtarget.h:141
llvm::ARMSubtarget::isTargetMachO
bool isTargetMachO() const
Definition: ARMSubtarget.h:767
llvm::ARMSubtarget::HasV7Clrex
bool HasV7Clrex
HasV7Clrex - True if the subtarget supports CLREX instructions.
Definition: ARMSubtarget.h:302
llvm::ARMSubtarget::useFPVFMx16
bool useFPVFMx16() const
Definition: ARMSubtarget.h:695
llvm::ARMSubtarget::HasFPAO
bool HasFPAO
HasFPAO - if true, processor does positive address offset computation faster.
Definition: ARMSubtarget.h:380
llvm::ARMSubtarget::AvoidCPSRPartialUpdate
bool AvoidCPSRPartialUpdate
AvoidCPSRPartialUpdate - If true, codegen would avoid using instructions that partially update CPSR a...
Definition: ARMSubtarget.h:315
llvm::ARMSubtarget::isAAPCS_ABI
bool isAAPCS_ABI() const
Definition: ARMSubtarget.cpp:337
llvm::ARMSubtarget::NeoverseV1
@ NeoverseV1
Definition: ARMSubtarget.h:83
llvm::ARMSubtarget::Others
@ Others
Definition: ARMSubtarget.h:49
llvm::ARMSubtarget::HasMPExtension
bool HasMPExtension
HasMPExtension - True if the subtarget supports Multiprocessing extension (ARMv7 only).
Definition: ARMSubtarget.h:336
llvm::MCSchedModel
Machine model for scheduling, bundling, and heuristics.
Definition: MCSchedule.h:244
llvm::ARMSubtarget::HasVFPv4
bool HasVFPv4
Definition: ARMSubtarget.h:190
llvm::ARMSubtarget::CortexX1
@ CortexX1
Definition: ARMSubtarget.h:77
llvm::ARMSubtarget::hasV8_1MMainlineOps
bool hasV8_1MMainlineOps() const
Definition: ARMSubtarget.h:635
llvm::ARMSubtarget::HasVFPv4D16SP
bool HasVFPv4D16SP
Definition: ARMSubtarget.h:207
llvm::ARMSubtarget::hasV8_1aOps
bool hasV8_1aOps() const
Definition: ARMSubtarget.h:623
llvm::ARMSubtarget::getMaxMemcpyTPInlineSizeThreshold
unsigned getMaxMemcpyTPInlineSizeThreshold() const
getMaxMemcpyTPInlineSizeThreshold - Returns the maximum size that still makes it profitable to inline...
Definition: ARMSubtarget.h:557
llvm::ARMSubtarget::SingleIssuePlusExtras
@ SingleIssuePlusExtras
Can load/store 1 register/cycle, but needs an extra cycle for address computation and potentially als...
Definition: ARMSubtarget.h:144
llvm::ARMSubtarget::UseNEONForFPMovs
bool UseNEONForFPMovs
If true, VMOVRS, VMOVSR and VMOVS will be converted from VFP to NEON.
Definition: ARMSubtarget.h:434
llvm::ARMSubtarget::hasVFP4Base
bool hasVFP4Base() const
Definition: ARMSubtarget.h:663
llvm::ARMSubtarget::HasMuxedUnits
bool HasMuxedUnits
If true, the AGU and NEON/FPU units are multiplexed.
Definition: ARMSubtarget.h:416
llvm::ARMSubtarget::ARMv6m
@ ARMv6m
Definition: ARMSubtarget.h:107
llvm::ARMSubtarget::MClass
@ MClass
Definition: ARMSubtarget.h:90
llvm::ARMSubtarget::CortexA8
@ CortexA8
Definition: ARMSubtarget.h:68
llvm::ARMSubtarget::HasV8_5aOps
bool HasV8_5aOps
Definition: ARMSubtarget.h:173
llvm::ARMSubtarget::HardenSlsRetBr
bool HardenSlsRetBr
Harden against Straight Line Speculation for Returns and Indirect Branches.
Definition: ARMSubtarget.h:482
ARMISelLowering.h
llvm::ARMSubtarget::ARMv5te
@ ARMv5te
Definition: ARMSubtarget.h:102
llvm::ARMSubtarget::CortexA12
@ CortexA12
Definition: ARMSubtarget.h:51
llvm::ARMSubtarget::hasV8MMainlineOps
bool hasV8MMainlineOps() const
Definition: ARMSubtarget.h:634
llvm::ARMSubtarget::HasVFPv3D16
bool HasVFPv3D16
Definition: ARMSubtarget.h:203
llvm::ARMSubtarget::HasV9_2aOps
bool HasV9_2aOps
Definition: ARMSubtarget.h:178
llvm::ARMSubtarget::CortexA76
@ CortexA76
Definition: ARMSubtarget.h:64
llvm::Triple::isOSNetBSD
bool isOSNetBSD() const
Definition: Triple.h:505
llvm::ARMSubtarget::IsProfitableToUnpredicate
bool IsProfitableToUnpredicate
If true, if conversion may decide to leave some instructions unpredicated.
Definition: ARMSubtarget.h:391
llvm::ARMSubtarget::ReserveR9
bool ReserveR9
ReserveR9 - True if R9 is not available as a general purpose register.
Definition: ARMSubtarget.h:257
llvm::ARMSubtarget::isTargetEHABICompatible
bool isTargetEHABICompatible() const
Definition: ARMSubtarget.h:794
llvm::ARMSubtarget::CortexA35
@ CortexA35
Definition: ARMSubtarget.h:55
llvm::ARMSubtarget::HasDataBarrier
bool HasDataBarrier
HasDataBarrier - True if the subtarget supports DMB / DSB data barrier instructions.
Definition: ARMSubtarget.h:295
llvm::ARMSubtarget::CortexA78
@ CortexA78
Definition: ARMSubtarget.h:66
llvm::ARMSubtarget::hasMinSize
bool hasMinSize() const
Definition: ARMSubtarget.h:822
llvm::ARMSubtarget::CortexA53
@ CortexA53
Definition: ARMSubtarget.h:57
TargetTransformInfo.h
llvm::ARMSubtarget::hasAcquireRelease
bool hasAcquireRelease() const
Definition: ARMSubtarget.h:684
llvm::ARMSubtarget::SlowOddRegister
bool SlowOddRegister
If true, a VLDM/VSTM starting with an odd register number is considered to take more microops than si...
Definition: ARMSubtarget.h:407
llvm::ARMSubtarget::restrictIT
bool restrictIT() const
Definition: ARMSubtarget.h:859
llvm::ARMSubtarget::isGVIndirectSymbol
bool isGVIndirectSymbol(const GlobalValue *GV) const
True if the GV will be accessed via an indirect symbol.
Definition: ARMSubtarget.cpp:356
llvm::ARMSubtarget::hasV8MBaselineOps
bool hasV8MBaselineOps() const
Definition: ARMSubtarget.h:633
llvm::Triple::getEnvironment
EnvironmentType getEnvironment() const
getEnvironment - Get the parsed environment type of this triple.
Definition: Triple.h:328
llvm::ARMSubtarget::ARMv85a
@ ARMv85a
Definition: ARMSubtarget.h:119
llvm::Triple::EABIHF
@ EABIHF
Definition: Triple.h:219
llvm::ARMSubtarget::CortexA5
@ CortexA5
Definition: ARMSubtarget.h:56
llvm::LegalizerInfo
Definition: LegalizerInfo.h:1108
llvm::Triple::GNUEABIHF
@ GNUEABIHF
Definition: Triple.h:214
llvm::ARMSubtarget::UseNaClTrap
bool UseNaClTrap
NaCl TRAP instruction is generated instead of the regular TRAP.
Definition: ARMSubtarget.h:456
llvm::ARMSubtarget::HasFPRegs
bool HasFPRegs
Definition: ARMSubtarget.h:193
llvm::ARMSubtarget::CortexA32
@ CortexA32
Definition: ARMSubtarget.h:54
llvm::ARMSubtarget::isThumb2
bool isThumb2() const
Definition: ARMSubtarget.h:824
llvm::ARMSubtarget::hasFuseAES
bool hasFuseAES() const
Definition: ARMSubtarget.h:747
llvm::ARMSubtarget::getPrefLoopLogAlignment
unsigned getPrefLoopLogAlignment() const
Definition: ARMSubtarget.h:936
llvm::ARMSubtarget::getGPRAllocationOrder
unsigned getGPRAllocationOrder(const MachineFunction &MF) const
Definition: ARMSubtarget.cpp:451
llvm::ARMSubtarget::HasMatMulInt8
bool HasMatMulInt8
HasMatMulInt8 - True if subtarget supports 8-bit integer matrix multiply.
Definition: ARMSubtarget.h:281
llvm::ARMSubtarget::HasV7Ops
bool HasV7Ops
Definition: ARMSubtarget.h:167
llvm::ARMSubtarget::useWideStrideVFP
bool useWideStrideVFP() const
Definition: ARMSubtarget.h:714
llvm::ARMSubtarget::HasPerfMon
bool HasPerfMon
If true, the processor supports the Performance Monitor Extensions.
Definition: ARMSubtarget.h:349
MachineFunction.h
llvm::ARMSubtarget::hasV5TEOps
bool hasV5TEOps() const
Definition: ARMSubtarget.h:616
llvm::ARMSubtarget::hasV8_7aOps
bool hasV8_7aOps() const
Definition: ARMSubtarget.h:629
llvm::Triple::EABI
@ EABI
Definition: Triple.h:218
llvm::ARMSubtarget::hasDivideInThumbMode
bool hasDivideInThumbMode() const
Definition: ARMSubtarget.h:679
llvm::CallLowering
Definition: CallLowering.h:43
llvm::ARMSubtarget::isTargetNaCl
bool isTargetNaCl() const
Definition: ARMSubtarget.h:761
llvm::ARMSubtarget::HasFPARMv8D16SP
bool HasFPARMv8D16SP
Definition: ARMSubtarget.h:208
llvm::ARMSubtarget::isXRaySupported
bool isXRaySupported() const override
Definition: ARMSubtarget.cpp:143
llvm::InstrItineraryData
Itinerary data supplied by a subtarget to be used by a target.
Definition: MCInstrItineraries.h:109
llvm::ARMSubtarget::isCortexA8
bool isCortexA8() const
Definition: ARMSubtarget.h:648
llvm::ARMSubtarget::SplatVFPToNeon
bool SplatVFPToNeon
If true, splat a register between VFP and NEON instructions.
Definition: ARMSubtarget.h:422
llvm::ARMSubtarget::isTargetGNUAEABI
bool isTargetGNUAEABI() const
Definition: ARMSubtarget.h:781
llvm::ARMSubtarget::hasAnyDataBarrier
bool hasAnyDataBarrier() const
Definition: ARMSubtarget.h:686
llvm::ARMSubtarget::hasFullDataBarrier
bool hasFullDataBarrier() const
Definition: ARMSubtarget.h:682
llvm::ARMSubtarget::HasSB
bool HasSB
Has speculation barrier.
Definition: ARMSubtarget.h:471
llvm::ARMSubtarget::useStride4VFPs
bool useStride4VFPs() const
Definition: ARMSubtarget.cpp:420
llvm::ARMSubtarget::hasFuseLiterals
bool hasFuseLiterals() const
Definition: ARMSubtarget.h:748
llvm::ARMSubtarget::hasVFP2Base
bool hasVFP2Base() const
Definition: ARMSubtarget.h:661
llvm::ARMSubtarget::getReturnOpcode
unsigned getReturnOpcode() const
Returns the correct return opcode for the current feature set.
Definition: ARMSubtarget.h:921
llvm::ARMSubtarget::genExecuteOnly
bool genExecuteOnly() const
Definition: ARMSubtarget.h:733
llvm::ARMSubtarget::HasLOB
bool HasLOB
HasLOB - if true, the processor supports the Low Overhead Branch extension.
Definition: ARMSubtarget.h:373
llvm::ARMSubtarget::isThumb
bool isThumb() const
Definition: ARMSubtarget.h:821
llvm::ARMSubtarget::hasV8Ops
bool hasV8Ops() const
Definition: ARMSubtarget.h:622
llvm::ARMSubtarget::HasFPRegs64
bool HasFPRegs64
Definition: ARMSubtarget.h:195
llvm::ARMSubtarget::HasV5TOps
bool HasV5TOps
Definition: ARMSubtarget.h:161
llvm::ARMSubtarget::HasV8MBaselineOps
bool HasV8MBaselineOps
Definition: ARMSubtarget.h:179
llvm::ARMSubtarget::ARMv6kz
@ ARMv6kz
Definition: ARMSubtarget.h:106