LLVM  14.0.0git
ARMSubtarget.h
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1 //===-- ARMSubtarget.h - Define Subtarget for the ARM ----------*- C++ -*--===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file declares the ARM specific subclass of TargetSubtargetInfo.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H
14 #define LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H
15 
16 #include "ARMBaseInstrInfo.h"
17 #include "ARMBaseRegisterInfo.h"
18 #include "ARMConstantPoolValue.h"
19 #include "ARMFrameLowering.h"
20 #include "ARMISelLowering.h"
21 #include "ARMMachineFunctionInfo.h"
22 #include "ARMSelectionDAGInfo.h"
23 #include "llvm/ADT/Triple.h"
32 #include "llvm/MC/MCSchedule.h"
35 #include <memory>
36 #include <string>
37 
38 #define GET_SUBTARGETINFO_HEADER
39 #include "ARMGenSubtargetInfo.inc"
40 
41 namespace llvm {
42 
43 class ARMBaseTargetMachine;
44 class GlobalValue;
45 class StringRef;
46 
48 protected:
51 
87  };
90 
94  };
95  enum ARMArchEnum {
134  };
135 
136 public:
137  /// What kind of timing do load multiple/store multiple instructions have.
139  /// Can load/store 2 registers/cycle.
141  /// Can load/store 2 registers/cycle, but needs an extra cycle if the access
142  /// is not 64-bit aligned.
144  /// Can load/store 1 register/cycle.
146  /// Can load/store 1 register/cycle, but needs an extra cycle for address
147  /// computation and potentially also for register writeback.
149  };
150 
151 protected:
152  /// ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.
154 
155  /// ARMProcClass - ARM processor class: None, AClass, RClass or MClass.
157 
158  /// ARMArch - ARM architecture
160 
161  /// HasV4TOps, HasV5TOps, HasV5TEOps,
162  /// HasV6Ops, HasV6MOps, HasV6KOps, HasV6T2Ops, HasV7Ops, HasV8Ops -
163  /// Specify whether target support specific ARM ISA variants.
164  bool HasV4TOps = false;
165  bool HasV5TOps = false;
166  bool HasV5TEOps = false;
167  bool HasV6Ops = false;
168  bool HasV6MOps = false;
169  bool HasV6KOps = false;
170  bool HasV6T2Ops = false;
171  bool HasV7Ops = false;
172  bool HasV8Ops = false;
173  bool HasV8_1aOps = false;
174  bool HasV8_2aOps = false;
175  bool HasV8_3aOps = false;
176  bool HasV8_4aOps = false;
177  bool HasV8_5aOps = false;
178  bool HasV8_6aOps = false;
179  bool HasV8_8aOps = false;
180  bool HasV8_7aOps = false;
181  bool HasV9_0aOps = false;
182  bool HasV9_1aOps = false;
183  bool HasV9_2aOps = false;
184  bool HasV9_3aOps = false;
185  bool HasV8MBaselineOps = false;
186  bool HasV8MMainlineOps = false;
187  bool HasV8_1MMainlineOps = false;
188  bool HasMVEIntegerOps = false;
189  bool HasMVEFloatOps = false;
190  bool HasCDEOps = false;
191 
192  /// HasVFPv2, HasVFPv3, HasVFPv4, HasFPARMv8, HasNEON - Specify what
193  /// floating point ISAs are supported.
194  bool HasVFPv2 = false;
195  bool HasVFPv3 = false;
196  bool HasVFPv4 = false;
197  bool HasFPARMv8 = false;
198  bool HasNEON = false;
199  bool HasFPRegs = false;
200  bool HasFPRegs16 = false;
201  bool HasFPRegs64 = false;
202 
203  /// Versions of the VFP flags restricted to single precision, or to
204  /// 16 d-registers, or both.
205  bool HasVFPv2SP = false;
206  bool HasVFPv3SP = false;
207  bool HasVFPv4SP = false;
208  bool HasFPARMv8SP = false;
209  bool HasVFPv3D16 = false;
210  bool HasVFPv4D16 = false;
211  bool HasFPARMv8D16 = false;
212  bool HasVFPv3D16SP = false;
213  bool HasVFPv4D16SP = false;
214  bool HasFPARMv8D16SP = false;
215 
216  /// HasDotProd - True if the ARMv8.2A dot product instructions are supported.
217  bool HasDotProd = false;
218 
219  /// UseNEONForSinglePrecisionFP - if the NEONFP attribute has been
220  /// specified. Use the method useNEONForSinglePrecisionFP() to
221  /// determine if NEON should actually be used.
223 
224  /// UseMulOps - True if non-microcoded fused integer multiply-add and
225  /// multiply-subtract instructions should be used.
226  bool UseMulOps = false;
227 
228  /// SlowFPVMLx - If the VFP2 / NEON instructions are available, indicates
229  /// whether the FP VML[AS] instructions are slow (if so, don't use them).
230  bool SlowFPVMLx = false;
231 
232  /// SlowFPVFMx - If the VFP4 / NEON instructions are available, indicates
233  /// whether the FP VFM[AS] instructions are slow (if so, don't use them).
234  bool SlowFPVFMx = false;
235 
236  /// HasVMLxForwarding - If true, NEON has special multiplier accumulator
237  /// forwarding to allow mul + mla being issued back to back.
238  bool HasVMLxForwarding = false;
239 
240  /// SlowFPBrcc - True if floating point compare + branch is slow.
241  bool SlowFPBrcc = false;
242 
243  /// InThumbMode - True if compiling for Thumb, false for ARM.
244  bool InThumbMode = false;
245 
246  /// UseSoftFloat - True if we're using software floating point features.
247  bool UseSoftFloat = false;
248 
249  /// UseMISched - True if MachineScheduler should be used for this subtarget.
250  bool UseMISched = false;
251 
252  /// DisablePostRAScheduler - False if scheduling should happen again after
253  /// register allocation.
255 
256  /// HasThumb2 - True if Thumb2 instructions are supported.
257  bool HasThumb2 = false;
258 
259  /// NoARM - True if subtarget does not support ARM mode execution.
260  bool NoARM = false;
261 
262  /// ReserveR9 - True if R9 is not available as a general purpose register.
263  bool ReserveR9 = false;
264 
265  /// NoMovt - True if MOVT / MOVW pairs are not used for materialization of
266  /// 32-bit imms (including global addresses).
267  bool NoMovt = false;
268 
269  /// SupportsTailCall - True if the OS supports tail call. The dynamic linker
270  /// must be able to synthesize call stubs for interworking between ARM and
271  /// Thumb.
272  bool SupportsTailCall = false;
273 
274  /// HasFP16 - True if subtarget supports half-precision FP conversions
275  bool HasFP16 = false;
276 
277  /// HasFullFP16 - True if subtarget supports half-precision FP operations
278  bool HasFullFP16 = false;
279 
280  /// HasFP16FML - True if subtarget supports half-precision FP fml operations
281  bool HasFP16FML = false;
282 
283  /// HasBF16 - True if subtarget supports BFloat16 floating point operations
284  bool HasBF16 = false;
285 
286  /// HasMatMulInt8 - True if subtarget supports 8-bit integer matrix multiply
287  bool HasMatMulInt8 = false;
288 
289  /// HasD32 - True if subtarget has the full 32 double precision
290  /// FP registers for VFPv3.
291  bool HasD32 = false;
292 
293  /// HasHardwareDivide - True if subtarget supports [su]div in Thumb mode
295 
296  /// HasHardwareDivideInARM - True if subtarget supports [su]div in ARM mode
298 
299  /// HasDataBarrier - True if the subtarget supports DMB / DSB data barrier
300  /// instructions.
301  bool HasDataBarrier = false;
302 
303  /// HasFullDataBarrier - True if the subtarget supports DFB data barrier
304  /// instruction.
305  bool HasFullDataBarrier = false;
306 
307  /// HasV7Clrex - True if the subtarget supports CLREX instructions
308  bool HasV7Clrex = false;
309 
310  /// HasAcquireRelease - True if the subtarget supports v8 atomics (LDA/LDAEX etc)
311  /// instructions
312  bool HasAcquireRelease = false;
313 
314  /// Pref32BitThumb - If true, codegen would prefer 32-bit Thumb instructions
315  /// over 16-bit ones.
316  bool Pref32BitThumb = false;
317 
318  /// AvoidCPSRPartialUpdate - If true, codegen would avoid using instructions
319  /// that partially update CPSR and add false dependency on the previous
320  /// CPSR setting instruction.
322 
323  /// CheapPredicableCPSRDef - If true, disable +1 predication cost
324  /// for instructions updating CPSR. Enabled for Cortex-A57.
326 
327  /// AvoidMOVsShifterOperand - If true, codegen should avoid using flag setting
328  /// movs with shifter operand (i.e. asr, lsl, lsr).
330 
331  /// HasRetAddrStack - Some processors perform return stack prediction. CodeGen should
332  /// avoid issue "normal" call instructions to callees which do not return.
333  bool HasRetAddrStack = false;
334 
335  /// HasBranchPredictor - True if the subtarget has a branch predictor. Having
336  /// a branch predictor or not changes the expected cost of taking a branch
337  /// which affects the choice of whether to use predicated instructions.
338  bool HasBranchPredictor = true;
339 
340  /// HasMPExtension - True if the subtarget supports Multiprocessing
341  /// extension (ARMv7 only).
342  bool HasMPExtension = false;
343 
344  /// HasVirtualization - True if the subtarget supports the Virtualization
345  /// extension.
346  bool HasVirtualization = false;
347 
348  /// HasFP64 - If true, the floating point unit supports double
349  /// precision.
350  bool HasFP64 = false;
351 
352  /// If true, the processor supports the Performance Monitor Extensions. These
353  /// include a generic cycle-counter as well as more fine-grained (often
354  /// implementation-specific) events.
355  bool HasPerfMon = false;
356 
357  /// HasTrustZone - if true, processor supports TrustZone security extensions
358  bool HasTrustZone = false;
359 
360  /// Has8MSecExt - if true, processor supports ARMv8-M Security Extensions
361  bool Has8MSecExt = false;
362 
363  /// HasSHA2 - if true, processor supports SHA1 and SHA256
364  bool HasSHA2 = false;
365 
366  /// HasAES - if true, processor supports AES
367  bool HasAES = false;
368 
369  /// HasCrypto - if true, processor supports Cryptography extensions
370  bool HasCrypto = false;
371 
372  /// HasCRC - if true, processor supports CRC instructions
373  bool HasCRC = false;
374 
375  /// HasRAS - if true, the processor supports RAS extensions
376  bool HasRAS = false;
377 
378  /// HasLOB - if true, the processor supports the Low Overhead Branch extension
379  bool HasLOB = false;
380 
381  bool HasPACBTI = false;
382 
383  /// If true, the instructions "vmov.i32 d0, #0" and "vmov.i32 q0, #0" are
384  /// particularly effective at zeroing a VFP register.
385  bool HasZeroCycleZeroing = false;
386 
387  /// HasFPAO - if true, processor does positive address offset computation faster
388  bool HasFPAO = false;
389 
390  /// HasFuseAES - if true, processor executes back to back AES instruction
391  /// pairs faster.
392  bool HasFuseAES = false;
393 
394  /// HasFuseLiterals - if true, processor executes back to back
395  /// bottom and top halves of literal generation faster.
396  bool HasFuseLiterals = false;
397 
398  /// If true, if conversion may decide to leave some instructions unpredicated.
400 
401  /// If true, VMOV will be favored over VGETLNi32.
402  bool HasSlowVGETLNi32 = false;
403 
404  /// If true, VMOV will be favored over VDUP.
405  bool HasSlowVDUP32 = false;
406 
407  /// If true, VMOVSR will be favored over VMOVDRR.
408  bool PreferVMOVSR = false;
409 
410  /// If true, ISHST barriers will be used for Release semantics.
411  bool PreferISHST = false;
412 
413  /// If true, a VLDM/VSTM starting with an odd register number is considered to
414  /// take more microops than single VLDRS/VSTRS.
415  bool SlowOddRegister = false;
416 
417  /// If true, loading into a D subregister will be penalized.
418  bool SlowLoadDSubregister = false;
419 
420  /// If true, use a wider stride when allocating VFP registers.
421  bool UseWideStrideVFP = false;
422 
423  /// If true, the AGU and NEON/FPU units are multiplexed.
424  bool HasMuxedUnits = false;
425 
426  /// If true, VMOVS will never be widened to VMOVD.
427  bool DontWidenVMOVS = false;
428 
429  /// If true, splat a register between VFP and NEON instructions.
430  bool SplatVFPToNeon = false;
431 
432  /// If true, run the MLx expansion pass.
433  bool ExpandMLx = false;
434 
435  /// If true, VFP/NEON VMLA/VMLS have special RAW hazards.
436  bool HasVMLxHazards = false;
437 
438  // If true, read thread pointer from coprocessor register.
439  bool ReadTPHard = false;
440 
441  /// If true, VMOVRS, VMOVSR and VMOVS will be converted from VFP to NEON.
442  bool UseNEONForFPMovs = false;
443 
444  /// If true, VLDn instructions take an extra cycle for unaligned accesses.
445  bool CheckVLDnAlign = false;
446 
447  /// If true, VFP instructions are not pipelined.
448  bool NonpipelinedVFP = false;
449 
450  /// StrictAlign - If true, the subtarget disallows unaligned memory
451  /// accesses for some types. For details, see
452  /// ARMTargetLowering::allowsMisalignedMemoryAccesses().
453  bool StrictAlign = false;
454 
455  /// RestrictIT - If true, the subtarget disallows generation of deprecated IT
456  /// blocks to conform to ARMv8 rule.
457  bool RestrictIT = false;
458 
459  /// HasDSP - If true, the subtarget supports the DSP (saturating arith
460  /// and such) instructions.
461  bool HasDSP = false;
462 
463  /// NaCl TRAP instruction is generated instead of the regular TRAP.
464  bool UseNaClTrap = false;
465 
466  /// Generate calls via indirect call instructions.
467  bool GenLongCalls = false;
468 
469  /// Generate code that does not contain data access to code sections.
470  bool GenExecuteOnly = false;
471 
472  /// Target machine allowed unsafe FP math (such as use of NEON fp)
473  bool UnsafeFPMath = false;
474 
475  /// UseSjLjEH - If true, the target uses SjLj exception handling (e.g. iOS).
476  bool UseSjLjEH = false;
477 
478  /// Has speculation barrier
479  bool HasSB = false;
480 
481  /// Implicitly convert an instruction to a different one if its immediates
482  /// cannot be encoded. For example, ADD r0, r1, #FFFFFFFF -> SUB r0, r1, #1.
483  bool NegativeImmediates = true;
484 
485  /// Mitigate against the cve-2021-35465 security vulnurability.
487 
488  /// Harden against Straight Line Speculation for Returns and Indirect
489  /// Branches.
490  bool HardenSlsRetBr = false;
491 
492  /// Harden against Straight Line Speculation for indirect calls.
493  bool HardenSlsBlr = false;
494 
495  /// Generate thunk code for SLS mitigation in the normal text section.
496  bool HardenSlsNoComdat = false;
497 
498  /// stackAlignment - The minimum alignment known to hold of the stack frame on
499  /// entry to the function and which must be maintained by every function.
501 
502  /// CPUString - String name of used CPU.
503  std::string CPUString;
504 
505  unsigned MaxInterleaveFactor = 1;
506 
507  /// Clearance before partial register updates (in number of instructions)
509 
510  /// What kind of timing do load multiple/store multiple have (double issue,
511  /// single issue etc).
513 
514  /// The adjustment that we need to apply to get the operand latency from the
515  /// operand cycle returned by the itinerary data for pre-ISel operands.
517 
518  /// What alignment is preferred for loop bodies, in log2(bytes).
519  unsigned PrefLoopLogAlignment = 0;
520 
521  /// The cost factor for MVE instructions, representing the multiple beats an
522  // instruction can take. The default is 2, (set in initSubtargetFeatures so
523  // that we can use subtarget features less than 2).
524  unsigned MVEVectorCostFactor = 0;
525 
526  /// OptMinSize - True if we're optimising for minimum code size, equal to
527  /// the function attribute.
528  bool OptMinSize = false;
529 
530  /// IsLittle - The target is Little Endian
531  bool IsLittle;
532 
533  /// TargetTriple - What processor and OS we're targeting.
535 
536  /// SchedModel - Processor specific instruction costs.
538 
539  /// Selected instruction itineraries (one entry per itinerary class.)
541 
542  /// NoBTIAtReturnTwice - Don't place a BTI instruction after
543  /// return-twice constructs (setjmp)
544  bool NoBTIAtReturnTwice = false;
545 
546  /// Options passed via command line that could influence the target
548 
550 
551 public:
552  /// This constructor initializes the data members to match that
553  /// of the specified triple.
554  ///
555  ARMSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS,
556  const ARMBaseTargetMachine &TM, bool IsLittle,
557  bool MinSize = false);
558 
559  /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
560  /// that still makes it profitable to inline the call.
561  unsigned getMaxInlineSizeThreshold() const {
562  return 64;
563  }
564 
565  /// getMaxMemcpyTPInlineSizeThreshold - Returns the maximum size
566  /// that still makes it profitable to inline a llvm.memcpy as a Tail
567  /// Predicated loop.
568  /// This threshold should only be used for constant size inputs.
569  unsigned getMaxMemcpyTPInlineSizeThreshold() const { return 128; }
570 
571  /// ParseSubtargetFeatures - Parses features string setting specified
572  /// subtarget options. Definition of function is auto generated by tblgen.
574 
575  /// initializeSubtargetDependencies - Initializes using a CPU and feature string
576  /// so that we can use initializer lists for subtarget initialization.
578 
579  const ARMSelectionDAGInfo *getSelectionDAGInfo() const override {
580  return &TSInfo;
581  }
582 
583  const ARMBaseInstrInfo *getInstrInfo() const override {
584  return InstrInfo.get();
585  }
586 
587  const ARMTargetLowering *getTargetLowering() const override {
588  return &TLInfo;
589  }
590 
591  const ARMFrameLowering *getFrameLowering() const override {
592  return FrameLowering.get();
593  }
594 
595  const ARMBaseRegisterInfo *getRegisterInfo() const override {
596  return &InstrInfo->getRegisterInfo();
597  }
598 
599  const CallLowering *getCallLowering() const override;
601  const LegalizerInfo *getLegalizerInfo() const override;
602  const RegisterBankInfo *getRegBankInfo() const override;
603 
604 private:
605  ARMSelectionDAGInfo TSInfo;
606  // Either Thumb1FrameLowering or ARMFrameLowering.
607  std::unique_ptr<ARMFrameLowering> FrameLowering;
608  // Either Thumb1InstrInfo or Thumb2InstrInfo.
609  std::unique_ptr<ARMBaseInstrInfo> InstrInfo;
610  ARMTargetLowering TLInfo;
611 
612  /// GlobalISel related APIs.
613  std::unique_ptr<CallLowering> CallLoweringInfo;
614  std::unique_ptr<InstructionSelector> InstSelector;
615  std::unique_ptr<LegalizerInfo> Legalizer;
616  std::unique_ptr<RegisterBankInfo> RegBankInfo;
617 
618  void initializeEnvironment();
619  void initSubtargetFeatures(StringRef CPU, StringRef FS);
620  ARMFrameLowering *initializeFrameLowering(StringRef CPU, StringRef FS);
621 
622  std::bitset<8> CoprocCDE = {};
623 public:
624  void computeIssueWidth();
625 
626  bool hasV4TOps() const { return HasV4TOps; }
627  bool hasV5TOps() const { return HasV5TOps; }
628  bool hasV5TEOps() const { return HasV5TEOps; }
629  bool hasV6Ops() const { return HasV6Ops; }
630  bool hasV6MOps() const { return HasV6MOps; }
631  bool hasV6KOps() const { return HasV6KOps; }
632  bool hasV6T2Ops() const { return HasV6T2Ops; }
633  bool hasV7Ops() const { return HasV7Ops; }
634  bool hasV8Ops() const { return HasV8Ops; }
635  bool hasV8_1aOps() const { return HasV8_1aOps; }
636  bool hasV8_2aOps() const { return HasV8_2aOps; }
637  bool hasV8_3aOps() const { return HasV8_3aOps; }
638  bool hasV8_4aOps() const { return HasV8_4aOps; }
639  bool hasV8_5aOps() const { return HasV8_5aOps; }
640  bool hasV8_6aOps() const { return HasV8_6aOps; }
641  bool hasV8_7aOps() const { return HasV8_7aOps; }
642  bool hasV8_8aOps() const { return HasV8_8aOps; }
643  bool hasV9_0aOps() const { return HasV9_0aOps; }
644  bool hasV9_1aOps() const { return HasV9_1aOps; }
645  bool hasV9_2aOps() const { return HasV9_2aOps; }
646  bool hasV9_3aOps() const { return HasV9_3aOps; }
647  bool hasV8MBaselineOps() const { return HasV8MBaselineOps; }
648  bool hasV8MMainlineOps() const { return HasV8MMainlineOps; }
649  bool hasV8_1MMainlineOps() const { return HasV8_1MMainlineOps; }
650  bool hasMVEIntegerOps() const { return HasMVEIntegerOps; }
651  bool hasMVEFloatOps() const { return HasMVEFloatOps; }
652  bool hasCDEOps() const { return HasCDEOps; }
653  bool hasFPRegs() const { return HasFPRegs; }
654  bool hasFPRegs16() const { return HasFPRegs16; }
655  bool hasFPRegs64() const { return HasFPRegs64; }
656 
657  /// @{
658  /// These functions are obsolete, please consider adding subtarget features
659  /// or properties instead of calling them.
660  bool isCortexA5() const { return ARMProcFamily == CortexA5; }
661  bool isCortexA7() const { return ARMProcFamily == CortexA7; }
662  bool isCortexA8() const { return ARMProcFamily == CortexA8; }
663  bool isCortexA9() const { return ARMProcFamily == CortexA9; }
664  bool isCortexA15() const { return ARMProcFamily == CortexA15; }
665  bool isSwift() const { return ARMProcFamily == Swift; }
666  bool isCortexM3() const { return ARMProcFamily == CortexM3; }
667  bool isCortexM7() const { return ARMProcFamily == CortexM7; }
668  bool isLikeA9() const { return isCortexA9() || isCortexA15() || isKrait(); }
669  bool isCortexR5() const { return ARMProcFamily == CortexR5; }
670  bool isKrait() const { return ARMProcFamily == Krait; }
671  /// @}
672 
673  bool hasARMOps() const { return !NoARM; }
674 
675  bool hasVFP2Base() const { return HasVFPv2SP; }
676  bool hasVFP3Base() const { return HasVFPv3D16SP; }
677  bool hasVFP4Base() const { return HasVFPv4D16SP; }
678  bool hasFPARMv8Base() const { return HasFPARMv8D16SP; }
679  bool hasNEON() const { return HasNEON; }
680  bool hasSHA2() const { return HasSHA2; }
681  bool hasAES() const { return HasAES; }
682  bool hasCrypto() const { return HasCrypto; }
683  bool hasDotProd() const { return HasDotProd; }
684  bool hasCRC() const { return HasCRC; }
685  bool hasRAS() const { return HasRAS; }
686  bool hasLOB() const { return HasLOB; }
687  bool hasPACBTI() const { return HasPACBTI; }
688  bool hasVirtualization() const { return HasVirtualization; }
689 
692  }
693 
696  bool hasDataBarrier() const { return HasDataBarrier; }
697  bool hasFullDataBarrier() const { return HasFullDataBarrier; }
698  bool hasV7Clrex() const { return HasV7Clrex; }
699  bool hasAcquireRelease() const { return HasAcquireRelease; }
700 
701  bool hasAnyDataBarrier() const {
702  return HasDataBarrier || (hasV6Ops() && !isThumb());
703  }
704 
705  bool useMulOps() const { return UseMulOps; }
706  bool useFPVMLx() const { return !SlowFPVMLx; }
707  bool useFPVFMx() const {
708  return !isTargetDarwin() && hasVFP4Base() && !SlowFPVFMx;
709  }
710  bool useFPVFMx16() const { return useFPVFMx() && hasFullFP16(); }
711  bool useFPVFMx64() const { return useFPVFMx() && hasFP64(); }
712  bool hasVMLxForwarding() const { return HasVMLxForwarding; }
713  bool isFPBrccSlow() const { return SlowFPBrcc; }
714  bool hasFP64() const { return HasFP64; }
715  bool hasPerfMon() const { return HasPerfMon; }
716  bool hasTrustZone() const { return HasTrustZone; }
717  bool has8MSecExt() const { return Has8MSecExt; }
718  bool hasZeroCycleZeroing() const { return HasZeroCycleZeroing; }
719  bool hasFPAO() const { return HasFPAO; }
721  bool hasSlowVGETLNi32() const { return HasSlowVGETLNi32; }
722  bool hasSlowVDUP32() const { return HasSlowVDUP32; }
723  bool preferVMOVSR() const { return PreferVMOVSR; }
724  bool preferISHSTBarriers() const { return PreferISHST; }
725  bool expandMLx() const { return ExpandMLx; }
726  bool hasVMLxHazards() const { return HasVMLxHazards; }
727  bool hasSlowOddRegister() const { return SlowOddRegister; }
729  bool useWideStrideVFP() const { return UseWideStrideVFP; }
730  bool hasMuxedUnits() const { return HasMuxedUnits; }
731  bool dontWidenVMOVS() const { return DontWidenVMOVS; }
732  bool useSplatVFPToNeon() const { return SplatVFPToNeon; }
733  bool useNEONForFPMovs() const { return UseNEONForFPMovs; }
734  bool checkVLDnAccessAlignment() const { return CheckVLDnAlign; }
735  bool nonpipelinedVFP() const { return NonpipelinedVFP; }
736  bool prefers32BitThumb() const { return Pref32BitThumb; }
740  bool hasRetAddrStack() const { return HasRetAddrStack; }
741  bool hasBranchPredictor() const { return HasBranchPredictor; }
742  bool hasMPExtension() const { return HasMPExtension; }
743  bool hasDSP() const { return HasDSP; }
744  bool useNaClTrap() const { return UseNaClTrap; }
745  bool useSjLjEH() const { return UseSjLjEH; }
746  bool hasSB() const { return HasSB; }
747  bool genLongCalls() const { return GenLongCalls; }
748  bool genExecuteOnly() const { return GenExecuteOnly; }
749  bool hasBaseDSP() const {
750  if (isThumb())
751  return hasDSP();
752  else
753  return hasV5TEOps();
754  }
755 
756  bool hasFP16() const { return HasFP16; }
757  bool hasD32() const { return HasD32; }
758  bool hasFullFP16() const { return HasFullFP16; }
759  bool hasFP16FML() const { return HasFP16FML; }
760  bool hasBF16() const { return HasBF16; }
761 
762  bool hasFuseAES() const { return HasFuseAES; }
763  bool hasFuseLiterals() const { return HasFuseLiterals; }
764  /// Return true if the CPU supports any kind of instruction fusion.
765  bool hasFusion() const { return hasFuseAES() || hasFuseLiterals(); }
766 
767  bool hasMatMulInt8() const { return HasMatMulInt8; }
768 
769  const Triple &getTargetTriple() const { return TargetTriple; }
770 
771  bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
772  bool isTargetIOS() const { return TargetTriple.isiOS(); }
773  bool isTargetWatchOS() const { return TargetTriple.isWatchOS(); }
774  bool isTargetWatchABI() const { return TargetTriple.isWatchABI(); }
775  bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
776  bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
777  bool isTargetNetBSD() const { return TargetTriple.isOSNetBSD(); }
778  bool isTargetWindows() const { return TargetTriple.isOSWindows(); }
779 
780  bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
781  bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
782  bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
783 
784  // ARM EABI is the bare-metal EABI described in ARM ABI documents and
785  // can be accessed via -target arm-none-eabi. This is NOT GNUEABI.
786  // FIXME: Add a flag for bare-metal for that target and set Triple::EABI
787  // even for GNUEABI, so we can make a distinction here and still conform to
788  // the EABI on GNU (and Android) mode. This requires change in Clang, too.
789  // FIXME: The Darwin exception is temporary, while we move users to
790  // "*-*-*-macho" triples as quickly as possible.
791  bool isTargetAEABI() const {
795  }
796  bool isTargetGNUAEABI() const {
800  }
801  bool isTargetMuslAEABI() const {
805  }
806 
807  // ARM Targets that support EHABI exception handling standard
808  // Darwin uses SjLj. Other targets might need more checks.
809  bool isTargetEHABICompatible() const {
811  }
812 
813  bool isTargetHardFloat() const;
814 
815  bool isTargetAndroid() const { return TargetTriple.isAndroid(); }
816 
817  bool isXRaySupported() const override;
818 
819  bool isAPCS_ABI() const;
820  bool isAAPCS_ABI() const;
821  bool isAAPCS16_ABI() const;
822 
823  bool isROPI() const;
824  bool isRWPI() const;
825 
826  bool useMachineScheduler() const { return UseMISched; }
828  bool useSoftFloat() const { return UseSoftFloat; }
829  bool isThumb() const { return InThumbMode; }
830  bool hasMinSize() const { return OptMinSize; }
831  bool isThumb1Only() const { return InThumbMode && !HasThumb2; }
832  bool isThumb2() const { return InThumbMode && HasThumb2; }
833  bool hasThumb2() const { return HasThumb2; }
834  bool isMClass() const { return ARMProcClass == MClass; }
835  bool isRClass() const { return ARMProcClass == RClass; }
836  bool isAClass() const { return ARMProcClass == AClass; }
837  bool isReadTPHard() const { return ReadTPHard; }
838 
839  bool isR9Reserved() const {
840  return isTargetMachO() ? (ReserveR9 || !HasV6Ops) : ReserveR9;
841  }
842 
844  if (isTargetDarwin() || (!isTargetWindows() && isThumb()))
845  return ARM::R7;
846  return ARM::R11;
847  }
848 
849  /// Returns true if the frame setup is split into two separate pushes (first
850  /// r0-r7,lr then r8-r11), principally so that the frame pointer is adjacent
851  /// to lr. This is always required on Thumb1-only targets, as the push and
852  /// pop instructions can't access the high registers.
853  bool splitFramePushPop(const MachineFunction &MF) const {
855  return true;
856  return (getFramePointerReg() == ARM::R7 &&
858  isThumb1Only();
859  }
860 
861  bool useStride4VFPs() const;
862 
863  bool useMovt() const;
864 
865  bool supportsTailCall() const { return SupportsTailCall; }
866 
867  bool allowsUnalignedMem() const { return !StrictAlign; }
868 
869  bool restrictIT() const { return RestrictIT; }
870 
871  const std::string & getCPUString() const { return CPUString; }
872 
873  bool isLittle() const { return IsLittle; }
874 
875  unsigned getMispredictionPenalty() const;
876 
877  /// Returns true if machine scheduler should be enabled.
878  bool enableMachineScheduler() const override;
879 
880  /// True for some subtargets at > -O0.
881  bool enablePostRAScheduler() const override;
882 
883  /// True for some subtargets at > -O0.
884  bool enablePostRAMachineScheduler() const override;
885 
886  /// Check whether this subtarget wants to use subregister liveness.
887  bool enableSubRegLiveness() const override;
888 
889  /// Enable use of alias analysis during code generation (during MI
890  /// scheduling, DAGCombine, etc.).
891  bool useAA() const override { return true; }
892 
893  // enableAtomicExpand- True if we need to expand our atomics.
894  bool enableAtomicExpand() const override;
895 
896  /// getInstrItins - Return the instruction itineraries based on subtarget
897  /// selection.
898  const InstrItineraryData *getInstrItineraryData() const override {
899  return &InstrItins;
900  }
901 
902  /// getStackAlignment - Returns the minimum alignment known to hold of the
903  /// stack frame on entry to the function and which must be maintained by every
904  /// function for this subtarget.
906 
907  unsigned getMaxInterleaveFactor() const { return MaxInterleaveFactor; }
908 
910 
912  return LdStMultipleTiming;
913  }
914 
917  }
918 
919  /// True if the GV will be accessed via an indirect symbol.
920  bool isGVIndirectSymbol(const GlobalValue *GV) const;
921 
922  /// Returns the constant pool modifier needed to access the GV.
923  bool isGVInGOT(const GlobalValue *GV) const;
924 
925  /// True if fast-isel is used.
926  bool useFastISel() const;
927 
928  /// Returns the correct return opcode for the current feature set.
929  /// Use BX if available to allow mixing thumb/arm code, but fall back
930  /// to plain mov pc,lr on ARMv4.
931  unsigned getReturnOpcode() const {
932  if (isThumb())
933  return ARM::tBX_RET;
934  if (hasV4TOps())
935  return ARM::BX_RET;
936  return ARM::MOVPCLR;
937  }
938 
939  /// Allow movt+movw for PIC global address calculation.
940  /// ELF does not have GOT relocations for movt+movw.
941  /// ROPI does not use GOT.
943  return isROPI() || !isTargetELF();
944  }
945 
946  unsigned getPrefLoopLogAlignment() const { return PrefLoopLogAlignment; }
947 
948  unsigned
951  return 1;
952  return MVEVectorCostFactor;
953  }
954 
956  unsigned PhysReg) const override;
957  unsigned getGPRAllocationOrder(const MachineFunction &MF) const;
958 
960 
961  bool hardenSlsRetBr() const { return HardenSlsRetBr; }
962  bool hardenSlsBlr() const { return HardenSlsBlr; }
963  bool hardenSlsNoComdat() const { return HardenSlsNoComdat; }
964 
965  bool getNoBTIAtReturnTwice() const { return NoBTIAtReturnTwice; }
966 };
967 
968 } // end namespace llvm
969 
970 #endif // LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H
llvm::ARMSubtarget::HasCDEOps
bool HasCDEOps
Definition: ARMSubtarget.h:190
llvm::ARMSubtarget::HasV8_3aOps
bool HasV8_3aOps
Definition: ARMSubtarget.h:175
llvm::ARMSubtarget::SupportsTailCall
bool SupportsTailCall
SupportsTailCall - True if the OS supports tail call.
Definition: ARMSubtarget.h:272
llvm::ARMSubtarget::CortexA17
@ CortexA17
Definition: ARMSubtarget.h:54
llvm::ARMSubtarget::hasV8_8aOps
bool hasV8_8aOps() const
Definition: ARMSubtarget.h:642
llvm::ARMSubtarget::HasV5TEOps
bool HasV5TEOps
Definition: ARMSubtarget.h:166
llvm::ARMSubtarget::UseSjLjEH
bool UseSjLjEH
UseSjLjEH - If true, the target uses SjLj exception handling (e.g. iOS).
Definition: ARMSubtarget.h:476
llvm::ARMSubtarget::useSjLjEH
bool useSjLjEH() const
Definition: ARMSubtarget.h:745
llvm::ARMSubtarget::hasBaseDSP
bool hasBaseDSP() const
Definition: ARMSubtarget.h:749
llvm::ARMSubtarget::TM
const ARMBaseTargetMachine & TM
Definition: ARMSubtarget.h:549
llvm::ARMSubtarget::CortexR7
@ CortexR7
Definition: ARMSubtarget.h:78
llvm::ARMSubtarget::hasRAS
bool hasRAS() const
Definition: ARMSubtarget.h:685
llvm::ARMSubtarget::enableSubRegLiveness
bool enableSubRegLiveness() const override
Check whether this subtarget wants to use subregister liveness.
Definition: ARMSubtarget.cpp:394
llvm::ARMFunctionInfo
ARMFunctionInfo - This class is derived from MachineFunctionInfo and contains private ARM-specific in...
Definition: ARMMachineFunctionInfo.h:27
llvm::TargetTransformInfo::TargetCostKind
TargetCostKind
The kind of cost model.
Definition: TargetTransformInfo.h:211
llvm::ARMSubtarget::HasVFPv3SP
bool HasVFPv3SP
Definition: ARMSubtarget.h:206
llvm::ARMSubtarget::HasCrypto
bool HasCrypto
HasCrypto - if true, processor supports Cryptography extensions.
Definition: ARMSubtarget.h:370
llvm::ARMSubtarget::hardenSlsRetBr
bool hardenSlsRetBr() const
Definition: ARMSubtarget.h:961
llvm::ARMSubtarget::hasV6MOps
bool hasV6MOps() const
Definition: ARMSubtarget.h:630
llvm::ARMSubtarget::HasAcquireRelease
bool HasAcquireRelease
HasAcquireRelease - True if the subtarget supports v8 atomics (LDA/LDAEX etc) instructions.
Definition: ARMSubtarget.h:312
llvm::ARMSubtarget::fixCMSE_CVE_2021_35465
bool fixCMSE_CVE_2021_35465() const
Definition: ARMSubtarget.h:959
llvm::ARMSubtarget::genLongCalls
bool genLongCalls() const
Definition: ARMSubtarget.h:747
llvm::ARMBaseTargetMachine
Definition: ARMTargetMachine.h:27
llvm::ARMSubtarget::hasV8_5aOps
bool hasV8_5aOps() const
Definition: ARMSubtarget.h:639
llvm::ARMSubtarget::hasSB
bool hasSB() const
Definition: ARMSubtarget.h:746
llvm::ARMSubtarget::hasV5TOps
bool hasV5TOps() const
Definition: ARMSubtarget.h:627
llvm::ARMSubtarget::NoBTIAtReturnTwice
bool NoBTIAtReturnTwice
NoBTIAtReturnTwice - Don't place a BTI instruction after return-twice constructs (setjmp)
Definition: ARMSubtarget.h:544
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AllocatorList.h:23
llvm::ARMSubtarget::ARMProcFamilyEnum
ARMProcFamilyEnum
Definition: ARMSubtarget.h:49
llvm::ARMSubtarget::SlowFPBrcc
bool SlowFPBrcc
SlowFPBrcc - True if floating point compare + branch is slow.
Definition: ARMSubtarget.h:241
llvm::ARMSubtarget::hasFusion
bool hasFusion() const
Return true if the CPU supports any kind of instruction fusion.
Definition: ARMSubtarget.h:765
llvm::ARMSubtarget::ARMv9a
@ ARMv9a
Definition: ARMSubtarget.h:130
llvm::ARMSubtarget::hasMVEFloatOps
bool hasMVEFloatOps() const
Definition: ARMSubtarget.h:651
llvm::ARMSubtarget::hasARMOps
bool hasARMOps() const
Definition: ARMSubtarget.h:673
llvm::ARMSubtarget::isTargetAndroid
bool isTargetAndroid() const
Definition: ARMSubtarget.h:815
llvm::ARMSubtarget::computeIssueWidth
void computeIssueWidth()
llvm::ARMSubtarget::HasSlowVDUP32
bool HasSlowVDUP32
If true, VMOV will be favored over VDUP.
Definition: ARMSubtarget.h:405
llvm::ARMSubtarget::getLegalizerInfo
const LegalizerInfo * getLegalizerInfo() const override
Definition: ARMSubtarget.cpp:136
llvm::ARMSubtarget::HasVMLxForwarding
bool HasVMLxForwarding
HasVMLxForwarding - If true, NEON has special multiplier accumulator forwarding to allow mul + mla be...
Definition: ARMSubtarget.h:238
llvm::ARMSubtarget::HasVirtualization
bool HasVirtualization
HasVirtualization - True if the subtarget supports the Virtualization extension.
Definition: ARMSubtarget.h:346
llvm::ARMSubtarget::enableMachineScheduler
bool enableMachineScheduler() const override
Returns true if machine scheduler should be enabled.
Definition: ARMSubtarget.cpp:381
llvm::ARMSubtarget::NoARM
bool NoARM
NoARM - True if subtarget does not support ARM mode execution.
Definition: ARMSubtarget.h:260
llvm::ARMSubtarget::hasV9_0aOps
bool hasV9_0aOps() const
Definition: ARMSubtarget.h:643
CallLowering.h
llvm::ARMSubtarget::HasV8_1MMainlineOps
bool HasV8_1MMainlineOps
Definition: ARMSubtarget.h:187
llvm::ARMSubtarget::CortexA57
@ CortexA57
Definition: ARMSubtarget.h:60
ARMGenSubtargetInfo
llvm::TargetOptions
Definition: TargetOptions.h:124
llvm::ARMSubtarget::HasVFPv2
bool HasVFPv2
HasVFPv2, HasVFPv3, HasVFPv4, HasFPARMv8, HasNEON - Specify what floating point ISAs are supported.
Definition: ARMSubtarget.h:194
llvm::Triple::isOSBinFormatCOFF
bool isOSBinFormatCOFF() const
Tests whether the OS uses the COFF binary format.
Definition: Triple.h:621
llvm::ARMSubtarget::GenLongCalls
bool GenLongCalls
Generate calls via indirect call instructions.
Definition: ARMSubtarget.h:467
llvm::ARMSubtarget
Definition: ARMSubtarget.h:47
llvm::ARMSubtarget::ARMv7m
@ ARMv7m
Definition: ARMSubtarget.h:114
llvm::ARMSubtarget::HasTrustZone
bool HasTrustZone
HasTrustZone - if true, processor supports TrustZone security extensions.
Definition: ARMSubtarget.h:358
llvm::ARMSubtarget::hasVMLxForwarding
bool hasVMLxForwarding() const
Definition: ARMSubtarget.h:712
llvm::ARMSubtarget::HasNEON
bool HasNEON
Definition: ARMSubtarget.h:198
llvm::ARMSubtarget::isAClass
bool isAClass() const
Definition: ARMSubtarget.h:836
llvm::ARMSubtarget::hasPACBTI
bool hasPACBTI() const
Definition: ARMSubtarget.h:687
llvm::ARMSubtarget::hasFPRegs64
bool hasFPRegs64() const
Definition: ARMSubtarget.h:655
llvm::ARMSubtarget::HasFPARMv8SP
bool HasFPARMv8SP
Definition: ARMSubtarget.h:208
llvm::ARMSubtarget::isTargetWatchOS
bool isTargetWatchOS() const
Definition: ARMSubtarget.h:773
llvm::ARMSubtarget::getMispredictionPenalty
unsigned getMispredictionPenalty() const
Definition: ARMSubtarget.cpp:377
llvm::ARMSubtarget::HasFullDataBarrier
bool HasFullDataBarrier
HasFullDataBarrier - True if the subtarget supports DFB data barrier instruction.
Definition: ARMSubtarget.h:305
llvm::ARMSubtarget::HasThumb2
bool HasThumb2
HasThumb2 - True if Thumb2 instructions are supported.
Definition: ARMSubtarget.h:257
llvm::ARMSubtarget::getPartialUpdateClearance
unsigned getPartialUpdateClearance() const
Definition: ARMSubtarget.h:909
llvm::ARMSubtarget::isCortexM3
bool isCortexM3() const
Definition: ARMSubtarget.h:666
llvm::ARMSubtarget::Has8MSecExt
bool Has8MSecExt
Has8MSecExt - if true, processor supports ARMv8-M Security Extensions.
Definition: ARMSubtarget.h:361
llvm::ARMSubtarget::Pref32BitThumb
bool Pref32BitThumb
Pref32BitThumb - If true, codegen would prefer 32-bit Thumb instructions over 16-bit ones.
Definition: ARMSubtarget.h:316
llvm::ARMSubtarget::hasFPARMv8Base
bool hasFPARMv8Base() const
Definition: ARMSubtarget.h:678
llvm::ARMSubtarget::StrictAlign
bool StrictAlign
StrictAlign - If true, the subtarget disallows unaligned memory accesses for some types.
Definition: ARMSubtarget.h:453
llvm::ARMSubtarget::ARMProcFamily
ARMProcFamilyEnum ARMProcFamily
ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.
Definition: ARMSubtarget.h:153
llvm::ARMSubtarget::hasSHA2
bool hasSHA2() const
Definition: ARMSubtarget.h:680
llvm::ARMSubtarget::isReadTPHard
bool isReadTPHard() const
Definition: ARMSubtarget.h:837
llvm::Triple::MuslEABIHF
@ MuslEABIHF
Definition: Triple.h:226
llvm::ARMSubtarget::hasFP16FML
bool hasFP16FML() const
Definition: ARMSubtarget.h:759
ARMMachineFunctionInfo.h
RegisterBankInfo.h
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
llvm::ARMSubtarget::useFPVFMx
bool useFPVFMx() const
Definition: ARMSubtarget.h:707
llvm::ARMSubtarget::HasFPARMv8D16
bool HasFPARMv8D16
Definition: ARMSubtarget.h:211
llvm::ARMSubtarget::hasBF16
bool hasBF16() const
Definition: ARMSubtarget.h:760
llvm::ARMSubtarget::hasV9_3aOps
bool hasV9_3aOps() const
Definition: ARMSubtarget.h:646
llvm::TargetTransformInfo::TCK_CodeSize
@ TCK_CodeSize
Instruction code size.
Definition: TargetTransformInfo.h:214
llvm::ARMSubtarget::hasV6T2Ops
bool hasV6T2Ops() const
Definition: ARMSubtarget.h:632
llvm::ARMSubtarget::getTargetTriple
const Triple & getTargetTriple() const
Definition: ARMSubtarget.h:769
llvm::ARMSubtarget::HasV8MMainlineOps
bool HasV8MMainlineOps
Definition: ARMSubtarget.h:186
llvm::ARMSubtarget::isRWPI
bool isRWPI() const
Definition: ARMSubtarget.cpp:353
llvm::ARMSubtarget::HardenSlsBlr
bool HardenSlsBlr
Harden against Straight Line Speculation for indirect calls.
Definition: ARMSubtarget.h:493
llvm::ARMSubtarget::ParseSubtargetFeatures
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
llvm::ARMSubtarget::ARMv7r
@ ARMv7r
Definition: ARMSubtarget.h:115
llvm::ARMSubtarget::getPreISelOperandLatencyAdjustment
int getPreISelOperandLatencyAdjustment() const
Definition: ARMSubtarget.h:915
llvm::ARMSubtarget::hasV8_3aOps
bool hasV8_3aOps() const
Definition: ARMSubtarget.h:637
llvm::ARMSubtarget::HasRAS
bool HasRAS
HasRAS - if true, the processor supports RAS extensions.
Definition: ARMSubtarget.h:376
llvm::ARMTargetLowering
Definition: ARMISelLowering.h:390
llvm::ARMSubtarget::getInstrItineraryData
const InstrItineraryData * getInstrItineraryData() const override
getInstrItins - Return the instruction itineraries based on subtarget selection.
Definition: ARMSubtarget.h:898
llvm::ARMSubtarget::HasFuseAES
bool HasFuseAES
HasFuseAES - if true, processor executes back to back AES instruction pairs faster.
Definition: ARMSubtarget.h:392
llvm::ARMSubtarget::hasThumb2
bool hasThumb2() const
Definition: ARMSubtarget.h:833
llvm::ARMSubtarget::getTargetLowering
const ARMTargetLowering * getTargetLowering() const override
Definition: ARMSubtarget.h:587
llvm::ARMSubtarget::NegativeImmediates
bool NegativeImmediates
Implicitly convert an instruction to a different one if its immediates cannot be encoded.
Definition: ARMSubtarget.h:483
llvm::ARMSubtarget::ARMv83a
@ ARMv83a
Definition: ARMSubtarget.h:119
llvm::ARMSubtarget::HasRetAddrStack
bool HasRetAddrStack
HasRetAddrStack - Some processors perform return stack prediction.
Definition: ARMSubtarget.h:333
llvm::ARMSubtarget::hasDivideInARMMode
bool hasDivideInARMMode() const
Definition: ARMSubtarget.h:695
llvm::ARMSubtarget::getInstrInfo
const ARMBaseInstrInfo * getInstrInfo() const override
Definition: ARMSubtarget.h:583
llvm::ARMSubtarget::hasAES
bool hasAES() const
Definition: ARMSubtarget.h:681
llvm::ARMSubtarget::CortexM7
@ CortexM7
Definition: ARMSubtarget.h:73
llvm::ARMSubtarget::HasVFPv4SP
bool HasVFPv4SP
Definition: ARMSubtarget.h:207
llvm::ARMSubtarget::hasMVEIntegerOps
bool hasMVEIntegerOps() const
Definition: ARMSubtarget.h:650
llvm::Triple::isOSLinux
bool isOSLinux() const
Tests whether the OS is Linux.
Definition: Triple.h:579
llvm::ARMSubtarget::getSelectionDAGInfo
const ARMSelectionDAGInfo * getSelectionDAGInfo() const override
Definition: ARMSubtarget.h:579
llvm::ARMSubtarget::HasVMLxHazards
bool HasVMLxHazards
If true, VFP/NEON VMLA/VMLS have special RAW hazards.
Definition: ARMSubtarget.h:436
llvm::ARMSubtarget::ARMv7a
@ ARMv7a
Definition: ARMSubtarget.h:112
llvm::ARMSubtarget::hasV9_2aOps
bool hasV9_2aOps() const
Definition: ARMSubtarget.h:645
llvm::ARMSubtarget::getStackAlignment
Align getStackAlignment() const
getStackAlignment - Returns the minimum alignment known to hold of the stack frame on entry to the fu...
Definition: ARMSubtarget.h:905
llvm::ARMSubtarget::hasSlowVGETLNi32
bool hasSlowVGETLNi32() const
Definition: ARMSubtarget.h:721
llvm::ARMSubtarget::hardenSlsNoComdat
bool hardenSlsNoComdat() const
Definition: ARMSubtarget.h:963
llvm::ARMSubtarget::HasBF16
bool HasBF16
HasBF16 - True if subtarget supports BFloat16 floating point operations.
Definition: ARMSubtarget.h:284
llvm::ARMSubtarget::expandMLx
bool expandMLx() const
Definition: ARMSubtarget.h:725
llvm::ARMSubtarget::hasV9_1aOps
bool hasV9_1aOps() const
Definition: ARMSubtarget.h:644
llvm::ARMSubtarget::hasV8_6aOps
bool hasV8_6aOps() const
Definition: ARMSubtarget.h:640
llvm::ARMSubtarget::HasV8_1aOps
bool HasV8_1aOps
Definition: ARMSubtarget.h:173
llvm::ARMSubtarget::isTargetLinux
bool isTargetLinux() const
Definition: ARMSubtarget.h:775
llvm::ARMSubtarget::supportsTailCall
bool supportsTailCall() const
Definition: ARMSubtarget.h:865
llvm::ARMSubtarget::useNEONForFPMovs
bool useNEONForFPMovs() const
Definition: ARMSubtarget.h:733
llvm::ARMSubtarget::getMaxInlineSizeThreshold
unsigned getMaxInlineSizeThreshold() const
getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size that still makes it profitable t...
Definition: ARMSubtarget.h:561
llvm::ARMSubtarget::ARMLdStMultipleTiming
ARMLdStMultipleTiming
What kind of timing do load multiple/store multiple instructions have.
Definition: ARMSubtarget.h:138
llvm::ARMSubtarget::UseMISched
bool UseMISched
UseMISched - True if MachineScheduler should be used for this subtarget.
Definition: ARMSubtarget.h:250
LegalizerInfo.h
llvm::ARMSubtarget::hasSlowVDUP32
bool hasSlowVDUP32() const
Definition: ARMSubtarget.h:722
llvm::ARMSubtarget::RClass
@ RClass
Definition: ARMSubtarget.h:93
llvm::ARMSubtarget::HasMVEFloatOps
bool HasMVEFloatOps
Definition: ARMSubtarget.h:189
llvm::ARMSubtarget::PreferISHST
bool PreferISHST
If true, ISHST barriers will be used for Release semantics.
Definition: ARMSubtarget.h:411
llvm::ARMSubtarget::Kryo
@ Kryo
Definition: ARMSubtarget.h:82
llvm::ARMSubtarget::isTargetWatchABI
bool isTargetWatchABI() const
Definition: ARMSubtarget.h:774
llvm::ARMSubtarget::ARMv2
@ ARMv2
Definition: ARMSubtarget.h:96
llvm::Triple::GNUEABI
@ GNUEABI
Definition: Triple.h:216
llvm::ARMSubtarget::ARMv92a
@ ARMv92a
Definition: ARMSubtarget.h:132
llvm::ARMSubtarget::ARMv93a
@ ARMv93a
Definition: ARMSubtarget.h:133
llvm::ARMSubtarget::OptMinSize
bool OptMinSize
OptMinSize - True if we're optimising for minimum code size, equal to the function attribute.
Definition: ARMSubtarget.h:528
llvm::ARMSubtarget::HasAES
bool HasAES
HasAES - if true, processor supports AES.
Definition: ARMSubtarget.h:367
llvm::ARMSubtarget::ARMv84a
@ ARMv84a
Definition: ARMSubtarget.h:120
llvm::ARMSubtarget::HasVFPv2SP
bool HasVFPv2SP
Versions of the VFP flags restricted to single precision, or to 16 d-registers, or both.
Definition: ARMSubtarget.h:205
llvm::ARMSubtarget::HasV6KOps
bool HasV6KOps
Definition: ARMSubtarget.h:169
llvm::ARMSubtarget::hasDSP
bool hasDSP() const
Definition: ARMSubtarget.h:743
llvm::ARMSubtarget::HasV9_0aOps
bool HasV9_0aOps
Definition: ARMSubtarget.h:181
llvm::ARMSubtarget::hasD32
bool hasD32() const
Definition: ARMSubtarget.h:757
llvm::ARMSubtarget::HasVFPv4D16
bool HasVFPv4D16
Definition: ARMSubtarget.h:210
llvm::ARMSubtarget::avoidMOVsShifterOperand
bool avoidMOVsShifterOperand() const
Definition: ARMSubtarget.h:739
llvm::ARMSubtarget::preferVMOVSR
bool preferVMOVSR() const
Definition: ARMSubtarget.h:723
llvm::ARMSubtarget::NeoverseN1
@ NeoverseN1
Definition: ARMSubtarget.h:83
llvm::ARMSubtarget::splitFramePushPop
bool splitFramePushPop(const MachineFunction &MF) const
Returns true if the frame setup is split into two separate pushes (first r0-r7,lr then r8-r11),...
Definition: ARMSubtarget.h:853
llvm::ARMSubtarget::hasLOB
bool hasLOB() const
Definition: ARMSubtarget.h:686
llvm::ARMSubtarget::isTargetMuslAEABI
bool isTargetMuslAEABI() const
Definition: ARMSubtarget.h:801
ARMConstantPoolValue.h
llvm::ARMSubtarget::HasZeroCycleZeroing
bool HasZeroCycleZeroing
If true, the instructions "vmov.i32 d0, #0" and "vmov.i32 q0, #0" are particularly effective at zeroi...
Definition: ARMSubtarget.h:385
llvm::ARMSubtarget::ARMv6sm
@ ARMv6sm
Definition: ARMSubtarget.h:110
llvm::ARMSubtarget::ARMv7ve
@ ARMv7ve
Definition: ARMSubtarget.h:116
llvm::Triple::isAndroid
bool isAndroid() const
Tests whether the target is Android.
Definition: Triple.h:657
llvm::ARMSubtarget::hasMPExtension
bool hasMPExtension() const
Definition: ARMSubtarget.h:742
MCInstrItineraries.h
llvm::ARMSubtarget::CortexA73
@ CortexA73
Definition: ARMSubtarget.h:63
llvm::Triple::isOSBinFormatELF
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:616
llvm::ARMSubtarget::ARMv6
@ ARMv6
Definition: ARMSubtarget.h:106
TargetMachine.h
llvm::ARMSubtarget::useSoftFloat
bool useSoftFloat() const
Definition: ARMSubtarget.h:828
llvm::ARMSubtarget::CortexR5
@ CortexR5
Definition: ARMSubtarget.h:76
llvm::ARMSubtarget::NeoverseN2
@ NeoverseN2
Definition: ARMSubtarget.h:84
llvm::ARMSubtarget::AClass
@ AClass
Definition: ARMSubtarget.h:91
llvm::ARMSubtarget::IsLittle
bool IsLittle
IsLittle - The target is Little Endian.
Definition: ARMSubtarget.h:531
llvm::ARMSubtarget::useAA
bool useAA() const override
Enable use of alias analysis during code generation (during MI scheduling, DAGCombine,...
Definition: ARMSubtarget.h:891
llvm::ARMSubtarget::useFPVMLx
bool useFPVMLx() const
Definition: ARMSubtarget.h:706
llvm::ARMSubtarget::isFPBrccSlow
bool isFPBrccSlow() const
Definition: ARMSubtarget.h:713
llvm::ARMSubtarget::isLikeA9
bool isLikeA9() const
Definition: ARMSubtarget.h:668
llvm::ARMSubtarget::SchedModel
MCSchedModel SchedModel
SchedModel - Processor specific instruction costs.
Definition: ARMSubtarget.h:537
llvm::ARMSubtarget::ARMv8r
@ ARMv8r
Definition: ARMSubtarget.h:128
llvm::Triple::isOSDarwin
bool isOSDarwin() const
Is this a "Darwin" OS (macOS, iOS, tvOS or watchOS).
Definition: Triple.h:468
llvm::MachineFunction::getInfo
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Definition: MachineFunction.h:739
llvm::ARMSubtarget::disablePostRAScheduler
bool disablePostRAScheduler() const
Definition: ARMSubtarget.h:827
llvm::ARMSubtarget::HasVFPv3
bool HasVFPv3
Definition: ARMSubtarget.h:195
llvm::ARMSubtarget::enableAtomicExpand
bool enableAtomicExpand() const override
Definition: ARMSubtarget.cpp:420
llvm::ARMSubtarget::MaxInterleaveFactor
unsigned MaxInterleaveFactor
Definition: ARMSubtarget.h:505
llvm::ARMSubtarget::isCortexM7
bool isCortexM7() const
Definition: ARMSubtarget.h:667
llvm::Legalizer
Definition: Legalizer.h:30
llvm::ARMSubtarget::isCortexA5
bool isCortexA5() const
Definition: ARMSubtarget.h:660
llvm::ARMSubtarget::HasV4TOps
bool HasV4TOps
HasV4TOps, HasV5TOps, HasV5TEOps, HasV6Ops, HasV6MOps, HasV6KOps, HasV6T2Ops, HasV7Ops,...
Definition: ARMSubtarget.h:164
llvm::ARMSubtarget::CortexA72
@ CortexA72
Definition: ARMSubtarget.h:62
llvm::ARMSubtarget::hasV6KOps
bool hasV6KOps() const
Definition: ARMSubtarget.h:631
llvm::ARMSubtarget::DisablePostRAScheduler
bool DisablePostRAScheduler
DisablePostRAScheduler - False if scheduling should happen again after register allocation.
Definition: ARMSubtarget.h:254
llvm::ARMSubtarget::hasBranchPredictor
bool hasBranchPredictor() const
Definition: ARMSubtarget.h:741
llvm::ARMSubtarget::checkVLDnAccessAlignment
bool checkVLDnAccessAlignment() const
Definition: ARMSubtarget.h:734
llvm::ARMSubtarget::useMulOps
bool useMulOps() const
Definition: ARMSubtarget.h:705
llvm::ARMSubtarget::HasV8_8aOps
bool HasV8_8aOps
Definition: ARMSubtarget.h:179
llvm::ARMSubtarget::DoubleIssue
@ DoubleIssue
Can load/store 2 registers/cycle.
Definition: ARMSubtarget.h:140
llvm::ARMSubtarget::useMovt
bool useMovt() const
Definition: ARMSubtarget.cpp:430
llvm::ARMSubtarget::isCortexA15
bool isCortexA15() const
Definition: ARMSubtarget.h:664
llvm::ARMSubtarget::hasCrypto
bool hasCrypto() const
Definition: ARMSubtarget.h:682
llvm::ARMSubtarget::isTargetHardFloat
bool isTargetHardFloat() const
Definition: ARMSubtarget.cpp:333
llvm::ARMSubtarget::nonpipelinedVFP
bool nonpipelinedVFP() const
Definition: ARMSubtarget.h:735
llvm::ARMSubtarget::ARMArchEnum
ARMArchEnum
Definition: ARMSubtarget.h:95
llvm::ARMSubtarget::ReadTPHard
bool ReadTPHard
Definition: ARMSubtarget.h:439
llvm::ARMSubtarget::isAAPCS16_ABI
bool isAAPCS16_ABI() const
Definition: ARMSubtarget.cpp:344
llvm::ARMSubtarget::CortexA55
@ CortexA55
Definition: ARMSubtarget.h:59
llvm::ARMSubtarget::HardenSlsNoComdat
bool HardenSlsNoComdat
Generate thunk code for SLS mitigation in the normal text section.
Definition: ARMSubtarget.h:496
llvm::ARMSubtarget::HasHardwareDivideInARM
bool HasHardwareDivideInARM
HasHardwareDivideInARM - True if subtarget supports [su]div in ARM mode.
Definition: ARMSubtarget.h:297
llvm::ARMSubtarget::CheckVLDnAlign
bool CheckVLDnAlign
If true, VLDn instructions take an extra cycle for unaligned accesses.
Definition: ARMSubtarget.h:445
llvm::ARMSubtarget::HasSHA2
bool HasSHA2
HasSHA2 - if true, processor supports SHA1 and SHA256.
Definition: ARMSubtarget.h:364
llvm::ARMSubtarget::ARMv5
@ ARMv5
Definition: ARMSubtarget.h:102
llvm::ARMSubtarget::HasDSP
bool HasDSP
HasDSP - If true, the subtarget supports the DSP (saturating arith and such) instructions.
Definition: ARMSubtarget.h:461
llvm::ARMSubtarget::ExpandMLx
bool ExpandMLx
If true, run the MLx expansion pass.
Definition: ARMSubtarget.h:433
llvm::ARMSubtarget::DoubleIssueCheckUnalignedAccess
@ DoubleIssueCheckUnalignedAccess
Can load/store 2 registers/cycle, but needs an extra cycle if the access is not 64-bit aligned.
Definition: ARMSubtarget.h:143
llvm::Triple::isOSBinFormatMachO
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
Definition: Triple.h:629
llvm::ARMSubtarget::UseSoftFloat
bool UseSoftFloat
UseSoftFloat - True if we're using software floating point features.
Definition: ARMSubtarget.h:247
llvm::ARMSubtarget::HasFP16
bool HasFP16
HasFP16 - True if subtarget supports half-precision FP conversions.
Definition: ARMSubtarget.h:275
llvm::ARMSubtarget::ARMv81a
@ ARMv81a
Definition: ARMSubtarget.h:117
llvm::ARMSubtarget::DontWidenVMOVS
bool DontWidenVMOVS
If true, VMOVS will never be widened to VMOVD.
Definition: ARMSubtarget.h:427
llvm::ARMSubtarget::ARMv5tej
@ ARMv5tej
Definition: ARMSubtarget.h:105
llvm::ARMSubtarget::getNoBTIAtReturnTwice
bool getNoBTIAtReturnTwice() const
Definition: ARMSubtarget.h:965
llvm::ARMSubtarget::isTargetAEABI
bool isTargetAEABI() const
Definition: ARMSubtarget.h:791
llvm::ARMSubtarget::HasV6Ops
bool HasV6Ops
Definition: ARMSubtarget.h:167
llvm::ARMSubtarget::hasSlowOddRegister
bool hasSlowOddRegister() const
Definition: ARMSubtarget.h:727
llvm::ARMSubtarget::PrefLoopLogAlignment
unsigned PrefLoopLogAlignment
What alignment is preferred for loop bodies, in log2(bytes).
Definition: ARMSubtarget.h:519
llvm::ARMSubtarget::HasDotProd
bool HasDotProd
HasDotProd - True if the ARMv8.2A dot product instructions are supported.
Definition: ARMSubtarget.h:217
llvm::ARMSubtarget::CortexA78C
@ CortexA78C
Definition: ARMSubtarget.h:68
llvm::ARMSubtarget::ARMv4
@ ARMv4
Definition: ARMSubtarget.h:100
llvm::ARMSubtarget::enablePostRAScheduler
bool enablePostRAScheduler() const override
True for some subtargets at > -O0.
Definition: ARMSubtarget.cpp:403
llvm::ARMSubtarget::isKrait
bool isKrait() const
Definition: ARMSubtarget.h:670
llvm::ARMSubtarget::hasV6Ops
bool hasV6Ops() const
Definition: ARMSubtarget.h:629
llvm::Triple::MuslEABI
@ MuslEABI
Definition: Triple.h:225
llvm::ARMSubtarget::has8MSecExt
bool has8MSecExt() const
Definition: ARMSubtarget.h:717
Align
uint64_t Align
Definition: ELFObjHandler.cpp:82
llvm::ARMSubtarget::hasCDEOps
bool hasCDEOps() const
Definition: ARMSubtarget.h:652
llvm::ARMSubtarget::hasFP64
bool hasFP64() const
Definition: ARMSubtarget.h:714
llvm::ARMSubtarget::HasMVEIntegerOps
bool HasMVEIntegerOps
Definition: ARMSubtarget.h:188
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::ARMSubtarget::ARMv8a
@ ARMv8a
Definition: ARMSubtarget.h:125
llvm::ARMSubtarget::HasFPARMv8
bool HasFPARMv8
Definition: ARMSubtarget.h:197
llvm::ARMSubtarget::CortexA7
@ CortexA7
Definition: ARMSubtarget.h:61
llvm::ARMSubtarget::ARMv8mBaseline
@ ARMv8mBaseline
Definition: ARMSubtarget.h:126
llvm::ARMSubtarget::HasFuseLiterals
bool HasFuseLiterals
HasFuseLiterals - if true, processor executes back to back bottom and top halves of literal generatio...
Definition: ARMSubtarget.h:396
llvm::ARMSubtarget::getMVEVectorCostFactor
unsigned getMVEVectorCostFactor(TargetTransformInfo::TargetCostKind CostKind) const
Definition: ARMSubtarget.h:949
llvm::Triple::isOSNaCl
bool isOSNaCl() const
Tests whether the OS is NaCl (Native Client)
Definition: Triple.h:574
llvm::ARMSubtarget::ARMv3
@ ARMv3
Definition: ARMSubtarget.h:98
llvm::ARMSubtarget::getRegBankInfo
const RegisterBankInfo * getRegBankInfo() const override
Definition: ARMSubtarget.cpp:140
llvm::ARMSubtarget::hasVFP3Base
bool hasVFP3Base() const
Definition: ARMSubtarget.h:676
llvm::ARMSubtarget::hasFP16
bool hasFP16() const
Definition: ARMSubtarget.h:756
llvm::ARMSubtarget::isSwift
bool isSwift() const
Definition: ARMSubtarget.h:665
llvm::X86AS::FS
@ FS
Definition: X86.h:188
llvm::ARMSubtarget::FixCMSE_CVE_2021_35465
bool FixCMSE_CVE_2021_35465
Mitigate against the cve-2021-35465 security vulnurability.
Definition: ARMSubtarget.h:486
llvm::ARMSubtarget::HasV6T2Ops
bool HasV6T2Ops
Definition: ARMSubtarget.h:170
llvm::ARMSubtarget::HasSlowVGETLNi32
bool HasSlowVGETLNi32
If true, VMOV will be favored over VGETLNi32.
Definition: ARMSubtarget.h:402
llvm::ARMSubtarget::ARMv91a
@ ARMv91a
Definition: ARMSubtarget.h:131
llvm::ARMSubtarget::ARMProcClassEnum
ARMProcClassEnum
Definition: ARMSubtarget.h:88
llvm::ARMSubtarget::HasFullFP16
bool HasFullFP16
HasFullFP16 - True if subtarget supports half-precision FP operations.
Definition: ARMSubtarget.h:278
llvm::ARMSubtarget::HasV8Ops
bool HasV8Ops
Definition: ARMSubtarget.h:172
llvm::ARMSubtarget::TargetTriple
Triple TargetTriple
TargetTriple - What processor and OS we're targeting.
Definition: ARMSubtarget.h:534
llvm::ARMSubtarget::ARMv6t2
@ ARMv6t2
Definition: ARMSubtarget.h:111
InstructionSelector.h
llvm::TargetOptions::DisableFramePointerElim
bool DisableFramePointerElim(const MachineFunction &MF) const
DisableFramePointerElim - This returns true if frame pointer elimination optimization should be disab...
Definition: TargetOptionsImpl.cpp:24
ARMSelectionDAGInfo.h
llvm::ARMSubtarget::SlowLoadDSubregister
bool SlowLoadDSubregister
If true, loading into a D subregister will be penalized.
Definition: ARMSubtarget.h:418
llvm::ARMSubtarget::hasV8_4aOps
bool hasV8_4aOps() const
Definition: ARMSubtarget.h:638
llvm::ARMSubtarget::CortexA9
@ CortexA9
Definition: ARMSubtarget.h:71
llvm::ARMSubtarget::PreferVMOVSR
bool PreferVMOVSR
If true, VMOVSR will be favored over VMOVDRR.
Definition: ARMSubtarget.h:408
llvm::ARMSubtarget::hasFPRegs16
bool hasFPRegs16() const
Definition: ARMSubtarget.h:654
llvm::Triple::isTargetEHABICompatible
bool isTargetEHABICompatible() const
Tests whether the target supports the EHABI exception handling standard.
Definition: Triple.h:713
llvm::ARMSubtarget::HasFPRegs16
bool HasFPRegs16
Definition: ARMSubtarget.h:200
llvm::ARMSubtarget::hardenSlsBlr
bool hardenSlsBlr() const
Definition: ARMSubtarget.h:962
llvm::ARMSubtarget::hasTrustZone
bool hasTrustZone() const
Definition: ARMSubtarget.h:716
llvm::RegisterBankInfo
Holds all the information related to register banks.
Definition: RegisterBankInfo.h:39
llvm::GlobalValue
Definition: GlobalValue.h:44
llvm::InstructionSelector
Provides the logic to select generic machine instructions.
Definition: InstructionSelector.h:423
llvm::ARMSubtarget::CheapPredicableCPSRDef
bool CheapPredicableCPSRDef
CheapPredicableCPSRDef - If true, disable +1 predication cost for instructions updating CPSR.
Definition: ARMSubtarget.h:325
ARMBaseRegisterInfo.h
MCSchedule.h
llvm::ARMSubtarget::HasV9_1aOps
bool HasV9_1aOps
Definition: ARMSubtarget.h:182
llvm::ARMSubtarget::isThumb1Only
bool isThumb1Only() const
Definition: ARMSubtarget.h:831
llvm::ARMSubtarget::getCPUString
const std::string & getCPUString() const
Definition: ARMSubtarget.h:871
llvm::ARMSubtarget::cheapPredicableCPSRDef
bool cheapPredicableCPSRDef() const
Definition: ARMSubtarget.h:738
llvm::ARMSubtarget::allowPositionIndependentMovt
bool allowPositionIndependentMovt() const
Allow movt+movw for PIC global address calculation.
Definition: ARMSubtarget.h:942
llvm::ARMSubtarget::isRClass
bool isRClass() const
Definition: ARMSubtarget.h:835
llvm::ARMSubtarget::hasMuxedUnits
bool hasMuxedUnits() const
Definition: ARMSubtarget.h:730
llvm::ARMSubtarget::preferISHSTBarriers
bool preferISHSTBarriers() const
Definition: ARMSubtarget.h:724
llvm::ARMSubtarget::InstrItins
InstrItineraryData InstrItins
Selected instruction itineraries (one entry per itinerary class.)
Definition: ARMSubtarget.h:540
llvm::ARMSubtarget::hasZeroCycleZeroing
bool hasZeroCycleZeroing() const
Definition: ARMSubtarget.h:718
llvm::ARMSubtarget::HasPACBTI
bool HasPACBTI
Definition: ARMSubtarget.h:381
llvm::ARMSubtarget::LdStMultipleTiming
ARMLdStMultipleTiming LdStMultipleTiming
What kind of timing do load multiple/store multiple have (double issue, single issue etc).
Definition: ARMSubtarget.h:512
llvm::ARMSubtarget::ARMv82a
@ ARMv82a
Definition: ARMSubtarget.h:118
llvm::ARMSubtarget::hasPerfMon
bool hasPerfMon() const
Definition: ARMSubtarget.h:715
llvm::ARMSubtarget::prefers32BitThumb
bool prefers32BitThumb() const
Definition: ARMSubtarget.h:736
llvm::ARMSubtarget::hasFPAO
bool hasFPAO() const
Definition: ARMSubtarget.h:719
llvm::ARMSubtarget::HasV8_6aOps
bool HasV8_6aOps
Definition: ARMSubtarget.h:178
llvm::ARMSubtarget::ARMSubtarget
ARMSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS, const ARMBaseTargetMachine &TM, bool IsLittle, bool MinSize=false)
This constructor initializes the data members to match that of the specified triple.
Definition: ARMSubtarget.cpp:97
llvm::ARMSubtarget::isR9Reserved
bool isR9Reserved() const
Definition: ARMSubtarget.h:839
llvm::ARMSubtarget::getLdStMultipleTiming
ARMLdStMultipleTiming getLdStMultipleTiming() const
Definition: ARMSubtarget.h:911
llvm::ARMSubtarget::CortexA75
@ CortexA75
Definition: ARMSubtarget.h:64
llvm::ARMSubtarget::GenExecuteOnly
bool GenExecuteOnly
Generate code that does not contain data access to code sections.
Definition: ARMSubtarget.h:470
llvm::ARMSubtarget::isTargetNetBSD
bool isTargetNetBSD() const
Definition: ARMSubtarget.h:777
llvm::ARMSubtarget::isMClass
bool isMClass() const
Definition: ARMSubtarget.h:834
llvm::ARMSubtarget::stackAlignment
Align stackAlignment
stackAlignment - The minimum alignment known to hold of the stack frame on entry to the function and ...
Definition: ARMSubtarget.h:500
llvm::ARMSubtarget::HasV6MOps
bool HasV6MOps
Definition: ARMSubtarget.h:168
llvm::ARMSubtarget::avoidCPSRPartialUpdate
bool avoidCPSRPartialUpdate() const
Definition: ARMSubtarget.h:737
llvm::ARMSubtarget::HasBranchPredictor
bool HasBranchPredictor
HasBranchPredictor - True if the subtarget has a branch predictor.
Definition: ARMSubtarget.h:338
llvm::ARMSubtarget::initializeSubtargetDependencies
ARMSubtarget & initializeSubtargetDependencies(StringRef CPU, StringRef FS)
initializeSubtargetDependencies - Initializes using a CPU and feature string so that we can use initi...
Definition: ARMSubtarget.cpp:81
llvm::ARMSubtarget::InThumbMode
bool InThumbMode
InThumbMode - True if compiling for Thumb, false for ARM.
Definition: ARMSubtarget.h:244
llvm::ARMSubtarget::SlowFPVFMx
bool SlowFPVFMx
SlowFPVFMx - If the VFP4 / NEON instructions are available, indicates whether the FP VFM[AS] instruct...
Definition: ARMSubtarget.h:234
llvm::ARMSubtarget::isProfitableToUnpredicate
bool isProfitableToUnpredicate() const
Definition: ARMSubtarget.h:720
llvm::ARMSubtarget::HasHardwareDivideInThumb
bool HasHardwareDivideInThumb
HasHardwareDivide - True if subtarget supports [su]div in Thumb mode.
Definition: ARMSubtarget.h:294
llvm::ARMBaseInstrInfo
Definition: ARMBaseInstrInfo.h:37
llvm::ARMSubtarget::getFramePointerReg
MCPhysReg getFramePointerReg() const
Definition: ARMSubtarget.h:843
llvm::ARMSubtarget::isTargetIOS
bool isTargetIOS() const
Definition: ARMSubtarget.h:772
llvm::ARMSubtarget::dontWidenVMOVS
bool dontWidenVMOVS() const
Definition: ARMSubtarget.h:731
llvm::Triple::isWatchABI
bool isWatchABI() const
Definition: Triple.h:461
llvm::ARMSubtarget::CPUString
std::string CPUString
CPUString - String name of used CPU.
Definition: ARMSubtarget.h:503
llvm::ARMSubtarget::isTargetELF
bool isTargetELF() const
Definition: ARMSubtarget.h:781
llvm::ARMSubtarget::hasV7Ops
bool hasV7Ops() const
Definition: ARMSubtarget.h:633
llvm::ARMSubtarget::NoMovt
bool NoMovt
NoMovt - True if MOVT / MOVW pairs are not used for materialization of 32-bit imms (including global ...
Definition: ARMSubtarget.h:267
llvm::ARMSubtarget::useSplatVFPToNeon
bool useSplatVFPToNeon() const
Definition: ARMSubtarget.h:732
llvm::ARMSubtarget::MVEVectorCostFactor
unsigned MVEVectorCostFactor
The cost factor for MVE instructions, representing the multiple beats an.
Definition: ARMSubtarget.h:524
llvm::ARMSubtarget::Options
const TargetOptions & Options
Options passed via command line that could influence the target.
Definition: ARMSubtarget.h:547
llvm::ARMSubtarget::RestrictIT
bool RestrictIT
RestrictIT - If true, the subtarget disallows generation of deprecated IT blocks to conform to ARMv8 ...
Definition: ARMSubtarget.h:457
llvm::ARMSubtarget::hasDataBarrier
bool hasDataBarrier() const
Definition: ARMSubtarget.h:696
llvm::ARMSubtarget::getFrameLowering
const ARMFrameLowering * getFrameLowering() const override
Definition: ARMSubtarget.h:591
llvm::ARMSubtarget::isTargetCOFF
bool isTargetCOFF() const
Definition: ARMSubtarget.h:780
llvm::TargetMachine::Options
TargetOptions Options
Definition: TargetMachine.h:121
llvm::ARMSubtarget::isROPI
bool isROPI() const
Definition: ARMSubtarget.cpp:349
llvm::ARMSubtarget::useNaClTrap
bool useNaClTrap() const
Definition: ARMSubtarget.h:744
llvm::ARMFrameLowering
Definition: ARMFrameLowering.h:21
llvm::ARMSubtarget::CortexA77
@ CortexA77
Definition: ARMSubtarget.h:66
llvm::ARMSubtarget::hasSlowLoadDSubregister
bool hasSlowLoadDSubregister() const
Definition: ARMSubtarget.h:728
ARMBaseInstrInfo.h
llvm::ARMSubtarget::ARMv4t
@ ARMv4t
Definition: ARMSubtarget.h:101
llvm::ARMSubtarget::hasFullFP16
bool hasFullFP16() const
Definition: ARMSubtarget.h:758
llvm::ARMSubtarget::enablePostRAMachineScheduler
bool enablePostRAMachineScheduler() const override
True for some subtargets at > -O0.
Definition: ARMSubtarget.cpp:412
llvm::ARMSubtarget::allowsUnalignedMem
bool allowsUnalignedMem() const
Definition: ARMSubtarget.h:867
llvm::ARMSubtarget::CortexM3
@ CortexM3
Definition: ARMSubtarget.h:72
llvm::ARMSubtarget::ARMv7em
@ ARMv7em
Definition: ARMSubtarget.h:113
llvm::ARMSubtarget::useNEONForSinglePrecisionFP
bool useNEONForSinglePrecisionFP() const
Definition: ARMSubtarget.h:690
llvm::ARMSubtarget::isLittle
bool isLittle() const
Definition: ARMSubtarget.h:873
llvm::ARMSubtarget::ARMv81mMainline
@ ARMv81mMainline
Definition: ARMSubtarget.h:129
llvm::ARMSubtarget::useFastISel
bool useFastISel() const
True if fast-isel is used.
Definition: ARMSubtarget.cpp:438
llvm::ARMSubtarget::ARMv3m
@ ARMv3m
Definition: ARMSubtarget.h:99
llvm::ARMSubtarget::UnsafeFPMath
bool UnsafeFPMath
Target machine allowed unsafe FP math (such as use of NEON fp)
Definition: ARMSubtarget.h:473
llvm::ARMSubtarget::HasFP64
bool HasFP64
HasFP64 - If true, the floating point unit supports double precision.
Definition: ARMSubtarget.h:350
llvm::MachineFunction
Definition: MachineFunction.h:241
llvm::ARMSubtarget::Exynos
@ Exynos
Definition: ARMSubtarget.h:80
llvm::ARMSubtarget::HasV8_7aOps
bool HasV8_7aOps
Definition: ARMSubtarget.h:180
llvm::ARMSubtarget::None
@ None
Definition: ARMSubtarget.h:89
llvm::ARMSubtarget::hasV7Clrex
bool hasV7Clrex() const
Definition: ARMSubtarget.h:698
Triple.h
llvm::ARMSubtarget::hasV8_2aOps
bool hasV8_2aOps() const
Definition: ARMSubtarget.h:636
llvm::ARMSubtarget::HasCRC
bool HasCRC
HasCRC - if true, processor supports CRC instructions.
Definition: ARMSubtarget.h:373
llvm::ARMSubtarget::ARMv6k
@ ARMv6k
Definition: ARMSubtarget.h:107
llvm::ARMSubtarget::HasFP16FML
bool HasFP16FML
HasFP16FML - True if subtarget supports half-precision FP fml operations.
Definition: ARMSubtarget.h:281
llvm::ARMSubtarget::hasDotProd
bool hasDotProd() const
Definition: ARMSubtarget.h:683
TargetOptions.h
llvm::ARMSubtarget::NonpipelinedVFP
bool NonpipelinedVFP
If true, VFP instructions are not pipelined.
Definition: ARMSubtarget.h:448
llvm::ARMSubtarget::getCallLowering
const CallLowering * getCallLowering() const override
Definition: ARMSubtarget.cpp:128
llvm::ARMSubtarget::SlowFPVMLx
bool SlowFPVMLx
SlowFPVMLx - If the VFP2 / NEON instructions are available, indicates whether the FP VML[AS] instruct...
Definition: ARMSubtarget.h:230
llvm::ARMSubtarget::hasNEON
bool hasNEON() const
Definition: ARMSubtarget.h:679
llvm::ARMSubtarget::getRegisterInfo
const ARMBaseRegisterInfo * getRegisterInfo() const override
Definition: ARMSubtarget.h:595
llvm::ARMSubtarget::hasMatMulInt8
bool hasMatMulInt8() const
Definition: ARMSubtarget.h:767
llvm::ARMSubtarget::hasVMLxHazards
bool hasVMLxHazards() const
Definition: ARMSubtarget.h:726
llvm::ARMSubtarget::CortexR4F
@ CortexR4F
Definition: ARMSubtarget.h:75
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
llvm::ARMSubtarget::useMachineScheduler
bool useMachineScheduler() const
Definition: ARMSubtarget.h:826
llvm::ARMSubtarget::hasCRC
bool hasCRC() const
Definition: ARMSubtarget.h:684
llvm::ARMSubtarget::ARMv87a
@ ARMv87a
Definition: ARMSubtarget.h:123
llvm::ARMSubtarget::hasRetAddrStack
bool hasRetAddrStack() const
Definition: ARMSubtarget.h:740
llvm::ARMSubtarget::HasVFPv3D16SP
bool HasVFPv3D16SP
Definition: ARMSubtarget.h:212
llvm::ARMSubtarget::PartialUpdateClearance
unsigned PartialUpdateClearance
Clearance before partial register updates (in number of instructions)
Definition: ARMSubtarget.h:508
llvm::ARMSubtarget::HasV9_3aOps
bool HasV9_3aOps
Definition: ARMSubtarget.h:184
CostKind
static cl::opt< TargetTransformInfo::TargetCostKind > CostKind("cost-kind", cl::desc("Target cost kind"), cl::init(TargetTransformInfo::TCK_RecipThroughput), cl::values(clEnumValN(TargetTransformInfo::TCK_RecipThroughput, "throughput", "Reciprocal throughput"), clEnumValN(TargetTransformInfo::TCK_Latency, "latency", "Instruction latency"), clEnumValN(TargetTransformInfo::TCK_CodeSize, "code-size", "Code size"), clEnumValN(TargetTransformInfo::TCK_SizeAndLatency, "size-latency", "Code size and latency")))
llvm::ARMSubtarget::ARMv2a
@ ARMv2a
Definition: ARMSubtarget.h:97
llvm::ARMFunctionInfo::shouldSignReturnAddress
bool shouldSignReturnAddress() const
Definition: ARMMachineFunctionInfo.h:283
TargetSubtargetInfo.h
llvm::ARMSubtarget::getInstructionSelector
InstructionSelector * getInstructionSelector() const override
Definition: ARMSubtarget.cpp:132
llvm::ARMSubtarget::UseNEONForSinglePrecisionFP
bool UseNEONForSinglePrecisionFP
UseNEONForSinglePrecisionFP - if the NEONFP attribute has been specified.
Definition: ARMSubtarget.h:222
llvm::ARMSubtarget::useFPVFMx64
bool useFPVFMx64() const
Definition: ARMSubtarget.h:711
llvm::Triple::isiOS
bool isiOS() const
Is this an iOS triple.
Definition: Triple.h:447
llvm::ARMSubtarget::getMaxInterleaveFactor
unsigned getMaxInterleaveFactor() const
Definition: ARMSubtarget.h:907
llvm::ARMSubtarget::isCortexA7
bool isCortexA7() const
Definition: ARMSubtarget.h:661
llvm::ARMSubtarget::ARMProcClass
ARMProcClassEnum ARMProcClass
ARMProcClass - ARM processor class: None, AClass, RClass or MClass.
Definition: ARMSubtarget.h:156
llvm::ARMSubtarget::HasV8_2aOps
bool HasV8_2aOps
Definition: ARMSubtarget.h:174
llvm::ARMSubtarget::hasVirtualization
bool hasVirtualization() const
Definition: ARMSubtarget.h:688
llvm::ARMSubtarget::CortexA15
@ CortexA15
Definition: ARMSubtarget.h:53
llvm::ARMSubtarget::hasV4TOps
bool hasV4TOps() const
Definition: ARMSubtarget.h:626
llvm::ARMSubtarget::ARMv86a
@ ARMv86a
Definition: ARMSubtarget.h:122
llvm::Triple::isWatchOS
bool isWatchOS() const
Is this an Apple watchOS triple.
Definition: Triple.h:457
llvm::ARMSelectionDAGInfo
Definition: ARMSelectionDAGInfo.h:38
llvm::ARMSubtarget::PreISelOperandLatencyAdjustment
int PreISelOperandLatencyAdjustment
The adjustment that we need to apply to get the operand latency from the operand cycle returned by th...
Definition: ARMSubtarget.h:516
llvm::ARMSubtarget::isCortexA9
bool isCortexA9() const
Definition: ARMSubtarget.h:663
llvm::ARMSubtarget::isTargetWindows
bool isTargetWindows() const
Definition: ARMSubtarget.h:778
llvm::ARMSubtarget::HasD32
bool HasD32
HasD32 - True if subtarget has the full 32 double precision FP registers for VFPv3.
Definition: ARMSubtarget.h:291
llvm::ARMSubtarget::isGVInGOT
bool isGVInGOT(const GlobalValue *GV) const
Returns the constant pool modifier needed to access the GV.
Definition: ARMSubtarget.cpp:372
llvm::ARMSubtarget::ARMv5t
@ ARMv5t
Definition: ARMSubtarget.h:103
llvm::ARMBaseRegisterInfo
Definition: ARMBaseRegisterInfo.h:100
llvm::Triple::isOSWindows
bool isOSWindows() const
Tests whether the OS is Windows.
Definition: Triple.h:531
llvm::ARMSubtarget::ignoreCSRForAllocationOrder
bool ignoreCSRForAllocationOrder(const MachineFunction &MF, unsigned PhysReg) const override
Definition: ARMSubtarget.cpp:484
llvm::ARMSubtarget::AvoidMOVsShifterOperand
bool AvoidMOVsShifterOperand
AvoidMOVsShifterOperand - If true, codegen should avoid using flag setting movs with shifter operand ...
Definition: ARMSubtarget.h:329
llvm::ARMSubtarget::Swift
@ Swift
Definition: ARMSubtarget.h:86
llvm::ARMSubtarget::CortexR4
@ CortexR4
Definition: ARMSubtarget.h:74
llvm::ARMSubtarget::CortexR52
@ CortexR52
Definition: ARMSubtarget.h:77
llvm::ARMSubtarget::UseMulOps
bool UseMulOps
UseMulOps - True if non-microcoded fused integer multiply-add and multiply-subtract instructions shou...
Definition: ARMSubtarget.h:226
llvm::ARMSubtarget::ARMv8mMainline
@ ARMv8mMainline
Definition: ARMSubtarget.h:127
llvm::ARMSubtarget::ARMArch
ARMArchEnum ARMArch
ARMArch - ARM architecture.
Definition: ARMSubtarget.h:159
llvm::ARMSubtarget::hasFPRegs
bool hasFPRegs() const
Definition: ARMSubtarget.h:653
ARMFrameLowering.h
llvm::ARMSubtarget::isTargetDarwin
bool isTargetDarwin() const
Definition: ARMSubtarget.h:771
llvm::ARMSubtarget::Krait
@ Krait
Definition: ARMSubtarget.h:81
uint16_t
llvm::ARMSubtarget::UseWideStrideVFP
bool UseWideStrideVFP
If true, use a wider stride when allocating VFP registers.
Definition: ARMSubtarget.h:421
llvm::MachineFunction::getTarget
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Definition: MachineFunction.h:637
llvm::ARMSubtarget::HasV8_4aOps
bool HasV8_4aOps
Definition: ARMSubtarget.h:176
llvm::ARMSubtarget::isCortexR5
bool isCortexR5() const
Definition: ARMSubtarget.h:669
llvm::ARMSubtarget::isAPCS_ABI
bool isAPCS_ABI() const
Definition: ARMSubtarget.cpp:335
llvm::ARMSubtarget::SingleIssue
@ SingleIssue
Can load/store 1 register/cycle.
Definition: ARMSubtarget.h:145
llvm::ARMSubtarget::isTargetMachO
bool isTargetMachO() const
Definition: ARMSubtarget.h:782
llvm::ARMSubtarget::HasV7Clrex
bool HasV7Clrex
HasV7Clrex - True if the subtarget supports CLREX instructions.
Definition: ARMSubtarget.h:308
llvm::ARMSubtarget::useFPVFMx16
bool useFPVFMx16() const
Definition: ARMSubtarget.h:710
llvm::ARMSubtarget::HasFPAO
bool HasFPAO
HasFPAO - if true, processor does positive address offset computation faster.
Definition: ARMSubtarget.h:388
llvm::ARMSubtarget::AvoidCPSRPartialUpdate
bool AvoidCPSRPartialUpdate
AvoidCPSRPartialUpdate - If true, codegen would avoid using instructions that partially update CPSR a...
Definition: ARMSubtarget.h:321
llvm::ARMSubtarget::isAAPCS_ABI
bool isAAPCS_ABI() const
Definition: ARMSubtarget.cpp:339
llvm::ARMSubtarget::NeoverseV1
@ NeoverseV1
Definition: ARMSubtarget.h:85
llvm::ARMSubtarget::Others
@ Others
Definition: ARMSubtarget.h:50
llvm::ARMSubtarget::HasMPExtension
bool HasMPExtension
HasMPExtension - True if the subtarget supports Multiprocessing extension (ARMv7 only).
Definition: ARMSubtarget.h:342
llvm::MCSchedModel
Machine model for scheduling, bundling, and heuristics.
Definition: MCSchedule.h:244
llvm::ARMSubtarget::HasVFPv4
bool HasVFPv4
Definition: ARMSubtarget.h:196
llvm::ARMSubtarget::CortexX1
@ CortexX1
Definition: ARMSubtarget.h:79
llvm::ARMSubtarget::hasV8_1MMainlineOps
bool hasV8_1MMainlineOps() const
Definition: ARMSubtarget.h:649
llvm::ARMSubtarget::HasVFPv4D16SP
bool HasVFPv4D16SP
Definition: ARMSubtarget.h:213
llvm::ARMSubtarget::hasV8_1aOps
bool hasV8_1aOps() const
Definition: ARMSubtarget.h:635
llvm::ARMSubtarget::getMaxMemcpyTPInlineSizeThreshold
unsigned getMaxMemcpyTPInlineSizeThreshold() const
getMaxMemcpyTPInlineSizeThreshold - Returns the maximum size that still makes it profitable to inline...
Definition: ARMSubtarget.h:569
llvm::ARMSubtarget::SingleIssuePlusExtras
@ SingleIssuePlusExtras
Can load/store 1 register/cycle, but needs an extra cycle for address computation and potentially als...
Definition: ARMSubtarget.h:148
llvm::ARMSubtarget::UseNEONForFPMovs
bool UseNEONForFPMovs
If true, VMOVRS, VMOVSR and VMOVS will be converted from VFP to NEON.
Definition: ARMSubtarget.h:442
llvm::ARMSubtarget::hasVFP4Base
bool hasVFP4Base() const
Definition: ARMSubtarget.h:677
llvm::ARMSubtarget::HasMuxedUnits
bool HasMuxedUnits
If true, the AGU and NEON/FPU units are multiplexed.
Definition: ARMSubtarget.h:424
llvm::ARMSubtarget::ARMv6m
@ ARMv6m
Definition: ARMSubtarget.h:109
llvm::ARMSubtarget::MClass
@ MClass
Definition: ARMSubtarget.h:92
llvm::ARMSubtarget::CortexA8
@ CortexA8
Definition: ARMSubtarget.h:70
llvm::ARMSubtarget::HasV8_5aOps
bool HasV8_5aOps
Definition: ARMSubtarget.h:177
llvm::ARMSubtarget::HardenSlsRetBr
bool HardenSlsRetBr
Harden against Straight Line Speculation for Returns and Indirect Branches.
Definition: ARMSubtarget.h:490
ARMISelLowering.h
llvm::ARMSubtarget::ARMv5te
@ ARMv5te
Definition: ARMSubtarget.h:104
llvm::ARMSubtarget::CortexA12
@ CortexA12
Definition: ARMSubtarget.h:52
llvm::ARMSubtarget::hasV8MMainlineOps
bool hasV8MMainlineOps() const
Definition: ARMSubtarget.h:648
llvm::ARMSubtarget::HasVFPv3D16
bool HasVFPv3D16
Definition: ARMSubtarget.h:209
llvm::ARMSubtarget::HasV9_2aOps
bool HasV9_2aOps
Definition: ARMSubtarget.h:183
llvm::ARMSubtarget::CortexA76
@ CortexA76
Definition: ARMSubtarget.h:65
llvm::Triple::isOSNetBSD
bool isOSNetBSD() const
Definition: Triple.h:486
llvm::ARMSubtarget::IsProfitableToUnpredicate
bool IsProfitableToUnpredicate
If true, if conversion may decide to leave some instructions unpredicated.
Definition: ARMSubtarget.h:399
llvm::ARMSubtarget::ReserveR9
bool ReserveR9
ReserveR9 - True if R9 is not available as a general purpose register.
Definition: ARMSubtarget.h:263
llvm::ARMSubtarget::isTargetEHABICompatible
bool isTargetEHABICompatible() const
Definition: ARMSubtarget.h:809
llvm::ARMSubtarget::CortexA35
@ CortexA35
Definition: ARMSubtarget.h:56
llvm::ARMSubtarget::HasDataBarrier
bool HasDataBarrier
HasDataBarrier - True if the subtarget supports DMB / DSB data barrier instructions.
Definition: ARMSubtarget.h:301
llvm::ARMSubtarget::CortexA78
@ CortexA78
Definition: ARMSubtarget.h:67
llvm::ARMSubtarget::hasMinSize
bool hasMinSize() const
Definition: ARMSubtarget.h:830
llvm::ARMSubtarget::CortexA53
@ CortexA53
Definition: ARMSubtarget.h:58
TargetTransformInfo.h
llvm::ARMSubtarget::hasAcquireRelease
bool hasAcquireRelease() const
Definition: ARMSubtarget.h:699
llvm::ARMSubtarget::SlowOddRegister
bool SlowOddRegister
If true, a VLDM/VSTM starting with an odd register number is considered to take more microops than si...
Definition: ARMSubtarget.h:415
llvm::ARMSubtarget::restrictIT
bool restrictIT() const
Definition: ARMSubtarget.h:869
llvm::ARMSubtarget::isGVIndirectSymbol
bool isGVIndirectSymbol(const GlobalValue *GV) const
True if the GV will be accessed via an indirect symbol.
Definition: ARMSubtarget.cpp:358
llvm::ARMSubtarget::hasV8MBaselineOps
bool hasV8MBaselineOps() const
Definition: ARMSubtarget.h:647
llvm::Triple::getEnvironment
EnvironmentType getEnvironment() const
Get the parsed environment type of this triple.
Definition: Triple.h:328
llvm::ARMSubtarget::ARMv85a
@ ARMv85a
Definition: ARMSubtarget.h:121
llvm::Triple::EABIHF
@ EABIHF
Definition: Triple.h:222
llvm::ARMSubtarget::CortexA5
@ CortexA5
Definition: ARMSubtarget.h:57
llvm::LegalizerInfo
Definition: LegalizerInfo.h:1143
llvm::Triple::GNUEABIHF
@ GNUEABIHF
Definition: Triple.h:217
llvm::ARMSubtarget::UseNaClTrap
bool UseNaClTrap
NaCl TRAP instruction is generated instead of the regular TRAP.
Definition: ARMSubtarget.h:464
llvm::ARMSubtarget::HasFPRegs
bool HasFPRegs
Definition: ARMSubtarget.h:199
llvm::ARMSubtarget::CortexA32
@ CortexA32
Definition: ARMSubtarget.h:55
llvm::ARMSubtarget::isThumb2
bool isThumb2() const
Definition: ARMSubtarget.h:832
llvm::ARMSubtarget::hasFuseAES
bool hasFuseAES() const
Definition: ARMSubtarget.h:762
llvm::ARMSubtarget::getPrefLoopLogAlignment
unsigned getPrefLoopLogAlignment() const
Definition: ARMSubtarget.h:946
llvm::ARMSubtarget::ARMv88a
@ ARMv88a
Definition: ARMSubtarget.h:124
llvm::ARMSubtarget::CortexA710
@ CortexA710
Definition: ARMSubtarget.h:69
llvm::ARMSubtarget::getGPRAllocationOrder
unsigned getGPRAllocationOrder(const MachineFunction &MF) const
Definition: ARMSubtarget.cpp:453
llvm::ARMSubtarget::HasMatMulInt8
bool HasMatMulInt8
HasMatMulInt8 - True if subtarget supports 8-bit integer matrix multiply.
Definition: ARMSubtarget.h:287
llvm::ARMSubtarget::HasV7Ops
bool HasV7Ops
Definition: ARMSubtarget.h:171
llvm::ARMSubtarget::useWideStrideVFP
bool useWideStrideVFP() const
Definition: ARMSubtarget.h:729
llvm::ARMSubtarget::HasPerfMon
bool HasPerfMon
If true, the processor supports the Performance Monitor Extensions.
Definition: ARMSubtarget.h:355
MachineFunction.h
llvm::ARMSubtarget::hasV5TEOps
bool hasV5TEOps() const
Definition: ARMSubtarget.h:628
llvm::ARMSubtarget::hasV8_7aOps
bool hasV8_7aOps() const
Definition: ARMSubtarget.h:641
llvm::Triple::EABI
@ EABI
Definition: Triple.h:221
llvm::ARMSubtarget::hasDivideInThumbMode
bool hasDivideInThumbMode() const
Definition: ARMSubtarget.h:694
llvm::CallLowering
Definition: CallLowering.h:43
llvm::ARMSubtarget::isTargetNaCl
bool isTargetNaCl() const
Definition: ARMSubtarget.h:776
llvm::ARMSubtarget::HasFPARMv8D16SP
bool HasFPARMv8D16SP
Definition: ARMSubtarget.h:214
llvm::ARMSubtarget::isXRaySupported
bool isXRaySupported() const override
Definition: ARMSubtarget.cpp:144
llvm::InstrItineraryData
Itinerary data supplied by a subtarget to be used by a target.
Definition: MCInstrItineraries.h:109
llvm::ARMSubtarget::isCortexA8
bool isCortexA8() const
Definition: ARMSubtarget.h:662
llvm::ARMSubtarget::SplatVFPToNeon
bool SplatVFPToNeon
If true, splat a register between VFP and NEON instructions.
Definition: ARMSubtarget.h:430
llvm::ARMSubtarget::isTargetGNUAEABI
bool isTargetGNUAEABI() const
Definition: ARMSubtarget.h:796
llvm::ARMSubtarget::hasAnyDataBarrier
bool hasAnyDataBarrier() const
Definition: ARMSubtarget.h:701
llvm::ARMSubtarget::hasFullDataBarrier
bool hasFullDataBarrier() const
Definition: ARMSubtarget.h:697
llvm::ARMSubtarget::HasSB
bool HasSB
Has speculation barrier.
Definition: ARMSubtarget.h:479
llvm::ARMSubtarget::useStride4VFPs
bool useStride4VFPs() const
Definition: ARMSubtarget.cpp:422
llvm::ARMSubtarget::hasFuseLiterals
bool hasFuseLiterals() const
Definition: ARMSubtarget.h:763
llvm::ARMSubtarget::hasVFP2Base
bool hasVFP2Base() const
Definition: ARMSubtarget.h:675
llvm::ARMSubtarget::getReturnOpcode
unsigned getReturnOpcode() const
Returns the correct return opcode for the current feature set.
Definition: ARMSubtarget.h:931
llvm::ARMSubtarget::genExecuteOnly
bool genExecuteOnly() const
Definition: ARMSubtarget.h:748
llvm::ARMSubtarget::HasLOB
bool HasLOB
HasLOB - if true, the processor supports the Low Overhead Branch extension.
Definition: ARMSubtarget.h:379
llvm::ARMSubtarget::isThumb
bool isThumb() const
Definition: ARMSubtarget.h:829
llvm::ARMSubtarget::hasV8Ops
bool hasV8Ops() const
Definition: ARMSubtarget.h:634
llvm::ARMSubtarget::HasFPRegs64
bool HasFPRegs64
Definition: ARMSubtarget.h:201
llvm::ARMSubtarget::HasV5TOps
bool HasV5TOps
Definition: ARMSubtarget.h:165
llvm::ARMSubtarget::HasV8MBaselineOps
bool HasV8MBaselineOps
Definition: ARMSubtarget.h:185
llvm::ARMSubtarget::ARMv6kz
@ ARMv6kz
Definition: ARMSubtarget.h:108