LLVM 19.0.0git
ARMSubtarget.h
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1//===-- ARMSubtarget.h - Define Subtarget for the ARM ----------*- C++ -*--===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file declares the ARM specific subclass of TargetSubtargetInfo.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H
14#define LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H
15
16#include "ARMBaseInstrInfo.h"
17#include "ARMBaseRegisterInfo.h"
19#include "ARMFrameLowering.h"
20#include "ARMISelLowering.h"
22#include "ARMSelectionDAGInfo.h"
31#include "llvm/MC/MCSchedule.h"
35#include <bitset>
36#include <memory>
37#include <string>
38
39#define GET_SUBTARGETINFO_HEADER
40#include "ARMGenSubtargetInfo.inc"
41
42namespace llvm {
43
44class ARMBaseTargetMachine;
45class GlobalValue;
46class StringRef;
47
49protected:
52#define ARM_PROCESSOR_FAMILY(ENUM) ENUM,
53#include "llvm/TargetParser/ARMTargetParserDef.inc"
54#undef ARM_PROCESSOR_FAMILY
55 };
58
61 RClass
62 };
64#define ARM_ARCHITECTURE(ENUM) ENUM,
65#include "llvm/TargetParser/ARMTargetParserDef.inc"
66#undef ARM_ARCHITECTURE
67 };
68
69public:
70 /// What kind of timing do load multiple/store multiple instructions have.
72 /// Can load/store 2 registers/cycle.
74 /// Can load/store 2 registers/cycle, but needs an extra cycle if the access
75 /// is not 64-bit aligned.
77 /// Can load/store 1 register/cycle.
79 /// Can load/store 1 register/cycle, but needs an extra cycle for address
80 /// computation and potentially also for register writeback.
82 };
83
84protected:
85// Bool members corresponding to the SubtargetFeatures defined in tablegen
86#define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \
87 bool ATTRIBUTE = DEFAULT;
88#include "ARMGenSubtargetInfo.inc"
89
90 /// ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.
92
93 /// ARMProcClass - ARM processor class: None, AClass, RClass or MClass.
95
96 /// ARMArch - ARM architecture
98
99 /// UseMulOps - True if non-microcoded fused integer multiply-add and
100 /// multiply-subtract instructions should be used.
101 bool UseMulOps = false;
102
103 /// SupportsTailCall - True if the OS supports tail call. The dynamic linker
104 /// must be able to synthesize call stubs for interworking between ARM and
105 /// Thumb.
106 bool SupportsTailCall = false;
107
108 /// RestrictIT - If true, the subtarget disallows generation of complex IT
109 /// blocks.
110 bool RestrictIT = false;
111
112 /// UseSjLjEH - If true, the target uses SjLj exception handling (e.g. iOS).
113 bool UseSjLjEH = false;
114
115 /// stackAlignment - The minimum alignment known to hold of the stack frame on
116 /// entry to the function and which must be maintained by every function.
118
119 /// CPUString - String name of used CPU.
120 std::string CPUString;
121
123
124 /// Clearance before partial register updates (in number of instructions)
126
127 /// What kind of timing do load multiple/store multiple have (double issue,
128 /// single issue etc).
130
131 /// The adjustment that we need to apply to get the operand latency from the
132 /// operand cycle returned by the itinerary data for pre-ISel operands.
134
135 /// What alignment is preferred for loop bodies and functions, in log2(bytes).
137
138 /// The cost factor for MVE instructions, representing the multiple beats an
139 // instruction can take. The default is 2, (set in initSubtargetFeatures so
140 // that we can use subtarget features less than 2).
142
143 /// OptMinSize - True if we're optimising for minimum code size, equal to
144 /// the function attribute.
145 bool OptMinSize = false;
146
147 /// IsLittle - The target is Little Endian
149
150 /// TargetTriple - What processor and OS we're targeting.
152
153 /// SchedModel - Processor specific instruction costs.
155
156 /// Selected instruction itineraries (one entry per itinerary class.)
158
159 /// Options passed via command line that could influence the target
161
163
164public:
165 /// This constructor initializes the data members to match that
166 /// of the specified triple.
167 ///
168 ARMSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS,
169 const ARMBaseTargetMachine &TM, bool IsLittle,
170 bool MinSize = false);
171
172 /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
173 /// that still makes it profitable to inline the call.
174 unsigned getMaxInlineSizeThreshold() const {
175 return 64;
176 }
177
178 /// getMaxMemcpyTPInlineSizeThreshold - Returns the maximum size
179 /// that still makes it profitable to inline a llvm.memcpy as a Tail
180 /// Predicated loop.
181 /// This threshold should only be used for constant size inputs.
182 unsigned getMaxMemcpyTPInlineSizeThreshold() const { return 128; }
183
184 /// ParseSubtargetFeatures - Parses features string setting specified
185 /// subtarget options. Definition of function is auto generated by tblgen.
187
188 /// initializeSubtargetDependencies - Initializes using a CPU and feature string
189 /// so that we can use initializer lists for subtarget initialization.
191
192 const ARMSelectionDAGInfo *getSelectionDAGInfo() const override {
193 return &TSInfo;
194 }
195
196 const ARMBaseInstrInfo *getInstrInfo() const override {
197 return InstrInfo.get();
198 }
199
200 const ARMTargetLowering *getTargetLowering() const override {
201 return &TLInfo;
202 }
203
204 const ARMFrameLowering *getFrameLowering() const override {
205 return FrameLowering.get();
206 }
207
208 const ARMBaseRegisterInfo *getRegisterInfo() const override {
209 return &InstrInfo->getRegisterInfo();
210 }
211
212 /// The correct instructions have been implemented to initialize undef
213 /// registers, therefore the ARM Architecture is supported by the Init Undef
214 /// Pass. This will return true as the pass needs to be supported for all
215 /// types of instructions. The pass will then perform more checks to ensure it
216 /// should be applying the Pseudo Instructions.
217 bool supportsInitUndef() const override { return true; }
218
219 const CallLowering *getCallLowering() const override;
221 const LegalizerInfo *getLegalizerInfo() const override;
222 const RegisterBankInfo *getRegBankInfo() const override;
223
224private:
225 ARMSelectionDAGInfo TSInfo;
226 // Either Thumb1FrameLowering or ARMFrameLowering.
227 std::unique_ptr<ARMFrameLowering> FrameLowering;
228 // Either Thumb1InstrInfo or Thumb2InstrInfo.
229 std::unique_ptr<ARMBaseInstrInfo> InstrInfo;
230 ARMTargetLowering TLInfo;
231
232 /// GlobalISel related APIs.
233 std::unique_ptr<CallLowering> CallLoweringInfo;
234 std::unique_ptr<InstructionSelector> InstSelector;
235 std::unique_ptr<LegalizerInfo> Legalizer;
236 std::unique_ptr<RegisterBankInfo> RegBankInfo;
237
238 void initializeEnvironment();
239 void initSubtargetFeatures(StringRef CPU, StringRef FS);
240 ARMFrameLowering *initializeFrameLowering(StringRef CPU, StringRef FS);
241
242 std::bitset<8> CoprocCDE = {};
243public:
244// Getters for SubtargetFeatures defined in tablegen
245#define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \
246 bool GETTER() const { return ATTRIBUTE; }
247#include "ARMGenSubtargetInfo.inc"
248
249 /// @{
250 /// These functions are obsolete, please consider adding subtarget features
251 /// or properties instead of calling them.
252 bool isCortexA5() const { return ARMProcFamily == CortexA5; }
253 bool isCortexA7() const { return ARMProcFamily == CortexA7; }
254 bool isCortexA8() const { return ARMProcFamily == CortexA8; }
255 bool isCortexA9() const { return ARMProcFamily == CortexA9; }
256 bool isCortexA15() const { return ARMProcFamily == CortexA15; }
257 bool isSwift() const { return ARMProcFamily == Swift; }
258 bool isCortexM3() const { return ARMProcFamily == CortexM3; }
259 bool isCortexM7() const { return ARMProcFamily == CortexM7; }
260 bool isLikeA9() const { return isCortexA9() || isCortexA15() || isKrait(); }
261 bool isCortexR5() const { return ARMProcFamily == CortexR5; }
262 bool isKrait() const { return ARMProcFamily == Krait; }
263 /// @}
264
265 bool hasARMOps() const { return !NoARM; }
266
268 return hasNEON() && hasNEONForFP();
269 }
270
271 bool hasVFP2Base() const { return hasVFPv2SP(); }
272 bool hasVFP3Base() const { return hasVFPv3D16SP(); }
273 bool hasVFP4Base() const { return hasVFPv4D16SP(); }
274 bool hasFPARMv8Base() const { return hasFPARMv8D16SP(); }
275
276 bool hasAnyDataBarrier() const {
277 return HasDataBarrier || (hasV6Ops() && !isThumb());
278 }
279
280 bool useMulOps() const { return UseMulOps; }
281 bool useFPVMLx() const { return !SlowFPVMLx; }
282 bool useFPVFMx() const {
283 return !isTargetDarwin() && hasVFP4Base() && !SlowFPVFMx;
284 }
285 bool useFPVFMx16() const { return useFPVFMx() && hasFullFP16(); }
286 bool useFPVFMx64() const { return useFPVFMx() && hasFP64(); }
287 bool useSjLjEH() const { return UseSjLjEH; }
288 bool hasBaseDSP() const {
289 if (isThumb())
290 return hasThumb2() && hasDSP();
291 else
292 return hasV5TEOps();
293 }
294
295 /// Return true if the CPU supports any kind of instruction fusion.
296 bool hasFusion() const { return hasFuseAES() || hasFuseLiterals(); }
297
298 const Triple &getTargetTriple() const { return TargetTriple; }
299
300 bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
301 bool isTargetIOS() const { return TargetTriple.isiOS(); }
302 bool isTargetWatchOS() const { return TargetTriple.isWatchOS(); }
303 bool isTargetWatchABI() const { return TargetTriple.isWatchABI(); }
304 bool isTargetDriverKit() const { return TargetTriple.isDriverKit(); }
305 bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
306 bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
307 bool isTargetNetBSD() const { return TargetTriple.isOSNetBSD(); }
308 bool isTargetWindows() const { return TargetTriple.isOSWindows(); }
309
310 bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
311 bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
313
314 // ARM EABI is the bare-metal EABI described in ARM ABI documents and
315 // can be accessed via -target arm-none-eabi. This is NOT GNUEABI.
316 // FIXME: Add a flag for bare-metal for that target and set Triple::EABI
317 // even for GNUEABI, so we can make a distinction here and still conform to
318 // the EABI on GNU (and Android) mode. This requires change in Clang, too.
319 // FIXME: The Darwin exception is temporary, while we move users to
320 // "*-*-*-macho" triples as quickly as possible.
321 bool isTargetAEABI() const {
325 }
326 bool isTargetGNUAEABI() const {
330 }
331 bool isTargetMuslAEABI() const {
336 }
337
338 // ARM Targets that support EHABI exception handling standard
339 // Darwin uses SjLj. Other targets might need more checks.
342 }
343
344 bool isTargetHardFloat() const;
345
346 bool isReadTPSoft() const {
347 return !(isReadTPTPIDRURW() || isReadTPTPIDRURO() || isReadTPTPIDRPRW());
348 }
349
350 bool isTargetAndroid() const { return TargetTriple.isAndroid(); }
351
352 bool isXRaySupported() const override;
353
354 bool isAPCS_ABI() const;
355 bool isAAPCS_ABI() const;
356 bool isAAPCS16_ABI() const;
357
358 bool isROPI() const;
359 bool isRWPI() const;
360
361 bool useMachineScheduler() const { return UseMISched; }
362 bool useMachinePipeliner() const { return UseMIPipeliner; }
363 bool hasMinSize() const { return OptMinSize; }
364 bool isThumb1Only() const { return isThumb() && !hasThumb2(); }
365 bool isThumb2() const { return isThumb() && hasThumb2(); }
366 bool isMClass() const { return ARMProcClass == MClass; }
367 bool isRClass() const { return ARMProcClass == RClass; }
368 bool isAClass() const { return ARMProcClass == AClass; }
369
370 bool isR9Reserved() const {
371 return isTargetMachO() ? (ReserveR9 || !HasV6Ops) : ReserveR9;
372 }
373
375 if (isTargetDarwin() ||
376 (!isTargetWindows() && isThumb() && !createAAPCSFrameChain()))
377 return ARM::R7;
378 return ARM::R11;
379 }
380
381 /// Returns true if the frame setup is split into two separate pushes (first
382 /// r0-r7,lr then r8-r11), principally so that the frame pointer is adjacent
383 /// to lr. This is always required on Thumb1-only targets, as the push and
384 /// pop instructions can't access the high registers.
385 bool splitFramePushPop(const MachineFunction &MF) const {
387 return true;
388 return (getFramePointerReg() == ARM::R7 &&
390 isThumb1Only();
391 }
392
393 bool splitFramePointerPush(const MachineFunction &MF) const;
394
395 bool useStride4VFPs() const;
396
397 bool useMovt() const;
398
399 bool supportsTailCall() const { return SupportsTailCall; }
400
401 bool allowsUnalignedMem() const { return !StrictAlign; }
402
403 bool restrictIT() const { return RestrictIT; }
404
405 const std::string & getCPUString() const { return CPUString; }
406
407 bool isLittle() const { return IsLittle; }
408
409 unsigned getMispredictionPenalty() const;
410
411 /// Returns true if machine scheduler should be enabled.
412 bool enableMachineScheduler() const override;
413
414 /// Returns true if machine pipeliner should be enabled.
415 bool enableMachinePipeliner() const override;
416 bool useDFAforSMS() const override;
417
418 /// True for some subtargets at > -O0.
419 bool enablePostRAScheduler() const override;
420
421 /// True for some subtargets at > -O0.
422 bool enablePostRAMachineScheduler() const override;
423
424 /// Check whether this subtarget wants to use subregister liveness.
425 bool enableSubRegLiveness() const override;
426
427 /// Enable use of alias analysis during code generation (during MI
428 /// scheduling, DAGCombine, etc.).
429 bool useAA() const override { return true; }
430
431 /// getInstrItins - Return the instruction itineraries based on subtarget
432 /// selection.
434 return &InstrItins;
435 }
436
437 /// getStackAlignment - Returns the minimum alignment known to hold of the
438 /// stack frame on entry to the function and which must be maintained by every
439 /// function for this subtarget.
441
442 // Returns the required alignment for LDRD/STRD instructions
444 return Align(hasV7Ops() || allowsUnalignedMem() ? 4 : 8);
445 }
446
447 unsigned getMaxInterleaveFactor() const { return MaxInterleaveFactor; }
448
450
452 return LdStMultipleTiming;
453 }
454
457 }
458
459 /// True if the GV will be accessed via an indirect symbol.
460 bool isGVIndirectSymbol(const GlobalValue *GV) const;
461
462 /// Returns the constant pool modifier needed to access the GV.
463 bool isGVInGOT(const GlobalValue *GV) const;
464
465 /// True if fast-isel is used.
466 bool useFastISel() const;
467
468 /// Returns the correct return opcode for the current feature set.
469 /// Use BX if available to allow mixing thumb/arm code, but fall back
470 /// to plain mov pc,lr on ARMv4.
471 unsigned getReturnOpcode() const {
472 if (isThumb())
473 return ARM::tBX_RET;
474 if (hasV4TOps())
475 return ARM::BX_RET;
476 return ARM::MOVPCLR;
477 }
478
479 /// Allow movt+movw for PIC global address calculation.
480 /// ELF does not have GOT relocations for movt+movw.
481 /// ROPI does not use GOT.
483 return isROPI() || !isTargetELF();
484 }
485
487
488 unsigned
491 return 1;
492 return MVEVectorCostFactor;
493 }
494
496 unsigned PhysReg) const override;
497 unsigned getGPRAllocationOrder(const MachineFunction &MF) const;
498};
499
500} // end namespace llvm
501
502#endif // LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H
static bool isThumb(const MCSubtargetInfo &STI)
This file describes how to lower LLVM calls to machine code calls.
static cl::opt< TargetTransformInfo::TargetCostKind > CostKind("cost-kind", cl::desc("Target cost kind"), cl::init(TargetTransformInfo::TCK_RecipThroughput), cl::values(clEnumValN(TargetTransformInfo::TCK_RecipThroughput, "throughput", "Reciprocal throughput"), clEnumValN(TargetTransformInfo::TCK_Latency, "latency", "Instruction latency"), clEnumValN(TargetTransformInfo::TCK_CodeSize, "code-size", "Code size"), clEnumValN(TargetTransformInfo::TCK_SizeAndLatency, "size-latency", "Code size and latency")))
Interface for Targets to specify which operations they can successfully select and how the others sho...
This pass exposes codegen information to IR-level passes.
ARMFunctionInfo - This class is derived from MachineFunctionInfo and contains private ARM-specific in...
bool useFastISel() const
True if fast-isel is used.
bool isTargetMachO() const
Definition: ARMSubtarget.h:312
bool hasFusion() const
Return true if the CPU supports any kind of instruction fusion.
Definition: ARMSubtarget.h:296
bool isCortexA7() const
Definition: ARMSubtarget.h:253
bool IsLittle
IsLittle - The target is Little Endian.
Definition: ARMSubtarget.h:148
bool useMovt() const
bool isSwift() const
Definition: ARMSubtarget.h:257
bool isTargetAEABI() const
Definition: ARMSubtarget.h:321
bool enablePostRAScheduler() const override
True for some subtargets at > -O0.
ARMLdStMultipleTiming LdStMultipleTiming
What kind of timing do load multiple/store multiple have (double issue, single issue etc).
Definition: ARMSubtarget.h:129
bool hasARMOps() const
Definition: ARMSubtarget.h:265
bool supportsTailCall() const
Definition: ARMSubtarget.h:399
bool supportsInitUndef() const override
The correct instructions have been implemented to initialize undef registers, therefore the ARM Archi...
Definition: ARMSubtarget.h:217
const Triple & getTargetTriple() const
Definition: ARMSubtarget.h:298
bool UseSjLjEH
UseSjLjEH - If true, the target uses SjLj exception handling (e.g. iOS).
Definition: ARMSubtarget.h:113
bool hasVFP4Base() const
Definition: ARMSubtarget.h:273
unsigned getGPRAllocationOrder(const MachineFunction &MF) const
const RegisterBankInfo * getRegBankInfo() const override
unsigned MaxInterleaveFactor
Definition: ARMSubtarget.h:122
const ARMBaseTargetMachine & TM
Definition: ARMSubtarget.h:162
bool isRClass() const
Definition: ARMSubtarget.h:367
ARMLdStMultipleTiming getLdStMultipleTiming() const
Definition: ARMSubtarget.h:451
const ARMBaseInstrInfo * getInstrInfo() const override
Definition: ARMSubtarget.h:196
bool useFPVMLx() const
Definition: ARMSubtarget.h:281
bool isThumb1Only() const
Definition: ARMSubtarget.h:364
ARMProcFamilyEnum ARMProcFamily
ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.
Definition: ARMSubtarget.h:91
bool useFPVFMx() const
Definition: ARMSubtarget.h:282
ARMArchEnum ARMArch
ARMArch - ARM architecture.
Definition: ARMSubtarget.h:97
bool isCortexM7() const
Definition: ARMSubtarget.h:259
bool hasFPARMv8Base() const
Definition: ARMSubtarget.h:274
bool isAClass() const
Definition: ARMSubtarget.h:368
bool isThumb2() const
Definition: ARMSubtarget.h:365
bool useDFAforSMS() const override
bool isReadTPSoft() const
Definition: ARMSubtarget.h:346
ARMProcClassEnum ARMProcClass
ARMProcClass - ARM processor class: None, AClass, RClass or MClass.
Definition: ARMSubtarget.h:94
bool ignoreCSRForAllocationOrder(const MachineFunction &MF, unsigned PhysReg) const override
bool isAAPCS16_ABI() const
MCPhysReg getFramePointerReg() const
Definition: ARMSubtarget.h:374
bool isTargetWindows() const
Definition: ARMSubtarget.h:308
bool isTargetEHABICompatible() const
Definition: ARMSubtarget.h:340
bool isCortexR5() const
Definition: ARMSubtarget.h:261
bool enableSubRegLiveness() const override
Check whether this subtarget wants to use subregister liveness.
bool isGVIndirectSymbol(const GlobalValue *GV) const
True if the GV will be accessed via an indirect symbol.
unsigned MVEVectorCostFactor
The cost factor for MVE instructions, representing the multiple beats an.
Definition: ARMSubtarget.h:141
bool hasBaseDSP() const
Definition: ARMSubtarget.h:288
const ARMTargetLowering * getTargetLowering() const override
Definition: ARMSubtarget.h:200
bool useSjLjEH() const
Definition: ARMSubtarget.h:287
MCSchedModel SchedModel
SchedModel - Processor specific instruction costs.
Definition: ARMSubtarget.h:154
std::string CPUString
CPUString - String name of used CPU.
Definition: ARMSubtarget.h:120
unsigned getMispredictionPenalty() const
Triple TargetTriple
TargetTriple - What processor and OS we're targeting.
Definition: ARMSubtarget.h:151
bool enableMachineScheduler() const override
Returns true if machine scheduler should be enabled.
bool isLikeA9() const
Definition: ARMSubtarget.h:260
bool isTargetDarwin() const
Definition: ARMSubtarget.h:300
const ARMBaseRegisterInfo * getRegisterInfo() const override
Definition: ARMSubtarget.h:208
InstrItineraryData InstrItins
Selected instruction itineraries (one entry per itinerary class.)
Definition: ARMSubtarget.h:157
bool useStride4VFPs() const
bool OptMinSize
OptMinSize - True if we're optimising for minimum code size, equal to the function attribute.
Definition: ARMSubtarget.h:145
unsigned getReturnOpcode() const
Returns the correct return opcode for the current feature set.
Definition: ARMSubtarget.h:471
bool RestrictIT
RestrictIT - If true, the subtarget disallows generation of complex IT blocks.
Definition: ARMSubtarget.h:110
Align getStackAlignment() const
getStackAlignment - Returns the minimum alignment known to hold of the stack frame on entry to the fu...
Definition: ARMSubtarget.h:440
bool isKrait() const
Definition: ARMSubtarget.h:262
bool isCortexA5() const
Definition: ARMSubtarget.h:252
bool hasVFP2Base() const
Definition: ARMSubtarget.h:271
unsigned PrefLoopLogAlignment
What alignment is preferred for loop bodies and functions, in log2(bytes).
Definition: ARMSubtarget.h:136
bool useAA() const override
Enable use of alias analysis during code generation (during MI scheduling, DAGCombine,...
Definition: ARMSubtarget.h:429
bool isTargetAndroid() const
Definition: ARMSubtarget.h:350
bool isROPI() const
Align stackAlignment
stackAlignment - The minimum alignment known to hold of the stack frame on entry to the function and ...
Definition: ARMSubtarget.h:117
unsigned getMaxMemcpyTPInlineSizeThreshold() const
getMaxMemcpyTPInlineSizeThreshold - Returns the maximum size that still makes it profitable to inline...
Definition: ARMSubtarget.h:182
unsigned PartialUpdateClearance
Clearance before partial register updates (in number of instructions)
Definition: ARMSubtarget.h:125
bool enableMachinePipeliner() const override
Returns true if machine pipeliner should be enabled.
bool enablePostRAMachineScheduler() const override
True for some subtargets at > -O0.
bool isTargetCOFF() const
Definition: ARMSubtarget.h:310
bool splitFramePushPop(const MachineFunction &MF) const
Returns true if the frame setup is split into two separate pushes (first r0-r7,lr then r8-r11),...
Definition: ARMSubtarget.h:385
unsigned getMaxInlineSizeThreshold() const
getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size that still makes it profitable t...
Definition: ARMSubtarget.h:174
bool isTargetGNUAEABI() const
Definition: ARMSubtarget.h:326
const ARMSelectionDAGInfo * getSelectionDAGInfo() const override
Definition: ARMSubtarget.h:192
const std::string & getCPUString() const
Definition: ARMSubtarget.h:405
InstructionSelector * getInstructionSelector() const override
unsigned getMaxInterleaveFactor() const
Definition: ARMSubtarget.h:447
bool hasVFP3Base() const
Definition: ARMSubtarget.h:272
bool isR9Reserved() const
Definition: ARMSubtarget.h:370
bool isAPCS_ABI() const
bool useFPVFMx64() const
Definition: ARMSubtarget.h:286
unsigned getPartialUpdateClearance() const
Definition: ARMSubtarget.h:449
bool isTargetNetBSD() const
Definition: ARMSubtarget.h:307
bool isTargetWatchOS() const
Definition: ARMSubtarget.h:302
bool isXRaySupported() const override
const CallLowering * getCallLowering() const override
bool hasMinSize() const
Definition: ARMSubtarget.h:363
bool splitFramePointerPush(const MachineFunction &MF) const
ARMSubtarget & initializeSubtargetDependencies(StringRef CPU, StringRef FS)
initializeSubtargetDependencies - Initializes using a CPU and feature string so that we can use initi...
bool isTargetIOS() const
Definition: ARMSubtarget.h:301
bool isGVInGOT(const GlobalValue *GV) const
Returns the constant pool modifier needed to access the GV.
bool useNEONForSinglePrecisionFP() const
Definition: ARMSubtarget.h:267
bool isTargetNaCl() const
Definition: ARMSubtarget.h:306
const InstrItineraryData * getInstrItineraryData() const override
getInstrItins - Return the instruction itineraries based on subtarget selection.
Definition: ARMSubtarget.h:433
bool isCortexM3() const
Definition: ARMSubtarget.h:258
bool isTargetWatchABI() const
Definition: ARMSubtarget.h:303
bool allowPositionIndependentMovt() const
Allow movt+movw for PIC global address calculation.
Definition: ARMSubtarget.h:482
bool isCortexA8() const
Definition: ARMSubtarget.h:254
bool UseMulOps
UseMulOps - True if non-microcoded fused integer multiply-add and multiply-subtract instructions shou...
Definition: ARMSubtarget.h:101
const TargetOptions & Options
Options passed via command line that could influence the target.
Definition: ARMSubtarget.h:160
ARMLdStMultipleTiming
What kind of timing do load multiple/store multiple instructions have.
Definition: ARMSubtarget.h:71
@ DoubleIssueCheckUnalignedAccess
Can load/store 2 registers/cycle, but needs an extra cycle if the access is not 64-bit aligned.
Definition: ARMSubtarget.h:76
@ SingleIssue
Can load/store 1 register/cycle.
Definition: ARMSubtarget.h:78
@ DoubleIssue
Can load/store 2 registers/cycle.
Definition: ARMSubtarget.h:73
@ SingleIssuePlusExtras
Can load/store 1 register/cycle, but needs an extra cycle for address computation and potentially als...
Definition: ARMSubtarget.h:81
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
bool hasAnyDataBarrier() const
Definition: ARMSubtarget.h:276
bool useMachinePipeliner() const
Definition: ARMSubtarget.h:362
bool isTargetDriverKit() const
Definition: ARMSubtarget.h:304
int getPreISelOperandLatencyAdjustment() const
Definition: ARMSubtarget.h:455
bool isAAPCS_ABI() const
bool useMachineScheduler() const
Definition: ARMSubtarget.h:361
bool isCortexA15() const
Definition: ARMSubtarget.h:256
bool isRWPI() const
bool isLittle() const
Definition: ARMSubtarget.h:407
bool allowsUnalignedMem() const
Definition: ARMSubtarget.h:401
bool isTargetMuslAEABI() const
Definition: ARMSubtarget.h:331
const LegalizerInfo * getLegalizerInfo() const override
bool isTargetLinux() const
Definition: ARMSubtarget.h:305
bool isCortexA9() const
Definition: ARMSubtarget.h:255
bool useFPVFMx16() const
Definition: ARMSubtarget.h:285
bool isMClass() const
Definition: ARMSubtarget.h:366
bool SupportsTailCall
SupportsTailCall - True if the OS supports tail call.
Definition: ARMSubtarget.h:106
unsigned getPrefLoopLogAlignment() const
Definition: ARMSubtarget.h:486
int PreISelOperandLatencyAdjustment
The adjustment that we need to apply to get the operand latency from the operand cycle returned by th...
Definition: ARMSubtarget.h:133
bool isTargetHardFloat() const
bool useMulOps() const
Definition: ARMSubtarget.h:280
bool isTargetELF() const
Definition: ARMSubtarget.h:311
bool restrictIT() const
Definition: ARMSubtarget.h:403
unsigned getMVEVectorCostFactor(TargetTransformInfo::TargetCostKind CostKind) const
Definition: ARMSubtarget.h:489
const ARMFrameLowering * getFrameLowering() const override
Definition: ARMSubtarget.h:204
Align getDualLoadStoreAlignment() const
Definition: ARMSubtarget.h:443
Itinerary data supplied by a subtarget to be used by a target.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Holds all the information related to register banks.
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
TargetOptions Options
bool DisableFramePointerElim(const MachineFunction &MF) const
DisableFramePointerElim - This returns true if frame pointer elimination optimization should be disab...
TargetCostKind
The kind of cost model.
@ TCK_CodeSize
Instruction code size.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
bool isOSNaCl() const
Tests whether the OS is NaCl (Native Client)
Definition: Triple.h:671
bool isWatchABI() const
Definition: Triple.h:543
@ MuslEABIHF
Definition: Triple.h:261
bool isDriverKit() const
Is this an Apple DriverKit triple.
Definition: Triple.h:551
bool isTargetEHABICompatible() const
Tests whether the target supports the EHABI exception handling standard.
Definition: Triple.h:861
bool isOSNetBSD() const
Definition: Triple.h:574
bool isAndroid() const
Tests whether the target is Android.
Definition: Triple.h:767
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
Definition: Triple.h:730
bool isOSBinFormatCOFF() const
Tests whether the OS uses the COFF binary format.
Definition: Triple.h:722
EnvironmentType getEnvironment() const
Get the parsed environment type of this triple.
Definition: Triple.h:388
bool isOSWindows() const
Tests whether the OS is Windows.
Definition: Triple.h:622
bool isOSLinux() const
Tests whether the OS is Linux.
Definition: Triple.h:676
bool isOSDarwin() const
Is this a "Darwin" OS (macOS, iOS, tvOS, watchOS, XROS, or DriverKit).
Definition: Triple.h:556
bool isWatchOS() const
Is this an Apple watchOS triple.
Definition: Triple.h:539
bool isiOS() const
Is this an iOS triple.
Definition: Triple.h:529
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:717
@ Swift
Calling convention for Swift.
Definition: CallingConv.h:69
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
Machine model for scheduling, bundling, and heuristics.
Definition: MCSchedule.h:253