LLVM  14.0.0git
ARMSelectionDAGInfo.h
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1 //===-- ARMSelectionDAGInfo.h - ARM SelectionDAG Info -----------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the ARM subclass for SelectionDAGTargetInfo.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_ARM_ARMSELECTIONDAGINFO_H
14 #define LLVM_LIB_TARGET_ARM_ARMSELECTIONDAGINFO_H
15 
19 
20 namespace llvm {
21 
22 namespace ARM_AM {
23  static inline ShiftOpc getShiftOpcForNode(unsigned Opcode) {
24  switch (Opcode) {
25  default: return ARM_AM::no_shift;
26  case ISD::SHL: return ARM_AM::lsl;
27  case ISD::SRL: return ARM_AM::lsr;
28  case ISD::SRA: return ARM_AM::asr;
29  case ISD::ROTR: return ARM_AM::ror;
30  //case ISD::ROTL: // Only if imm -> turn into ROTR.
31  // Can't handle RRX here, because it would require folding a flag into
32  // the addressing mode. :( This causes us to miss certain things.
33  //case ARMISD::RRX: return ARM_AM::rrx;
34  }
35  }
36 } // end namespace ARM_AM
37 
39 public:
41  SDValue Chain, SDValue Dst, SDValue Src,
42  SDValue Size, Align Alignment,
43  bool isVolatile, bool AlwaysInline,
44  MachinePointerInfo DstPtrInfo,
45  MachinePointerInfo SrcPtrInfo) const override;
46 
47  SDValue
48  EmitTargetCodeForMemmove(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain,
49  SDValue Dst, SDValue Src, SDValue Size,
50  Align Alignment, bool isVolatile,
51  MachinePointerInfo DstPtrInfo,
52  MachinePointerInfo SrcPtrInfo) const override;
53 
54  // Adjust parameters for memset, see RTABI section 4.3.4
56  SDValue Chain, SDValue Op1, SDValue Op2,
57  SDValue Op3, Align Alignment, bool isVolatile,
58  MachinePointerInfo DstPtrInfo) const override;
59 
61  SDValue Chain, SDValue Dst, SDValue Src,
62  SDValue Size, unsigned Align,
63  RTLIB::Libcall LC) const;
64 };
65 
66 }
67 
68 #endif
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
llvm::ARM_AM::ror
@ ror
Definition: ARMAddressingModes.h:32
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
llvm::ARM_AM::lsr
@ lsr
Definition: ARMAddressingModes.h:31
llvm::SDLoc
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Definition: SelectionDAGNodes.h:1086
llvm::ARM_AM::getShiftOpcForNode
static ShiftOpc getShiftOpcForNode(unsigned Opcode)
Definition: ARMSelectionDAGInfo.h:23
llvm::ARMSelectionDAGInfo::EmitSpecializedLibcall
SDValue EmitSpecializedLibcall(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, RTLIB::Libcall LC) const
Definition: ARMSelectionDAGInfo.cpp:38
llvm::RTLIB::Libcall
Libcall
RTLIB::Libcall enum - This enum defines all of the runtime library calls the backend can emit.
Definition: RuntimeLibcalls.h:30
llvm::ARM_AM::ShiftOpc
ShiftOpc
Definition: ARMAddressingModes.h:27
llvm::ARMSelectionDAGInfo::EmitTargetCodeForMemcpy
SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVolatile, bool AlwaysInline, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const override
Emit target-specific code that performs a memcpy.
Definition: ARMSelectionDAGInfo.cpp:169
llvm::SelectionDAG
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:216
llvm::ARMSelectionDAGInfo::EmitTargetCodeForMemset
SDValue EmitTargetCodeForMemset(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Op1, SDValue Op2, SDValue Op3, Align Alignment, bool isVolatile, MachinePointerInfo DstPtrInfo) const override
Emit target-specific code that performs a memset.
Definition: ARMSelectionDAGInfo.cpp:297
llvm::ARMSelectionDAGInfo::EmitTargetCodeForMemmove
SDValue EmitTargetCodeForMemmove(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVolatile, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const override
Emit target-specific code that performs a memmove.
Definition: ARMSelectionDAGInfo.cpp:289
llvm::ARM_AM::no_shift
@ no_shift
Definition: ARMAddressingModes.h:28
llvm::ISD::SRA
@ SRA
Definition: ISDOpcodes.h:658
llvm::SelectionDAGTargetInfo
Targets can subclass this to parameterize the SelectionDAG lowering and instruction selection process...
Definition: SelectionDAGTargetInfo.h:31
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
RuntimeLibcalls.h
llvm::MachinePointerInfo
This class contains a discriminated union of information about pointers in memory operands,...
Definition: MachineMemOperand.h:38
ARMAddressingModes.h
llvm::ARMSelectionDAGInfo
Definition: ARMSelectionDAGInfo.h:38
llvm::SDValue
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
Definition: SelectionDAGNodes.h:138
SelectionDAGTargetInfo.h
llvm::ISD::SHL
@ SHL
Shift and rotation operations.
Definition: ISDOpcodes.h:657
llvm::ISD::SRL
@ SRL
Definition: ISDOpcodes.h:659
llvm::ISD::ROTR
@ ROTR
Definition: ISDOpcodes.h:661
llvm::ARM_AM::lsl
@ lsl
Definition: ARMAddressingModes.h:30
llvm::ARM_AM::asr
@ asr
Definition: ARMAddressingModes.h:29