Go to the documentation of this file.
15 #ifndef LLVM_CODEGEN_MACHINEMEMOPERAND_H
16 #define LLVM_CODEGEN_MACHINEMEMOPERAND_H
29 class FoldingSetNodeID;
32 class MachineFunction;
33 class ModuleSlotTracker;
34 class TargetInstrInfo;
73 AddrSpace = ValPtr->getType()->getPointerAddressSpace();
159 struct MachineAtomicInfo {
164 unsigned Ordering : 4;
167 unsigned FailureOrdering : 4;
170 MachinePointerInfo PtrInfo;
178 MachineAtomicInfo AtomicInfo;
180 const MDNode *Ranges;
189 Align a,
const AAMDNodes &AAInfo = AAMDNodes(),
190 const MDNode *Ranges =
nullptr,
195 const AAMDNodes &AAInfo = AAMDNodes(),
196 const MDNode *Ranges =
nullptr,
236 return MemoryType.isValid() ? MemoryType.getSizeInBytes() : ~UINT64_C(0);
241 return MemoryType.isValid() ? MemoryType.getSizeInBits() : ~UINT64_C(0);
319 void setOffset(int64_t NewOffset) { PtrInfo.Offset = NewOffset; }
339 return LHS.getValue() ==
RHS.getValue() &&
340 LHS.getPseudoValue() ==
RHS.getPseudoValue() &&
341 LHS.getSize() ==
RHS.getSize() &&
342 LHS.getOffset() ==
RHS.getOffset() &&
343 LHS.getFlags() ==
RHS.getFlags() &&
344 LHS.getAAInfo() ==
RHS.getAAInfo() &&
345 LHS.getRanges() ==
RHS.getRanges() &&
346 LHS.getAlign() ==
RHS.getAlign() &&
347 LHS.getAddrSpace() ==
RHS.getAddrSpace();
void setValue(const Value *NewSV)
Change the SourceValue for this MachineMemOperand.
MachineMemOperand(MachinePointerInfo PtrInfo, Flags flags, uint64_t s, Align a, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
Construct a MachineMemOperand object with the specified PtrInfo, flags, size, and base alignment.
bool isNull() const
Test if the pointer held in the union is null, regardless of which type it is.
This is an optimization pass for GlobalISel generic memory operations.
A parsed version of the target data layout string in and methods for querying it.
Align getAlign() const
Return the minimum known alignment in bytes of the actual memory reference.
#define LLVM_MARK_AS_BITMASK_ENUM(LargestValue)
LLVM_MARK_AS_BITMASK_ENUM lets you opt in an individual enum type so you can perform bitwise operatio...
void print(raw_ostream &OS, ModuleSlotTracker &MST, SmallVectorImpl< StringRef > &SSNs, const LLVMContext &Context, const MachineFrameInfo *MFI, const TargetInstrInfo *TII) const
Support for operator<<.
AtomicOrdering getMergedAtomicOrdering(AtomicOrdering AO, AtomicOrdering Other)
Return a single atomic ordering that is at least as strong as both the AO and Other orderings for an ...
static MachinePointerInfo getConstantPool(MachineFunction &MF)
Return a MachinePointerInfo record that refers to the constant pool.
static MachinePointerInfo getUnknownStack(MachineFunction &MF)
Stack memory without other information.
int64_t getOffset() const
For normal values, this is a byte offset added to the base address.
unsigned getPointerAddressSpace() const
Get the address space of this pointer or pointer vector type.
@ MOInvariant
The memory access always returns the same value (or traps).
MachinePointerInfo(const PseudoSourceValue *v, int64_t offset=0, uint8_t ID=0)
uint64_t getSizeInBits() const
Return the size in bits of the memory reference.
A collection of metadata nodes that might be associated with a memory access used by the alias-analys...
const void * getOpaqueValue() const
A description of a memory reference used in the backend.
@ MODereferenceable
The memory access is dereferenceable (i.e., doesn't trap).
AAMDNodes getAAInfo() const
Return the AA tags for the memory reference.
bool isUnordered() const
Returns true if this memory operation doesn't have any ordering constraints other than normal aliasin...
Manage lifetime of a slot tracker for printing IR.
T get() const
Returns the value of the specified pointer type.
static MachinePointerInfo getJumpTable(MachineFunction &MF)
Return a MachinePointerInfo record that refers to a jump table entry.
bool is() const
Test if the Union currently holds the type matching T.
=0.0 ? 0.0 :(a > 0.0 ? 1.0 :-1.0) a
int64_t Offset
Offset - This is an offset from the base Value*.
AddressSpace getAddressSpace(T *V)
const MachinePointerInfo & getPointerInfo() const
TargetInstrInfo - Interface to description of machine instruction set.
Align getBaseAlign() const
Return the minimum known alignment in bytes of the base address, without the offset.
Itanium Name Demangler i e convert the string _Z1fv into f()". You can also use the CRTP base ManglingParser to perform some simple analysis on the mangled name
unsigned getAddrSpace() const
const Value * getValue() const
Return the base address of the memory access.
(vector float) vec_cmpeq(*A, *B) C
static MachinePointerInfo getGOT(MachineFunction &MF)
Return a MachinePointerInfo record that refers to a GOT entry.
const HexagonInstrInfo * TII
This class implements an extremely fast bulk output stream that can only output to a stream.
@ System
Synchronized with respect to all concurrently executing threads.
Special value supplied for machine level alias analysis.
This struct is a compact representation of a valid (non-zero power of two) alignment.
MachinePointerInfo(const Value *v, int64_t offset=0, uint8_t ID=0)
SyncScope::ID getSyncScopeID() const
Returns the synchronization scope ID for this memory operation.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
void setFlags(Flags f)
Bitwise OR the current flags with the given flags.
void Profile(FoldingSetNodeID &ID) const
Profile - Gather unique data for the object.
MachinePointerInfo(unsigned AddressSpace=0, int64_t offset=0)
AtomicOrdering
Atomic ordering for LLVM's memory model.
AMD64 Optimization Manual has some nice information about optimizing integer multiplication by a constant How much of it applies to Intel s X86 implementation There are definite trade offs to xmm0 cvttss2siq rdx jb L3 subss xmm0 rax cvttss2siq rdx xorq rdx rax ret instead of xmm1 cvttss2siq rcx movaps xmm2 subss xmm2 cvttss2siq rax rdx xorq rax ucomiss xmm0 cmovb rax ret Seems like the jb branch has high likelihood of being taken It would have saved a few instructions It s not possible to reference and DH registers in an instruction requiring REX prefix divb and mulb both produce results in AH If isel emits a CopyFromReg which gets turned into a movb and that can be allocated a r8b r15b To get around isel emits a CopyFromReg from AX and then right shift it down by and truncate it It s not pretty but it works We need some register allocation magic to make the hack go which would often require a callee saved register Callees usually need to keep this value live for most of their body so it doesn t add a significant burden on them We currently implement this in however this is suboptimal because it means that it would be quite awkward to implement the optimization for callers A better implementation would be to relax the LLVM IR rules for sret arguments to allow a function with an sret argument to have a non void return type
bool isDereferenceable(unsigned Size, LLVMContext &C, const DataLayout &DL) const
Return true if memory region [V, V+Offset+Size) is known to be dereferenceable.
bool isDereferenceable() const
multiplies can be turned into SHL s
T dyn_cast() const
Returns the current pointer if it is of the specified pointer type, otherwise returns null.
This class contains a discriminated union of information about pointers in memory operands,...
This is an important class for using LLVM in a threaded context.
void setOffset(int64_t NewOffset)
Flags
Flags values. These may be or'd together.
unsigned getAddressSpace() const
AtomicOrdering getSuccessOrdering() const
Return the atomic ordering requirements for this memory operation.
@ MONonTemporal
The memory access is non-temporal.
LLT getMemoryType() const
Return the memory type of the memory reference.
MachinePointerInfo getWithOffset(int64_t O) const
PointerUnion< const Value *, const PseudoSourceValue * > V
This is the IR pointer value for the access, or it is null if unknown.
Type * getType() const
All values are typed, get the type of this value.
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
FoldingSetNodeID - This class is used to gather all the unique data bits of a node.
@ MOVolatile
The memory access is volatile.
unsigned getAddrSpace() const
Return the LLVM IR address space number that this pointer points into.
@ MOLoad
The memory access reads data.
uint64_t getSize() const
Return the size in bytes of the memory reference.
friend bool operator==(const MachineMemOperand &LHS, const MachineMemOperand &RHS)
bool isAtomic() const
Returns true if this operation has an atomic ordering requirement of unordered or higher,...
AtomicOrdering getMergedOrdering() const
Return a single atomic ordering that is at least as strong as both the success and failure orderings ...
void refineAlignment(const MachineMemOperand *MMO)
Update this MachineMemOperand to reflect the alignment of MMO, if it has a greater alignment.
@ MOStore
The memory access writes data.
void setValue(const PseudoSourceValue *NewSV)
friend bool operator!=(const MachineMemOperand &LHS, const MachineMemOperand &RHS)
void setType(LLT NewTy)
Reset the tracked memory type.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
AtomicOrdering getFailureOrdering() const
For cmpxchg atomic operations, return the atomic ordering requirements when store does not occur.
bool isNonTemporal() const
const MDNode * getRanges() const
Return the range tag for the memory reference.
static MachinePointerInfo getStack(MachineFunction &MF, int64_t Offset, uint8_t ID=0)
Stack pointer relative access.
MachinePointerInfo(PointerUnion< const Value *, const PseudoSourceValue * > v, int64_t offset=0, uint8_t ID=0)
LLVM Value Representation.
Flags getFlags() const
Return the raw flags of the source value,.
const PseudoSourceValue * getPseudoValue() const