LLVM  14.0.0git
MachineMemOperand.h
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1 //==- llvm/CodeGen/MachineMemOperand.h - MachineMemOperand class -*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the declaration of the MachineMemOperand class, which is a
10 // description of a memory reference. It is used to help track dependencies
11 // in the backend.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_CODEGEN_MACHINEMEMOPERAND_H
16 #define LLVM_CODEGEN_MACHINEMEMOPERAND_H
17 
18 #include "llvm/ADT/BitmaskEnum.h"
19 #include "llvm/ADT/PointerUnion.h"
21 #include "llvm/IR/DerivedTypes.h"
22 #include "llvm/IR/Value.h" // PointerLikeTypeTraits<Value*>
24 #include "llvm/Support/DataTypes.h"
26 
27 namespace llvm {
28 
29 class FoldingSetNodeID;
30 class MDNode;
31 class raw_ostream;
32 class MachineFunction;
33 class ModuleSlotTracker;
34 
35 /// This class contains a discriminated union of information about pointers in
36 /// memory operands, relating them back to LLVM IR or to virtual locations (such
37 /// as frame indices) that are exposed during codegen.
39  /// This is the IR pointer value for the access, or it is null if unknown.
40  /// If this is null, then the access is to a pointer in the default address
41  /// space.
43 
44  /// Offset - This is an offset from the base Value*.
45  int64_t Offset;
46 
47  unsigned AddrSpace = 0;
48 
49  uint8_t StackID;
50 
51  explicit MachinePointerInfo(const Value *v, int64_t offset = 0,
52  uint8_t ID = 0)
53  : V(v), Offset(offset), StackID(ID) {
54  AddrSpace = v ? v->getType()->getPointerAddressSpace() : 0;
55  }
56 
57  explicit MachinePointerInfo(const PseudoSourceValue *v, int64_t offset = 0,
58  uint8_t ID = 0)
59  : V(v), Offset(offset), StackID(ID) {
60  AddrSpace = v ? v->getAddressSpace() : 0;
61  }
62 
63  explicit MachinePointerInfo(unsigned AddressSpace = 0, int64_t offset = 0)
64  : V((const Value *)nullptr), Offset(offset), AddrSpace(AddressSpace),
65  StackID(0) {}
66 
69  int64_t offset = 0,
70  uint8_t ID = 0)
71  : V(v), Offset(offset), StackID(ID) {
72  if (V) {
73  if (const auto *ValPtr = V.dyn_cast<const Value*>())
74  AddrSpace = ValPtr->getType()->getPointerAddressSpace();
75  else
76  AddrSpace = V.get<const PseudoSourceValue*>()->getAddressSpace();
77  }
78  }
79 
81  if (V.isNull())
83  if (V.is<const Value*>())
84  return MachinePointerInfo(V.get<const Value*>(), Offset + O, StackID);
85  return MachinePointerInfo(V.get<const PseudoSourceValue*>(), Offset + O,
86  StackID);
87  }
88 
89  /// Return true if memory region [V, V+Offset+Size) is known to be
90  /// dereferenceable.
91  bool isDereferenceable(unsigned Size, LLVMContext &C,
92  const DataLayout &DL) const;
93 
94  /// Return the LLVM IR address space number that this pointer points into.
95  unsigned getAddrSpace() const;
96 
97  /// Return a MachinePointerInfo record that refers to the constant pool.
99 
100  /// Return a MachinePointerInfo record that refers to the specified
101  /// FrameIndex.
103  int64_t Offset = 0);
104 
105  /// Return a MachinePointerInfo record that refers to a jump table entry.
107 
108  /// Return a MachinePointerInfo record that refers to a GOT entry.
110 
111  /// Stack pointer relative access.
113  uint8_t ID = 0);
114 
115  /// Stack memory without other information.
117 };
118 
119 
120 //===----------------------------------------------------------------------===//
121 /// A description of a memory reference used in the backend.
122 /// Instead of holding a StoreInst or LoadInst, this class holds the address
123 /// Value of the reference along with a byte size and offset. This allows it
124 /// to describe lowered loads and stores. Also, the special PseudoSourceValue
125 /// objects can be used to represent loads and stores to memory locations
126 /// that aren't explicit in the regular LLVM IR.
127 ///
129 public:
130  /// Flags values. These may be or'd together.
131  enum Flags : uint16_t {
132  // No flags set.
133  MONone = 0,
134  /// The memory access reads data.
135  MOLoad = 1u << 0,
136  /// The memory access writes data.
137  MOStore = 1u << 1,
138  /// The memory access is volatile.
139  MOVolatile = 1u << 2,
140  /// The memory access is non-temporal.
141  MONonTemporal = 1u << 3,
142  /// The memory access is dereferenceable (i.e., doesn't trap).
143  MODereferenceable = 1u << 4,
144  /// The memory access always returns the same value (or traps).
145  MOInvariant = 1u << 5,
146 
147  // Reserved for use by target-specific passes.
148  // Targets may override getSerializableMachineMemOperandTargetFlags() to
149  // enable MIR serialization/parsing of these flags. If more of these flags
150  // are added, the MIR printing/parsing code will need to be updated as well.
151  MOTargetFlag1 = 1u << 6,
152  MOTargetFlag2 = 1u << 7,
153  MOTargetFlag3 = 1u << 8,
154 
155  LLVM_MARK_AS_BITMASK_ENUM(/* LargestFlag = */ MOTargetFlag3)
156  };
157 
158 private:
159  /// Atomic information for this memory operation.
160  struct MachineAtomicInfo {
161  /// Synchronization scope ID for this memory operation.
162  unsigned SSID : 8; // SyncScope::ID
163  /// Atomic ordering requirements for this memory operation. For cmpxchg
164  /// atomic operations, atomic ordering requirements when store occurs.
165  unsigned Ordering : 4; // enum AtomicOrdering
166  /// For cmpxchg atomic operations, atomic ordering requirements when store
167  /// does not occur.
168  unsigned FailureOrdering : 4; // enum AtomicOrdering
169  };
170 
171  MachinePointerInfo PtrInfo;
172 
173  /// Track the memory type of the access. An access size which is unknown or
174  /// too large to be represented by LLT should use the invalid LLT.
175  LLT MemoryType;
176 
177  Flags FlagVals;
178  Align BaseAlign;
179  MachineAtomicInfo AtomicInfo;
180  AAMDNodes AAInfo;
181  const MDNode *Ranges;
182 
183 public:
184  /// Construct a MachineMemOperand object with the specified PtrInfo, flags,
185  /// size, and base alignment. For atomic operations the synchronization scope
186  /// and atomic ordering requirements must also be specified. For cmpxchg
187  /// atomic operations the atomic ordering requirements when store does not
188  /// occur must also be specified.
189  MachineMemOperand(MachinePointerInfo PtrInfo, Flags flags, uint64_t s,
190  Align a, const AAMDNodes &AAInfo = AAMDNodes(),
191  const MDNode *Ranges = nullptr,
194  AtomicOrdering FailureOrdering = AtomicOrdering::NotAtomic);
195  MachineMemOperand(MachinePointerInfo PtrInfo, Flags flags, LLT type, Align a,
196  const AAMDNodes &AAInfo = AAMDNodes(),
197  const MDNode *Ranges = nullptr,
200  AtomicOrdering FailureOrdering = AtomicOrdering::NotAtomic);
201 
202  const MachinePointerInfo &getPointerInfo() const { return PtrInfo; }
203 
204  /// Return the base address of the memory access. This may either be a normal
205  /// LLVM IR Value, or one of the special values used in CodeGen.
206  /// Special values are those obtained via
207  /// PseudoSourceValue::getFixedStack(int), PseudoSourceValue::getStack, and
208  /// other PseudoSourceValue member functions which return objects which stand
209  /// for frame/stack pointer relative references and other special references
210  /// which are not representable in the high-level IR.
211  const Value *getValue() const { return PtrInfo.V.dyn_cast<const Value*>(); }
212 
214  return PtrInfo.V.dyn_cast<const PseudoSourceValue*>();
215  }
216 
217  const void *getOpaqueValue() const { return PtrInfo.V.getOpaqueValue(); }
218 
219  /// Return the raw flags of the source value, \see Flags.
220  Flags getFlags() const { return FlagVals; }
221 
222  /// Bitwise OR the current flags with the given flags.
223  void setFlags(Flags f) { FlagVals |= f; }
224 
225  /// For normal values, this is a byte offset added to the base address.
226  /// For PseudoSourceValue::FPRel values, this is the FrameIndex number.
227  int64_t getOffset() const { return PtrInfo.Offset; }
228 
229  unsigned getAddrSpace() const { return PtrInfo.getAddrSpace(); }
230 
231  /// Return the memory type of the memory reference. This should only be relied
232  /// on for GlobalISel G_* operation legalization.
233  LLT getMemoryType() const { return MemoryType; }
234 
235  /// Return the size in bytes of the memory reference.
236  uint64_t getSize() const {
237  return MemoryType.isValid() ? MemoryType.getSizeInBytes() : ~UINT64_C(0);
238  }
239 
240  /// Return the size in bits of the memory reference.
241  uint64_t getSizeInBits() const {
242  return MemoryType.isValid() ? MemoryType.getSizeInBits() : ~UINT64_C(0);
243  }
244 
245  LLT getType() const {
246  return MemoryType;
247  }
248 
249  /// Return the minimum known alignment in bytes of the actual memory
250  /// reference.
251  Align getAlign() const;
252 
253  /// Return the minimum known alignment in bytes of the base address, without
254  /// the offset.
255  Align getBaseAlign() const { return BaseAlign; }
256 
257  /// Return the AA tags for the memory reference.
258  AAMDNodes getAAInfo() const { return AAInfo; }
259 
260  /// Return the range tag for the memory reference.
261  const MDNode *getRanges() const { return Ranges; }
262 
263  /// Returns the synchronization scope ID for this memory operation.
265  return static_cast<SyncScope::ID>(AtomicInfo.SSID);
266  }
267 
268  /// Return the atomic ordering requirements for this memory operation. For
269  /// cmpxchg atomic operations, return the atomic ordering requirements when
270  /// store occurs.
272  return static_cast<AtomicOrdering>(AtomicInfo.Ordering);
273  }
274 
275  /// For cmpxchg atomic operations, return the atomic ordering requirements
276  /// when store does not occur.
278  return static_cast<AtomicOrdering>(AtomicInfo.FailureOrdering);
279  }
280 
281  /// Return a single atomic ordering that is at least as strong as both the
282  /// success and failure orderings for an atomic operation. (For operations
283  /// other than cmpxchg, this is equivalent to getSuccessOrdering().)
285  AtomicOrdering Ordering = getSuccessOrdering();
286  AtomicOrdering FailureOrdering = getFailureOrdering();
287  if (FailureOrdering == AtomicOrdering::SequentiallyConsistent)
289  if (FailureOrdering == AtomicOrdering::Acquire) {
290  if (Ordering == AtomicOrdering::Monotonic)
292  if (Ordering == AtomicOrdering::Release)
294  }
295  return Ordering;
296  }
297 
298  bool isLoad() const { return FlagVals & MOLoad; }
299  bool isStore() const { return FlagVals & MOStore; }
300  bool isVolatile() const { return FlagVals & MOVolatile; }
301  bool isNonTemporal() const { return FlagVals & MONonTemporal; }
302  bool isDereferenceable() const { return FlagVals & MODereferenceable; }
303  bool isInvariant() const { return FlagVals & MOInvariant; }
304 
305  /// Returns true if this operation has an atomic ordering requirement of
306  /// unordered or higher, false otherwise.
307  bool isAtomic() const {
309  }
310 
311  /// Returns true if this memory operation doesn't have any ordering
312  /// constraints other than normal aliasing. Volatile and (ordered) atomic
313  /// memory operations can't be reordered.
314  bool isUnordered() const {
317  !isVolatile();
318  }
319 
320  /// Update this MachineMemOperand to reflect the alignment of MMO, if it has a
321  /// greater alignment. This must only be used when the new alignment applies
322  /// to all users of this MachineMemOperand.
323  void refineAlignment(const MachineMemOperand *MMO);
324 
325  /// Change the SourceValue for this MachineMemOperand. This should only be
326  /// used when an object is being relocated and all references to it are being
327  /// updated.
328  void setValue(const Value *NewSV) { PtrInfo.V = NewSV; }
329  void setValue(const PseudoSourceValue *NewSV) { PtrInfo.V = NewSV; }
330  void setOffset(int64_t NewOffset) { PtrInfo.Offset = NewOffset; }
331 
332  /// Reset the tracked memory type.
333  void setType(LLT NewTy) {
334  MemoryType = NewTy;
335  }
336 
337  /// Profile - Gather unique data for the object.
338  ///
339  void Profile(FoldingSetNodeID &ID) const;
340 
341  /// Support for operator<<.
342  /// @{
343  void print(raw_ostream &OS, ModuleSlotTracker &MST,
345  const MachineFrameInfo *MFI, const TargetInstrInfo *TII) const;
346  /// @}
347 
348  friend bool operator==(const MachineMemOperand &LHS,
349  const MachineMemOperand &RHS) {
350  return LHS.getValue() == RHS.getValue() &&
351  LHS.getPseudoValue() == RHS.getPseudoValue() &&
352  LHS.getSize() == RHS.getSize() &&
353  LHS.getOffset() == RHS.getOffset() &&
354  LHS.getFlags() == RHS.getFlags() &&
355  LHS.getAAInfo() == RHS.getAAInfo() &&
356  LHS.getRanges() == RHS.getRanges() &&
357  LHS.getAlign() == RHS.getAlign() &&
358  LHS.getAddrSpace() == RHS.getAddrSpace();
359  }
360 
361  friend bool operator!=(const MachineMemOperand &LHS,
362  const MachineMemOperand &RHS) {
363  return !(LHS == RHS);
364  }
365 };
366 
367 } // End llvm namespace
368 
369 #endif
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
llvm::MachineMemOperand::setValue
void setValue(const Value *NewSV)
Change the SourceValue for this MachineMemOperand.
Definition: MachineMemOperand.h:328
llvm::MachineMemOperand::MachineMemOperand
MachineMemOperand(MachinePointerInfo PtrInfo, Flags flags, uint64_t s, Align a, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
Construct a MachineMemOperand object with the specified PtrInfo, flags, size, and base alignment.
Definition: MachineOperand.cpp:1045
llvm::MachineMemOperand::isStore
bool isStore() const
Definition: MachineMemOperand.h:299
llvm::AtomicOrdering::AcquireRelease
@ AcquireRelease
llvm::PointerUnion::isNull
bool isNull() const
Test if the pointer held in the union is null, regardless of which type it is.
Definition: PointerUnion.h:142
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:112
llvm::MachineMemOperand::getAlign
Align getAlign() const
Return the minimum known alignment in bytes of the actual memory reference.
Definition: MachineOperand.cpp:1082
llvm::MachinePointerInfo::StackID
uint8_t StackID
Definition: MachineMemOperand.h:49
AtomicOrdering.h
LLVM_MARK_AS_BITMASK_ENUM
#define LLVM_MARK_AS_BITMASK_ENUM(LargestValue)
LLVM_MARK_AS_BITMASK_ENUM lets you opt in an individual enum type so you can perform bitwise operatio...
Definition: BitmaskEnum.h:41
llvm::MachineMemOperand::print
void print(raw_ostream &OS, ModuleSlotTracker &MST, SmallVectorImpl< StringRef > &SSNs, const LLVMContext &Context, const MachineFrameInfo *MFI, const TargetInstrInfo *TII) const
Support for operator<<.
Definition: MachineOperand.cpp:1086
llvm::MachinePointerInfo::getConstantPool
static MachinePointerInfo getConstantPool(MachineFunction &MF)
Return a MachinePointerInfo record that refers to the constant pool.
Definition: MachineOperand.cpp:997
llvm::MachinePointerInfo::getUnknownStack
static MachinePointerInfo getUnknownStack(MachineFunction &MF)
Stack memory without other information.
Definition: MachineOperand.cpp:1021
llvm::MachineMemOperand::isLoad
bool isLoad() const
Definition: MachineMemOperand.h:298
llvm::MachineMemOperand::getOffset
int64_t getOffset() const
For normal values, this is a byte offset added to the base address.
Definition: MachineMemOperand.h:227
llvm::Type::getPointerAddressSpace
unsigned getPointerAddressSpace() const
Get the address space of this pointer or pointer vector type.
Definition: DerivedTypes.h:733
llvm::SyncScope::System
@ System
Synchronized with respect to all concurrently executing threads.
Definition: LLVMContext.h:58
llvm::MachineMemOperand::MOInvariant
@ MOInvariant
The memory access always returns the same value (or traps).
Definition: MachineMemOperand.h:145
llvm::AtomicOrdering::SequentiallyConsistent
@ SequentiallyConsistent
llvm::MachinePointerInfo::MachinePointerInfo
MachinePointerInfo(const PseudoSourceValue *v, int64_t offset=0, uint8_t ID=0)
Definition: MachineMemOperand.h:57
llvm::MachineMemOperand::MOTargetFlag2
@ MOTargetFlag2
Definition: MachineMemOperand.h:152
llvm::MachineMemOperand::getSizeInBits
uint64_t getSizeInBits() const
Return the size in bits of the memory reference.
Definition: MachineMemOperand.h:241
llvm::AAMDNodes
A collection of metadata nodes that might be associated with a memory access used by the alias-analys...
Definition: Metadata.h:651
llvm::MachineMemOperand::getOpaqueValue
const void * getOpaqueValue() const
Definition: MachineMemOperand.h:217
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition: MachineMemOperand.h:128
llvm::MachineMemOperand::MODereferenceable
@ MODereferenceable
The memory access is dereferenceable (i.e., doesn't trap).
Definition: MachineMemOperand.h:143
llvm::MachineMemOperand::isInvariant
bool isInvariant() const
Definition: MachineMemOperand.h:303
llvm::MachineMemOperand::getAAInfo
AAMDNodes getAAInfo() const
Return the AA tags for the memory reference.
Definition: MachineMemOperand.h:258
llvm::MachineMemOperand::isUnordered
bool isUnordered() const
Returns true if this memory operation doesn't have any ordering constraints other than normal aliasin...
Definition: MachineMemOperand.h:314
llvm::ModuleSlotTracker
Manage lifetime of a slot tracker for printing IR.
Definition: ModuleSlotTracker.h:44
llvm::PointerUnion::get
T get() const
Returns the value of the specified pointer type.
Definition: PointerUnion.h:157
llvm::MachinePointerInfo::getJumpTable
static MachinePointerInfo getJumpTable(MachineFunction &MF)
Return a MachinePointerInfo record that refers to a jump table entry.
Definition: MachineOperand.cpp:1008
llvm::AtomicOrdering::Monotonic
@ Monotonic
llvm::PointerUnion::is
bool is() const
Test if the Union currently holds the type matching T.
Definition: PointerUnion.h:147
a
=0.0 ? 0.0 :(a > 0.0 ? 1.0 :-1.0) a
Definition: README.txt:489
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
llvm::MachinePointerInfo::Offset
int64_t Offset
Offset - This is an offset from the base Value*.
Definition: MachineMemOperand.h:45
llvm::MachineMemOperand::getPointerInfo
const MachinePointerInfo & getPointerInfo() const
Definition: MachineMemOperand.h:202
llvm::MachineMemOperand::MOTargetFlag1
@ MOTargetFlag1
Definition: MachineMemOperand.h:151
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:97
llvm::MachineMemOperand::getBaseAlign
Align getBaseAlign() const
Return the minimum known alignment in bytes of the base address, without the offset.
Definition: MachineMemOperand.h:255
f
Itanium Name Demangler i e convert the string _Z1fv into f()". You can also use the CRTP base ManglingParser to perform some simple analysis on the mangled name
llvm::MachineMemOperand::getAddrSpace
unsigned getAddrSpace() const
Definition: MachineMemOperand.h:229
llvm::MachineMemOperand::getValue
const Value * getValue() const
Return the base address of the memory access.
Definition: MachineMemOperand.h:211
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::MachinePointerInfo::getGOT
static MachinePointerInfo getGOT(MachineFunction &MF)
Return a MachinePointerInfo record that refers to a GOT entry.
Definition: MachineOperand.cpp:1012
PseudoSourceValue.h
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:129
llvm::AtomicOrdering::Acquire
@ Acquire
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:53
llvm::PseudoSourceValue
Special value supplied for machine level alias analysis.
Definition: PseudoSourceValue.h:35
Align
uint64_t Align
Definition: ELFObjHandler.cpp:83
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::AddressSpace
AddressSpace
Definition: NVPTXBaseInfo.h:21
llvm::MachinePointerInfo::MachinePointerInfo
MachinePointerInfo(const Value *v, int64_t offset=0, uint8_t ID=0)
Definition: MachineMemOperand.h:51
llvm::MachineMemOperand::getSyncScopeID
SyncScope::ID getSyncScopeID() const
Returns the synchronization scope ID for this memory operation.
Definition: MachineMemOperand.h:264
LowLevelTypeImpl.h
llvm::MachineMemOperand::setFlags
void setFlags(Flags f)
Bitwise OR the current flags with the given flags.
Definition: MachineMemOperand.h:223
llvm::MachineMemOperand::Profile
void Profile(FoldingSetNodeID &ID) const
Profile - Gather unique data for the object.
Definition: MachineOperand.cpp:1057
llvm::MachinePointerInfo::MachinePointerInfo
MachinePointerInfo(unsigned AddressSpace=0, int64_t offset=0)
Definition: MachineMemOperand.h:63
llvm::AtomicOrdering
AtomicOrdering
Atomic ordering for LLVM's memory model.
Definition: AtomicOrdering.h:56
llvm::RISCVFenceField::O
@ O
Definition: RISCVBaseInfo.h:179
type
AMD64 Optimization Manual has some nice information about optimizing integer multiplication by a constant How much of it applies to Intel s X86 implementation There are definite trade offs to xmm0 cvttss2siq rdx jb L3 subss xmm0 rax cvttss2siq rdx xorq rdx rax ret instead of xmm1 cvttss2siq rcx movaps xmm2 subss xmm2 cvttss2siq rax rdx xorq rax ucomiss xmm0 cmovb rax ret Seems like the jb branch has high likelihood of being taken It would have saved a few instructions It s not possible to reference and DH registers in an instruction requiring REX prefix divb and mulb both produce results in AH If isel emits a CopyFromReg which gets turned into a movb and that can be allocated a r8b r15b To get around isel emits a CopyFromReg from AX and then right shift it down by and truncate it It s not pretty but it works We need some register allocation magic to make the hack go which would often require a callee saved register Callees usually need to keep this value live for most of their body so it doesn t add a significant burden on them We currently implement this in however this is suboptimal because it means that it would be quite awkward to implement the optimization for callers A better implementation would be to relax the LLVM IR rules for sret arguments to allow a function with an sret argument to have a non void return type
Definition: README-X86-64.txt:70
llvm::MachinePointerInfo::isDereferenceable
bool isDereferenceable(unsigned Size, LLVMContext &C, const DataLayout &DL) const
Return true if memory region [V, V+Offset+Size) is known to be dereferenceable.
Definition: MachineOperand.cpp:982
llvm::MachineMemOperand::isDereferenceable
bool isDereferenceable() const
Definition: MachineMemOperand.h:302
const
aarch64 promote const
Definition: AArch64PromoteConstant.cpp:232
s
multiplies can be turned into SHL s
Definition: README.txt:370
llvm::PointerUnion::dyn_cast
T dyn_cast() const
Returns the current pointer if it is of the specified pointer type, otherwise returns null.
Definition: PointerUnion.h:164
llvm::MachinePointerInfo
This class contains a discriminated union of information about pointers in memory operands,...
Definition: MachineMemOperand.h:38
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:68
llvm::SyncScope::ID
uint8_t ID
Definition: LLVMContext.h:47
llvm::AtomicOrdering::Unordered
@ Unordered
llvm::MachineMemOperand::setOffset
void setOffset(int64_t NewOffset)
Definition: MachineMemOperand.h:330
llvm::MachineMemOperand::Flags
Flags
Flags values. These may be or'd together.
Definition: MachineMemOperand.h:131
llvm::PseudoSourceValue::getAddressSpace
unsigned getAddressSpace() const
Definition: PseudoSourceValue.h:73
llvm::MachineMemOperand::getSuccessOrdering
AtomicOrdering getSuccessOrdering() const
Return the atomic ordering requirements for this memory operation.
Definition: MachineMemOperand.h:271
llvm::MachineMemOperand::MONonTemporal
@ MONonTemporal
The memory access is non-temporal.
Definition: MachineMemOperand.h:141
PointerUnion.h
llvm::MachineMemOperand::getMemoryType
LLT getMemoryType() const
Return the memory type of the memory reference.
Definition: MachineMemOperand.h:233
llvm::MDNode
Metadata node.
Definition: Metadata.h:897
llvm::MachineMemOperand::getType
LLT getType() const
Definition: MachineMemOperand.h:245
llvm::MachinePointerInfo::getWithOffset
MachinePointerInfo getWithOffset(int64_t O) const
Definition: MachineMemOperand.h:80
llvm::MachineFunction
Definition: MachineFunction.h:230
llvm::MachineMemOperand::MOTargetFlag3
@ MOTargetFlag3
Definition: MachineMemOperand.h:153
llvm::MachinePointerInfo::V
PointerUnion< const Value *, const PseudoSourceValue * > V
This is the IR pointer value for the access, or it is null if unknown.
Definition: MachineMemOperand.h:42
llvm::Value::getType
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:256
BitmaskEnum.h
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::MachinePointerInfo::AddrSpace
unsigned AddrSpace
Definition: MachineMemOperand.h:47
llvm::FoldingSetNodeID
FoldingSetNodeID - This class is used to gather all the unique data bits of a node.
Definition: FoldingSet.h:313
llvm::MachineMemOperand::MOVolatile
@ MOVolatile
The memory access is volatile.
Definition: MachineMemOperand.h:139
llvm::MachinePointerInfo::getAddrSpace
unsigned getAddrSpace() const
Return the LLVM IR address space number that this pointer points into.
Definition: MachineOperand.cpp:978
llvm::MachineMemOperand::MOLoad
@ MOLoad
The memory access reads data.
Definition: MachineMemOperand.h:135
llvm::PointerUnion< const Value *, const PseudoSourceValue * >
llvm::AtomicOrdering::Release
@ Release
llvm::MachineMemOperand::isVolatile
bool isVolatile() const
Definition: MachineMemOperand.h:300
uint16_t
llvm::MachineMemOperand::getSize
uint64_t getSize() const
Return the size in bytes of the memory reference.
Definition: MachineMemOperand.h:236
llvm::MachineMemOperand::operator==
friend bool operator==(const MachineMemOperand &LHS, const MachineMemOperand &RHS)
Definition: MachineMemOperand.h:348
llvm::MachineMemOperand::isAtomic
bool isAtomic() const
Returns true if this operation has an atomic ordering requirement of unordered or higher,...
Definition: MachineMemOperand.h:307
llvm::MachineMemOperand::getMergedOrdering
AtomicOrdering getMergedOrdering() const
Return a single atomic ordering that is at least as strong as both the success and failure orderings ...
Definition: MachineMemOperand.h:284
llvm::MachineMemOperand::refineAlignment
void refineAlignment(const MachineMemOperand *MMO)
Update this MachineMemOperand to reflect the alignment of MMO, if it has a greater alignment.
Definition: MachineOperand.cpp:1065
llvm::MachineMemOperand::MOStore
@ MOStore
The memory access writes data.
Definition: MachineMemOperand.h:137
llvm::MachineMemOperand::setValue
void setValue(const PseudoSourceValue *NewSV)
Definition: MachineMemOperand.h:329
llvm::MachineMemOperand::operator!=
friend bool operator!=(const MachineMemOperand &LHS, const MachineMemOperand &RHS)
Definition: MachineMemOperand.h:361
llvm::MachineMemOperand::setType
void setType(LLT NewTy)
Reset the tracked memory type.
Definition: MachineMemOperand.h:333
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:107
llvm::MachinePointerInfo::getFixedStack
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
Definition: MachineOperand.cpp:1003
llvm::SmallVectorImpl< StringRef >
llvm::MachineMemOperand::getFailureOrdering
AtomicOrdering getFailureOrdering() const
For cmpxchg atomic operations, return the atomic ordering requirements when store does not occur.
Definition: MachineMemOperand.h:277
DataTypes.h
DerivedTypes.h
llvm::MachineMemOperand::isNonTemporal
bool isNonTemporal() const
Definition: MachineMemOperand.h:301
llvm::MachineMemOperand::getRanges
const MDNode * getRanges() const
Return the range tag for the memory reference.
Definition: MachineMemOperand.h:261
Value.h
llvm::MachineMemOperand::MONone
@ MONone
Definition: MachineMemOperand.h:133
llvm::MachinePointerInfo::getStack
static MachinePointerInfo getStack(MachineFunction &MF, int64_t Offset, uint8_t ID=0)
Stack pointer relative access.
Definition: MachineOperand.cpp:1016
llvm::MachinePointerInfo::MachinePointerInfo
MachinePointerInfo(PointerUnion< const Value *, const PseudoSourceValue * > v, int64_t offset=0, uint8_t ID=0)
Definition: MachineMemOperand.h:67
llvm::Value
LLVM Value Representation.
Definition: Value.h:75
llvm::MachineMemOperand::getFlags
Flags getFlags() const
Return the raw flags of the source value,.
Definition: MachineMemOperand.h:220
llvm::AtomicOrdering::NotAtomic
@ NotAtomic
llvm::MachineMemOperand::getPseudoValue
const PseudoSourceValue * getPseudoValue() const
Definition: MachineMemOperand.h:213
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:38
llvm::LLT
Definition: LowLevelTypeImpl.h:40