LLVM 18.0.0git
AntiDepBreaker.h
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1//===- llvm/CodeGen/AntiDepBreaker.h - Anti-Dependence Breaking -*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the AntiDepBreaker class, which implements
10// anti-dependence breaking heuristics for post-register-allocation scheduling.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_CODEGEN_ANTIDEPBREAKER_H
15#define LLVM_CODEGEN_ANTIDEPBREAKER_H
16
22#include <cassert>
23#include <utility>
24#include <vector>
25
26namespace llvm {
27
28class RegisterClassInfo;
29
30/// This class works in conjunction with the post-RA scheduler to rename
31/// registers to break register anti-dependencies (WAR hazards).
33public:
35 std::vector<std::pair<MachineInstr *, MachineInstr *>>;
36
37 virtual ~AntiDepBreaker();
38
39 /// Initialize anti-dep breaking for a new basic block.
40 virtual void StartBlock(MachineBasicBlock *BB) = 0;
41
42 /// Identifiy anti-dependencies within a basic-block region and break them by
43 /// renaming registers. Return the number of anti-dependencies broken.
44 virtual unsigned BreakAntiDependencies(const std::vector<SUnit> &SUnits,
47 unsigned InsertPosIndex,
48 DbgValueVector &DbgValues) = 0;
49
50 /// Update liveness information to account for the current
51 /// instruction, which will not be scheduled.
52 virtual void Observe(MachineInstr &MI, unsigned Count,
53 unsigned InsertPosIndex) = 0;
54
55 /// Finish anti-dep breaking for a basic block.
56 virtual void FinishBlock() = 0;
57
58 /// Update DBG_VALUE or DBG_PHI if dependency breaker is updating
59 /// other machine instruction to use NewReg.
60 void UpdateDbgValue(MachineInstr &MI, unsigned OldReg, unsigned NewReg) {
61 if (MI.isDebugValue()) {
62 if (MI.getDebugOperand(0).isReg() &&
63 MI.getDebugOperand(0).getReg() == OldReg)
64 MI.getDebugOperand(0).setReg(NewReg);
65 } else if (MI.isDebugPHI()) {
66 if (MI.getOperand(0).isReg() &&
67 MI.getOperand(0).getReg() == OldReg)
68 MI.getOperand(0).setReg(NewReg);
69 } else {
70 llvm_unreachable("MI is not DBG_VALUE / DBG_PHI!");
71 }
72 }
73
74 /// Update all DBG_VALUE instructions that may be affected by the dependency
75 /// breaker's update of ParentMI to use NewReg.
76 void UpdateDbgValues(const DbgValueVector &DbgValues, MachineInstr *ParentMI,
77 unsigned OldReg, unsigned NewReg) {
78 // The following code is dependent on the order in which the DbgValues are
79 // constructed in ScheduleDAGInstrs::buildSchedGraph.
80 MachineInstr *PrevDbgMI = nullptr;
81 for (const auto &DV : make_range(DbgValues.crbegin(), DbgValues.crend())) {
82 MachineInstr *PrevMI = DV.second;
83 if ((PrevMI == ParentMI) || (PrevMI == PrevDbgMI)) {
84 MachineInstr *DbgMI = DV.first;
85 UpdateDbgValue(*DbgMI, OldReg, NewReg);
86 PrevDbgMI = DbgMI;
87 } else if (PrevDbgMI) {
88 break; // If no match and already found a DBG_VALUE, we're done.
89 }
90 }
91 }
92};
93
94AntiDepBreaker *createAggressiveAntiDepBreaker(
95 MachineFunction &MFi, const RegisterClassInfo &RCI,
97
98AntiDepBreaker *createCriticalAntiDepBreaker(MachineFunction &MFi,
99 const RegisterClassInfo &RCI);
100
101} // end namespace llvm
102
103#endif // LLVM_CODEGEN_ANTIDEPBREAKER_H
bool End
Definition: ELF_riscv.cpp:478
IRTranslator LLVM IR MI
This class works in conjunction with the post-RA scheduler to rename registers to break register anti...
virtual void FinishBlock()=0
Finish anti-dep breaking for a basic block.
virtual unsigned BreakAntiDependencies(const std::vector< SUnit > &SUnits, MachineBasicBlock::iterator Begin, MachineBasicBlock::iterator End, unsigned InsertPosIndex, DbgValueVector &DbgValues)=0
Identifiy anti-dependencies within a basic-block region and break them by renaming registers.
void UpdateDbgValue(MachineInstr &MI, unsigned OldReg, unsigned NewReg)
Update DBG_VALUE or DBG_PHI if dependency breaker is updating other machine instruction to use NewReg...
virtual void Observe(MachineInstr &MI, unsigned Count, unsigned InsertPosIndex)=0
Update liveness information to account for the current instruction, which will not be scheduled.
virtual ~AntiDepBreaker()
void UpdateDbgValues(const DbgValueVector &DbgValues, MachineInstr *ParentMI, unsigned OldReg, unsigned NewReg)
Update all DBG_VALUE instructions that may be affected by the dependency breaker's update of ParentMI...
virtual void StartBlock(MachineBasicBlock *BB)=0
Initialize anti-dep breaking for a new basic block.
std::vector< std::pair< MachineInstr *, MachineInstr * > > DbgValueVector
Representation of each machine instruction.
Definition: MachineInstr.h:68
SmallVectorImpl< const TargetRegisterClass * > RegClassVector
This provides a very simple, boring adaptor for a begin and end iterator into a range type.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
AntiDepBreaker * createAggressiveAntiDepBreaker(MachineFunction &MFi, const RegisterClassInfo &RCI, TargetSubtargetInfo::RegClassVector &CriticalPathRCs)
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
AntiDepBreaker * createCriticalAntiDepBreaker(MachineFunction &MFi, const RegisterClassInfo &RCI)