LLVM 17.0.0git
TargetSubtargetInfo.h
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1//===- llvm/CodeGen/TargetSubtargetInfo.h - Target Information --*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file describes the subtarget options of a Target machine.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_CODEGEN_TARGETSUBTARGETINFO_H
14#define LLVM_CODEGEN_TARGETSUBTARGETINFO_H
15
16#include "llvm/ADT/ArrayRef.h"
18#include "llvm/ADT/StringRef.h"
21#include "llvm/IR/GlobalValue.h"
24#include <memory>
25#include <vector>
26
27namespace llvm {
28
29class APInt;
30class MachineFunction;
31class ScheduleDAGMutation;
32class CallLowering;
33class GlobalValue;
34class InlineAsmLowering;
35class InstrItineraryData;
36struct InstrStage;
37class InstructionSelector;
38class LegalizerInfo;
39class MachineInstr;
40struct MachineSchedPolicy;
41struct MCReadAdvanceEntry;
42struct MCWriteLatencyEntry;
43struct MCWriteProcResEntry;
44class RegisterBankInfo;
45class SDep;
46class SelectionDAGTargetInfo;
47class SUnit;
48class TargetFrameLowering;
49class TargetInstrInfo;
50class TargetLowering;
51class TargetRegisterClass;
52class TargetRegisterInfo;
53class TargetSchedModel;
54class Triple;
55
56//===----------------------------------------------------------------------===//
57///
58/// TargetSubtargetInfo - Generic base class for all target subtargets. All
59/// Target-specific options that control code generation and printing should
60/// be exposed through a TargetSubtargetInfo-derived class.
61///
63protected: // Can only create subclasses...
64 TargetSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU,
67 const MCWriteProcResEntry *WPR,
68 const MCWriteLatencyEntry *WL,
69 const MCReadAdvanceEntry *RA, const InstrStage *IS,
70 const unsigned *OC, const unsigned *FP);
71
72public:
73 // AntiDepBreakMode - Type of anti-dependence breaking that should
74 // be performed before post-RA scheduling.
75 using AntiDepBreakMode = enum { ANTIDEP_NONE, ANTIDEP_CRITICAL, ANTIDEP_ALL };
77
82
83 virtual bool isXRaySupported() const { return false; }
84
85 // Interfaces to the major aspects of target machine information:
86 //
87 // -- Instruction opcode and operand information
88 // -- Pipelines and scheduling information
89 // -- Stack frame information
90 // -- Selection DAG lowering information
91 // -- Call lowering information
92 //
93 // N.B. These objects may change during compilation. It's not safe to cache
94 // them between functions.
95 virtual const TargetInstrInfo *getInstrInfo() const { return nullptr; }
96 virtual const TargetFrameLowering *getFrameLowering() const {
97 return nullptr;
98 }
99 virtual const TargetLowering *getTargetLowering() const { return nullptr; }
101 return nullptr;
102 }
103 virtual const CallLowering *getCallLowering() const { return nullptr; }
104
106 return nullptr;
107 }
108
109 // FIXME: This lets targets specialize the selector by subtarget (which lets
110 // us do things like a dedicated avx512 selector). However, we might want
111 // to also specialize selectors by MachineFunction, which would let us be
112 // aware of optsize/optnone and such.
114 return nullptr;
115 }
116
117 /// Target can subclass this hook to select a different DAG scheduler.
120 return nullptr;
121 }
122
123 virtual const LegalizerInfo *getLegalizerInfo() const { return nullptr; }
124
125 /// getRegisterInfo - If register information is available, return it. If
126 /// not, return null.
127 virtual const TargetRegisterInfo *getRegisterInfo() const { return nullptr; }
128
129 /// If the information for the register banks is available, return it.
130 /// Otherwise return nullptr.
131 virtual const RegisterBankInfo *getRegBankInfo() const { return nullptr; }
132
133 /// getInstrItineraryData - Returns instruction itinerary data for the target
134 /// or specific subtarget.
136 return nullptr;
137 }
138
139 /// Resolve a SchedClass at runtime, where SchedClass identifies an
140 /// MCSchedClassDesc with the isVariant property. This may return the ID of
141 /// another variant SchedClass, but repeated invocation must quickly terminate
142 /// in a nonvariant SchedClass.
143 virtual unsigned resolveSchedClass(unsigned SchedClass,
144 const MachineInstr *MI,
145 const TargetSchedModel *SchedModel) const {
146 return 0;
147 }
148
149 /// Returns true if MI is a dependency breaking zero-idiom instruction for the
150 /// subtarget.
151 ///
152 /// This function also sets bits in Mask related to input operands that
153 /// are not in a data dependency relationship. There is one bit for each
154 /// machine operand; implicit operands follow explicit operands in the bit
155 /// representation used for Mask. An empty (i.e. a mask with all bits
156 /// cleared) means: data dependencies are "broken" for all the explicit input
157 /// machine operands of MI.
158 virtual bool isZeroIdiom(const MachineInstr *MI, APInt &Mask) const {
159 return false;
160 }
161
162 /// Returns true if MI is a dependency breaking instruction for the subtarget.
163 ///
164 /// Similar in behavior to `isZeroIdiom`. However, it knows how to identify
165 /// all dependency breaking instructions (i.e. not just zero-idioms).
166 ///
167 /// As for `isZeroIdiom`, this method returns a mask of "broken" dependencies.
168 /// (See method `isZeroIdiom` for a detailed description of Mask).
169 virtual bool isDependencyBreaking(const MachineInstr *MI, APInt &Mask) const {
170 return isZeroIdiom(MI, Mask);
171 }
172
173 /// Returns true if MI is a candidate for move elimination.
174 ///
175 /// A candidate for move elimination may be optimized out at register renaming
176 /// stage. Subtargets can specify the set of optimizable moves by
177 /// instantiating tablegen class `IsOptimizableRegisterMove` (see
178 /// llvm/Target/TargetInstrPredicate.td).
179 ///
180 /// SubtargetEmitter is responsible for processing all the definitions of class
181 /// IsOptimizableRegisterMove, and auto-generate an override for this method.
182 virtual bool isOptimizableRegisterMove(const MachineInstr *MI) const {
183 return false;
184 }
185
186 /// True if the subtarget should run MachineScheduler after aggressive
187 /// coalescing.
188 ///
189 /// This currently replaces the SelectionDAG scheduler with the "source" order
190 /// scheduler (though see below for an option to turn this off and use the
191 /// TargetLowering preference). It does not yet disable the postRA scheduler.
192 virtual bool enableMachineScheduler() const;
193
194 /// True if the machine scheduler should disable the TLI preference
195 /// for preRA scheduling with the source level scheduler.
196 virtual bool enableMachineSchedDefaultSched() const { return true; }
197
198 /// True if the subtarget should run MachinePipeliner
199 virtual bool enableMachinePipeliner() const { return true; };
200
201 /// True if the subtarget should enable joining global copies.
202 ///
203 /// By default this is enabled if the machine scheduler is enabled, but
204 /// can be overridden.
205 virtual bool enableJoinGlobalCopies() const;
206
207 /// True if the subtarget should run a scheduler after register allocation.
208 ///
209 /// By default this queries the PostRAScheduling bit in the scheduling model
210 /// which is the preferred way to influence this.
211 virtual bool enablePostRAScheduler() const;
212
213 /// True if the subtarget should run a machine scheduler after register
214 /// allocation.
215 virtual bool enablePostRAMachineScheduler() const;
216
217 /// True if the subtarget should run the atomic expansion pass.
218 virtual bool enableAtomicExpand() const;
219
220 /// True if the subtarget should run the indirectbr expansion pass.
221 virtual bool enableIndirectBrExpand() const;
222
223 /// Override generic scheduling policy within a region.
224 ///
225 /// This is a convenient way for targets that don't provide any custom
226 /// scheduling heuristics (no custom MachineSchedStrategy) to make
227 /// changes to the generic scheduling policy.
229 unsigned NumRegionInstrs) const {}
230
231 // Perform target-specific adjustments to the latency of a schedule
232 // dependency.
233 // If a pair of operands is associated with the schedule dependency, DefOpIdx
234 // and UseOpIdx are the indices of the operands in Def and Use, respectively.
235 // Otherwise, either may be -1.
236 virtual void adjustSchedDependency(SUnit *Def, int DefOpIdx, SUnit *Use,
237 int UseOpIdx, SDep &Dep) const {}
238
239 // For use with PostRAScheduling: get the anti-dependence breaking that should
240 // be performed before post-RA scheduling.
241 virtual AntiDepBreakMode getAntiDepBreakMode() const { return ANTIDEP_NONE; }
242
243 // For use with PostRAScheduling: in CriticalPathRCs, return any register
244 // classes that should only be considered for anti-dependence breaking if they
245 // are on the critical path.
246 virtual void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const {
247 return CriticalPathRCs.clear();
248 }
249
250 // Provide an ordered list of schedule DAG mutations for the post-RA
251 // scheduler.
252 virtual void getPostRAMutations(
253 std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations) const {
254 }
255
256 // Provide an ordered list of schedule DAG mutations for the machine
257 // pipeliner.
258 virtual void getSMSMutations(
259 std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations) const {
260 }
261
262 /// Default to DFA for resource management, return false when target will use
263 /// ProcResource in InstrSchedModel instead.
264 virtual bool useDFAforSMS() const { return true; }
265
266 // For use with PostRAScheduling: get the minimum optimization level needed
267 // to enable post-RA scheduling.
269 return CodeGenOpt::Default;
270 }
271
272 /// True if the subtarget should run the local reassignment
273 /// heuristic of the register allocator.
274 /// This heuristic may be compile time intensive, \p OptLevel provides
275 /// a finer grain to tune the register allocator.
276 virtual bool enableRALocalReassignment(CodeGenOpt::Level OptLevel) const;
277
278 /// Enable use of alias analysis during code generation (during MI
279 /// scheduling, DAGCombine, etc.).
280 virtual bool useAA() const;
281
282 /// \brief Sink addresses into blocks using GEP instructions rather than
283 /// pointer casts and arithmetic.
284 virtual bool addrSinkUsingGEPs() const {
285 return useAA();
286 }
287
288 /// Enable the use of the early if conversion pass.
289 virtual bool enableEarlyIfConversion() const { return false; }
290
291 /// Return PBQPConstraint(s) for the target.
292 ///
293 /// Override to provide custom PBQP constraints.
294 virtual std::unique_ptr<PBQPRAConstraint> getCustomPBQPConstraints() const {
295 return nullptr;
296 }
297
298 /// Enable tracking of subregister liveness in register allocator.
299 /// Please use MachineRegisterInfo::subRegLivenessEnabled() instead where
300 /// possible.
301 virtual bool enableSubRegLiveness() const { return false; }
302
303 /// This is called after a .mir file was loaded.
304 virtual void mirFileLoaded(MachineFunction &MF) const;
305
306 /// True if the register allocator should use the allocation orders exactly as
307 /// written in the tablegen descriptions, false if it should allocate
308 /// the specified physical register later if is it callee-saved.
310 unsigned PhysReg) const {
311 return false;
312 }
313
314 /// Classify a global function reference. This mainly used to fetch target
315 /// special flags for lowering a function address. For example mark a function
316 /// call should be plt or pc-related addressing.
317 virtual unsigned char
319 return 0;
320 }
321};
322
323} // end namespace llvm
324
325#endif // LLVM_CODEGEN_TARGETSUBTARGETINFO_H
IRTranslator LLVM IR MI
unsigned UseOpIdx
SI optimize exec mask operations pre RA
This file defines the SmallVector class.
Class for arbitrary precision integers.
Definition: APInt.h:75
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
Itinerary data supplied by a subtarget to be used by a target.
Provides the logic to select generic machine instructions.
Generic base class for all target subtargets.
Representation of each machine instruction.
Definition: MachineInstr.h:68
Holds all the information related to register banks.
ScheduleDAGSDNodes *(*)(SelectionDAGISel *, CodeGenOpt::Level) FunctionPassCtor
Scheduling dependency.
Definition: ScheduleDAG.h:49
Scheduling unit. This is a node in the scheduling DAG.
Definition: ScheduleDAG.h:242
Targets can subclass this to parameterize the SelectionDAG lowering and instruction selection process...
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:577
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
Information about stack frame layout on the target.
TargetInstrInfo - Interface to description of machine instruction set.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Provide an instruction scheduling machine model to CodeGen passes.
TargetSubtargetInfo - Generic base class for all target subtargets.
virtual unsigned char classifyGlobalFunctionReference(const GlobalValue *GV) const
Classify a global function reference.
virtual bool enableJoinGlobalCopies() const
True if the subtarget should enable joining global copies.
virtual bool enableIndirectBrExpand() const
True if the subtarget should run the indirectbr expansion pass.
enum { ANTIDEP_NONE, ANTIDEP_CRITICAL, ANTIDEP_ALL } AntiDepBreakMode
virtual const SelectionDAGTargetInfo * getSelectionDAGInfo() const
virtual const InlineAsmLowering * getInlineAsmLowering() const
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
virtual RegisterScheduler::FunctionPassCtor getDAGScheduler(CodeGenOpt::Level) const
Target can subclass this hook to select a different DAG scheduler.
virtual std::unique_ptr< PBQPRAConstraint > getCustomPBQPConstraints() const
Return PBQPConstraint(s) for the target.
virtual bool enableRALocalReassignment(CodeGenOpt::Level OptLevel) const
True if the subtarget should run the local reassignment heuristic of the register allocator.
virtual void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const
virtual bool enableMachineScheduler() const
True if the subtarget should run MachineScheduler after aggressive coalescing.
virtual void adjustSchedDependency(SUnit *Def, int DefOpIdx, SUnit *Use, int UseOpIdx, SDep &Dep) const
virtual bool ignoreCSRForAllocationOrder(const MachineFunction &MF, unsigned PhysReg) const
True if the register allocator should use the allocation orders exactly as written in the tablegen de...
virtual bool isDependencyBreaking(const MachineInstr *MI, APInt &Mask) const
Returns true if MI is a dependency breaking instruction for the subtarget.
virtual const CallLowering * getCallLowering() const
virtual bool isXRaySupported() const
virtual const RegisterBankInfo * getRegBankInfo() const
If the information for the register banks is available, return it.
virtual bool useAA() const
Enable use of alias analysis during code generation (during MI scheduling, DAGCombine,...
virtual void overrideSchedPolicy(MachineSchedPolicy &Policy, unsigned NumRegionInstrs) const
Override generic scheduling policy within a region.
TargetSubtargetInfo(const TargetSubtargetInfo &)=delete
virtual void mirFileLoaded(MachineFunction &MF) const
This is called after a .mir file was loaded.
virtual InstructionSelector * getInstructionSelector() const
virtual AntiDepBreakMode getAntiDepBreakMode() const
virtual void getPostRAMutations(std::vector< std::unique_ptr< ScheduleDAGMutation > > &Mutations) const
virtual void getSMSMutations(std::vector< std::unique_ptr< ScheduleDAGMutation > > &Mutations) const
virtual bool enablePostRAMachineScheduler() const
True if the subtarget should run a machine scheduler after register allocation.
virtual bool enableAtomicExpand() const
True if the subtarget should run the atomic expansion pass.
virtual bool enableMachinePipeliner() const
True if the subtarget should run MachinePipeliner.
virtual const LegalizerInfo * getLegalizerInfo() const
virtual bool useDFAforSMS() const
Default to DFA for resource management, return false when target will use ProcResource in InstrSchedM...
virtual CodeGenOpt::Level getOptLevelToEnablePostRAScheduler() const
virtual const TargetFrameLowering * getFrameLowering() const
virtual bool isOptimizableRegisterMove(const MachineInstr *MI) const
Returns true if MI is a candidate for move elimination.
virtual const TargetInstrInfo * getInstrInfo() const
virtual bool isZeroIdiom(const MachineInstr *MI, APInt &Mask) const
Returns true if MI is a dependency breaking zero-idiom instruction for the subtarget.
virtual bool enableMachineSchedDefaultSched() const
True if the machine scheduler should disable the TLI preference for preRA scheduling with the source ...
virtual bool enablePostRAScheduler() const
True if the subtarget should run a scheduler after register allocation.
virtual bool enableSubRegLiveness() const
Enable tracking of subregister liveness in register allocator.
virtual const TargetLowering * getTargetLowering() const
virtual bool addrSinkUsingGEPs() const
Sink addresses into blocks using GEP instructions rather than pointer casts and arithmetic.
virtual const InstrItineraryData * getInstrItineraryData() const
getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget.
virtual unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const
Resolve a SchedClass at runtime, where SchedClass identifies an MCSchedClassDesc with the isVariant p...
TargetSubtargetInfo & operator=(const TargetSubtargetInfo &)=delete
virtual bool enableEarlyIfConversion() const
Enable the use of the early if conversion pass.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
A Use represents the edge between a Value definition and its users.
Definition: Use.h:43
Level
Code generation optimization level.
Definition: CodeGen.h:57
@ Default
-O2, -Os
Definition: CodeGen.h:60
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
These values represent a non-pipelined step in the execution of an instruction.
Specify the number of cycles allowed after instruction issue before a particular use operand reads it...
Definition: MCSchedule.h:94
Specify the latency in cpu cycles for a particular scheduling class and def index.
Definition: MCSchedule.h:77
Identify one of the processor resource kinds consumed by a particular scheduling class for the specif...
Definition: MCSchedule.h:63
Define a generic scheduling policy for targets that don't provide their own MachineSchedStrategy.