LLVM  15.0.0git
TargetSubtargetInfo.h
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1 //===- llvm/CodeGen/TargetSubtargetInfo.h - Target Information --*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file describes the subtarget options of a Target machine.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_CODEGEN_TARGETSUBTARGETINFO_H
14 #define LLVM_CODEGEN_TARGETSUBTARGETINFO_H
15 
16 #include "llvm/ADT/ArrayRef.h"
17 #include "llvm/ADT/SmallVector.h"
18 #include "llvm/ADT/StringRef.h"
22 #include "llvm/Support/CodeGen.h"
23 #include <memory>
24 #include <vector>
25 
26 namespace llvm {
27 
28 class APInt;
29 class MachineFunction;
30 class ScheduleDAGMutation;
31 class CallLowering;
32 class InlineAsmLowering;
33 class InstrItineraryData;
34 struct InstrStage;
35 class InstructionSelector;
36 class LegalizerInfo;
37 class MachineInstr;
38 struct MachineSchedPolicy;
39 struct MCReadAdvanceEntry;
40 struct MCWriteLatencyEntry;
41 struct MCWriteProcResEntry;
42 class RegisterBankInfo;
43 class SDep;
44 class SelectionDAGTargetInfo;
45 class SUnit;
46 class TargetFrameLowering;
47 class TargetInstrInfo;
48 class TargetLowering;
49 class TargetRegisterClass;
50 class TargetRegisterInfo;
51 class TargetSchedModel;
52 class Triple;
53 
54 //===----------------------------------------------------------------------===//
55 ///
56 /// TargetSubtargetInfo - Generic base class for all target subtargets. All
57 /// Target-specific options that control code generation and printing should
58 /// be exposed through a TargetSubtargetInfo-derived class.
59 ///
61 protected: // Can only create subclasses...
62  TargetSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU,
65  const MCWriteProcResEntry *WPR,
66  const MCWriteLatencyEntry *WL,
67  const MCReadAdvanceEntry *RA, const InstrStage *IS,
68  const unsigned *OC, const unsigned *FP);
69 
70 public:
71  // AntiDepBreakMode - Type of anti-dependence breaking that should
72  // be performed before post-RA scheduling.
73  using AntiDepBreakMode = enum { ANTIDEP_NONE, ANTIDEP_CRITICAL, ANTIDEP_ALL };
75 
76  TargetSubtargetInfo() = delete;
77  TargetSubtargetInfo(const TargetSubtargetInfo &) = delete;
79  ~TargetSubtargetInfo() override;
80 
81  virtual bool isXRaySupported() const { return false; }
82 
83  // Interfaces to the major aspects of target machine information:
84  //
85  // -- Instruction opcode and operand information
86  // -- Pipelines and scheduling information
87  // -- Stack frame information
88  // -- Selection DAG lowering information
89  // -- Call lowering information
90  //
91  // N.B. These objects may change during compilation. It's not safe to cache
92  // them between functions.
93  virtual const TargetInstrInfo *getInstrInfo() const { return nullptr; }
94  virtual const TargetFrameLowering *getFrameLowering() const {
95  return nullptr;
96  }
97  virtual const TargetLowering *getTargetLowering() const { return nullptr; }
99  return nullptr;
100  }
101  virtual const CallLowering *getCallLowering() const { return nullptr; }
102 
103  virtual const InlineAsmLowering *getInlineAsmLowering() const {
104  return nullptr;
105  }
106 
107  // FIXME: This lets targets specialize the selector by subtarget (which lets
108  // us do things like a dedicated avx512 selector). However, we might want
109  // to also specialize selectors by MachineFunction, which would let us be
110  // aware of optsize/optnone and such.
112  return nullptr;
113  }
114 
115  /// Target can subclass this hook to select a different DAG scheduler.
118  return nullptr;
119  }
120 
121  virtual const LegalizerInfo *getLegalizerInfo() const { return nullptr; }
122 
123  /// getRegisterInfo - If register information is available, return it. If
124  /// not, return null.
125  virtual const TargetRegisterInfo *getRegisterInfo() const { return nullptr; }
126 
127  /// If the information for the register banks is available, return it.
128  /// Otherwise return nullptr.
129  virtual const RegisterBankInfo *getRegBankInfo() const { return nullptr; }
130 
131  /// getInstrItineraryData - Returns instruction itinerary data for the target
132  /// or specific subtarget.
133  virtual const InstrItineraryData *getInstrItineraryData() const {
134  return nullptr;
135  }
136 
137  /// Resolve a SchedClass at runtime, where SchedClass identifies an
138  /// MCSchedClassDesc with the isVariant property. This may return the ID of
139  /// another variant SchedClass, but repeated invocation must quickly terminate
140  /// in a nonvariant SchedClass.
141  virtual unsigned resolveSchedClass(unsigned SchedClass,
142  const MachineInstr *MI,
143  const TargetSchedModel *SchedModel) const {
144  return 0;
145  }
146 
147  /// Returns true if MI is a dependency breaking zero-idiom instruction for the
148  /// subtarget.
149  ///
150  /// This function also sets bits in Mask related to input operands that
151  /// are not in a data dependency relationship. There is one bit for each
152  /// machine operand; implicit operands follow explicit operands in the bit
153  /// representation used for Mask. An empty (i.e. a mask with all bits
154  /// cleared) means: data dependencies are "broken" for all the explicit input
155  /// machine operands of MI.
156  virtual bool isZeroIdiom(const MachineInstr *MI, APInt &Mask) const {
157  return false;
158  }
159 
160  /// Returns true if MI is a dependency breaking instruction for the subtarget.
161  ///
162  /// Similar in behavior to `isZeroIdiom`. However, it knows how to identify
163  /// all dependency breaking instructions (i.e. not just zero-idioms).
164  ///
165  /// As for `isZeroIdiom`, this method returns a mask of "broken" dependencies.
166  /// (See method `isZeroIdiom` for a detailed description of Mask).
167  virtual bool isDependencyBreaking(const MachineInstr *MI, APInt &Mask) const {
168  return isZeroIdiom(MI, Mask);
169  }
170 
171  /// Returns true if MI is a candidate for move elimination.
172  ///
173  /// A candidate for move elimination may be optimized out at register renaming
174  /// stage. Subtargets can specify the set of optimizable moves by
175  /// instantiating tablegen class `IsOptimizableRegisterMove` (see
176  /// llvm/Target/TargetInstrPredicate.td).
177  ///
178  /// SubtargetEmitter is responsible for processing all the definitions of class
179  /// IsOptimizableRegisterMove, and auto-generate an override for this method.
180  virtual bool isOptimizableRegisterMove(const MachineInstr *MI) const {
181  return false;
182  }
183 
184  /// True if the subtarget should run MachineScheduler after aggressive
185  /// coalescing.
186  ///
187  /// This currently replaces the SelectionDAG scheduler with the "source" order
188  /// scheduler (though see below for an option to turn this off and use the
189  /// TargetLowering preference). It does not yet disable the postRA scheduler.
190  virtual bool enableMachineScheduler() const;
191 
192  /// True if the machine scheduler should disable the TLI preference
193  /// for preRA scheduling with the source level scheduler.
194  virtual bool enableMachineSchedDefaultSched() const { return true; }
195 
196  /// True if the subtarget should run MachinePipeliner
197  virtual bool enableMachinePipeliner() const { return true; };
198 
199  /// True if the subtarget should enable joining global copies.
200  ///
201  /// By default this is enabled if the machine scheduler is enabled, but
202  /// can be overridden.
203  virtual bool enableJoinGlobalCopies() const;
204 
205  /// True if the subtarget should run a scheduler after register allocation.
206  ///
207  /// By default this queries the PostRAScheduling bit in the scheduling model
208  /// which is the preferred way to influence this.
209  virtual bool enablePostRAScheduler() const;
210 
211  /// True if the subtarget should run a machine scheduler after register
212  /// allocation.
213  virtual bool enablePostRAMachineScheduler() const;
214 
215  /// True if the subtarget should run the atomic expansion pass.
216  virtual bool enableAtomicExpand() const;
217 
218  /// True if the subtarget should run the indirectbr expansion pass.
219  virtual bool enableIndirectBrExpand() const;
220 
221  /// Override generic scheduling policy within a region.
222  ///
223  /// This is a convenient way for targets that don't provide any custom
224  /// scheduling heuristics (no custom MachineSchedStrategy) to make
225  /// changes to the generic scheduling policy.
227  unsigned NumRegionInstrs) const {}
228 
229  // Perform target-specific adjustments to the latency of a schedule
230  // dependency.
231  // If a pair of operands is associated with the schedule dependency, DefOpIdx
232  // and UseOpIdx are the indices of the operands in Def and Use, respectively.
233  // Otherwise, either may be -1.
234  virtual void adjustSchedDependency(SUnit *Def, int DefOpIdx, SUnit *Use,
235  int UseOpIdx, SDep &Dep) const {}
236 
237  // For use with PostRAScheduling: get the anti-dependence breaking that should
238  // be performed before post-RA scheduling.
239  virtual AntiDepBreakMode getAntiDepBreakMode() const { return ANTIDEP_NONE; }
240 
241  // For use with PostRAScheduling: in CriticalPathRCs, return any register
242  // classes that should only be considered for anti-dependence breaking if they
243  // are on the critical path.
244  virtual void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const {
245  return CriticalPathRCs.clear();
246  }
247 
248  // Provide an ordered list of schedule DAG mutations for the post-RA
249  // scheduler.
250  virtual void getPostRAMutations(
251  std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations) const {
252  }
253 
254  // Provide an ordered list of schedule DAG mutations for the machine
255  // pipeliner.
256  virtual void getSMSMutations(
257  std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations) const {
258  }
259 
260  /// Default to DFA for resource management, return false when target will use
261  /// ProcResource in InstrSchedModel instead.
262  virtual bool useDFAforSMS() const { return true; }
263 
264  // For use with PostRAScheduling: get the minimum optimization level needed
265  // to enable post-RA scheduling.
267  return CodeGenOpt::Default;
268  }
269 
270  /// True if the subtarget should run the local reassignment
271  /// heuristic of the register allocator.
272  /// This heuristic may be compile time intensive, \p OptLevel provides
273  /// a finer grain to tune the register allocator.
274  virtual bool enableRALocalReassignment(CodeGenOpt::Level OptLevel) const;
275 
276  /// Enable use of alias analysis during code generation (during MI
277  /// scheduling, DAGCombine, etc.).
278  virtual bool useAA() const;
279 
280  /// \brief Sink addresses into blocks using GEP instructions rather than
281  /// pointer casts and arithmetic.
282  virtual bool addrSinkUsingGEPs() const {
283  return useAA();
284  }
285 
286  /// Enable the use of the early if conversion pass.
287  virtual bool enableEarlyIfConversion() const { return false; }
288 
289  /// Return PBQPConstraint(s) for the target.
290  ///
291  /// Override to provide custom PBQP constraints.
292  virtual std::unique_ptr<PBQPRAConstraint> getCustomPBQPConstraints() const {
293  return nullptr;
294  }
295 
296  /// Enable tracking of subregister liveness in register allocator.
297  /// Please use MachineRegisterInfo::subRegLivenessEnabled() instead where
298  /// possible.
299  virtual bool enableSubRegLiveness() const { return false; }
300 
301  /// This is called after a .mir file was loaded.
302  virtual void mirFileLoaded(MachineFunction &MF) const;
303 
304  /// True if the register allocator should use the allocation orders exactly as
305  /// written in the tablegen descriptions, false if it should allocate
306  /// the specified physical register later if is it callee-saved.
308  unsigned PhysReg) const {
309  return false;
310  }
311 };
312 
313 } // end namespace llvm
314 
315 #endif // LLVM_CODEGEN_TARGETSUBTARGETINFO_H
CmpMode::FP
@ FP
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:104
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::tgtok::Def
@ Def
Definition: TGLexer.h:50
llvm::TargetFrameLowering
Information about stack frame layout on the target.
Definition: TargetFrameLowering.h:43
llvm::TargetSubtargetInfo::AntiDepBreakMode
enum { ANTIDEP_NONE, ANTIDEP_CRITICAL, ANTIDEP_ALL } AntiDepBreakMode
Definition: TargetSubtargetInfo.h:73
llvm::TargetSubtargetInfo::enablePostRAScheduler
virtual bool enablePostRAScheduler() const
True if the subtarget should run a scheduler after register allocation.
Definition: TargetSubtargetInfo.cpp:48
llvm::InlineAsmLowering
Definition: InlineAsmLowering.h:28
llvm::TargetSubtargetInfo::resolveSchedClass
virtual unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const
Resolve a SchedClass at runtime, where SchedClass identifies an MCSchedClassDesc with the isVariant p...
Definition: TargetSubtargetInfo.h:141
StringRef.h
SchedulerRegistry.h
llvm::TargetSubtargetInfo::getInstrInfo
virtual const TargetInstrInfo * getInstrInfo() const
Definition: TargetSubtargetInfo.h:93
llvm::X86II::PD
@ PD
Definition: X86BaseInfo.h:787
PBQPRAConstraint.h
llvm::TargetSubtargetInfo::enableRALocalReassignment
virtual bool enableRALocalReassignment(CodeGenOpt::Level OptLevel) const
True if the subtarget should run the local reassignment heuristic of the register allocator.
Definition: TargetSubtargetInfo.cpp:43
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
llvm::TargetSubtargetInfo::getRegisterInfo
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
Definition: TargetSubtargetInfo.h:125
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:234
llvm::TargetSubtargetInfo::enableSubRegLiveness
virtual bool enableSubRegLiveness() const
Enable tracking of subregister liveness in register allocator.
Definition: TargetSubtargetInfo.h:299
llvm::TargetSubtargetInfo::mirFileLoaded
virtual void mirFileLoaded(MachineFunction &MF) const
This is called after a .mir file was loaded.
Definition: TargetSubtargetInfo.cpp:60
llvm::TargetSubtargetInfo::enableMachineSchedDefaultSched
virtual bool enableMachineSchedDefaultSched() const
True if the machine scheduler should disable the TLI preference for preRA scheduling with the source ...
Definition: TargetSubtargetInfo.h:194
llvm::TargetSubtargetInfo::getOptLevelToEnablePostRAScheduler
virtual CodeGenOpt::Level getOptLevelToEnablePostRAScheduler() const
Definition: TargetSubtargetInfo.h:266
llvm::MCWriteProcResEntry
Identify one of the processor resource kinds consumed by a particular scheduling class for the specif...
Definition: MCSchedule.h:63
llvm::TargetSubtargetInfo::ignoreCSRForAllocationOrder
virtual bool ignoreCSRForAllocationOrder(const MachineFunction &MF, unsigned PhysReg) const
True if the register allocator should use the allocation orders exactly as written in the tablegen de...
Definition: TargetSubtargetInfo.h:307
llvm::TargetSubtargetInfo::getInstructionSelector
virtual InstructionSelector * getInstructionSelector() const
Definition: TargetSubtargetInfo.h:111
llvm::TargetSubtargetInfo::getSelectionDAGInfo
virtual const SelectionDAGTargetInfo * getSelectionDAGInfo() const
Definition: TargetSubtargetInfo.h:98
llvm::BitmaskEnumDetail::Mask
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:97
llvm::TargetSubtargetInfo::isXRaySupported
virtual bool isXRaySupported() const
Definition: TargetSubtargetInfo.h:81
llvm::TargetLowering
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Definition: TargetLowering.h:3412
llvm::SelectionDAGTargetInfo
Targets can subclass this to parameterize the SelectionDAG lowering and instruction selection process...
Definition: SelectionDAGTargetInfo.h:31
llvm::TargetSubtargetInfo::getCriticalPathRCs
virtual void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const
Definition: TargetSubtargetInfo.h:244
llvm::TargetSubtargetInfo::~TargetSubtargetInfo
~TargetSubtargetInfo() override
MCSubtargetInfo.h
llvm::RegisterScheduler::FunctionPassCtor
ScheduleDAGSDNodes *(*)(SelectionDAGISel *, CodeGenOpt::Level) FunctionPassCtor
Definition: SchedulerRegistry.h:36
llvm::RegisterBankInfo
Holds all the information related to register banks.
Definition: RegisterBankInfo.h:39
llvm::InstructionSelector
Provides the logic to select generic machine instructions.
Definition: InstructionSelector.h:424
llvm::CodeGenOpt::Default
@ Default
Definition: CodeGen.h:55
llvm::TargetSubtargetInfo::enableIndirectBrExpand
virtual bool enableIndirectBrExpand() const
True if the subtarget should run the indirectbr expansion pass.
Definition: TargetSubtargetInfo.cpp:31
llvm::TargetSchedModel
Provide an instruction scheduling machine model to CodeGen passes.
Definition: TargetSchedule.h:30
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::TargetSubtargetInfo::enablePostRAMachineScheduler
virtual bool enablePostRAMachineScheduler() const
True if the subtarget should run a machine scheduler after register allocation.
Definition: TargetSubtargetInfo.cpp:52
llvm::TargetSubtargetInfo::isOptimizableRegisterMove
virtual bool isOptimizableRegisterMove(const MachineInstr *MI) const
Returns true if MI is a candidate for move elimination.
Definition: TargetSubtargetInfo.h:180
llvm::MCWriteLatencyEntry
Specify the latency in cpu cycles for a particular scheduling class and def index.
Definition: MCSchedule.h:77
ArrayRef.h
llvm::TargetSubtargetInfo::useDFAforSMS
virtual bool useDFAforSMS() const
Default to DFA for resource management, return false when target will use ProcResource in InstrSchedM...
Definition: TargetSubtargetInfo.h:262
llvm::TargetSubtargetInfo::enableEarlyIfConversion
virtual bool enableEarlyIfConversion() const
Enable the use of the early if conversion pass.
Definition: TargetSubtargetInfo.h:287
llvm::TargetSubtargetInfo::getDAGScheduler
virtual RegisterScheduler::FunctionPassCtor getDAGScheduler(CodeGenOpt::Level) const
Target can subclass this hook to select a different DAG scheduler.
Definition: TargetSubtargetInfo.h:117
llvm::X86AS::FS
@ FS
Definition: X86.h:192
llvm::SystemZISD::OC
@ OC
Definition: SystemZISelLowering.h:122
llvm::TargetSubtargetInfo::overrideSchedPolicy
virtual void overrideSchedPolicy(MachineSchedPolicy &Policy, unsigned NumRegionInstrs) const
Override generic scheduling policy within a region.
Definition: TargetSubtargetInfo.h:226
RA
SI optimize exec mask operations pre RA
Definition: SIOptimizeExecMaskingPreRA.cpp:71
llvm::TargetSubtargetInfo::useAA
virtual bool useAA() const
Enable use of alias analysis during code generation (during MI scheduling, DAGCombine,...
Definition: TargetSubtargetInfo.cpp:56
llvm::TargetSubtargetInfo::getRegBankInfo
virtual const RegisterBankInfo * getRegBankInfo() const
If the information for the register banks is available, return it.
Definition: TargetSubtargetInfo.h:129
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::TargetSubtargetInfo::getCallLowering
virtual const CallLowering * getCallLowering() const
Definition: TargetSubtargetInfo.h:101
llvm::TargetSubtargetInfo::isZeroIdiom
virtual bool isZeroIdiom(const MachineInstr *MI, APInt &Mask) const
Returns true if MI is a dependency breaking zero-idiom instruction for the subtarget.
Definition: TargetSubtargetInfo.h:156
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::TargetSubtargetInfo::enableMachinePipeliner
virtual bool enableMachinePipeliner() const
True if the subtarget should run MachinePipeliner.
Definition: TargetSubtargetInfo.h:197
llvm::TargetSubtargetInfo::enableJoinGlobalCopies
virtual bool enableJoinGlobalCopies() const
True if the subtarget should enable joining global copies.
Definition: TargetSubtargetInfo.cpp:39
llvm::CodeGenOpt::Level
Level
Definition: CodeGen.h:52
llvm::TargetSubtargetInfo
TargetSubtargetInfo - Generic base class for all target subtargets.
Definition: TargetSubtargetInfo.h:60
llvm::TargetSubtargetInfo::getCustomPBQPConstraints
virtual std::unique_ptr< PBQPRAConstraint > getCustomPBQPConstraints() const
Return PBQPConstraint(s) for the target.
Definition: TargetSubtargetInfo.h:292
llvm::InstrStage
These values represent a non-pipelined step in the execution of an instruction.
Definition: MCInstrItineraries.h:58
llvm::SDep
Scheduling dependency.
Definition: ScheduleDAG.h:49
llvm::TargetSubtargetInfo::getLegalizerInfo
virtual const LegalizerInfo * getLegalizerInfo() const
Definition: TargetSubtargetInfo.h:121
llvm::TargetSubtargetInfo::getFrameLowering
virtual const TargetFrameLowering * getFrameLowering() const
Definition: TargetSubtargetInfo.h:94
llvm::MCReadAdvanceEntry
Specify the number of cycles allowed after instruction issue before a particular use operand reads it...
Definition: MCSchedule.h:94
llvm::TargetSubtargetInfo::TargetSubtargetInfo
TargetSubtargetInfo()=delete
llvm::SmallVectorImpl::clear
void clear()
Definition: SmallVector.h:591
llvm::TargetSubtargetInfo::getInlineAsmLowering
virtual const InlineAsmLowering * getInlineAsmLowering() const
Definition: TargetSubtargetInfo.h:103
llvm::TargetSubtargetInfo::getPostRAMutations
virtual void getPostRAMutations(std::vector< std::unique_ptr< ScheduleDAGMutation >> &Mutations) const
Definition: TargetSubtargetInfo.h:250
llvm::TargetSubtargetInfo::isDependencyBreaking
virtual bool isDependencyBreaking(const MachineInstr *MI, APInt &Mask) const
Returns true if MI is a dependency breaking instruction for the subtarget.
Definition: TargetSubtargetInfo.h:167
CodeGen.h
llvm::TargetSubtargetInfo::getSMSMutations
virtual void getSMSMutations(std::vector< std::unique_ptr< ScheduleDAGMutation >> &Mutations) const
Definition: TargetSubtargetInfo.h:256
llvm::TargetSubtargetInfo::addrSinkUsingGEPs
virtual bool addrSinkUsingGEPs() const
Sink addresses into blocks using GEP instructions rather than pointer casts and arithmetic.
Definition: TargetSubtargetInfo.h:282
llvm::TargetSubtargetInfo::getTargetLowering
virtual const TargetLowering * getTargetLowering() const
Definition: TargetSubtargetInfo.h:97
SmallVector.h
llvm::TargetSubtargetInfo::getInstrItineraryData
virtual const InstrItineraryData * getInstrItineraryData() const
getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget.
Definition: TargetSubtargetInfo.h:133
llvm::TargetSubtargetInfo::adjustSchedDependency
virtual void adjustSchedDependency(SUnit *Def, int DefOpIdx, SUnit *Use, int UseOpIdx, SDep &Dep) const
Definition: TargetSubtargetInfo.h:234
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
llvm::TargetSubtargetInfo::operator=
TargetSubtargetInfo & operator=(const TargetSubtargetInfo &)=delete
llvm::LegalizerInfo
Definition: LegalizerInfo.h:1180
llvm::SUnit
Scheduling unit. This is a node in the scheduling DAG.
Definition: ScheduleDAG.h:242
llvm::MachineSchedPolicy
Define a generic scheduling policy for targets that don't provide their own MachineSchedStrategy.
Definition: MachineScheduler.h:179
llvm::CallLowering
Definition: CallLowering.h:44
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:76
llvm::TargetSubtargetInfo::enableMachineScheduler
virtual bool enableMachineScheduler() const
True if the subtarget should run MachineScheduler after aggressive coalescing.
Definition: TargetSubtargetInfo.cpp:35
llvm::InstrItineraryData
Itinerary data supplied by a subtarget to be used by a target.
Definition: MCInstrItineraries.h:109
llvm::TargetSubtargetInfo::getAntiDepBreakMode
virtual AntiDepBreakMode getAntiDepBreakMode() const
Definition: TargetSubtargetInfo.h:239
llvm::Use
A Use represents the edge between a Value definition and its users.
Definition: Use.h:43
llvm::TargetSubtargetInfo::enableAtomicExpand
virtual bool enableAtomicExpand() const
True if the subtarget should run the atomic expansion pass.
Definition: TargetSubtargetInfo.cpp:27