LLVM 19.0.0git
BPFMCCodeEmitter.cpp
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1//===-- BPFMCCodeEmitter.cpp - Convert BPF code to machine code -----------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the BPFMCCodeEmitter class.
10//
11//===----------------------------------------------------------------------===//
12
17#include "llvm/MC/MCExpr.h"
18#include "llvm/MC/MCFixup.h"
19#include "llvm/MC/MCInst.h"
20#include "llvm/MC/MCInstrInfo.h"
23#include "llvm/Support/Endian.h"
25#include <cassert>
26#include <cstdint>
27
28using namespace llvm;
29
30#define DEBUG_TYPE "mccodeemitter"
31
32namespace {
33
34class BPFMCCodeEmitter : public MCCodeEmitter {
35 const MCRegisterInfo &MRI;
36 bool IsLittleEndian;
37
38public:
39 BPFMCCodeEmitter(const MCInstrInfo &, const MCRegisterInfo &mri,
40 bool IsLittleEndian)
41 : MRI(mri), IsLittleEndian(IsLittleEndian) { }
42 BPFMCCodeEmitter(const BPFMCCodeEmitter &) = delete;
43 void operator=(const BPFMCCodeEmitter &) = delete;
44 ~BPFMCCodeEmitter() override = default;
45
46 // getBinaryCodeForInstr - TableGen'erated function for getting the
47 // binary encoding for an instruction.
48 uint64_t getBinaryCodeForInstr(const MCInst &MI,
50 const MCSubtargetInfo &STI) const;
51
52 // getMachineOpValue - Return binary encoding of operand. If the machin
53 // operand requires relocation, record the relocation and return zero.
54 unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,
56 const MCSubtargetInfo &STI) const;
57
58 uint64_t getMemoryOpValue(const MCInst &MI, unsigned Op,
60 const MCSubtargetInfo &STI) const;
61
64 const MCSubtargetInfo &STI) const override;
65};
66
67} // end anonymous namespace
68
70 MCContext &Ctx) {
71 return new BPFMCCodeEmitter(MCII, *Ctx.getRegisterInfo(), true);
72}
73
75 MCContext &Ctx) {
76 return new BPFMCCodeEmitter(MCII, *Ctx.getRegisterInfo(), false);
77}
78
79unsigned BPFMCCodeEmitter::getMachineOpValue(const MCInst &MI,
80 const MCOperand &MO,
82 const MCSubtargetInfo &STI) const {
83 if (MO.isReg())
84 return MRI.getEncodingValue(MO.getReg());
85 if (MO.isImm())
86 return static_cast<unsigned>(MO.getImm());
87
88 assert(MO.isExpr());
89
90 const MCExpr *Expr = MO.getExpr();
91
93
94 if (MI.getOpcode() == BPF::JAL)
95 // func call name
96 Fixups.push_back(MCFixup::create(0, Expr, FK_PCRel_4));
97 else if (MI.getOpcode() == BPF::LD_imm64)
98 Fixups.push_back(MCFixup::create(0, Expr, FK_SecRel_8));
99 else if (MI.getOpcode() == BPF::JMPL)
100 Fixups.push_back(MCFixup::create(0, Expr, (MCFixupKind)BPF::FK_BPF_PCRel_4));
101 else
102 // bb label
103 Fixups.push_back(MCFixup::create(0, Expr, FK_PCRel_2));
104
105 return 0;
106}
107
108static uint8_t SwapBits(uint8_t Val)
109{
110 return (Val & 0x0F) << 4 | (Val & 0xF0) >> 4;
111}
112
113void BPFMCCodeEmitter::encodeInstruction(const MCInst &MI,
116 const MCSubtargetInfo &STI) const {
117 unsigned Opcode = MI.getOpcode();
121
122 if (Opcode == BPF::LD_imm64 || Opcode == BPF::LD_pseudo) {
123 uint64_t Value = getBinaryCodeForInstr(MI, Fixups, STI);
124 CB.push_back(Value >> 56);
125 if (IsLittleEndian)
126 CB.push_back((Value >> 48) & 0xff);
127 else
128 CB.push_back(SwapBits((Value >> 48) & 0xff));
129 OSE.write<uint16_t>(0);
130 OSE.write<uint32_t>(Value & 0xffffFFFF);
131
132 const MCOperand &MO = MI.getOperand(1);
133 uint64_t Imm = MO.isImm() ? MO.getImm() : 0;
134 OSE.write<uint8_t>(0);
135 OSE.write<uint8_t>(0);
136 OSE.write<uint16_t>(0);
137 OSE.write<uint32_t>(Imm >> 32);
138 } else {
139 // Get instruction encoding and emit it
140 uint64_t Value = getBinaryCodeForInstr(MI, Fixups, STI);
141 CB.push_back(Value >> 56);
142 if (IsLittleEndian)
143 CB.push_back(char((Value >> 48) & 0xff));
144 else
145 CB.push_back(SwapBits((Value >> 48) & 0xff));
146 OSE.write<uint16_t>((Value >> 32) & 0xffff);
147 OSE.write<uint32_t>(Value & 0xffffFFFF);
148 }
149}
150
151// Encode BPF Memory Operand
152uint64_t BPFMCCodeEmitter::getMemoryOpValue(const MCInst &MI, unsigned Op,
154 const MCSubtargetInfo &STI) const {
155 // For CMPXCHG instructions, output is implicitly in R0/W0,
156 // so memory operand starts from operand 0.
157 int MemOpStartIndex = 1, Opcode = MI.getOpcode();
158 if (Opcode == BPF::CMPXCHGW32 || Opcode == BPF::CMPXCHGD)
159 MemOpStartIndex = 0;
160
161 uint64_t Encoding;
162 const MCOperand Op1 = MI.getOperand(MemOpStartIndex);
163 assert(Op1.isReg() && "First operand is not register.");
164 Encoding = MRI.getEncodingValue(Op1.getReg());
165 Encoding <<= 16;
166 MCOperand Op2 = MI.getOperand(MemOpStartIndex + 1);
167 assert(Op2.isImm() && "Second operand is not immediate.");
168 Encoding |= Op2.getImm() & 0xffff;
169 return Encoding;
170}
171
172#include "BPFGenMCCodeEmitter.inc"
unsigned const MachineRegisterInfo * MRI
static uint8_t SwapBits(uint8_t Val)
IRTranslator LLVM IR MI
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
raw_pwrite_stream & OS
This file defines the SmallVector class.
This class represents an Operation in the Expression.
MCCodeEmitter - Generic instruction encoding interface.
Definition: MCCodeEmitter.h:21
virtual void encodeInstruction(const MCInst &Inst, SmallVectorImpl< char > &CB, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const =0
Encode the given Inst to bytes and append to CB.
MCCodeEmitter & operator=(const MCCodeEmitter &)=delete
Context object for machine code objects.
Definition: MCContext.h:82
const MCRegisterInfo * getRegisterInfo() const
Definition: MCContext.h:417
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
@ SymbolRef
References to labels and assigned expressions.
Definition: MCExpr.h:40
ExprKind getKind() const
Definition: MCExpr.h:81
static MCFixup create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, SMLoc Loc=SMLoc())
Definition: MCFixup.h:87
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:26
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:36
int64_t getImm() const
Definition: MCInst.h:80
bool isImm() const
Definition: MCInst.h:62
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:69
bool isReg() const
Definition: MCInst.h:61
const MCExpr * getExpr() const
Definition: MCInst.h:114
bool isExpr() const
Definition: MCInst.h:65
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Generic base class for all target subtargets.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:586
void push_back(const T &Elt)
Definition: SmallVector.h:426
LLVM Value Representation.
Definition: Value.h:74
A raw_ostream that writes to an SmallVector or SmallString.
Definition: raw_ostream.h:691
@ FK_BPF_PCRel_4
Definition: BPFMCFixups.h:18
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
MCFixupKind
Extensible enumeration to represent the type of a fixup.
Definition: MCFixup.h:21
@ FK_PCRel_4
A four-byte pc relative fixup.
Definition: MCFixup.h:30
@ FK_PCRel_2
A two-byte pc relative fixup.
Definition: MCFixup.h:29
@ FK_SecRel_8
A eight-byte section relative fixup.
Definition: MCFixup.h:43
MCCodeEmitter * createBPFbeMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)
MCCodeEmitter * createBPFMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)
Adapter to write values to a stream in a particular byte order.
Definition: EndianStream.h:67