LLVM  13.0.0git
BPFMCCodeEmitter.cpp
Go to the documentation of this file.
1 //===-- BPFMCCodeEmitter.cpp - Convert BPF code to machine code -----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the BPFMCCodeEmitter class.
10 //
11 //===----------------------------------------------------------------------===//
12 
14 #include "llvm/ADT/SmallVector.h"
15 #include "llvm/MC/MCCodeEmitter.h"
16 #include "llvm/MC/MCExpr.h"
17 #include "llvm/MC/MCFixup.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/MC/MCInstrInfo.h"
20 #include "llvm/MC/MCRegisterInfo.h"
22 #include "llvm/Support/Endian.h"
24 #include <cassert>
25 #include <cstdint>
26 
27 using namespace llvm;
28 
29 #define DEBUG_TYPE "mccodeemitter"
30 
31 namespace {
32 
33 class BPFMCCodeEmitter : public MCCodeEmitter {
34  const MCInstrInfo &MCII;
35  const MCRegisterInfo &MRI;
36  bool IsLittleEndian;
37 
38 public:
39  BPFMCCodeEmitter(const MCInstrInfo &mcii, const MCRegisterInfo &mri,
40  bool IsLittleEndian)
41  : MCII(mcii), MRI(mri), IsLittleEndian(IsLittleEndian) {}
42  BPFMCCodeEmitter(const BPFMCCodeEmitter &) = delete;
43  void operator=(const BPFMCCodeEmitter &) = delete;
44  ~BPFMCCodeEmitter() override = default;
45 
46  // getBinaryCodeForInstr - TableGen'erated function for getting the
47  // binary encoding for an instruction.
48  uint64_t getBinaryCodeForInstr(const MCInst &MI,
50  const MCSubtargetInfo &STI) const;
51 
52  // getMachineOpValue - Return binary encoding of operand. If the machin
53  // operand requires relocation, record the relocation and return zero.
54  unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,
56  const MCSubtargetInfo &STI) const;
57 
58  uint64_t getMemoryOpValue(const MCInst &MI, unsigned Op,
60  const MCSubtargetInfo &STI) const;
61 
62  void encodeInstruction(const MCInst &MI, raw_ostream &OS,
64  const MCSubtargetInfo &STI) const override;
65 
66 private:
67  FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) const;
68  void
69  verifyInstructionPredicates(const MCInst &MI,
70  const FeatureBitset &AvailableFeatures) const;
71 };
72 
73 } // end anonymous namespace
74 
76  const MCRegisterInfo &MRI,
77  MCContext &Ctx) {
78  return new BPFMCCodeEmitter(MCII, MRI, true);
79 }
80 
82  const MCRegisterInfo &MRI,
83  MCContext &Ctx) {
84  return new BPFMCCodeEmitter(MCII, MRI, false);
85 }
86 
87 unsigned BPFMCCodeEmitter::getMachineOpValue(const MCInst &MI,
88  const MCOperand &MO,
90  const MCSubtargetInfo &STI) const {
91  if (MO.isReg())
92  return MRI.getEncodingValue(MO.getReg());
93  if (MO.isImm())
94  return static_cast<unsigned>(MO.getImm());
95 
96  assert(MO.isExpr());
97 
98  const MCExpr *Expr = MO.getExpr();
99 
100  assert(Expr->getKind() == MCExpr::SymbolRef);
101 
102  if (MI.getOpcode() == BPF::JAL)
103  // func call name
104  Fixups.push_back(MCFixup::create(0, Expr, FK_PCRel_4));
105  else if (MI.getOpcode() == BPF::LD_imm64)
106  Fixups.push_back(MCFixup::create(0, Expr, FK_SecRel_8));
107  else
108  // bb label
109  Fixups.push_back(MCFixup::create(0, Expr, FK_PCRel_2));
110 
111  return 0;
112 }
113 
114 static uint8_t SwapBits(uint8_t Val)
115 {
116  return (Val & 0x0F) << 4 | (Val & 0xF0) >> 4;
117 }
118 
119 void BPFMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
121  const MCSubtargetInfo &STI) const {
122  verifyInstructionPredicates(MI,
123  computeAvailableFeatures(STI.getFeatureBits()));
124 
125  unsigned Opcode = MI.getOpcode();
127  IsLittleEndian ? support::little : support::big);
128 
129  if (Opcode == BPF::LD_imm64 || Opcode == BPF::LD_pseudo) {
130  uint64_t Value = getBinaryCodeForInstr(MI, Fixups, STI);
131  OS << char(Value >> 56);
132  if (IsLittleEndian)
133  OS << char((Value >> 48) & 0xff);
134  else
135  OS << char(SwapBits((Value >> 48) & 0xff));
136  OSE.write<uint16_t>(0);
137  OSE.write<uint32_t>(Value & 0xffffFFFF);
138 
139  const MCOperand &MO = MI.getOperand(1);
140  uint64_t Imm = MO.isImm() ? MO.getImm() : 0;
141  OSE.write<uint8_t>(0);
142  OSE.write<uint8_t>(0);
143  OSE.write<uint16_t>(0);
144  OSE.write<uint32_t>(Imm >> 32);
145  } else {
146  // Get instruction encoding and emit it
147  uint64_t Value = getBinaryCodeForInstr(MI, Fixups, STI);
148  OS << char(Value >> 56);
149  if (IsLittleEndian)
150  OS << char((Value >> 48) & 0xff);
151  else
152  OS << char(SwapBits((Value >> 48) & 0xff));
153  OSE.write<uint16_t>((Value >> 32) & 0xffff);
154  OSE.write<uint32_t>(Value & 0xffffFFFF);
155  }
156 }
157 
158 // Encode BPF Memory Operand
159 uint64_t BPFMCCodeEmitter::getMemoryOpValue(const MCInst &MI, unsigned Op,
161  const MCSubtargetInfo &STI) const {
162  // For CMPXCHG instructions, output is implicitly in R0/W0,
163  // so memory operand starts from operand 0.
164  int MemOpStartIndex = 1, Opcode = MI.getOpcode();
165  if (Opcode == BPF::CMPXCHGW32 || Opcode == BPF::CMPXCHGD)
166  MemOpStartIndex = 0;
167 
168  uint64_t Encoding;
169  const MCOperand Op1 = MI.getOperand(MemOpStartIndex);
170  assert(Op1.isReg() && "First operand is not register.");
171  Encoding = MRI.getEncodingValue(Op1.getReg());
172  Encoding <<= 16;
173  MCOperand Op2 = MI.getOperand(MemOpStartIndex + 1);
174  assert(Op2.isImm() && "Second operand is not immediate.");
175  Encoding |= Op2.getImm() & 0xffff;
176  return Encoding;
177 }
178 
179 #define ENABLE_INSTR_PREDICATE_VERIFIER
180 #include "BPFGenMCCodeEmitter.inc"
BPFMCTargetDesc.h
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:100
llvm
Definition: AllocatorList.h:23
llvm::MCOperand::isReg
bool isReg() const
Definition: MCInst.h:60
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:71
MCCodeEmitter.h
llvm::MCFixup::create
static MCFixup create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, SMLoc Loc=SMLoc())
Definition: MCFixup.h:97
SwapBits
static uint8_t SwapBits(uint8_t Val)
Definition: BPFMCCodeEmitter.cpp:114
llvm::FeatureBitset
Container class for subtarget features.
Definition: SubtargetFeature.h:40
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:183
llvm::support::endian::Writer
Adapter to write values to a stream in a particular byte order.
Definition: EndianStream.h:51
llvm::support::little
@ little
Definition: Endian.h:27
MCInstrInfo.h
llvm::MCOperand::getImm
int64_t getImm() const
Definition: MCInst.h:79
MCInst.h
llvm::AArch64::Fixups
Fixups
Definition: AArch64FixupKinds.h:17
MCSubtargetInfo.h
llvm::MCSubtargetInfo::getFeatureBits
const FeatureBitset & getFeatureBits() const
Definition: MCSubtargetInfo.h:111
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:50
llvm::MCExpr::getKind
ExprKind getKind() const
Definition: MCExpr.h:81
llvm::MCOperand::isImm
bool isImm() const
Definition: MCInst.h:61
MCRegisterInfo.h
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::FK_PCRel_2
@ FK_PCRel_2
A two-byte pc relative fixup.
Definition: MCFixup.h:29
llvm::FK_PCRel_4
@ FK_PCRel_4
A four-byte pc relative fixup.
Definition: MCFixup.h:30
llvm::createBPFbeMCCodeEmitter
MCCodeEmitter * createBPFbeMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)
Definition: BPFMCCodeEmitter.cpp:81
llvm::createBPFMCCodeEmitter
MCCodeEmitter * createBPFMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)
Definition: BPFMCCodeEmitter.cpp:75
uint32_t
MCFixup.h
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition: MCRegisterInfo.h:135
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::MCInstrInfo
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:25
EndianStream.h
uint16_t
llvm::MCCodeEmitter
MCCodeEmitter - Generic instruction encoding interface.
Definition: MCCodeEmitter.h:21
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:314
llvm::FK_SecRel_8
@ FK_SecRel_8
A eight-byte section relative fixup.
Definition: MCFixup.h:43
llvm::MCOperand::getExpr
const MCExpr * getExpr() const
Definition: MCInst.h:113
llvm::MCOperand::isExpr
bool isExpr() const
Definition: MCInst.h:64
SmallVector.h
llvm::MCExpr::SymbolRef
@ SymbolRef
References to labels and assigned expressions.
Definition: MCExpr.h:40
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
llvm::MCOperand
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:35
Endian.h
MCExpr.h
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:75
llvm::Value
LLVM Value Representation.
Definition: Value.h:75
llvm::MCExpr
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
llvm::support::big
@ big
Definition: Endian.h:27
llvm::MCOperand::getReg
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:68