LLVM  15.0.0git
BPFMCCodeEmitter.cpp
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1 //===-- BPFMCCodeEmitter.cpp - Convert BPF code to machine code -----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the BPFMCCodeEmitter class.
10 //
11 //===----------------------------------------------------------------------===//
12 
14 #include "llvm/ADT/SmallVector.h"
15 #include "llvm/MC/MCCodeEmitter.h"
16 #include "llvm/MC/MCExpr.h"
17 #include "llvm/MC/MCFixup.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/MC/MCInstrInfo.h"
20 #include "llvm/MC/MCRegisterInfo.h"
22 #include "llvm/Support/Endian.h"
24 #include <cassert>
25 #include <cstdint>
26 
27 using namespace llvm;
28 
29 #define DEBUG_TYPE "mccodeemitter"
30 
31 namespace {
32 
33 class BPFMCCodeEmitter : public MCCodeEmitter {
34  const MCRegisterInfo &MRI;
35  bool IsLittleEndian;
36 
37 public:
38  BPFMCCodeEmitter(const MCInstrInfo &, const MCRegisterInfo &mri,
39  bool IsLittleEndian)
40  : MRI(mri), IsLittleEndian(IsLittleEndian) { }
41  BPFMCCodeEmitter(const BPFMCCodeEmitter &) = delete;
42  void operator=(const BPFMCCodeEmitter &) = delete;
43  ~BPFMCCodeEmitter() override = default;
44 
45  // getBinaryCodeForInstr - TableGen'erated function for getting the
46  // binary encoding for an instruction.
47  uint64_t getBinaryCodeForInstr(const MCInst &MI,
49  const MCSubtargetInfo &STI) const;
50 
51  // getMachineOpValue - Return binary encoding of operand. If the machin
52  // operand requires relocation, record the relocation and return zero.
53  unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,
55  const MCSubtargetInfo &STI) const;
56 
57  uint64_t getMemoryOpValue(const MCInst &MI, unsigned Op,
59  const MCSubtargetInfo &STI) const;
60 
61  void encodeInstruction(const MCInst &MI, raw_ostream &OS,
63  const MCSubtargetInfo &STI) const override;
64 };
65 
66 } // end anonymous namespace
67 
69  MCContext &Ctx) {
70  return new BPFMCCodeEmitter(MCII, *Ctx.getRegisterInfo(), true);
71 }
72 
74  MCContext &Ctx) {
75  return new BPFMCCodeEmitter(MCII, *Ctx.getRegisterInfo(), false);
76 }
77 
78 unsigned BPFMCCodeEmitter::getMachineOpValue(const MCInst &MI,
79  const MCOperand &MO,
81  const MCSubtargetInfo &STI) const {
82  if (MO.isReg())
83  return MRI.getEncodingValue(MO.getReg());
84  if (MO.isImm())
85  return static_cast<unsigned>(MO.getImm());
86 
87  assert(MO.isExpr());
88 
89  const MCExpr *Expr = MO.getExpr();
90 
91  assert(Expr->getKind() == MCExpr::SymbolRef);
92 
93  if (MI.getOpcode() == BPF::JAL)
94  // func call name
95  Fixups.push_back(MCFixup::create(0, Expr, FK_PCRel_4));
96  else if (MI.getOpcode() == BPF::LD_imm64)
97  Fixups.push_back(MCFixup::create(0, Expr, FK_SecRel_8));
98  else
99  // bb label
100  Fixups.push_back(MCFixup::create(0, Expr, FK_PCRel_2));
101 
102  return 0;
103 }
104 
105 static uint8_t SwapBits(uint8_t Val)
106 {
107  return (Val & 0x0F) << 4 | (Val & 0xF0) >> 4;
108 }
109 
110 void BPFMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
112  const MCSubtargetInfo &STI) const {
113  unsigned Opcode = MI.getOpcode();
115  IsLittleEndian ? support::little : support::big);
116 
117  if (Opcode == BPF::LD_imm64 || Opcode == BPF::LD_pseudo) {
118  uint64_t Value = getBinaryCodeForInstr(MI, Fixups, STI);
119  OS << char(Value >> 56);
120  if (IsLittleEndian)
121  OS << char((Value >> 48) & 0xff);
122  else
123  OS << char(SwapBits((Value >> 48) & 0xff));
124  OSE.write<uint16_t>(0);
125  OSE.write<uint32_t>(Value & 0xffffFFFF);
126 
127  const MCOperand &MO = MI.getOperand(1);
128  uint64_t Imm = MO.isImm() ? MO.getImm() : 0;
129  OSE.write<uint8_t>(0);
130  OSE.write<uint8_t>(0);
131  OSE.write<uint16_t>(0);
132  OSE.write<uint32_t>(Imm >> 32);
133  } else {
134  // Get instruction encoding and emit it
135  uint64_t Value = getBinaryCodeForInstr(MI, Fixups, STI);
136  OS << char(Value >> 56);
137  if (IsLittleEndian)
138  OS << char((Value >> 48) & 0xff);
139  else
140  OS << char(SwapBits((Value >> 48) & 0xff));
141  OSE.write<uint16_t>((Value >> 32) & 0xffff);
142  OSE.write<uint32_t>(Value & 0xffffFFFF);
143  }
144 }
145 
146 // Encode BPF Memory Operand
147 uint64_t BPFMCCodeEmitter::getMemoryOpValue(const MCInst &MI, unsigned Op,
149  const MCSubtargetInfo &STI) const {
150  // For CMPXCHG instructions, output is implicitly in R0/W0,
151  // so memory operand starts from operand 0.
152  int MemOpStartIndex = 1, Opcode = MI.getOpcode();
153  if (Opcode == BPF::CMPXCHGW32 || Opcode == BPF::CMPXCHGD)
154  MemOpStartIndex = 0;
155 
156  uint64_t Encoding;
157  const MCOperand Op1 = MI.getOperand(MemOpStartIndex);
158  assert(Op1.isReg() && "First operand is not register.");
159  Encoding = MRI.getEncodingValue(Op1.getReg());
160  Encoding <<= 16;
161  MCOperand Op2 = MI.getOperand(MemOpStartIndex + 1);
162  assert(Op2.isImm() && "Second operand is not immediate.");
163  Encoding |= Op2.getImm() & 0xffff;
164  return Encoding;
165 }
166 
167 #include "BPFGenMCCodeEmitter.inc"
BPFMCTargetDesc.h
llvm::createBPFbeMCCodeEmitter
MCCodeEmitter * createBPFbeMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)
Definition: BPFMCCodeEmitter.cpp:73
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:105
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::MCOperand::isReg
bool isReg() const
Definition: MCInst.h:61
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:76
llvm::MCContext::getRegisterInfo
const MCRegisterInfo * getRegisterInfo() const
Definition: MCContext.h:448
MCCodeEmitter.h
llvm::MCFixup::create
static MCFixup create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, SMLoc Loc=SMLoc())
Definition: MCFixup.h:87
SwapBits
static uint8_t SwapBits(uint8_t Val)
Definition: BPFMCCodeEmitter.cpp:105
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
llvm::support::endian::Writer
Adapter to write values to a stream in a particular byte order.
Definition: EndianStream.h:52
llvm::support::little
@ little
Definition: Endian.h:27
MCInstrInfo.h
llvm::MCOperand::getImm
int64_t getImm() const
Definition: MCInst.h:80
MCInst.h
llvm::AArch64::Fixups
Fixups
Definition: AArch64FixupKinds.h:17
MCSubtargetInfo.h
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:54
llvm::MCExpr::getKind
ExprKind getKind() const
Definition: MCExpr.h:81
llvm::MCOperand::isImm
bool isImm() const
Definition: MCInst.h:62
uint64_t
MCRegisterInfo.h
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::FK_PCRel_2
@ FK_PCRel_2
A two-byte pc relative fixup.
Definition: MCFixup.h:29
llvm::FK_PCRel_4
@ FK_PCRel_4
A four-byte pc relative fixup.
Definition: MCFixup.h:30
uint32_t
MCFixup.h
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition: MCRegisterInfo.h:135
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::createBPFMCCodeEmitter
MCCodeEmitter * createBPFMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)
Definition: BPFMCCodeEmitter.cpp:68
llvm::MCInstrInfo
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:26
EndianStream.h
uint16_t
llvm::MCCodeEmitter
MCCodeEmitter - Generic instruction encoding interface.
Definition: MCCodeEmitter.h:21
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:348
llvm::FK_SecRel_8
@ FK_SecRel_8
A eight-byte section relative fixup.
Definition: MCFixup.h:43
llvm::MCOperand::getExpr
const MCExpr * getExpr() const
Definition: MCInst.h:114
llvm::MCOperand::isExpr
bool isExpr() const
Definition: MCInst.h:65
llvm::RISCVMatInt::Imm
@ Imm
Definition: RISCVMatInt.h:23
SmallVector.h
llvm::MCExpr::SymbolRef
@ SymbolRef
References to labels and assigned expressions.
Definition: MCExpr.h:40
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
llvm::MCOperand
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:36
Endian.h
MCExpr.h
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:76
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::MCExpr
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
llvm::support::big
@ big
Definition: Endian.h:27
llvm::MCOperand::getReg
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:69