31 #define DEBUG_TYPE "mccodeemitter"
33 #define GET_INSTRMAP_INFO
34 #include "AVRGenInstrInfo.inc"
35 #undef GET_INSTRMAP_INFO
68 AVRMCCodeEmitter::loadStorePostEncoder(
const MCInst &
MI,
unsigned EncodedValue,
69 const MCSubtargetInfo &STI)
const {
71 assert(
MI.getOperand(0).isReg() &&
MI.getOperand(1).isReg() &&
72 "the load/store operands must be registers");
74 unsigned Opcode =
MI.getOpcode();
77 bool IsRegX =
MI.getOperand(0).getReg() == AVR::R27R26 ||
78 MI.getOperand(1).getReg() == AVR::R27R26;
80 bool IsPredec = Opcode == AVR::LDRdPtrPd || Opcode == AVR::STPtrPdRr;
81 bool IsPostinc = Opcode == AVR::LDRdPtrPi || Opcode == AVR::STPtrPiRr;
84 if (IsRegX || IsPredec || IsPostinc) {
85 EncodedValue |= (1 << 12);
91 template <AVR::Fixups Fixup>
93 AVRMCCodeEmitter::encodeRelCondBrTarget(
const MCInst &
MI,
unsigned OpNo,
94 SmallVectorImpl<MCFixup> &
Fixups,
95 const MCSubtargetInfo &STI)
const {
96 const MCOperand &MO =
MI.getOperand(OpNo);
108 auto target = MO.getImm();
113 unsigned AVRMCCodeEmitter::encodeLDSTPtrReg(
const MCInst &
MI,
unsigned OpNo,
114 SmallVectorImpl<MCFixup> &
Fixups,
115 const MCSubtargetInfo &STI)
const {
116 auto MO =
MI.getOperand(OpNo);
121 switch (MO.getReg()) {
137 unsigned AVRMCCodeEmitter::encodeMemri(
const MCInst &
MI,
unsigned OpNo,
138 SmallVectorImpl<MCFixup> &
Fixups,
139 const MCSubtargetInfo &STI)
const {
140 auto RegOp =
MI.getOperand(OpNo);
141 auto OffsetOp =
MI.getOperand(OpNo + 1);
143 assert(RegOp.isReg() &&
"Expected register operand");
147 switch (RegOp.getReg()) {
160 if (OffsetOp.isImm()) {
161 OffsetBits = OffsetOp.getImm();
162 }
else if (OffsetOp.isExpr()) {
170 return (RegBit << 6) | OffsetBits;
173 unsigned AVRMCCodeEmitter::encodeComplement(
const MCInst &
MI,
unsigned OpNo,
174 SmallVectorImpl<MCFixup> &
Fixups,
175 const MCSubtargetInfo &STI)
const {
177 assert(
MI.getOperand(OpNo).isImm());
179 auto Imm =
MI.getOperand(OpNo).getImm();
183 template <AVR::Fixups Fixup,
unsigned Offset>
184 unsigned AVRMCCodeEmitter::encodeImm(
const MCInst &
MI,
unsigned OpNo,
185 SmallVectorImpl<MCFixup> &
Fixups,
186 const MCSubtargetInfo &STI)
const {
187 auto MO =
MI.getOperand(OpNo);
190 if (isa<AVRMCExpr>(MO.getExpr())) {
195 return getExprOpValue(MO.getExpr(),
Fixups, STI);
209 unsigned AVRMCCodeEmitter::encodeCallTarget(
const MCInst &
MI,
unsigned OpNo,
210 SmallVectorImpl<MCFixup> &
Fixups,
211 const MCSubtargetInfo &STI)
const {
212 auto MO =
MI.getOperand(OpNo);
222 auto Target = MO.getImm();
227 unsigned AVRMCCodeEmitter::getExprOpValue(
const MCExpr *Expr,
228 SmallVectorImpl<MCFixup> &
Fixups,
229 const MCSubtargetInfo &STI)
const {
234 Expr =
static_cast<const MCBinaryExpr *
>(Expr)->getLHS();
235 Kind = Expr->getKind();
239 AVRMCExpr
const *AVRExpr = cast<AVRMCExpr>(Expr);
241 if (AVRExpr->evaluateAsConstant(Result)) {
254 unsigned AVRMCCodeEmitter::getMachineOpValue(
const MCInst &
MI,
256 SmallVectorImpl<MCFixup> &
Fixups,
257 const MCSubtargetInfo &STI)
const {
261 return static_cast<unsigned>(MO.getImm());
264 return static_cast<unsigned>(bit_cast<double>(MO.getDFPImm()));
269 return getExprOpValue(MO.getExpr(),
Fixups, STI);
272 void AVRMCCodeEmitter::emitInstruction(
uint64_t Val,
unsigned Size,
273 const MCSubtargetInfo &STI,
274 raw_ostream &OS)
const {
275 size_t WordCount = Size / 2;
277 for (int64_t
i = WordCount - 1;
i >= 0; --
i) {
283 void AVRMCCodeEmitter::encodeInstruction(
const MCInst &
MI, raw_ostream &OS,
284 SmallVectorImpl<MCFixup> &
Fixups,
285 const MCSubtargetInfo &STI)
const {
286 const MCInstrDesc &Desc = MCII.
get(
MI.getOpcode());
289 unsigned Size = Desc.getSize();
291 assert(Size > 0 &&
"Instruction size cannot be zero");
294 emitInstruction(BinaryOpCode, Size, STI, OS);
299 return new AVRMCCodeEmitter(MCII, Ctx);
302 #include "AVRGenMCCodeEmitter.inc"