LLVM  14.0.0git
Context.h
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1 //===---------------------------- Context.h ---------------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 ///
10 /// This file defines a class for holding ownership of various simulated
11 /// hardware units. A Context also provides a utility routine for constructing
12 /// a default out-of-order pipeline with fetch, dispatch, execute, and retire
13 /// stages.
14 ///
15 //===----------------------------------------------------------------------===//
16 
17 #ifndef LLVM_MCA_CONTEXT_H
18 #define LLVM_MCA_CONTEXT_H
19 
20 #include "llvm/MC/MCRegisterInfo.h"
24 #include "llvm/MCA/Pipeline.h"
25 #include "llvm/MCA/SourceMgr.h"
26 #include <memory>
27 
28 namespace llvm {
29 namespace mca {
30 
31 /// This is a convenience struct to hold the parameters necessary for creating
32 /// the pre-built "default" out-of-order pipeline.
34  PipelineOptions(unsigned UOPQSize, unsigned DecThr, unsigned DW, unsigned RFS,
35  unsigned LQS, unsigned SQS, bool NoAlias,
36  bool ShouldEnableBottleneckAnalysis = false)
37  : MicroOpQueueSize(UOPQSize), DecodersThroughput(DecThr),
39  StoreQueueSize(SQS), AssumeNoAlias(NoAlias),
40  EnableBottleneckAnalysis(ShouldEnableBottleneckAnalysis) {}
41  unsigned MicroOpQueueSize;
42  unsigned DecodersThroughput; // Instructions per cycle.
43  unsigned DispatchWidth;
44  unsigned RegisterFileSize;
45  unsigned LoadQueueSize;
46  unsigned StoreQueueSize;
49 };
50 
51 class Context {
53  const MCRegisterInfo &MRI;
54  const MCSubtargetInfo &STI;
55 
56 public:
57  Context(const MCRegisterInfo &R, const MCSubtargetInfo &S) : MRI(R), STI(S) {}
58  Context(const Context &C) = delete;
59  Context &operator=(const Context &C) = delete;
60 
61  const MCRegisterInfo &getMCRegisterInfo() const { return MRI; }
62  const MCSubtargetInfo &getMCSubtargetInfo() const { return STI; }
63 
64  void addHardwareUnit(std::unique_ptr<HardwareUnit> H) {
65  Hardware.push_back(std::move(H));
66  }
67 
68  /// Construct a basic pipeline for simulating an out-of-order pipeline.
69  /// This pipeline consists of Fetch, Dispatch, Execute, and Retire stages.
70  std::unique_ptr<Pipeline> createDefaultPipeline(const PipelineOptions &Opts,
72  CustomBehaviour &CB);
73 
74  /// Construct a basic pipeline for simulating an in-order pipeline.
75  /// This pipeline consists of Fetch, InOrderIssue, and Retire stages.
76  std::unique_ptr<Pipeline> createInOrderPipeline(const PipelineOptions &Opts,
78  CustomBehaviour &CB);
79 };
80 
81 } // namespace mca
82 } // namespace llvm
83 #endif // LLVM_MCA_CONTEXT_H
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
llvm::mca::PipelineOptions::StoreQueueSize
unsigned StoreQueueSize
Definition: Context.h:46
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1168
Pipeline.h
llvm::mca::PipelineOptions::MicroOpQueueSize
unsigned MicroOpQueueSize
Definition: Context.h:41
llvm::mca::PipelineOptions::LoadQueueSize
unsigned LoadQueueSize
Definition: Context.h:45
llvm::mca::Context::getMCRegisterInfo
const MCRegisterInfo & getMCRegisterInfo() const
Definition: Context.h:61
SourceMgr.h
llvm::mca::PipelineOptions::PipelineOptions
PipelineOptions(unsigned UOPQSize, unsigned DecThr, unsigned DW, unsigned RFS, unsigned LQS, unsigned SQS, bool NoAlias, bool ShouldEnableBottleneckAnalysis=false)
Definition: Context.h:34
llvm::mca::Context::Context
Context(const MCRegisterInfo &R, const MCSubtargetInfo &S)
Definition: Context.h:57
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::SrcMgr
SourceMgr SrcMgr
Definition: Error.cpp:24
llvm::mca::PipelineOptions
This is a convenience struct to hold the parameters necessary for creating the pre-built "default" ou...
Definition: Context.h:33
llvm::mca::PipelineOptions::RegisterFileSize
unsigned RegisterFileSize
Definition: Context.h:44
MCSubtargetInfo.h
CustomBehaviour.h
HardwareUnit.h
llvm::mca::Context
Definition: Context.h:51
llvm::mca::CustomBehaviour
Class which can be overriden by targets to enforce instruction dependencies and behaviours that aren'...
Definition: CustomBehaviour.h:56
move
compiles ldr LCPI1_0 ldr ldr mov lsr tst moveq r1 ldr LCPI1_1 and r0 bx lr It would be better to do something like to fold the shift into the conditional move
Definition: README.txt:546
MCRegisterInfo.h
llvm::mca::Context::createDefaultPipeline
std::unique_ptr< Pipeline > createDefaultPipeline(const PipelineOptions &Opts, SourceMgr &SrcMgr, CustomBehaviour &CB)
Construct a basic pipeline for simulating an out-of-order pipeline.
Definition: Context.cpp:32
llvm::mca::Context::operator=
Context & operator=(const Context &C)=delete
llvm::mca::Context::createInOrderPipeline
std::unique_ptr< Pipeline > createInOrderPipeline(const PipelineOptions &Opts, SourceMgr &SrcMgr, CustomBehaviour &CB)
Construct a basic pipeline for simulating an in-order pipeline.
Definition: Context.cpp:73
llvm::mca::PipelineOptions::AssumeNoAlias
bool AssumeNoAlias
Definition: Context.h:47
llvm::mca::PipelineOptions::DecodersThroughput
unsigned DecodersThroughput
Definition: Context.h:42
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition: MCRegisterInfo.h:135
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::mca::SourceMgr
Definition: SourceMgr.h:28
H
#define H(x, y, z)
Definition: MD5.cpp:58
llvm::mca::Context::addHardwareUnit
void addHardwareUnit(std::unique_ptr< HardwareUnit > H)
Definition: Context.h:64
llvm::mca::PipelineOptions::DispatchWidth
unsigned DispatchWidth
Definition: Context.h:43
llvm::mca::Context::getMCSubtargetInfo
const MCSubtargetInfo & getMCSubtargetInfo() const
Definition: Context.h:62
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:75
llvm::mca::PipelineOptions::EnableBottleneckAnalysis
bool EnableBottleneckAnalysis
Definition: Context.h:48