const MCRegisterInfo & getMCRegisterInfo() const
PipelineOptions(unsigned UOPQSize, unsigned DecThr, unsigned DW, unsigned RFS, unsigned LQS, unsigned SQS, bool NoAlias, bool ShouldEnableBottleneckAnalysis=false)
Context(const MCRegisterInfo &R, const MCSubtargetInfo &S)
std::unique_ptr< Pipeline > createDefaultPipeline(const PipelineOptions &Opts, SourceMgr &SrcMgr, CustomBehaviour &CB)
Construct a basic pipeline for simulating an out-of-order pipeline.
Context & operator=(const Context &C)=delete
std::unique_ptr< Pipeline > createInOrderPipeline(const PipelineOptions &Opts, SourceMgr &SrcMgr, CustomBehaviour &CB)
Construct a basic pipeline for simulating an in-order pipeline.
void addHardwareUnit(std::unique_ptr< HardwareUnit > H)
const MCSubtargetInfo & getMCSubtargetInfo() const