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HexagonMCTargetDesc.h
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1 //===-- HexagonMCTargetDesc.h - Hexagon Target Descriptions -----*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file provides Hexagon specific target descriptions.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCTARGETDESC_H
14 #define LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCTARGETDESC_H
15 
16 #include "llvm/MC/MCRegisterInfo.h"
18 #include <cstdint>
19 #include <string>
20 
21 #define Hexagon_POINTER_SIZE 4
22 
23 #define Hexagon_PointerSize (Hexagon_POINTER_SIZE)
24 #define Hexagon_PointerSize_Bits (Hexagon_POINTER_SIZE * 8)
25 #define Hexagon_WordSize Hexagon_PointerSize
26 #define Hexagon_WordSize_Bits Hexagon_PointerSize_Bits
27 
28 // allocframe saves LR and FP on stack before allocating
29 // a new stack frame. This takes 8 bytes.
30 #define HEXAGON_LRFP_SIZE 8
31 
32 // Normal instruction size (in bytes).
33 #define HEXAGON_INSTR_SIZE 4
34 
35 // Maximum number of words and instructions in a packet.
36 #define HEXAGON_PACKET_SIZE 4
37 #define HEXAGON_MAX_PACKET_SIZE (HEXAGON_PACKET_SIZE * HEXAGON_INSTR_SIZE)
38 // Minimum number of instructions in an end-loop packet.
39 #define HEXAGON_PACKET_INNER_SIZE 2
40 #define HEXAGON_PACKET_OUTER_SIZE 3
41 // Maximum number of instructions in a packet before shuffling,
42 // including a compound one or a duplex or an extender.
43 #define HEXAGON_PRESHUFFLE_PACKET_SIZE (HEXAGON_PACKET_SIZE + 3)
44 
45 // Name of the global offset table as defined by the Hexagon ABI
46 #define HEXAGON_GOT_SYM_NAME "_GLOBAL_OFFSET_TABLE_"
47 
48 namespace llvm {
49 
50 struct InstrStage;
51 class FeatureBitset;
52 class MCAsmBackend;
53 class MCCodeEmitter;
54 class MCContext;
55 class MCInstrInfo;
56 class MCObjectTargetWriter;
57 class MCRegisterInfo;
58 class MCSubtargetInfo;
59 class MCTargetOptions;
60 class Target;
61 class Triple;
62 class StringRef;
63 
64 extern cl::opt<bool> HexagonDisableCompound;
65 extern cl::opt<bool> HexagonDisableDuplex;
66 extern const InstrStage HexagonStages[];
67 
68 MCInstrInfo *createHexagonMCInstrInfo();
69 MCRegisterInfo *createHexagonMCRegisterInfo(StringRef TT);
70 
71 namespace Hexagon_MC {
73 
75  /// Create a Hexagon MCSubtargetInfo instance. This is exposed so Asm parser,
76  /// etc. do not need to go through TargetRegistry.
78  StringRef FS);
80  void addArchSubtarget(MCSubtargetInfo const *STI,
81  StringRef FS);
82  unsigned GetELFFlags(const MCSubtargetInfo &STI);
83 
85 }
86 
88  const MCRegisterInfo &MRI,
89  MCContext &MCT);
90 
92  const MCSubtargetInfo &STI,
93  const MCRegisterInfo &MRI,
94  const MCTargetOptions &Options);
95 
96 std::unique_ptr<MCObjectTargetWriter>
97 createHexagonELFObjectWriter(uint8_t OSABI, StringRef CPU);
98 
99 unsigned HexagonGetLastSlot();
100 unsigned HexagonConvertUnits(unsigned ItinUnits, unsigned *Lanes);
101 
102 } // End llvm namespace
103 
104 // Define symbolic names for Hexagon registers. This defines a mapping from
105 // register name to register number.
106 //
107 #define GET_REGINFO_ENUM
108 #include "HexagonGenRegisterInfo.inc"
109 
110 // Defines symbolic names for the Hexagon instructions.
111 //
112 #define GET_INSTRINFO_ENUM
113 #define GET_INSTRINFO_SCHED_ENUM
114 #include "HexagonGenInstrInfo.inc"
115 
116 #define GET_SUBTARGETINFO_ENUM
117 #include "HexagonGenSubtargetInfo.inc"
118 
119 #endif // LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCTARGETDESC_H
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
llvm::HexagonConvertUnits
unsigned HexagonConvertUnits(unsigned ItinUnits, unsigned *Lanes)
Definition: HexagonMCTargetDesc.cpp:150
llvm::HexagonDisableCompound
cl::opt< bool > HexagonDisableCompound
llvm::createHexagonMCCodeEmitter
MCCodeEmitter * createHexagonMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &MCT)
Definition: HexagonMCCodeEmitter.cpp:789
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:72
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:137
llvm::Hexagon_MC::GetELFFlags
unsigned GetELFFlags(const MCSubtargetInfo &STI)
Definition: HexagonMCTargetDesc.cpp:530
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:45
llvm::Hexagon_MC::addArchSubtarget
void addArchSubtarget(MCSubtargetInfo const *STI, StringRef FS)
Definition: HexagonMCTargetDesc.cpp:517
llvm::AMDGPU::Exp::Target
Target
Definition: SIDefines.h:732
llvm::FeatureBitset
Container class for subtarget features.
Definition: SubtargetFeature.h:40
llvm::Hexagon_MC::getArchSubtarget
const MCSubtargetInfo * getArchSubtarget(MCSubtargetInfo const *STI)
Definition: HexagonMCTargetDesc.cpp:411
CommandLine.h
llvm::MCAsmBackend
Generic interface to target specific assembler backends.
Definition: MCAsmBackend.h:36
llvm::HexagonDisableDuplex
cl::opt< bool > HexagonDisableDuplex
Options
const char LLVMTargetMachineRef LLVMPassBuilderOptionsRef Options
Definition: PassBuilderBindings.cpp:48
llvm::Hexagon_MC::GetVectRegRev
llvm::ArrayRef< MCPhysReg > GetVectRegRev()
Definition: HexagonMCTargetDesc.cpp:548
llvm::createHexagonMCInstrInfo
MCInstrInfo * createHexagonMCInstrInfo()
Definition: HexagonMCTargetDesc.cpp:280
llvm::createHexagonMCRegisterInfo
MCRegisterInfo * createHexagonMCRegisterInfo(StringRef TT)
llvm::X86AS::FS
@ FS
Definition: X86.h:188
MCRegisterInfo.h
llvm::HexagonGetLastSlot
unsigned HexagonGetLastSlot()
Definition: HexagonMCTargetDesc.cpp:148
llvm::MCTargetOptions
Definition: MCTargetOptions.h:36
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::HexagonStages
const InstrStage HexagonStages[]
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition: MCRegisterInfo.h:135
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::MCInstrInfo
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:25
llvm::MCCodeEmitter
MCCodeEmitter - Generic instruction encoding interface.
Definition: MCCodeEmitter.h:21
llvm::Hexagon_MC::createHexagonMCSubtargetInfo
MCSubtargetInfo * createHexagonMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS)
Create a Hexagon MCSubtargetInfo instance.
Definition: HexagonMCTargetDesc.cpp:476
llvm::Hexagon_MC::selectHexagonCPU
StringRef selectHexagonCPU(StringRef CPU)
Definition: HexagonMCTargetDesc.cpp:129
llvm::Hexagon_MC::completeHVXFeatures
FeatureBitset completeHVXFeatures(const FeatureBitset &FB)
Definition: HexagonMCTargetDesc.cpp:419
llvm::createHexagonAsmBackend
MCAsmBackend * createHexagonAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
Definition: HexagonAsmBackend.cpp:772
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:75
llvm::createHexagonELFObjectWriter
std::unique_ptr< MCObjectTargetWriter > createHexagonELFObjectWriter(uint8_t OSABI, StringRef CPU)
Definition: HexagonELFObjectWriter.cpp:301