LLVM 20.0.0git
HexagonMCTargetDesc.h
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1//===-- HexagonMCTargetDesc.h - Hexagon Target Descriptions -----*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file provides Hexagon specific target descriptions.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCTARGETDESC_H
14#define LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCTARGETDESC_H
15
18#include <cstdint>
19
20#define Hexagon_POINTER_SIZE 4
21
22#define Hexagon_PointerSize (Hexagon_POINTER_SIZE)
23#define Hexagon_PointerSize_Bits (Hexagon_POINTER_SIZE * 8)
24#define Hexagon_WordSize Hexagon_PointerSize
25#define Hexagon_WordSize_Bits Hexagon_PointerSize_Bits
26
27// allocframe saves LR and FP on stack before allocating
28// a new stack frame. This takes 8 bytes.
29#define HEXAGON_LRFP_SIZE 8
30
31// Normal instruction size (in bytes).
32#define HEXAGON_INSTR_SIZE 4
33
34// Maximum number of words and instructions in a packet.
35#define HEXAGON_PACKET_SIZE 4
36#define HEXAGON_MAX_PACKET_SIZE (HEXAGON_PACKET_SIZE * HEXAGON_INSTR_SIZE)
37// Minimum number of instructions in an end-loop packet.
38#define HEXAGON_PACKET_INNER_SIZE 2
39#define HEXAGON_PACKET_OUTER_SIZE 3
40// Maximum number of instructions in a packet before shuffling,
41// including a compound one or a duplex or an extender.
42#define HEXAGON_PRESHUFFLE_PACKET_SIZE (HEXAGON_PACKET_SIZE + 3)
43
44// Name of the global offset table as defined by the Hexagon ABI
45#define HEXAGON_GOT_SYM_NAME "_GLOBAL_OFFSET_TABLE_"
46
47namespace llvm {
48
49struct InstrStage;
50class FeatureBitset;
51class MCAsmBackend;
52class MCCodeEmitter;
53class MCContext;
54class MCInstrInfo;
55class MCObjectTargetWriter;
56class MCRegisterInfo;
57class MCSubtargetInfo;
58class MCTargetOptions;
59class Target;
60class Triple;
61class StringRef;
62
63extern cl::opt<bool> HexagonDisableCompound;
64extern cl::opt<bool> HexagonDisableDuplex;
65extern const InstrStage HexagonStages[];
66
67MCInstrInfo *createHexagonMCInstrInfo();
69
70namespace Hexagon_MC {
72
74 /// Create a Hexagon MCSubtargetInfo instance. This is exposed so Asm parser,
75 /// etc. do not need to go through TargetRegistry.
77 StringRef FS);
79 void addArchSubtarget(MCSubtargetInfo const *STI,
80 StringRef FS);
81 unsigned GetELFFlags(const MCSubtargetInfo &STI);
82
84
85 std::optional<unsigned> getHVXVersion(const FeatureBitset &Features);
86
87 unsigned getArchVersion(const FeatureBitset &Features);
88 } // namespace Hexagon_MC
89
91 MCContext &MCT);
92
94 const MCSubtargetInfo &STI,
95 const MCRegisterInfo &MRI,
97
98std::unique_ptr<MCObjectTargetWriter>
99createHexagonELFObjectWriter(uint8_t OSABI, StringRef CPU);
100
101unsigned HexagonGetLastSlot();
102unsigned HexagonConvertUnits(unsigned ItinUnits, unsigned *Lanes);
103
104} // End llvm namespace
105
106// Define symbolic names for Hexagon registers. This defines a mapping from
107// register name to register number.
108//
109#define GET_REGINFO_ENUM
110#include "HexagonGenRegisterInfo.inc"
111
112// Defines symbolic names for the Hexagon instructions.
113//
114#define GET_INSTRINFO_ENUM
115#define GET_INSTRINFO_SCHED_ENUM
116#define GET_INSTRINFO_MC_HELPER_DECLS
117#include "HexagonGenInstrInfo.inc"
118
119#define GET_SUBTARGETINFO_ENUM
120#include "HexagonGenSubtargetInfo.inc"
121
122#endif // LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCTARGETDESC_H
unsigned const MachineRegisterInfo * MRI
static LVOptions Options
Definition: LVOptions.cpp:25
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
Container class for subtarget features.
Generic interface to target specific assembler backends.
Definition: MCAsmBackend.h:42
MCCodeEmitter - Generic instruction encoding interface.
Definition: MCCodeEmitter.h:21
Context object for machine code objects.
Definition: MCContext.h:83
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:26
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Generic base class for all target subtargets.
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
Target - Wrapper for Target specific information.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
llvm::ArrayRef< MCPhysReg > GetVectRegRev()
unsigned getArchVersion(const FeatureBitset &Features)
unsigned GetELFFlags(const MCSubtargetInfo &STI)
std::optional< unsigned > getHVXVersion(const FeatureBitset &Features)
MCSubtargetInfo const * getArchSubtarget(MCSubtargetInfo const *STI)
StringRef selectHexagonCPU(StringRef CPU)
void addArchSubtarget(MCSubtargetInfo const *STI, StringRef FS)
FeatureBitset completeHVXFeatures(const FeatureBitset &FB)
MCSubtargetInfo * createHexagonMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS)
Create a Hexagon MCSubtargetInfo instance.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
unsigned HexagonConvertUnits(unsigned ItinUnits, unsigned *Lanes)
cl::opt< bool > HexagonDisableCompound
MCCodeEmitter * createHexagonMCCodeEmitter(const MCInstrInfo &MCII, MCContext &MCT)
MCRegisterInfo * createHexagonMCRegisterInfo(StringRef TT)
unsigned HexagonGetLastSlot()
std::unique_ptr< MCObjectTargetWriter > createHexagonELFObjectWriter(uint8_t OSABI, StringRef CPU)
MCAsmBackend * createHexagonAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
MCInstrInfo * createHexagonMCInstrInfo()
const InstrStage HexagonStages[]
cl::opt< bool > HexagonDisableDuplex