LLVM  14.0.0git
HexagonMCTargetDesc.cpp
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1 //===-- HexagonMCTargetDesc.cpp - Hexagon Target Descriptions -------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file provides Hexagon specific target descriptions.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "HexagonArch.h"
14 #include "HexagonTargetStreamer.h"
21 #include "llvm/ADT/StringExtras.h"
22 #include "llvm/ADT/StringRef.h"
23 #include "llvm/BinaryFormat/ELF.h"
24 #include "llvm/MC/MCAsmBackend.h"
25 #include "llvm/MC/MCCodeEmitter.h"
26 #include "llvm/MC/MCContext.h"
27 #include "llvm/MC/MCDwarf.h"
28 #include "llvm/MC/MCELFStreamer.h"
30 #include "llvm/MC/MCInstrInfo.h"
31 #include "llvm/MC/MCObjectWriter.h"
32 #include "llvm/MC/MCRegisterInfo.h"
33 #include "llvm/MC/MCStreamer.h"
38 #include <cassert>
39 #include <cstdint>
40 #include <mutex>
41 #include <new>
42 #include <string>
43 #include <unordered_map>
44 
45 using namespace llvm;
46 
47 #define GET_INSTRINFO_MC_DESC
48 #include "HexagonGenInstrInfo.inc"
49 
50 #define GET_SUBTARGETINFO_MC_DESC
51 #include "HexagonGenSubtargetInfo.inc"
52 
53 #define GET_REGINFO_MC_DESC
54 #include "HexagonGenRegisterInfo.inc"
55 
57  ("mno-compound",
58  cl::desc("Disable looking for compound instructions for Hexagon"));
59 
61  ("mno-pairing",
62  cl::desc("Disable looking for duplex instructions for Hexagon"));
63 
64 namespace { // These flags are to be deprecated
65 cl::opt<bool> MV5("mv5", cl::Hidden, cl::desc("Build for Hexagon V5"),
66  cl::init(false));
67 cl::opt<bool> MV55("mv55", cl::Hidden, cl::desc("Build for Hexagon V55"),
68  cl::init(false));
69 cl::opt<bool> MV60("mv60", cl::Hidden, cl::desc("Build for Hexagon V60"),
70  cl::init(false));
71 cl::opt<bool> MV62("mv62", cl::Hidden, cl::desc("Build for Hexagon V62"),
72  cl::init(false));
73 cl::opt<bool> MV65("mv65", cl::Hidden, cl::desc("Build for Hexagon V65"),
74  cl::init(false));
75 cl::opt<bool> MV66("mv66", cl::Hidden, cl::desc("Build for Hexagon V66"),
76  cl::init(false));
77 cl::opt<bool> MV67("mv67", cl::Hidden, cl::desc("Build for Hexagon V67"),
78  cl::init(false));
79 cl::opt<bool> MV67T("mv67t", cl::Hidden, cl::desc("Build for Hexagon V67T"),
80  cl::init(false));
81 cl::opt<bool> MV68("mv68", cl::Hidden, cl::desc("Build for Hexagon V68"),
82  cl::init(false));
83 
85  EnableHVX("mhvx",
86  cl::desc("Enable Hexagon Vector eXtensions"),
87  cl::values(
88  clEnumValN(Hexagon::ArchEnum::V60, "v60", "Build for HVX v60"),
89  clEnumValN(Hexagon::ArchEnum::V62, "v62", "Build for HVX v62"),
90  clEnumValN(Hexagon::ArchEnum::V65, "v65", "Build for HVX v65"),
91  clEnumValN(Hexagon::ArchEnum::V66, "v66", "Build for HVX v66"),
92  clEnumValN(Hexagon::ArchEnum::V67, "v67", "Build for HVX v67"),
93  clEnumValN(Hexagon::ArchEnum::V68, "v68", "Build for HVX v68"),
94  // Sentinel for no value specified.
96  // Sentinel for flag not present.
98 } // namespace
99 
100 static cl::opt<bool>
101  DisableHVX("mno-hvx", cl::Hidden,
102  cl::desc("Disable Hexagon Vector eXtensions"));
103 
104 
105 static StringRef DefaultArch = "hexagonv60";
106 
108  if (MV5)
109  return "hexagonv5";
110  if (MV55)
111  return "hexagonv55";
112  if (MV60)
113  return "hexagonv60";
114  if (MV62)
115  return "hexagonv62";
116  if (MV65)
117  return "hexagonv65";
118  if (MV66)
119  return "hexagonv66";
120  if (MV67)
121  return "hexagonv67";
122  if (MV67T)
123  return "hexagonv67t";
124  if (MV68)
125  return "hexagonv68";
126  return "";
127 }
128 
131  if (!ArchV.empty() && !CPU.empty()) {
132  // Tiny cores have a "t" suffix that is discarded when creating a secondary
133  // non-tiny subtarget. See: addArchSubtarget
134  std::pair<StringRef,StringRef> ArchP = ArchV.split('t');
135  std::pair<StringRef,StringRef> CPUP = CPU.split('t');
136  if (!ArchP.first.equals(CPUP.first))
137  report_fatal_error("conflicting architectures specified.");
138  return CPU;
139  }
140  if (ArchV.empty()) {
141  if (CPU.empty())
142  CPU = DefaultArch;
143  return CPU;
144  }
145  return ArchV;
146 }
147 
148 unsigned llvm::HexagonGetLastSlot() { return HexagonItinerariesV5FU::SLOT3; }
149 
150 unsigned llvm::HexagonConvertUnits(unsigned ItinUnits, unsigned *Lanes) {
151  enum {
152  CVI_NONE = 0,
153  CVI_XLANE = 1 << 0,
154  CVI_SHIFT = 1 << 1,
155  CVI_MPY0 = 1 << 2,
156  CVI_MPY1 = 1 << 3,
157  CVI_ZW = 1 << 4
158  };
159 
160  if (ItinUnits == HexagonItinerariesV62FU::CVI_ALL ||
161  ItinUnits == HexagonItinerariesV62FU::CVI_ALL_NOMEM)
162  return (*Lanes = 4, CVI_XLANE);
163  else if (ItinUnits & HexagonItinerariesV62FU::CVI_MPY01 &&
164  ItinUnits & HexagonItinerariesV62FU::CVI_XLSHF)
165  return (*Lanes = 2, CVI_XLANE | CVI_MPY0);
166  else if (ItinUnits & HexagonItinerariesV62FU::CVI_MPY01)
167  return (*Lanes = 2, CVI_MPY0);
168  else if (ItinUnits & HexagonItinerariesV62FU::CVI_XLSHF)
169  return (*Lanes = 2, CVI_XLANE);
170  else if (ItinUnits & HexagonItinerariesV62FU::CVI_XLANE &&
171  ItinUnits & HexagonItinerariesV62FU::CVI_SHIFT &&
172  ItinUnits & HexagonItinerariesV62FU::CVI_MPY0 &&
173  ItinUnits & HexagonItinerariesV62FU::CVI_MPY1)
174  return (*Lanes = 1, CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1);
175  else if (ItinUnits & HexagonItinerariesV62FU::CVI_XLANE &&
176  ItinUnits & HexagonItinerariesV62FU::CVI_SHIFT)
177  return (*Lanes = 1, CVI_XLANE | CVI_SHIFT);
178  else if (ItinUnits & HexagonItinerariesV62FU::CVI_MPY0 &&
179  ItinUnits & HexagonItinerariesV62FU::CVI_MPY1)
180  return (*Lanes = 1, CVI_MPY0 | CVI_MPY1);
181  else if (ItinUnits == HexagonItinerariesV62FU::CVI_ZW)
182  return (*Lanes = 1, CVI_ZW);
183  else if (ItinUnits == HexagonItinerariesV62FU::CVI_XLANE)
184  return (*Lanes = 1, CVI_XLANE);
185  else if (ItinUnits == HexagonItinerariesV62FU::CVI_SHIFT)
186  return (*Lanes = 1, CVI_SHIFT);
187 
188  return (*Lanes = 0, CVI_NONE);
189 }
190 
191 
192 namespace llvm {
193 namespace HexagonFUnits {
194 bool isSlot0Only(unsigned units) {
195  return HexagonItinerariesV62FU::SLOT0 == units;
196 }
197 } // namespace HexagonFUnits
198 } // namespace llvm
199 
200 namespace {
201 
202 class HexagonTargetAsmStreamer : public HexagonTargetStreamer {
203 public:
204  HexagonTargetAsmStreamer(MCStreamer &S,
206  bool isVerboseAsm,
207  MCInstPrinter &IP)
209 
210  void prettyPrintAsm(MCInstPrinter &InstPrinter, uint64_t Address,
211  const MCInst &Inst, const MCSubtargetInfo &STI,
212  raw_ostream &OS) override {
215  std::string Buffer;
216  {
217  raw_string_ostream TempStream(Buffer);
218  InstPrinter.printInst(&Inst, Address, "", STI, TempStream);
219  }
220  StringRef Contents(Buffer);
221  auto PacketBundle = Contents.rsplit('\n');
222  auto HeadTail = PacketBundle.first.split('\n');
223  StringRef Separator = "\n";
224  StringRef Indent = "\t";
225  OS << "\t{\n";
226  while (!HeadTail.first.empty()) {
227  StringRef InstTxt;
228  auto Duplex = HeadTail.first.split('\v');
229  if (!Duplex.second.empty()) {
230  OS << Indent << Duplex.first << Separator;
231  InstTxt = Duplex.second;
232  } else if (!HeadTail.first.trim().startswith("immext")) {
233  InstTxt = Duplex.first;
234  }
235  if (!InstTxt.empty())
236  OS << Indent << InstTxt << Separator;
237  HeadTail = HeadTail.second.split('\n');
238  }
239 
241  OS << "\n\t} :mem_noshuf" << PacketBundle.second;
242  else
243  OS << "\t}" << PacketBundle.second;
244  }
245 };
246 
247 class HexagonTargetELFStreamer : public HexagonTargetStreamer {
248 public:
249  MCELFStreamer &getStreamer() {
250  return static_cast<MCELFStreamer &>(Streamer);
251  }
252  HexagonTargetELFStreamer(MCStreamer &S, MCSubtargetInfo const &STI)
254  MCAssembler &MCA = getStreamer().getAssembler();
256  }
257 
258 
259  void emitCommonSymbolSorted(MCSymbol *Symbol, uint64_t Size,
260  unsigned ByteAlignment,
261  unsigned AccessSize) override {
262  HexagonMCELFStreamer &HexagonELFStreamer =
263  static_cast<HexagonMCELFStreamer &>(getStreamer());
264  HexagonELFStreamer.HexagonMCEmitCommonSymbol(Symbol, Size, ByteAlignment,
265  AccessSize);
266  }
267 
268  void emitLocalCommonSymbolSorted(MCSymbol *Symbol, uint64_t Size,
269  unsigned ByteAlignment,
270  unsigned AccessSize) override {
271  HexagonMCELFStreamer &HexagonELFStreamer =
272  static_cast<HexagonMCELFStreamer &>(getStreamer());
273  HexagonELFStreamer.HexagonMCEmitLocalCommonSymbol(
274  Symbol, Size, ByteAlignment, AccessSize);
275  }
276 };
277 
278 } // end anonymous namespace
279 
281  MCInstrInfo *X = new MCInstrInfo();
282  InitHexagonMCInstrInfo(X);
283  return X;
284 }
285 
288  InitHexagonMCRegisterInfo(X, Hexagon::R31);
289  return X;
290 }
291 
293  const Triple &TT,
294  const MCTargetOptions &Options) {
295  MCAsmInfo *MAI = new HexagonMCAsmInfo(TT);
296 
297  // VirtualFP = (R30 + #0).
299  nullptr, MRI.getDwarfRegNum(Hexagon::R30, true), 0);
300  MAI->addInitialFrameState(Inst);
301 
302  return MAI;
303 }
304 
306  unsigned SyntaxVariant,
307  const MCAsmInfo &MAI,
308  const MCInstrInfo &MII,
309  const MCRegisterInfo &MRI)
310 {
311  if (SyntaxVariant == 0)
312  return new HexagonInstPrinter(MAI, MII, MRI);
313  else
314  return nullptr;
315 }
316 
317 static MCTargetStreamer *
319  MCInstPrinter *IP, bool IsVerboseAsm) {
320  return new HexagonTargetAsmStreamer(S, OS, IsVerboseAsm, *IP);
321 }
322 
324  std::unique_ptr<MCAsmBackend> &&MAB,
325  std::unique_ptr<MCObjectWriter> &&OW,
326  std::unique_ptr<MCCodeEmitter> &&Emitter,
327  bool RelaxAll) {
329  std::move(Emitter));
330 }
331 
332 static MCTargetStreamer *
334  return new HexagonTargetELFStreamer(S, STI);
335 }
336 
338  if (STI->getFeatureBits()[F])
339  STI->ToggleFeature(F);
340 }
341 
343  return STI->getFeatureBits()[F];
344 }
345 
346 namespace {
347 std::string selectHexagonFS(StringRef CPU, StringRef FS) {
349  if (!FS.empty())
350  Result.push_back(FS);
351 
352  switch (EnableHVX) {
355  break;
357  Result.push_back("+hvxv60");
358  break;
360  Result.push_back("+hvxv62");
361  break;
363  Result.push_back("+hvxv65");
364  break;
366  Result.push_back("+hvxv66");
367  break;
369  Result.push_back("+hvxv67");
370  break;
372  Result.push_back("+hvxv68");
373  break;
375  Result.push_back(StringSwitch<StringRef>(CPU)
376  .Case("hexagonv60", "+hvxv60")
377  .Case("hexagonv62", "+hvxv62")
378  .Case("hexagonv65", "+hvxv65")
379  .Case("hexagonv66", "+hvxv66")
380  .Case("hexagonv67", "+hvxv67")
381  .Case("hexagonv67t", "+hvxv67")
382  .Case("hexagonv68", "+hvxv68"));
383  break;
384  }
386  // Sentinel if -mhvx isn't specified
387  break;
388  }
389  return join(Result.begin(), Result.end(), ",");
390 }
391 }
392 
393 static bool isCPUValid(const std::string &CPU) {
394  return Hexagon::CpuTable.find(CPU) != Hexagon::CpuTable.cend();
395 }
396 
397 namespace {
398 std::pair<std::string, std::string> selectCPUAndFS(StringRef CPU,
399  StringRef FS) {
400  std::pair<std::string, std::string> Result;
401  Result.first = std::string(Hexagon_MC::selectHexagonCPU(CPU));
402  Result.second = selectHexagonFS(Result.first, FS);
403  return Result;
404 }
405 std::mutex ArchSubtargetMutex;
406 std::unordered_map<std::string, std::unique_ptr<MCSubtargetInfo const>>
407  ArchSubtarget;
408 } // namespace
409 
410 MCSubtargetInfo const *
412  std::lock_guard<std::mutex> Lock(ArchSubtargetMutex);
413  auto Existing = ArchSubtarget.find(std::string(STI->getCPU()));
414  if (Existing == ArchSubtarget.end())
415  return nullptr;
416  return Existing->second.get();
417 }
418 
420  using namespace Hexagon;
421  // Make sure that +hvx-length turns hvx on, and that "hvx" alone
422  // turns on hvxvNN, corresponding to the existing ArchVNN.
423  FeatureBitset FB = S;
424  unsigned CpuArch = ArchV5;
425  for (unsigned F : {ArchV68, ArchV67, ArchV66, ArchV65, ArchV62, ArchV60,
426  ArchV55, ArchV5}) {
427  if (!FB.test(F))
428  continue;
429  CpuArch = F;
430  break;
431  }
432  bool UseHvx = false;
433  for (unsigned F : {ExtensionHVX, ExtensionHVX64B, ExtensionHVX128B}) {
434  if (!FB.test(F))
435  continue;
436  UseHvx = true;
437  break;
438  }
439  bool HasHvxVer = false;
440  for (unsigned F : {ExtensionHVXV60, ExtensionHVXV62, ExtensionHVXV65,
441  ExtensionHVXV66, ExtensionHVXV67, ExtensionHVXV68}) {
442  if (!FB.test(F))
443  continue;
444  HasHvxVer = true;
445  UseHvx = true;
446  break;
447  }
448 
449  if (!UseHvx || HasHvxVer)
450  return FB;
451 
452  // HasHvxVer is false, and UseHvx is true.
453  switch (CpuArch) {
454  case ArchV68:
455  FB.set(ExtensionHVXV68);
457  case ArchV67:
458  FB.set(ExtensionHVXV67);
460  case ArchV66:
461  FB.set(ExtensionHVXV66);
463  case ArchV65:
464  FB.set(ExtensionHVXV65);
466  case ArchV62:
467  FB.set(ExtensionHVXV62);
469  case ArchV60:
470  FB.set(ExtensionHVXV60);
471  break;
472  }
473  return FB;
474 }
475 
477  StringRef CPU,
478  StringRef FS) {
479  std::pair<std::string, std::string> Features = selectCPUAndFS(CPU, FS);
480  StringRef CPUName = Features.first;
481  StringRef ArchFS = Features.second;
482 
483  MCSubtargetInfo *X = createHexagonMCSubtargetInfoImpl(
484  TT, CPUName, /*TuneCPU*/ CPUName, ArchFS);
485  if (X != nullptr && (CPUName == "hexagonv67t"))
486  addArchSubtarget(X, ArchFS);
487 
488  if (CPU.equals("help"))
489  exit(0);
490 
491  if (!isCPUValid(CPUName.str())) {
492  errs() << "error: invalid CPU \"" << CPUName.str().c_str()
493  << "\" specified\n";
494  return nullptr;
495  }
496 
497  if (HexagonDisableDuplex) {
498  llvm::FeatureBitset Features = X->getFeatureBits();
499  X->setFeatureBits(Features.reset(Hexagon::FeatureDuplex));
500  }
501 
502  X->setFeatureBits(completeHVXFeatures(X->getFeatureBits()));
503 
504  // The Z-buffer instructions are grandfathered in for current
505  // architectures but omitted for new ones. Future instruction
506  // sets may introduce new/conflicting z-buffer instructions.
507  const bool ZRegOnDefault =
508  (CPUName == "hexagonv67") || (CPUName == "hexagonv66");
509  if (ZRegOnDefault) {
510  llvm::FeatureBitset Features = X->getFeatureBits();
511  X->setFeatureBits(Features.set(Hexagon::ExtensionZReg));
512  }
513 
514  return X;
515 }
516 
518  StringRef FS) {
519  assert(STI != nullptr);
520  if (STI->getCPU().contains("t")) {
521  auto ArchSTI = createHexagonMCSubtargetInfo(
522  STI->getTargetTriple(),
523  STI->getCPU().substr(0, STI->getCPU().size() - 1), FS);
524  std::lock_guard<std::mutex> Lock(ArchSubtargetMutex);
525  ArchSubtarget[std::string(STI->getCPU())] =
526  std::unique_ptr<MCSubtargetInfo const>(ArchSTI);
527  }
528 }
529 
531  static std::map<StringRef,unsigned> ElfFlags = {
532  {"hexagonv5", ELF::EF_HEXAGON_MACH_V5},
533  {"hexagonv55", ELF::EF_HEXAGON_MACH_V55},
534  {"hexagonv60", ELF::EF_HEXAGON_MACH_V60},
535  {"hexagonv62", ELF::EF_HEXAGON_MACH_V62},
536  {"hexagonv65", ELF::EF_HEXAGON_MACH_V65},
537  {"hexagonv66", ELF::EF_HEXAGON_MACH_V66},
538  {"hexagonv67", ELF::EF_HEXAGON_MACH_V67},
539  {"hexagonv67t", ELF::EF_HEXAGON_MACH_V67T},
540  {"hexagonv68", ELF::EF_HEXAGON_MACH_V68},
541  };
542 
543  auto F = ElfFlags.find(STI.getCPU());
544  assert(F != ElfFlags.end() && "Unrecognized Architecture");
545  return F->second;
546 }
547 
549  return makeArrayRef(VectRegRev);
550 }
551 
552 namespace {
553 class HexagonMCInstrAnalysis : public MCInstrAnalysis {
554 public:
555  HexagonMCInstrAnalysis(MCInstrInfo const *Info) : MCInstrAnalysis(Info) {}
556 
557  bool isUnconditionalBranch(MCInst const &Inst) const override {
558  //assert(!HexagonMCInstrInfo::isBundle(Inst));
560  }
561 
562  bool isConditionalBranch(MCInst const &Inst) const override {
563  //assert(!HexagonMCInstrInfo::isBundle(Inst));
565  }
566 
567  bool evaluateBranch(MCInst const &Inst, uint64_t Addr,
568  uint64_t Size, uint64_t &Target) const override {
569  if (!(isCall(Inst) || isUnconditionalBranch(Inst) ||
570  isConditionalBranch(Inst)))
571  return false;
572 
573  //assert(!HexagonMCInstrInfo::isBundle(Inst));
575  return false;
576  auto const &Extended(HexagonMCInstrInfo::getExtendableOperand(*Info, Inst));
577  assert(Extended.isExpr());
578  int64_t Value;
579  if(!Extended.getExpr()->evaluateAsAbsolute(Value))
580  return false;
581  Target = Value;
582  return true;
583  }
584 };
585 }
586 
588  return new HexagonMCInstrAnalysis(Info);
589 }
590 
591 // Force static initialization.
593  // Register the MC asm info.
595 
596  // Register the MC instruction info.
599 
600  // Register the MC register info.
603 
604  // Register the MC subtarget info.
607 
608  // Register the MC Code Emitter
611 
612  // Register the asm backend
615 
616 
617  // Register the MC instruction analyzer.
620 
621  // Register the obj streamer
624 
625  // Register the obj target streamer
628 
629  // Register the asm streamer
632 
633  // Register the MC Inst Printer
636 }
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
HexagonTargetInfo.h
HexagonMCTargetDesc.h
llvm::ELF::EF_HEXAGON_MACH_V65
@ EF_HEXAGON_MACH_V65
Definition: ELF.h:606
HexagonInstPrinter.h
MCDwarf.h
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
llvm::Hexagon::ArchEnum::NoArch
@ NoArch
llvm::HexagonConvertUnits
unsigned HexagonConvertUnits(unsigned ItinUnits, unsigned *Lanes)
Definition: HexagonMCTargetDesc.cpp:150
llvm::MCSymbol
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
llvm::StringRef::empty
LLVM_NODISCARD bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:153
llvm::Hexagon::ArchEnum::V65
@ V65
HexagonGetArchVariant
static StringRef HexagonGetArchVariant()
Definition: HexagonMCTargetDesc.cpp:107
createMCStreamer
static MCStreamer * createMCStreamer(Triple const &T, MCContext &Context, std::unique_ptr< MCAsmBackend > &&MAB, std::unique_ptr< MCObjectWriter > &&OW, std::unique_ptr< MCCodeEmitter > &&Emitter, bool RelaxAll)
Definition: HexagonMCTargetDesc.cpp:323
llvm::HexagonDisableCompound
cl::opt< bool > HexagonDisableCompound
llvm::createHexagonMCCodeEmitter
MCCodeEmitter * createHexagonMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &MCT)
Definition: HexagonMCCodeEmitter.cpp:789
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:72
StringRef.h
llvm::ELF::EF_HEXAGON_MACH_V66
@ EF_HEXAGON_MACH_V66
Definition: ELF.h:607
MCCodeEmitter.h
llvm::raw_string_ostream
A raw_ostream that writes to an std::string.
Definition: raw_ostream.h:623
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:137
llvm::MCAsmInfo
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1168
ErrorHandling.h
llvm::cl::ValueOptional
@ ValueOptional
Definition: CommandLine.h:136
llvm::Hexagon_MC::GetELFFlags
unsigned GetELFFlags(const MCSubtargetInfo &STI)
Definition: HexagonMCTargetDesc.cpp:530
llvm::TargetRegistry::RegisterAsmTargetStreamer
static void RegisterAsmTargetStreamer(Target &T, Target::AsmTargetStreamerCtorTy Fn)
Definition: TargetRegistry.h:972
llvm::TargetRegistry::RegisterMCInstrAnalysis
static void RegisterMCInstrAnalysis(Target &T, Target::MCInstrAnalysisCtorFnTy Fn)
RegisterMCInstrAnalysis - Register a MCInstrAnalysis implementation for the given target.
Definition: TargetRegistry.h:823
createHexagonMCInstPrinter
static MCInstPrinter * createHexagonMCInstPrinter(const Triple &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI)
Definition: HexagonMCTargetDesc.cpp:305
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:45
llvm::Hexagon_MC::addArchSubtarget
void addArchSubtarget(MCSubtargetInfo const *STI, StringRef FS)
Definition: HexagonMCTargetDesc.cpp:517
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:143
llvm::ELF::EF_HEXAGON_MACH_V67T
@ EF_HEXAGON_MACH_V67T
Definition: ELF.h:609
isCPUValid
static bool isCPUValid(const std::string &CPU)
Definition: HexagonMCTargetDesc.cpp:393
llvm::HexagonInstPrinter
Prints bundles as a newline separated list of individual instructions Duplexes are separated by a ver...
Definition: HexagonInstPrinter.h:25
T
#define T
Definition: Mips16ISelLowering.cpp:341
llvm::Hexagon::ArchEnum::V5
@ V5
llvm::FeatureBitset
Container class for subtarget features.
Definition: SubtargetFeature.h:40
llvm::errs
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
Definition: raw_ostream.cpp:892
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
HexagonArch.h
LLVM_ATTRIBUTE_UNUSED
#define LLVM_ATTRIBUTE_UNUSED
Definition: Compiler.h:188
llvm::TargetRegistry::RegisterMCInstPrinter
static void RegisterMCInstPrinter(Target &T, Target::MCInstPrinterCtorTy Fn)
RegisterMCInstPrinter - Register a MCInstPrinter implementation for the given target.
Definition: TargetRegistry.h:930
llvm::Hexagon_MC::getArchSubtarget
const MCSubtargetInfo * getArchSubtarget(MCSubtargetInfo const *STI)
Definition: HexagonMCTargetDesc.cpp:411
llvm::MCInstPrinter::printInst
virtual void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &OS)=0
Print the specified MCInst to the specified raw_ostream.
MCELFStreamer.h
F
#define F(x, y, z)
Definition: MD5.cpp:56
llvm::Hexagon::ArchEnum::V66
@ V66
llvm::FeatureBitset::set
FeatureBitset & set()
Definition: SubtargetFeature.h:59
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
llvm::Lock
static sys::Mutex Lock
Definition: NVPTXUtilities.cpp:39
llvm::StringRef::substr
LLVM_NODISCARD StringRef substr(size_t Start, size_t N=npos) const
Return a reference to the substring from [Start, Start + N).
Definition: StringRef.h:611
llvm::HexagonMCInstrInfo::isMemReorderDisabled
bool isMemReorderDisabled(MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:788
llvm::MCStreamer
Streaming machine code generation interface.
Definition: MCStreamer.h:197
llvm::ELF::EF_HEXAGON_MACH_V68
@ EF_HEXAGON_MACH_V68
Definition: ELF.h:610
llvm::createHexagonELFStreamer
MCStreamer * createHexagonELFStreamer(Triple const &TT, MCContext &Context, std::unique_ptr< MCAsmBackend > MAB, std::unique_ptr< MCObjectWriter > OW, std::unique_ptr< MCCodeEmitter > CE)
Definition: HexagonMCELFStreamer.cpp:153
ELF.h
llvm::MCELFStreamer
Definition: MCELFStreamer.h:24
MCAsmBackend.h
llvm::HexagonDisableDuplex
cl::opt< bool > HexagonDisableDuplex
HexagonMCInstrInfo.h
llvm::StringRef::split
LLVM_NODISCARD std::pair< StringRef, StringRef > split(char Separator) const
Split into two substrings around the first occurrence of a separator character.
Definition: StringRef.h:749
llvm::MCSubtargetInfo::getTargetTriple
const Triple & getTargetTriple() const
Definition: MCSubtargetInfo.h:107
MCContext.h
llvm::HexagonMCInstrInfo::isBundle
bool isBundle(MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:532
MCInstrInfo.h
llvm::ms_demangle::QualifierMangleMode::Result
@ Result
llvm::Hexagon::ArchEnum::Generic
@ Generic
IP
Definition: NVPTXLowerArgs.cpp:166
llvm::MCInstrAnalysis
Definition: MCInstrAnalysis.h:27
MCSubtargetInfo.h
llvm::MCSubtargetInfo::getFeatureBits
const FeatureBitset & getFeatureBits() const
Definition: MCSubtargetInfo.h:111
llvm::MCInstrAnalysis::isUnconditionalBranch
virtual bool isUnconditionalBranch(const MCInst &Inst) const
Definition: MCInstrAnalysis.h:45
llvm::HexagonTargetStreamer
Definition: HexagonTargetStreamer.h:15
llvm::StringRef::contains
LLVM_NODISCARD bool contains(StringRef Other) const
Return true if the given string is a substring of *this, and false otherwise.
Definition: StringRef.h:462
llvm::Hexagon::ArchEnum::V62
@ V62
llvm::report_fatal_error
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:140
Options
const char LLVMTargetMachineRef LLVMPassBuilderOptionsRef Options
Definition: PassBuilderBindings.cpp:48
llvm::ELF::EF_HEXAGON_MACH_V60
@ EF_HEXAGON_MACH_V60
Definition: ELF.h:604
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:53
llvm::MCTargetStreamer
Target specific streamer interface.
Definition: MCStreamer.h:91
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::StringRef::str
LLVM_NODISCARD std::string str() const
str - Get the contents as an std::string.
Definition: StringRef.h:245
llvm::RegisterMCAsmInfoFn
RegisterMCAsmInfoFn - Helper template for registering a target assembly info implementation.
Definition: TargetRegistry.h:1097
llvm::HexagonMCInstrInfo::bundleSize
size_t bundleSize(MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:116
llvm::MCCFIInstruction
Definition: MCDwarf.h:434
X
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
llvm::StringRef::equals
LLVM_NODISCARD bool equals(StringRef RHS) const
equals - Check for string equality, this is more efficient than compare() when the relative ordering ...
Definition: StringRef.h:187
llvm::MCSubtargetInfo::ToggleFeature
FeatureBitset ToggleFeature(uint64_t FB)
Toggle a feature and return the re-computed feature bits.
Definition: MCSubtargetInfo.cpp:240
llvm::Hexagon::ArchEnum::V67
@ V67
llvm::cl::opt< bool >
llvm::Hexagon_MC::GetVectRegRev
llvm::ArrayRef< MCPhysReg > GetVectRegRev()
Definition: HexagonMCTargetDesc.cpp:548
llvm::MCAssembler
Definition: MCAssembler.h:60
llvm::cl::values
ValuesClass values(OptsTy... Options)
Helper to build a ValuesClass by forwarding a variable number of arguments as an initializer list to ...
Definition: CommandLine.h:699
llvm::ELF::EF_HEXAGON_MACH_V67
@ EF_HEXAGON_MACH_V67
Definition: ELF.h:608
llvm::TargetRegistry::RegisterMCAsmBackend
static void RegisterMCAsmBackend(Target &T, Target::MCAsmBackendCtorTy Fn)
RegisterMCAsmBackend - Register a MCAsmBackend implementation for the given target.
Definition: TargetRegistry.h:877
HexagonMCELFStreamer.h
llvm::createHexagonMCInstrInfo
MCInstrInfo * createHexagonMCInstrInfo()
Definition: HexagonMCTargetDesc.cpp:280
llvm::MCInstrAnalysis::isConditionalBranch
virtual bool isConditionalBranch(const MCInst &Inst) const
Definition: MCInstrAnalysis.h:41
llvm::MCInstPrinter
This is an instance of a target assembly language printer that converts an MCInst to valid target ass...
Definition: MCInstPrinter.h:43
LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:132
Addr
uint64_t Addr
Definition: ELFObjHandler.cpp:80
createHexagonMCAsmInfo
static MCAsmInfo * createHexagonMCAsmInfo(const MCRegisterInfo &MRI, const Triple &TT, const MCTargetOptions &Options)
Definition: HexagonMCTargetDesc.cpp:292
llvm::createHexagonMCRegisterInfo
MCRegisterInfo * createHexagonMCRegisterInfo(StringRef TT)
move
compiles ldr LCPI1_0 ldr ldr mov lsr tst moveq r1 ldr LCPI1_1 and r0 bx lr It would be better to do something like to fold the shift into the conditional move
Definition: README.txt:546
checkFeature
static bool LLVM_ATTRIBUTE_UNUSED checkFeature(MCSubtargetInfo *STI, uint64_t F)
Definition: HexagonMCTargetDesc.cpp:342
llvm::MCSubtargetInfo::getCPU
StringRef getCPU() const
Definition: MCSubtargetInfo.h:108
llvm::X86AS::FS
@ FS
Definition: X86.h:188
StringExtras.h
llvm::TargetRegistry::RegisterObjectTargetStreamer
static void RegisterObjectTargetStreamer(Target &T, Target::ObjectTargetStreamerCtorTy Fn)
Definition: TargetRegistry.h:978
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:443
MCRegisterInfo.h
llvm::HexagonGetLastSlot
unsigned HexagonGetLastSlot()
Definition: HexagonMCTargetDesc.cpp:148
llvm::MCAssembler::setELFHeaderEFlags
void setELFHeaderEFlags(unsigned Flags)
Definition: MCAssembler.h:263
llvm::formatted_raw_ostream
formatted_raw_ostream - A raw_ostream that wraps another one and keeps track of line and column posit...
Definition: FormattedStream.h:30
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::Hexagon::ArchEnum::V55
@ V55
llvm::MCCFIInstruction::cfiDefCfa
static MCCFIInstruction cfiDefCfa(MCSymbol *L, unsigned Register, int Offset)
.cfi_def_cfa defines a rule for computing CFA as: take address from Register and add Offset to it.
Definition: MCDwarf.h:488
llvm::MCAsmInfo::addInitialFrameState
void addInitialFrameState(const MCCFIInstruction &Inst)
Definition: MCAsmInfo.cpp:86
llvm::TargetRegistry::RegisterMCSubtargetInfo
static void RegisterMCSubtargetInfo(Target &T, Target::MCSubtargetInfoCtorFnTy Fn)
RegisterMCSubtargetInfo - Register a MCSubtargetInfo implementation for the given target.
Definition: TargetRegistry.h:850
llvm::MCTargetOptions
Definition: MCTargetOptions.h:36
llvm::getTheHexagonTarget
Target & getTheHexagonTarget()
Definition: HexagonTargetInfo.cpp:13
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
MCInstrAnalysis.h
llvm::Hexagon::CpuTable
static const std::map< std::string, ArchEnum > CpuTable
Definition: HexagonDepArch.h:38
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
clEnumValN
#define clEnumValN(ENUMVAL, FLAGNAME, DESC)
Definition: CommandLine.h:674
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
llvm::HexagonMCAsmInfo
Definition: HexagonMCAsmInfo.h:21
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition: MCRegisterInfo.h:135
LLVM_FALLTHROUGH
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:273
llvm::FeatureBitset::reset
constexpr FeatureBitset & reset(unsigned I)
Definition: SubtargetFeature.h:71
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
isUnconditionalBranch
static bool isUnconditionalBranch(Instruction *Term)
Definition: ADCE.cpp:211
llvm::HexagonMCELFStreamer
Definition: HexagonMCELFStreamer.h:20
llvm::ELF::EF_HEXAGON_MACH_V62
@ EF_HEXAGON_MACH_V62
Definition: ELF.h:605
llvm::HexagonFUnits::isSlot0Only
bool isSlot0Only(unsigned units)
Definition: HexagonMCTargetDesc.cpp:194
MCObjectWriter.h
llvm::TargetRegistry::RegisterMCInstrInfo
static void RegisterMCInstrInfo(Target &T, Target::MCInstrInfoCtorFnTy Fn)
RegisterMCInstrInfo - Register a MCInstrInfo implementation for the given target.
Definition: TargetRegistry.h:817
llvm::TargetRegistry::RegisterMCCodeEmitter
static void RegisterMCCodeEmitter(Target &T, Target::MCCodeEmitterCtorTy Fn)
RegisterMCCodeEmitter - Register a MCCodeEmitter implementation for the given target.
Definition: TargetRegistry.h:943
llvm::MCInstrInfo
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:25
LLVMInitializeHexagonTargetMC
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeHexagonTargetMC()
Definition: HexagonMCTargetDesc.cpp:592
llvm::TargetRegistry::RegisterMCRegInfo
static void RegisterMCRegInfo(Target &T, Target::MCRegInfoCtorFnTy Fn)
RegisterMCRegInfo - Register a MCRegisterInfo implementation for the given target.
Definition: TargetRegistry.h:837
DisableHVX
static cl::opt< bool > DisableHVX("mno-hvx", cl::Hidden, cl::desc("Disable Hexagon Vector eXtensions"))
llvm::TargetRegistry::RegisterELFStreamer
static void RegisterELFStreamer(Target &T, Target::ELFStreamerCtorTy Fn)
Definition: TargetRegistry.h:955
llvm::TargetStackID::Value
Value
Definition: TargetFrameLowering.h:27
llvm::HexagonMCInstrInfo::getExtendableOperand
const MCOperand & getExtendableOperand(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:316
llvm::LCOMM::ByteAlignment
@ ByteAlignment
Definition: MCAsmInfo.h:50
llvm::makeArrayRef
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
Definition: ArrayRef.h:476
llvm::ARMBuildAttrs::Symbol
@ Symbol
Definition: ARMBuildAttributes.h:79
llvm::Hexagon_MC::createHexagonMCSubtargetInfo
MCSubtargetInfo * createHexagonMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS)
Create a Hexagon MCSubtargetInfo instance.
Definition: HexagonMCTargetDesc.cpp:476
createHexagonMCInstrAnalysis
static MCInstrAnalysis * createHexagonMCInstrAnalysis(const MCInstrInfo *Info)
Definition: HexagonMCTargetDesc.cpp:587
llvm::FeatureBitset::test
constexpr bool test(unsigned I) const
Definition: SubtargetFeature.h:90
llvm::Hexagon_MC::selectHexagonCPU
StringRef selectHexagonCPU(StringRef CPU)
Definition: HexagonMCTargetDesc.cpp:129
createMCAsmTargetStreamer
static MCTargetStreamer * createMCAsmTargetStreamer(MCStreamer &S, formatted_raw_ostream &OS, MCInstPrinter *IP, bool IsVerboseAsm)
Definition: HexagonMCTargetDesc.cpp:318
clearFeature
static void LLVM_ATTRIBUTE_UNUSED clearFeature(MCSubtargetInfo *STI, uint64_t F)
Definition: HexagonMCTargetDesc.cpp:337
DefaultArch
static StringRef DefaultArch
Definition: HexagonMCTargetDesc.cpp:105
exit
declare void exit(i32) noreturn nounwind This compiles into
Definition: README.txt:1072
MCStreamer.h
llvm::Hexagon::ArchEnum::V68
@ V68
createHexagonObjectTargetStreamer
static MCTargetStreamer * createHexagonObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI)
Definition: HexagonMCTargetDesc.cpp:333
HexagonMCAsmInfo.h
llvm::Hexagon::ArchEnum::V60
@ V60
llvm::ELF::EF_HEXAGON_MACH_V55
@ EF_HEXAGON_MACH_V55
Definition: ELF.h:603
llvm::StringSwitch
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:42
llvm::Hexagon_MC::completeHVXFeatures
FeatureBitset completeHVXFeatures(const FeatureBitset &FB)
Definition: HexagonMCTargetDesc.cpp:419
llvm::HexagonMCELFStreamer::HexagonMCEmitLocalCommonSymbol
void HexagonMCEmitLocalCommonSymbol(MCSymbol *Symbol, uint64_t Size, unsigned ByteAlignment, unsigned AccessSize)
Definition: HexagonMCELFStreamer.cpp:140
llvm::cl::desc
Definition: CommandLine.h:414
raw_ostream.h
HEXAGON_PACKET_SIZE
#define HEXAGON_PACKET_SIZE
Definition: HexagonMCTargetDesc.h:36
llvm::ELF::EF_HEXAGON_MACH_V5
@ EF_HEXAGON_MACH_V5
Definition: ELF.h:602
llvm::StringRef::size
LLVM_NODISCARD size_t size() const
size - Get the string size.
Definition: StringRef.h:157
TargetRegistry.h
llvm::createHexagonAsmBackend
MCAsmBackend * createHexagonAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
Definition: HexagonAsmBackend.cpp:772
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:75
llvm::Value
LLVM Value Representation.
Definition: Value.h:75
HexagonTargetStreamer.h
llvm::HexagonMCELFStreamer::HexagonMCEmitCommonSymbol
void HexagonMCEmitCommonSymbol(MCSymbol *Symbol, uint64_t Size, unsigned ByteAlignment, unsigned AccessSize)
Definition: HexagonMCELFStreamer.cpp:88
llvm::HexagonMCInstrInfo::isExtendable
bool isExtendable(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:613