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HexagonMCTargetDesc.cpp
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1 //===-- HexagonMCTargetDesc.cpp - Hexagon Target Descriptions -------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file provides Hexagon specific target descriptions.
10 //
11 //===----------------------------------------------------------------------===//
12 
14 #include "HexagonDepArch.h"
15 #include "HexagonTargetStreamer.h"
21 #include "llvm/ADT/StringExtras.h"
22 #include "llvm/ADT/StringRef.h"
23 #include "llvm/BinaryFormat/ELF.h"
24 #include "llvm/MC/MCAsmBackend.h"
25 #include "llvm/MC/MCAssembler.h"
26 #include "llvm/MC/MCCodeEmitter.h"
27 #include "llvm/MC/MCContext.h"
28 #include "llvm/MC/MCDwarf.h"
29 #include "llvm/MC/MCELFStreamer.h"
31 #include "llvm/MC/MCInstrInfo.h"
32 #include "llvm/MC/MCObjectWriter.h"
33 #include "llvm/MC/MCRegisterInfo.h"
34 #include "llvm/MC/MCStreamer.h"
36 #include "llvm/MC/TargetRegistry.h"
39 #include <cassert>
40 #include <cstdint>
41 #include <mutex>
42 #include <new>
43 #include <string>
44 #include <unordered_map>
45 
46 using namespace llvm;
47 
48 #define GET_INSTRINFO_MC_DESC
49 #define ENABLE_INSTR_PREDICATE_VERIFIER
50 #include "HexagonGenInstrInfo.inc"
51 
52 #define GET_SUBTARGETINFO_MC_DESC
53 #include "HexagonGenSubtargetInfo.inc"
54 
55 #define GET_REGINFO_MC_DESC
56 #include "HexagonGenRegisterInfo.inc"
57 
59  ("mno-compound",
60  cl::desc("Disable looking for compound instructions for Hexagon"));
61 
63  ("mno-pairing",
64  cl::desc("Disable looking for duplex instructions for Hexagon"));
65 
66 namespace { // These flags are to be deprecated
67 cl::opt<bool> MV5("mv5", cl::Hidden, cl::desc("Build for Hexagon V5"),
68  cl::init(false));
69 cl::opt<bool> MV55("mv55", cl::Hidden, cl::desc("Build for Hexagon V55"),
70  cl::init(false));
71 cl::opt<bool> MV60("mv60", cl::Hidden, cl::desc("Build for Hexagon V60"),
72  cl::init(false));
73 cl::opt<bool> MV62("mv62", cl::Hidden, cl::desc("Build for Hexagon V62"),
74  cl::init(false));
75 cl::opt<bool> MV65("mv65", cl::Hidden, cl::desc("Build for Hexagon V65"),
76  cl::init(false));
77 cl::opt<bool> MV66("mv66", cl::Hidden, cl::desc("Build for Hexagon V66"),
78  cl::init(false));
79 cl::opt<bool> MV67("mv67", cl::Hidden, cl::desc("Build for Hexagon V67"),
80  cl::init(false));
81 cl::opt<bool> MV67T("mv67t", cl::Hidden, cl::desc("Build for Hexagon V67T"),
82  cl::init(false));
83 cl::opt<bool> MV68("mv68", cl::Hidden, cl::desc("Build for Hexagon V68"),
84  cl::init(false));
85 cl::opt<bool> MV69("mv69", cl::Hidden, cl::desc("Build for Hexagon V69"),
86  cl::init(false));
87 
89  EnableHVX("mhvx",
90  cl::desc("Enable Hexagon Vector eXtensions"),
91  cl::values(
92  clEnumValN(Hexagon::ArchEnum::V60, "v60", "Build for HVX v60"),
93  clEnumValN(Hexagon::ArchEnum::V62, "v62", "Build for HVX v62"),
94  clEnumValN(Hexagon::ArchEnum::V65, "v65", "Build for HVX v65"),
95  clEnumValN(Hexagon::ArchEnum::V66, "v66", "Build for HVX v66"),
96  clEnumValN(Hexagon::ArchEnum::V67, "v67", "Build for HVX v67"),
97  clEnumValN(Hexagon::ArchEnum::V68, "v68", "Build for HVX v68"),
98  clEnumValN(Hexagon::ArchEnum::V69, "v69", "Build for HVX v69"),
99  // Sentinel for no value specified.
101  // Sentinel for flag not present.
103 } // namespace
104 
105 static cl::opt<bool>
106  DisableHVX("mno-hvx", cl::Hidden,
107  cl::desc("Disable Hexagon Vector eXtensions"));
108 
109 static cl::opt<bool>
110  EnableHvxIeeeFp("mhvx-ieee-fp", cl::Hidden,
111  cl::desc("Enable HVX IEEE floating point extensions"));
113  ("mcabac", cl::desc("tbd"), cl::init(false));
114 
115 static StringRef DefaultArch = "hexagonv60";
116 
118  if (MV5)
119  return "hexagonv5";
120  if (MV55)
121  return "hexagonv55";
122  if (MV60)
123  return "hexagonv60";
124  if (MV62)
125  return "hexagonv62";
126  if (MV65)
127  return "hexagonv65";
128  if (MV66)
129  return "hexagonv66";
130  if (MV67)
131  return "hexagonv67";
132  if (MV67T)
133  return "hexagonv67t";
134  if (MV68)
135  return "hexagonv68";
136  if (MV69)
137  return "hexagonv69";
138  return "";
139 }
140 
143  if (!ArchV.empty() && !CPU.empty()) {
144  // Tiny cores have a "t" suffix that is discarded when creating a secondary
145  // non-tiny subtarget. See: addArchSubtarget
146  std::pair<StringRef,StringRef> ArchP = ArchV.split('t');
147  std::pair<StringRef,StringRef> CPUP = CPU.split('t');
148  if (!ArchP.first.equals(CPUP.first))
149  report_fatal_error("conflicting architectures specified.");
150  return CPU;
151  }
152  if (ArchV.empty()) {
153  if (CPU.empty())
154  CPU = DefaultArch;
155  return CPU;
156  }
157  return ArchV;
158 }
159 
160 unsigned llvm::HexagonGetLastSlot() { return HexagonItinerariesV5FU::SLOT3; }
161 
162 unsigned llvm::HexagonConvertUnits(unsigned ItinUnits, unsigned *Lanes) {
163  enum {
164  CVI_NONE = 0,
165  CVI_XLANE = 1 << 0,
166  CVI_SHIFT = 1 << 1,
167  CVI_MPY0 = 1 << 2,
168  CVI_MPY1 = 1 << 3,
169  CVI_ZW = 1 << 4
170  };
171 
172  if (ItinUnits == HexagonItinerariesV62FU::CVI_ALL ||
173  ItinUnits == HexagonItinerariesV62FU::CVI_ALL_NOMEM)
174  return (*Lanes = 4, CVI_XLANE);
175  else if (ItinUnits & HexagonItinerariesV62FU::CVI_MPY01 &&
176  ItinUnits & HexagonItinerariesV62FU::CVI_XLSHF)
177  return (*Lanes = 2, CVI_XLANE | CVI_MPY0);
178  else if (ItinUnits & HexagonItinerariesV62FU::CVI_MPY01)
179  return (*Lanes = 2, CVI_MPY0);
180  else if (ItinUnits & HexagonItinerariesV62FU::CVI_XLSHF)
181  return (*Lanes = 2, CVI_XLANE);
182  else if (ItinUnits & HexagonItinerariesV62FU::CVI_XLANE &&
183  ItinUnits & HexagonItinerariesV62FU::CVI_SHIFT &&
184  ItinUnits & HexagonItinerariesV62FU::CVI_MPY0 &&
185  ItinUnits & HexagonItinerariesV62FU::CVI_MPY1)
186  return (*Lanes = 1, CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1);
187  else if (ItinUnits & HexagonItinerariesV62FU::CVI_XLANE &&
188  ItinUnits & HexagonItinerariesV62FU::CVI_SHIFT)
189  return (*Lanes = 1, CVI_XLANE | CVI_SHIFT);
190  else if (ItinUnits & HexagonItinerariesV62FU::CVI_MPY0 &&
191  ItinUnits & HexagonItinerariesV62FU::CVI_MPY1)
192  return (*Lanes = 1, CVI_MPY0 | CVI_MPY1);
193  else if (ItinUnits == HexagonItinerariesV62FU::CVI_ZW)
194  return (*Lanes = 1, CVI_ZW);
195  else if (ItinUnits == HexagonItinerariesV62FU::CVI_XLANE)
196  return (*Lanes = 1, CVI_XLANE);
197  else if (ItinUnits == HexagonItinerariesV62FU::CVI_SHIFT)
198  return (*Lanes = 1, CVI_SHIFT);
199 
200  return (*Lanes = 0, CVI_NONE);
201 }
202 
203 
204 namespace llvm {
205 namespace HexagonFUnits {
206 bool isSlot0Only(unsigned units) {
207  return HexagonItinerariesV62FU::SLOT0 == units;
208 }
209 } // namespace HexagonFUnits
210 } // namespace llvm
211 
212 namespace {
213 
214 class HexagonTargetAsmStreamer : public HexagonTargetStreamer {
215 public:
216  HexagonTargetAsmStreamer(MCStreamer &S,
218  bool isVerboseAsm,
219  MCInstPrinter &IP)
221 
222  void prettyPrintAsm(MCInstPrinter &InstPrinter, uint64_t Address,
223  const MCInst &Inst, const MCSubtargetInfo &STI,
224  raw_ostream &OS) override {
227  std::string Buffer;
228  {
229  raw_string_ostream TempStream(Buffer);
230  InstPrinter.printInst(&Inst, Address, "", STI, TempStream);
231  }
232  StringRef Contents(Buffer);
233  auto PacketBundle = Contents.rsplit('\n');
234  auto HeadTail = PacketBundle.first.split('\n');
235  StringRef Separator = "\n";
236  StringRef Indent = "\t";
237  OS << "\t{\n";
238  while (!HeadTail.first.empty()) {
239  StringRef InstTxt;
240  auto Duplex = HeadTail.first.split('\v');
241  if (!Duplex.second.empty()) {
242  OS << Indent << Duplex.first << Separator;
243  InstTxt = Duplex.second;
244  } else if (!HeadTail.first.trim().startswith("immext")) {
245  InstTxt = Duplex.first;
246  }
247  if (!InstTxt.empty())
248  OS << Indent << InstTxt << Separator;
249  HeadTail = HeadTail.second.split('\n');
250  }
251 
253  OS << "\n\t} :mem_noshuf" << PacketBundle.second;
254  else
255  OS << "\t}" << PacketBundle.second;
256  }
257 };
258 
259 class HexagonTargetELFStreamer : public HexagonTargetStreamer {
260 public:
261  MCELFStreamer &getStreamer() {
262  return static_cast<MCELFStreamer &>(Streamer);
263  }
264  HexagonTargetELFStreamer(MCStreamer &S, MCSubtargetInfo const &STI)
266  MCAssembler &MCA = getStreamer().getAssembler();
268  }
269 
270 
271  void emitCommonSymbolSorted(MCSymbol *Symbol, uint64_t Size,
272  unsigned ByteAlignment,
273  unsigned AccessSize) override {
274  HexagonMCELFStreamer &HexagonELFStreamer =
275  static_cast<HexagonMCELFStreamer &>(getStreamer());
276  HexagonELFStreamer.HexagonMCEmitCommonSymbol(Symbol, Size, ByteAlignment,
277  AccessSize);
278  }
279 
280  void emitLocalCommonSymbolSorted(MCSymbol *Symbol, uint64_t Size,
281  unsigned ByteAlignment,
282  unsigned AccessSize) override {
283  HexagonMCELFStreamer &HexagonELFStreamer =
284  static_cast<HexagonMCELFStreamer &>(getStreamer());
285  HexagonELFStreamer.HexagonMCEmitLocalCommonSymbol(
286  Symbol, Size, ByteAlignment, AccessSize);
287  }
288 };
289 
290 } // end anonymous namespace
291 
293  MCInstrInfo *X = new MCInstrInfo();
294  InitHexagonMCInstrInfo(X);
295  return X;
296 }
297 
300  InitHexagonMCRegisterInfo(X, Hexagon::R31);
301  return X;
302 }
303 
305  const Triple &TT,
306  const MCTargetOptions &Options) {
307  MCAsmInfo *MAI = new HexagonMCAsmInfo(TT);
308 
309  // VirtualFP = (R30 + #0).
311  nullptr, MRI.getDwarfRegNum(Hexagon::R30, true), 0);
312  MAI->addInitialFrameState(Inst);
313 
314  return MAI;
315 }
316 
318  unsigned SyntaxVariant,
319  const MCAsmInfo &MAI,
320  const MCInstrInfo &MII,
321  const MCRegisterInfo &MRI)
322 {
323  if (SyntaxVariant == 0)
324  return new HexagonInstPrinter(MAI, MII, MRI);
325  else
326  return nullptr;
327 }
328 
329 static MCTargetStreamer *
331  MCInstPrinter *IP, bool IsVerboseAsm) {
332  return new HexagonTargetAsmStreamer(S, OS, IsVerboseAsm, *IP);
333 }
334 
336  std::unique_ptr<MCAsmBackend> &&MAB,
337  std::unique_ptr<MCObjectWriter> &&OW,
338  std::unique_ptr<MCCodeEmitter> &&Emitter,
339  bool RelaxAll) {
341  std::move(Emitter));
342 }
343 
344 static MCTargetStreamer *
346  return new HexagonTargetELFStreamer(S, STI);
347 }
348 
350  if (STI->getFeatureBits()[F])
351  STI->ToggleFeature(F);
352 }
353 
355  return STI->getFeatureBits()[F];
356 }
357 
358 namespace {
359 std::string selectHexagonFS(StringRef CPU, StringRef FS) {
361  if (!FS.empty())
362  Result.push_back(FS);
363 
364  switch (EnableHVX) {
367  break;
369  Result.push_back("+hvxv60");
370  break;
372  Result.push_back("+hvxv62");
373  break;
375  Result.push_back("+hvxv65");
376  break;
378  Result.push_back("+hvxv66");
379  break;
381  Result.push_back("+hvxv67");
382  break;
384  Result.push_back("+hvxv68");
385  break;
387  Result.push_back("+hvxv69");
388  break;
390  Result.push_back(StringSwitch<StringRef>(CPU)
391  .Case("hexagonv60", "+hvxv60")
392  .Case("hexagonv62", "+hvxv62")
393  .Case("hexagonv65", "+hvxv65")
394  .Case("hexagonv66", "+hvxv66")
395  .Case("hexagonv67", "+hvxv67")
396  .Case("hexagonv67t", "+hvxv67")
397  .Case("hexagonv68", "+hvxv68")
398  .Case("hexagonv69", "+hvxv69"));
399  break;
400  }
402  // Sentinel if -mhvx isn't specified
403  break;
404  }
405  if (EnableHvxIeeeFp)
406  Result.push_back("+hvx-ieee-fp");
407  if (EnableHexagonCabac)
408  Result.push_back("+cabac");
409 
410  return join(Result.begin(), Result.end(), ",");
411 }
412 }
413 
414 static bool isCPUValid(StringRef CPU) {
415  return Hexagon::getCpu(CPU).has_value();
416 }
417 
418 namespace {
419 std::pair<std::string, std::string> selectCPUAndFS(StringRef CPU,
420  StringRef FS) {
421  std::pair<std::string, std::string> Result;
422  Result.first = std::string(Hexagon_MC::selectHexagonCPU(CPU));
423  Result.second = selectHexagonFS(Result.first, FS);
424  return Result;
425 }
426 std::mutex ArchSubtargetMutex;
427 std::unordered_map<std::string, std::unique_ptr<MCSubtargetInfo const>>
428  ArchSubtarget;
429 } // namespace
430 
431 MCSubtargetInfo const *
433  std::lock_guard<std::mutex> Lock(ArchSubtargetMutex);
434  auto Existing = ArchSubtarget.find(std::string(STI->getCPU()));
435  if (Existing == ArchSubtarget.end())
436  return nullptr;
437  return Existing->second.get();
438 }
439 
441  using namespace Hexagon;
442  // Make sure that +hvx-length turns hvx on, and that "hvx" alone
443  // turns on hvxvNN, corresponding to the existing ArchVNN.
444  FeatureBitset FB = S;
445  unsigned CpuArch = ArchV5;
446  for (unsigned F : {ArchV69, ArchV68, ArchV67, ArchV66, ArchV65, ArchV62,
447  ArchV60, ArchV55, ArchV5}) {
448  if (!FB.test(F))
449  continue;
450  CpuArch = F;
451  break;
452  }
453  bool UseHvx = false;
454  for (unsigned F : {ExtensionHVX, ExtensionHVX64B, ExtensionHVX128B}) {
455  if (!FB.test(F))
456  continue;
457  UseHvx = true;
458  break;
459  }
460  bool HasHvxVer = false;
461  for (unsigned F : {ExtensionHVXV60, ExtensionHVXV62, ExtensionHVXV65,
462  ExtensionHVXV66, ExtensionHVXV67, ExtensionHVXV68,
463  ExtensionHVXV69}) {
464  if (!FB.test(F))
465  continue;
466  HasHvxVer = true;
467  UseHvx = true;
468  break;
469  }
470 
471  if (!UseHvx || HasHvxVer)
472  return FB;
473 
474  // HasHvxVer is false, and UseHvx is true.
475  switch (CpuArch) {
476  case ArchV69:
477  FB.set(ExtensionHVXV69);
478  [[fallthrough]];
479  case ArchV68:
480  FB.set(ExtensionHVXV68);
481  [[fallthrough]];
482  case ArchV67:
483  FB.set(ExtensionHVXV67);
484  [[fallthrough]];
485  case ArchV66:
486  FB.set(ExtensionHVXV66);
487  [[fallthrough]];
488  case ArchV65:
489  FB.set(ExtensionHVXV65);
490  [[fallthrough]];
491  case ArchV62:
492  FB.set(ExtensionHVXV62);
493  [[fallthrough]];
494  case ArchV60:
495  FB.set(ExtensionHVXV60);
496  break;
497  }
498  return FB;
499 }
500 
502  StringRef CPU,
503  StringRef FS) {
504  std::pair<std::string, std::string> Features = selectCPUAndFS(CPU, FS);
505  StringRef CPUName = Features.first;
506  StringRef ArchFS = Features.second;
507 
508  MCSubtargetInfo *X = createHexagonMCSubtargetInfoImpl(
509  TT, CPUName, /*TuneCPU*/ CPUName, ArchFS);
510  if (X != nullptr && (CPUName == "hexagonv67t"))
511  addArchSubtarget(X, ArchFS);
512 
513  if (CPU.equals("help"))
514  exit(0);
515 
516  if (!isCPUValid(CPUName.str())) {
517  errs() << "error: invalid CPU \"" << CPUName.str().c_str()
518  << "\" specified\n";
519  return nullptr;
520  }
521 
522  // Add qfloat subtarget feature by default to v68 and above
523  // unless explicitely disabled
524  if (checkFeature(X, Hexagon::ExtensionHVXV68) &&
525  ArchFS.find("-hvx-qfloat", 0) == std::string::npos) {
526  llvm::FeatureBitset Features = X->getFeatureBits();
527  X->setFeatureBits(Features.set(Hexagon::ExtensionHVXQFloat));
528  }
529 
530  if (HexagonDisableDuplex) {
531  llvm::FeatureBitset Features = X->getFeatureBits();
532  X->setFeatureBits(Features.reset(Hexagon::FeatureDuplex));
533  }
534 
535  X->setFeatureBits(completeHVXFeatures(X->getFeatureBits()));
536 
537  // The Z-buffer instructions are grandfathered in for current
538  // architectures but omitted for new ones. Future instruction
539  // sets may introduce new/conflicting z-buffer instructions.
540  const bool ZRegOnDefault =
541  (CPUName == "hexagonv67") || (CPUName == "hexagonv66");
542  if (ZRegOnDefault) {
543  llvm::FeatureBitset Features = X->getFeatureBits();
544  X->setFeatureBits(Features.set(Hexagon::ExtensionZReg));
545  }
546 
547  return X;
548 }
549 
551  StringRef FS) {
552  assert(STI != nullptr);
553  if (STI->getCPU().contains("t")) {
554  auto ArchSTI = createHexagonMCSubtargetInfo(
555  STI->getTargetTriple(),
556  STI->getCPU().substr(0, STI->getCPU().size() - 1), FS);
557  std::lock_guard<std::mutex> Lock(ArchSubtargetMutex);
558  ArchSubtarget[std::string(STI->getCPU())] =
559  std::unique_ptr<MCSubtargetInfo const>(ArchSTI);
560  }
561 }
562 
564  return StringSwitch<unsigned>(STI.getCPU())
566  .Case("hexagonv5", llvm::ELF::EF_HEXAGON_MACH_V5)
567  .Case("hexagonv55", llvm::ELF::EF_HEXAGON_MACH_V55)
568  .Case("hexagonv60", llvm::ELF::EF_HEXAGON_MACH_V60)
569  .Case("hexagonv62", llvm::ELF::EF_HEXAGON_MACH_V62)
570  .Case("hexagonv65", llvm::ELF::EF_HEXAGON_MACH_V65)
571  .Case("hexagonv66", llvm::ELF::EF_HEXAGON_MACH_V66)
572  .Case("hexagonv67", llvm::ELF::EF_HEXAGON_MACH_V67)
573  .Case("hexagonv67t", llvm::ELF::EF_HEXAGON_MACH_V67T)
574  .Case("hexagonv68", llvm::ELF::EF_HEXAGON_MACH_V68)
575  .Case("hexagonv69", llvm::ELF::EF_HEXAGON_MACH_V69);
576 }
577 
579  return makeArrayRef(VectRegRev);
580 }
581 
582 namespace {
583 class HexagonMCInstrAnalysis : public MCInstrAnalysis {
584 public:
585  HexagonMCInstrAnalysis(MCInstrInfo const *Info) : MCInstrAnalysis(Info) {}
586 
587  bool isUnconditionalBranch(MCInst const &Inst) const override {
588  //assert(!HexagonMCInstrInfo::isBundle(Inst));
590  }
591 
592  bool isConditionalBranch(MCInst const &Inst) const override {
593  //assert(!HexagonMCInstrInfo::isBundle(Inst));
595  }
596 
597  bool evaluateBranch(MCInst const &Inst, uint64_t Addr,
598  uint64_t Size, uint64_t &Target) const override {
599  if (!(isCall(Inst) || isUnconditionalBranch(Inst) ||
600  isConditionalBranch(Inst)))
601  return false;
602 
603  //assert(!HexagonMCInstrInfo::isBundle(Inst));
605  return false;
606  auto const &Extended(HexagonMCInstrInfo::getExtendableOperand(*Info, Inst));
607  assert(Extended.isExpr());
608  int64_t Value;
609  if(!Extended.getExpr()->evaluateAsAbsolute(Value))
610  return false;
611  Target = Value;
612  return true;
613  }
614 };
615 }
616 
618  return new HexagonMCInstrAnalysis(Info);
619 }
620 
621 // Force static initialization.
623  // Register the MC asm info.
625 
626  // Register the MC instruction info.
629 
630  // Register the MC register info.
633 
634  // Register the MC subtarget info.
637 
638  // Register the MC Code Emitter
641 
642  // Register the asm backend
645 
646 
647  // Register the MC instruction analyzer.
650 
651  // Register the obj streamer
654 
655  // Register the obj target streamer
658 
659  // Register the asm streamer
662 
663  // Register the MC Inst Printer
666 }
HexagonTargetInfo.h
llvm::StringSwitch::Case
StringSwitch & Case(StringLiteral S, T Value)
Definition: StringSwitch.h:69
HexagonMCTargetDesc.h
HexagonInstPrinter.h
EnableHvxIeeeFp
static cl::opt< bool > EnableHvxIeeeFp("mhvx-ieee-fp", cl::Hidden, cl::desc("Enable HVX IEEE floating point extensions"))
MCDwarf.h
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::Hexagon::ArchEnum::NoArch
@ NoArch
llvm::HexagonConvertUnits
unsigned HexagonConvertUnits(unsigned ItinUnits, unsigned *Lanes)
Definition: HexagonMCTargetDesc.cpp:162
llvm::MCSymbol
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
llvm::ELF::EF_HEXAGON_MACH_V65
@ EF_HEXAGON_MACH_V65
Definition: ELF.h:617
llvm::Hexagon::ArchEnum::V65
@ V65
HexagonGetArchVariant
static StringRef HexagonGetArchVariant()
Definition: HexagonMCTargetDesc.cpp:117
createMCStreamer
static MCStreamer * createMCStreamer(Triple const &T, MCContext &Context, std::unique_ptr< MCAsmBackend > &&MAB, std::unique_ptr< MCObjectWriter > &&OW, std::unique_ptr< MCCodeEmitter > &&Emitter, bool RelaxAll)
Definition: HexagonMCTargetDesc.cpp:335
llvm::HexagonDisableCompound
cl::opt< bool > HexagonDisableCompound
T
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:76
StringRef.h
MCCodeEmitter.h
llvm::raw_string_ostream
A raw_ostream that writes to an std::string.
Definition: raw_ostream.h:628
isCPUValid
static bool isCPUValid(StringRef CPU)
Definition: HexagonMCTargetDesc.cpp:414
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:145
llvm::MCAsmInfo
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1181
ErrorHandling.h
llvm::ELF::EF_HEXAGON_MACH_V69
@ EF_HEXAGON_MACH_V69
Definition: ELF.h:622
llvm::cl::ValueOptional
@ ValueOptional
Definition: CommandLine.h:132
llvm::Hexagon_MC::GetELFFlags
unsigned GetELFFlags(const MCSubtargetInfo &STI)
Definition: HexagonMCTargetDesc.cpp:563
llvm::TargetRegistry::RegisterAsmTargetStreamer
static void RegisterAsmTargetStreamer(Target &T, Target::AsmTargetStreamerCtorTy Fn)
Definition: TargetRegistry.h:1015
llvm::ELF::EF_HEXAGON_MACH_V55
@ EF_HEXAGON_MACH_V55
Definition: ELF.h:614
llvm::TargetRegistry::RegisterMCInstrAnalysis
static void RegisterMCInstrAnalysis(Target &T, Target::MCInstrAnalysisCtorFnTy Fn)
RegisterMCInstrAnalysis - Register a MCInstrAnalysis implementation for the given target.
Definition: TargetRegistry.h:858
createHexagonMCInstPrinter
static MCInstPrinter * createHexagonMCInstPrinter(const Triple &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI)
Definition: HexagonMCTargetDesc.cpp:317
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
MCAssembler.h
llvm::Hexagon_MC::addArchSubtarget
void addArchSubtarget(MCSubtargetInfo const *STI, StringRef FS)
Definition: HexagonMCTargetDesc.cpp:550
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:139
llvm::HexagonInstPrinter
Prints bundles as a newline separated list of individual instructions Duplexes are separated by a ver...
Definition: HexagonInstPrinter.h:25
llvm::StringRef::substr
StringRef substr(size_t Start, size_t N=npos) const
Return a reference to the substring from [Start, Start + N).
Definition: StringRef.h:561
llvm::Hexagon::ArchEnum::V5
@ V5
llvm::FeatureBitset
Container class for subtarget features.
Definition: SubtargetFeature.h:40
llvm::errs
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
Definition: raw_ostream.cpp:891
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
LLVM_ATTRIBUTE_UNUSED
#define LLVM_ATTRIBUTE_UNUSED
Definition: Compiler.h:172
llvm::TargetRegistry::RegisterMCInstPrinter
static void RegisterMCInstPrinter(Target &T, Target::MCInstPrinterCtorTy Fn)
RegisterMCInstPrinter - Register a MCInstPrinter implementation for the given target.
Definition: TargetRegistry.h:965
llvm::Hexagon_MC::getArchSubtarget
const MCSubtargetInfo * getArchSubtarget(MCSubtargetInfo const *STI)
Definition: HexagonMCTargetDesc.cpp:432
llvm::MCInstPrinter::printInst
virtual void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &OS)=0
Print the specified MCInst to the specified raw_ostream.
MCELFStreamer.h
F
#define F(x, y, z)
Definition: MD5.cpp:55
llvm::Hexagon::ArchEnum::V66
@ V66
llvm::FeatureBitset::set
FeatureBitset & set()
Definition: SubtargetFeature.h:56
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
llvm::HexagonMCInstrInfo::isMemReorderDisabled
bool isMemReorderDisabled(MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:795
llvm::MCStreamer
Streaming machine code generation interface.
Definition: MCStreamer.h:212
llvm::createHexagonELFStreamer
MCStreamer * createHexagonELFStreamer(Triple const &TT, MCContext &Context, std::unique_ptr< MCAsmBackend > MAB, std::unique_ptr< MCObjectWriter > OW, std::unique_ptr< MCCodeEmitter > CE)
Definition: HexagonMCELFStreamer.cpp:153
ELF.h
llvm::MCELFStreamer
Definition: MCELFStreamer.h:31
MCAsmBackend.h
llvm::HexagonDisableDuplex
cl::opt< bool > HexagonDisableDuplex
HexagonMCInstrInfo.h
llvm::MCSubtargetInfo::getTargetTriple
const Triple & getTargetTriple() const
Definition: MCSubtargetInfo.h:108
MCContext.h
llvm::HexagonMCInstrInfo::isBundle
bool isBundle(MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:539
MCInstrInfo.h
llvm::ms_demangle::QualifierMangleMode::Result
@ Result
llvm::Hexagon::ArchEnum::Generic
@ Generic
IP
Definition: NVPTXLowerArgs.cpp:168
llvm::ELF::EF_HEXAGON_MACH_V60
@ EF_HEXAGON_MACH_V60
Definition: ELF.h:615
llvm::MCInstrAnalysis
Definition: MCInstrAnalysis.h:30
MCSubtargetInfo.h
llvm::MCSubtargetInfo::getFeatureBits
const FeatureBitset & getFeatureBits() const
Definition: MCSubtargetInfo.h:112
llvm::MCInstrAnalysis::isUnconditionalBranch
virtual bool isUnconditionalBranch(const MCInst &Inst) const
Definition: MCInstrAnalysis.h:48
llvm::HexagonTargetStreamer
Definition: HexagonTargetStreamer.h:15
llvm::Hexagon::ArchEnum::V62
@ V62
llvm::report_fatal_error
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:145
Options
const char LLVMTargetMachineRef LLVMPassBuilderOptionsRef Options
Definition: PassBuilderBindings.cpp:48
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
llvm::MCTargetStreamer
Target specific streamer interface.
Definition: MCStreamer.h:93
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::RegisterMCAsmInfoFn
RegisterMCAsmInfoFn - Helper template for registering a target assembly info implementation.
Definition: TargetRegistry.h:1140
llvm::HexagonMCInstrInfo::bundleSize
size_t bundleSize(MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:116
llvm::ELF::EF_HEXAGON_MACH_V66
@ EF_HEXAGON_MACH_V66
Definition: ELF.h:618
llvm::MCCFIInstruction
Definition: MCDwarf.h:478
X
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
llvm::StringRef::equals
bool equals(StringRef RHS) const
equals - Check for string equality, this is more efficient than compare() when the relative ordering ...
Definition: StringRef.h:164
llvm::MCSubtargetInfo::ToggleFeature
FeatureBitset ToggleFeature(uint64_t FB)
Toggle a feature and return the re-computed feature bits.
Definition: MCSubtargetInfo.cpp:240
llvm::Hexagon::ArchEnum::V67
@ V67
llvm::StringRef::empty
constexpr bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:134
llvm::cl::opt< bool >
llvm::Hexagon_MC::GetVectRegRev
llvm::ArrayRef< MCPhysReg > GetVectRegRev()
Definition: HexagonMCTargetDesc.cpp:578
llvm::MCAssembler
Definition: MCAssembler.h:73
llvm::cl::values
ValuesClass values(OptsTy... Options)
Helper to build a ValuesClass by forwarding a variable number of arguments as an initializer list to ...
Definition: CommandLine.h:692
llvm::TargetRegistry::RegisterMCAsmBackend
static void RegisterMCAsmBackend(Target &T, Target::MCAsmBackendCtorTy Fn)
RegisterMCAsmBackend - Register a MCAsmBackend implementation for the given target.
Definition: TargetRegistry.h:912
HexagonMCELFStreamer.h
llvm::createHexagonMCInstrInfo
MCInstrInfo * createHexagonMCInstrInfo()
Definition: HexagonMCTargetDesc.cpp:292
uint64_t
llvm::MCInstrAnalysis::isConditionalBranch
virtual bool isConditionalBranch(const MCInst &Inst) const
Definition: MCInstrAnalysis.h:44
llvm::MCInstPrinter
This is an instance of a target assembly language printer that converts an MCInst to valid target ass...
Definition: MCInstPrinter.h:43
LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:127
Addr
uint64_t Addr
Definition: ELFObjHandler.cpp:78
createHexagonMCAsmInfo
static MCAsmInfo * createHexagonMCAsmInfo(const MCRegisterInfo &MRI, const Triple &TT, const MCTargetOptions &Options)
Definition: HexagonMCTargetDesc.cpp:304
llvm::createHexagonMCRegisterInfo
MCRegisterInfo * createHexagonMCRegisterInfo(StringRef TT)
move
compiles ldr LCPI1_0 ldr ldr mov lsr tst moveq r1 ldr LCPI1_1 and r0 bx lr It would be better to do something like to fold the shift into the conditional move
Definition: README.txt:546
checkFeature
static bool LLVM_ATTRIBUTE_UNUSED checkFeature(MCSubtargetInfo *STI, uint64_t F)
Definition: HexagonMCTargetDesc.cpp:354
llvm::MCSubtargetInfo::getCPU
StringRef getCPU() const
Definition: MCSubtargetInfo.h:109
StringExtras.h
llvm::TargetRegistry::RegisterObjectTargetStreamer
static void RegisterObjectTargetStreamer(Target &T, Target::ObjectTargetStreamerCtorTy Fn)
Definition: TargetRegistry.h:1021
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:439
MCRegisterInfo.h
llvm::HexagonGetLastSlot
unsigned HexagonGetLastSlot()
Definition: HexagonMCTargetDesc.cpp:160
llvm::MCAssembler::setELFHeaderEFlags
void setELFHeaderEFlags(unsigned Flags)
Definition: MCAssembler.h:277
llvm::formatted_raw_ostream
formatted_raw_ostream - A raw_ostream that wraps another one and keeps track of line and column posit...
Definition: FormattedStream.h:30
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::Hexagon::ArchEnum::V55
@ V55
llvm::Hexagon::getCpu
Optional< Hexagon::ArchEnum > getCpu(StringRef CPU)
Definition: HexagonDepArch.h:21
llvm::X86AS::FS
@ FS
Definition: X86.h:200
llvm::MCCFIInstruction::cfiDefCfa
static MCCFIInstruction cfiDefCfa(MCSymbol *L, unsigned Register, int Offset)
.cfi_def_cfa defines a rule for computing CFA as: take address from Register and add Offset to it.
Definition: MCDwarf.h:532
llvm::MCAsmInfo::addInitialFrameState
void addInitialFrameState(const MCCFIInstruction &Inst)
Definition: MCAsmInfo.cpp:86
llvm::TargetRegistry::RegisterMCSubtargetInfo
static void RegisterMCSubtargetInfo(Target &T, Target::MCSubtargetInfoCtorFnTy Fn)
RegisterMCSubtargetInfo - Register a MCSubtargetInfo implementation for the given target.
Definition: TargetRegistry.h:885
llvm::MCTargetOptions
Definition: MCTargetOptions.h:37
llvm::getTheHexagonTarget
Target & getTheHexagonTarget()
Definition: HexagonTargetInfo.cpp:13
EnableHexagonCabac
static cl::opt< bool > EnableHexagonCabac("mcabac", cl::desc("tbd"), cl::init(false))
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
MCInstrAnalysis.h
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
clEnumValN
#define clEnumValN(ENUMVAL, FLAGNAME, DESC)
Definition: CommandLine.h:667
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
llvm::HexagonMCAsmInfo
Definition: HexagonMCAsmInfo.h:21
llvm::ELF::EF_HEXAGON_MACH_V68
@ EF_HEXAGON_MACH_V68
Definition: ELF.h:621
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition: MCRegisterInfo.h:135
llvm::FeatureBitset::reset
constexpr FeatureBitset & reset(unsigned I)
Definition: SubtargetFeature.h:68
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
isUnconditionalBranch
static bool isUnconditionalBranch(Instruction *Term)
Definition: ADCE.cpp:210
llvm::HexagonMCELFStreamer
Definition: HexagonMCELFStreamer.h:20
llvm::HexagonFUnits::isSlot0Only
bool isSlot0Only(unsigned units)
Definition: HexagonMCTargetDesc.cpp:206
llvm::StringRef::size
constexpr size_t size() const
size - Get the string size.
Definition: StringRef.h:137
MCObjectWriter.h
llvm::TargetRegistry::RegisterMCInstrInfo
static void RegisterMCInstrInfo(Target &T, Target::MCInstrInfoCtorFnTy Fn)
RegisterMCInstrInfo - Register a MCInstrInfo implementation for the given target.
Definition: TargetRegistry.h:852
llvm::TargetRegistry::RegisterMCCodeEmitter
static void RegisterMCCodeEmitter(Target &T, Target::MCCodeEmitterCtorTy Fn)
RegisterMCCodeEmitter - Register a MCCodeEmitter implementation for the given target.
Definition: TargetRegistry.h:978
llvm::MCInstrInfo
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:26
LLVMInitializeHexagonTargetMC
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeHexagonTargetMC()
Definition: HexagonMCTargetDesc.cpp:622
llvm::TargetRegistry::RegisterMCRegInfo
static void RegisterMCRegInfo(Target &T, Target::MCRegInfoCtorFnTy Fn)
RegisterMCRegInfo - Register a MCRegisterInfo implementation for the given target.
Definition: TargetRegistry.h:872
DisableHVX
static cl::opt< bool > DisableHVX("mno-hvx", cl::Hidden, cl::desc("Disable Hexagon Vector eXtensions"))
llvm::TargetRegistry::RegisterELFStreamer
static void RegisterELFStreamer(Target &T, Target::ELFStreamerCtorTy Fn)
Definition: TargetRegistry.h:990
llvm::Hexagon::ArchEnum::V69
@ V69
llvm::TargetStackID::Value
Value
Definition: TargetFrameLowering.h:27
llvm::HexagonMCInstrInfo::getExtendableOperand
const MCOperand & getExtendableOperand(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:323
llvm::LCOMM::ByteAlignment
@ ByteAlignment
Definition: MCAsmInfo.h:50
llvm::ELF::EF_HEXAGON_MACH_V5
@ EF_HEXAGON_MACH_V5
Definition: ELF.h:613
llvm::StringRef::contains
bool contains(StringRef Other) const
Return true if the given string is a substring of *this, and false otherwise.
Definition: StringRef.h:415
llvm::makeArrayRef
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
Definition: ArrayRef.h:475
llvm::ARMBuildAttrs::Symbol
@ Symbol
Definition: ARMBuildAttributes.h:83
HexagonDepArch.h
llvm::Hexagon_MC::createHexagonMCSubtargetInfo
MCSubtargetInfo * createHexagonMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS)
Create a Hexagon MCSubtargetInfo instance.
Definition: HexagonMCTargetDesc.cpp:501
createHexagonMCInstrAnalysis
static MCInstrAnalysis * createHexagonMCInstrAnalysis(const MCInstrInfo *Info)
Definition: HexagonMCTargetDesc.cpp:617
llvm::FeatureBitset::test
constexpr bool test(unsigned I) const
Definition: SubtargetFeature.h:87
llvm::createHexagonMCCodeEmitter
MCCodeEmitter * createHexagonMCCodeEmitter(const MCInstrInfo &MCII, MCContext &MCT)
Definition: HexagonMCCodeEmitter.cpp:789
llvm::Hexagon_MC::selectHexagonCPU
StringRef selectHexagonCPU(StringRef CPU)
Definition: HexagonMCTargetDesc.cpp:141
createMCAsmTargetStreamer
static MCTargetStreamer * createMCAsmTargetStreamer(MCStreamer &S, formatted_raw_ostream &OS, MCInstPrinter *IP, bool IsVerboseAsm)
Definition: HexagonMCTargetDesc.cpp:330
clearFeature
static void LLVM_ATTRIBUTE_UNUSED clearFeature(MCSubtargetInfo *STI, uint64_t F)
Definition: HexagonMCTargetDesc.cpp:349
DefaultArch
static StringRef DefaultArch
Definition: HexagonMCTargetDesc.cpp:115
exit
declare void exit(i32) noreturn nounwind This compiles into
Definition: README.txt:1072
MCStreamer.h
llvm::Hexagon::ArchEnum::V68
@ V68
createHexagonObjectTargetStreamer
static MCTargetStreamer * createHexagonObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI)
Definition: HexagonMCTargetDesc.cpp:345
HexagonMCAsmInfo.h
llvm::Hexagon::ArchEnum::V60
@ V60
llvm::StringSwitch
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:44
llvm::StringRef::str
std::string str() const
str - Get the contents as an std::string.
Definition: StringRef.h:221
llvm::StringRef::find
size_t find(char C, size_t From=0) const
Search for the first character C in the string.
Definition: StringRef.h:281
llvm::Hexagon_MC::completeHVXFeatures
FeatureBitset completeHVXFeatures(const FeatureBitset &FB)
Definition: HexagonMCTargetDesc.cpp:440
llvm::HexagonMCELFStreamer::HexagonMCEmitLocalCommonSymbol
void HexagonMCEmitLocalCommonSymbol(MCSymbol *Symbol, uint64_t Size, unsigned ByteAlignment, unsigned AccessSize)
Definition: HexagonMCELFStreamer.cpp:140
llvm::cl::desc
Definition: CommandLine.h:412
raw_ostream.h
llvm::ELF::EF_HEXAGON_MACH_V67T
@ EF_HEXAGON_MACH_V67T
Definition: ELF.h:620
HEXAGON_PACKET_SIZE
#define HEXAGON_PACKET_SIZE
Definition: HexagonMCTargetDesc.h:36
TargetRegistry.h
llvm::createHexagonAsmBackend
MCAsmBackend * createHexagonAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
Definition: HexagonAsmBackend.cpp:774
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:76
llvm::StringRef::split
std::pair< StringRef, StringRef > split(char Separator) const
Split into two substrings around the first occurrence of a separator character.
Definition: StringRef.h:689
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
HexagonTargetStreamer.h
llvm::ELF::EF_HEXAGON_MACH_V62
@ EF_HEXAGON_MACH_V62
Definition: ELF.h:616
llvm::HexagonMCELFStreamer::HexagonMCEmitCommonSymbol
void HexagonMCEmitCommonSymbol(MCSymbol *Symbol, uint64_t Size, unsigned ByteAlignment, unsigned AccessSize)
Definition: HexagonMCELFStreamer.cpp:88
llvm::HexagonMCInstrInfo::isExtendable
bool isExtendable(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:620
llvm::ELF::EF_HEXAGON_MACH_V67
@ EF_HEXAGON_MACH_V67
Definition: ELF.h:619