LLVM 20.0.0git
HexagonAsmBackend.cpp
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1//===-- HexagonAsmBackend.cpp - Hexagon Assembler Backend -----------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#include "HexagonFixupKinds.h"
17#include "llvm/MC/MCAssembler.h"
18#include "llvm/MC/MCContext.h"
21#include "llvm/MC/MCInstrInfo.h"
25#include "llvm/Support/Debug.h"
27
28#include <sstream>
29
30using namespace llvm;
31using namespace Hexagon;
32
33#define DEBUG_TYPE "hexagon-asm-backend"
34
36 ("mno-fixup", cl::desc("Disable fixing up resolved relocations for Hexagon"));
37
38namespace {
39
40class HexagonAsmBackend : public MCAsmBackend {
41 uint8_t OSABI;
42 StringRef CPU;
43 mutable uint64_t relaxedCnt;
44 std::unique_ptr <MCInstrInfo> MCII;
45 std::unique_ptr <MCInst *> RelaxTarget;
46 MCInst * Extender;
47 unsigned MaxPacketSize;
48
49 void ReplaceInstruction(MCCodeEmitter &E, MCRelaxableFragment &RF,
50 MCInst &HMB) const {
53 E.encodeInstruction(HMB, Code, Fixups, *RF.getSubtargetInfo());
54
55 // Update the fragment.
56 RF.setInst(HMB);
57 RF.getContents() = Code;
58 RF.getFixups() = Fixups;
59 }
60
61public:
62 HexagonAsmBackend(const Target &T, const Triple &TT, uint8_t OSABI,
63 StringRef CPU)
64 : MCAsmBackend(llvm::endianness::little), OSABI(OSABI), CPU(CPU),
65 relaxedCnt(0), MCII(T.createMCInstrInfo()), RelaxTarget(new MCInst *),
66 Extender(nullptr), MaxPacketSize(HexagonMCInstrInfo::packetSize(CPU)) {}
67
68 std::unique_ptr<MCObjectTargetWriter>
69 createObjectTargetWriter() const override {
70 return createHexagonELFObjectWriter(OSABI, CPU);
71 }
72
73 void setExtender(MCContext &Context) const {
74 if (Extender == nullptr)
75 const_cast<HexagonAsmBackend *>(this)->Extender = Context.createMCInst();
76 }
77
78 MCInst *takeExtender() const {
79 assert(Extender != nullptr);
80 MCInst * Result = Extender;
81 const_cast<HexagonAsmBackend *>(this)->Extender = nullptr;
82 return Result;
83 }
84
85 unsigned getNumFixupKinds() const override {
87 }
88
89 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override {
90 const static MCFixupKindInfo Infos[Hexagon::NumTargetFixupKinds] = {
91 // This table *must* be in same the order of fixup_* kinds in
92 // HexagonFixupKinds.h.
93 //
94 // namei offset bits flags
95 { "fixup_Hexagon_B22_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
96 { "fixup_Hexagon_B15_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
97 { "fixup_Hexagon_B7_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
98 { "fixup_Hexagon_LO16", 0, 32, 0 },
99 { "fixup_Hexagon_HI16", 0, 32, 0 },
100 { "fixup_Hexagon_32", 0, 32, 0 },
101 { "fixup_Hexagon_16", 0, 32, 0 },
102 { "fixup_Hexagon_8", 0, 32, 0 },
103 { "fixup_Hexagon_GPREL16_0", 0, 32, 0 },
104 { "fixup_Hexagon_GPREL16_1", 0, 32, 0 },
105 { "fixup_Hexagon_GPREL16_2", 0, 32, 0 },
106 { "fixup_Hexagon_GPREL16_3", 0, 32, 0 },
107 { "fixup_Hexagon_HL16", 0, 32, 0 },
108 { "fixup_Hexagon_B13_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
109 { "fixup_Hexagon_B9_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
110 { "fixup_Hexagon_B32_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
111 { "fixup_Hexagon_32_6_X", 0, 32, 0 },
112 { "fixup_Hexagon_B22_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
113 { "fixup_Hexagon_B15_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
114 { "fixup_Hexagon_B13_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
115 { "fixup_Hexagon_B9_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
116 { "fixup_Hexagon_B7_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
117 { "fixup_Hexagon_16_X", 0, 32, 0 },
118 { "fixup_Hexagon_12_X", 0, 32, 0 },
119 { "fixup_Hexagon_11_X", 0, 32, 0 },
120 { "fixup_Hexagon_10_X", 0, 32, 0 },
121 { "fixup_Hexagon_9_X", 0, 32, 0 },
122 { "fixup_Hexagon_8_X", 0, 32, 0 },
123 { "fixup_Hexagon_7_X", 0, 32, 0 },
124 { "fixup_Hexagon_6_X", 0, 32, 0 },
125 { "fixup_Hexagon_32_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
126 { "fixup_Hexagon_COPY", 0, 32, 0 },
127 { "fixup_Hexagon_GLOB_DAT", 0, 32, 0 },
128 { "fixup_Hexagon_JMP_SLOT", 0, 32, 0 },
129 { "fixup_Hexagon_RELATIVE", 0, 32, 0 },
130 { "fixup_Hexagon_PLT_B22_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
131 { "fixup_Hexagon_GOTREL_LO16", 0, 32, 0 },
132 { "fixup_Hexagon_GOTREL_HI16", 0, 32, 0 },
133 { "fixup_Hexagon_GOTREL_32", 0, 32, 0 },
134 { "fixup_Hexagon_GOT_LO16", 0, 32, 0 },
135 { "fixup_Hexagon_GOT_HI16", 0, 32, 0 },
136 { "fixup_Hexagon_GOT_32", 0, 32, 0 },
137 { "fixup_Hexagon_GOT_16", 0, 32, 0 },
138 { "fixup_Hexagon_DTPMOD_32", 0, 32, 0 },
139 { "fixup_Hexagon_DTPREL_LO16", 0, 32, 0 },
140 { "fixup_Hexagon_DTPREL_HI16", 0, 32, 0 },
141 { "fixup_Hexagon_DTPREL_32", 0, 32, 0 },
142 { "fixup_Hexagon_DTPREL_16", 0, 32, 0 },
143 { "fixup_Hexagon_GD_PLT_B22_PCREL",0, 32, MCFixupKindInfo::FKF_IsPCRel },
144 { "fixup_Hexagon_LD_PLT_B22_PCREL",0, 32, MCFixupKindInfo::FKF_IsPCRel },
145 { "fixup_Hexagon_GD_GOT_LO16", 0, 32, 0 },
146 { "fixup_Hexagon_GD_GOT_HI16", 0, 32, 0 },
147 { "fixup_Hexagon_GD_GOT_32", 0, 32, 0 },
148 { "fixup_Hexagon_GD_GOT_16", 0, 32, 0 },
149 { "fixup_Hexagon_LD_GOT_LO16", 0, 32, 0 },
150 { "fixup_Hexagon_LD_GOT_HI16", 0, 32, 0 },
151 { "fixup_Hexagon_LD_GOT_32", 0, 32, 0 },
152 { "fixup_Hexagon_LD_GOT_16", 0, 32, 0 },
153 { "fixup_Hexagon_IE_LO16", 0, 32, 0 },
154 { "fixup_Hexagon_IE_HI16", 0, 32, 0 },
155 { "fixup_Hexagon_IE_32", 0, 32, 0 },
156 { "fixup_Hexagon_IE_16", 0, 32, 0 },
157 { "fixup_Hexagon_IE_GOT_LO16", 0, 32, 0 },
158 { "fixup_Hexagon_IE_GOT_HI16", 0, 32, 0 },
159 { "fixup_Hexagon_IE_GOT_32", 0, 32, 0 },
160 { "fixup_Hexagon_IE_GOT_16", 0, 32, 0 },
161 { "fixup_Hexagon_TPREL_LO16", 0, 32, 0 },
162 { "fixup_Hexagon_TPREL_HI16", 0, 32, 0 },
163 { "fixup_Hexagon_TPREL_32", 0, 32, 0 },
164 { "fixup_Hexagon_TPREL_16", 0, 32, 0 },
165 { "fixup_Hexagon_6_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
166 { "fixup_Hexagon_GOTREL_32_6_X", 0, 32, 0 },
167 { "fixup_Hexagon_GOTREL_16_X", 0, 32, 0 },
168 { "fixup_Hexagon_GOTREL_11_X", 0, 32, 0 },
169 { "fixup_Hexagon_GOT_32_6_X", 0, 32, 0 },
170 { "fixup_Hexagon_GOT_16_X", 0, 32, 0 },
171 { "fixup_Hexagon_GOT_11_X", 0, 32, 0 },
172 { "fixup_Hexagon_DTPREL_32_6_X", 0, 32, 0 },
173 { "fixup_Hexagon_DTPREL_16_X", 0, 32, 0 },
174 { "fixup_Hexagon_DTPREL_11_X", 0, 32, 0 },
175 { "fixup_Hexagon_GD_GOT_32_6_X", 0, 32, 0 },
176 { "fixup_Hexagon_GD_GOT_16_X", 0, 32, 0 },
177 { "fixup_Hexagon_GD_GOT_11_X", 0, 32, 0 },
178 { "fixup_Hexagon_LD_GOT_32_6_X", 0, 32, 0 },
179 { "fixup_Hexagon_LD_GOT_16_X", 0, 32, 0 },
180 { "fixup_Hexagon_LD_GOT_11_X", 0, 32, 0 },
181 { "fixup_Hexagon_IE_32_6_X", 0, 32, 0 },
182 { "fixup_Hexagon_IE_16_X", 0, 32, 0 },
183 { "fixup_Hexagon_IE_GOT_32_6_X", 0, 32, 0 },
184 { "fixup_Hexagon_IE_GOT_16_X", 0, 32, 0 },
185 { "fixup_Hexagon_IE_GOT_11_X", 0, 32, 0 },
186 { "fixup_Hexagon_TPREL_32_6_X", 0, 32, 0 },
187 { "fixup_Hexagon_TPREL_16_X", 0, 32, 0 },
188 { "fixup_Hexagon_TPREL_11_X", 0, 32, 0 },
189 { "fixup_Hexagon_GD_PLT_B22_PCREL_X",0, 32, MCFixupKindInfo::FKF_IsPCRel },
190 { "fixup_Hexagon_GD_PLT_B32_PCREL_X",0, 32, MCFixupKindInfo::FKF_IsPCRel },
191 { "fixup_Hexagon_LD_PLT_B22_PCREL_X",0, 32, MCFixupKindInfo::FKF_IsPCRel },
192 { "fixup_Hexagon_LD_PLT_B32_PCREL_X",0, 32, MCFixupKindInfo::FKF_IsPCRel }
193 };
194
195 if (Kind < FirstTargetFixupKind)
197
198 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
199 "Invalid kind!");
200 return Infos[Kind - FirstTargetFixupKind];
201 }
202
203 bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup,
204 const MCValue &Target,
205 const MCSubtargetInfo *STI) override {
206 switch(Fixup.getTargetKind()) {
207 default:
208 llvm_unreachable("Unknown Fixup Kind!");
209
212 case fixup_Hexagon_16:
213 case fixup_Hexagon_8:
298 // These relocations should always have a relocation recorded
299 return true;
300
302 //IsResolved = false;
303 break;
304
315 if (DisableFixup)
316 return true;
317 break;
318
319 case FK_Data_1:
320 case FK_Data_2:
321 case FK_Data_4:
322 case FK_PCRel_4:
323 case fixup_Hexagon_32:
324 // Leave these relocations alone as they are used for EH.
325 return false;
326 }
327 return false;
328 }
329
330 /// getFixupKindNumBytes - The number of bytes the fixup may change.
331 static unsigned getFixupKindNumBytes(unsigned Kind) {
332 switch (Kind) {
333 default:
334 return 0;
335
336 case FK_Data_1:
337 return 1;
338 case FK_Data_2:
339 return 2;
340 case FK_Data_4: // this later gets mapped to R_HEX_32
341 case FK_PCRel_4: // this later gets mapped to R_HEX_32_PCREL
342 case fixup_Hexagon_32:
356 return 4;
357 }
358 }
359
360 // Make up for left shift when encoding the operand.
362 switch((unsigned)Kind) {
363 default:
364 break;
365
371 Value >>= 2;
372 break;
373
379 Value &= 0x3f;
380 break;
381
385 Value >>= 6;
386 break;
387 }
388 return (Value);
389 }
390
391 void HandleFixupError(const int bits, const int align_bits,
392 const int64_t FixupValue, const char *fixupStr) const {
393 // Error: value 1124 out of range: -1024-1023 when resolving
394 // symbol in file xprtsock.S
395 const APInt IntMin = APInt::getSignedMinValue(bits+align_bits);
396 const APInt IntMax = APInt::getSignedMaxValue(bits+align_bits);
397 std::stringstream errStr;
398 errStr << "\nError: value " <<
399 FixupValue <<
400 " out of range: " <<
401 IntMin.getSExtValue() <<
402 "-" <<
403 IntMax.getSExtValue() <<
404 " when resolving " <<
405 fixupStr <<
406 " fixup\n";
407 llvm_unreachable(errStr.str().c_str());
408 }
409
410 /// ApplyFixup - Apply the \arg Value for given \arg Fixup into the provided
411 /// data fragment, at the offset specified by the fixup and following the
412 /// fixup kind as appropriate.
413 void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
415 uint64_t FixupValue, bool IsResolved,
416 const MCSubtargetInfo *STI) const override {
417
418 // When FixupValue is 0 the relocation is external and there
419 // is nothing for us to do.
420 if (!FixupValue) return;
421
422 MCFixupKind Kind = Fixup.getKind();
424 uint32_t InstMask;
425 uint32_t Reloc;
426
427 // LLVM gives us an encoded value, we have to convert it back
428 // to a real offset before we can use it.
429 uint32_t Offset = Fixup.getOffset();
430 unsigned NumBytes = getFixupKindNumBytes(Kind);
431 assert(Offset + NumBytes <= Data.size() && "Invalid fixup offset!");
432 char *InstAddr = Data.data() + Offset;
433
434 Value = adjustFixupValue(Kind, FixupValue);
435 if(!Value)
436 return;
437 int sValue = (int)Value;
438
439 switch((unsigned)Kind) {
440 default:
441 return;
442
444 if (!(isIntN(7, sValue)))
445 HandleFixupError(7, 2, (int64_t)FixupValue, "B7_PCREL");
446 [[fallthrough]];
448 InstMask = 0x00001f18; // Word32_B7
449 Reloc = (((Value >> 2) & 0x1f) << 8) | // Value 6-2 = Target 12-8
450 ((Value & 0x3) << 3); // Value 1-0 = Target 4-3
451 break;
452
454 if (!(isIntN(9, sValue)))
455 HandleFixupError(9, 2, (int64_t)FixupValue, "B9_PCREL");
456 [[fallthrough]];
458 InstMask = 0x003000fe; // Word32_B9
459 Reloc = (((Value >> 7) & 0x3) << 20) | // Value 8-7 = Target 21-20
460 ((Value & 0x7f) << 1); // Value 6-0 = Target 7-1
461 break;
462
463 // Since the existing branches that use this relocation cannot be
464 // extended, they should only be fixed up if the target is within range.
466 if (!(isIntN(13, sValue)))
467 HandleFixupError(13, 2, (int64_t)FixupValue, "B13_PCREL");
468 [[fallthrough]];
470 InstMask = 0x00202ffe; // Word32_B13
471 Reloc = (((Value >> 12) & 0x1) << 21) | // Value 12 = Target 21
472 (((Value >> 11) & 0x1) << 13) | // Value 11 = Target 13
473 ((Value & 0x7ff) << 1); // Value 10-0 = Target 11-1
474 break;
475
477 if (!(isIntN(15, sValue)))
478 HandleFixupError(15, 2, (int64_t)FixupValue, "B15_PCREL");
479 [[fallthrough]];
481 InstMask = 0x00df20fe; // Word32_B15
482 Reloc = (((Value >> 13) & 0x3) << 22) | // Value 14-13 = Target 23-22
483 (((Value >> 8) & 0x1f) << 16) | // Value 12-8 = Target 20-16
484 (((Value >> 7) & 0x1) << 13) | // Value 7 = Target 13
485 ((Value & 0x7f) << 1); // Value 6-0 = Target 7-1
486 break;
487
489 if (!(isIntN(22, sValue)))
490 HandleFixupError(22, 2, (int64_t)FixupValue, "B22_PCREL");
491 [[fallthrough]];
493 InstMask = 0x01ff3ffe; // Word32_B22
494 Reloc = (((Value >> 13) & 0x1ff) << 16) | // Value 21-13 = Target 24-16
495 ((Value & 0x1fff) << 1); // Value 12-0 = Target 13-1
496 break;
497
499 InstMask = 0x0fff3fff; // Word32_X26
500 Reloc = (((Value >> 14) & 0xfff) << 16) | // Value 25-14 = Target 27-16
501 (Value & 0x3fff); // Value 13-0 = Target 13-0
502 break;
503
504 case FK_Data_1:
505 case FK_Data_2:
506 case FK_Data_4:
507 case fixup_Hexagon_32:
508 InstMask = 0xffffffff; // Word32
509 Reloc = Value;
510 break;
511 }
512
513 LLVM_DEBUG(dbgs() << "Name=" << getFixupKindInfo(Kind).Name << "("
514 << (unsigned)Kind << ")\n");
516 uint32_t OldData = 0; for (unsigned i = 0; i < NumBytes; i++) OldData |=
517 (InstAddr[i] << (i * 8)) & (0xff << (i * 8));
518 dbgs() << "\tBValue=0x"; dbgs().write_hex(Value) << ": AValue=0x";
519 dbgs().write_hex(FixupValue)
520 << ": Offset=" << Offset << ": Size=" << Data.size() << ": OInst=0x";
521 dbgs().write_hex(OldData) << ": Reloc=0x"; dbgs().write_hex(Reloc););
522
523 // For each byte of the fragment that the fixup touches, mask in the
524 // bits from the fixup value. The Value has been "split up" into the
525 // appropriate bitfields above.
526 for (unsigned i = 0; i < NumBytes; i++){
527 InstAddr[i] &= uint8_t(~InstMask >> (i * 8)) & 0xff; // Clear reloc bits
528 InstAddr[i] |= uint8_t(Reloc >> (i * 8)) & 0xff; // Apply new reloc
529 }
530
531 LLVM_DEBUG(uint32_t NewData = 0;
532 for (unsigned i = 0; i < NumBytes; i++) NewData |=
533 (InstAddr[i] << (i * 8)) & (0xff << (i * 8));
534 dbgs() << ": NInst=0x"; dbgs().write_hex(NewData) << "\n";);
535 }
536
537 bool isInstRelaxable(MCInst const &HMI) const {
538 const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(*MCII, HMI);
539 bool Relaxable = false;
540 // Branches and loop-setup insns are handled as necessary by relaxation.
543 MCID.isBranch()) ||
545 MCID.isBranch()) ||
547 HMI.getOpcode() != Hexagon::C4_addipc))
548 if (HexagonMCInstrInfo::isExtendable(*MCII, HMI)) {
549 Relaxable = true;
550 MCOperand const &Operand =
553 Relaxable = false;
554 }
555
556 return Relaxable;
557 }
558
559 /// MayNeedRelaxation - Check whether the given instruction may need
560 /// relaxation.
561 ///
562 /// \param Inst - The instruction to test.
563 bool mayNeedRelaxation(MCInst const &Inst,
564 const MCSubtargetInfo &STI) const override {
565 return true;
566 }
567
568 /// fixupNeedsRelaxation - Target specific predicate for whether a given
569 /// fixup requires the associated instruction to be relaxed.
571 const MCFixup &Fixup, bool Resolved,
573 const MCRelaxableFragment *DF,
574 const bool WasForced) const override {
575 MCInst const &MCB = DF->getInst();
577
578 *RelaxTarget = nullptr;
579 MCInst &MCI = const_cast<MCInst &>(HexagonMCInstrInfo::instruction(
580 MCB, Fixup.getOffset() / HEXAGON_INSTR_SIZE));
581 bool Relaxable = isInstRelaxable(MCI);
582 if (Relaxable == false)
583 return false;
584 // If we cannot resolve the fixup value, it requires relaxation.
585 if (!Resolved) {
586 switch (Fixup.getTargetKind()) {
588 // GetFixupCount assumes B22 won't relax
589 [[fallthrough]];
590 default:
591 return false;
592 break;
598 ++relaxedCnt;
599 *RelaxTarget = &MCI;
600 setExtender(Asm.getContext());
601 return true;
602 } else {
603 return false;
604 }
605 break;
606 }
607 }
608 }
609
610 MCFixupKind Kind = Fixup.getKind();
611 int64_t sValue = Value;
612 int64_t maxValue;
613
614 switch ((unsigned)Kind) {
616 maxValue = 1 << 8;
617 break;
619 maxValue = 1 << 10;
620 break;
622 maxValue = 1 << 16;
623 break;
625 maxValue = 1 << 23;
626 break;
627 default:
628 maxValue = INT64_MAX;
629 break;
630 }
631
632 bool isFarAway = -maxValue > sValue || sValue > maxValue - 1;
633
634 if (isFarAway) {
636 ++relaxedCnt;
637 *RelaxTarget = &MCI;
638 setExtender(Asm.getContext());
639 return true;
640 }
641 }
642
643 return false;
644 }
645
646 void relaxInstruction(MCInst &Inst,
647 const MCSubtargetInfo &STI) const override {
649 "Hexagon relaxInstruction only works on bundles");
650
651 MCInst Res;
652 Res.setOpcode(Hexagon::BUNDLE);
654 // Copy the results into the bundle.
655 bool Update = false;
656 for (auto &I : HexagonMCInstrInfo::bundleInstructions(Inst)) {
657 MCInst &CrntHMI = const_cast<MCInst &>(*I.getInst());
658
659 // if immediate extender needed, add it in
660 if (*RelaxTarget == &CrntHMI) {
661 Update = true;
663 "No room to insert extender for relaxation");
664
665 MCInst *HMIx = takeExtender();
667 *MCII, CrntHMI,
670 *RelaxTarget = nullptr;
671 }
672 // now copy over the original instruction(the one we may have extended)
673 Res.addOperand(MCOperand::createInst(I.getInst()));
674 }
675
676 Inst = std::move(Res);
677 (void)Update;
678 assert(Update && "Didn't find relaxation target");
679 }
680
681 bool writeNopData(raw_ostream &OS, uint64_t Count,
682 const MCSubtargetInfo *STI) const override {
683 static const uint32_t Nopcode = 0x7f000000, // Hard-coded NOP.
684 ParseIn = 0x00004000, // In packet parse-bits.
685 ParseEnd = 0x0000c000; // End of packet parse-bits.
686
687 while (Count % HEXAGON_INSTR_SIZE) {
688 LLVM_DEBUG(dbgs() << "Alignment not a multiple of the instruction size:"
689 << Count % HEXAGON_INSTR_SIZE << "/"
690 << HEXAGON_INSTR_SIZE << "\n");
691 --Count;
692 OS << '\0';
693 }
694
695 while (Count) {
696 Count -= HEXAGON_INSTR_SIZE;
697 // Close the packet whenever a multiple of the maximum packet size remains
698 uint32_t ParseBits = (Count % (MaxPacketSize * HEXAGON_INSTR_SIZE)) ?
699 ParseIn : ParseEnd;
700 support::endian::write<uint32_t>(OS, Nopcode | ParseBits, Endian);
701 }
702 return true;
703 }
704
705 void finishLayout(MCAssembler const &Asm) const override {
707 for (MCSection &Sec : Asm) {
708 Frags.clear();
709 for (MCFragment &F : Sec)
710 Frags.push_back(&F);
711 for (size_t J = 0, E = Frags.size(); J != E; ++J) {
712 switch (Frags[J]->getKind()) {
713 default:
714 break;
716 auto Size = Asm.computeFragmentSize(*Frags[J]);
717 for (auto K = J; K != 0 && Size >= HEXAGON_PACKET_SIZE;) {
718 --K;
719 switch (Frags[K]->getKind()) {
720 default:
721 break;
723 // Don't pad before other alignments
724 Size = 0;
725 break;
726 }
728 MCContext &Context = Asm.getContext();
729 auto &RF = cast<MCRelaxableFragment>(*Frags[K]);
730 auto &Inst = const_cast<MCInst &>(RF.getInst());
731 while (Size > 0 &&
732 HexagonMCInstrInfo::bundleSize(Inst) < MaxPacketSize) {
733 MCInst *Nop = Context.createMCInst();
734 Nop->setOpcode(Hexagon::A2_nop);
736 Size -= 4;
737 if (!HexagonMCChecker(
738 Context, *MCII, *RF.getSubtargetInfo(), Inst,
739 *Context.getRegisterInfo(), false)
740 .check()) {
741 Inst.erase(Inst.end() - 1);
742 Size = 0;
743 }
744 }
745 bool Error = HexagonMCShuffle(Context, true, *MCII,
746 *RF.getSubtargetInfo(), Inst);
747 //assert(!Error);
748 (void)Error;
749 ReplaceInstruction(Asm.getEmitter(), RF, Inst);
750 Sec.setHasLayout(false);
751 Size = 0; // Only look back one instruction
752 break;
753 }
754 }
755 }
756 }
757 }
758 }
759 }
760 }
761}; // class HexagonAsmBackend
762
763} // namespace
764
765// MCAsmBackend
767 const MCSubtargetInfo &STI,
768 MCRegisterInfo const & /*MRI*/,
769 const MCTargetOptions &Options) {
770 const Triple &TT = STI.getTargetTriple();
771 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS());
772
774 return new HexagonAsmBackend(T, TT, OSABI, CPUString);
775}
static unsigned getFixupKindNumBytes(unsigned Kind)
The number of bytes the fixup may change.
static uint64_t adjustFixupValue(const MCFixup &Fixup, const MCValue &Target, uint64_t Value, MCContext &Ctx, const Triple &TheTriple, bool IsResolved)
#define LLVM_DEBUG(X)
Definition: Debug.h:101
static RegisterPass< DebugifyFunctionPass > DF("debugify-function", "Attach debug info to a function")
std::string Name
uint64_t Size
static cl::opt< bool > DisableFixup("mno-fixup", cl::desc("Disable fixing up resolved relocations for Hexagon"))
Definition for classes that emit Hexagon machine code from MCInsts.
#define HEXAGON_INSTR_SIZE
#define HEXAGON_PACKET_SIZE
static LVOptions Options
Definition: LVOptions.cpp:25
#define F(x, y, z)
Definition: MD5.cpp:55
#define I(x, y, z)
Definition: MD5.cpp:58
PowerPC TLS Dynamic Call Fixup
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
raw_pwrite_stream & OS
static MCInstrInfo * createMCInstrInfo()
Class for arbitrary precision integers.
Definition: APInt.h:78
static APInt getSignedMaxValue(unsigned numBits)
Gets maximum signed value of APInt for a specific bit width.
Definition: APInt.h:189
static APInt getSignedMinValue(unsigned numBits)
Gets minimum signed value of APInt for a specific bit width.
Definition: APInt.h:199
int64_t getSExtValue() const
Get sign extended value.
Definition: APInt.h:1522
Lightweight error class with error context and mandatory checking.
Definition: Error.h:160
Check for a valid bundle.
bool check(bool FullCheck=true)
Generic interface to target specific assembler backends.
Definition: MCAsmBackend.h:42
virtual bool writeNopData(raw_ostream &OS, uint64_t Count, const MCSubtargetInfo *STI) const =0
Write an (optimal) nop sequence of Count bytes to the given output.
virtual void relaxInstruction(MCInst &Inst, const MCSubtargetInfo &STI) const
Relax the instruction in the given fragment to the next wider instruction.
Definition: MCAsmBackend.h:179
virtual bool mayNeedRelaxation(const MCInst &Inst, const MCSubtargetInfo &STI) const
Check whether the given instruction may need relaxation.
Definition: MCAsmBackend.h:155
virtual bool fixupNeedsRelaxationAdvanced(const MCAssembler &Asm, const MCFixup &Fixup, bool Resolved, uint64_t Value, const MCRelaxableFragment *DF, const bool WasForced) const
Target specific predicate for whether a given fixup requires the associated instruction to be relaxed...
virtual std::unique_ptr< MCObjectTargetWriter > createObjectTargetWriter() const =0
virtual void finishLayout(MCAssembler const &Asm) const
Give backend an opportunity to finish layout after relaxation.
Definition: MCAsmBackend.h:223
virtual bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target, const MCSubtargetInfo *STI)
Hook to check if a relocation is needed for some target specific reason.
Definition: MCAsmBackend.h:96
virtual unsigned getNumFixupKinds() const =0
Get the number of target specific fixup kinds.
virtual const MCFixupKindInfo & getFixupKindInfo(MCFixupKind Kind) const
Get information on a fixup kind.
virtual void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target, MutableArrayRef< char > Data, uint64_t Value, bool IsResolved, const MCSubtargetInfo *STI) const =0
Apply the Value for given Fixup into the provided data fragment, at the offset specified by the fixup...
MCCodeEmitter - Generic instruction encoding interface.
Definition: MCCodeEmitter.h:21
virtual void encodeInstruction(const MCInst &Inst, SmallVectorImpl< char > &CB, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const =0
Encode the given Inst to bytes and append to CB.
Context object for machine code objects.
Definition: MCContext.h:83
MCInst * createMCInst()
Create and return a new MC instruction.
Definition: MCContext.cpp:195
const MCRegisterInfo * getRegisterInfo() const
Definition: MCContext.h:414
SmallVectorImpl< MCFixup > & getFixups()
Definition: MCFragment.h:200
SmallVectorImpl< char > & getContents()
Definition: MCFragment.h:197
const MCSubtargetInfo * getSubtargetInfo() const
Retrieve the MCSubTargetInfo in effect when the instruction was encoded.
Definition: MCFragment.h:167
Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...
Definition: MCFixup.h:71
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
void erase(iterator I)
Definition: MCInst.h:216
unsigned getOpcode() const
Definition: MCInst.h:198
void addOperand(const MCOperand Op)
Definition: MCInst.h:210
iterator end()
Definition: MCInst.h:221
void setOpcode(unsigned Op)
Definition: MCInst.h:197
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:206
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:198
bool isBranch() const
Returns true if this is a conditional, unconditional, or indirect branch.
Definition: MCInstrDesc.h:307
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:36
int64_t getImm() const
Definition: MCInst.h:80
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:141
const MCExpr * getExpr() const
Definition: MCInst.h:114
static MCOperand createInst(const MCInst *Val)
Definition: MCInst.h:169
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
A relaxable fragment holds on to its MCInst, since it may need to be relaxed during the assembler lay...
Definition: MCFragment.h:234
const MCInst & getInst() const
Definition: MCFragment.h:244
void setInst(const MCInst &Value)
Definition: MCFragment.h:245
Instances of this class represent a uniqued identifier for a section in the current translation unit.
Definition: MCSection.h:36
Generic base class for all target subtargets.
const Triple & getTargetTriple() const
StringRef getCPU() const
This represents an "assembler immediate".
Definition: MCValue.h:36
MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...
Definition: ArrayRef.h:307
SmallString - A SmallString is just a SmallVector with methods and accessors that make it work better...
Definition: SmallString.h:26
size_t size() const
Definition: SmallVector.h:92
void push_back(const T &Elt)
Definition: SmallVector.h:427
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1210
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
Target - Wrapper for Target specific information.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
LLVM Value Representation.
Definition: Value.h:74
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
raw_ostream & write_hex(unsigned long long N)
Output N in hexadecimal, without any prefix or padding.
#define INT64_MAX
Definition: DataTypes.h:71
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
size_t bundleSize(MCInst const &MCI)
unsigned short getExtendableOp(MCInstrInfo const &MCII, MCInst const &MCI)
bool mustNotExtend(MCExpr const &Expr)
MCInstrDesc const & getDesc(MCInstrInfo const &MCII, MCInst const &MCI)
iterator_range< Hexagon::PacketIterator > bundleInstructions(MCInstrInfo const &MCII, MCInst const &MCI)
bool isBundle(MCInst const &MCI)
bool isExtendable(MCInstrInfo const &MCII, MCInst const &MCI)
unsigned getType(MCInstrInfo const &MCII, MCInst const &MCI)
Return the Hexagon ISA class for the insn.
MCInst const & instruction(MCInst const &MCB, size_t Index)
MCOperand const & getExtendableOperand(MCInstrInfo const &MCII, MCInst const &MCI)
unsigned packetSize(StringRef CPU)
MCInst deriveExtender(MCInstrInfo const &MCII, MCInst const &Inst, MCOperand const &MO)
StringRef selectHexagonCPU(StringRef CPU)
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:480
bool HexagonMCShuffle(MCContext &Context, bool ReportErrors, MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst &MCB)
std::unique_ptr< MCObjectTargetWriter > createHexagonELFObjectWriter(uint8_t OSABI, StringRef CPU)
MCAsmBackend * createHexagonAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
MCFixupKind
Extensible enumeration to represent the type of a fixup.
Definition: MCFixup.h:21
@ FirstTargetFixupKind
Definition: MCFixup.h:45
@ FK_PCRel_4
A four-byte pc relative fixup.
Definition: MCFixup.h:30
@ FK_Data_1
A one-byte fixup.
Definition: MCFixup.h:23
@ FK_Data_4
A four-byte fixup.
Definition: MCFixup.h:25
@ FK_Data_2
A two-byte fixup.
Definition: MCFixup.h:24
bool isIntN(unsigned N, int64_t x)
Checks if an signed integer fits into the given (dynamic) bit width.
Definition: MathExtras.h:260
endianness
Definition: bit.h:70
Target independent information on a fixup kind.
@ FKF_IsPCRel
Is this fixup kind PCrelative? This is used by the assembler backend to evaluate fixup values in a ta...