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13 #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONMACHINESCHEDULER_H
14 #define LLVM_LIB_TARGET_HEXAGON_HEXAGONMACHINESCHEDULER_H
42 #endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONMACHINESCHEDULER_H
This is an optimization pass for GlobalISel generic memory operations.
VLIWResourceModel(const TargetSubtargetInfo &STI, const TargetSchedModel *SM)
Store the state used by ConvergingVLIWScheduler heuristics, required for the lifetime of one invocati...
VLIWResourceModel * createVLIWResourceModel(const TargetSubtargetInfo &STI, const TargetSchedModel *SchedModel) const override
Provide an instruction scheduling machine model to CodeGen passes.
TargetSubtargetInfo - Generic base class for all target subtargets.
Store the effects of a change in pressure on things that MI scheduler cares about.
const TargetSchedModel * SchedModel
int SchedulingCost(ReadyQueue &Q, SUnit *SU, SchedCandidate &Candidate, RegPressureDelta &Delta, bool verbose) override
Single point to compute overall scheduling cost.
bool hasDependence(const SUnit *SUd, const SUnit *SUu) override
Return true if there is a dependence between SUd and SUu.
Scheduling unit. This is a node in the scheduling DAG.
Helpers for implementing custom MachineSchedStrategy classes.