#include "Target/Hexagon/HexagonMachineScheduler.h"

Inheritance diagram for llvm::HexagonConvergingVLIWScheduler:

Protected Member Functions
VLIWResourceModel *	createVLIWResourceModel (const TargetSubtargetInfo &STI, const TargetSchedModel *SchedModel) const override
int	SchedulingCost (ReadyQueue &Q, SUnit *SU, SchedCandidate &Candidate, RegPressureDelta &Delta, bool verbose) override
	Single point to compute overall scheduling cost.
Protected Member Functions inherited from llvm::ConvergingVLIWScheduler
SUnit *	pickNodeBidrectional (bool &IsTopNode)
	Pick the best candidate node from either the top or bottom queue.
int	pressureChange (const SUnit *SU, bool isBotUp)
	Check if the instruction changes the register pressure of a register in the high pressure set.
CandResult	pickNodeFromQueue (VLIWSchedBoundary &Zone, const RegPressureTracker &RPTracker, SchedCandidate &Candidate)
	Pick the best candidate from the top queue.
void	traceCandidate (const char Label, const ReadyQueue &Q, SUnit SU, int Cost, PressureChange P=PressureChange())
void	readyQueueVerboseDump (const RegPressureTracker &RPTracker, SchedCandidate &Candidate, ReadyQueue &Q)

Additional Inherited Members
Public Types inherited from llvm::ConvergingVLIWScheduler
enum	{ TopQID = 1 , BotQID = 2 , LogMaxQID = 2 }
	SUnit::NodeQueueId: 0 (none), 1 (top), 2 (bot), 3 (both) More...
Public Member Functions inherited from llvm::ConvergingVLIWScheduler
	ConvergingVLIWScheduler ()
virtual	~ConvergingVLIWScheduler ()=default
void	initialize (ScheduleDAGMI *dag) override
	Initialize the strategy after building the DAG for a new region.
SUnit *	pickNode (bool &IsTopNode) override
	Pick the best node to balance the schedule. Implements MachineSchedStrategy.
void	schedNode (SUnit *SU, bool IsTopNode) override
	Update the scheduler's state after scheduling a node.
void	releaseTopNode (SUnit *SU) override
	When all predecessor dependencies have been resolved, free this node for top-down scheduling.
void	releaseBottomNode (SUnit *SU) override
	When all successor dependencies have been resolved, free this node for bottom-up scheduling.
unsigned	reportPackets ()
Public Member Functions inherited from llvm::MachineSchedStrategy
virtual	~MachineSchedStrategy ()=default
virtual void	initPolicy (MachineBasicBlock::iterator Begin, MachineBasicBlock::iterator End, unsigned NumRegionInstrs)
	Optionally override the per-region scheduling policy.
virtual MachineSchedPolicy	getPolicy () const
virtual void	dumpPolicy () const
virtual bool	shouldTrackPressure () const
	Check if pressure tracking is needed before building the DAG and initializing this strategy.
virtual bool	shouldTrackLaneMasks () const
	Returns true if lanemasks should be tracked.
virtual bool	doMBBSchedRegionsTopDown () const
virtual void	enterMBB (MachineBasicBlock *MBB)
	Tell the strategy that MBB is about to be processed.
virtual void	leaveMBB ()
	Tell the strategy that current MBB is done.
virtual void	registerRoots ()
	Notify this strategy that all roots have been released (including those that depend on EntrySU or ExitSU).
virtual void	scheduleTree (unsigned SubtreeID)
	Scheduler callback to notify that a new subtree is scheduled.
Protected Types inherited from llvm::ConvergingVLIWScheduler
enum	CandResult { NoCand , NodeOrder , SingleExcess , SingleCritical , SingleMax , MultiPressure , BestCost , Weak }
	Represent the type of SchedCandidate found within a single queue. More...
Protected Attributes inherited from llvm::ConvergingVLIWScheduler
VLIWMachineScheduler *	DAG = nullptr
const TargetSchedModel *	SchedModel = nullptr
VLIWSchedBoundary	Top
VLIWSchedBoundary	Bot
SmallVector< bool >	HighPressureSets
	List of pressure sets that have a high pressure level in the region.
Static Protected Attributes inherited from llvm::ConvergingVLIWScheduler
static constexpr unsigned	PriorityOne = 200
static constexpr unsigned	PriorityTwo = 50
static constexpr unsigned	PriorityThree = 75
static constexpr unsigned	ScaleTwo = 10

Detailed Description

Definition at line 31 of file HexagonMachineScheduler.h.

Member Function Documentation

◆ createVLIWResourceModel()

VLIWResourceModel * HexagonConvergingVLIWScheduler::createVLIWResourceModel	(	const TargetSubtargetInfo &	STI,
		const TargetSchedModel *	SchedModel ) const