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11 #ifndef LLVM_CODEGEN_VLIWMACHINESCHEDULER_H
12 #define LLVM_CODEGEN_VLIWMACHINESCHEDULER_H
25 class RegisterClassInfo;
26 class ScheduleHazardRecognizer;
28 class TargetInstrInfo;
29 class TargetSubtargetInfo;
72 std::unique_ptr<MachineSchedStrategy>
S)
174 unsigned MaxPath = 0;
176 MaxPath =
std::max(MaxPath,
isTop() ? SU.getHeight() : SU.getDepth());
254 SchedCandidate &Candidate);
268 #endif // LLVM_CODEGEN_VLIWMACHINESCHEDULER_H
void initialize(ScheduleDAGMI *dag) override
Initialize the strategy after building the DAG for a new region.
This is an optimization pass for GlobalISel generic memory operations.
RegisterClassInfo * getRegClassInfo()
SUnit * pickNode(bool &IsTopNode) override
Pick the best node to balance the schedule. Implements MachineSchedStrategy.
SUnit * pickNodeBidrectional(bool &IsTopNode)
Pick the best candidate node from either the top or bottom queue.
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
void readyQueueVerboseDump(const RegPressureTracker &RPTracker, SchedCandidate &Candidate, ReadyQueue &Q)
VLIWResourceModel(const TargetSubtargetInfo &STI, const TargetSchedModel *SM)
Store the state used by ConvergingVLIWScheduler heuristics, required for the lifetime of one invocati...
virtual bool hasDependence(const SUnit *SUd, const SUnit *SUu)
Return true if there is a dependence between SUd and SUu.
SmallVector< bool > HighPressureSets
List of pressure sets that have a high pressure level in the region.
Track the current register pressure at some position in the instruction stream, and remember the high...
Extend the standard ScheduleDAGMILive to provide more context and override the top-level schedule() d...
VLIWSchedBoundary(unsigned ID, const Twine &Name)
Pending queues extend the ready queues with the same ID and the PendingFlag set.
unsigned getDepth() const
Returns the depth of this node, which is the length of the maximum path up to any node which has no p...
Expected< ExpressionValue > max(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
static constexpr unsigned PriorityOne
ConvergingVLIWScheduler()
const TargetSchedModel * SchedModel
static constexpr unsigned PriorityTwo
unsigned CriticalPathLength
void traceCandidate(const char *Label, const ReadyQueue &Q, SUnit *SU, int Cost, PressureChange P=PressureChange())
void releaseBottomNode(SUnit *SU) override
When all successor dependencies have been resolved, free this node for bottom-up scheduling.
MachineSchedStrategy - Interface to the scheduling algorithm used by ScheduleDAGMI.
TargetInstrInfo - Interface to description of machine instruction set.
unsigned getIssueWidth() const
Maximum number of micro-ops that may be scheduled per cycle.
(vector float) vec_cmpeq(*A, *B) C
int pressureChange(const SUnit *SU, bool isBotUp)
Check if the instruction changes the register pressure of a register in the high pressure set.
const TargetInstrInfo * TII
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
CandResult
Represent the type of SchedCandidate found within a single queue.
unsigned getHeight() const
Returns the height of this node, which is the length of the maximum path down to any node which has n...
RegisterClassInfo * RegClassInfo
bool checkHazard(SUnit *SU)
Does this SU have a hazard within the current instruction group.
void schedule() override
Schedule - This is called back from ScheduleDAGInstrs::Run() when it's time to do some work.
virtual bool isResourceAvailable(SUnit *SU, bool IsTop)
Check if scheduling of this SU is possible in the current packet.
DFAPacketizer * ResourcesModel
ResourcesModel - Represents VLIW state.
ScheduleHazardRecognizer * HazardRec
bool isInPacket(SUnit *SU) const
Provide an instruction scheduling machine model to CodeGen passes.
unsigned getTotalPackets() const
virtual int SchedulingCost(ReadyQueue &Q, SUnit *SU, SchedCandidate &Candidate, RegPressureDelta &Delta, bool verbose)
Single point to compute overall scheduling cost.
MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...
void bumpNode(SUnit *SU)
Move the boundary of scheduled code by one SUnit.
bool is_contained(R &&Range, const E &Element)
Wrapper function around std::find to detect if an element exists in a container.
virtual bool reserveResources(SUnit *SU, bool IsTop)
Keep track of available resources.
static constexpr unsigned ScaleTwo
OutputIt move(R &&Range, OutputIt Out)
Provide wrappers to std::move which take ranges instead of having to pass begin/end explicitly.
Each Scheduling boundary is associated with ready queues.
void releasePending()
Release pending ready nodes in to the available queue.
ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...
SmallVector< SUnit * > Packet
Local packet/bundle model.
ScheduleDAGMILive * createVLIWSched(MachineSchedContext *C)
VLIWMachineScheduler * DAG
VLIWMachineScheduler * DAG
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
TargetSubtargetInfo - Generic base class for all target subtargets.
unsigned TotalPackets
Total packets created.
const TargetSchedModel * SchedModel
VLIWResourceModel * ResourceModel
Store the effects of a change in pressure on things that MI scheduler cares about.
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
std::vector< SUnit > SUnits
The scheduling units.
void schedNode(SUnit *SU, bool IsTopNode) override
Update the scheduler's state after scheduling a node.
virtual ~VLIWResourceModel()
Capture a change in pressure for a single pressure set.
void bumpCycle()
Move the boundary of scheduled code by one cycle.
void releaseNode(SUnit *SU, unsigned ReadyCycle)
MachineBasicBlock * BB
The block in which to insert instructions.
virtual VLIWResourceModel * createVLIWResourceModel(const TargetSubtargetInfo &STI, const TargetSchedModel *SchedModel) const
const TargetSchedModel * SchedModel
bool isLatencyBound(SUnit *SU)
void releaseTopNode(SUnit *SU) override
When all predecessor dependencies have been resolved, free this node for top-down scheduling.
CandResult pickNodeFromQueue(VLIWSchedBoundary &Zone, const RegPressureTracker &RPTracker, SchedCandidate &Candidate)
Pick the best candidate from the top queue.
size_t getPacketInstCount() const
VLIWMachineScheduler(MachineSchedContext *C, std::unique_ptr< MachineSchedStrategy > S)
SUnit * pickOnlyChoice()
If this queue only has one ready candidate, return it.
void removeReady(SUnit *SU)
Remove SU from the ready set for this boundary.
Scheduling unit. This is a node in the scheduling DAG.
ScheduleDAGMILive is an implementation of ScheduleDAGInstrs that schedules machine instructions while...
Helpers for implementing custom MachineSchedStrategy classes.
HazardRecognizer - This determines whether or not an instruction can be issued this cycle,...
virtual DFAPacketizer * createPacketizer(const TargetSubtargetInfo &STI) const
void init(VLIWMachineScheduler *dag, const TargetSchedModel *smodel)
static constexpr unsigned PriorityThree
virtual ~ConvergingVLIWScheduler()=default
unsigned MinReadyCycle
MinReadyCycle - Cycle of the soonest available instruction.