11#ifndef LLVM_CODEGEN_VLIWMACHINESCHEDULER_H
12#define LLVM_CODEGEN_VLIWMACHINESCHEDULER_H
73 std::unique_ptr<MachineSchedStrategy> S)
78 void schedule()
override;
168 const auto BBSize =
DAG->getBBSize();
178 unsigned MaxPath = 0;
179 for (
auto &SU :
DAG->SUnits)
180 MaxPath = std::max(MaxPath,
isTop() ? SU.getHeight() : SU.getDepth());
239 return Top.ResourceModel->getTotalPackets() +
240 Bot.ResourceModel->getTotalPackets();
248 SUnit *pickNodeBidrectional(
bool &IsTopNode);
250 int pressureChange(
const SUnit *SU,
bool isBotUp);
256 CandResult pickNodeFromQueue(VLIWSchedBoundary &Zone,
258 SchedCandidate &Candidate);
static SUnit * pickOnlyChoice(SchedBoundary &Zone)
static constexpr unsigned SM(unsigned Version)
This file defines the SmallVector class.
static void initialize(TargetLibraryInfoImpl &TLI, const Triple &T, const llvm::StringTable &StandardNames, VectorLibrary VecLib)
Initialize the set of available library functions based on the specified target triple.
VLIWMachineScheduler * DAG
~ConvergingVLIWScheduler() override=default
void releaseBottomNode(SUnit *SU) override
When all successor dependencies have been resolved, free this node for bottom-up scheduling.
static constexpr unsigned PriorityOne
SUnit * pickNode(bool &IsTopNode) override
Pick the best node to balance the schedule. Implements MachineSchedStrategy.
SmallVector< bool > HighPressureSets
List of pressure sets that have a high pressure level in the region.
static constexpr unsigned ScaleTwo
void schedNode(SUnit *SU, bool IsTopNode) override
Update the scheduler's state after scheduling a node.
void releaseTopNode(SUnit *SU) override
When all predecessor dependencies have been resolved, free this node for top-down scheduling.
static constexpr unsigned PriorityTwo
ConvergingVLIWScheduler()
static constexpr unsigned PriorityThree
const TargetSchedModel * SchedModel
CandResult
Represent the type of SchedCandidate found within a single queue.
MachineSchedStrategy - Interface to the scheduling algorithm used by ScheduleDAGMI.
Capture a change in pressure for a single pressure set.
Helpers for implementing custom MachineSchedStrategy classes.
Track the current register pressure at some position in the instruction stream, and remember the high...
Scheduling unit. This is a node in the scheduling DAG.
unsigned getHeight() const
Returns the height of this node, which is the length of the maximum path down to any node which has n...
unsigned getDepth() const
Returns the depth of this node, which is the length of the maximum path up to any node which has no p...
MachineBasicBlock * BB
The block in which to insert instructions.
ScheduleDAGMILive(MachineSchedContext *C, std::unique_ptr< MachineSchedStrategy > S)
RegisterClassInfo * RegClassInfo
ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...
HazardRecognizer - This determines whether or not an instruction can be issued this cycle,...
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
TargetInstrInfo - Interface to description of machine instruction set.
Provide an instruction scheduling machine model to CodeGen passes.
TargetSubtargetInfo - Generic base class for all target subtargets.
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Extend the standard ScheduleDAGMILive to provide more context and override the top-level schedule() d...
VLIWMachineScheduler(MachineSchedContext *C, std::unique_ptr< MachineSchedStrategy > S)
RegisterClassInfo * getRegClassInfo()
unsigned TotalPackets
Total packets created.
size_t getPacketInstCount() const
virtual bool hasDependence(const SUnit *SUd, const SUnit *SUu)
Return true if there is a dependence between SUd and SUu.
virtual bool reserveResources(SUnit *SU, bool IsTop)
Keep track of available resources.
VLIWResourceModel & operator=(const VLIWResourceModel &other)=delete
bool isInPacket(SUnit *SU) const
DFAPacketizer * ResourcesModel
ResourcesModel - Represents VLIW state.
SmallVector< SUnit * > Packet
Local packet/bundle model.
const TargetSchedModel * SchedModel
VLIWResourceModel(const VLIWResourceModel &other)=delete
VLIWResourceModel(const TargetSubtargetInfo &STI, const TargetSchedModel *SM)
unsigned getTotalPackets() const
virtual bool isResourceAvailable(SUnit *SU, bool IsTop)
Check if scheduling of this SU is possible in the current packet.
const TargetInstrInfo * TII
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
@ C
The default llvm calling convention, compatible with C.
This is an optimization pass for GlobalISel generic memory operations.
OutputIt move(R &&Range, OutputIt Out)
Provide wrappers to std::move which take ranges instead of having to pass begin/end explicitly.
bool is_contained(R &&Range, const E &Element)
Returns true if Element is found in Range.
Implement std::hash so that hash_code can be used in STL containers.
Each Scheduling boundary is associated with ready queues.
const TargetSchedModel * SchedModel
unsigned CriticalPathLength
bool isLatencyBound(SUnit *SU)
VLIWSchedBoundary(unsigned ID, const Twine &Name)
Pending queues extend the ready queues with the same ID and the PendingFlag set.
VLIWSchedBoundary & operator=(const VLIWSchedBoundary &other)=delete
ScheduleHazardRecognizer * HazardRec
unsigned MinReadyCycle
MinReadyCycle - Cycle of the soonest available instruction.
VLIWResourceModel * ResourceModel
VLIWMachineScheduler * DAG
void init(VLIWMachineScheduler *dag, const TargetSchedModel *smodel)
VLIWSchedBoundary(const VLIWSchedBoundary &other)=delete
MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...
Store the effects of a change in pressure on things that MI scheduler cares about.