LLVM 17.0.0git
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1//===- HexagonMachineScheduler.cpp - MI Scheduler for Hexagon -------------===//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
9// MachineScheduler schedules machine instructions after phi elimination. It
10// preserves LiveIntervals so it can be invoked before register allocation.
15#include "HexagonInstrInfo.h"
16#include "HexagonSubtarget.h"
21using namespace llvm;
23#define DEBUG_TYPE "machine-scheduler"
25/// Return true if there is a dependence between SUd and SUu.
27 const SUnit *SUu) {
28 const auto *QII = static_cast<const HexagonInstrInfo *>(TII);
30 // Enable .cur formation.
31 if (QII->mayBeCurLoad(*SUd->getInstr()))
32 return false;
34 if (QII->canExecuteInBundle(*SUd->getInstr(), *SUu->getInstr()))
35 return false;
37 return VLIWResourceModel::hasDependence(SUd, SUu);
41 const TargetSubtargetInfo &STI, const TargetSchedModel *SchedModel) const {
42 return new HexagonVLIWResourceModel(STI, SchedModel);
46 SchedCandidate &Candidate,
47 RegPressureDelta &Delta,
48 bool verbose) {
49 int ResCount =
50 ConvergingVLIWScheduler::SchedulingCost(Q, SU, Candidate, Delta, verbose);
52 if (!SU || SU->isScheduled)
53 return ResCount;
55 auto &QST = DAG->MF.getSubtarget<HexagonSubtarget>();
56 auto &QII = *QST.getInstrInfo();
57 if (SU->isInstr() && QII.mayBeCurLoad(*SU->getInstr())) {
58 if (Q.getID() == TopQID &&
60 ResCount += PriorityTwo;
61 LLVM_DEBUG(if (verbose) dbgs() << "C|");
62 } else if (Q.getID() == BotQID &&
64 ResCount += PriorityTwo;
65 LLVM_DEBUG(if (verbose) dbgs() << "C|");
66 }
67 }
69 return ResCount;
#define LLVM_DEBUG(X)
Definition: Debug.h:101
static constexpr unsigned PriorityTwo
const TargetSchedModel * SchedModel
virtual int SchedulingCost(ReadyQueue &Q, SUnit *SU, SchedCandidate &Candidate, RegPressureDelta &Delta, bool verbose)
Single point to compute overall scheduling cost.
VLIWResourceModel * createVLIWResourceModel(const TargetSubtargetInfo &STI, const TargetSchedModel *SchedModel) const override
int SchedulingCost(ReadyQueue &Q, SUnit *SU, SchedCandidate &Candidate, RegPressureDelta &Delta, bool verbose) override
Single point to compute overall scheduling cost.
const HexagonInstrInfo * getInstrInfo() const override
bool hasDependence(const SUnit *SUd, const SUnit *SUu) override
Return true if there is a dependence between SUd and SUu.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Helpers for implementing custom MachineSchedStrategy classes.
unsigned getID() const
Scheduling unit. This is a node in the scheduling DAG.
Definition: ScheduleDAG.h:242
bool isInstr() const
Returns true if this SUnit refers to a machine instruction as opposed to an SDNode.
Definition: ScheduleDAG.h:362
bool isScheduled
True once scheduled.
Definition: ScheduleDAG.h:284
MachineInstr * getInstr() const
Returns the representative MachineInstr for this SUnit.
Definition: ScheduleDAG.h:373
MachineFunction & MF
Machine function.
Definition: ScheduleDAG.h:559
Provide an instruction scheduling machine model to CodeGen passes.
TargetSubtargetInfo - Generic base class for all target subtargets.
virtual bool hasDependence(const SUnit *SUd, const SUnit *SUu)
Return true if there is a dependence between SUd and SUu.
virtual bool isResourceAvailable(SUnit *SU, bool IsTop)
Check if scheduling of this SU is possible in the current packet.
const TargetInstrInfo * TII
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
Store the state used by ConvergingVLIWScheduler heuristics, required for the lifetime of one invocati...
Store the effects of a change in pressure on things that MI scheduler cares about.