LLVM  15.0.0git
HexagonMachineScheduler.cpp
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1 //===- HexagonMachineScheduler.cpp - MI Scheduler for Hexagon -------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // MachineScheduler schedules machine instructions after phi elimination. It
10 // preserves LiveIntervals so it can be invoked before register allocation.
11 //
12 //===----------------------------------------------------------------------===//
13 
15 #include "HexagonInstrInfo.h"
16 #include "HexagonSubtarget.h"
20 
21 using namespace llvm;
22 
23 #define DEBUG_TYPE "machine-scheduler"
24 
25 /// Return true if there is a dependence between SUd and SUu.
27  const SUnit *SUu) {
28  const auto *QII = static_cast<const HexagonInstrInfo *>(TII);
29 
30  // Enable .cur formation.
31  if (QII->mayBeCurLoad(*SUd->getInstr()))
32  return false;
33 
34  if (QII->canExecuteInBundle(*SUd->getInstr(), *SUu->getInstr()))
35  return false;
36 
37  return VLIWResourceModel::hasDependence(SUd, SUu);
38 }
39 
41  const TargetSubtargetInfo &STI, const TargetSchedModel *SchedModel) const {
42  return new HexagonVLIWResourceModel(STI, SchedModel);
43 }
44 
46  SchedCandidate &Candidate,
47  RegPressureDelta &Delta,
48  bool verbose) {
49  int ResCount =
50  ConvergingVLIWScheduler::SchedulingCost(Q, SU, Candidate, Delta, verbose);
51 
52  if (!SU || SU->isScheduled)
53  return ResCount;
54 
55  auto &QST = DAG->MF.getSubtarget<HexagonSubtarget>();
56  auto &QII = *QST.getInstrInfo();
57  if (SU->isInstr() && QII.mayBeCurLoad(*SU->getInstr())) {
58  if (Q.getID() == TopQID &&
60  ResCount += PriorityTwo;
61  LLVM_DEBUG(if (verbose) dbgs() << "C|");
62  } else if (Q.getID() == BotQID &&
64  ResCount += PriorityTwo;
65  LLVM_DEBUG(if (verbose) dbgs() << "C|");
66  }
67  }
68 
69  return ResCount;
70 }
ScheduleDAG.h
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
HexagonSubtarget.h
llvm::ConvergingVLIWScheduler::SchedCandidate
Store the state used by ConvergingVLIWScheduler heuristics, required for the lifetime of one invocati...
Definition: VLIWMachineScheduler.h:92
llvm::VLIWResourceModel::hasDependence
virtual bool hasDependence(const SUnit *SUd, const SUnit *SUu)
Return true if there is a dependence between SUd and SUu.
Definition: VLIWMachineScheduler.cpp:88
llvm::HexagonConvergingVLIWScheduler::createVLIWResourceModel
VLIWResourceModel * createVLIWResourceModel(const TargetSubtargetInfo &STI, const TargetSchedModel *SchedModel) const override
Definition: HexagonMachineScheduler.cpp:40
llvm::ConvergingVLIWScheduler::PriorityTwo
static constexpr unsigned PriorityTwo
Definition: VLIWMachineScheduler.h:119
LLVM_DEBUG
#define LLVM_DEBUG(X)
Definition: Debug.h:101
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
llvm::ReadyQueue::getID
unsigned getID() const
Definition: MachineScheduler.h:540
llvm::VLIWResourceModel::TII
const TargetInstrInfo * TII
Definition: VLIWMachineScheduler.h:33
llvm::ConvergingVLIWScheduler::Bot
VLIWSchedBoundary Bot
Definition: VLIWMachineScheduler.h:212
HexagonInstrInfo.h
llvm::ConvergingVLIWScheduler::Top
VLIWSchedBoundary Top
Definition: VLIWMachineScheduler.h:211
llvm::HexagonSubtarget::getInstrInfo
const HexagonInstrInfo * getInstrInfo() const override
Definition: HexagonSubtarget.h:124
llvm::VLIWResourceModel
Definition: VLIWMachineScheduler.h:31
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:640
llvm::VLIWResourceModel::isResourceAvailable
virtual bool isResourceAvailable(SUnit *SU, bool IsTop)
Check if scheduling of this SU is possible in the current packet.
Definition: VLIWMachineScheduler.cpp:109
llvm::ConvergingVLIWScheduler::BotQID
@ BotQID
Definition: VLIWMachineScheduler.h:219
llvm::TargetSchedModel
Provide an instruction scheduling machine model to CodeGen passes.
Definition: TargetSchedule.h:30
llvm::ConvergingVLIWScheduler::SchedulingCost
virtual int SchedulingCost(ReadyQueue &Q, SUnit *SU, SchedCandidate &Candidate, RegPressureDelta &Delta, bool verbose)
Single point to compute overall scheduling cost.
Definition: VLIWMachineScheduler.cpp:597
llvm::SUnit::getInstr
MachineInstr * getInstr() const
Returns the representative MachineInstr for this SUnit.
Definition: ScheduleDAG.h:373
llvm::SUnit::isScheduled
bool isScheduled
True once scheduled.
Definition: ScheduleDAG.h:284
HexagonMachineScheduler.h
llvm::HexagonInstrInfo
Definition: HexagonInstrInfo.h:38
llvm::ConvergingVLIWScheduler::DAG
VLIWMachineScheduler * DAG
Definition: VLIWMachineScheduler.h:207
llvm::ScheduleDAG::MF
MachineFunction & MF
Machine function.
Definition: ScheduleDAG.h:560
llvm::HexagonVLIWResourceModel
Definition: HexagonMachineScheduler.h:25
llvm::TargetSubtargetInfo
TargetSubtargetInfo - Generic base class for all target subtargets.
Definition: TargetSubtargetInfo.h:60
llvm::ConvergingVLIWScheduler::VLIWSchedBoundary::ResourceModel
VLIWResourceModel * ResourceModel
Definition: VLIWMachineScheduler.h:135
llvm::RegPressureDelta
Store the effects of a change in pressure on things that MI scheduler cares about.
Definition: RegisterPressure.h:238
llvm::ConvergingVLIWScheduler::TopQID
@ TopQID
Definition: VLIWMachineScheduler.h:219
VLIWMachineScheduler.h
llvm::ConvergingVLIWScheduler::SchedModel
const TargetSchedModel * SchedModel
Definition: VLIWMachineScheduler.h:208
MachineScheduler.h
llvm::SUnit::isInstr
bool isInstr() const
Returns true if this SUnit refers to a machine instruction as opposed to an SDNode.
Definition: ScheduleDAG.h:362
llvm::HexagonConvergingVLIWScheduler::SchedulingCost
int SchedulingCost(ReadyQueue &Q, SUnit *SU, SchedCandidate &Candidate, RegPressureDelta &Delta, bool verbose) override
Single point to compute overall scheduling cost.
Definition: HexagonMachineScheduler.cpp:45
llvm::HexagonSubtarget
Definition: HexagonSubtarget.h:43
llvm::HexagonVLIWResourceModel::hasDependence
bool hasDependence(const SUnit *SUd, const SUnit *SUu) override
Return true if there is a dependence between SUd and SUu.
Definition: HexagonMachineScheduler.cpp:26
llvm::SUnit
Scheduling unit. This is a node in the scheduling DAG.
Definition: ScheduleDAG.h:242
llvm::ReadyQueue
Helpers for implementing custom MachineSchedStrategy classes.
Definition: MachineScheduler.h:532