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HexagonShuffler.h
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1 //===- HexagonShuffler.h - Instruction bundle shuffling ---------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This implements the shuffling of insns inside a bundle according to the
10 // packet formation rules of the Hexagon ISA.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONSHUFFLER_H
15 #define LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONSHUFFLER_H
16 
19 #include "llvm/ADT/DenseMap.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/ADT/SmallVector.h"
22 #include "llvm/ADT/StringRef.h"
24 #include "llvm/Support/SMLoc.h"
25 #include <cstdint>
26 #include <functional>
27 #include <utility>
28 
29 namespace llvm {
30 
31 class MCContext;
32 class MCInst;
33 class MCInstrInfo;
34 class MCSubtargetInfo;
35 
36 // Insn resources.
38  // Mask of the slots or units that may execute the insn and
39  // the weight or priority that the insn requires to be assigned a slot.
40  unsigned Slots, Weight;
41 
42 public:
43  HexagonResource(unsigned s) { setUnits(s); }
44 
45  void setUnits(unsigned s) {
46  Slots = s & ((1u << HEXAGON_PACKET_SIZE) - 1);
47  setWeight(s);
48  }
49 
50  void setAllUnits() {
51  setUnits(((1u << HEXAGON_PACKET_SIZE) - 1));
52  }
53  unsigned setWeight(unsigned s);
54 
55  unsigned getUnits() const { return (Slots); }
56  unsigned getWeight() const { return (Weight); }
57 
58  // Check if the resources are in ascending slot order.
59  static bool lessUnits(const HexagonResource &A, const HexagonResource &B) {
60  return (countPopulation(A.getUnits()) < countPopulation(B.getUnits()));
61  }
62 
63  // Check if the resources are in ascending weight order.
64  static bool lessWeight(const HexagonResource &A, const HexagonResource &B) {
65  return (A.getWeight() < B.getWeight());
66  }
67 };
68 
69 // HVX insn resources.
71 public:
72  using UnitsAndLanes = std::pair<unsigned, unsigned>;
73 
74 private:
75  // Available HVX slots.
76  enum {
77  CVI_NONE = 0,
78  CVI_XLANE = 1 << 0,
79  CVI_SHIFT = 1 << 1,
80  CVI_MPY0 = 1 << 2,
81  CVI_MPY1 = 1 << 3,
82  CVI_ZW = 1 << 4
83  };
84 
85  // Count of adjacent slots that the insn requires to be executed.
86  unsigned Lanes;
87  // Flag whether the insn is a load or a store.
88  bool Load, Store;
89  // Flag whether the HVX resources are valid.
90  bool Valid;
91 
92  void setLanes(unsigned l) { Lanes = l; }
93  void setLoad(bool f = true) { Load = f; }
94  void setStore(bool f = true) { Store = f; }
95 
96 public:
97  HexagonCVIResource(MCInstrInfo const &MCII,
98  MCSubtargetInfo const &STI,
99  unsigned s, MCInst const *id);
100 
101  bool isValid() const { return Valid; }
102  unsigned getLanes() const { return Lanes; }
103  bool mayLoad() const { return Load; }
104  bool mayStore() const { return Store; }
105 };
106 
107 // Handle to an insn used by the shuffling algorithm.
109  friend class HexagonShuffler;
110 
111  MCInst const *ID;
112  MCInst const *Extender;
113  HexagonResource Core;
114  HexagonCVIResource CVI;
115 
116 public:
118  MCSubtargetInfo const &STI, MCInst const *id,
119  MCInst const *Extender, unsigned s)
120  : ID(id), Extender(Extender), Core(s), CVI(MCII, STI, s, id){};
121 
122  MCInst const &getDesc() const { return *ID; }
123  MCInst const *getExtender() const { return Extender; }
124 
125  // Check if the handles are in ascending order for shuffling purposes.
126  bool operator<(const HexagonInstr &B) const {
127  return (HexagonResource::lessWeight(B.Core, Core));
128  }
129 
130  // Check if the handles are in ascending order by core slots.
131  static bool lessCore(const HexagonInstr &A, const HexagonInstr &B) {
132  return (HexagonResource::lessUnits(A.Core, B.Core));
133  }
134 
135  // Check if the handles are in ascending order by HVX slots.
136  static bool lessCVI(const HexagonInstr &A, const HexagonInstr &B) {
137  return (HexagonResource::lessUnits(A.CVI, B.CVI));
138  }
139 };
140 
141 // Bundle shuffler.
143  using HexagonPacket =
145 
146  struct HexagonPacketSummary {
147  // Number of memory operations, loads, solo loads, stores, solo stores,
148  // single stores.
149  unsigned memory;
150  unsigned loads;
151  unsigned load0;
152  unsigned stores;
153  unsigned store0;
154  unsigned store1;
155  unsigned NonZCVIloads;
156  unsigned AllCVIloads;
157  unsigned CVIstores;
158  // Number of duplex insns
159  unsigned duplex;
160  unsigned pSlot3Cnt;
161  Optional<HexagonInstr *> PrefSlot3Inst;
162  unsigned memops;
163  unsigned ReservedSlotMask;
165  Optional<SMLoc> Slot1AOKLoc;
166  Optional<SMLoc> NoSlot1StoreLoc;
167  };
168  // Insn handles in a bundle.
169  HexagonPacket Packet;
170 
171 protected:
173  int64_t BundleFlags;
179  std::vector<std::pair<SMLoc, std::string>> AppliedRestrictions;
180  bool applySlotRestrictions(HexagonPacketSummary const &Summary);
181  void restrictSlot1AOK(HexagonPacketSummary const &Summary);
182  void restrictNoSlot1Store(HexagonPacketSummary const &Summary);
183  void restrictNoSlot1();
184  bool restrictStoreLoadOrder(HexagonPacketSummary const &Summary);
185  void restrictBranchOrder(HexagonPacketSummary const &Summary);
186  void restrictPreferSlot3(HexagonPacketSummary const &Summary);
187  void permitNonSlot();
188 
189  Optional<HexagonPacket> tryAuction(HexagonPacketSummary const &Summary) const;
190 
191  HexagonPacketSummary GetPacketSummary();
192  bool ValidPacketMemoryOps(HexagonPacketSummary const &Summary) const;
193  bool ValidResourceUsage(HexagonPacketSummary const &Summary);
194  bool validPacketInsts() const;
195 
196 public:
201 
203  MCInstrInfo const &MCII, MCSubtargetInfo const &STI);
204 
205  // Reset to initial state.
206  void reset();
207  // Check if the bundle may be validly shuffled.
208  bool check();
209  // Reorder the insn handles in the bundle.
210  bool shuffle();
211 
212  unsigned size() const { return (Packet.size()); }
213 
214  bool isMemReorderDisabled() const {
216  }
217 
218  iterator begin() { return (Packet.begin()); }
219  iterator end() { return (Packet.end()); }
220  const_iterator cbegin() const { return (Packet.begin()); }
221  const_iterator cend() const { return (Packet.end()); }
223  return make_range(P.begin(), P.end());
224  }
226  return make_range(P.begin(), P.end());
227  }
228  packet_range insts() { return make_range(begin(), end()); }
229  const_packet_range insts() const { return make_range(cbegin(), cend()); }
230 
231  using InstPredicate = bool (*)(MCInstrInfo const &, MCInst const &);
232 
233  bool HasInstWith(InstPredicate Pred) const {
234  return llvm::any_of(insts(), [&](HexagonInstr const &I) {
235  MCInst const &Inst = I.getDesc();
236  return (*Pred)(MCII, Inst);
237  });
238  }
239 
240  // Add insn handle to the bundle .
241  void append(MCInst const &ID, MCInst const *Extender, unsigned S);
242 
243  // Return the error code for the last check or shuffling of the bundle.
244  void reportError(Twine const &Msg);
245 };
246 
247 } // end namespace llvm
248 
249 #endif // LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONSHUFFLER_H
HexagonMCTargetDesc.h
llvm::HexagonShuffler::MCII
const MCInstrInfo & MCII
Definition: HexagonShuffler.h:174
llvm::HexagonShuffler::cend
const_iterator cend() const
Definition: HexagonShuffler.h:221
llvm::HexagonShuffler::begin
iterator begin()
Definition: HexagonShuffler.h:218
llvm::HexagonShuffler::GetPacketSummary
HexagonPacketSummary GetPacketSummary()
Definition: HexagonShuffler.cpp:441
MathExtras.h
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
llvm::HexagonShuffler::reportError
void reportError(Twine const &Msg)
Definition: HexagonShuffler.cpp:687
llvm::HexagonShuffler::shuffle
bool shuffle()
Definition: HexagonShuffler.cpp:634
llvm::make_range
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
Definition: iterator_range.h:53
llvm::HexagonCVIResource::HexagonCVIResource
HexagonCVIResource(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, unsigned s, MCInst const *id)
Definition: HexagonShuffler.cpp:108
llvm::HexagonShuffler::CheckFailure
bool CheckFailure
Definition: HexagonShuffler.h:178
llvm::HexagonCVIResource::mayLoad
bool mayLoad() const
Definition: HexagonShuffler.h:103
llvm::HexagonShuffler::restrictStoreLoadOrder
bool restrictStoreLoadOrder(HexagonPacketSummary const &Summary)
Definition: HexagonShuffler.cpp:355
llvm::HexagonShuffler::Loc
SMLoc Loc
Definition: HexagonShuffler.h:176
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:72
llvm::HexagonResource::setUnits
void setUnits(unsigned s)
Definition: HexagonShuffler.h:45
StringRef.h
P
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
Definition: README-SSE.txt:411
llvm::HexagonShuffler::isMemReorderDisabled
bool isMemReorderDisabled() const
Definition: HexagonShuffler.h:214
llvm::SmallVector< HexagonInstr, HEXAGON_PRESHUFFLE_PACKET_SIZE >
llvm::HexagonShuffler::iterator
HexagonPacket::iterator iterator
Definition: HexagonShuffler.h:197
llvm::HexagonShuffler::restrictNoSlot1Store
void restrictNoSlot1Store(HexagonPacketSummary const &Summary)
Definition: HexagonShuffler.cpp:217
stores
hexagon widen stores
Definition: HexagonStoreWidening.cpp:118
llvm::HexagonShuffler::insts
const_packet_range insts(HexagonPacket const &P) const
Definition: HexagonShuffler.h:225
llvm::HexagonShuffler::insts
const_packet_range insts() const
Definition: HexagonShuffler.h:229
DenseMap.h
llvm::HexagonResource::getUnits
unsigned getUnits() const
Definition: HexagonShuffler.h:55
llvm::Optional
Definition: APInt.h:33
STLExtras.h
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
llvm::HexagonShuffler::permitNonSlot
void permitNonSlot()
Definition: HexagonShuffler.cpp:310
llvm::HexagonCVIResource::isValid
bool isValid() const
Definition: HexagonShuffler.h:101
llvm::HexagonInstr::lessCVI
static bool lessCVI(const HexagonInstr &A, const HexagonInstr &B)
Definition: HexagonShuffler.h:136
llvm::SMLoc
Represents a location in source code.
Definition: SMLoc.h:23
llvm::HexagonShuffler::restrictSlot1AOK
void restrictSlot1AOK(HexagonPacketSummary const &Summary)
Definition: HexagonShuffler.cpp:194
f
Itanium Name Demangler i e convert the string _Z1fv into f()". You can also use the CRTP base ManglingParser to perform some simple analysis on the mangled name
HexagonMCInstrInfo.h
llvm::HexagonShuffler::restrictBranchOrder
void restrictBranchOrder(HexagonPacketSummary const &Summary)
Definition: HexagonShuffler.cpp:269
llvm::HexagonCVIResource::mayStore
bool mayStore() const
Definition: HexagonShuffler.h:104
llvm::HexagonShuffler::size
unsigned size() const
Definition: HexagonShuffler.h:212
llvm::HexagonShuffler::insts
packet_range insts()
Definition: HexagonShuffler.h:228
l
This requires reassociating to forms of expressions that are already something that reassoc doesn t think about yet These two functions should generate the same code on big endian int * l
Definition: README.txt:100
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
llvm::HexagonShuffler
Definition: HexagonShuffler.h:142
SMLoc.h
llvm::HexagonShuffler::Context
MCContext & Context
Definition: HexagonShuffler.h:172
llvm::HexagonShuffler::check
bool check()
Check that the packet is legal and enforce relative insn order.
Definition: HexagonShuffler.cpp:593
llvm::HexagonResource::setAllUnits
void setAllUnits()
Definition: HexagonShuffler.h:50
llvm::HexagonInstr::operator<
bool operator<(const HexagonInstr &B) const
Definition: HexagonShuffler.h:126
llvm::HexagonShuffler::end
iterator end()
Definition: HexagonShuffler.h:219
llvm::HexagonResource::lessWeight
static bool lessWeight(const HexagonResource &A, const HexagonResource &B)
Definition: HexagonShuffler.h:64
llvm::countPopulation
unsigned countPopulation(T Value)
Count the number of set bits in a value.
Definition: MathExtras.h:567
llvm::HexagonShuffler::InstPredicate
bool(*)(MCInstrInfo const &, MCInst const &) InstPredicate
Definition: HexagonShuffler.h:231
llvm::HexagonInstr
Definition: HexagonShuffler.h:108
s
multiplies can be turned into SHL s
Definition: README.txt:370
llvm::HexagonShuffler::cbegin
const_iterator cbegin() const
Definition: HexagonShuffler.h:220
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::HexagonShuffler::applySlotRestrictions
bool applySlotRestrictions(HexagonPacketSummary const &Summary)
Definition: HexagonShuffler.cpp:247
llvm::HexagonShuffler::AppliedRestrictions
std::vector< std::pair< SMLoc, std::string > > AppliedRestrictions
Definition: HexagonShuffler.h:179
llvm::SmallVectorImpl< HexagonInstr >::const_iterator
typename SuperClass::const_iterator const_iterator
Definition: SmallVector.h:563
llvm::SPII::Store
@ Store
Definition: SparcInstrInfo.h:33
llvm::HexagonShuffler::HasInstWith
bool HasInstWith(InstPredicate Pred) const
Definition: HexagonShuffler.h:233
llvm::HexagonShuffler::BundleFlags
int64_t BundleFlags
Definition: HexagonShuffler.h:173
llvm::HexagonCVIResource::getLanes
unsigned getLanes() const
Definition: HexagonShuffler.h:102
llvm::HexagonShuffler::STI
const MCSubtargetInfo & STI
Definition: HexagonShuffler.h:175
llvm::HexagonShuffler::append
void append(MCInst const &ID, MCInst const *Extender, unsigned S)
Definition: HexagonShuffler.cpp:180
llvm::HexagonShuffler::ValidResourceUsage
bool ValidResourceUsage(HexagonPacketSummary const &Summary)
Definition: HexagonShuffler.cpp:318
llvm::any_of
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1556
llvm::HexagonResource
Definition: HexagonShuffler.h:37
llvm::HexagonResource::setWeight
unsigned setWeight(unsigned s)
Definition: HexagonShuffler.cpp:90
A
* A
Definition: README_ALTIVEC.txt:89
llvm::HexagonCVIResource
Definition: HexagonShuffler.h:70
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
llvm::HexagonShuffler::reset
void reset()
Definition: HexagonShuffler.cpp:174
llvm::HexagonResource::getWeight
unsigned getWeight() const
Definition: HexagonShuffler.h:56
llvm::Twine
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:83
llvm::HexagonMCInstrInfo::memReorderDisabledMask
const int64_t memReorderDisabledMask
Definition: HexagonMCInstrInfo.h:76
llvm::MCInstrInfo
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:25
llvm::HexagonInstr::getDesc
const MCInst & getDesc() const
Definition: HexagonShuffler.h:122
llvm::HexagonShuffler::ValidPacketMemoryOps
bool ValidPacketMemoryOps(HexagonPacketSummary const &Summary) const
Definition: HexagonShuffler.cpp:555
llvm::HexagonShuffler::HexagonShuffler
HexagonShuffler(MCContext &Context, bool ReportErrors, MCInstrInfo const &MCII, MCSubtargetInfo const &STI)
Definition: HexagonShuffler.cpp:167
llvm::HexagonInstr::HexagonInstr
HexagonInstr(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst const *id, MCInst const *Extender, unsigned s)
Definition: HexagonShuffler.h:117
llvm::HexagonShuffler::ReportErrors
bool ReportErrors
Definition: HexagonShuffler.h:177
SmallVector.h
llvm::SmallVectorImpl< HexagonInstr >::iterator
typename SuperClass::iterator iterator
Definition: SmallVector.h:562
llvm::HexagonShuffler::validPacketInsts
bool validPacketInsts() const
llvm::iterator_range
A range adaptor for a pair of iterators.
Definition: iterator_range.h:30
llvm::HexagonInstr::lessCore
static bool lessCore(const HexagonInstr &A, const HexagonInstr &B)
Definition: HexagonShuffler.h:131
llvm::HexagonShuffler::restrictPreferSlot3
void restrictPreferSlot3(HexagonPacketSummary const &Summary)
Definition: HexagonShuffler.cpp:568
llvm::HexagonResource::lessUnits
static bool lessUnits(const HexagonResource &A, const HexagonResource &B)
Definition: HexagonShuffler.h:59
llvm::HexagonCVIResource::UnitsAndLanes
std::pair< unsigned, unsigned > UnitsAndLanes
Definition: HexagonShuffler.h:72
llvm::HexagonInstr::getExtender
const MCInst * getExtender() const
Definition: HexagonShuffler.h:123
HEXAGON_PACKET_SIZE
#define HEXAGON_PACKET_SIZE
Definition: HexagonMCTargetDesc.h:36
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:75
llvm::HexagonResource::HexagonResource
HexagonResource(unsigned s)
Definition: HexagonShuffler.h:43
llvm::HexagonShuffler::tryAuction
Optional< HexagonPacket > tryAuction(HexagonPacketSummary const &Summary) const
Definition: HexagonShuffler.cpp:609
llvm::HexagonShuffler::insts
packet_range insts(HexagonPacket &P)
Definition: HexagonShuffler.h:222
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:37
llvm::HexagonShuffler::const_iterator
HexagonPacket::const_iterator const_iterator
Definition: HexagonShuffler.h:198
llvm::HexagonShuffler::restrictNoSlot1
void restrictNoSlot1()