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14 #ifndef LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONSHUFFLER_H
15 #define LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONSHUFFLER_H
34 class MCSubtargetInfo;
40 unsigned Slots, Weight;
65 return (A.getWeight() <
B.getWeight());
82 void setLanes(
unsigned l) { Lanes =
l; }
83 void setLoad(
bool f =
true) { Load =
f; }
84 void setStore(
bool f =
true) { Store =
f; }
88 MCSubtargetInfo
const &STI,
89 unsigned s, MCInst
const *
id);
109 MCInst const *Extender,
unsigned s)
110 :
ID(id), Extender(Extender), Core(
s), CVI(MCII, STI,
s, id){};
136 struct HexagonPacketSummary {
145 unsigned NonZCVIloads;
146 unsigned AllCVIloads;
153 unsigned ReservedSlotMask;
172 const bool DoShuffle);
179 const bool DoShuffle);
200 bool check(
const bool RequireShuffle =
true);
204 unsigned size()
const {
return (Packet.size()); }
227 MCInst const &Inst =
I.getDesc();
228 return (*Pred)(
MCII, Inst);
243 #endif // LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONSHUFFLER_H
const_iterator cend() const
HexagonPacketSummary GetPacketSummary()
This is an optimization pass for GlobalISel generic memory operations.
void reportError(Twine const &Msg)
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
HexagonCVIResource(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, unsigned s, MCInst const *id)
bool restrictStoreLoadOrder(HexagonPacketSummary const &Summary)
Context object for machine code objects.
void setUnits(unsigned s)
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
bool isMemReorderDisabled() const
HexagonPacket::iterator iterator
void reportResourceUsage(HexagonPacketSummary const &Summary)
void restrictNoSlot1Store(HexagonPacketSummary const &Summary)
const_packet_range insts(HexagonPacket const &P) const
const_packet_range insts() const
unsigned getUnits() const
Instances of this class represent a single low-level machine instruction.
static bool lessCVI(const HexagonInstr &A, const HexagonInstr &B)
Represents a location in source code.
void restrictSlot1AOK(HexagonPacketSummary const &Summary)
Itanium Name Demangler i e convert the string _Z1fv into f()". You can also use the CRTP base ManglingParser to perform some simple analysis on the mangled name
void restrictBranchOrder(HexagonPacketSummary const &Summary)
This requires reassociating to forms of expressions that are already something that reassoc doesn t think about yet These two functions should generate the same code on big endian int * l
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
constexpr int64_t memReorderDisabledMask
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
bool operator<(const HexagonInstr &B) const
void reportResourceError(HexagonPacketSummary const &Summary, StringRef Err)
static bool lessWeight(const HexagonResource &A, const HexagonResource &B)
unsigned countPopulation(T Value)
Count the number of set bits in a value.
bool(*)(MCInstrInfo const &, MCInst const &) InstPredicate
multiplies can be turned into SHL s
bool applySlotRestrictions(HexagonPacketSummary const &Summary, const bool DoShuffle)
const_iterator cbegin() const
Optional< HexagonPacket > tryAuction(HexagonPacketSummary const &Summary)
std::vector< std::pair< SMLoc, std::string > > AppliedRestrictions
typename SuperClass::const_iterator const_iterator
bool HasInstWith(InstPredicate Pred) const
unsigned getLanes() const
const MCSubtargetInfo & STI
void append(MCInst const &ID, MCInst const *Extender, unsigned S)
bool ValidResourceUsage(HexagonPacketSummary const &Summary)
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
StringRef - Represent a constant reference to a string, i.e.
unsigned setWeight(unsigned s)
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
unsigned getWeight() const
const CustomOperand< const MCSubtargetInfo & > Msg[]
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Interface to description of machine instruction set.
const MCInst & getDesc() const
void restrictPreferSlot3(HexagonPacketSummary const &Summary, const bool DoShuffle)
bool ValidPacketMemoryOps(HexagonPacketSummary const &Summary) const
HexagonShuffler(MCContext &Context, bool ReportErrors, MCInstrInfo const &MCII, MCSubtargetInfo const &STI)
HexagonInstr(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst const *id, MCInst const *Extender, unsigned s)
typename SuperClass::iterator iterator
A range adaptor for a pair of iterators.
static bool lessCore(const HexagonInstr &A, const HexagonInstr &B)
static bool lessUnits(const HexagonResource &A, const HexagonResource &B)
std::pair< unsigned, unsigned > UnitsAndLanes
const MCInst * getExtender() const
#define HEXAGON_PACKET_SIZE
bool check(const bool RequireShuffle=true)
Check that the packet is legal and enforce relative insn order.
Generic base class for all target subtargets.
HexagonResource(unsigned s)
packet_range insts(HexagonPacket &P)
HexagonPacket::const_iterator const_iterator