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HexagonShuffler.h
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1 //===- HexagonShuffler.h - Instruction bundle shuffling ---------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This implements the shuffling of insns inside a bundle according to the
10 // packet formation rules of the Hexagon ISA.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONSHUFFLER_H
15 #define LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONSHUFFLER_H
16 
19 #include "llvm/ADT/DenseMap.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/ADT/SmallVector.h"
22 #include "llvm/ADT/StringRef.h"
24 #include "llvm/Support/SMLoc.h"
25 #include <cstdint>
26 #include <functional>
27 #include <utility>
28 
29 namespace llvm {
30 
31 class MCContext;
32 class MCInst;
33 class MCInstrInfo;
34 class MCSubtargetInfo;
35 
36 // Insn resources.
38  // Mask of the slots or units that may execute the insn and
39  // the weight or priority that the insn requires to be assigned a slot.
40  unsigned Slots, Weight;
41 
42 public:
43  HexagonResource(unsigned s) { setUnits(s); }
44 
45  void setUnits(unsigned s) {
46  Slots = s & ((1u << HEXAGON_PACKET_SIZE) - 1);
47  setWeight(s);
48  }
49 
50  void setAllUnits() {
51  setUnits(((1u << HEXAGON_PACKET_SIZE) - 1));
52  }
53  unsigned setWeight(unsigned s);
54 
55  unsigned getUnits() const { return (Slots); }
56  unsigned getWeight() const { return (Weight); }
57 
58  // Check if the resources are in ascending slot order.
59  static bool lessUnits(const HexagonResource &A, const HexagonResource &B) {
60  return (countPopulation(A.getUnits()) < countPopulation(B.getUnits()));
61  }
62 
63  // Check if the resources are in ascending weight order.
64  static bool lessWeight(const HexagonResource &A, const HexagonResource &B) {
65  return (A.getWeight() < B.getWeight());
66  }
67 };
68 
69 // HVX insn resources.
71 public:
72  using UnitsAndLanes = std::pair<unsigned, unsigned>;
73 
74 private:
75  // Count of adjacent slots that the insn requires to be executed.
76  unsigned Lanes;
77  // Flag whether the insn is a load or a store.
78  bool Load, Store;
79  // Flag whether the HVX resources are valid.
80  bool Valid;
81 
82  void setLanes(unsigned l) { Lanes = l; }
83  void setLoad(bool f = true) { Load = f; }
84  void setStore(bool f = true) { Store = f; }
85 
86 public:
87  HexagonCVIResource(MCInstrInfo const &MCII,
88  MCSubtargetInfo const &STI,
89  unsigned s, MCInst const *id);
90 
91  bool isValid() const { return Valid; }
92  unsigned getLanes() const { return Lanes; }
93  bool mayLoad() const { return Load; }
94  bool mayStore() const { return Store; }
95 };
96 
97 // Handle to an insn used by the shuffling algorithm.
98 class HexagonInstr {
99  friend class HexagonShuffler;
100 
101  MCInst const *ID;
102  MCInst const *Extender;
103  HexagonResource Core;
104  HexagonCVIResource CVI;
105 
106 public:
108  MCSubtargetInfo const &STI, MCInst const *id,
109  MCInst const *Extender, unsigned s)
110  : ID(id), Extender(Extender), Core(s), CVI(MCII, STI, s, id){};
111 
112  MCInst const &getDesc() const { return *ID; }
113  MCInst const *getExtender() const { return Extender; }
114 
115  // Check if the handles are in ascending order for shuffling purposes.
116  bool operator<(const HexagonInstr &B) const {
117  return (HexagonResource::lessWeight(B.Core, Core));
118  }
119 
120  // Check if the handles are in ascending order by core slots.
121  static bool lessCore(const HexagonInstr &A, const HexagonInstr &B) {
122  return (HexagonResource::lessUnits(A.Core, B.Core));
123  }
124 
125  // Check if the handles are in ascending order by HVX slots.
126  static bool lessCVI(const HexagonInstr &A, const HexagonInstr &B) {
127  return (HexagonResource::lessUnits(A.CVI, B.CVI));
128  }
129 };
130 
131 // Bundle shuffler.
133  using HexagonPacket =
135 
136  struct HexagonPacketSummary {
137  // Number of memory operations, loads, solo loads, stores, solo stores,
138  // single stores.
139  unsigned memory;
140  unsigned loads;
141  unsigned load0;
142  unsigned stores;
143  unsigned store0;
144  unsigned store1;
145  unsigned NonZCVIloads;
146  unsigned AllCVIloads;
147  unsigned CVIstores;
148  // Number of duplex insns
149  unsigned duplex;
150  unsigned pSlot3Cnt;
151  Optional<HexagonInstr *> PrefSlot3Inst;
152  unsigned memops;
153  unsigned ReservedSlotMask;
155  Optional<SMLoc> Slot1AOKLoc;
156  Optional<SMLoc> NoSlot1StoreLoc;
157  };
158  // Insn handles in a bundle.
159  HexagonPacket Packet;
160 
161 protected:
163  int64_t BundleFlags;
169  std::vector<std::pair<SMLoc, std::string>> AppliedRestrictions;
170 
171  bool applySlotRestrictions(HexagonPacketSummary const &Summary,
172  const bool DoShuffle);
173  void restrictSlot1AOK(HexagonPacketSummary const &Summary);
174  void restrictNoSlot1Store(HexagonPacketSummary const &Summary);
175  void restrictNoSlot1();
176  bool restrictStoreLoadOrder(HexagonPacketSummary const &Summary);
177  void restrictBranchOrder(HexagonPacketSummary const &Summary);
178  void restrictPreferSlot3(HexagonPacketSummary const &Summary,
179  const bool DoShuffle);
180  void permitNonSlot();
181 
182  Optional<HexagonPacket> tryAuction(HexagonPacketSummary const &Summary);
183 
184  HexagonPacketSummary GetPacketSummary();
185  bool ValidPacketMemoryOps(HexagonPacketSummary const &Summary) const;
186  bool ValidResourceUsage(HexagonPacketSummary const &Summary);
187 
188 public:
193 
195  MCInstrInfo const &MCII, MCSubtargetInfo const &STI);
196 
197  // Reset to initial state.
198  void reset();
199  // Check if the bundle may be validly shuffled.
200  bool check(const bool RequireShuffle = true);
201  // Reorder the insn handles in the bundle.
202  bool shuffle();
203 
204  unsigned size() const { return (Packet.size()); }
205 
206  bool isMemReorderDisabled() const {
208  }
209 
210  iterator begin() { return (Packet.begin()); }
211  iterator end() { return (Packet.end()); }
212  const_iterator cbegin() const { return (Packet.begin()); }
213  const_iterator cend() const { return (Packet.end()); }
215  return make_range(P.begin(), P.end());
216  }
218  return make_range(P.begin(), P.end());
219  }
220  packet_range insts() { return make_range(begin(), end()); }
221  const_packet_range insts() const { return make_range(cbegin(), cend()); }
222 
223  using InstPredicate = bool (*)(MCInstrInfo const &, MCInst const &);
224 
225  bool HasInstWith(InstPredicate Pred) const {
226  return llvm::any_of(insts(), [&](HexagonInstr const &I) {
227  MCInst const &Inst = I.getDesc();
228  return (*Pred)(MCII, Inst);
229  });
230  }
231 
232  // Add insn handle to the bundle .
233  void append(MCInst const &ID, MCInst const *Extender, unsigned S);
234 
235  // Return the error code for the last check or shuffling of the bundle.
236  void reportError(Twine const &Msg);
237  void reportResourceError(HexagonPacketSummary const &Summary, StringRef Err);
238  void reportResourceUsage(HexagonPacketSummary const &Summary);
239 };
240 
241 } // end namespace llvm
242 
243 #endif // LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONSHUFFLER_H
HexagonMCTargetDesc.h
llvm::HexagonShuffler::MCII
const MCInstrInfo & MCII
Definition: HexagonShuffler.h:164
llvm::HexagonShuffler::cend
const_iterator cend() const
Definition: HexagonShuffler.h:213
llvm::HexagonShuffler::begin
iterator begin()
Definition: HexagonShuffler.h:210
llvm::HexagonShuffler::GetPacketSummary
HexagonPacketSummary GetPacketSummary()
Definition: HexagonShuffler.cpp:451
MathExtras.h
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AllocatorList.h:23
llvm::HexagonShuffler::reportError
void reportError(Twine const &Msg)
Definition: HexagonShuffler.cpp:731
llvm::HexagonShuffler::shuffle
bool shuffle()
Definition: HexagonShuffler.cpp:652
llvm::make_range
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
Definition: iterator_range.h:53
llvm::HexagonCVIResource::HexagonCVIResource
HexagonCVIResource(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, unsigned s, MCInst const *id)
Definition: HexagonShuffler.cpp:108
llvm::HexagonShuffler::CheckFailure
bool CheckFailure
Definition: HexagonShuffler.h:168
llvm::HexagonCVIResource::mayLoad
bool mayLoad() const
Definition: HexagonShuffler.h:93
llvm::HexagonShuffler::restrictStoreLoadOrder
bool restrictStoreLoadOrder(HexagonPacketSummary const &Summary)
Definition: HexagonShuffler.cpp:356
llvm::HexagonShuffler::Loc
SMLoc Loc
Definition: HexagonShuffler.h:166
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:72
llvm::HexagonResource::setUnits
void setUnits(unsigned s)
Definition: HexagonShuffler.h:45
StringRef.h
P
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
Definition: README-SSE.txt:411
llvm::HexagonShuffler::isMemReorderDisabled
bool isMemReorderDisabled() const
Definition: HexagonShuffler.h:206
llvm::SmallVector< HexagonInstr, HEXAGON_PRESHUFFLE_PACKET_SIZE >
llvm::HexagonShuffler::iterator
HexagonPacket::iterator iterator
Definition: HexagonShuffler.h:189
llvm::HexagonShuffler::reportResourceUsage
void reportResourceUsage(HexagonPacketSummary const &Summary)
Definition: HexagonShuffler.cpp:712
llvm::HexagonShuffler::restrictNoSlot1Store
void restrictNoSlot1Store(HexagonPacketSummary const &Summary)
Definition: HexagonShuffler.cpp:218
stores
hexagon widen stores
Definition: HexagonStoreWidening.cpp:118
llvm::HexagonShuffler::insts
const_packet_range insts(HexagonPacket const &P) const
Definition: HexagonShuffler.h:217
llvm::HexagonShuffler::insts
const_packet_range insts() const
Definition: HexagonShuffler.h:221
DenseMap.h
llvm::HexagonResource::getUnits
unsigned getUnits() const
Definition: HexagonShuffler.h:55
llvm::Optional
Definition: APInt.h:33
STLExtras.h
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
llvm::HexagonShuffler::permitNonSlot
void permitNonSlot()
Definition: HexagonShuffler.cpp:310
llvm::HexagonCVIResource::isValid
bool isValid() const
Definition: HexagonShuffler.h:91
llvm::HexagonInstr::lessCVI
static bool lessCVI(const HexagonInstr &A, const HexagonInstr &B)
Definition: HexagonShuffler.h:126
llvm::SMLoc
Represents a location in source code.
Definition: SMLoc.h:23
llvm::HexagonShuffler::restrictSlot1AOK
void restrictSlot1AOK(HexagonPacketSummary const &Summary)
Definition: HexagonShuffler.cpp:195
f
Itanium Name Demangler i e convert the string _Z1fv into f()". You can also use the CRTP base ManglingParser to perform some simple analysis on the mangled name
HexagonMCInstrInfo.h
llvm::HexagonShuffler::restrictBranchOrder
void restrictBranchOrder(HexagonPacketSummary const &Summary)
Definition: HexagonShuffler.cpp:270
llvm::HexagonCVIResource::mayStore
bool mayStore() const
Definition: HexagonShuffler.h:94
llvm::HexagonShuffler::size
unsigned size() const
Definition: HexagonShuffler.h:204
llvm::HexagonShuffler::insts
packet_range insts()
Definition: HexagonShuffler.h:220
l
This requires reassociating to forms of expressions that are already something that reassoc doesn t think about yet These two functions should generate the same code on big endian int * l
Definition: README.txt:100
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
llvm::HexagonShuffler
Definition: HexagonShuffler.h:132
llvm::HexagonMCInstrInfo::memReorderDisabledMask
constexpr int64_t memReorderDisabledMask
Definition: HexagonMCInstrInfo.h:77
SMLoc.h
llvm::HexagonShuffler::Context
MCContext & Context
Definition: HexagonShuffler.h:162
llvm::HexagonResource::setAllUnits
void setAllUnits()
Definition: HexagonShuffler.h:50
llvm::HexagonInstr::operator<
bool operator<(const HexagonInstr &B) const
Definition: HexagonShuffler.h:116
llvm::HexagonShuffler::end
iterator end()
Definition: HexagonShuffler.h:211
llvm::HexagonShuffler::reportResourceError
void reportResourceError(HexagonPacketSummary const &Summary, StringRef Err)
Definition: HexagonShuffler.cpp:705
llvm::HexagonResource::lessWeight
static bool lessWeight(const HexagonResource &A, const HexagonResource &B)
Definition: HexagonShuffler.h:64
llvm::countPopulation
unsigned countPopulation(T Value)
Count the number of set bits in a value.
Definition: MathExtras.h:567
llvm::HexagonShuffler::InstPredicate
bool(*)(MCInstrInfo const &, MCInst const &) InstPredicate
Definition: HexagonShuffler.h:223
llvm::HexagonInstr
Definition: HexagonShuffler.h:98
s
multiplies can be turned into SHL s
Definition: README.txt:370
llvm::HexagonShuffler::applySlotRestrictions
bool applySlotRestrictions(HexagonPacketSummary const &Summary, const bool DoShuffle)
Definition: HexagonShuffler.cpp:248
llvm::HexagonShuffler::cbegin
const_iterator cbegin() const
Definition: HexagonShuffler.h:212
llvm::HexagonShuffler::tryAuction
Optional< HexagonPacket > tryAuction(HexagonPacketSummary const &Summary)
Definition: HexagonShuffler.cpp:627
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::HexagonShuffler::AppliedRestrictions
std::vector< std::pair< SMLoc, std::string > > AppliedRestrictions
Definition: HexagonShuffler.h:169
llvm::SmallVectorImpl< HexagonInstr >::const_iterator
typename SuperClass::const_iterator const_iterator
Definition: SmallVector.h:559
llvm::HexagonShuffler::HasInstWith
bool HasInstWith(InstPredicate Pred) const
Definition: HexagonShuffler.h:225
llvm::HexagonShuffler::BundleFlags
int64_t BundleFlags
Definition: HexagonShuffler.h:163
llvm::HexagonCVIResource::getLanes
unsigned getLanes() const
Definition: HexagonShuffler.h:92
llvm::HexagonShuffler::STI
const MCSubtargetInfo & STI
Definition: HexagonShuffler.h:165
llvm::HexagonShuffler::append
void append(MCInst const &ID, MCInst const *Extender, unsigned S)
Definition: HexagonShuffler.cpp:181
llvm::HexagonShuffler::ValidResourceUsage
bool ValidResourceUsage(HexagonPacketSummary const &Summary)
Definition: HexagonShuffler.cpp:318
llvm::any_of
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1656
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
llvm::HexagonResource
Definition: HexagonShuffler.h:37
llvm::HexagonResource::setWeight
unsigned setWeight(unsigned s)
Definition: HexagonShuffler.cpp:90
A
* A
Definition: README_ALTIVEC.txt:89
llvm::HexagonCVIResource
Definition: HexagonShuffler.h:70
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
llvm::HexagonShuffler::reset
void reset()
Definition: HexagonShuffler.cpp:175
llvm::HexagonResource::getWeight
unsigned getWeight() const
Definition: HexagonShuffler.h:56
llvm::Twine
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:83
llvm::MCInstrInfo
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:25
llvm::HexagonInstr::getDesc
const MCInst & getDesc() const
Definition: HexagonShuffler.h:112
llvm::HexagonShuffler::restrictPreferSlot3
void restrictPreferSlot3(HexagonPacketSummary const &Summary, const bool DoShuffle)
Definition: HexagonShuffler.cpp:584
llvm::HexagonShuffler::ValidPacketMemoryOps
bool ValidPacketMemoryOps(HexagonPacketSummary const &Summary) const
Definition: HexagonShuffler.cpp:571
llvm::HexagonShuffler::HexagonShuffler
HexagonShuffler(MCContext &Context, bool ReportErrors, MCInstrInfo const &MCII, MCSubtargetInfo const &STI)
Definition: HexagonShuffler.cpp:167
llvm::HexagonInstr::HexagonInstr
HexagonInstr(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst const *id, MCInst const *Extender, unsigned s)
Definition: HexagonShuffler.h:107
llvm::HexagonShuffler::ReportErrors
bool ReportErrors
Definition: HexagonShuffler.h:167
SmallVector.h
llvm::SmallVectorImpl< HexagonInstr >::iterator
typename SuperClass::iterator iterator
Definition: SmallVector.h:558
llvm::iterator_range
A range adaptor for a pair of iterators.
Definition: iterator_range.h:30
llvm::HexagonInstr::lessCore
static bool lessCore(const HexagonInstr &A, const HexagonInstr &B)
Definition: HexagonShuffler.h:121
llvm::HexagonResource::lessUnits
static bool lessUnits(const HexagonResource &A, const HexagonResource &B)
Definition: HexagonShuffler.h:59
llvm::HexagonCVIResource::UnitsAndLanes
std::pair< unsigned, unsigned > UnitsAndLanes
Definition: HexagonShuffler.h:72
llvm::HexagonInstr::getExtender
const MCInst * getExtender() const
Definition: HexagonShuffler.h:113
HEXAGON_PACKET_SIZE
#define HEXAGON_PACKET_SIZE
Definition: HexagonMCTargetDesc.h:36
llvm::HexagonShuffler::check
bool check(const bool RequireShuffle=true)
Check that the packet is legal and enforce relative insn order.
Definition: HexagonShuffler.cpp:610
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:75
llvm::HexagonResource::HexagonResource
HexagonResource(unsigned s)
Definition: HexagonShuffler.h:43
llvm::HexagonShuffler::insts
packet_range insts(HexagonPacket &P)
Definition: HexagonShuffler.h:214
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:38
llvm::HexagonShuffler::const_iterator
HexagonPacket::const_iterator const_iterator
Definition: HexagonShuffler.h:190
llvm::HexagonShuffler::restrictNoSlot1
void restrictNoSlot1()