LLVM  14.0.0git
HexagonMCInstrInfo.h
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1 //===- HexagonMCInstrInfo.cpp - Utility functions on Hexagon MCInsts ------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Utility functions for Hexagon specific MCInst queries
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCINSTRINFO_H
14 #define LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCINSTRINFO_H
15 
16 #include "llvm/ADT/SmallVector.h"
17 #include "llvm/ADT/StringRef.h"
19 #include "llvm/MC/MCInst.h"
21 #include <cstddef>
22 #include <cstdint>
23 
24 namespace llvm {
25 
26 class HexagonMCChecker;
27 class MCContext;
28 class MCExpr;
29 class MCInstrDesc;
30 class MCInstrInfo;
31 class MCRegisterInfo;
32 class MCSubtargetInfo;
33 
35 public:
37 
38  DuplexCandidate(unsigned i, unsigned j, unsigned iClass)
40 };
41 
42 namespace Hexagon {
43 
45  MCInstrInfo const &MCII;
46  MCInst::const_iterator BundleCurrent;
47  MCInst::const_iterator BundleEnd;
48  MCInst::const_iterator DuplexCurrent;
49  MCInst::const_iterator DuplexEnd;
50 
51 public:
52  PacketIterator(MCInstrInfo const &MCII, MCInst const &Inst);
53  PacketIterator(MCInstrInfo const &MCII, MCInst const &Inst, std::nullptr_t);
54 
56  MCInst const &operator*() const;
57  bool operator==(PacketIterator const &Other) const;
58  bool operator!=(PacketIterator const &Other) const {
59  return !(*this == Other);
60  }
61 };
62 
63 } // end namespace Hexagon
64 
65 namespace HexagonMCInstrInfo {
66 
67 size_t const innerLoopOffset = 0;
68 int64_t const innerLoopMask = 1 << innerLoopOffset;
69 
70 size_t const outerLoopOffset = 1;
71 int64_t const outerLoopMask = 1 << outerLoopOffset;
72 
73 // do not reorder memory load/stores by default load/stores are re-ordered
74 // and by default loads can be re-ordered
75 size_t const memReorderDisabledOffset = 2;
77 
78 size_t const bundleInstructionsOffset = 1;
79 
81 void addConstExtender(MCContext &Context, MCInstrInfo const &MCII, MCInst &MCB,
82  MCInst const &MCI);
83 
84 // Returns a iterator range of instructions in this bundle
86 bundleInstructions(MCInstrInfo const &MCII, MCInst const &MCI);
88 
89 // Returns the number of instructions in the bundle
90 size_t bundleSize(MCInst const &MCI);
91 
92 // Put the packet in to canonical form, compound, duplex, pad, and shuffle
93 bool canonicalizePacket(MCInstrInfo const &MCII, MCSubtargetInfo const &STI,
94  MCContext &Context, MCInst &MCB,
95  HexagonMCChecker *Checker,
96  bool AttemptCompatibility = false);
97 
98 // Create a duplex instruction given the two subinsts
99 MCInst *deriveDuplex(MCContext &Context, unsigned iClass, MCInst const &inst0,
100  MCInst const &inst1);
101 MCInst deriveExtender(MCInstrInfo const &MCII, MCInst const &Inst,
102  MCOperand const &MO);
103 
104 // Convert this instruction in to a duplex subinst
105 MCInst deriveSubInst(MCInst const &Inst);
106 
107 // Return the extender for instruction at Index or nullptr if none
108 MCInst const *extenderForIndex(MCInst const &MCB, size_t Index);
109 void extendIfNeeded(MCContext &Context, MCInstrInfo const &MCII, MCInst &MCB,
110  MCInst const &MCI);
111 
112 // Return memory access size in bytes
113 unsigned getMemAccessSize(MCInstrInfo const &MCII, MCInst const &MCI);
114 
115 // Return memory access size
116 unsigned getAddrMode(MCInstrInfo const &MCII, MCInst const &MCI);
117 
118 MCInstrDesc const &getDesc(MCInstrInfo const &MCII, MCInst const &MCI);
119 
120 // Return which duplex group this instruction belongs to
121 unsigned getDuplexCandidateGroup(MCInst const &MI);
122 
123 // Return a list of all possible instruction duplex combinations
125 getDuplexPossibilties(MCInstrInfo const &MCII, MCSubtargetInfo const &STI,
126  MCInst const &MCB);
127 unsigned getDuplexRegisterNumbering(unsigned Reg);
128 
129 MCExpr const &getExpr(MCExpr const &Expr);
130 
131 // Return the index of the extendable operand
132 unsigned short getExtendableOp(MCInstrInfo const &MCII, MCInst const &MCI);
133 
134 // Return a reference to the extendable operand
135 MCOperand const &getExtendableOperand(MCInstrInfo const &MCII,
136  MCInst const &MCI);
137 
138 // Return the implicit alignment of the extendable operand
139 unsigned getExtentAlignment(MCInstrInfo const &MCII, MCInst const &MCI);
140 
141 // Return the number of logical bits of the extendable operand
142 unsigned getExtentBits(MCInstrInfo const &MCII, MCInst const &MCI);
143 
144 // Check if the extendable operand is signed.
145 bool isExtentSigned(MCInstrInfo const &MCII, MCInst const &MCI);
146 
147 // Return the max value that a constant extendable operand can have
148 // without being extended.
149 int getMaxValue(MCInstrInfo const &MCII, MCInst const &MCI);
150 
151 // Return the min value that a constant extendable operand can have
152 // without being extended.
153 int getMinValue(MCInstrInfo const &MCII, MCInst const &MCI);
154 
155 // Return instruction name
156 StringRef getName(MCInstrInfo const &MCII, MCInst const &MCI);
157 
158 // Return the operand index for the new value.
159 unsigned short getNewValueOp(MCInstrInfo const &MCII, MCInst const &MCI);
160 
161 // Return the operand that consumes or produces a new value.
162 MCOperand const &getNewValueOperand(MCInstrInfo const &MCII, MCInst const &MCI);
163 unsigned short getNewValueOp2(MCInstrInfo const &MCII, MCInst const &MCI);
164 MCOperand const &getNewValueOperand2(MCInstrInfo const &MCII,
165  MCInst const &MCI);
166 
167 // Return the Hexagon ISA class for the insn.
168 unsigned getType(MCInstrInfo const &MCII, MCInst const &MCI);
169 
170 /// Return the resources used by this instruction
171 unsigned getCVIResources(MCInstrInfo const &MCII,
172  MCSubtargetInfo const &STI,
173  MCInst const &MCI);
174 
175 /// Return the slots used by the insn.
176 unsigned getUnits(MCInstrInfo const &MCII, MCSubtargetInfo const &STI,
177  MCInst const &MCI);
178 unsigned getOtherReservedSlots(MCInstrInfo const &MCII,
179  MCSubtargetInfo const &STI, MCInst const &MCI);
180 bool hasDuplex(MCInstrInfo const &MCII, MCInst const &MCI);
181 
182 // Does the packet have an extender for the instruction at Index
183 bool hasExtenderForIndex(MCInst const &MCB, size_t Index);
184 
185 bool hasImmExt(MCInst const &MCI);
186 
187 // Return whether the instruction is a legal new-value producer.
188 bool hasNewValue(MCInstrInfo const &MCII, MCInst const &MCI);
189 bool hasNewValue2(MCInstrInfo const &MCII, MCInst const &MCI);
190 bool hasTmpDst(MCInstrInfo const &MCII, MCInst const &MCI);
191 unsigned iClassOfDuplexPair(unsigned Ga, unsigned Gb);
192 
193 int64_t minConstant(MCInst const &MCI, size_t Index);
194 template <unsigned N, unsigned S>
195 bool inRange(MCInst const &MCI, size_t Index) {
196  return isShiftedUInt<N, S>(minConstant(MCI, Index));
197 }
198 template <unsigned N, unsigned S>
199 bool inSRange(MCInst const &MCI, size_t Index) {
200  return isShiftedInt<N, S>(minConstant(MCI, Index));
201 }
202 template <unsigned N> bool inRange(MCInst const &MCI, size_t Index) {
203  return isUInt<N>(minConstant(MCI, Index));
204 }
205 
206 // Return the instruction at Index
207 MCInst const &instruction(MCInst const &MCB, size_t Index);
208 bool isAccumulator(MCInstrInfo const &MCII, MCInst const &MCI);
209 
210 // Returns whether this MCInst is a wellformed bundle
211 bool isBundle(MCInst const &MCI);
212 
213 // Return whether the insn is an actual insn.
214 bool isCanon(MCInstrInfo const &MCII, MCInst const &MCI);
215 bool isCofMax1(MCInstrInfo const &MCII, MCInst const &MCI);
216 bool isCofRelax1(MCInstrInfo const &MCII, MCInst const &MCI);
217 bool isCofRelax2(MCInstrInfo const &MCII, MCInst const &MCI);
218 bool isCompound(MCInstrInfo const &MCII, MCInst const &MCI);
219 
220 // Return whether the instruction needs to be constant extended.
221 bool isConstExtended(MCInstrInfo const &MCII, MCInst const &MCI);
222 bool isCVINew(MCInstrInfo const &MCII, MCInst const &MCI);
223 
224 // Is this double register suitable for use in a duplex subinst
225 bool isDblRegForSubInst(unsigned Reg);
226 
227 // Is this a duplex instruction
228 bool isDuplex(MCInstrInfo const &MCII, MCInst const &MCI);
229 
230 // Can these instructions be duplexed
231 bool isDuplexPair(MCInst const &MIa, MCInst const &MIb);
232 
233 // Can these duplex classes be combine in to a duplex instruction
234 bool isDuplexPairMatch(unsigned Ga, unsigned Gb);
235 
236 // Return true if the insn may be extended based on the operand value.
237 bool isExtendable(MCInstrInfo const &MCII, MCInst const &MCI);
238 
239 // Return whether the instruction must be always extended.
240 bool isExtended(MCInstrInfo const &MCII, MCInst const &MCI);
241 
242 /// Return whether it is a floating-point insn.
243 bool isFloat(MCInstrInfo const &MCII, MCInst const &MCI);
244 
245 bool isHVX(MCInstrInfo const &MCII, MCInst const &MCI);
246 
247 // Returns whether this instruction is an immediate extender
248 bool isImmext(MCInst const &MCI);
249 
250 // Returns whether this bundle is an endloop0
251 bool isInnerLoop(MCInst const &MCI);
252 
253 // Is this an integer register
254 bool isIntReg(unsigned Reg);
255 
256 // Is this register suitable for use in a duplex subinst
257 bool isIntRegForSubInst(unsigned Reg);
258 bool isMemReorderDisabled(MCInst const &MCI);
259 
260 // Return whether the insn is a new-value consumer.
261 bool isNewValue(MCInstrInfo const &MCII, MCInst const &MCI);
262 /// Return true if the operand is a new-value store insn.
263 bool isNewValueStore(MCInstrInfo const &MCII, MCInst const &MCI);
264 bool isOpExtendable(MCInstrInfo const &MCII, MCInst const &MCI, unsigned short);
265 
266 // Can these two instructions be duplexed
267 bool isOrderedDuplexPair(MCInstrInfo const &MCII, MCInst const &MIa,
268  bool ExtendedA, MCInst const &MIb, bool ExtendedB,
269  bool bisReversable, MCSubtargetInfo const &STI);
270 
271 // Returns whether this bundle is an endloop1
272 bool isOuterLoop(MCInst const &MCI);
273 
274 // Return whether this instruction is predicated
275 bool isPredicated(MCInstrInfo const &MCII, MCInst const &MCI);
276 bool isPredicateLate(MCInstrInfo const &MCII, MCInst const &MCI);
277 bool isPredicatedNew(MCInstrInfo const &MCII, MCInst const &MCI);
278 
279 // Return whether the predicate sense is true
280 bool isPredicatedTrue(MCInstrInfo const &MCII, MCInst const &MCI);
281 
282 // Return true if this is a scalar predicate register.
283 bool isPredReg(MCRegisterInfo const &MRI, unsigned Reg);
284 
285 // Returns true if the Ith operand is a predicate register.
286 bool isPredRegister(MCInstrInfo const &MCII, MCInst const &Inst, unsigned I);
287 
288 // Return whether the insn is a prefix.
289 bool isPrefix(MCInstrInfo const &MCII, MCInst const &MCI);
290 
291 // Return whether the insn is solo, i.e., cannot be in a packet.
292 bool isSolo(MCInstrInfo const &MCII, MCInst const &MCI);
293 
294 /// Return whether the insn can be packaged only with A and X-type insns.
295 bool isSoloAX(MCInstrInfo const &MCII, MCInst const &MCI);
296 
297 /// Return whether the insn can be packaged only with an A-type insn in slot #1.
298 bool isRestrictSlot1AOK(MCInstrInfo const &MCII, MCInst const &MCI);
299 bool isRestrictNoSlot1Store(MCInstrInfo const &MCII, MCInst const &MCI);
300 bool isSubInstruction(MCInst const &MCI);
301 bool isVector(MCInstrInfo const &MCII, MCInst const &MCI);
302 bool mustExtend(MCExpr const &Expr);
303 bool mustNotExtend(MCExpr const &Expr);
304 
305 // Returns true if this instruction requires a slot to execute.
306 bool requiresSlot(MCSubtargetInfo const &STI, MCInst const &MCI);
307 
308 unsigned packetSize(StringRef CPU);
309 
310 // Returns the maximum number of slots available in the given
311 // subtarget's packets.
312 unsigned packetSizeSlots(MCSubtargetInfo const &STI);
313 
314 // Returns the number of slots consumed by this packet, considering duplexed
315 // and compound instructions.
316 unsigned slotsConsumed(MCInstrInfo const &MCII, MCSubtargetInfo const &STI,
317  MCInst const &MCI);
318 
319 
320 // Pad the bundle with nops to satisfy endloop requirements
321 void padEndloop(MCInst &MCI, MCContext &Context);
323 public:
325  PredicateInfo(unsigned Register, unsigned Operand, bool PredicatedTrue)
327  bool isPredicated() const;
328  unsigned Register;
329  unsigned Operand;
331 };
332 PredicateInfo predicateInfo(MCInstrInfo const &MCII, MCInst const &MCI);
333 bool prefersSlot3(MCInstrInfo const &MCII, MCInst const &MCI);
334 
335 // Replace the instructions inside MCB, represented by Candidate
336 void replaceDuplex(MCContext &Context, MCInst &MCI, DuplexCandidate Candidate);
337 
338 bool s27_2_reloc(MCExpr const &Expr);
339 // Marks a bundle as endloop0
340 void setInnerLoop(MCInst &MCI);
341 void setMemReorderDisabled(MCInst &MCI);
342 void setMustExtend(MCExpr const &Expr, bool Val = true);
343 void setMustNotExtend(MCExpr const &Expr, bool Val = true);
344 void setS27_2_reloc(MCExpr const &Expr, bool Val = true);
345 
346 // Marks a bundle as endloop1
347 void setOuterLoop(MCInst &MCI);
348 
349 // Would duplexing this instruction create a requirement to extend
350 bool subInstWouldBeExtended(MCInst const &potentialDuplex);
351 unsigned SubregisterBit(unsigned Consumer, unsigned Producer,
352  unsigned Producer2);
353 
354 bool IsVecRegSingle(unsigned VecReg);
355 bool IsVecRegPair(unsigned VecReg);
356 bool IsReverseVecRegPair(unsigned VecReg);
357 bool IsSingleConsumerRefPairProducer(unsigned Producer, unsigned Consumer);
358 
359 /// Returns an ordered pair of the constituent register ordinals for
360 /// each of the elements of \a VecRegPair. For example, Hexagon::W0 ("v0:1")
361 /// returns { 0, 1 } and Hexagon::W1 ("v3:2") returns { 3, 2 }.
362 std::pair<unsigned, unsigned> GetVecRegPairIndices(unsigned VecRegPair);
363 
364 // Attempt to find and replace compound pairs
365 void tryCompound(MCInstrInfo const &MCII, MCSubtargetInfo const &STI,
366  MCContext &Context, MCInst &MCI);
367 
368 } // end namespace HexagonMCInstrInfo
369 
370 } // end namespace llvm
371 
372 #endif // LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCINSTRINFO_H
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Definition: README.txt:29
llvm::HexagonMCInstrInfo::mustNotExtend
bool mustNotExtend(MCExpr const &Expr)
Definition: HexagonMCInstrInfo.cpp:886
llvm::HexagonMCInstrInfo::setMustExtend
void setMustExtend(MCExpr const &Expr, bool Val=true)
Definition: HexagonMCInstrInfo.cpp:873
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:105
MathExtras.h
llvm
This file implements support for optimizing divisions by a constant.
Definition: AllocatorList.h:23
llvm::HexagonMCInstrInfo::getDesc
const MCInstrDesc & getDesc(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:248
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::DuplexCandidate
Definition: HexagonMCInstrInfo.h:34
llvm::HexagonMCInstrInfo::minConstant
int64_t minConstant(MCInst const &MCI, size_t Index)
Definition: HexagonMCInstrInfo.cpp:859
llvm::HexagonMCInstrInfo::isAccumulator
bool isAccumulator(MCInstrInfo const &MCII, MCInst const &MCI)
Return where the instruction is an accumulator.
Definition: HexagonMCInstrInfo.cpp:526
llvm::HexagonMCInstrInfo::setMustNotExtend
void setMustNotExtend(MCExpr const &Expr, bool Val=true)
Definition: HexagonMCInstrInfo.cpp:882
llvm::MCInst::const_iterator
SmallVectorImpl< MCOperand >::const_iterator const_iterator
Definition: MCInst.h:213
llvm::HexagonMCInstrInfo::isPredReg
bool isPredReg(MCRegisterInfo const &MRI, unsigned Reg)
Definition: HexagonMCInstrInfo.cpp:748
llvm::HexagonMCInstrInfo::isRestrictSlot1AOK
bool isRestrictSlot1AOK(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn can be packaged only with an A-type insn in slot #1.
Definition: HexagonMCInstrInfo.cpp:768
llvm::HexagonMCInstrInfo::getDuplexRegisterNumbering
unsigned getDuplexRegisterNumbering(unsigned Reg)
Definition: HexagonMCInstrInfo.cpp:253
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:72
llvm::HexagonMCInstrInfo::subInstWouldBeExtended
bool subInstWouldBeExtended(MCInst const &potentialDuplex)
Definition: HexagonMCDuplexInfo.cpp:539
llvm::HexagonMCInstrInfo::outerLoopMask
const int64_t outerLoopMask
Definition: HexagonMCInstrInfo.h:71
llvm::HexagonMCInstrInfo::innerLoopMask
const int64_t innerLoopMask
Definition: HexagonMCInstrInfo.h:68
StringRef.h
llvm::HexagonMCInstrInfo::isCofMax1
bool isCofMax1(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:577
llvm::HexagonMCInstrInfo::hasDuplex
bool hasDuplex(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:477
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1168
llvm::HexagonMCInstrInfo::isCofRelax2
bool isCofRelax2(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:588
llvm::HexagonMCInstrInfo::getCVIResources
unsigned getCVIResources(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst const &MCI)
Return the resources used by this instruction.
Definition: HexagonMCInstrInfo.cpp:423
llvm::HexagonMCInstrInfo::isDuplexPair
bool isDuplexPair(MCInst const &MIa, MCInst const &MIb)
Symmetrical. See if these two instructions are fit for duplex pair.
Definition: HexagonMCDuplexInfo.cpp:655
llvm::Hexagon::PacketIterator::operator*
const MCInst & operator*() const
Definition: HexagonMCInstrInfo.cpp:71
llvm::HexagonMCInstrInfo::getNewValueOp
unsigned short getNewValueOp(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:372
llvm::HexagonMCInstrInfo::inSRange
bool inSRange(MCInst const &MCI, size_t Index)
Definition: HexagonMCInstrInfo.h:199
llvm::HexagonMCInstrInfo::hasTmpDst
bool hasTmpDst(MCInstrInfo const &MCII, MCInst const &MCI)
return true if instruction has hasTmpDst attribute.
Definition: HexagonMCInstrInfo.cpp:943
llvm::HexagonMCInstrInfo::getMemAccessSize
unsigned getMemAccessSize(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:234
llvm::HexagonMCInstrInfo::getExtentAlignment
unsigned getExtentAlignment(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:327
llvm::HexagonMCInstrInfo::addConstExtender
void addConstExtender(MCContext &Context, MCInstrInfo const &MCII, MCInst &MCB, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:87
llvm::HexagonMCInstrInfo::PredicateInfo::PredicateInfo
PredicateInfo(unsigned Register, unsigned Operand, bool PredicatedTrue)
Definition: HexagonMCInstrInfo.h:325
llvm::HexagonMCInstrInfo::hasExtenderForIndex
bool hasExtenderForIndex(MCInst const &MCB, size_t Index)
Definition: HexagonMCInstrInfo.cpp:489
llvm::HexagonMCInstrInfo::PredicateInfo::isPredicated
bool isPredicated() const
Definition: HexagonMCInstrInfo.cpp:35
llvm::HexagonMCInstrInfo::isImmext
bool isImmext(MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:635
llvm::HexagonMCInstrInfo::extendIfNeeded
void extendIfNeeded(MCContext &Context, MCInstrInfo const &MCII, MCInst &MCB, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:227
llvm::HexagonMCInstrInfo::isSubInstruction
bool isSubInstruction(MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:794
llvm::HexagonMCInstrInfo::extenderForIndex
const MCInst * extenderForIndex(MCInst const &MCB, size_t Index)
Definition: HexagonMCInstrInfo.cpp:215
llvm::HexagonMCInstrInfo::setInnerLoop
void setInnerLoop(MCInst &MCI)
Definition: HexagonMCInstrInfo.cpp:989
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
llvm::HexagonMCInstrInfo::replaceDuplex
void replaceDuplex(MCContext &Context, MCInst &MCI, DuplexCandidate Candidate)
Definition: HexagonMCInstrInfo.cpp:975
llvm::HexagonMCInstrInfo::prefersSlot3
bool prefersSlot3(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:936
llvm::HexagonMCInstrInfo::isCofRelax1
bool isCofRelax1(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:582
llvm::HexagonMCInstrInfo::bundleInstructionsOffset
const size_t bundleInstructionsOffset
Definition: HexagonMCInstrInfo.h:78
llvm::HexagonMCInstrInfo::getOtherReservedSlots
unsigned getOtherReservedSlots(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst const &MCI)
Return the slots this instruction consumes in addition to the slot(s) it can execute out of.
Definition: HexagonMCInstrInfo.cpp:454
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
llvm::HexagonMCInstrInfo::PredicateInfo::PredicatedTrue
bool PredicatedTrue
Definition: HexagonMCInstrInfo.h:330
llvm::HexagonMCInstrInfo::isMemReorderDisabled
bool isMemReorderDisabled(MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:788
llvm::HexagonMCInstrInfo::isDblRegForSubInst
bool isDblRegForSubInst(unsigned Reg)
Definition: HexagonMCInstrInfo.cpp:604
llvm::HexagonMCInstrInfo::setS27_2_reloc
void setS27_2_reloc(MCExpr const &Expr, bool Val=true)
Definition: HexagonMCInstrInfo.cpp:890
llvm::HexagonMCInstrInfo::PredicateInfo
Definition: HexagonMCInstrInfo.h:322
llvm::HexagonMCInstrInfo::isDuplexPairMatch
bool isDuplexPairMatch(unsigned Ga, unsigned Gb)
Definition: HexagonMCDuplexInfo.cpp:89
llvm::HexagonMCInstrInfo::isPredicatedTrue
bool isPredicatedTrue(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:741
llvm::HexagonMCInstrInfo::s27_2_reloc
bool s27_2_reloc(MCExpr const &Expr)
Definition: HexagonMCInstrInfo.cpp:895
llvm::HexagonMCInstrInfo::hasImmExt
bool hasImmExt(MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:493
llvm::HexagonMCInstrInfo::requiresSlot
bool requiresSlot(MCSubtargetInfo const &STI, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:948
llvm::HexagonMCInstrInfo::setMemReorderDisabled
void setMemReorderDisabled(MCInst &MCI)
Definition: HexagonMCInstrInfo.cpp:995
llvm::HexagonMCInstrInfo::hasNewValue2
bool hasNewValue2(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn produces a second value.
Definition: HexagonMCInstrInfo.cpp:513
llvm::HexagonMCInstrInfo::isNewValue
bool isNewValue(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn expects newly produced value.
Definition: HexagonMCInstrInfo.cpp:655
llvm::HexagonMCInstrInfo::isPredicated
bool isPredicated(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:718
llvm::HexagonMCInstrInfo::isVector
bool isVector(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:854
llvm::HexagonMCInstrInfo::isBundle
bool isBundle(MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:532
llvm::HexagonMCInstrInfo::predicateInfo
PredicateInfo predicateInfo(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:926
MCInst.h
false
Definition: StackSlotColoring.cpp:142
llvm::HexagonMCInstrInfo::getName
StringRef getName(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:367
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:195
llvm::HexagonMCInstrInfo::isCanon
bool isCanon(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:572
llvm::HexagonMCInstrInfo::bundleInstructions
iterator_range< Hexagon::PacketIterator > bundleInstructions(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:103
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Definition: HexagonMCInstrInfo.cpp:77
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Definition: HexagonMCInstrInfo.cpp:649
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Definition: HexagonMCInstrInfo.h:67
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Definition: HexagonMCDuplexInfo.cpp:576
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Definition: HexagonMCInstrInfo.h:36
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Definition: HexagonMCInstrInfo.cpp:679
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Definition: HexagonMCInstrInfo.cpp:625
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Definition: HexagonMCInstrInfo.h:195
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Definition: HexagonMCInstrInfo.cpp:397
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Definition: HexagonMCInstrInfo.cpp:673
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Definition: HexagonMCInstrInfo.cpp:339
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Definition: HexagonMCInstrInfo.h:328
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Definition: StringRef.h:58
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Definition: HexagonMCInstrInfo.cpp:378
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Definition: MCRegisterInfo.h:135
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Definition: HexagonMCInstrInfo.cpp:309
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Definition: HexagonMCInstrInfo.cpp:1002
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Definition: HexagonMCInstrInfo.cpp:241
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Definition: AArch64AdvSIMDScalarPass.cpp:105
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Definition: Register.h:19
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Definition: HexagonMCInstrInfo.cpp:404
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Definition: HexagonMCInstrInfo.h:324
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Definition: HexagonMCInstrInfo.h:76
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Definition: MCInstrInfo.h:25
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Definition: HexagonMCInstrInfo.h:36
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Definition: HexagonMCChecker.h:34
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Definition: HexagonMCInstrInfo.cpp:416
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Definition: HexagonMCInstrInfo.cpp:201
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Definition: HexagonMCDuplexInfo.cpp:189
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Definition: HexagonMCInstrInfo.cpp:316
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Definition: HexagonMCInstrInfo.cpp:443
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Definition: HexagonMCInstrInfo.cpp:705
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Definition: HexagonMCInstrInfo.cpp:902
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Definition: HexagonMCInstrInfo.h:70
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Definition: HexagonMCInstrInfo.cpp:519
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Definition: HexagonMCInstrInfo.cpp:661
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Definition: HexagonMCInstrInfo.cpp:630
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Definition: HexagonMCInstrInfo.cpp:346
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Definition: HexagonMCInstrInfo.cpp:914
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Definition: HexagonMCInstrInfo.cpp:303
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Definition: iterator_range.h:30
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Definition: HexagonMCInstrInfo.cpp:357
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Definition: MCInst.h:36
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Definition: HexagonMCInstrInfo.cpp:619
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Definition: HexagonMCDuplexInfo.cpp:114
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Definition: HexagonMCInstrInfo.cpp:783
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Definition: HexagonMCInstrInfo.cpp:753
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Definition: HexagonMCInstrInfo.cpp:693
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Definition: HexagonMCInstrInfo.cpp:39
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Definition: HexagonMCInstrInfo.cpp:959
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Definition: HexagonMCInstrInfo.cpp:728
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Definition: MCSubtargetInfo.h:75
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LLVM Value Representation.
Definition: Value.h:74
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Definition: MCExpr.h:35
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Definition: HexagonMCInstrInfo.h:329
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Definition: ELFYAML.cpp:1184
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Definition: HexagonMCInstrInfo.cpp:735
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Definition: HexagonMCInstrInfo.h:38
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Definition: HexagonMCInstrInfo.cpp:613
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Definition: HexagonMCInstrInfo.cpp:639