LLVM 23.0.0git
LiveRegMatrix.h
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1//===- LiveRegMatrix.h - Track register interference ----------*- C++ -*---===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// The LiveRegMatrix analysis pass keeps track of virtual register interference
10// along two dimensions: Slot indexes and register units. The matrix is used by
11// register allocators to ensure that no interfering virtual registers get
12// assigned to overlapping physical registers.
13//
14// Register units are defined in MCRegisterInfo.h, they represent the smallest
15// unit of interference when dealing with overlapping physical registers. The
16// LiveRegMatrix is represented as a LiveIntervalUnion per register unit. When
17// a virtual register is assigned to a physical register, the live range for
18// the virtual register is inserted into the LiveIntervalUnion for each regunit
19// in the physreg.
20//
21//===----------------------------------------------------------------------===//
22
23#ifndef LLVM_CODEGEN_LIVEREGMATRIX_H
24#define LLVM_CODEGEN_LIVEREGMATRIX_H
25
26#include "llvm/ADT/BitVector.h"
29#include <memory>
30
31namespace llvm {
32
33class AnalysisUsage;
34class LiveInterval;
35class LiveIntervals;
36class MachineFunction;
38class VirtRegMap;
39
40class LiveRegMatrix {
43 const TargetRegisterInfo *TRI = nullptr;
44 LiveIntervals *LIS = nullptr;
45 VirtRegMap *VRM = nullptr;
46
47 // UserTag changes whenever virtual registers have been modified.
48 unsigned UserTag = 0;
49
50 // The matrix is represented as a LiveIntervalUnion per register unit.
51 std::unique_ptr<LiveIntervalUnion::Allocator> LIUAlloc;
53
54 // Cached queries per register unit.
55 std::unique_ptr<LiveIntervalUnion::Query[]> Queries;
56
57 // Cached register mask interference info.
58 unsigned RegMaskTag = 0;
59 Register RegMaskVirtReg;
60 BitVector RegMaskUsable;
61
62 LiveRegMatrix()
63 : LIUAlloc(std::make_unique<LiveIntervalUnion::Allocator>()) {};
64 void releaseMemory();
65
66public:
67 LiveRegMatrix(LiveRegMatrix &&Other) = default;
68
70
71 //===--------------------------------------------------------------------===//
72 // High-level interface.
73 //===--------------------------------------------------------------------===//
74 //
75 // Check for interference before assigning virtual registers to physical
76 // registers.
77 //
78
79 /// Invalidate cached interference queries after modifying virtual register
80 /// live ranges. Interference checks may return stale information unless
81 /// caches are invalidated.
82 void invalidateVirtRegs() { ++UserTag; }
83
85 /// No interference, go ahead and assign.
87
88 /// Virtual register interference. There are interfering virtual registers
89 /// assigned to PhysReg or its aliases. This interference could be resolved
90 /// by unassigning those other virtual registers.
92
93 /// Register unit interference. A fixed live range is in the way, typically
94 /// argument registers for a call. This can't be resolved by unassigning
95 /// other virtual registers.
97
98 /// RegMask interference. The live range is crossing an instruction with a
99 /// regmask operand that doesn't preserve PhysReg. This typically means
100 /// VirtReg is live across a call, and PhysReg isn't call-preserved.
102 };
103
104 /// Check for interference before assigning VirtReg to PhysReg.
105 /// If this function returns IK_Free, it is legal to assign(VirtReg, PhysReg).
106 /// When there is more than one kind of interference, the InterferenceKind
107 /// with the highest enum value is returned.
109 MCRegister PhysReg);
110
111 /// Check for interference in the segment [Start, End) that may prevent
112 /// assignment to PhysReg. If this function returns true, there is
113 /// interference in the segment [Start, End) of some other interval already
114 /// assigned to PhysReg. If this function returns false, PhysReg is free at
115 /// the segment [Start, End).
117 MCRegister PhysReg);
118
119 /// Check for interference in the segment [Start, End) that may prevent
120 /// assignment to PhysReg, like checkInterference. Returns a lane mask of
121 /// which lanes of the physical register interfere in the segment [Start, End)
122 /// of some other interval already assigned to PhysReg.
123 ///
124 /// If this function returns LaneBitmask::getNone(), PhysReg is completely
125 /// free at the segment [Start, End).
127 MCRegister PhysReg);
128
129 /// Assign VirtReg to PhysReg.
130 /// This will mark VirtReg's live range as occupied in the LiveRegMatrix and
131 /// update VirtRegMap. The live range is expected to be available in PhysReg.
132 LLVM_ABI void assign(const LiveInterval &VirtReg, MCRegister PhysReg);
133
134 /// Unassign VirtReg from its PhysReg.
135 /// Assuming that VirtReg was previously assigned to a PhysReg, this undoes
136 /// the assignment and updates VirtRegMap accordingly.
137 /// ClearAllReferencingSegments changes the way segments are removed from
138 /// the matrix:
139 /// - If false (default), only segments that exactly match VirtReg's live
140 /// range are removed.
141 /// - If true, all segments that reference VirtReg are removed. This is
142 /// useful when VirtReg's live range(s) is already empty.
143 LLVM_ABI void unassign(const LiveInterval &VirtReg,
144 bool ClearAllReferencingSegments = false);
145
146 /// Returns true if the given \p PhysReg has any live intervals assigned.
147 LLVM_ABI bool isPhysRegUsed(MCRegister PhysReg) const;
148
149 //===--------------------------------------------------------------------===//
150 // Low-level interface.
151 //===--------------------------------------------------------------------===//
152 //
153 // Provide access to the underlying LiveIntervalUnions.
154 //
155
156 /// Check for regmask interference only.
157 /// Return true if VirtReg crosses a regmask operand that clobbers PhysReg.
158 /// If PhysReg is null, check if VirtReg crosses any regmask operands.
159 LLVM_ABI bool
162
163 /// Check for regunit interference only.
164 /// Return true if VirtReg overlaps a fixed assignment of one of PhysRegs's
165 /// register units.
167 MCRegister PhysReg);
168
169 /// Query a line of the assigned virtual register matrix directly.
170 /// Use MCRegUnitIterator to enumerate all regunits in the desired PhysReg.
171 /// This returns a reference to an internal Query data structure that is only
172 /// valid until the next query() call.
174 MCRegUnit RegUnit);
175
176 /// Directly access the live interval unions per regunit.
177 /// This returns an array indexed by the regunit number.
179 return &Matrix[static_cast<MCRegUnit>(0)];
180 }
181
182 LLVM_ABI Register getOneVReg(unsigned PhysReg) const;
183
184#ifndef NDEBUG
185 /// This checks that each LiveInterval referenced in LiveIntervalUnion
186 /// actually exists in LiveIntervals and is not a dangling pointer.
187 bool isValid() const;
188#endif
189};
190
192 LiveRegMatrix LRM;
193
194public:
195 static char ID;
196
198
199 LiveRegMatrix &getLRM() { return LRM; }
200 const LiveRegMatrix &getLRM() const { return LRM; }
201
202 void getAnalysisUsage(AnalysisUsage &AU) const override;
203 bool runOnMachineFunction(MachineFunction &MF) override;
204 void releaseMemory() override;
205};
206
207class LiveRegMatrixAnalysis : public AnalysisInfoMixin<LiveRegMatrixAnalysis> {
209 static AnalysisKey Key;
210
211public:
213
216};
217
218} // end namespace llvm
219
220#endif // LLVM_CODEGEN_LIVEREGMATRIX_H
This file implements the BitVector class.
#define LLVM_ABI
Definition Compiler.h:213
Basic Register Allocator
Represent the analysis usage information of a pass.
Query interferences between a single live virtual register and a live interval union.
Union of live intervals that are strong candidates for coalescing into a single register (either phys...
LiveInterval - This class represents the liveness of a register, or stack slot.
This class represents the liveness of a register, stack slot, etc.
LLVM_ABI LiveRegMatrix run(MachineFunction &MF, MachineFunctionAnalysisManager &MFAM)
const LiveRegMatrix & getLRM() const
LLVM_ABI bool checkRegMaskInterference(const LiveInterval &VirtReg, MCRegister PhysReg=MCRegister::NoRegister)
Check for regmask interference only.
LLVM_ABI bool isPhysRegUsed(MCRegister PhysReg) const
Returns true if the given PhysReg has any live intervals assigned.
void invalidateVirtRegs()
Invalidate cached interference queries after modifying virtual register live ranges.
friend class LiveRegMatrixWrapperLegacy
LLVM_ABI Register getOneVReg(unsigned PhysReg) const
friend class LiveRegMatrixAnalysis
LLVM_ABI LiveIntervalUnion::Query & query(const LiveRange &LR, MCRegUnit RegUnit)
Query a line of the assigned virtual register matrix directly.
LLVM_ABI void unassign(const LiveInterval &VirtReg, bool ClearAllReferencingSegments=false)
Unassign VirtReg from its PhysReg.
bool isValid() const
This checks that each LiveInterval referenced in LiveIntervalUnion actually exists in LiveIntervals a...
@ IK_VirtReg
Virtual register interference.
@ IK_RegUnit
Register unit interference.
@ IK_Free
No interference, go ahead and assign.
@ IK_RegMask
RegMask interference.
LLVM_ABI void init(MachineFunction &MF, LiveIntervals &LIS, VirtRegMap &VRM)
LLVM_ABI void assign(const LiveInterval &VirtReg, MCRegister PhysReg)
Assign VirtReg to PhysReg.
LLVM_ABI InterferenceKind checkInterference(const LiveInterval &VirtReg, MCRegister PhysReg)
Check for interference before assigning VirtReg to PhysReg.
LLVM_ABI bool checkRegUnitInterference(const LiveInterval &VirtReg, MCRegister PhysReg)
Check for regunit interference only.
LiveRegMatrix(LiveRegMatrix &&Other)=default
LiveIntervalUnion * getLiveUnions()
Directly access the live interval unions per regunit.
LLVM_ABI LaneBitmask checkInterferenceLanes(SlotIndex Start, SlotIndex End, MCRegister PhysReg)
Check for interference in the segment [Start, End) that may prevent assignment to PhysReg,...
Wrapper class representing physical registers. Should be passed by value.
Definition MCRegister.h:41
static constexpr unsigned NoRegister
Definition MCRegister.h:60
Wrapper class representing virtual and physical registers.
Definition Register.h:20
SlotIndex - An opaque wrapper around machine indexes.
Definition SlotIndexes.h:66
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This is an optimization pass for GlobalISel generic memory operations.
AnalysisManager< MachineFunction > MachineFunctionAnalysisManager
@ Other
Any other memory.
Definition ModRef.h:68
Implement std::hash so that hash_code can be used in STL containers.
Definition BitVector.h:861
A CRTP mix-in that provides informational APIs needed for analysis passes.
A special type used by analysis passes to provide an address that identifies that particular analysis...
Definition Analysis.h:29