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13 #ifndef LLVM_LIB_TARGET_MSP430_MSP430INSTRINFO_H
14 #define LLVM_LIB_TARGET_MSP430_MSP430INSTRINFO_H
19 #define GET_INSTRINFO_HEADER
20 #include "MSP430GenInstrInfo.inc"
24 class MSP430Subtarget;
28 virtual void anchor();
40 bool KillSrc)
const override;
62 bool AllowModify)
const override;
65 int *BytesRemoved =
nullptr)
const override;
69 int *BytesAdded =
nullptr)
const override;
72 assert(isFrameInstr(
I) &&
"Not a frame instruction");
73 assert(
I.getOperand(1).getImm() >= 0 &&
"Size must not be negative");
74 return I.getOperand(1).getImm();
This is an optimization pass for GlobalISel generic memory operations.
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
MSP430InstrInfo(MSP430Subtarget &STI)
unsigned const TargetRegisterInfo * TRI
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
const TargetRegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
Representation of each machine instruction.
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
SmallVector< MachineOperand, 4 > Cond
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Wrapper class representing virtual and physical registers.
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
GetInstSize - Return the number of bytes of code the specified instruction may be.
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
int64_t getFramePoppedByCallee(const MachineInstr &I) const
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
Wrapper class representing physical registers. Should be passed by value.