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MSP430InstrInfo.cpp
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1 //===-- MSP430InstrInfo.cpp - MSP430 Instruction Information --------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the MSP430 implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "MSP430InstrInfo.h"
14 #include "MSP430.h"
16 #include "MSP430TargetMachine.h"
20 #include "llvm/IR/Function.h"
21 #include "llvm/MC/TargetRegistry.h"
23 
24 using namespace llvm;
25 
26 #define GET_INSTRINFO_CTOR_DTOR
27 #include "MSP430GenInstrInfo.inc"
28 
29 // Pin the vtable to this file.
30 void MSP430InstrInfo::anchor() {}
31 
33  : MSP430GenInstrInfo(MSP430::ADJCALLSTACKDOWN, MSP430::ADJCALLSTACKUP),
34  RI() {}
35 
38  Register SrcReg, bool isKill, int FrameIdx,
39  const TargetRegisterClass *RC,
40  const TargetRegisterInfo *TRI) const {
41  DebugLoc DL;
42  if (MI != MBB.end()) DL = MI->getDebugLoc();
43  MachineFunction &MF = *MBB.getParent();
44  MachineFrameInfo &MFI = MF.getFrameInfo();
45 
49  MFI.getObjectAlign(FrameIdx));
50 
51  if (RC == &MSP430::GR16RegClass)
52  BuildMI(MBB, MI, DL, get(MSP430::MOV16mr))
53  .addFrameIndex(FrameIdx).addImm(0)
54  .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
55  else if (RC == &MSP430::GR8RegClass)
56  BuildMI(MBB, MI, DL, get(MSP430::MOV8mr))
57  .addFrameIndex(FrameIdx).addImm(0)
58  .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
59  else
60  llvm_unreachable("Cannot store this register to stack slot!");
61 }
62 
65  Register DestReg, int FrameIdx,
66  const TargetRegisterClass *RC,
67  const TargetRegisterInfo *TRI) const{
68  DebugLoc DL;
69  if (MI != MBB.end()) DL = MI->getDebugLoc();
70  MachineFunction &MF = *MBB.getParent();
71  MachineFrameInfo &MFI = MF.getFrameInfo();
72 
76  MFI.getObjectAlign(FrameIdx));
77 
78  if (RC == &MSP430::GR16RegClass)
79  BuildMI(MBB, MI, DL, get(MSP430::MOV16rm))
80  .addReg(DestReg, getDefRegState(true)).addFrameIndex(FrameIdx)
81  .addImm(0).addMemOperand(MMO);
82  else if (RC == &MSP430::GR8RegClass)
83  BuildMI(MBB, MI, DL, get(MSP430::MOV8rm))
84  .addReg(DestReg, getDefRegState(true)).addFrameIndex(FrameIdx)
85  .addImm(0).addMemOperand(MMO);
86  else
87  llvm_unreachable("Cannot store this register to stack slot!");
88 }
89 
92  const DebugLoc &DL, MCRegister DestReg,
93  MCRegister SrcReg, bool KillSrc) const {
94  unsigned Opc;
95  if (MSP430::GR16RegClass.contains(DestReg, SrcReg))
96  Opc = MSP430::MOV16rr;
97  else if (MSP430::GR8RegClass.contains(DestReg, SrcReg))
98  Opc = MSP430::MOV8rr;
99  else
100  llvm_unreachable("Impossible reg-to-reg copy");
101 
102  BuildMI(MBB, I, DL, get(Opc), DestReg)
103  .addReg(SrcReg, getKillRegState(KillSrc));
104 }
105 
107  int *BytesRemoved) const {
108  assert(!BytesRemoved && "code size not handled");
109 
111  unsigned Count = 0;
112 
113  while (I != MBB.begin()) {
114  --I;
115  if (I->isDebugInstr())
116  continue;
117  if (I->getOpcode() != MSP430::JMP &&
118  I->getOpcode() != MSP430::JCC &&
119  I->getOpcode() != MSP430::Bi &&
120  I->getOpcode() != MSP430::Br &&
121  I->getOpcode() != MSP430::Bm)
122  break;
123  // Remove the branch.
124  I->eraseFromParent();
125  I = MBB.end();
126  ++Count;
127  }
128 
129  return Count;
130 }
131 
134  assert(Cond.size() == 1 && "Invalid Xbranch condition!");
135 
136  MSP430CC::CondCodes CC = static_cast<MSP430CC::CondCodes>(Cond[0].getImm());
137 
138  switch (CC) {
139  default: llvm_unreachable("Invalid branch condition!");
140  case MSP430CC::COND_E:
142  break;
143  case MSP430CC::COND_NE:
145  break;
146  case MSP430CC::COND_L:
148  break;
149  case MSP430CC::COND_GE:
151  break;
152  case MSP430CC::COND_HS:
154  break;
155  case MSP430CC::COND_LO:
157  break;
158  }
159 
160  Cond[0].setImm(CC);
161  return false;
162 }
163 
166  MachineBasicBlock *&FBB,
168  bool AllowModify) const {
169  // Start from the bottom of the block and work up, examining the
170  // terminator instructions.
172  while (I != MBB.begin()) {
173  --I;
174  if (I->isDebugInstr())
175  continue;
176 
177  // Working from the bottom, when we see a non-terminator
178  // instruction, we're done.
179  if (!isUnpredicatedTerminator(*I))
180  break;
181 
182  // A terminator that isn't a branch can't easily be handled
183  // by this analysis.
184  if (!I->isBranch())
185  return true;
186 
187  // Cannot handle indirect branches.
188  if (I->getOpcode() == MSP430::Br ||
189  I->getOpcode() == MSP430::Bm)
190  return true;
191 
192  // Handle unconditional branches.
193  if (I->getOpcode() == MSP430::JMP || I->getOpcode() == MSP430::Bi) {
194  if (!AllowModify) {
195  TBB = I->getOperand(0).getMBB();
196  continue;
197  }
198 
199  // If the block has any instructions after a JMP, delete them.
200  MBB.erase(std::next(I), MBB.end());
201  Cond.clear();
202  FBB = nullptr;
203 
204  // Delete the JMP if it's equivalent to a fall-through.
205  if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
206  TBB = nullptr;
207  I->eraseFromParent();
208  I = MBB.end();
209  continue;
210  }
211 
212  // TBB is used to indicate the unconditinal destination.
213  TBB = I->getOperand(0).getMBB();
214  continue;
215  }
216 
217  // Handle conditional branches.
218  assert(I->getOpcode() == MSP430::JCC && "Invalid conditional branch");
219  MSP430CC::CondCodes BranchCode =
220  static_cast<MSP430CC::CondCodes>(I->getOperand(1).getImm());
221  if (BranchCode == MSP430CC::COND_INVALID)
222  return true; // Can't handle weird stuff.
223 
224  // Working from the bottom, handle the first conditional branch.
225  if (Cond.empty()) {
226  FBB = TBB;
227  TBB = I->getOperand(0).getMBB();
228  Cond.push_back(MachineOperand::CreateImm(BranchCode));
229  continue;
230  }
231 
232  // Handle subsequent conditional branches. Only handle the case where all
233  // conditional branches branch to the same destination.
234  assert(Cond.size() == 1);
235  assert(TBB);
236 
237  // Only handle the case where all conditional branches branch to
238  // the same destination.
239  if (TBB != I->getOperand(0).getMBB())
240  return true;
241 
242  MSP430CC::CondCodes OldBranchCode = (MSP430CC::CondCodes)Cond[0].getImm();
243  // If the conditions are the same, we can leave them alone.
244  if (OldBranchCode == BranchCode)
245  continue;
246 
247  return true;
248  }
249 
250  return false;
251 }
252 
255  MachineBasicBlock *FBB,
257  const DebugLoc &DL,
258  int *BytesAdded) const {
259  // Shouldn't be a fall through.
260  assert(TBB && "insertBranch must not be told to insert a fallthrough");
261  assert((Cond.size() == 1 || Cond.size() == 0) &&
262  "MSP430 branch conditions have one component!");
263  assert(!BytesAdded && "code size not handled");
264 
265  if (Cond.empty()) {
266  // Unconditional branch?
267  assert(!FBB && "Unconditional branch with multiple successors!");
268  BuildMI(&MBB, DL, get(MSP430::JMP)).addMBB(TBB);
269  return 1;
270  }
271 
272  // Conditional branch.
273  unsigned Count = 0;
274  BuildMI(&MBB, DL, get(MSP430::JCC)).addMBB(TBB).addImm(Cond[0].getImm());
275  ++Count;
276 
277  if (FBB) {
278  // Two-way Conditional branch. Insert the second branch.
279  BuildMI(&MBB, DL, get(MSP430::JMP)).addMBB(FBB);
280  ++Count;
281  }
282  return Count;
283 }
284 
285 /// GetInstSize - Return the number of bytes of code the specified
286 /// instruction may be. This returns the maximum number of bytes.
287 ///
289  const MCInstrDesc &Desc = MI.getDesc();
290 
291  switch (Desc.getOpcode()) {
292  case TargetOpcode::CFI_INSTRUCTION:
294  case TargetOpcode::IMPLICIT_DEF:
295  case TargetOpcode::KILL:
296  case TargetOpcode::DBG_VALUE:
297  return 0;
300  const MachineFunction *MF = MI.getParent()->getParent();
301  const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo();
302  return TII.getInlineAsmLength(MI.getOperand(0).getSymbolName(),
303  *MF->getTarget().getMCAsmInfo());
304  }
305  }
306 
307  return Desc.getSize();
308 }
llvm::MCInstrDesc::getOpcode
unsigned getOpcode() const
Return the opcode number for this descriptor.
Definition: MCInstrDesc.h:223
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:109
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:131
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
MSP430TargetMachine.h
MSP430GenInstrInfo
llvm::TargetSubtargetInfo::getInstrInfo
virtual const TargetInstrInfo * getInstrInfo() const
Definition: TargetSubtargetInfo.h:95
contains
return AArch64::GPR64RegClass contains(Reg)
llvm::MachineFunction::getMachineMemOperand
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
Definition: MachineFunction.cpp:454
llvm::MSP430InstrInfo::removeBranch
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
Definition: MSP430InstrInfo.cpp:106
ErrorHandling.h
llvm::ISD::EH_LABEL
@ EH_LABEL
EH_LABEL - Represents a label in mid basic block used to track locations needed for debug and excepti...
Definition: ISDOpcodes.h:1033
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:237
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition: MachineMemOperand.h:127
llvm::MSP430InstrInfo::MSP430InstrInfo
MSP430InstrInfo(MSP430Subtarget &STI)
Definition: MSP430InstrInfo.cpp:32
MSP430InstrInfo.h
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
MachineRegisterInfo.h
llvm::ISD::INLINEASM
@ INLINEASM
INLINEASM - Represents an inline asm block.
Definition: ISDOpcodes.h:1025
llvm::MachineBasicBlock::erase
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
Definition: MachineBasicBlock.cpp:1314
llvm::get
decltype(auto) get(const PointerIntPair< PointerTy, IntBits, IntType, PtrTraits, Info > &Pair)
Definition: PointerIntPair.h:234
llvm::getDefRegState
unsigned getDefRegState(bool B)
Definition: MachineInstrBuilder.h:540
MSP430CC::COND_INVALID
@ COND_INVALID
Definition: MSP430.h:32
llvm::MCInstrDesc::getSize
unsigned getSize() const
Return the number of bytes in the encoding of this instruction, or zero if the encoding size cannot b...
Definition: MCInstrDesc.h:622
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:98
llvm::MachineInstrBuilder::addMBB
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:146
llvm::MachineOperand::CreateImm
static MachineOperand CreateImm(int64_t Val)
Definition: MachineOperand.h:782
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
TBB
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
Definition: RISCVRedundantCopyElimination.cpp:76
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:125
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:197
llvm::MSP430Subtarget
Definition: MSP430Subtarget.h:31
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:657
llvm::MachineInstrBuilder::addFrameIndex
const MachineInstrBuilder & addFrameIndex(int Idx) const
Definition: MachineInstrBuilder.h:152
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::MachineFrameInfo::getObjectSize
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
Definition: MachineFrameInfo.h:470
MSP430CC::CondCodes
CondCodes
Definition: MSP430.h:22
llvm::MSP430InstrInfo::analyzeBranch
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
Definition: MSP430InstrInfo.cpp:164
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::MachineFrameInfo::getObjectAlign
Align getObjectAlign(int ObjectIdx) const
Return the alignment of the specified stack object.
Definition: MachineFrameInfo.h:484
llvm::MSP430InstrInfo::storeRegToStackSlot
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Definition: MSP430InstrInfo.cpp:36
MSP430CC::COND_LO
@ COND_LO
Definition: MSP430.h:26
llvm::MSP430InstrInfo::copyPhysReg
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
Definition: MSP430InstrInfo.cpp:90
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:673
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:261
llvm::MachineInstrBuilder::addMemOperand
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
Definition: MachineInstrBuilder.h:202
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:97
llvm::MachineFunction
Definition: MachineFunction.h:257
MSP430CC::COND_L
@ COND_L
Definition: MSP430.h:28
llvm::TargetMachine::getMCAsmInfo
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
Definition: TargetMachine.h:205
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
MSP430CC::COND_NE
@ COND_NE
Definition: MSP430.h:24
Cond
SmallVector< MachineOperand, 4 > Cond
Definition: BasicBlockSections.cpp:138
llvm::HexagonInstrInfo::getInlineAsmLength
unsigned getInlineAsmLength(const char *Str, const MCAsmInfo &MAI, const TargetSubtargetInfo *STI=nullptr) const override
Measure the specified inline asm to determine an approximation of its length.
Definition: HexagonInstrInfo.cpp:1834
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
MSP430.h
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
CC
auto CC
Definition: RISCVRedundantCopyElimination.cpp:79
llvm::MachineMemOperand::MOLoad
@ MOLoad
The memory access reads data.
Definition: MachineMemOperand.h:134
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::MSP430InstrInfo::loadRegFromStackSlot
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Definition: MSP430InstrInfo.cpp:63
llvm::MachineFunction::getTarget
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Definition: MachineFunction.h:653
MachineFrameInfo.h
llvm::ISD::INLINEASM_BR
@ INLINEASM_BR
INLINEASM_BR - Branching version of inline asm. Used by asm-goto.
Definition: ISDOpcodes.h:1028
Function.h
MSP430MachineFunctionInfo.h
llvm::MachineBasicBlock::isLayoutSuccessor
bool isLayoutSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB will be emitted immediately after this block, such that if this bloc...
Definition: MachineBasicBlock.cpp:928
MSP430CC::COND_HS
@ COND_HS
Definition: MSP430.h:25
llvm::MachineMemOperand::MOStore
@ MOStore
The memory access writes data.
Definition: MachineMemOperand.h:136
llvm::getKillRegState
unsigned getKillRegState(bool B)
Definition: MachineInstrBuilder.h:546
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:106
llvm::MSP430InstrInfo::getInstSizeInBytes
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
GetInstSize - Return the number of bytes of code the specified instruction may be.
Definition: MSP430InstrInfo.cpp:288
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:357
llvm::MachinePointerInfo::getFixedStack
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
Definition: MachineOperand.cpp:1019
llvm::MachineBasicBlock::begin
iterator begin()
Definition: MachineBasicBlock.h:305
MachineInstrBuilder.h
llvm::MSP430InstrInfo::insertBranch
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
Definition: MSP430InstrInfo.cpp:253
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
MSP430CC::COND_E
@ COND_E
Definition: MSP430.h:23
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
MSP430CC::COND_GE
@ COND_GE
Definition: MSP430.h:27
llvm::MachineInstrBundleIterator< MachineInstr >
TargetRegistry.h
llvm::MachineBasicBlock::end
iterator end()
Definition: MachineBasicBlock.h:307
llvm::MSP430InstrInfo::reverseBranchCondition
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
Definition: MSP430InstrInfo.cpp:133
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24